si.h revision 34832
110015Speter/* 212496Speter * Device driver for Specialix range (SI/XIO) of serial line multiplexors. 310015Speter * 'C' definitions for Specialix serial multiplex driver. 410015Speter * 534832Speter * Copyright (C) 1990, 1992, 1998 Specialix International, 610015Speter * Copyright (C) 1993, Andy Rutter <andy@acronym.co.uk> 734832Speter * Copyright (C) 1995, Peter Wemm <peter@netplex.com.au> 810015Speter * 910015Speter * Derived from: SunOS 4.x version 1010015Speter * 1110015Speter * Redistribution and use in source and binary forms, with or without 1210015Speter * modification, are permitted provided that the following conditions 1310015Speter * are met: 1410015Speter * 1. Redistributions of source code must retain the above copyright 1510015Speter * notices, this list of conditions and the following disclaimer. 1610015Speter * 2. Redistributions in binary form must reproduce the above copyright 1710015Speter * notices, this list of conditions and the following disclaimer in the 1810015Speter * documentation and/or other materials provided with the distribution. 1910015Speter * 3. All advertising materials mentioning features or use of this software 2010015Speter * must display the following acknowledgement: 2110015Speter * This product includes software developed by Andy Rutter of 2210015Speter * Advanced Methods and Tools Ltd. based on original information 2310015Speter * from Specialix International. 2410015Speter * 4. Neither the name of Advanced Methods and Tools, nor Specialix 2510015Speter * International may be used to endorse or promote products derived from 2610015Speter * this software without specific prior written permission. 2710015Speter * 2810015Speter * THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED 2910015Speter * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 3010015Speter * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 3110015Speter * NO EVENT SHALL THE AUTHORS BE LIABLE. 3210015Speter * 3334832Speter * $Id: si.h,v 1.11 1998/03/21 06:17:14 peter Exp $ 3410015Speter */ 3510015Speter 3629676Sgibbs#include <sys/callout.h> 3729676Sgibbs 3810015Speter/* 3910015Speter * Macro to turn a device number into various parameters, and test for 4010015Speter * CONTROL device. 4110015Speter * max of 4 controllers with up to 32 ports per controller. 4210015Speter * minor device allocation is: 4310015Speter * adapter port 4410015Speter * 0 0-31 4510015Speter * 1 32-63 4610015Speter * 2 64-95 4710015Speter * 3 96-127 4810015Speter */ 4910015Speter#define SI_MAXPORTPERCARD 32 5010015Speter#define SI_MAXCONTROLLER 4 5110015Speter 5210015Speter 5310015Speter/* 5410015Speter * breakup of minor device number: 5510015Speter * lowest 5 bits: port number on card 0x1f 5610015Speter * next 2 bits: card number 0x60 5710015Speter * top bit: callout 0x80 5810015Speter * next 8 bits is the major number 5910015Speter * next 2 bits select initial/lock states 6010015Speter * next 1 bit selects the master control device 6110015Speter */ 6210015Speter 6310015Speter#define SI_PORT_MASK 0x1f 6410015Speter#define SI_CARD_MASK 0x60 6510015Speter#define SI_TTY_MASK 0x7f 6610015Speter#define SI_CALLOUT_MASK 0x80 6710015Speter#define SI_INIT_STATE_MASK 0x10000 6810015Speter#define SI_LOCK_STATE_MASK 0x20000 6910015Speter#define SI_STATE_MASK 0x30000 7010015Speter#define SI_CONTROLDEV_MASK 0x40000 7110015Speter#define SI_SPECIAL_MASK 0x70000 7210015Speter 7334736Speter#define SI_CARDSHIFT 5 7410015Speter#define SI_PORT(m) (m & SI_PORT_MASK) 7534736Speter#define SI_CARD(m) ((m & SI_CARD_MASK) >> SI_CARDSHIFT) 7610015Speter#define SI_TTY(m) (m & SI_TTY_MASK) 7710015Speter 7810015Speter#define IS_CALLOUT(m) (m & SI_CALLOUT_MASK) 7910015Speter#define IS_STATE(m) (m & SI_STATE_MASK) 8010015Speter#define IS_CONTROLDEV(m) (m & SI_CONTROLDEV_MASK) 8110015Speter#define IS_SPECIAL(m) (m & SI_SPECIAL_MASK) 8210015Speter 8310015Speter#define MINOR2SC(m) (&si_softc[SI_CARD(m)]) 8410015Speter#define MINOR2PP(m) (MINOR2SC((m))->sc_ports + SI_PORT((m))) 8510015Speter#define MINOR2TP(m) (MINOR2PP((m))->sp_tty) 8610015Speter#define TP2PP(tp) (MINOR2PP(SI_TTY(minor((tp)->t_dev)))) 8710015Speter 8810015Speter/* Adapter types */ 8910015Speter#define SIEMPTY 0 9010015Speter#define SIHOST 1 9134832Speter#define SIMCA 2 9210015Speter#define SIHOST2 3 9310015Speter#define SIEISA 4 9433395Speter#define SIPCI 5 9533395Speter#define SIJETPCI 6 9633395Speter#define SIJETISA 7 9710015Speter 9833395Speter 9910015Speter/* Buffer parameters */ 10012496Speter#define SI_BUFFERSIZE 256 10110015Speter 10210015Spetertypedef unsigned char BYTE; /* Type cast for unsigned 8 bit */ 10310015Spetertypedef unsigned short WORD; /* Type cast for unsigned 16 bit */ 10410015Speter 10510015Speter 10610015Speter/* 10710015Speter * Hardware `registers', stored in the shared memory. 10810015Speter * These are related to the firmware running on the Z280. 10910015Speter */ 11010015Speter 11110015Speterstruct si_reg { 11210015Speter BYTE initstat; 11310015Speter BYTE memsize; 11410015Speter WORD int_count; 11510015Speter WORD revision; 11634832Speter BYTE rx_int_count; /* isr_count on Jet */ 11734832Speter BYTE main_count; /* spare on Z-280 */ 11810015Speter WORD int_pending; 11910015Speter WORD int_counter; 12010015Speter BYTE int_scounter; 12110015Speter BYTE res[0x80 - 13]; 12210015Speter}; 12310015Speter 12410015Speter/* 12510015Speter * Per module control structure, stored in shared memory. 12610015Speter */ 12710015Speterstruct si_module { 12810015Speter WORD sm_next; /* Next module */ 12910015Speter BYTE sm_type; /* Number of channels */ 13010015Speter BYTE sm_number; /* Module number on cable */ 13110015Speter BYTE sm_dsr; /* Private dsr copy */ 13210015Speter BYTE sm_res[0x80 - 5]; /* Reserve space to 128 bytes */ 13310015Speter}; 13410015Speter 13510015Speter/* 13610015Speter * The 'next' pointer & with 0x7fff + SI base addres give 13710015Speter * the address of the next module block if fitted. (else 0) 13810015Speter * Note that next points to the TX buffer so 0x60 must be 13910015Speter * subtracted to find the true base. 14010015Speter */ 14134832Speter#define TA4 0x00 14234832Speter#define TA8 0x08 14334832Speter#define TA4_ASIC 0x0A 14434832Speter#define TA8_ASIC 0x0B 14534832Speter#define MTA 0x28 14634832Speter#define SXDC 0x48 14710015Speter 14810015Speter/* 14910015Speter * Per channel(port) control structure, stored in shared memory. 15010015Speter */ 15110015Speterstruct si_channel { 15210015Speter /* 15310015Speter * Generic stuff 15410015Speter */ 15510015Speter WORD next; /* Next Channel */ 15610015Speter WORD addr_uart; /* Uart address */ 15710015Speter WORD module; /* address of module struct */ 15810015Speter BYTE type; /* Uart type */ 15910015Speter BYTE fill; 16010015Speter /* 16110015Speter * Uart type specific stuff 16210015Speter */ 16310015Speter BYTE x_status; /* XON / XOFF status */ 16410015Speter BYTE c_status; /* cooking status */ 16510015Speter BYTE hi_rxipos; /* stuff into rx buff */ 16610015Speter BYTE hi_rxopos; /* stuff out of rx buffer */ 16710015Speter BYTE hi_txopos; /* Stuff into tx ptr */ 16810015Speter BYTE hi_txipos; /* ditto out */ 16910015Speter BYTE hi_stat; /* Command register */ 17010015Speter BYTE dsr_bit; /* Magic bit for DSR */ 17110015Speter BYTE txon; /* TX XON char */ 17210015Speter BYTE txoff; /* ditto XOFF */ 17310015Speter BYTE rxon; /* RX XON char */ 17410015Speter BYTE rxoff; /* ditto XOFF */ 17510015Speter BYTE hi_mr1; /* mode 1 image */ 17610015Speter BYTE hi_mr2; /* mode 2 image */ 17710015Speter BYTE hi_csr; /* clock register */ 17810015Speter BYTE hi_op; /* Op control */ 17910015Speter BYTE hi_ip; /* Input pins */ 18010015Speter BYTE hi_state; /* status */ 18110015Speter BYTE hi_prtcl; /* Protocol */ 18210015Speter BYTE hi_txon; /* host copy tx xon stuff */ 18310015Speter BYTE hi_txoff; 18410015Speter BYTE hi_rxon; 18510015Speter BYTE hi_rxoff; 18610015Speter BYTE close_prev; /* Was channel previously closed */ 18710015Speter BYTE hi_break; /* host copy break process */ 18810015Speter BYTE break_state; /* local copy ditto */ 18910015Speter BYTE hi_mask; /* Mask for CS7 etc. */ 19010015Speter BYTE mask_z280; /* Z280's copy */ 19110015Speter BYTE res[0x60 - 36]; 19212496Speter BYTE hi_txbuf[SI_BUFFERSIZE]; 19312496Speter BYTE hi_rxbuf[SI_BUFFERSIZE]; 19410015Speter BYTE res1[0xA0]; 19510015Speter}; 19610015Speter 19710015Speter/* 19810015Speter * Register definitions 19910015Speter */ 20010015Speter 20110015Speter/* 20210015Speter * Break input control register definitions 20310015Speter */ 20410015Speter#define BR_IGN 0x01 /* Ignore any received breaks */ 20510015Speter#define BR_INT 0x02 /* Interrupt on received break */ 20610015Speter#define BR_PARMRK 0x04 /* Enable parmrk parity error processing */ 20710015Speter#define BR_PARIGN 0x08 /* Ignore chars with parity errors */ 20810015Speter 20910015Speter/* 21010015Speter * Protocol register provided by host for XON/XOFF and cooking 21110015Speter */ 21210015Speter#define SP_TANY 0x01 /* Tx XON any char */ 21310015Speter#define SP_TXEN 0x02 /* Tx XON/XOFF enabled */ 21410015Speter#define SP_CEN 0x04 /* Cooking enabled */ 21510015Speter#define SP_RXEN 0x08 /* Rx XON/XOFF enabled */ 21610015Speter#define SP_DCEN 0x20 /* DCD / DTR check */ 21710015Speter#define SP_PAEN 0x80 /* Parity checking enabled */ 21810015Speter 21910015Speter/* 22010015Speter * HOST STATUS / COMMAND REGISTER 22110015Speter */ 22210015Speter#define IDLE_OPEN 0x00 /* Default mode, TX and RX polled 22310015Speter buffer updated etc */ 22410015Speter#define LOPEN 0x02 /* Local open command (no modem ctl */ 22510015Speter#define MOPEN 0x04 /* Open and monitor modem lines (blocks 22610015Speter for DCD */ 22710015Speter#define MPEND 0x06 /* Wating for DCD */ 22810015Speter#define CONFIG 0x08 /* Channel config has changed */ 22910015Speter#define CLOSE 0x0A /* Close channel */ 23010015Speter#define SBREAK 0x0C /* Start break */ 23110015Speter#define EBREAK 0x0E /* End break */ 23210015Speter#define IDLE_CLOSE 0x10 /* Closed channel */ 23310015Speter#define IDLE_BREAK 0x12 /* In a break */ 23410015Speter#define FCLOSE 0x14 /* Force a close */ 23510015Speter#define RESUME 0x16 /* Clear a pending xoff */ 23610015Speter#define WFLUSH 0x18 /* Flush output buffer */ 23710015Speter#define RFLUSH 0x1A /* Flush input buffer */ 23810015Speter 23910015Speter/* 24010015Speter * Host status register 24110015Speter */ 24210015Speter#define ST_BREAK 0x01 /* Break received (clear with config) */ 24310015Speter 24410015Speter/* 24510015Speter * OUTPUT PORT REGISTER 24610015Speter */ 24710015Speter#define OP_CTS 0x01 /* Enable CTS */ 24810015Speter#define OP_DSR 0x02 /* Enable DSR */ 24910015Speter/* 25010015Speter * INPUT PORT REGISTER 25110015Speter */ 25210015Speter#define IP_DCD 0x04 /* DCD High */ 25310015Speter#define IP_DTR 0x20 /* DTR High */ 25410015Speter#define IP_RTS 0x02 /* RTS High */ 25510015Speter#define IP_RI 0x40 /* RI High */ 25610015Speter 25710015Speter/* 25810015Speter * Mode register and uart specific stuff 25910015Speter */ 26010015Speter/* 26110015Speter * MODE REGISTER 1 26210015Speter */ 26310015Speter#define MR1_5_BITS 0x00 26410015Speter#define MR1_6_BITS 0x01 26510015Speter#define MR1_7_BITS 0x02 26610015Speter#define MR1_8_BITS 0x03 26710015Speter/* 26810015Speter * Parity 26910015Speter */ 27010015Speter#define MR1_ODD 0x04 27110015Speter#define MR1_EVEN 0x00 27210015Speter/* 27310015Speter * Parity mode 27410015Speter */ 27510015Speter#define MR1_WITH 0x00 27610015Speter#define MR1_FORCE 0x08 27710015Speter#define MR1_NONE 0x10 27810015Speter#define MR1_SPECIAL 0x18 27910015Speter/* 28010015Speter * Error mode 28110015Speter */ 28210015Speter#define MR1_CHAR 0x00 28310015Speter#define MR1_BLOCK 0x20 28410015Speter/* 28510015Speter * Request to send line automatic control 28610015Speter */ 28710015Speter#define MR1_CTSCONT 0x80 28810015Speter 28910015Speter/* 29010015Speter * MODE REGISTER 2 29110015Speter */ 29210015Speter/* 29310015Speter * Number of stop bits 29410015Speter */ 29510015Speter#define MR2_1_STOP 0x07 29610015Speter#define MR2_2_STOP 0x0F 29710015Speter/* 29810015Speter * Clear to send automatic testing before character sent 29910015Speter */ 30010015Speter#define MR2_RTSCONT 0x10 30110015Speter/* 30210015Speter * Reset RTS automatically after sending character? 30310015Speter */ 30410015Speter#define MR2_CTSCONT 0x20 30510015Speter/* 30610015Speter * Channel mode 30710015Speter */ 30810015Speter#define MR2_NORMAL 0x00 30910015Speter#define MR2_AUTO 0x40 31010015Speter#define MR2_LOCAL 0x80 31110015Speter#define MR2_REMOTE 0xC0 31210015Speter 31310015Speter/* 31410015Speter * CLOCK SELECT REGISTER - this and the code assumes ispeed == ospeed 31510015Speter */ 31610015Speter/* 31710015Speter * Clocking rates are in lower and upper nibbles.. R = upper, T = lower 31810015Speter */ 31910015Speter#define CLK75 0x0 32010015Speter#define CLK110 0x1 /* 110 on XIO!! */ 32110015Speter#define CLK38400 0x2 /* out of sequence */ 32210015Speter#define CLK150 0x3 32310015Speter#define CLK300 0x4 32410015Speter#define CLK600 0x5 32510015Speter#define CLK1200 0x6 32610015Speter#define CLK2000 0x7 32710015Speter#define CLK2400 0x8 32810015Speter#define CLK4800 0x9 32910015Speter#define CLK7200 0xa /* unchecked */ 33010015Speter#define CLK9600 0xb 33110015Speter#define CLK19200 0xc 33210015Speter#define CLK57600 0xd 33310015Speter 33410015Speter/* 33510044Speter * Per-port (channel) soft information structure, stored in the driver. 33610015Speter * This is visible via ioctl()'s. 33710015Speter */ 33810015Speterstruct si_port { 33910015Speter volatile struct si_channel *sp_ccb; 34010015Speter struct tty *sp_tty; 34110015Speter int sp_pend; /* pending command */ 34210015Speter int sp_last_hi_ip; /* cached DCD */ 34310015Speter int sp_state; 34410015Speter int sp_active_out; /* callout is open */ 34510015Speter int sp_dtr_wait; /* DTR holddown in hz */ 34612174Speter int sp_delta_overflows; 34710015Speter u_int sp_wopeners; /* # procs waiting DCD */ 34810015Speter u_char sp_hotchar; /* ldisc specific ASAP char */ 34910015Speter /* Initial state. */ 35010015Speter struct termios sp_iin; 35110015Speter struct termios sp_iout; 35210015Speter /* Lock state. */ 35310015Speter struct termios sp_lin; 35410015Speter struct termios sp_lout; 35529676Sgibbs struct callout_handle lstart_ch;/* For canceling our timeout */ 35610015Speter#ifdef SI_DEBUG 35710015Speter int sp_debug; /* debug mask */ 35810015Speter#endif 35910015Speter}; 36010015Speter 36110015Speter/* sp_state */ 36210015Speter#define SS_CLOSED 0x0000 36310015Speter#define SS_OPEN 0x0001 /* Port is active */ 36410015Speter/* 0x0002 -- */ 36510015Speter/* 0x0004 -- */ 36610015Speter/* 0x0008 -- */ 36710015Speter/* 0x0010 -- */ 36810015Speter/* 0x0020 -- */ 36910015Speter/* 0x0040 -- */ 37010015Speter/* 0x0080 -- */ 37110015Speter#define SS_LSTART 0x0100 /* lstart timeout pending */ 37210015Speter#define SS_INLSTART 0x0200 /* running an lstart induced t_oproc */ 37310015Speter#define SS_CLOSING 0x0400 /* in the middle of a siclose() */ 37410015Speter/* 0x0800 -- */ 37510015Speter#define SS_WAITWRITE 0x1000 37610015Speter#define SS_BLOCKWRITE 0x2000 37710015Speter#define SS_DTR_OFF 0x4000 /* DTR held off */ 37810015Speter 37910015Speter/* 38010015Speter * Command post flags 38110015Speter */ 38210015Speter#define SI_NOWAIT 0x00 /* Don't wait for command */ 38310015Speter#define SI_WAIT 0x01 /* Wait for complete */ 38410015Speter 38510015Speter/* 38610015Speter * Extensive debugging stuff - manipulated using siconfig(8) 38710015Speter */ 38810015Speter#define DBG_ENTRY 0x00000001 38910015Speter#define DBG_DRAIN 0x00000002 39010015Speter#define DBG_OPEN 0x00000004 39110015Speter#define DBG_CLOSE 0x00000008 39210015Speter#define DBG_READ 0x00000010 39310015Speter#define DBG_WRITE 0x00000020 39410015Speter#define DBG_PARAM 0x00000040 39510015Speter#define DBG_INTR 0x00000080 39610015Speter#define DBG_IOCTL 0x00000100 39710015Speter/* 0x00000200 */ 39810015Speter#define DBG_SELECT 0x00000400 39910160Speter#define DBG_OPTIM 0x00000800 40010015Speter#define DBG_START 0x00001000 40110015Speter#define DBG_EXIT 0x00002000 40210015Speter#define DBG_FAIL 0x00004000 40310015Speter#define DBG_STOP 0x00008000 40410015Speter#define DBG_AUTOBOOT 0x00010000 40510015Speter#define DBG_MODEM 0x00020000 40610015Speter#define DBG_DOWNLOAD 0x00040000 40710015Speter#define DBG_LSTART 0x00080000 40810015Speter#define DBG_POLL 0x00100000 40910015Speter#define DBG_ALL 0xffffffff 41010015Speter 41110015Speter/* 41210015Speter * SI ioctls 41310015Speter */ 41410015Speter/* 41510015Speter * struct for use by Specialix ioctls - used by siconfig(8) 41610015Speter */ 41710015Spetertypedef struct { 41810015Speter unsigned char 41910015Speter sid_port:5, /* 0 - 31 ports per card */ 42010044Speter sid_card:2, /* 0 - 3 cards */ 42110044Speter sid_control:1; /* controlling device (all cards) */ 42210015Speter} sidev_t; 42310015Speterstruct si_tcsi { 42410015Speter sidev_t tc_dev; 42510015Speter union { 42610015Speter int x_int; 42710015Speter int x_dbglvl; 42810015Speter } tc_action; 42910015Speter#define tc_card tc_dev.sid_card 43010015Speter#define tc_port tc_dev.sid_port 43110015Speter#define tc_int tc_action.x_int 43210015Speter#define tc_dbglvl tc_action.x_dbglvl 43310015Speter}; 43410044Speter 43510044Speterstruct si_pstat { 43610044Speter sidev_t tc_dev; 43710044Speter union { 43810044Speter struct si_port x_siport; 43910044Speter struct si_channel x_ccb; 44010044Speter struct tty x_tty; 44110044Speter } tc_action; 44210044Speter#define tc_siport tc_action.x_siport 44310044Speter#define tc_ccb tc_action.x_ccb 44410044Speter#define tc_tty tc_action.x_tty 44510044Speter}; 44610044Speter 44710015Speter#define IOCTL_MIN 96 44810015Speter#define TCSIDEBUG _IOW('S', 96, struct si_tcsi) /* Toggle debug */ 44910015Speter#define TCSIRXIT _IOW('S', 97, struct si_tcsi) /* RX int throttle */ 45010015Speter#define TCSIIT _IOW('S', 98, struct si_tcsi) /* TX int throttle */ 45110044Speter /* 99 defunct */ 45210015Speter /* 100 defunct */ 45310015Speter /* 101 defunct */ 45410015Speter /* 102 defunct */ 45510015Speter /* 103 defunct */ 45610015Speter /* 104 defunct */ 45710015Speter#define TCSISTATE _IOWR('S', 105, struct si_tcsi) /* get current state of RTS 45810015Speter DCD and DTR pins */ 45912174Speter /* 106 defunct */ 46010015Speter#define TCSIPORTS _IOR('S', 107, int) /* Number of ports found */ 46110015Speter#define TCSISDBG_LEVEL _IOW('S', 108, struct si_tcsi) /* equivalent of TCSIDEBUG which sets a 46210015Speter * particular debug level (DBG_??? bit 46310015Speter * mask), default is 0xffff */ 46410015Speter#define TCSIGDBG_LEVEL _IOWR('S', 109, struct si_tcsi) 46510015Speter#define TCSIGRXIT _IOWR('S', 110, struct si_tcsi) 46610015Speter#define TCSIGIT _IOWR('S', 111, struct si_tcsi) 46710044Speter /* 112 defunct */ 46810015Speter /* 113 defunct */ 46910015Speter /* 114 defunct */ 47010015Speter /* 115 defunct */ 47110015Speter /* 116 defunct */ 47212174Speter /* 117 defunct */ 47310015Speter 47410015Speter#define TCSISDBG_ALL _IOW('S', 118, int) /* set global debug level */ 47510015Speter#define TCSIGDBG_ALL _IOR('S', 119, int) /* get global debug level */ 47610015Speter 47712174Speter /* 120 defunct */ 47810044Speter /* 121 defunct */ 47910044Speter /* 122 defunct */ 48012174Speter /* 123 defunct */ 48110015Speter#define TCSIMODULES _IOR('S', 124, int) /* Number of modules found */ 48210015Speter 48310044Speter/* Various stats and monitoring hooks per tty device */ 48410044Speter#define TCSI_PORT _IOWR('S', 125, struct si_pstat) /* get si_port */ 48510044Speter#define TCSI_CCB _IOWR('S', 126, struct si_pstat) /* get si_ccb */ 48610044Speter#define TCSI_TTY _IOWR('S', 127, struct si_pstat) /* get tty struct */ 48710015Speter 48810044Speter#define IOCTL_MAX 127 48910044Speter 49010015Speter#define IS_SI_IOCTL(cmd) ((u_int)((cmd)&0xff00) == ('S'<<8) && \ 49110015Speter (u_int)((cmd)&0xff) >= IOCTL_MIN && \ 49210015Speter (u_int)((cmd)&0xff) <= IOCTL_MAX) 49310015Speter 49410015Speter#define CONTROLDEV "/dev/si_control" 495