rp_pci.c revision 61541 
1/*
2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
3 * All rights reserved.
4 *
5 * PCI-specific part separated from:
6 * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted prodived that the follwoing conditions
10 * are met.
11 * 1. Redistributions of source code must retain the above copyright
12 *    notive, this list of conditions and the following disclainer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials prodided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 *    must display the following acknowledgement:
18 *       This product includes software developed by Comtrol Corporation.
19 * 4. The name of Comtrol Corporation may not be used to endorse or
20 *    promote products derived from this software without specific
21 *    prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED.  IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * $FreeBSD: head/sys/dev/rp/rp_pci.c 61541 2000-06-11 06:43:16Z tanimura $
36 */
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/fcntl.h>
41#include <sys/malloc.h>
42#include <sys/tty.h>
43#include <sys/proc.h>
44#include <sys/conf.h>
45#include <sys/kernel.h>
46#include <machine/resource.h>
47#include <machine/bus.h>
48#include <sys/bus.h>
49#include <sys/rman.h>
50
51#define ROCKET_C
52#include <dev/rp/rpreg.h>
53#include <dev/rp/rpvar.h>
54
55#include <pci/pcireg.h>
56#include <pci/pcivar.h>
57
58/* PCI IDs  */
59#define RP_VENDOR_ID		0x11FE
60#define RP_DEVICE_ID_32I	0x0001
61#define RP_DEVICE_ID_8I		0x0002
62#define RP_DEVICE_ID_16I	0x0003
63#define RP_DEVICE_ID_4Q		0x0004
64#define RP_DEVICE_ID_8O		0x0005
65#define RP_DEVICE_ID_8J		0x0006
66#define RP_DEVICE_ID_4J		0x0007
67#define RP_DEVICE_ID_6M		0x000C
68#define RP_DEVICE_ID_4M		0x000D
69
70/**************************************************************************
71  MUDBAC remapped for PCI
72**************************************************************************/
73
74#define _CFG_INT_PCI	0x40
75#define _PCI_INT_FUNC	0x3A
76
77#define PCI_STROB	0x2000
78#define INTR_EN_PCI	0x0010
79
80/***************************************************************************
81Function: sPCIControllerEOI
82Purpose:  Strobe the MUDBAC's End Of Interrupt bit.
83Call:	  sPCIControllerEOI(CtlP)
84	  CONTROLLER_T *CtlP; Ptr to controller structure
85*/
86#define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB)
87
88/***************************************************************************
89Function: sPCIGetControllerIntStatus
90Purpose:  Get the controller interrupt status
91Call:	  sPCIGetControllerIntStatus(CtlP)
92	  CONTROLLER_T *CtlP; Ptr to controller structure
93Return:   Byte_t: The controller interrupt status in the lower 4
94			 bits.	Bits 0 through 3 represent AIOP's 0
95			 through 3 respectively.  If a bit is set that
96			 AIOP is interrupting.	Bits 4 through 7 will
97			 always be cleared.
98*/
99#define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f)
100
101static devclass_t rp_devclass;
102
103static int rp_pciprobe(device_t dev);
104static int rp_pciattach(device_t dev);
105#if notdef
106static int rp_pcidetach(device_t dev);
107static int rp_pcishutdown(device_t dev);
108#endif /* notdef */
109static void rp_pcireleaseresource(CONTROLLER_t *ctlp);
110static int sPCIInitController( CONTROLLER_t *CtlP,
111			       int AiopNum,
112			       int IRQNum,
113			       Byte_t Frequency,
114			       int PeriodicOnly,
115			       int VendorDevice);
116static rp_aiop2rid_t rp_pci_aiop2rid;
117static rp_aiop2off_t rp_pci_aiop2off;
118static rp_ctlmask_t rp_pci_ctlmask;
119
120/*
121 * The following functions are the pci-specific part
122 * of rp driver.
123 */
124
125static int
126rp_pciprobe(device_t dev)
127{
128	char *s;
129
130	s = NULL;
131	if ((pci_get_devid(dev) & 0xffff) == RP_VENDOR_ID)
132		s = "RocketPort PCI";
133
134	if (s != NULL) {
135		device_set_desc(dev, s);
136		return (0);
137	}
138
139	return (ENXIO);
140}
141
142static int
143rp_pciattach(device_t dev)
144{
145	int	num_ports, num_aiops;
146	int	aiop;
147	CONTROLLER_t	*ctlp;
148	int	unit;
149	int	retval;
150	u_int32_t	stcmd;
151
152	ctlp = device_get_softc(dev);
153	bzero(ctlp, sizeof(*ctlp));
154	ctlp->dev = dev;
155	unit = device_get_unit(dev);
156	ctlp->aiop2rid = rp_pci_aiop2rid;
157	ctlp->aiop2off = rp_pci_aiop2off;
158	ctlp->ctlmask = rp_pci_ctlmask;
159
160	/* Wake up the device. */
161	stcmd = pci_read_config(dev, PCIR_COMMAND, 4);
162	if ((stcmd & PCIM_CMD_PORTEN) == 0) {
163		stcmd |= (PCIM_CMD_PORTEN);
164		pci_write_config(dev, PCIR_COMMAND, 4, stcmd);
165	}
166
167	/* The IO ports of AIOPs for a PCI controller are continuous. */
168	ctlp->io_num = 1;
169	ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT);
170	ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num, M_DEVBUF, M_NOWAIT);
171	if (ctlp->io_rid == NULL || ctlp->io == NULL) {
172		device_printf(dev, "rp_pciattach: Out of memory.\n");
173		retval = ENOMEM;
174		goto nogo;
175	}
176	bzero(ctlp->io_rid, sizeof(*(ctlp->io_rid)) * ctlp->io_num);
177	bzero(ctlp->io, sizeof(*(ctlp->io)) * ctlp->io_num);
178
179	ctlp->bus_ctlp = NULL;
180
181	ctlp->io_rid[0] = 0x10;
182	ctlp->io[0] = bus_alloc_resource(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0, ~0, 1, RF_ACTIVE);
183	if(ctlp->io[0] == NULL) {
184		device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n");
185		retval = ENXIO;
186		goto nogo;
187	}
188
189	num_aiops = sPCIInitController(ctlp,
190				       MAX_AIOPS_PER_BOARD, 0,
191				       FREQ_DIS, 0, (pci_get_devid(dev) >> 16) & 0xffff);
192
193	num_ports = 0;
194	for(aiop=0; aiop < num_aiops; aiop++) {
195		sResetAiopByNum(ctlp, aiop);
196		num_ports += sGetAiopNumChan(ctlp, aiop);
197	}
198
199	retval = rp_attachcommon(ctlp, num_aiops, num_ports);
200	if (retval != 0)
201		goto nogo;
202
203	return (0);
204
205nogo:
206	rp_pcireleaseresource(ctlp);
207
208	return (retval);
209}
210
211#if notdef
212static int
213rp_pcidetach(device_t dev)
214{
215	CONTROLLER_t	*ctlp;
216
217	if (device_get_state(dev) == DS_BUSY)
218		return (EBUSY);
219
220	ctlp = device_get_softc(dev);
221
222	rp_pcireleaseresource(ctlp);
223
224	return (0);
225}
226
227static int
228rp_pcishutdown(device_t dev)
229{
230	CONTROLLER_t	*ctlp;
231
232	if (device_get_state(dev) == DS_BUSY)
233		return (EBUSY);
234
235	ctlp = device_get_softc(dev);
236
237	rp_pcireleaseresource(ctlp);
238
239	return (0);
240}
241#endif /* notdef */
242
243static void
244rp_pcireleaseresource(CONTROLLER_t *ctlp)
245{
246	rp_releaseresource(ctlp);
247
248	if (ctlp->io != NULL) {
249		if (ctlp->io[0] != NULL)
250			bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]);
251		free(ctlp->io, M_DEVBUF);
252	}
253	if (ctlp->io_rid != NULL)
254		free(ctlp->io_rid, M_DEVBUF);
255}
256
257static int
258sPCIInitController( CONTROLLER_t *CtlP,
259		    int AiopNum,
260		    int IRQNum,
261		    Byte_t Frequency,
262		    int PeriodicOnly,
263		    int VendorDevice)
264{
265	int		i;
266
267	CtlP->CtlID = CTLID_0001;	/* controller release 1 */
268
269	sPCIControllerEOI(CtlP);
270
271	/* Init AIOPs */
272	CtlP->NumAiop = 0;
273	for(i=0; i < AiopNum; i++)
274	{
275		/*device_printf(CtlP->dev, "aiop %d.\n", i);*/
276		CtlP->AiopID[i] = sReadAiopID(CtlP, i);	/* read AIOP ID */
277		/*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/
278		if(CtlP->AiopID[i] == AIOPID_NULL)	/* if AIOP does not exist */
279		{
280			break;				/* done looking for AIOPs */
281		}
282
283		switch( VendorDevice ) {
284		case RP_DEVICE_ID_4Q:
285		case RP_DEVICE_ID_4J:
286		case RP_DEVICE_ID_4M:
287      			CtlP->AiopNumChan[i] = 4;
288			break;
289		case RP_DEVICE_ID_6M:
290      			CtlP->AiopNumChan[i] = 6;
291			break;
292		case RP_DEVICE_ID_8O:
293		case RP_DEVICE_ID_8J:
294		case RP_DEVICE_ID_8I:
295		case RP_DEVICE_ID_16I:
296		case RP_DEVICE_ID_32I:
297      			CtlP->AiopNumChan[i] = 8;
298			break;
299		default:
300#if notdef
301      			CtlP->AiopNumChan[i] = 8;
302#else
303      			CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);
304#endif /* notdef */
305			break;
306		}
307		/*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/
308		rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE);	/* clock prescaler */
309		/*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/
310		rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC);
311		/*device_printf(CtlP->dev, "configured clock prescaler.\n");*/
312		CtlP->NumAiop++;				/* bump count of AIOPs */
313	}
314
315	if(CtlP->NumAiop == 0)
316		return(-1);
317	else
318		return(CtlP->NumAiop);
319}
320
321/*
322 * ARGSUSED
323 * Maps (aiop, offset) to rid.
324 */
325static int
326rp_pci_aiop2rid(int aiop, int offset)
327{
328	/* Always return zero for a PCI controller. */
329	return 0;
330}
331
332/*
333 * ARGSUSED
334 * Maps (aiop, offset) to the offset of resource.
335 */
336static int
337rp_pci_aiop2off(int aiop, int offset)
338{
339	/* Each AIOP reserves 0x40 bytes. */
340	return aiop * 0x40 + offset;
341}
342
343/* Read the int status for a PCI controller. */
344unsigned char
345rp_pci_ctlmask(CONTROLLER_t *ctlp)
346{
347	return sPCIGetControllerIntStatus(ctlp);
348}
349
350static device_method_t rp_pcimethods[] = {
351	/* Device interface */
352	DEVMETHOD(device_probe,		rp_pciprobe),
353	DEVMETHOD(device_attach,	rp_pciattach),
354#if notdef
355	DEVMETHOD(device_detach,	rp_pcidetach),
356	DEVMETHOD(device_shutdown,	rp_pcishutdown),
357#endif /* notdef */
358
359	{ 0, 0 }
360};
361
362static driver_t rp_pcidriver = {
363	"rp",
364	rp_pcimethods,
365	sizeof(CONTROLLER_t),
366};
367
368/*
369 * rp can be attached to a pci bus.
370 */
371DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0);
372