rp_pci.c revision 196858 
1/*-
2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
3 * All rights reserved.
4 *
5 * PCI-specific part separated from:
6 * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted prodived that the follwoing conditions
10 * are met.
11 * 1. Redistributions of source code must retain the above copyright
12 *    notive, this list of conditions and the following disclainer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials prodided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 *    must display the following acknowledgement:
18 *       This product includes software developed by Comtrol Corporation.
19 * 4. The name of Comtrol Corporation may not be used to endorse or
20 *    promote products derived from this software without specific
21 *    prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED.  IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36#include <sys/cdefs.h>
37__FBSDID("$FreeBSD: head/sys/dev/rp/rp_pci.c 196858 2009-09-05 08:38:25Z imp $");
38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/fcntl.h>
42#include <sys/malloc.h>
43#include <sys/tty.h>
44#include <sys/conf.h>
45#include <sys/kernel.h>
46#include <sys/module.h>
47#include <machine/resource.h>
48#include <machine/bus.h>
49#include <sys/bus.h>
50#include <sys/rman.h>
51
52#define ROCKET_C
53#include <dev/rp/rpreg.h>
54#include <dev/rp/rpvar.h>
55
56#include <dev/pci/pcireg.h>
57#include <dev/pci/pcivar.h>
58
59/* PCI IDs  */
60#define RP_VENDOR_ID		0x11FE
61#define RP_DEVICE_ID_32I	0x0001
62#define RP_DEVICE_ID_8I		0x0002
63#define RP_DEVICE_ID_16I	0x0003
64#define RP_DEVICE_ID_4Q		0x0004
65#define RP_DEVICE_ID_8O		0x0005
66#define RP_DEVICE_ID_8J		0x0006
67#define RP_DEVICE_ID_4J		0x0007
68#define RP_DEVICE_ID_6M		0x000C
69#define RP_DEVICE_ID_4M		0x000D
70#define RP_DEVICE_ID_UPCI_32	0x0801
71#define RP_DEVICE_ID_UPCI_16	0x0803
72#define RP_DEVICE_ID_UPCI_8O	0x0805
73
74/**************************************************************************
75  MUDBAC remapped for PCI
76**************************************************************************/
77
78#define _CFG_INT_PCI	0x40
79#define _PCI_INT_FUNC	0x3A
80
81#define PCI_STROB	0x2000
82#define INTR_EN_PCI	0x0010
83
84/***************************************************************************
85Function: sPCIControllerEOI
86Purpose:  Strobe the MUDBAC's End Of Interrupt bit.
87Call:	  sPCIControllerEOI(CtlP)
88	  CONTROLLER_T *CtlP; Ptr to controller structure
89*/
90#define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB)
91
92/***************************************************************************
93Function: sPCIGetControllerIntStatus
94Purpose:  Get the controller interrupt status
95Call:	  sPCIGetControllerIntStatus(CtlP)
96	  CONTROLLER_T *CtlP; Ptr to controller structure
97Return:   Byte_t: The controller interrupt status in the lower 4
98			 bits.	Bits 0 through 3 represent AIOP's 0
99			 through 3 respectively.  If a bit is set that
100			 AIOP is interrupting.	Bits 4 through 7 will
101			 always be cleared.
102*/
103#define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f)
104
105static devclass_t rp_devclass;
106
107static int rp_pciprobe(device_t dev);
108static int rp_pciattach(device_t dev);
109#ifdef notdef
110static int rp_pcidetach(device_t dev);
111static int rp_pcishutdown(device_t dev);
112#endif /* notdef */
113static void rp_pcireleaseresource(CONTROLLER_t *ctlp);
114static int sPCIInitController( CONTROLLER_t *CtlP,
115			       int AiopNum,
116			       int IRQNum,
117			       Byte_t Frequency,
118			       int PeriodicOnly,
119			       int VendorDevice);
120static rp_aiop2rid_t rp_pci_aiop2rid;
121static rp_aiop2off_t rp_pci_aiop2off;
122static rp_ctlmask_t rp_pci_ctlmask;
123
124/*
125 * The following functions are the pci-specific part
126 * of rp driver.
127 */
128
129static int
130rp_pciprobe(device_t dev)
131{
132	char *s;
133
134	s = NULL;
135	if (pci_get_vendor(dev) == RP_VENDOR_ID)
136		s = "RocketPort PCI";
137
138	if (s != NULL) {
139		device_set_desc(dev, s);
140		return (BUS_PROBE_DEFAULT);
141	}
142
143	return (ENXIO);
144}
145
146static int
147rp_pciattach(device_t dev)
148{
149	int	num_ports, num_aiops;
150	int	aiop;
151	CONTROLLER_t	*ctlp;
152	int	unit;
153	int	retval;
154	u_int32_t	stcmd;
155
156	ctlp = device_get_softc(dev);
157	bzero(ctlp, sizeof(*ctlp));
158	ctlp->dev = dev;
159	unit = device_get_unit(dev);
160	ctlp->aiop2rid = rp_pci_aiop2rid;
161	ctlp->aiop2off = rp_pci_aiop2off;
162	ctlp->ctlmask = rp_pci_ctlmask;
163
164	/* Wake up the device. */
165	stcmd = pci_read_config(dev, PCIR_COMMAND, 4);
166	if ((stcmd & PCIM_CMD_PORTEN) == 0) {
167		stcmd |= (PCIM_CMD_PORTEN);
168		pci_write_config(dev, PCIR_COMMAND, 4, stcmd);
169	}
170
171	/* The IO ports of AIOPs for a PCI controller are continuous. */
172	ctlp->io_num = 1;
173	ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
174	ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
175	if (ctlp->io_rid == NULL || ctlp->io == NULL) {
176		device_printf(dev, "rp_pciattach: Out of memory.\n");
177		retval = ENOMEM;
178		goto nogo;
179	}
180
181	ctlp->bus_ctlp = NULL;
182
183	switch (pci_get_device(dev)) {
184	case RP_DEVICE_ID_UPCI_16:
185	case RP_DEVICE_ID_UPCI_32:
186	case RP_DEVICE_ID_UPCI_8O:
187		ctlp->io_rid[0] = PCIR_BAR(2);
188		break;
189	default:
190		ctlp->io_rid[0] = PCIR_BAR(0);
191		break;
192	}
193	ctlp->io[0] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
194		&ctlp->io_rid[0], RF_ACTIVE);
195	if(ctlp->io[0] == NULL) {
196		device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n");
197		retval = ENXIO;
198		goto nogo;
199	}
200
201	num_aiops = sPCIInitController(ctlp,
202				       MAX_AIOPS_PER_BOARD, 0,
203				       FREQ_DIS, 0, pci_get_device(dev));
204
205	num_ports = 0;
206	for(aiop=0; aiop < num_aiops; aiop++) {
207		sResetAiopByNum(ctlp, aiop);
208		num_ports += sGetAiopNumChan(ctlp, aiop);
209	}
210
211	retval = rp_attachcommon(ctlp, num_aiops, num_ports);
212	if (retval != 0)
213		goto nogo;
214
215	return (0);
216
217nogo:
218	rp_pcireleaseresource(ctlp);
219
220	return (retval);
221}
222
223static int
224rp_pcidetach(device_t dev)
225{
226	CONTROLLER_t	*ctlp;
227
228	ctlp = device_get_softc(dev);
229	rp_pcireleaseresource(ctlp);
230
231	return (0);
232}
233
234static int
235rp_pcishutdown(device_t dev)
236{
237	CONTROLLER_t	*ctlp;
238
239	ctlp = device_get_softc(dev);
240	rp_pcireleaseresource(ctlp);
241
242	return (0);
243}
244
245static void
246rp_pcireleaseresource(CONTROLLER_t *ctlp)
247{
248	rp_untimeout();
249	if (ctlp->io != NULL) {
250		if (ctlp->io[0] != NULL)
251			bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]);
252		free(ctlp->io, M_DEVBUF);
253		ctlp->io = NULL;
254	}
255	if (ctlp->io_rid != NULL) {
256		free(ctlp->io_rid, M_DEVBUF);
257		ctlp->io = NULL;
258	}
259	rp_releaseresource(ctlp);
260}
261
262static int
263sPCIInitController( CONTROLLER_t *CtlP,
264		    int AiopNum,
265		    int IRQNum,
266		    Byte_t Frequency,
267		    int PeriodicOnly,
268		    int VendorDevice)
269{
270	int		i;
271
272	CtlP->CtlID = CTLID_0001;	/* controller release 1 */
273
274	sPCIControllerEOI(CtlP);
275
276	/* Init AIOPs */
277	CtlP->NumAiop = 0;
278	for(i=0; i < AiopNum; i++)
279	{
280		/*device_printf(CtlP->dev, "aiop %d.\n", i);*/
281		CtlP->AiopID[i] = sReadAiopID(CtlP, i);	/* read AIOP ID */
282		/*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/
283		if(CtlP->AiopID[i] == AIOPID_NULL)	/* if AIOP does not exist */
284		{
285			break;				/* done looking for AIOPs */
286		}
287
288		switch( VendorDevice ) {
289		case RP_DEVICE_ID_4Q:
290		case RP_DEVICE_ID_4J:
291		case RP_DEVICE_ID_4M:
292      			CtlP->AiopNumChan[i] = 4;
293			break;
294		case RP_DEVICE_ID_6M:
295      			CtlP->AiopNumChan[i] = 6;
296			break;
297		case RP_DEVICE_ID_8O:
298		case RP_DEVICE_ID_8J:
299		case RP_DEVICE_ID_8I:
300		case RP_DEVICE_ID_16I:
301		case RP_DEVICE_ID_32I:
302      			CtlP->AiopNumChan[i] = 8;
303			break;
304		default:
305#ifdef notdef
306      			CtlP->AiopNumChan[i] = 8;
307#else
308      			CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);
309#endif /* notdef */
310			break;
311		}
312		/*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/
313		rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE);	/* clock prescaler */
314		/*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/
315		rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC);
316		/*device_printf(CtlP->dev, "configured clock prescaler.\n");*/
317		CtlP->NumAiop++;				/* bump count of AIOPs */
318	}
319
320	if(CtlP->NumAiop == 0)
321		return(-1);
322	else
323		return(CtlP->NumAiop);
324}
325
326/*
327 * ARGSUSED
328 * Maps (aiop, offset) to rid.
329 */
330static int
331rp_pci_aiop2rid(int aiop, int offset)
332{
333	/* Always return zero for a PCI controller. */
334	return 0;
335}
336
337/*
338 * ARGSUSED
339 * Maps (aiop, offset) to the offset of resource.
340 */
341static int
342rp_pci_aiop2off(int aiop, int offset)
343{
344	/* Each AIOP reserves 0x40 bytes. */
345	return aiop * 0x40 + offset;
346}
347
348/* Read the int status for a PCI controller. */
349static unsigned char
350rp_pci_ctlmask(CONTROLLER_t *ctlp)
351{
352	return sPCIGetControllerIntStatus(ctlp);
353}
354
355static device_method_t rp_pcimethods[] = {
356	/* Device interface */
357	DEVMETHOD(device_probe,		rp_pciprobe),
358	DEVMETHOD(device_attach,	rp_pciattach),
359	DEVMETHOD(device_detach,	rp_pcidetach),
360	DEVMETHOD(device_shutdown,	rp_pcishutdown),
361
362	{ 0, 0 }
363};
364
365static driver_t rp_pcidriver = {
366	"rp",
367	rp_pcimethods,
368	sizeof(CONTROLLER_t),
369};
370
371/*
372 * rp can be attached to a pci bus.
373 */
374DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0);
375