if_re.c revision 231728
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: stable/9/sys/dev/re/if_re.c 231728 2012-02-15 03:41:48Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/sysctl.h> 127#include <sys/taskqueue.h> 128 129#include <net/if.h> 130#include <net/if_arp.h> 131#include <net/ethernet.h> 132#include <net/if_dl.h> 133#include <net/if_media.h> 134#include <net/if_types.h> 135#include <net/if_vlan_var.h> 136 137#include <net/bpf.h> 138 139#include <machine/bus.h> 140#include <machine/resource.h> 141#include <sys/bus.h> 142#include <sys/rman.h> 143 144#include <dev/mii/mii.h> 145#include <dev/mii/miivar.h> 146 147#include <dev/pci/pcireg.h> 148#include <dev/pci/pcivar.h> 149 150#include <pci/if_rlreg.h> 151 152MODULE_DEPEND(re, pci, 1, 1, 1); 153MODULE_DEPEND(re, ether, 1, 1, 1); 154MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156/* "device miibus" required. See GENERIC if you get errors here. */ 157#include "miibus_if.h" 158 159/* Tunables. */ 160static int intr_filter = 0; 161TUNABLE_INT("hw.re.intr_filter", &intr_filter); 162static int msi_disable = 0; 163TUNABLE_INT("hw.re.msi_disable", &msi_disable); 164static int msix_disable = 0; 165TUNABLE_INT("hw.re.msix_disable", &msix_disable); 166static int prefer_iomap = 0; 167TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 168 169#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 171/* 172 * Various supported device vendors/types and their names. 173 */ 174static const struct rl_type const re_devs[] = { 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 179 { RT_VENDORID, RT_DEVICEID_8139, 0, 180 "RealTek 8139C+ 10/100BaseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8101E, 0, 182 "RealTek 810xE PCIe 10/100baseTX" }, 183 { RT_VENDORID, RT_DEVICEID_8168, 0, 184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, 0, 186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, 0, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 195}; 196 197static const struct rl_hwrev const re_hwrevs[] = { 198 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 227 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 228 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 229 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 230 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 232 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 233 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 234 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 235 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 237 { 0, 0, NULL, 0 } 238}; 239 240static int re_probe (device_t); 241static int re_attach (device_t); 242static int re_detach (device_t); 243 244static int re_encap (struct rl_softc *, struct mbuf **); 245 246static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 247static int re_allocmem (device_t, struct rl_softc *); 248static __inline void re_discard_rxbuf 249 (struct rl_softc *, int); 250static int re_newbuf (struct rl_softc *, int); 251static int re_jumbo_newbuf (struct rl_softc *, int); 252static int re_rx_list_init (struct rl_softc *); 253static int re_jrx_list_init (struct rl_softc *); 254static int re_tx_list_init (struct rl_softc *); 255#ifdef RE_FIXUP_RX 256static __inline void re_fixup_rx 257 (struct mbuf *); 258#endif 259static int re_rxeof (struct rl_softc *, int *); 260static void re_txeof (struct rl_softc *); 261#ifdef DEVICE_POLLING 262static int re_poll (struct ifnet *, enum poll_cmd, int); 263static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 264#endif 265static int re_intr (void *); 266static void re_intr_msi (void *); 267static void re_tick (void *); 268static void re_int_task (void *, int); 269static void re_start (struct ifnet *); 270static void re_start_locked (struct ifnet *); 271static int re_ioctl (struct ifnet *, u_long, caddr_t); 272static void re_init (void *); 273static void re_init_locked (struct rl_softc *); 274static void re_stop (struct rl_softc *); 275static void re_watchdog (struct rl_softc *); 276static int re_suspend (device_t); 277static int re_resume (device_t); 278static int re_shutdown (device_t); 279static int re_ifmedia_upd (struct ifnet *); 280static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 281 282static void re_eeprom_putbyte (struct rl_softc *, int); 283static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 284static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 285static int re_gmii_readreg (device_t, int, int); 286static int re_gmii_writereg (device_t, int, int, int); 287 288static int re_miibus_readreg (device_t, int, int); 289static int re_miibus_writereg (device_t, int, int, int); 290static void re_miibus_statchg (device_t); 291 292static void re_set_jumbo (struct rl_softc *, int); 293static void re_set_rxmode (struct rl_softc *); 294static void re_reset (struct rl_softc *); 295static void re_setwol (struct rl_softc *); 296static void re_clrwol (struct rl_softc *); 297static void re_set_linkspeed (struct rl_softc *); 298 299#ifdef RE_DIAG 300static int re_diag (struct rl_softc *); 301#endif 302 303static void re_add_sysctls (struct rl_softc *); 304static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 305static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 306static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 307 308static device_method_t re_methods[] = { 309 /* Device interface */ 310 DEVMETHOD(device_probe, re_probe), 311 DEVMETHOD(device_attach, re_attach), 312 DEVMETHOD(device_detach, re_detach), 313 DEVMETHOD(device_suspend, re_suspend), 314 DEVMETHOD(device_resume, re_resume), 315 DEVMETHOD(device_shutdown, re_shutdown), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, re_miibus_readreg), 319 DEVMETHOD(miibus_writereg, re_miibus_writereg), 320 DEVMETHOD(miibus_statchg, re_miibus_statchg), 321 322 DEVMETHOD_END 323}; 324 325static driver_t re_driver = { 326 "re", 327 re_methods, 328 sizeof(struct rl_softc) 329}; 330 331static devclass_t re_devclass; 332 333DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 334DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 335 336#define EE_SET(x) \ 337 CSR_WRITE_1(sc, RL_EECMD, \ 338 CSR_READ_1(sc, RL_EECMD) | x) 339 340#define EE_CLR(x) \ 341 CSR_WRITE_1(sc, RL_EECMD, \ 342 CSR_READ_1(sc, RL_EECMD) & ~x) 343 344/* 345 * Send a read command and address to the EEPROM, check for ACK. 346 */ 347static void 348re_eeprom_putbyte(struct rl_softc *sc, int addr) 349{ 350 int d, i; 351 352 d = addr | (RL_9346_READ << sc->rl_eewidth); 353 354 /* 355 * Feed in each bit and strobe the clock. 356 */ 357 358 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 359 if (d & i) { 360 EE_SET(RL_EE_DATAIN); 361 } else { 362 EE_CLR(RL_EE_DATAIN); 363 } 364 DELAY(100); 365 EE_SET(RL_EE_CLK); 366 DELAY(150); 367 EE_CLR(RL_EE_CLK); 368 DELAY(100); 369 } 370} 371 372/* 373 * Read a word of data stored in the EEPROM at address 'addr.' 374 */ 375static void 376re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 377{ 378 int i; 379 u_int16_t word = 0; 380 381 /* 382 * Send address of word we want to read. 383 */ 384 re_eeprom_putbyte(sc, addr); 385 386 /* 387 * Start reading bits from EEPROM. 388 */ 389 for (i = 0x8000; i; i >>= 1) { 390 EE_SET(RL_EE_CLK); 391 DELAY(100); 392 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 393 word |= i; 394 EE_CLR(RL_EE_CLK); 395 DELAY(100); 396 } 397 398 *dest = word; 399} 400 401/* 402 * Read a sequence of words from the EEPROM. 403 */ 404static void 405re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 406{ 407 int i; 408 u_int16_t word = 0, *ptr; 409 410 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 411 412 DELAY(100); 413 414 for (i = 0; i < cnt; i++) { 415 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 416 re_eeprom_getword(sc, off + i, &word); 417 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 418 ptr = (u_int16_t *)(dest + (i * 2)); 419 *ptr = word; 420 } 421 422 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 423} 424 425static int 426re_gmii_readreg(device_t dev, int phy, int reg) 427{ 428 struct rl_softc *sc; 429 u_int32_t rval; 430 int i; 431 432 sc = device_get_softc(dev); 433 434 /* Let the rgephy driver read the GMEDIASTAT register */ 435 436 if (reg == RL_GMEDIASTAT) { 437 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 438 return (rval); 439 } 440 441 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 442 443 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 444 rval = CSR_READ_4(sc, RL_PHYAR); 445 if (rval & RL_PHYAR_BUSY) 446 break; 447 DELAY(25); 448 } 449 450 if (i == RL_PHY_TIMEOUT) { 451 device_printf(sc->rl_dev, "PHY read failed\n"); 452 return (0); 453 } 454 455 /* 456 * Controller requires a 20us delay to process next MDIO request. 457 */ 458 DELAY(20); 459 460 return (rval & RL_PHYAR_PHYDATA); 461} 462 463static int 464re_gmii_writereg(device_t dev, int phy, int reg, int data) 465{ 466 struct rl_softc *sc; 467 u_int32_t rval; 468 int i; 469 470 sc = device_get_softc(dev); 471 472 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 473 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 474 475 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 476 rval = CSR_READ_4(sc, RL_PHYAR); 477 if (!(rval & RL_PHYAR_BUSY)) 478 break; 479 DELAY(25); 480 } 481 482 if (i == RL_PHY_TIMEOUT) { 483 device_printf(sc->rl_dev, "PHY write failed\n"); 484 return (0); 485 } 486 487 /* 488 * Controller requires a 20us delay to process next MDIO request. 489 */ 490 DELAY(20); 491 492 return (0); 493} 494 495static int 496re_miibus_readreg(device_t dev, int phy, int reg) 497{ 498 struct rl_softc *sc; 499 u_int16_t rval = 0; 500 u_int16_t re8139_reg = 0; 501 502 sc = device_get_softc(dev); 503 504 if (sc->rl_type == RL_8169) { 505 rval = re_gmii_readreg(dev, phy, reg); 506 return (rval); 507 } 508 509 switch (reg) { 510 case MII_BMCR: 511 re8139_reg = RL_BMCR; 512 break; 513 case MII_BMSR: 514 re8139_reg = RL_BMSR; 515 break; 516 case MII_ANAR: 517 re8139_reg = RL_ANAR; 518 break; 519 case MII_ANER: 520 re8139_reg = RL_ANER; 521 break; 522 case MII_ANLPAR: 523 re8139_reg = RL_LPAR; 524 break; 525 case MII_PHYIDR1: 526 case MII_PHYIDR2: 527 return (0); 528 /* 529 * Allow the rlphy driver to read the media status 530 * register. If we have a link partner which does not 531 * support NWAY, this is the register which will tell 532 * us the results of parallel detection. 533 */ 534 case RL_MEDIASTAT: 535 rval = CSR_READ_1(sc, RL_MEDIASTAT); 536 return (rval); 537 default: 538 device_printf(sc->rl_dev, "bad phy register\n"); 539 return (0); 540 } 541 rval = CSR_READ_2(sc, re8139_reg); 542 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 543 /* 8139C+ has different bit layout. */ 544 rval &= ~(BMCR_LOOP | BMCR_ISO); 545 } 546 return (rval); 547} 548 549static int 550re_miibus_writereg(device_t dev, int phy, int reg, int data) 551{ 552 struct rl_softc *sc; 553 u_int16_t re8139_reg = 0; 554 int rval = 0; 555 556 sc = device_get_softc(dev); 557 558 if (sc->rl_type == RL_8169) { 559 rval = re_gmii_writereg(dev, phy, reg, data); 560 return (rval); 561 } 562 563 switch (reg) { 564 case MII_BMCR: 565 re8139_reg = RL_BMCR; 566 if (sc->rl_type == RL_8139CPLUS) { 567 /* 8139C+ has different bit layout. */ 568 data &= ~(BMCR_LOOP | BMCR_ISO); 569 } 570 break; 571 case MII_BMSR: 572 re8139_reg = RL_BMSR; 573 break; 574 case MII_ANAR: 575 re8139_reg = RL_ANAR; 576 break; 577 case MII_ANER: 578 re8139_reg = RL_ANER; 579 break; 580 case MII_ANLPAR: 581 re8139_reg = RL_LPAR; 582 break; 583 case MII_PHYIDR1: 584 case MII_PHYIDR2: 585 return (0); 586 break; 587 default: 588 device_printf(sc->rl_dev, "bad phy register\n"); 589 return (0); 590 } 591 CSR_WRITE_2(sc, re8139_reg, data); 592 return (0); 593} 594 595static void 596re_miibus_statchg(device_t dev) 597{ 598 struct rl_softc *sc; 599 struct ifnet *ifp; 600 struct mii_data *mii; 601 602 sc = device_get_softc(dev); 603 mii = device_get_softc(sc->rl_miibus); 604 ifp = sc->rl_ifp; 605 if (mii == NULL || ifp == NULL || 606 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 607 return; 608 609 sc->rl_flags &= ~RL_FLAG_LINK; 610 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 611 (IFM_ACTIVE | IFM_AVALID)) { 612 switch (IFM_SUBTYPE(mii->mii_media_active)) { 613 case IFM_10_T: 614 case IFM_100_TX: 615 sc->rl_flags |= RL_FLAG_LINK; 616 break; 617 case IFM_1000_T: 618 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 619 break; 620 sc->rl_flags |= RL_FLAG_LINK; 621 break; 622 default: 623 break; 624 } 625 } 626 /* 627 * RealTek controllers does not provide any interface to 628 * Tx/Rx MACs for resolved speed, duplex and flow-control 629 * parameters. 630 */ 631} 632 633/* 634 * Set the RX configuration and 64-bit multicast hash filter. 635 */ 636static void 637re_set_rxmode(struct rl_softc *sc) 638{ 639 struct ifnet *ifp; 640 struct ifmultiaddr *ifma; 641 uint32_t hashes[2] = { 0, 0 }; 642 uint32_t h, rxfilt; 643 644 RL_LOCK_ASSERT(sc); 645 646 ifp = sc->rl_ifp; 647 648 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 649 650 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 651 if (ifp->if_flags & IFF_PROMISC) 652 rxfilt |= RL_RXCFG_RX_ALLPHYS; 653 /* 654 * Unlike other hardwares, we have to explicitly set 655 * RL_RXCFG_RX_MULTI to receive multicast frames in 656 * promiscuous mode. 657 */ 658 rxfilt |= RL_RXCFG_RX_MULTI; 659 hashes[0] = hashes[1] = 0xffffffff; 660 goto done; 661 } 662 663 if_maddr_rlock(ifp); 664 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 665 if (ifma->ifma_addr->sa_family != AF_LINK) 666 continue; 667 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 668 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 669 if (h < 32) 670 hashes[0] |= (1 << h); 671 else 672 hashes[1] |= (1 << (h - 32)); 673 } 674 if_maddr_runlock(ifp); 675 676 if (hashes[0] != 0 || hashes[1] != 0) { 677 /* 678 * For some unfathomable reason, RealTek decided to 679 * reverse the order of the multicast hash registers 680 * in the PCI Express parts. This means we have to 681 * write the hash pattern in reverse order for those 682 * devices. 683 */ 684 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 685 h = bswap32(hashes[0]); 686 hashes[0] = bswap32(hashes[1]); 687 hashes[1] = h; 688 } 689 rxfilt |= RL_RXCFG_RX_MULTI; 690 } 691 692done: 693 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 694 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 695 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 696} 697 698static void 699re_reset(struct rl_softc *sc) 700{ 701 int i; 702 703 RL_LOCK_ASSERT(sc); 704 705 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 706 707 for (i = 0; i < RL_TIMEOUT; i++) { 708 DELAY(10); 709 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 710 break; 711 } 712 if (i == RL_TIMEOUT) 713 device_printf(sc->rl_dev, "reset never completed!\n"); 714 715 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 716 CSR_WRITE_1(sc, 0x82, 1); 717 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 718 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 719} 720 721#ifdef RE_DIAG 722 723/* 724 * The following routine is designed to test for a defect on some 725 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 726 * lines connected to the bus, however for a 32-bit only card, they 727 * should be pulled high. The result of this defect is that the 728 * NIC will not work right if you plug it into a 64-bit slot: DMA 729 * operations will be done with 64-bit transfers, which will fail 730 * because the 64-bit data lines aren't connected. 731 * 732 * There's no way to work around this (short of talking a soldering 733 * iron to the board), however we can detect it. The method we use 734 * here is to put the NIC into digital loopback mode, set the receiver 735 * to promiscuous mode, and then try to send a frame. We then compare 736 * the frame data we sent to what was received. If the data matches, 737 * then the NIC is working correctly, otherwise we know the user has 738 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 739 * slot. In the latter case, there's no way the NIC can work correctly, 740 * so we print out a message on the console and abort the device attach. 741 */ 742 743static int 744re_diag(struct rl_softc *sc) 745{ 746 struct ifnet *ifp = sc->rl_ifp; 747 struct mbuf *m0; 748 struct ether_header *eh; 749 struct rl_desc *cur_rx; 750 u_int16_t status; 751 u_int32_t rxstat; 752 int total_len, i, error = 0, phyaddr; 753 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 754 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 755 756 /* Allocate a single mbuf */ 757 MGETHDR(m0, M_DONTWAIT, MT_DATA); 758 if (m0 == NULL) 759 return (ENOBUFS); 760 761 RL_LOCK(sc); 762 763 /* 764 * Initialize the NIC in test mode. This sets the chip up 765 * so that it can send and receive frames, but performs the 766 * following special functions: 767 * - Puts receiver in promiscuous mode 768 * - Enables digital loopback mode 769 * - Leaves interrupts turned off 770 */ 771 772 ifp->if_flags |= IFF_PROMISC; 773 sc->rl_testmode = 1; 774 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 775 re_init_locked(sc); 776 sc->rl_flags |= RL_FLAG_LINK; 777 if (sc->rl_type == RL_8169) 778 phyaddr = 1; 779 else 780 phyaddr = 0; 781 782 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 783 for (i = 0; i < RL_TIMEOUT; i++) { 784 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 785 if (!(status & BMCR_RESET)) 786 break; 787 } 788 789 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 790 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 791 792 DELAY(100000); 793 794 /* Put some data in the mbuf */ 795 796 eh = mtod(m0, struct ether_header *); 797 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 798 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 799 eh->ether_type = htons(ETHERTYPE_IP); 800 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 801 802 /* 803 * Queue the packet, start transmission. 804 * Note: IF_HANDOFF() ultimately calls re_start() for us. 805 */ 806 807 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 808 RL_UNLOCK(sc); 809 /* XXX: re_diag must not be called when in ALTQ mode */ 810 IF_HANDOFF(&ifp->if_snd, m0, ifp); 811 RL_LOCK(sc); 812 m0 = NULL; 813 814 /* Wait for it to propagate through the chip */ 815 816 DELAY(100000); 817 for (i = 0; i < RL_TIMEOUT; i++) { 818 status = CSR_READ_2(sc, RL_ISR); 819 CSR_WRITE_2(sc, RL_ISR, status); 820 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 821 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 822 break; 823 DELAY(10); 824 } 825 826 if (i == RL_TIMEOUT) { 827 device_printf(sc->rl_dev, 828 "diagnostic failed, failed to receive packet in" 829 " loopback mode\n"); 830 error = EIO; 831 goto done; 832 } 833 834 /* 835 * The packet should have been dumped into the first 836 * entry in the RX DMA ring. Grab it from there. 837 */ 838 839 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 840 sc->rl_ldata.rl_rx_list_map, 841 BUS_DMASYNC_POSTREAD); 842 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 843 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 844 BUS_DMASYNC_POSTREAD); 845 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 846 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 847 848 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 849 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 850 eh = mtod(m0, struct ether_header *); 851 852 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 853 total_len = RL_RXBYTES(cur_rx); 854 rxstat = le32toh(cur_rx->rl_cmdstat); 855 856 if (total_len != ETHER_MIN_LEN) { 857 device_printf(sc->rl_dev, 858 "diagnostic failed, received short packet\n"); 859 error = EIO; 860 goto done; 861 } 862 863 /* Test that the received packet data matches what we sent. */ 864 865 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 866 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 867 ntohs(eh->ether_type) != ETHERTYPE_IP) { 868 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 869 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 870 dst, ":", src, ":", ETHERTYPE_IP); 871 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 872 eh->ether_dhost, ":", eh->ether_shost, ":", 873 ntohs(eh->ether_type)); 874 device_printf(sc->rl_dev, "You may have a defective 32-bit " 875 "NIC plugged into a 64-bit PCI slot.\n"); 876 device_printf(sc->rl_dev, "Please re-install the NIC in a " 877 "32-bit slot for proper operation.\n"); 878 device_printf(sc->rl_dev, "Read the re(4) man page for more " 879 "details.\n"); 880 error = EIO; 881 } 882 883done: 884 /* Turn interface off, release resources */ 885 886 sc->rl_testmode = 0; 887 sc->rl_flags &= ~RL_FLAG_LINK; 888 ifp->if_flags &= ~IFF_PROMISC; 889 re_stop(sc); 890 if (m0 != NULL) 891 m_freem(m0); 892 893 RL_UNLOCK(sc); 894 895 return (error); 896} 897 898#endif 899 900/* 901 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 902 * IDs against our list and return a device name if we find a match. 903 */ 904static int 905re_probe(device_t dev) 906{ 907 const struct rl_type *t; 908 uint16_t devid, vendor; 909 uint16_t revid, sdevid; 910 int i; 911 912 vendor = pci_get_vendor(dev); 913 devid = pci_get_device(dev); 914 revid = pci_get_revid(dev); 915 sdevid = pci_get_subdevice(dev); 916 917 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 918 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 919 /* 920 * Only attach to rev. 3 of the Linksys EG1032 adapter. 921 * Rev. 2 is supported by sk(4). 922 */ 923 return (ENXIO); 924 } 925 } 926 927 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 928 if (revid != 0x20) { 929 /* 8139, let rl(4) take care of this device. */ 930 return (ENXIO); 931 } 932 } 933 934 t = re_devs; 935 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 936 if (vendor == t->rl_vid && devid == t->rl_did) { 937 device_set_desc(dev, t->rl_name); 938 return (BUS_PROBE_DEFAULT); 939 } 940 } 941 942 return (ENXIO); 943} 944 945/* 946 * Map a single buffer address. 947 */ 948 949static void 950re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 951{ 952 bus_addr_t *addr; 953 954 if (error) 955 return; 956 957 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 958 addr = arg; 959 *addr = segs->ds_addr; 960} 961 962static int 963re_allocmem(device_t dev, struct rl_softc *sc) 964{ 965 bus_addr_t lowaddr; 966 bus_size_t rx_list_size, tx_list_size; 967 int error; 968 int i; 969 970 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 971 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 972 973 /* 974 * Allocate the parent bus DMA tag appropriate for PCI. 975 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 976 * register should be set. However some RealTek chips are known 977 * to be buggy on DAC handling, therefore disable DAC by limiting 978 * DMA address space to 32bit. PCIe variants of RealTek chips 979 * may not have the limitation. 980 */ 981 lowaddr = BUS_SPACE_MAXADDR; 982 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 983 lowaddr = BUS_SPACE_MAXADDR_32BIT; 984 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 985 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 986 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 987 NULL, NULL, &sc->rl_parent_tag); 988 if (error) { 989 device_printf(dev, "could not allocate parent DMA tag\n"); 990 return (error); 991 } 992 993 /* 994 * Allocate map for TX mbufs. 995 */ 996 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 997 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 998 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 999 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1000 if (error) { 1001 device_printf(dev, "could not allocate TX DMA tag\n"); 1002 return (error); 1003 } 1004 1005 /* 1006 * Allocate map for RX mbufs. 1007 */ 1008 1009 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1010 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1011 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1012 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1013 &sc->rl_ldata.rl_jrx_mtag); 1014 if (error) { 1015 device_printf(dev, 1016 "could not allocate jumbo RX DMA tag\n"); 1017 return (error); 1018 } 1019 } 1020 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1021 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1022 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1023 if (error) { 1024 device_printf(dev, "could not allocate RX DMA tag\n"); 1025 return (error); 1026 } 1027 1028 /* 1029 * Allocate map for TX descriptor list. 1030 */ 1031 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1032 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1033 NULL, tx_list_size, 1, tx_list_size, 0, 1034 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1035 if (error) { 1036 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1037 return (error); 1038 } 1039 1040 /* Allocate DMA'able memory for the TX ring */ 1041 1042 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1043 (void **)&sc->rl_ldata.rl_tx_list, 1044 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1045 &sc->rl_ldata.rl_tx_list_map); 1046 if (error) { 1047 device_printf(dev, "could not allocate TX DMA ring\n"); 1048 return (error); 1049 } 1050 1051 /* Load the map for the TX ring. */ 1052 1053 sc->rl_ldata.rl_tx_list_addr = 0; 1054 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1055 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1056 tx_list_size, re_dma_map_addr, 1057 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1058 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1059 device_printf(dev, "could not load TX DMA ring\n"); 1060 return (ENOMEM); 1061 } 1062 1063 /* Create DMA maps for TX buffers */ 1064 1065 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1066 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1067 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1068 if (error) { 1069 device_printf(dev, "could not create DMA map for TX\n"); 1070 return (error); 1071 } 1072 } 1073 1074 /* 1075 * Allocate map for RX descriptor list. 1076 */ 1077 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1078 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1079 NULL, rx_list_size, 1, rx_list_size, 0, 1080 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1081 if (error) { 1082 device_printf(dev, "could not create RX DMA ring tag\n"); 1083 return (error); 1084 } 1085 1086 /* Allocate DMA'able memory for the RX ring */ 1087 1088 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1089 (void **)&sc->rl_ldata.rl_rx_list, 1090 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1091 &sc->rl_ldata.rl_rx_list_map); 1092 if (error) { 1093 device_printf(dev, "could not allocate RX DMA ring\n"); 1094 return (error); 1095 } 1096 1097 /* Load the map for the RX ring. */ 1098 1099 sc->rl_ldata.rl_rx_list_addr = 0; 1100 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1101 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1102 rx_list_size, re_dma_map_addr, 1103 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1104 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1105 device_printf(dev, "could not load RX DMA ring\n"); 1106 return (ENOMEM); 1107 } 1108 1109 /* Create DMA maps for RX buffers */ 1110 1111 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1112 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1113 &sc->rl_ldata.rl_jrx_sparemap); 1114 if (error) { 1115 device_printf(dev, 1116 "could not create spare DMA map for jumbo RX\n"); 1117 return (error); 1118 } 1119 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1120 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1121 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1122 if (error) { 1123 device_printf(dev, 1124 "could not create DMA map for jumbo RX\n"); 1125 return (error); 1126 } 1127 } 1128 } 1129 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1130 &sc->rl_ldata.rl_rx_sparemap); 1131 if (error) { 1132 device_printf(dev, "could not create spare DMA map for RX\n"); 1133 return (error); 1134 } 1135 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1136 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1137 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1138 if (error) { 1139 device_printf(dev, "could not create DMA map for RX\n"); 1140 return (error); 1141 } 1142 } 1143 1144 /* Create DMA map for statistics. */ 1145 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1146 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1147 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1148 &sc->rl_ldata.rl_stag); 1149 if (error) { 1150 device_printf(dev, "could not create statistics DMA tag\n"); 1151 return (error); 1152 } 1153 /* Allocate DMA'able memory for statistics. */ 1154 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1155 (void **)&sc->rl_ldata.rl_stats, 1156 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1157 &sc->rl_ldata.rl_smap); 1158 if (error) { 1159 device_printf(dev, 1160 "could not allocate statistics DMA memory\n"); 1161 return (error); 1162 } 1163 /* Load the map for statistics. */ 1164 sc->rl_ldata.rl_stats_addr = 0; 1165 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1166 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1167 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1168 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1169 device_printf(dev, "could not load statistics DMA memory\n"); 1170 return (ENOMEM); 1171 } 1172 1173 return (0); 1174} 1175 1176/* 1177 * Attach the interface. Allocate softc structures, do ifmedia 1178 * setup and ethernet/BPF attach. 1179 */ 1180static int 1181re_attach(device_t dev) 1182{ 1183 u_char eaddr[ETHER_ADDR_LEN]; 1184 u_int16_t as[ETHER_ADDR_LEN / 2]; 1185 struct rl_softc *sc; 1186 struct ifnet *ifp; 1187 const struct rl_hwrev *hw_rev; 1188 u_int32_t cap, ctl; 1189 int hwrev; 1190 u_int16_t devid, re_did = 0; 1191 int error = 0, i, phy, rid; 1192 int msic, msixc, reg; 1193 uint8_t cfg; 1194 1195 sc = device_get_softc(dev); 1196 sc->rl_dev = dev; 1197 1198 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1199 MTX_DEF); 1200 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1201 1202 /* 1203 * Map control/status registers. 1204 */ 1205 pci_enable_busmaster(dev); 1206 1207 devid = pci_get_device(dev); 1208 /* 1209 * Prefer memory space register mapping over IO space. 1210 * Because RTL8169SC does not seem to work when memory mapping 1211 * is used always activate io mapping. 1212 */ 1213 if (devid == RT_DEVICEID_8169SC) 1214 prefer_iomap = 1; 1215 if (prefer_iomap == 0) { 1216 sc->rl_res_id = PCIR_BAR(1); 1217 sc->rl_res_type = SYS_RES_MEMORY; 1218 /* RTL8168/8101E seems to use different BARs. */ 1219 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1220 sc->rl_res_id = PCIR_BAR(2); 1221 } else { 1222 sc->rl_res_id = PCIR_BAR(0); 1223 sc->rl_res_type = SYS_RES_IOPORT; 1224 } 1225 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1226 &sc->rl_res_id, RF_ACTIVE); 1227 if (sc->rl_res == NULL && prefer_iomap == 0) { 1228 sc->rl_res_id = PCIR_BAR(0); 1229 sc->rl_res_type = SYS_RES_IOPORT; 1230 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1231 &sc->rl_res_id, RF_ACTIVE); 1232 } 1233 if (sc->rl_res == NULL) { 1234 device_printf(dev, "couldn't map ports/memory\n"); 1235 error = ENXIO; 1236 goto fail; 1237 } 1238 1239 sc->rl_btag = rman_get_bustag(sc->rl_res); 1240 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1241 1242 msic = pci_msi_count(dev); 1243 msixc = pci_msix_count(dev); 1244 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1245 sc->rl_flags |= RL_FLAG_PCIE; 1246 sc->rl_expcap = reg; 1247 } 1248 if (bootverbose) { 1249 device_printf(dev, "MSI count : %d\n", msic); 1250 device_printf(dev, "MSI-X count : %d\n", msixc); 1251 } 1252 if (msix_disable > 0) 1253 msixc = 0; 1254 if (msi_disable > 0) 1255 msic = 0; 1256 /* Prefer MSI-X to MSI. */ 1257 if (msixc > 0) { 1258 msixc = 1; 1259 rid = PCIR_BAR(4); 1260 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1261 &rid, RF_ACTIVE); 1262 if (sc->rl_res_pba == NULL) { 1263 device_printf(sc->rl_dev, 1264 "could not allocate MSI-X PBA resource\n"); 1265 } 1266 if (sc->rl_res_pba != NULL && 1267 pci_alloc_msix(dev, &msixc) == 0) { 1268 if (msixc == 1) { 1269 device_printf(dev, "Using %d MSI-X message\n", 1270 msixc); 1271 sc->rl_flags |= RL_FLAG_MSIX; 1272 } else 1273 pci_release_msi(dev); 1274 } 1275 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1276 if (sc->rl_res_pba != NULL) 1277 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1278 sc->rl_res_pba); 1279 sc->rl_res_pba = NULL; 1280 msixc = 0; 1281 } 1282 } 1283 /* Prefer MSI to INTx. */ 1284 if (msixc == 0 && msic > 0) { 1285 msic = 1; 1286 if (pci_alloc_msi(dev, &msic) == 0) { 1287 if (msic == RL_MSI_MESSAGES) { 1288 device_printf(dev, "Using %d MSI message\n", 1289 msic); 1290 sc->rl_flags |= RL_FLAG_MSI; 1291 /* Explicitly set MSI enable bit. */ 1292 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1293 cfg = CSR_READ_1(sc, RL_CFG2); 1294 cfg |= RL_CFG2_MSI; 1295 CSR_WRITE_1(sc, RL_CFG2, cfg); 1296 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1297 } else 1298 pci_release_msi(dev); 1299 } 1300 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1301 msic = 0; 1302 } 1303 1304 /* Allocate interrupt */ 1305 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1306 rid = 0; 1307 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1308 RF_SHAREABLE | RF_ACTIVE); 1309 if (sc->rl_irq[0] == NULL) { 1310 device_printf(dev, "couldn't allocate IRQ resources\n"); 1311 error = ENXIO; 1312 goto fail; 1313 } 1314 } else { 1315 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1316 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1317 SYS_RES_IRQ, &rid, RF_ACTIVE); 1318 if (sc->rl_irq[i] == NULL) { 1319 device_printf(dev, 1320 "couldn't llocate IRQ resources for " 1321 "message %d\n", rid); 1322 error = ENXIO; 1323 goto fail; 1324 } 1325 } 1326 } 1327 1328 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1329 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1330 cfg = CSR_READ_1(sc, RL_CFG2); 1331 if ((cfg & RL_CFG2_MSI) != 0) { 1332 device_printf(dev, "turning off MSI enable bit.\n"); 1333 cfg &= ~RL_CFG2_MSI; 1334 CSR_WRITE_1(sc, RL_CFG2, cfg); 1335 } 1336 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1337 } 1338 1339 /* Disable ASPM L0S/L1. */ 1340 if (sc->rl_expcap != 0) { 1341 cap = pci_read_config(dev, sc->rl_expcap + 1342 PCIR_EXPRESS_LINK_CAP, 2); 1343 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 1344 ctl = pci_read_config(dev, sc->rl_expcap + 1345 PCIR_EXPRESS_LINK_CTL, 2); 1346 if ((ctl & 0x0003) != 0) { 1347 ctl &= ~0x0003; 1348 pci_write_config(dev, sc->rl_expcap + 1349 PCIR_EXPRESS_LINK_CTL, ctl, 2); 1350 device_printf(dev, "ASPM disabled\n"); 1351 } 1352 } else 1353 device_printf(dev, "no ASPM capability\n"); 1354 } 1355 1356 hw_rev = re_hwrevs; 1357 hwrev = CSR_READ_4(sc, RL_TXCFG); 1358 switch (hwrev & 0x70000000) { 1359 case 0x00000000: 1360 case 0x10000000: 1361 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1362 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1363 break; 1364 default: 1365 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1366 hwrev &= RL_TXCFG_HWREV; 1367 break; 1368 } 1369 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1370 while (hw_rev->rl_desc != NULL) { 1371 if (hw_rev->rl_rev == hwrev) { 1372 sc->rl_type = hw_rev->rl_type; 1373 sc->rl_hwrev = hw_rev; 1374 break; 1375 } 1376 hw_rev++; 1377 } 1378 if (hw_rev->rl_desc == NULL) { 1379 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1380 error = ENXIO; 1381 goto fail; 1382 } 1383 1384 switch (hw_rev->rl_rev) { 1385 case RL_HWREV_8139CPLUS: 1386 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1387 break; 1388 case RL_HWREV_8100E: 1389 case RL_HWREV_8101E: 1390 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1391 break; 1392 case RL_HWREV_8102E: 1393 case RL_HWREV_8102EL: 1394 case RL_HWREV_8102EL_SPIN1: 1395 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1396 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1397 RL_FLAG_AUTOPAD; 1398 break; 1399 case RL_HWREV_8103E: 1400 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1401 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1402 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1403 break; 1404 case RL_HWREV_8401E: 1405 case RL_HWREV_8105E: 1406 case RL_HWREV_8105E_SPIN1: 1407 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1408 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1409 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1410 break; 1411 case RL_HWREV_8402: 1412 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1413 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1414 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1415 RL_FLAG_CMDSTOP_WAIT_TXQ; 1416 break; 1417 case RL_HWREV_8168B_SPIN1: 1418 case RL_HWREV_8168B_SPIN2: 1419 sc->rl_flags |= RL_FLAG_WOLRXENB; 1420 /* FALLTHROUGH */ 1421 case RL_HWREV_8168B_SPIN3: 1422 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1423 break; 1424 case RL_HWREV_8168C_SPIN2: 1425 sc->rl_flags |= RL_FLAG_MACSLEEP; 1426 /* FALLTHROUGH */ 1427 case RL_HWREV_8168C: 1428 if ((hwrev & 0x00700000) == 0x00200000) 1429 sc->rl_flags |= RL_FLAG_MACSLEEP; 1430 /* FALLTHROUGH */ 1431 case RL_HWREV_8168CP: 1432 case RL_HWREV_8168D: 1433 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1434 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1435 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1436 break; 1437 case RL_HWREV_8168DP: 1438 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1439 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1440 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1441 break; 1442 case RL_HWREV_8168E: 1443 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1444 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1445 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1446 RL_FLAG_WOL_MANLINK; 1447 break; 1448 case RL_HWREV_8168E_VL: 1449 case RL_HWREV_8168F: 1450 case RL_HWREV_8411: 1451 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1452 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1453 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1454 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1455 break; 1456 case RL_HWREV_8169_8110SB: 1457 case RL_HWREV_8169_8110SBL: 1458 case RL_HWREV_8169_8110SC: 1459 case RL_HWREV_8169_8110SCE: 1460 sc->rl_flags |= RL_FLAG_PHYWAKE; 1461 /* FALLTHROUGH */ 1462 case RL_HWREV_8169: 1463 case RL_HWREV_8169S: 1464 case RL_HWREV_8110S: 1465 sc->rl_flags |= RL_FLAG_MACRESET; 1466 break; 1467 default: 1468 break; 1469 } 1470 1471 /* Reset the adapter. */ 1472 RL_LOCK(sc); 1473 re_reset(sc); 1474 RL_UNLOCK(sc); 1475 1476 /* Enable PME. */ 1477 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1478 cfg = CSR_READ_1(sc, RL_CFG1); 1479 cfg |= RL_CFG1_PME; 1480 CSR_WRITE_1(sc, RL_CFG1, cfg); 1481 cfg = CSR_READ_1(sc, RL_CFG5); 1482 cfg &= RL_CFG5_PME_STS; 1483 CSR_WRITE_1(sc, RL_CFG5, cfg); 1484 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1485 1486 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1487 /* 1488 * XXX Should have a better way to extract station 1489 * address from EEPROM. 1490 */ 1491 for (i = 0; i < ETHER_ADDR_LEN; i++) 1492 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1493 } else { 1494 sc->rl_eewidth = RL_9356_ADDR_LEN; 1495 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1496 if (re_did != 0x8129) 1497 sc->rl_eewidth = RL_9346_ADDR_LEN; 1498 1499 /* 1500 * Get station address from the EEPROM. 1501 */ 1502 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1503 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1504 as[i] = le16toh(as[i]); 1505 bcopy(as, eaddr, sizeof(eaddr)); 1506 } 1507 1508 if (sc->rl_type == RL_8169) { 1509 /* Set RX length mask and number of descriptors. */ 1510 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1511 sc->rl_txstart = RL_GTXSTART; 1512 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1513 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1514 } else { 1515 /* Set RX length mask and number of descriptors. */ 1516 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1517 sc->rl_txstart = RL_TXSTART; 1518 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1519 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1520 } 1521 1522 error = re_allocmem(dev, sc); 1523 if (error) 1524 goto fail; 1525 re_add_sysctls(sc); 1526 1527 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1528 if (ifp == NULL) { 1529 device_printf(dev, "can not if_alloc()\n"); 1530 error = ENOSPC; 1531 goto fail; 1532 } 1533 1534 /* Take controller out of deep sleep mode. */ 1535 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1536 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1537 CSR_WRITE_1(sc, RL_GPIO, 1538 CSR_READ_1(sc, RL_GPIO) | 0x01); 1539 else 1540 CSR_WRITE_1(sc, RL_GPIO, 1541 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1542 } 1543 1544 /* Take PHY out of power down mode. */ 1545 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1546 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1547 if (hw_rev->rl_rev == RL_HWREV_8401E) 1548 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1549 } 1550 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1551 re_gmii_writereg(dev, 1, 0x1f, 0); 1552 re_gmii_writereg(dev, 1, 0x0e, 0); 1553 } 1554 1555#define RE_PHYAD_INTERNAL 0 1556 1557 /* Do MII setup. */ 1558 phy = RE_PHYAD_INTERNAL; 1559 if (sc->rl_type == RL_8169) 1560 phy = 1; 1561 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1562 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1563 if (error != 0) { 1564 device_printf(dev, "attaching PHYs failed\n"); 1565 goto fail; 1566 } 1567 1568 ifp->if_softc = sc; 1569 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1570 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1571 ifp->if_ioctl = re_ioctl; 1572 ifp->if_start = re_start; 1573 /* 1574 * RTL8168/8111C generates wrong IP checksummed frame if the 1575 * packet has IP options so disable TX IP checksum offloading. 1576 */ 1577 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1578 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2) 1579 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1580 else 1581 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1582 ifp->if_hwassist |= CSUM_TSO; 1583 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1584 ifp->if_capenable = ifp->if_capabilities; 1585 ifp->if_init = re_init; 1586 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1587 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1588 IFQ_SET_READY(&ifp->if_snd); 1589 1590 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1591 1592 /* 1593 * Call MI attach routine. 1594 */ 1595 ether_ifattach(ifp, eaddr); 1596 1597 /* VLAN capability setup */ 1598 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1599 if (ifp->if_capabilities & IFCAP_HWCSUM) 1600 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1601 /* Enable WOL if PM is supported. */ 1602 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1603 ifp->if_capabilities |= IFCAP_WOL; 1604 ifp->if_capenable = ifp->if_capabilities; 1605 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1606 /* 1607 * Don't enable TSO by default. It is known to generate 1608 * corrupted TCP segments(bad TCP options) under certain 1609 * circumtances. 1610 */ 1611 ifp->if_hwassist &= ~CSUM_TSO; 1612 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1613#ifdef DEVICE_POLLING 1614 ifp->if_capabilities |= IFCAP_POLLING; 1615#endif 1616 /* 1617 * Tell the upper layer(s) we support long frames. 1618 * Must appear after the call to ether_ifattach() because 1619 * ether_ifattach() sets ifi_hdrlen to the default value. 1620 */ 1621 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1622 1623#ifdef RE_DIAG 1624 /* 1625 * Perform hardware diagnostic on the original RTL8169. 1626 * Some 32-bit cards were incorrectly wired and would 1627 * malfunction if plugged into a 64-bit slot. 1628 */ 1629 1630 if (hwrev == RL_HWREV_8169) { 1631 error = re_diag(sc); 1632 if (error) { 1633 device_printf(dev, 1634 "attach aborted due to hardware diag failure\n"); 1635 ether_ifdetach(ifp); 1636 goto fail; 1637 } 1638 } 1639#endif 1640 1641#ifdef RE_TX_MODERATION 1642 intr_filter = 1; 1643#endif 1644 /* Hook interrupt last to avoid having to lock softc */ 1645 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1646 intr_filter == 0) { 1647 error = bus_setup_intr(dev, sc->rl_irq[0], 1648 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1649 &sc->rl_intrhand[0]); 1650 } else { 1651 error = bus_setup_intr(dev, sc->rl_irq[0], 1652 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1653 &sc->rl_intrhand[0]); 1654 } 1655 if (error) { 1656 device_printf(dev, "couldn't set up irq\n"); 1657 ether_ifdetach(ifp); 1658 } 1659 1660fail: 1661 1662 if (error) 1663 re_detach(dev); 1664 1665 return (error); 1666} 1667 1668/* 1669 * Shutdown hardware and free up resources. This can be called any 1670 * time after the mutex has been initialized. It is called in both 1671 * the error case in attach and the normal detach case so it needs 1672 * to be careful about only freeing resources that have actually been 1673 * allocated. 1674 */ 1675static int 1676re_detach(device_t dev) 1677{ 1678 struct rl_softc *sc; 1679 struct ifnet *ifp; 1680 int i, rid; 1681 1682 sc = device_get_softc(dev); 1683 ifp = sc->rl_ifp; 1684 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1685 1686 /* These should only be active if attach succeeded */ 1687 if (device_is_attached(dev)) { 1688#ifdef DEVICE_POLLING 1689 if (ifp->if_capenable & IFCAP_POLLING) 1690 ether_poll_deregister(ifp); 1691#endif 1692 RL_LOCK(sc); 1693#if 0 1694 sc->suspended = 1; 1695#endif 1696 re_stop(sc); 1697 RL_UNLOCK(sc); 1698 callout_drain(&sc->rl_stat_callout); 1699 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1700 /* 1701 * Force off the IFF_UP flag here, in case someone 1702 * still had a BPF descriptor attached to this 1703 * interface. If they do, ether_ifdetach() will cause 1704 * the BPF code to try and clear the promisc mode 1705 * flag, which will bubble down to re_ioctl(), 1706 * which will try to call re_init() again. This will 1707 * turn the NIC back on and restart the MII ticker, 1708 * which will panic the system when the kernel tries 1709 * to invoke the re_tick() function that isn't there 1710 * anymore. 1711 */ 1712 ifp->if_flags &= ~IFF_UP; 1713 ether_ifdetach(ifp); 1714 } 1715 if (sc->rl_miibus) 1716 device_delete_child(dev, sc->rl_miibus); 1717 bus_generic_detach(dev); 1718 1719 /* 1720 * The rest is resource deallocation, so we should already be 1721 * stopped here. 1722 */ 1723 1724 if (sc->rl_intrhand[0] != NULL) { 1725 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1726 sc->rl_intrhand[0] = NULL; 1727 } 1728 if (ifp != NULL) 1729 if_free(ifp); 1730 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1731 rid = 0; 1732 else 1733 rid = 1; 1734 if (sc->rl_irq[0] != NULL) { 1735 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1736 sc->rl_irq[0] = NULL; 1737 } 1738 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1739 pci_release_msi(dev); 1740 if (sc->rl_res_pba) { 1741 rid = PCIR_BAR(4); 1742 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1743 } 1744 if (sc->rl_res) 1745 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1746 sc->rl_res); 1747 1748 /* Unload and free the RX DMA ring memory and map */ 1749 1750 if (sc->rl_ldata.rl_rx_list_tag) { 1751 if (sc->rl_ldata.rl_rx_list_map) 1752 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1753 sc->rl_ldata.rl_rx_list_map); 1754 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1755 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1756 sc->rl_ldata.rl_rx_list, 1757 sc->rl_ldata.rl_rx_list_map); 1758 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1759 } 1760 1761 /* Unload and free the TX DMA ring memory and map */ 1762 1763 if (sc->rl_ldata.rl_tx_list_tag) { 1764 if (sc->rl_ldata.rl_tx_list_map) 1765 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1766 sc->rl_ldata.rl_tx_list_map); 1767 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1768 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1769 sc->rl_ldata.rl_tx_list, 1770 sc->rl_ldata.rl_tx_list_map); 1771 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1772 } 1773 1774 /* Destroy all the RX and TX buffer maps */ 1775 1776 if (sc->rl_ldata.rl_tx_mtag) { 1777 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1778 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1779 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1780 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1781 } 1782 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1783 } 1784 if (sc->rl_ldata.rl_rx_mtag) { 1785 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1786 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1787 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1788 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1789 } 1790 if (sc->rl_ldata.rl_rx_sparemap) 1791 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1792 sc->rl_ldata.rl_rx_sparemap); 1793 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1794 } 1795 if (sc->rl_ldata.rl_jrx_mtag) { 1796 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1797 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1798 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1799 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1800 } 1801 if (sc->rl_ldata.rl_jrx_sparemap) 1802 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1803 sc->rl_ldata.rl_jrx_sparemap); 1804 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1805 } 1806 /* Unload and free the stats buffer and map */ 1807 1808 if (sc->rl_ldata.rl_stag) { 1809 if (sc->rl_ldata.rl_smap) 1810 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1811 sc->rl_ldata.rl_smap); 1812 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1813 bus_dmamem_free(sc->rl_ldata.rl_stag, 1814 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1815 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1816 } 1817 1818 if (sc->rl_parent_tag) 1819 bus_dma_tag_destroy(sc->rl_parent_tag); 1820 1821 mtx_destroy(&sc->rl_mtx); 1822 1823 return (0); 1824} 1825 1826static __inline void 1827re_discard_rxbuf(struct rl_softc *sc, int idx) 1828{ 1829 struct rl_desc *desc; 1830 struct rl_rxdesc *rxd; 1831 uint32_t cmdstat; 1832 1833 if (sc->rl_ifp->if_mtu > RL_MTU && 1834 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1835 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1836 else 1837 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1838 desc = &sc->rl_ldata.rl_rx_list[idx]; 1839 desc->rl_vlanctl = 0; 1840 cmdstat = rxd->rx_size; 1841 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1842 cmdstat |= RL_RDESC_CMD_EOR; 1843 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1844} 1845 1846static int 1847re_newbuf(struct rl_softc *sc, int idx) 1848{ 1849 struct mbuf *m; 1850 struct rl_rxdesc *rxd; 1851 bus_dma_segment_t segs[1]; 1852 bus_dmamap_t map; 1853 struct rl_desc *desc; 1854 uint32_t cmdstat; 1855 int error, nsegs; 1856 1857 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1858 if (m == NULL) 1859 return (ENOBUFS); 1860 1861 m->m_len = m->m_pkthdr.len = MCLBYTES; 1862#ifdef RE_FIXUP_RX 1863 /* 1864 * This is part of an evil trick to deal with non-x86 platforms. 1865 * The RealTek chip requires RX buffers to be aligned on 64-bit 1866 * boundaries, but that will hose non-x86 machines. To get around 1867 * this, we leave some empty space at the start of each buffer 1868 * and for non-x86 hosts, we copy the buffer back six bytes 1869 * to achieve word alignment. This is slightly more efficient 1870 * than allocating a new buffer, copying the contents, and 1871 * discarding the old buffer. 1872 */ 1873 m_adj(m, RE_ETHER_ALIGN); 1874#endif 1875 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1876 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1877 if (error != 0) { 1878 m_freem(m); 1879 return (ENOBUFS); 1880 } 1881 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1882 1883 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1884 if (rxd->rx_m != NULL) { 1885 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1886 BUS_DMASYNC_POSTREAD); 1887 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1888 } 1889 1890 rxd->rx_m = m; 1891 map = rxd->rx_dmamap; 1892 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1893 rxd->rx_size = segs[0].ds_len; 1894 sc->rl_ldata.rl_rx_sparemap = map; 1895 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1896 BUS_DMASYNC_PREREAD); 1897 1898 desc = &sc->rl_ldata.rl_rx_list[idx]; 1899 desc->rl_vlanctl = 0; 1900 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1901 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1902 cmdstat = segs[0].ds_len; 1903 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1904 cmdstat |= RL_RDESC_CMD_EOR; 1905 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1906 1907 return (0); 1908} 1909 1910static int 1911re_jumbo_newbuf(struct rl_softc *sc, int idx) 1912{ 1913 struct mbuf *m; 1914 struct rl_rxdesc *rxd; 1915 bus_dma_segment_t segs[1]; 1916 bus_dmamap_t map; 1917 struct rl_desc *desc; 1918 uint32_t cmdstat; 1919 int error, nsegs; 1920 1921 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1922 if (m == NULL) 1923 return (ENOBUFS); 1924 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1925#ifdef RE_FIXUP_RX 1926 m_adj(m, RE_ETHER_ALIGN); 1927#endif 1928 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1929 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1930 if (error != 0) { 1931 m_freem(m); 1932 return (ENOBUFS); 1933 } 1934 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1935 1936 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1937 if (rxd->rx_m != NULL) { 1938 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1939 BUS_DMASYNC_POSTREAD); 1940 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1941 } 1942 1943 rxd->rx_m = m; 1944 map = rxd->rx_dmamap; 1945 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 1946 rxd->rx_size = segs[0].ds_len; 1947 sc->rl_ldata.rl_jrx_sparemap = map; 1948 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1949 BUS_DMASYNC_PREREAD); 1950 1951 desc = &sc->rl_ldata.rl_rx_list[idx]; 1952 desc->rl_vlanctl = 0; 1953 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1954 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1955 cmdstat = segs[0].ds_len; 1956 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1957 cmdstat |= RL_RDESC_CMD_EOR; 1958 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1959 1960 return (0); 1961} 1962 1963#ifdef RE_FIXUP_RX 1964static __inline void 1965re_fixup_rx(struct mbuf *m) 1966{ 1967 int i; 1968 uint16_t *src, *dst; 1969 1970 src = mtod(m, uint16_t *); 1971 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1972 1973 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1974 *dst++ = *src++; 1975 1976 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1977} 1978#endif 1979 1980static int 1981re_tx_list_init(struct rl_softc *sc) 1982{ 1983 struct rl_desc *desc; 1984 int i; 1985 1986 RL_LOCK_ASSERT(sc); 1987 1988 bzero(sc->rl_ldata.rl_tx_list, 1989 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1990 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1991 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1992 /* Set EOR. */ 1993 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1994 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1995 1996 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1997 sc->rl_ldata.rl_tx_list_map, 1998 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1999 2000 sc->rl_ldata.rl_tx_prodidx = 0; 2001 sc->rl_ldata.rl_tx_considx = 0; 2002 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2003 2004 return (0); 2005} 2006 2007static int 2008re_rx_list_init(struct rl_softc *sc) 2009{ 2010 int error, i; 2011 2012 bzero(sc->rl_ldata.rl_rx_list, 2013 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2014 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2015 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2016 if ((error = re_newbuf(sc, i)) != 0) 2017 return (error); 2018 } 2019 2020 /* Flush the RX descriptors */ 2021 2022 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2023 sc->rl_ldata.rl_rx_list_map, 2024 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2025 2026 sc->rl_ldata.rl_rx_prodidx = 0; 2027 sc->rl_head = sc->rl_tail = NULL; 2028 sc->rl_int_rx_act = 0; 2029 2030 return (0); 2031} 2032 2033static int 2034re_jrx_list_init(struct rl_softc *sc) 2035{ 2036 int error, i; 2037 2038 bzero(sc->rl_ldata.rl_rx_list, 2039 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2040 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2041 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2042 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2043 return (error); 2044 } 2045 2046 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2047 sc->rl_ldata.rl_rx_list_map, 2048 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2049 2050 sc->rl_ldata.rl_rx_prodidx = 0; 2051 sc->rl_head = sc->rl_tail = NULL; 2052 sc->rl_int_rx_act = 0; 2053 2054 return (0); 2055} 2056 2057/* 2058 * RX handler for C+ and 8169. For the gigE chips, we support 2059 * the reception of jumbo frames that have been fragmented 2060 * across multiple 2K mbuf cluster buffers. 2061 */ 2062static int 2063re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2064{ 2065 struct mbuf *m; 2066 struct ifnet *ifp; 2067 int i, rxerr, total_len; 2068 struct rl_desc *cur_rx; 2069 u_int32_t rxstat, rxvlan; 2070 int jumbo, maxpkt = 16, rx_npkts = 0; 2071 2072 RL_LOCK_ASSERT(sc); 2073 2074 ifp = sc->rl_ifp; 2075 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2076 jumbo = 1; 2077 else 2078 jumbo = 0; 2079 2080 /* Invalidate the descriptor memory */ 2081 2082 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2083 sc->rl_ldata.rl_rx_list_map, 2084 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2085 2086 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2087 i = RL_RX_DESC_NXT(sc, i)) { 2088 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2089 break; 2090 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2091 rxstat = le32toh(cur_rx->rl_cmdstat); 2092 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2093 break; 2094 total_len = rxstat & sc->rl_rxlenmask; 2095 rxvlan = le32toh(cur_rx->rl_vlanctl); 2096 if (jumbo != 0) 2097 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2098 else 2099 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2100 2101 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2102 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2103 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2104 /* 2105 * RTL8168C or later controllers do not 2106 * support multi-fragment packet. 2107 */ 2108 re_discard_rxbuf(sc, i); 2109 continue; 2110 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2111 if (re_newbuf(sc, i) != 0) { 2112 /* 2113 * If this is part of a multi-fragment packet, 2114 * discard all the pieces. 2115 */ 2116 if (sc->rl_head != NULL) { 2117 m_freem(sc->rl_head); 2118 sc->rl_head = sc->rl_tail = NULL; 2119 } 2120 re_discard_rxbuf(sc, i); 2121 continue; 2122 } 2123 m->m_len = RE_RX_DESC_BUFLEN; 2124 if (sc->rl_head == NULL) 2125 sc->rl_head = sc->rl_tail = m; 2126 else { 2127 m->m_flags &= ~M_PKTHDR; 2128 sc->rl_tail->m_next = m; 2129 sc->rl_tail = m; 2130 } 2131 continue; 2132 } 2133 2134 /* 2135 * NOTE: for the 8139C+, the frame length field 2136 * is always 12 bits in size, but for the gigE chips, 2137 * it is 13 bits (since the max RX frame length is 16K). 2138 * Unfortunately, all 32 bits in the status word 2139 * were already used, so to make room for the extra 2140 * length bit, RealTek took out the 'frame alignment 2141 * error' bit and shifted the other status bits 2142 * over one slot. The OWN, EOR, FS and LS bits are 2143 * still in the same places. We have already extracted 2144 * the frame length and checked the OWN bit, so rather 2145 * than using an alternate bit mapping, we shift the 2146 * status bits one space to the right so we can evaluate 2147 * them using the 8169 status as though it was in the 2148 * same format as that of the 8139C+. 2149 */ 2150 if (sc->rl_type == RL_8169) 2151 rxstat >>= 1; 2152 2153 /* 2154 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2155 * set, but if CRC is clear, it will still be a valid frame. 2156 */ 2157 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2158 rxerr = 1; 2159 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2160 total_len > 8191 && 2161 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2162 rxerr = 0; 2163 if (rxerr != 0) { 2164 ifp->if_ierrors++; 2165 /* 2166 * If this is part of a multi-fragment packet, 2167 * discard all the pieces. 2168 */ 2169 if (sc->rl_head != NULL) { 2170 m_freem(sc->rl_head); 2171 sc->rl_head = sc->rl_tail = NULL; 2172 } 2173 re_discard_rxbuf(sc, i); 2174 continue; 2175 } 2176 } 2177 2178 /* 2179 * If allocating a replacement mbuf fails, 2180 * reload the current one. 2181 */ 2182 if (jumbo != 0) 2183 rxerr = re_jumbo_newbuf(sc, i); 2184 else 2185 rxerr = re_newbuf(sc, i); 2186 if (rxerr != 0) { 2187 ifp->if_iqdrops++; 2188 if (sc->rl_head != NULL) { 2189 m_freem(sc->rl_head); 2190 sc->rl_head = sc->rl_tail = NULL; 2191 } 2192 re_discard_rxbuf(sc, i); 2193 continue; 2194 } 2195 2196 if (sc->rl_head != NULL) { 2197 if (jumbo != 0) 2198 m->m_len = total_len; 2199 else { 2200 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2201 if (m->m_len == 0) 2202 m->m_len = RE_RX_DESC_BUFLEN; 2203 } 2204 /* 2205 * Special case: if there's 4 bytes or less 2206 * in this buffer, the mbuf can be discarded: 2207 * the last 4 bytes is the CRC, which we don't 2208 * care about anyway. 2209 */ 2210 if (m->m_len <= ETHER_CRC_LEN) { 2211 sc->rl_tail->m_len -= 2212 (ETHER_CRC_LEN - m->m_len); 2213 m_freem(m); 2214 } else { 2215 m->m_len -= ETHER_CRC_LEN; 2216 m->m_flags &= ~M_PKTHDR; 2217 sc->rl_tail->m_next = m; 2218 } 2219 m = sc->rl_head; 2220 sc->rl_head = sc->rl_tail = NULL; 2221 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2222 } else 2223 m->m_pkthdr.len = m->m_len = 2224 (total_len - ETHER_CRC_LEN); 2225 2226#ifdef RE_FIXUP_RX 2227 re_fixup_rx(m); 2228#endif 2229 ifp->if_ipackets++; 2230 m->m_pkthdr.rcvif = ifp; 2231 2232 /* Do RX checksumming if enabled */ 2233 2234 if (ifp->if_capenable & IFCAP_RXCSUM) { 2235 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2236 /* Check IP header checksum */ 2237 if (rxstat & RL_RDESC_STAT_PROTOID) 2238 m->m_pkthdr.csum_flags |= 2239 CSUM_IP_CHECKED; 2240 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2241 m->m_pkthdr.csum_flags |= 2242 CSUM_IP_VALID; 2243 2244 /* Check TCP/UDP checksum */ 2245 if ((RL_TCPPKT(rxstat) && 2246 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2247 (RL_UDPPKT(rxstat) && 2248 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2249 m->m_pkthdr.csum_flags |= 2250 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2251 m->m_pkthdr.csum_data = 0xffff; 2252 } 2253 } else { 2254 /* 2255 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2256 */ 2257 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2258 (rxvlan & RL_RDESC_IPV4)) 2259 m->m_pkthdr.csum_flags |= 2260 CSUM_IP_CHECKED; 2261 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2262 (rxvlan & RL_RDESC_IPV4)) 2263 m->m_pkthdr.csum_flags |= 2264 CSUM_IP_VALID; 2265 if (((rxstat & RL_RDESC_STAT_TCP) && 2266 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2267 ((rxstat & RL_RDESC_STAT_UDP) && 2268 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2269 m->m_pkthdr.csum_flags |= 2270 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2271 m->m_pkthdr.csum_data = 0xffff; 2272 } 2273 } 2274 } 2275 maxpkt--; 2276 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2277 m->m_pkthdr.ether_vtag = 2278 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2279 m->m_flags |= M_VLANTAG; 2280 } 2281 RL_UNLOCK(sc); 2282 (*ifp->if_input)(ifp, m); 2283 RL_LOCK(sc); 2284 rx_npkts++; 2285 } 2286 2287 /* Flush the RX DMA ring */ 2288 2289 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2290 sc->rl_ldata.rl_rx_list_map, 2291 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2292 2293 sc->rl_ldata.rl_rx_prodidx = i; 2294 2295 if (rx_npktsp != NULL) 2296 *rx_npktsp = rx_npkts; 2297 if (maxpkt) 2298 return (EAGAIN); 2299 2300 return (0); 2301} 2302 2303static void 2304re_txeof(struct rl_softc *sc) 2305{ 2306 struct ifnet *ifp; 2307 struct rl_txdesc *txd; 2308 u_int32_t txstat; 2309 int cons; 2310 2311 cons = sc->rl_ldata.rl_tx_considx; 2312 if (cons == sc->rl_ldata.rl_tx_prodidx) 2313 return; 2314 2315 ifp = sc->rl_ifp; 2316 /* Invalidate the TX descriptor list */ 2317 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2318 sc->rl_ldata.rl_tx_list_map, 2319 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2320 2321 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2322 cons = RL_TX_DESC_NXT(sc, cons)) { 2323 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2324 if (txstat & RL_TDESC_STAT_OWN) 2325 break; 2326 /* 2327 * We only stash mbufs in the last descriptor 2328 * in a fragment chain, which also happens to 2329 * be the only place where the TX status bits 2330 * are valid. 2331 */ 2332 if (txstat & RL_TDESC_CMD_EOF) { 2333 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2334 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2335 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2336 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2337 txd->tx_dmamap); 2338 KASSERT(txd->tx_m != NULL, 2339 ("%s: freeing NULL mbufs!", __func__)); 2340 m_freem(txd->tx_m); 2341 txd->tx_m = NULL; 2342 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2343 RL_TDESC_STAT_COLCNT)) 2344 ifp->if_collisions++; 2345 if (txstat & RL_TDESC_STAT_TXERRSUM) 2346 ifp->if_oerrors++; 2347 else 2348 ifp->if_opackets++; 2349 } 2350 sc->rl_ldata.rl_tx_free++; 2351 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2352 } 2353 sc->rl_ldata.rl_tx_considx = cons; 2354 2355 /* No changes made to the TX ring, so no flush needed */ 2356 2357 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2358#ifdef RE_TX_MODERATION 2359 /* 2360 * If not all descriptors have been reaped yet, reload 2361 * the timer so that we will eventually get another 2362 * interrupt that will cause us to re-enter this routine. 2363 * This is done in case the transmitter has gone idle. 2364 */ 2365 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2366#endif 2367 } else 2368 sc->rl_watchdog_timer = 0; 2369} 2370 2371static void 2372re_tick(void *xsc) 2373{ 2374 struct rl_softc *sc; 2375 struct mii_data *mii; 2376 2377 sc = xsc; 2378 2379 RL_LOCK_ASSERT(sc); 2380 2381 mii = device_get_softc(sc->rl_miibus); 2382 mii_tick(mii); 2383 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2384 re_miibus_statchg(sc->rl_dev); 2385 /* 2386 * Reclaim transmitted frames here. Technically it is not 2387 * necessary to do here but it ensures periodic reclamation 2388 * regardless of Tx completion interrupt which seems to be 2389 * lost on PCIe based controllers under certain situations. 2390 */ 2391 re_txeof(sc); 2392 re_watchdog(sc); 2393 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2394} 2395 2396#ifdef DEVICE_POLLING 2397static int 2398re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2399{ 2400 struct rl_softc *sc = ifp->if_softc; 2401 int rx_npkts = 0; 2402 2403 RL_LOCK(sc); 2404 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2405 rx_npkts = re_poll_locked(ifp, cmd, count); 2406 RL_UNLOCK(sc); 2407 return (rx_npkts); 2408} 2409 2410static int 2411re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2412{ 2413 struct rl_softc *sc = ifp->if_softc; 2414 int rx_npkts; 2415 2416 RL_LOCK_ASSERT(sc); 2417 2418 sc->rxcycles = count; 2419 re_rxeof(sc, &rx_npkts); 2420 re_txeof(sc); 2421 2422 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2423 re_start_locked(ifp); 2424 2425 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2426 u_int16_t status; 2427 2428 status = CSR_READ_2(sc, RL_ISR); 2429 if (status == 0xffff) 2430 return (rx_npkts); 2431 if (status) 2432 CSR_WRITE_2(sc, RL_ISR, status); 2433 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2434 (sc->rl_flags & RL_FLAG_PCIE)) 2435 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2436 2437 /* 2438 * XXX check behaviour on receiver stalls. 2439 */ 2440 2441 if (status & RL_ISR_SYSTEM_ERR) { 2442 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2443 re_init_locked(sc); 2444 } 2445 } 2446 return (rx_npkts); 2447} 2448#endif /* DEVICE_POLLING */ 2449 2450static int 2451re_intr(void *arg) 2452{ 2453 struct rl_softc *sc; 2454 uint16_t status; 2455 2456 sc = arg; 2457 2458 status = CSR_READ_2(sc, RL_ISR); 2459 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2460 return (FILTER_STRAY); 2461 CSR_WRITE_2(sc, RL_IMR, 0); 2462 2463 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2464 2465 return (FILTER_HANDLED); 2466} 2467 2468static void 2469re_int_task(void *arg, int npending) 2470{ 2471 struct rl_softc *sc; 2472 struct ifnet *ifp; 2473 u_int16_t status; 2474 int rval = 0; 2475 2476 sc = arg; 2477 ifp = sc->rl_ifp; 2478 2479 RL_LOCK(sc); 2480 2481 status = CSR_READ_2(sc, RL_ISR); 2482 CSR_WRITE_2(sc, RL_ISR, status); 2483 2484 if (sc->suspended || 2485 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2486 RL_UNLOCK(sc); 2487 return; 2488 } 2489 2490#ifdef DEVICE_POLLING 2491 if (ifp->if_capenable & IFCAP_POLLING) { 2492 RL_UNLOCK(sc); 2493 return; 2494 } 2495#endif 2496 2497 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2498 rval = re_rxeof(sc, NULL); 2499 2500 /* 2501 * Some chips will ignore a second TX request issued 2502 * while an existing transmission is in progress. If 2503 * the transmitter goes idle but there are still 2504 * packets waiting to be sent, we need to restart the 2505 * channel here to flush them out. This only seems to 2506 * be required with the PCIe devices. 2507 */ 2508 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2509 (sc->rl_flags & RL_FLAG_PCIE)) 2510 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2511 if (status & ( 2512#ifdef RE_TX_MODERATION 2513 RL_ISR_TIMEOUT_EXPIRED| 2514#else 2515 RL_ISR_TX_OK| 2516#endif 2517 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2518 re_txeof(sc); 2519 2520 if (status & RL_ISR_SYSTEM_ERR) { 2521 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2522 re_init_locked(sc); 2523 } 2524 2525 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2526 re_start_locked(ifp); 2527 2528 RL_UNLOCK(sc); 2529 2530 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2531 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2532 return; 2533 } 2534 2535 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2536} 2537 2538static void 2539re_intr_msi(void *xsc) 2540{ 2541 struct rl_softc *sc; 2542 struct ifnet *ifp; 2543 uint16_t intrs, status; 2544 2545 sc = xsc; 2546 RL_LOCK(sc); 2547 2548 ifp = sc->rl_ifp; 2549#ifdef DEVICE_POLLING 2550 if (ifp->if_capenable & IFCAP_POLLING) { 2551 RL_UNLOCK(sc); 2552 return; 2553 } 2554#endif 2555 /* Disable interrupts. */ 2556 CSR_WRITE_2(sc, RL_IMR, 0); 2557 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2558 RL_UNLOCK(sc); 2559 return; 2560 } 2561 2562 intrs = RL_INTRS_CPLUS; 2563 status = CSR_READ_2(sc, RL_ISR); 2564 CSR_WRITE_2(sc, RL_ISR, status); 2565 if (sc->rl_int_rx_act > 0) { 2566 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2567 RL_ISR_RX_OVERRUN); 2568 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2569 RL_ISR_RX_OVERRUN); 2570 } 2571 2572 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2573 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2574 re_rxeof(sc, NULL); 2575 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2576 if (sc->rl_int_rx_mod != 0 && 2577 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2578 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2579 /* Rearm one-shot timer. */ 2580 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2581 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2582 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2583 sc->rl_int_rx_act = 1; 2584 } else { 2585 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2586 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2587 sc->rl_int_rx_act = 0; 2588 } 2589 } 2590 } 2591 2592 /* 2593 * Some chips will ignore a second TX request issued 2594 * while an existing transmission is in progress. If 2595 * the transmitter goes idle but there are still 2596 * packets waiting to be sent, we need to restart the 2597 * channel here to flush them out. This only seems to 2598 * be required with the PCIe devices. 2599 */ 2600 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2601 (sc->rl_flags & RL_FLAG_PCIE)) 2602 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2603 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2604 re_txeof(sc); 2605 2606 if (status & RL_ISR_SYSTEM_ERR) { 2607 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2608 re_init_locked(sc); 2609 } 2610 2611 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2612 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2613 re_start_locked(ifp); 2614 CSR_WRITE_2(sc, RL_IMR, intrs); 2615 } 2616 RL_UNLOCK(sc); 2617} 2618 2619static int 2620re_encap(struct rl_softc *sc, struct mbuf **m_head) 2621{ 2622 struct rl_txdesc *txd, *txd_last; 2623 bus_dma_segment_t segs[RL_NTXSEGS]; 2624 bus_dmamap_t map; 2625 struct mbuf *m_new; 2626 struct rl_desc *desc; 2627 int nsegs, prod; 2628 int i, error, ei, si; 2629 int padlen; 2630 uint32_t cmdstat, csum_flags, vlanctl; 2631 2632 RL_LOCK_ASSERT(sc); 2633 M_ASSERTPKTHDR((*m_head)); 2634 2635 /* 2636 * With some of the RealTek chips, using the checksum offload 2637 * support in conjunction with the autopadding feature results 2638 * in the transmission of corrupt frames. For example, if we 2639 * need to send a really small IP fragment that's less than 60 2640 * bytes in size, and IP header checksumming is enabled, the 2641 * resulting ethernet frame that appears on the wire will 2642 * have garbled payload. To work around this, if TX IP checksum 2643 * offload is enabled, we always manually pad short frames out 2644 * to the minimum ethernet frame size. 2645 */ 2646 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2647 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2648 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2649 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2650 if (M_WRITABLE(*m_head) == 0) { 2651 /* Get a writable copy. */ 2652 m_new = m_dup(*m_head, M_DONTWAIT); 2653 m_freem(*m_head); 2654 if (m_new == NULL) { 2655 *m_head = NULL; 2656 return (ENOBUFS); 2657 } 2658 *m_head = m_new; 2659 } 2660 if ((*m_head)->m_next != NULL || 2661 M_TRAILINGSPACE(*m_head) < padlen) { 2662 m_new = m_defrag(*m_head, M_DONTWAIT); 2663 if (m_new == NULL) { 2664 m_freem(*m_head); 2665 *m_head = NULL; 2666 return (ENOBUFS); 2667 } 2668 } else 2669 m_new = *m_head; 2670 2671 /* 2672 * Manually pad short frames, and zero the pad space 2673 * to avoid leaking data. 2674 */ 2675 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2676 m_new->m_pkthdr.len += padlen; 2677 m_new->m_len = m_new->m_pkthdr.len; 2678 *m_head = m_new; 2679 } 2680 2681 prod = sc->rl_ldata.rl_tx_prodidx; 2682 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2683 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2684 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2685 if (error == EFBIG) { 2686 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2687 if (m_new == NULL) { 2688 m_freem(*m_head); 2689 *m_head = NULL; 2690 return (ENOBUFS); 2691 } 2692 *m_head = m_new; 2693 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2694 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2695 if (error != 0) { 2696 m_freem(*m_head); 2697 *m_head = NULL; 2698 return (error); 2699 } 2700 } else if (error != 0) 2701 return (error); 2702 if (nsegs == 0) { 2703 m_freem(*m_head); 2704 *m_head = NULL; 2705 return (EIO); 2706 } 2707 2708 /* Check for number of available descriptors. */ 2709 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2710 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2711 return (ENOBUFS); 2712 } 2713 2714 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2715 BUS_DMASYNC_PREWRITE); 2716 2717 /* 2718 * Set up checksum offload. Note: checksum offload bits must 2719 * appear in all descriptors of a multi-descriptor transmit 2720 * attempt. This is according to testing done with an 8169 2721 * chip. This is a requirement. 2722 */ 2723 vlanctl = 0; 2724 csum_flags = 0; 2725 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2726 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2727 csum_flags |= RL_TDESC_CMD_LGSEND; 2728 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2729 RL_TDESC_CMD_MSSVALV2_SHIFT); 2730 } else { 2731 csum_flags |= RL_TDESC_CMD_LGSEND | 2732 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2733 RL_TDESC_CMD_MSSVAL_SHIFT); 2734 } 2735 } else { 2736 /* 2737 * Unconditionally enable IP checksum if TCP or UDP 2738 * checksum is required. Otherwise, TCP/UDP checksum 2739 * does't make effects. 2740 */ 2741 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2742 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2743 csum_flags |= RL_TDESC_CMD_IPCSUM; 2744 if (((*m_head)->m_pkthdr.csum_flags & 2745 CSUM_TCP) != 0) 2746 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2747 if (((*m_head)->m_pkthdr.csum_flags & 2748 CSUM_UDP) != 0) 2749 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2750 } else { 2751 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2752 if (((*m_head)->m_pkthdr.csum_flags & 2753 CSUM_TCP) != 0) 2754 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2755 if (((*m_head)->m_pkthdr.csum_flags & 2756 CSUM_UDP) != 0) 2757 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2758 } 2759 } 2760 } 2761 2762 /* 2763 * Set up hardware VLAN tagging. Note: vlan tag info must 2764 * appear in all descriptors of a multi-descriptor 2765 * transmission attempt. 2766 */ 2767 if ((*m_head)->m_flags & M_VLANTAG) 2768 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2769 RL_TDESC_VLANCTL_TAG; 2770 2771 si = prod; 2772 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2773 desc = &sc->rl_ldata.rl_tx_list[prod]; 2774 desc->rl_vlanctl = htole32(vlanctl); 2775 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2776 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2777 cmdstat = segs[i].ds_len; 2778 if (i != 0) 2779 cmdstat |= RL_TDESC_CMD_OWN; 2780 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2781 cmdstat |= RL_TDESC_CMD_EOR; 2782 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2783 sc->rl_ldata.rl_tx_free--; 2784 } 2785 /* Update producer index. */ 2786 sc->rl_ldata.rl_tx_prodidx = prod; 2787 2788 /* Set EOF on the last descriptor. */ 2789 ei = RL_TX_DESC_PRV(sc, prod); 2790 desc = &sc->rl_ldata.rl_tx_list[ei]; 2791 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2792 2793 desc = &sc->rl_ldata.rl_tx_list[si]; 2794 /* Set SOF and transfer ownership of packet to the chip. */ 2795 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2796 2797 /* 2798 * Insure that the map for this transmission 2799 * is placed at the array index of the last descriptor 2800 * in this chain. (Swap last and first dmamaps.) 2801 */ 2802 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2803 map = txd->tx_dmamap; 2804 txd->tx_dmamap = txd_last->tx_dmamap; 2805 txd_last->tx_dmamap = map; 2806 txd_last->tx_m = *m_head; 2807 2808 return (0); 2809} 2810 2811static void 2812re_start(struct ifnet *ifp) 2813{ 2814 struct rl_softc *sc; 2815 2816 sc = ifp->if_softc; 2817 RL_LOCK(sc); 2818 re_start_locked(ifp); 2819 RL_UNLOCK(sc); 2820} 2821 2822/* 2823 * Main transmit routine for C+ and gigE NICs. 2824 */ 2825static void 2826re_start_locked(struct ifnet *ifp) 2827{ 2828 struct rl_softc *sc; 2829 struct mbuf *m_head; 2830 int queued; 2831 2832 sc = ifp->if_softc; 2833 2834 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2835 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2836 return; 2837 2838 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2839 sc->rl_ldata.rl_tx_free > 1;) { 2840 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2841 if (m_head == NULL) 2842 break; 2843 2844 if (re_encap(sc, &m_head) != 0) { 2845 if (m_head == NULL) 2846 break; 2847 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2848 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2849 break; 2850 } 2851 2852 /* 2853 * If there's a BPF listener, bounce a copy of this frame 2854 * to him. 2855 */ 2856 ETHER_BPF_MTAP(ifp, m_head); 2857 2858 queued++; 2859 } 2860 2861 if (queued == 0) { 2862#ifdef RE_TX_MODERATION 2863 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2864 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2865#endif 2866 return; 2867 } 2868 2869 /* Flush the TX descriptors */ 2870 2871 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2872 sc->rl_ldata.rl_tx_list_map, 2873 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2874 2875 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2876 2877#ifdef RE_TX_MODERATION 2878 /* 2879 * Use the countdown timer for interrupt moderation. 2880 * 'TX done' interrupts are disabled. Instead, we reset the 2881 * countdown timer, which will begin counting until it hits 2882 * the value in the TIMERINT register, and then trigger an 2883 * interrupt. Each time we write to the TIMERCNT register, 2884 * the timer count is reset to 0. 2885 */ 2886 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2887#endif 2888 2889 /* 2890 * Set a timeout in case the chip goes out to lunch. 2891 */ 2892 sc->rl_watchdog_timer = 5; 2893} 2894 2895static void 2896re_set_jumbo(struct rl_softc *sc, int jumbo) 2897{ 2898 2899 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2900 pci_set_max_read_req(sc->rl_dev, 4096); 2901 return; 2902 } 2903 2904 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2905 if (jumbo != 0) { 2906 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) | 2907 RL_CFG3_JUMBO_EN0); 2908 switch (sc->rl_hwrev->rl_rev) { 2909 case RL_HWREV_8168DP: 2910 break; 2911 case RL_HWREV_8168E: 2912 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2913 0x01); 2914 break; 2915 default: 2916 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2917 RL_CFG4_JUMBO_EN1); 2918 } 2919 } else { 2920 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) & 2921 ~RL_CFG3_JUMBO_EN0); 2922 switch (sc->rl_hwrev->rl_rev) { 2923 case RL_HWREV_8168DP: 2924 break; 2925 case RL_HWREV_8168E: 2926 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2927 ~0x01); 2928 break; 2929 default: 2930 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2931 ~RL_CFG4_JUMBO_EN1); 2932 } 2933 } 2934 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2935 2936 switch (sc->rl_hwrev->rl_rev) { 2937 case RL_HWREV_8168DP: 2938 pci_set_max_read_req(sc->rl_dev, 4096); 2939 break; 2940 default: 2941 if (jumbo != 0) 2942 pci_set_max_read_req(sc->rl_dev, 512); 2943 else 2944 pci_set_max_read_req(sc->rl_dev, 4096); 2945 } 2946} 2947 2948static void 2949re_init(void *xsc) 2950{ 2951 struct rl_softc *sc = xsc; 2952 2953 RL_LOCK(sc); 2954 re_init_locked(sc); 2955 RL_UNLOCK(sc); 2956} 2957 2958static void 2959re_init_locked(struct rl_softc *sc) 2960{ 2961 struct ifnet *ifp = sc->rl_ifp; 2962 struct mii_data *mii; 2963 uint32_t reg; 2964 uint16_t cfg; 2965 union { 2966 uint32_t align_dummy; 2967 u_char eaddr[ETHER_ADDR_LEN]; 2968 } eaddr; 2969 2970 RL_LOCK_ASSERT(sc); 2971 2972 mii = device_get_softc(sc->rl_miibus); 2973 2974 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2975 return; 2976 2977 /* 2978 * Cancel pending I/O and free all RX/TX buffers. 2979 */ 2980 re_stop(sc); 2981 2982 /* Put controller into known state. */ 2983 re_reset(sc); 2984 2985 /* 2986 * For C+ mode, initialize the RX descriptors and mbufs. 2987 */ 2988 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 2989 if (ifp->if_mtu > RL_MTU) { 2990 if (re_jrx_list_init(sc) != 0) { 2991 device_printf(sc->rl_dev, 2992 "no memory for jumbo RX buffers\n"); 2993 re_stop(sc); 2994 return; 2995 } 2996 /* Disable checksum offloading for jumbo frames. */ 2997 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 2998 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 2999 } else { 3000 if (re_rx_list_init(sc) != 0) { 3001 device_printf(sc->rl_dev, 3002 "no memory for RX buffers\n"); 3003 re_stop(sc); 3004 return; 3005 } 3006 } 3007 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3008 } else { 3009 if (re_rx_list_init(sc) != 0) { 3010 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3011 re_stop(sc); 3012 return; 3013 } 3014 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3015 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3016 if (ifp->if_mtu > RL_MTU) 3017 pci_set_max_read_req(sc->rl_dev, 512); 3018 else 3019 pci_set_max_read_req(sc->rl_dev, 4096); 3020 } 3021 } 3022 re_tx_list_init(sc); 3023 3024 /* 3025 * Enable C+ RX and TX mode, as well as VLAN stripping and 3026 * RX checksum offload. We must configure the C+ register 3027 * before all others. 3028 */ 3029 cfg = RL_CPLUSCMD_PCI_MRW; 3030 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3031 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3032 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3033 cfg |= RL_CPLUSCMD_VLANSTRIP; 3034 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3035 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3036 /* XXX magic. */ 3037 cfg |= 0x0001; 3038 } else 3039 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3040 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3041 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3042 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3043 reg = 0x000fff00; 3044 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 3045 reg |= 0x000000ff; 3046 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3047 reg |= 0x00f00000; 3048 CSR_WRITE_4(sc, 0x7c, reg); 3049 /* Disable interrupt mitigation. */ 3050 CSR_WRITE_2(sc, 0xe2, 0); 3051 } 3052 /* 3053 * Disable TSO if interface MTU size is greater than MSS 3054 * allowed in controller. 3055 */ 3056 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3057 ifp->if_capenable &= ~IFCAP_TSO4; 3058 ifp->if_hwassist &= ~CSUM_TSO; 3059 } 3060 3061 /* 3062 * Init our MAC address. Even though the chipset 3063 * documentation doesn't mention it, we need to enter "Config 3064 * register write enable" mode to modify the ID registers. 3065 */ 3066 /* Copy MAC address on stack to align. */ 3067 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3068 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3069 CSR_WRITE_4(sc, RL_IDR0, 3070 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3071 CSR_WRITE_4(sc, RL_IDR4, 3072 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3073 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3074 3075 /* 3076 * Load the addresses of the RX and TX lists into the chip. 3077 */ 3078 3079 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3080 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3081 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3082 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3083 3084 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3085 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3086 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3087 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3088 3089 /* 3090 * Enable transmit and receive. 3091 */ 3092 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3093 3094 /* 3095 * Set the initial TX configuration. 3096 */ 3097 if (sc->rl_testmode) { 3098 if (sc->rl_type == RL_8169) 3099 CSR_WRITE_4(sc, RL_TXCFG, 3100 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3101 else 3102 CSR_WRITE_4(sc, RL_TXCFG, 3103 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3104 } else 3105 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3106 3107 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3108 3109 /* 3110 * Set the initial RX configuration. 3111 */ 3112 re_set_rxmode(sc); 3113 3114 /* Configure interrupt moderation. */ 3115 if (sc->rl_type == RL_8169) { 3116 /* Magic from vendor. */ 3117 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3118 } 3119 3120#ifdef DEVICE_POLLING 3121 /* 3122 * Disable interrupts if we are polling. 3123 */ 3124 if (ifp->if_capenable & IFCAP_POLLING) 3125 CSR_WRITE_2(sc, RL_IMR, 0); 3126 else /* otherwise ... */ 3127#endif 3128 3129 /* 3130 * Enable interrupts. 3131 */ 3132 if (sc->rl_testmode) 3133 CSR_WRITE_2(sc, RL_IMR, 0); 3134 else 3135 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3136 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3137 3138 /* Set initial TX threshold */ 3139 sc->rl_txthresh = RL_TX_THRESH_INIT; 3140 3141 /* Start RX/TX process. */ 3142 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3143#ifdef notdef 3144 /* Enable receiver and transmitter. */ 3145 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3146#endif 3147 3148 /* 3149 * Initialize the timer interrupt register so that 3150 * a timer interrupt will be generated once the timer 3151 * reaches a certain number of ticks. The timer is 3152 * reloaded on each transmit. 3153 */ 3154#ifdef RE_TX_MODERATION 3155 /* 3156 * Use timer interrupt register to moderate TX interrupt 3157 * moderation, which dramatically improves TX frame rate. 3158 */ 3159 if (sc->rl_type == RL_8169) 3160 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3161 else 3162 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3163#else 3164 /* 3165 * Use timer interrupt register to moderate RX interrupt 3166 * moderation. 3167 */ 3168 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3169 intr_filter == 0) { 3170 if (sc->rl_type == RL_8169) 3171 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3172 RL_USECS(sc->rl_int_rx_mod)); 3173 } else { 3174 if (sc->rl_type == RL_8169) 3175 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3176 } 3177#endif 3178 3179 /* 3180 * For 8169 gigE NICs, set the max allowed RX packet 3181 * size so we can receive jumbo frames. 3182 */ 3183 if (sc->rl_type == RL_8169) { 3184 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3185 /* 3186 * For controllers that use new jumbo frame scheme, 3187 * set maximum size of jumbo frame depedning on 3188 * controller revisions. 3189 */ 3190 if (ifp->if_mtu > RL_MTU) 3191 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3192 sc->rl_hwrev->rl_max_mtu + 3193 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3194 ETHER_CRC_LEN); 3195 else 3196 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3197 RE_RX_DESC_BUFLEN); 3198 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3199 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3200 /* RTL810x has no jumbo frame support. */ 3201 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3202 } else 3203 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3204 } 3205 3206 if (sc->rl_testmode) 3207 return; 3208 3209 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 3210 3211 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3212 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3213 3214 sc->rl_flags &= ~RL_FLAG_LINK; 3215 mii_mediachg(mii); 3216 3217 sc->rl_watchdog_timer = 0; 3218 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3219} 3220 3221/* 3222 * Set media options. 3223 */ 3224static int 3225re_ifmedia_upd(struct ifnet *ifp) 3226{ 3227 struct rl_softc *sc; 3228 struct mii_data *mii; 3229 int error; 3230 3231 sc = ifp->if_softc; 3232 mii = device_get_softc(sc->rl_miibus); 3233 RL_LOCK(sc); 3234 error = mii_mediachg(mii); 3235 RL_UNLOCK(sc); 3236 3237 return (error); 3238} 3239 3240/* 3241 * Report current media status. 3242 */ 3243static void 3244re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3245{ 3246 struct rl_softc *sc; 3247 struct mii_data *mii; 3248 3249 sc = ifp->if_softc; 3250 mii = device_get_softc(sc->rl_miibus); 3251 3252 RL_LOCK(sc); 3253 mii_pollstat(mii); 3254 ifmr->ifm_active = mii->mii_media_active; 3255 ifmr->ifm_status = mii->mii_media_status; 3256 RL_UNLOCK(sc); 3257} 3258 3259static int 3260re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3261{ 3262 struct rl_softc *sc = ifp->if_softc; 3263 struct ifreq *ifr = (struct ifreq *) data; 3264 struct mii_data *mii; 3265 uint32_t rev; 3266 int error = 0; 3267 3268 switch (command) { 3269 case SIOCSIFMTU: 3270 if (ifr->ifr_mtu < ETHERMIN || 3271 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) { 3272 error = EINVAL; 3273 break; 3274 } 3275 RL_LOCK(sc); 3276 if (ifp->if_mtu != ifr->ifr_mtu) { 3277 ifp->if_mtu = ifr->ifr_mtu; 3278 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3279 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3280 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3281 re_init_locked(sc); 3282 } 3283 if (ifp->if_mtu > RL_TSO_MTU && 3284 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3285 ifp->if_capenable &= ~(IFCAP_TSO4 | 3286 IFCAP_VLAN_HWTSO); 3287 ifp->if_hwassist &= ~CSUM_TSO; 3288 } 3289 VLAN_CAPABILITIES(ifp); 3290 } 3291 RL_UNLOCK(sc); 3292 break; 3293 case SIOCSIFFLAGS: 3294 RL_LOCK(sc); 3295 if ((ifp->if_flags & IFF_UP) != 0) { 3296 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3297 if (((ifp->if_flags ^ sc->rl_if_flags) 3298 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3299 re_set_rxmode(sc); 3300 } else 3301 re_init_locked(sc); 3302 } else { 3303 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3304 re_stop(sc); 3305 } 3306 sc->rl_if_flags = ifp->if_flags; 3307 RL_UNLOCK(sc); 3308 break; 3309 case SIOCADDMULTI: 3310 case SIOCDELMULTI: 3311 RL_LOCK(sc); 3312 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3313 re_set_rxmode(sc); 3314 RL_UNLOCK(sc); 3315 break; 3316 case SIOCGIFMEDIA: 3317 case SIOCSIFMEDIA: 3318 mii = device_get_softc(sc->rl_miibus); 3319 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3320 break; 3321 case SIOCSIFCAP: 3322 { 3323 int mask, reinit; 3324 3325 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3326 reinit = 0; 3327#ifdef DEVICE_POLLING 3328 if (mask & IFCAP_POLLING) { 3329 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3330 error = ether_poll_register(re_poll, ifp); 3331 if (error) 3332 return (error); 3333 RL_LOCK(sc); 3334 /* Disable interrupts */ 3335 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3336 ifp->if_capenable |= IFCAP_POLLING; 3337 RL_UNLOCK(sc); 3338 } else { 3339 error = ether_poll_deregister(ifp); 3340 /* Enable interrupts. */ 3341 RL_LOCK(sc); 3342 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3343 ifp->if_capenable &= ~IFCAP_POLLING; 3344 RL_UNLOCK(sc); 3345 } 3346 } 3347#endif /* DEVICE_POLLING */ 3348 RL_LOCK(sc); 3349 if ((mask & IFCAP_TXCSUM) != 0 && 3350 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3351 ifp->if_capenable ^= IFCAP_TXCSUM; 3352 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3353 rev = sc->rl_hwrev->rl_rev; 3354 if (rev == RL_HWREV_8168C || 3355 rev == RL_HWREV_8168C_SPIN2) 3356 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3357 else 3358 ifp->if_hwassist |= RE_CSUM_FEATURES; 3359 } else 3360 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3361 reinit = 1; 3362 } 3363 if ((mask & IFCAP_RXCSUM) != 0 && 3364 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3365 ifp->if_capenable ^= IFCAP_RXCSUM; 3366 reinit = 1; 3367 } 3368 if ((mask & IFCAP_TSO4) != 0 && 3369 (ifp->if_capabilities & IFCAP_TSO) != 0) { 3370 ifp->if_capenable ^= IFCAP_TSO4; 3371 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3372 ifp->if_hwassist |= CSUM_TSO; 3373 else 3374 ifp->if_hwassist &= ~CSUM_TSO; 3375 if (ifp->if_mtu > RL_TSO_MTU && 3376 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3377 ifp->if_capenable &= ~IFCAP_TSO4; 3378 ifp->if_hwassist &= ~CSUM_TSO; 3379 } 3380 } 3381 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3382 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3383 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3384 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3385 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3386 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3387 /* TSO over VLAN requires VLAN hardware tagging. */ 3388 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3389 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3390 reinit = 1; 3391 } 3392 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3393 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3394 IFCAP_VLAN_HWTSO)) != 0) 3395 reinit = 1; 3396 if ((mask & IFCAP_WOL) != 0 && 3397 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3398 if ((mask & IFCAP_WOL_UCAST) != 0) 3399 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3400 if ((mask & IFCAP_WOL_MCAST) != 0) 3401 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3402 if ((mask & IFCAP_WOL_MAGIC) != 0) 3403 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3404 } 3405 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3406 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3407 re_init_locked(sc); 3408 } 3409 RL_UNLOCK(sc); 3410 VLAN_CAPABILITIES(ifp); 3411 } 3412 break; 3413 default: 3414 error = ether_ioctl(ifp, command, data); 3415 break; 3416 } 3417 3418 return (error); 3419} 3420 3421static void 3422re_watchdog(struct rl_softc *sc) 3423{ 3424 struct ifnet *ifp; 3425 3426 RL_LOCK_ASSERT(sc); 3427 3428 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3429 return; 3430 3431 ifp = sc->rl_ifp; 3432 re_txeof(sc); 3433 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3434 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3435 "-- recovering\n"); 3436 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3437 re_start_locked(ifp); 3438 return; 3439 } 3440 3441 if_printf(ifp, "watchdog timeout\n"); 3442 ifp->if_oerrors++; 3443 3444 re_rxeof(sc, NULL); 3445 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3446 re_init_locked(sc); 3447 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3448 re_start_locked(ifp); 3449} 3450 3451/* 3452 * Stop the adapter and free any mbufs allocated to the 3453 * RX and TX lists. 3454 */ 3455static void 3456re_stop(struct rl_softc *sc) 3457{ 3458 int i; 3459 struct ifnet *ifp; 3460 struct rl_txdesc *txd; 3461 struct rl_rxdesc *rxd; 3462 3463 RL_LOCK_ASSERT(sc); 3464 3465 ifp = sc->rl_ifp; 3466 3467 sc->rl_watchdog_timer = 0; 3468 callout_stop(&sc->rl_stat_callout); 3469 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3470 3471 /* 3472 * Disable accepting frames to put RX MAC into idle state. 3473 * Otherwise it's possible to get frames while stop command 3474 * execution is in progress and controller can DMA the frame 3475 * to already freed RX buffer during that period. 3476 */ 3477 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3478 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3479 RL_RXCFG_RX_BROAD)); 3480 3481 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3482 for (i = RL_TIMEOUT; i > 0; i--) { 3483 if ((CSR_READ_1(sc, sc->rl_txstart) & 3484 RL_TXSTART_START) == 0) 3485 break; 3486 DELAY(20); 3487 } 3488 if (i == 0) 3489 device_printf(sc->rl_dev, 3490 "stopping TX poll timed out!\n"); 3491 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3492 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3493 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3494 RL_CMD_RX_ENB); 3495 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3496 for (i = RL_TIMEOUT; i > 0; i--) { 3497 if ((CSR_READ_4(sc, RL_TXCFG) & 3498 RL_TXCFG_QUEUE_EMPTY) != 0) 3499 break; 3500 DELAY(100); 3501 } 3502 if (i == 0) 3503 device_printf(sc->rl_dev, 3504 "stopping TXQ timed out!\n"); 3505 } 3506 } else 3507 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3508 DELAY(1000); 3509 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3510 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3511 3512 if (sc->rl_head != NULL) { 3513 m_freem(sc->rl_head); 3514 sc->rl_head = sc->rl_tail = NULL; 3515 } 3516 3517 /* Free the TX list buffers. */ 3518 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3519 txd = &sc->rl_ldata.rl_tx_desc[i]; 3520 if (txd->tx_m != NULL) { 3521 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3522 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3523 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3524 txd->tx_dmamap); 3525 m_freem(txd->tx_m); 3526 txd->tx_m = NULL; 3527 } 3528 } 3529 3530 /* Free the RX list buffers. */ 3531 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3532 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3533 if (rxd->rx_m != NULL) { 3534 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3535 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3536 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3537 rxd->rx_dmamap); 3538 m_freem(rxd->rx_m); 3539 rxd->rx_m = NULL; 3540 } 3541 } 3542 3543 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3544 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3545 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3546 if (rxd->rx_m != NULL) { 3547 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3548 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3549 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3550 rxd->rx_dmamap); 3551 m_freem(rxd->rx_m); 3552 rxd->rx_m = NULL; 3553 } 3554 } 3555 } 3556} 3557 3558/* 3559 * Device suspend routine. Stop the interface and save some PCI 3560 * settings in case the BIOS doesn't restore them properly on 3561 * resume. 3562 */ 3563static int 3564re_suspend(device_t dev) 3565{ 3566 struct rl_softc *sc; 3567 3568 sc = device_get_softc(dev); 3569 3570 RL_LOCK(sc); 3571 re_stop(sc); 3572 re_setwol(sc); 3573 sc->suspended = 1; 3574 RL_UNLOCK(sc); 3575 3576 return (0); 3577} 3578 3579/* 3580 * Device resume routine. Restore some PCI settings in case the BIOS 3581 * doesn't, re-enable busmastering, and restart the interface if 3582 * appropriate. 3583 */ 3584static int 3585re_resume(device_t dev) 3586{ 3587 struct rl_softc *sc; 3588 struct ifnet *ifp; 3589 3590 sc = device_get_softc(dev); 3591 3592 RL_LOCK(sc); 3593 3594 ifp = sc->rl_ifp; 3595 /* Take controller out of sleep mode. */ 3596 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3597 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3598 CSR_WRITE_1(sc, RL_GPIO, 3599 CSR_READ_1(sc, RL_GPIO) | 0x01); 3600 } 3601 3602 /* 3603 * Clear WOL matching such that normal Rx filtering 3604 * wouldn't interfere with WOL patterns. 3605 */ 3606 re_clrwol(sc); 3607 3608 /* reinitialize interface if necessary */ 3609 if (ifp->if_flags & IFF_UP) 3610 re_init_locked(sc); 3611 3612 sc->suspended = 0; 3613 RL_UNLOCK(sc); 3614 3615 return (0); 3616} 3617 3618/* 3619 * Stop all chip I/O so that the kernel's probe routines don't 3620 * get confused by errant DMAs when rebooting. 3621 */ 3622static int 3623re_shutdown(device_t dev) 3624{ 3625 struct rl_softc *sc; 3626 3627 sc = device_get_softc(dev); 3628 3629 RL_LOCK(sc); 3630 re_stop(sc); 3631 /* 3632 * Mark interface as down since otherwise we will panic if 3633 * interrupt comes in later on, which can happen in some 3634 * cases. 3635 */ 3636 sc->rl_ifp->if_flags &= ~IFF_UP; 3637 re_setwol(sc); 3638 RL_UNLOCK(sc); 3639 3640 return (0); 3641} 3642 3643static void 3644re_set_linkspeed(struct rl_softc *sc) 3645{ 3646 struct mii_softc *miisc; 3647 struct mii_data *mii; 3648 int aneg, i, phyno; 3649 3650 RL_LOCK_ASSERT(sc); 3651 3652 mii = device_get_softc(sc->rl_miibus); 3653 mii_pollstat(mii); 3654 aneg = 0; 3655 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3656 (IFM_ACTIVE | IFM_AVALID)) { 3657 switch IFM_SUBTYPE(mii->mii_media_active) { 3658 case IFM_10_T: 3659 case IFM_100_TX: 3660 return; 3661 case IFM_1000_T: 3662 aneg++; 3663 break; 3664 default: 3665 break; 3666 } 3667 } 3668 miisc = LIST_FIRST(&mii->mii_phys); 3669 phyno = miisc->mii_phy; 3670 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3671 PHY_RESET(miisc); 3672 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3673 re_miibus_writereg(sc->rl_dev, phyno, 3674 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3675 re_miibus_writereg(sc->rl_dev, phyno, 3676 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3677 DELAY(1000); 3678 if (aneg != 0) { 3679 /* 3680 * Poll link state until re(4) get a 10/100Mbps link. 3681 */ 3682 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3683 mii_pollstat(mii); 3684 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3685 == (IFM_ACTIVE | IFM_AVALID)) { 3686 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3687 case IFM_10_T: 3688 case IFM_100_TX: 3689 return; 3690 default: 3691 break; 3692 } 3693 } 3694 RL_UNLOCK(sc); 3695 pause("relnk", hz); 3696 RL_LOCK(sc); 3697 } 3698 if (i == MII_ANEGTICKS_GIGE) 3699 device_printf(sc->rl_dev, 3700 "establishing a link failed, WOL may not work!"); 3701 } 3702 /* 3703 * No link, force MAC to have 100Mbps, full-duplex link. 3704 * MAC does not require reprogramming on resolved speed/duplex, 3705 * so this is just for completeness. 3706 */ 3707 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3708 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3709} 3710 3711static void 3712re_setwol(struct rl_softc *sc) 3713{ 3714 struct ifnet *ifp; 3715 int pmc; 3716 uint16_t pmstat; 3717 uint8_t v; 3718 3719 RL_LOCK_ASSERT(sc); 3720 3721 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3722 return; 3723 3724 ifp = sc->rl_ifp; 3725 /* Put controller into sleep mode. */ 3726 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3727 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3728 CSR_WRITE_1(sc, RL_GPIO, 3729 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3730 } 3731 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3732 re_set_rxmode(sc); 3733 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3734 re_set_linkspeed(sc); 3735 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3736 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3737 } 3738 /* Enable config register write. */ 3739 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3740 3741 /* Enable PME. */ 3742 v = CSR_READ_1(sc, RL_CFG1); 3743 v &= ~RL_CFG1_PME; 3744 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3745 v |= RL_CFG1_PME; 3746 CSR_WRITE_1(sc, RL_CFG1, v); 3747 3748 v = CSR_READ_1(sc, RL_CFG3); 3749 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3750 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3751 v |= RL_CFG3_WOL_MAGIC; 3752 CSR_WRITE_1(sc, RL_CFG3, v); 3753 3754 v = CSR_READ_1(sc, RL_CFG5); 3755 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3756 RL_CFG5_WOL_LANWAKE); 3757 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3758 v |= RL_CFG5_WOL_UCAST; 3759 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3760 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3761 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3762 v |= RL_CFG5_WOL_LANWAKE; 3763 CSR_WRITE_1(sc, RL_CFG5, v); 3764 3765 /* Config register write done. */ 3766 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3767 3768 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3769 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3770 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3771 /* 3772 * It seems that hardware resets its link speed to 100Mbps in 3773 * power down mode so switching to 100Mbps in driver is not 3774 * needed. 3775 */ 3776 3777 /* Request PME if WOL is requested. */ 3778 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3779 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3780 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3781 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3782 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3783} 3784 3785static void 3786re_clrwol(struct rl_softc *sc) 3787{ 3788 int pmc; 3789 uint8_t v; 3790 3791 RL_LOCK_ASSERT(sc); 3792 3793 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3794 return; 3795 3796 /* Enable config register write. */ 3797 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3798 3799 v = CSR_READ_1(sc, RL_CFG3); 3800 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3801 CSR_WRITE_1(sc, RL_CFG3, v); 3802 3803 /* Config register write done. */ 3804 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3805 3806 v = CSR_READ_1(sc, RL_CFG5); 3807 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3808 v &= ~RL_CFG5_WOL_LANWAKE; 3809 CSR_WRITE_1(sc, RL_CFG5, v); 3810} 3811 3812static void 3813re_add_sysctls(struct rl_softc *sc) 3814{ 3815 struct sysctl_ctx_list *ctx; 3816 struct sysctl_oid_list *children; 3817 int error; 3818 3819 ctx = device_get_sysctl_ctx(sc->rl_dev); 3820 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3821 3822 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3823 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3824 "Statistics Information"); 3825 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3826 return; 3827 3828 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3829 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3830 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3831 /* Pull in device tunables. */ 3832 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3833 error = resource_int_value(device_get_name(sc->rl_dev), 3834 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3835 if (error == 0) { 3836 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3837 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3838 device_printf(sc->rl_dev, "int_rx_mod value out of " 3839 "range; using default: %d\n", 3840 RL_TIMER_DEFAULT); 3841 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3842 } 3843 } 3844 3845} 3846 3847static int 3848re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3849{ 3850 struct rl_softc *sc; 3851 struct rl_stats *stats; 3852 int error, i, result; 3853 3854 result = -1; 3855 error = sysctl_handle_int(oidp, &result, 0, req); 3856 if (error || req->newptr == NULL) 3857 return (error); 3858 3859 if (result == 1) { 3860 sc = (struct rl_softc *)arg1; 3861 RL_LOCK(sc); 3862 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3863 RL_UNLOCK(sc); 3864 goto done; 3865 } 3866 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3867 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3868 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3869 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3870 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3871 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3872 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3873 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3874 RL_DUMPSTATS_START)); 3875 for (i = RL_TIMEOUT; i > 0; i--) { 3876 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3877 RL_DUMPSTATS_START) == 0) 3878 break; 3879 DELAY(1000); 3880 } 3881 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3882 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3883 RL_UNLOCK(sc); 3884 if (i == 0) { 3885 device_printf(sc->rl_dev, 3886 "DUMP statistics request timedout\n"); 3887 return (ETIMEDOUT); 3888 } 3889done: 3890 stats = sc->rl_ldata.rl_stats; 3891 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3892 printf("Tx frames : %ju\n", 3893 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3894 printf("Rx frames : %ju\n", 3895 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3896 printf("Tx errors : %ju\n", 3897 (uintmax_t)le64toh(stats->rl_tx_errs)); 3898 printf("Rx errors : %u\n", 3899 le32toh(stats->rl_rx_errs)); 3900 printf("Rx missed frames : %u\n", 3901 (uint32_t)le16toh(stats->rl_missed_pkts)); 3902 printf("Rx frame alignment errs : %u\n", 3903 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3904 printf("Tx single collisions : %u\n", 3905 le32toh(stats->rl_tx_onecoll)); 3906 printf("Tx multiple collisions : %u\n", 3907 le32toh(stats->rl_tx_multicolls)); 3908 printf("Rx unicast frames : %ju\n", 3909 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3910 printf("Rx broadcast frames : %ju\n", 3911 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3912 printf("Rx multicast frames : %u\n", 3913 le32toh(stats->rl_rx_mcasts)); 3914 printf("Tx aborts : %u\n", 3915 (uint32_t)le16toh(stats->rl_tx_aborts)); 3916 printf("Tx underruns : %u\n", 3917 (uint32_t)le16toh(stats->rl_rx_underruns)); 3918 } 3919 3920 return (error); 3921} 3922 3923static int 3924sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3925{ 3926 int error, value; 3927 3928 if (arg1 == NULL) 3929 return (EINVAL); 3930 value = *(int *)arg1; 3931 error = sysctl_handle_int(oidp, &value, 0, req); 3932 if (error || req->newptr == NULL) 3933 return (error); 3934 if (value < low || value > high) 3935 return (EINVAL); 3936 *(int *)arg1 = value; 3937 3938 return (0); 3939} 3940 3941static int 3942sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 3943{ 3944 3945 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 3946 RL_TIMER_MAX)); 3947} 3948