if_re.c revision 229529
1251881Speter/*- 2251881Speter * Copyright (c) 1997, 1998-2003 3251881Speter * Bill Paul <wpaul@windriver.com>. All rights reserved. 4251881Speter * 5251881Speter * Redistribution and use in source and binary forms, with or without 6251881Speter * modification, are permitted provided that the following conditions 7251881Speter * are met: 8251881Speter * 1. Redistributions of source code must retain the above copyright 9251881Speter * notice, this list of conditions and the following disclaimer. 10251881Speter * 2. Redistributions in binary form must reproduce the above copyright 11251881Speter * notice, this list of conditions and the following disclaimer in the 12251881Speter * documentation and/or other materials provided with the distribution. 13251881Speter * 3. All advertising materials mentioning features or use of this software 14251881Speter * must display the following acknowledgement: 15251881Speter * This product includes software developed by Bill Paul. 16251881Speter * 4. Neither the name of the author nor the names of any co-contributors 17251881Speter * may be used to endorse or promote products derived from this software 18251881Speter * without specific prior written permission. 19251881Speter * 20251881Speter * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21251881Speter * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22251881Speter * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23251881Speter * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24251881Speter * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25251881Speter * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26251881Speter * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27251881Speter * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28251881Speter * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29251881Speter * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30251881Speter * THE POSSIBILITY OF SUCH DAMAGE. 31251881Speter */ 32251881Speter 33251881Speter#include <sys/cdefs.h> 34251881Speter__FBSDID("$FreeBSD: stable/9/sys/dev/re/if_re.c 229529 2012-01-04 22:53:18Z yongari $"); 35251881Speter 36251881Speter/* 37251881Speter * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38251881Speter * 39251881Speter * Written by Bill Paul <wpaul@windriver.com> 40251881Speter * Senior Networking Software Engineer 41251881Speter * Wind River Systems 42251881Speter */ 43251881Speter 44251881Speter/* 45251881Speter * This driver is designed to support RealTek's next generation of 46251881Speter * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47251881Speter * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/sysctl.h> 127#include <sys/taskqueue.h> 128 129#include <net/if.h> 130#include <net/if_arp.h> 131#include <net/ethernet.h> 132#include <net/if_dl.h> 133#include <net/if_media.h> 134#include <net/if_types.h> 135#include <net/if_vlan_var.h> 136 137#include <net/bpf.h> 138 139#include <machine/bus.h> 140#include <machine/resource.h> 141#include <sys/bus.h> 142#include <sys/rman.h> 143 144#include <dev/mii/mii.h> 145#include <dev/mii/miivar.h> 146 147#include <dev/pci/pcireg.h> 148#include <dev/pci/pcivar.h> 149 150#include <pci/if_rlreg.h> 151 152MODULE_DEPEND(re, pci, 1, 1, 1); 153MODULE_DEPEND(re, ether, 1, 1, 1); 154MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156/* "device miibus" required. See GENERIC if you get errors here. */ 157#include "miibus_if.h" 158 159/* Tunables. */ 160static int intr_filter = 0; 161TUNABLE_INT("hw.re.intr_filter", &intr_filter); 162static int msi_disable = 0; 163TUNABLE_INT("hw.re.msi_disable", &msi_disable); 164static int msix_disable = 0; 165TUNABLE_INT("hw.re.msix_disable", &msix_disable); 166static int prefer_iomap = 0; 167TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 168 169#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 171/* 172 * Various supported device vendors/types and their names. 173 */ 174static struct rl_type re_devs[] = { 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 179 { RT_VENDORID, RT_DEVICEID_8139, 0, 180 "RealTek 8139C+ 10/100BaseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8101E, 0, 182 "RealTek 810xE PCIe 10/100baseTX" }, 183 { RT_VENDORID, RT_DEVICEID_8168, 0, 184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, 0, 186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, 0, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 195}; 196 197static struct rl_hwrev re_hwrevs[] = { 198 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 227 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 228 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 229 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 230 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 232 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 233 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 234 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 235 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 237 { 0, 0, NULL, 0 } 238}; 239 240static int re_probe (device_t); 241static int re_attach (device_t); 242static int re_detach (device_t); 243 244static int re_encap (struct rl_softc *, struct mbuf **); 245 246static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 247static int re_allocmem (device_t, struct rl_softc *); 248static __inline void re_discard_rxbuf 249 (struct rl_softc *, int); 250static int re_newbuf (struct rl_softc *, int); 251static int re_jumbo_newbuf (struct rl_softc *, int); 252static int re_rx_list_init (struct rl_softc *); 253static int re_jrx_list_init (struct rl_softc *); 254static int re_tx_list_init (struct rl_softc *); 255#ifdef RE_FIXUP_RX 256static __inline void re_fixup_rx 257 (struct mbuf *); 258#endif 259static int re_rxeof (struct rl_softc *, int *); 260static void re_txeof (struct rl_softc *); 261#ifdef DEVICE_POLLING 262static int re_poll (struct ifnet *, enum poll_cmd, int); 263static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 264#endif 265static int re_intr (void *); 266static void re_intr_msi (void *); 267static void re_tick (void *); 268static void re_int_task (void *, int); 269static void re_start (struct ifnet *); 270static void re_start_locked (struct ifnet *); 271static int re_ioctl (struct ifnet *, u_long, caddr_t); 272static void re_init (void *); 273static void re_init_locked (struct rl_softc *); 274static void re_stop (struct rl_softc *); 275static void re_watchdog (struct rl_softc *); 276static int re_suspend (device_t); 277static int re_resume (device_t); 278static int re_shutdown (device_t); 279static int re_ifmedia_upd (struct ifnet *); 280static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 281 282static void re_eeprom_putbyte (struct rl_softc *, int); 283static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 284static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 285static int re_gmii_readreg (device_t, int, int); 286static int re_gmii_writereg (device_t, int, int, int); 287 288static int re_miibus_readreg (device_t, int, int); 289static int re_miibus_writereg (device_t, int, int, int); 290static void re_miibus_statchg (device_t); 291 292static void re_set_jumbo (struct rl_softc *, int); 293static void re_set_rxmode (struct rl_softc *); 294static void re_reset (struct rl_softc *); 295static void re_setwol (struct rl_softc *); 296static void re_clrwol (struct rl_softc *); 297 298#ifdef RE_DIAG 299static int re_diag (struct rl_softc *); 300#endif 301 302static void re_add_sysctls (struct rl_softc *); 303static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 304static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 305static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 306 307static device_method_t re_methods[] = { 308 /* Device interface */ 309 DEVMETHOD(device_probe, re_probe), 310 DEVMETHOD(device_attach, re_attach), 311 DEVMETHOD(device_detach, re_detach), 312 DEVMETHOD(device_suspend, re_suspend), 313 DEVMETHOD(device_resume, re_resume), 314 DEVMETHOD(device_shutdown, re_shutdown), 315 316 /* MII interface */ 317 DEVMETHOD(miibus_readreg, re_miibus_readreg), 318 DEVMETHOD(miibus_writereg, re_miibus_writereg), 319 DEVMETHOD(miibus_statchg, re_miibus_statchg), 320 321 DEVMETHOD_END 322}; 323 324static driver_t re_driver = { 325 "re", 326 re_methods, 327 sizeof(struct rl_softc) 328}; 329 330static devclass_t re_devclass; 331 332DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 333DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 334 335#define EE_SET(x) \ 336 CSR_WRITE_1(sc, RL_EECMD, \ 337 CSR_READ_1(sc, RL_EECMD) | x) 338 339#define EE_CLR(x) \ 340 CSR_WRITE_1(sc, RL_EECMD, \ 341 CSR_READ_1(sc, RL_EECMD) & ~x) 342 343/* 344 * Send a read command and address to the EEPROM, check for ACK. 345 */ 346static void 347re_eeprom_putbyte(struct rl_softc *sc, int addr) 348{ 349 int d, i; 350 351 d = addr | (RL_9346_READ << sc->rl_eewidth); 352 353 /* 354 * Feed in each bit and strobe the clock. 355 */ 356 357 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 358 if (d & i) { 359 EE_SET(RL_EE_DATAIN); 360 } else { 361 EE_CLR(RL_EE_DATAIN); 362 } 363 DELAY(100); 364 EE_SET(RL_EE_CLK); 365 DELAY(150); 366 EE_CLR(RL_EE_CLK); 367 DELAY(100); 368 } 369} 370 371/* 372 * Read a word of data stored in the EEPROM at address 'addr.' 373 */ 374static void 375re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 376{ 377 int i; 378 u_int16_t word = 0; 379 380 /* 381 * Send address of word we want to read. 382 */ 383 re_eeprom_putbyte(sc, addr); 384 385 /* 386 * Start reading bits from EEPROM. 387 */ 388 for (i = 0x8000; i; i >>= 1) { 389 EE_SET(RL_EE_CLK); 390 DELAY(100); 391 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 392 word |= i; 393 EE_CLR(RL_EE_CLK); 394 DELAY(100); 395 } 396 397 *dest = word; 398} 399 400/* 401 * Read a sequence of words from the EEPROM. 402 */ 403static void 404re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 405{ 406 int i; 407 u_int16_t word = 0, *ptr; 408 409 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 410 411 DELAY(100); 412 413 for (i = 0; i < cnt; i++) { 414 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 415 re_eeprom_getword(sc, off + i, &word); 416 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 417 ptr = (u_int16_t *)(dest + (i * 2)); 418 *ptr = word; 419 } 420 421 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 422} 423 424static int 425re_gmii_readreg(device_t dev, int phy, int reg) 426{ 427 struct rl_softc *sc; 428 u_int32_t rval; 429 int i; 430 431 sc = device_get_softc(dev); 432 433 /* Let the rgephy driver read the GMEDIASTAT register */ 434 435 if (reg == RL_GMEDIASTAT) { 436 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 437 return (rval); 438 } 439 440 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 441 442 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 443 rval = CSR_READ_4(sc, RL_PHYAR); 444 if (rval & RL_PHYAR_BUSY) 445 break; 446 DELAY(25); 447 } 448 449 if (i == RL_PHY_TIMEOUT) { 450 device_printf(sc->rl_dev, "PHY read failed\n"); 451 return (0); 452 } 453 454 /* 455 * Controller requires a 20us delay to process next MDIO request. 456 */ 457 DELAY(20); 458 459 return (rval & RL_PHYAR_PHYDATA); 460} 461 462static int 463re_gmii_writereg(device_t dev, int phy, int reg, int data) 464{ 465 struct rl_softc *sc; 466 u_int32_t rval; 467 int i; 468 469 sc = device_get_softc(dev); 470 471 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 472 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 473 474 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 475 rval = CSR_READ_4(sc, RL_PHYAR); 476 if (!(rval & RL_PHYAR_BUSY)) 477 break; 478 DELAY(25); 479 } 480 481 if (i == RL_PHY_TIMEOUT) { 482 device_printf(sc->rl_dev, "PHY write failed\n"); 483 return (0); 484 } 485 486 /* 487 * Controller requires a 20us delay to process next MDIO request. 488 */ 489 DELAY(20); 490 491 return (0); 492} 493 494static int 495re_miibus_readreg(device_t dev, int phy, int reg) 496{ 497 struct rl_softc *sc; 498 u_int16_t rval = 0; 499 u_int16_t re8139_reg = 0; 500 501 sc = device_get_softc(dev); 502 503 if (sc->rl_type == RL_8169) { 504 rval = re_gmii_readreg(dev, phy, reg); 505 return (rval); 506 } 507 508 switch (reg) { 509 case MII_BMCR: 510 re8139_reg = RL_BMCR; 511 break; 512 case MII_BMSR: 513 re8139_reg = RL_BMSR; 514 break; 515 case MII_ANAR: 516 re8139_reg = RL_ANAR; 517 break; 518 case MII_ANER: 519 re8139_reg = RL_ANER; 520 break; 521 case MII_ANLPAR: 522 re8139_reg = RL_LPAR; 523 break; 524 case MII_PHYIDR1: 525 case MII_PHYIDR2: 526 return (0); 527 /* 528 * Allow the rlphy driver to read the media status 529 * register. If we have a link partner which does not 530 * support NWAY, this is the register which will tell 531 * us the results of parallel detection. 532 */ 533 case RL_MEDIASTAT: 534 rval = CSR_READ_1(sc, RL_MEDIASTAT); 535 return (rval); 536 default: 537 device_printf(sc->rl_dev, "bad phy register\n"); 538 return (0); 539 } 540 rval = CSR_READ_2(sc, re8139_reg); 541 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 542 /* 8139C+ has different bit layout. */ 543 rval &= ~(BMCR_LOOP | BMCR_ISO); 544 } 545 return (rval); 546} 547 548static int 549re_miibus_writereg(device_t dev, int phy, int reg, int data) 550{ 551 struct rl_softc *sc; 552 u_int16_t re8139_reg = 0; 553 int rval = 0; 554 555 sc = device_get_softc(dev); 556 557 if (sc->rl_type == RL_8169) { 558 rval = re_gmii_writereg(dev, phy, reg, data); 559 return (rval); 560 } 561 562 switch (reg) { 563 case MII_BMCR: 564 re8139_reg = RL_BMCR; 565 if (sc->rl_type == RL_8139CPLUS) { 566 /* 8139C+ has different bit layout. */ 567 data &= ~(BMCR_LOOP | BMCR_ISO); 568 } 569 break; 570 case MII_BMSR: 571 re8139_reg = RL_BMSR; 572 break; 573 case MII_ANAR: 574 re8139_reg = RL_ANAR; 575 break; 576 case MII_ANER: 577 re8139_reg = RL_ANER; 578 break; 579 case MII_ANLPAR: 580 re8139_reg = RL_LPAR; 581 break; 582 case MII_PHYIDR1: 583 case MII_PHYIDR2: 584 return (0); 585 break; 586 default: 587 device_printf(sc->rl_dev, "bad phy register\n"); 588 return (0); 589 } 590 CSR_WRITE_2(sc, re8139_reg, data); 591 return (0); 592} 593 594static void 595re_miibus_statchg(device_t dev) 596{ 597 struct rl_softc *sc; 598 struct ifnet *ifp; 599 struct mii_data *mii; 600 601 sc = device_get_softc(dev); 602 mii = device_get_softc(sc->rl_miibus); 603 ifp = sc->rl_ifp; 604 if (mii == NULL || ifp == NULL || 605 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 606 return; 607 608 sc->rl_flags &= ~RL_FLAG_LINK; 609 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 610 (IFM_ACTIVE | IFM_AVALID)) { 611 switch (IFM_SUBTYPE(mii->mii_media_active)) { 612 case IFM_10_T: 613 case IFM_100_TX: 614 sc->rl_flags |= RL_FLAG_LINK; 615 break; 616 case IFM_1000_T: 617 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 618 break; 619 sc->rl_flags |= RL_FLAG_LINK; 620 break; 621 default: 622 break; 623 } 624 } 625 /* 626 * RealTek controllers does not provide any interface to 627 * Tx/Rx MACs for resolved speed, duplex and flow-control 628 * parameters. 629 */ 630} 631 632/* 633 * Set the RX configuration and 64-bit multicast hash filter. 634 */ 635static void 636re_set_rxmode(struct rl_softc *sc) 637{ 638 struct ifnet *ifp; 639 struct ifmultiaddr *ifma; 640 uint32_t hashes[2] = { 0, 0 }; 641 uint32_t h, rxfilt; 642 643 RL_LOCK_ASSERT(sc); 644 645 ifp = sc->rl_ifp; 646 647 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 648 649 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 650 if (ifp->if_flags & IFF_PROMISC) 651 rxfilt |= RL_RXCFG_RX_ALLPHYS; 652 /* 653 * Unlike other hardwares, we have to explicitly set 654 * RL_RXCFG_RX_MULTI to receive multicast frames in 655 * promiscuous mode. 656 */ 657 rxfilt |= RL_RXCFG_RX_MULTI; 658 hashes[0] = hashes[1] = 0xffffffff; 659 goto done; 660 } 661 662 if_maddr_rlock(ifp); 663 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 664 if (ifma->ifma_addr->sa_family != AF_LINK) 665 continue; 666 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 667 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 668 if (h < 32) 669 hashes[0] |= (1 << h); 670 else 671 hashes[1] |= (1 << (h - 32)); 672 } 673 if_maddr_runlock(ifp); 674 675 if (hashes[0] != 0 || hashes[1] != 0) { 676 /* 677 * For some unfathomable reason, RealTek decided to 678 * reverse the order of the multicast hash registers 679 * in the PCI Express parts. This means we have to 680 * write the hash pattern in reverse order for those 681 * devices. 682 */ 683 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 684 h = bswap32(hashes[0]); 685 hashes[0] = bswap32(hashes[1]); 686 hashes[1] = h; 687 } 688 rxfilt |= RL_RXCFG_RX_MULTI; 689 } 690 691done: 692 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 693 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 694 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 695} 696 697static void 698re_reset(struct rl_softc *sc) 699{ 700 int i; 701 702 RL_LOCK_ASSERT(sc); 703 704 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 705 706 for (i = 0; i < RL_TIMEOUT; i++) { 707 DELAY(10); 708 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 709 break; 710 } 711 if (i == RL_TIMEOUT) 712 device_printf(sc->rl_dev, "reset never completed!\n"); 713 714 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 715 CSR_WRITE_1(sc, 0x82, 1); 716 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 717 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 718} 719 720#ifdef RE_DIAG 721 722/* 723 * The following routine is designed to test for a defect on some 724 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 725 * lines connected to the bus, however for a 32-bit only card, they 726 * should be pulled high. The result of this defect is that the 727 * NIC will not work right if you plug it into a 64-bit slot: DMA 728 * operations will be done with 64-bit transfers, which will fail 729 * because the 64-bit data lines aren't connected. 730 * 731 * There's no way to work around this (short of talking a soldering 732 * iron to the board), however we can detect it. The method we use 733 * here is to put the NIC into digital loopback mode, set the receiver 734 * to promiscuous mode, and then try to send a frame. We then compare 735 * the frame data we sent to what was received. If the data matches, 736 * then the NIC is working correctly, otherwise we know the user has 737 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 738 * slot. In the latter case, there's no way the NIC can work correctly, 739 * so we print out a message on the console and abort the device attach. 740 */ 741 742static int 743re_diag(struct rl_softc *sc) 744{ 745 struct ifnet *ifp = sc->rl_ifp; 746 struct mbuf *m0; 747 struct ether_header *eh; 748 struct rl_desc *cur_rx; 749 u_int16_t status; 750 u_int32_t rxstat; 751 int total_len, i, error = 0, phyaddr; 752 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 753 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 754 755 /* Allocate a single mbuf */ 756 MGETHDR(m0, M_DONTWAIT, MT_DATA); 757 if (m0 == NULL) 758 return (ENOBUFS); 759 760 RL_LOCK(sc); 761 762 /* 763 * Initialize the NIC in test mode. This sets the chip up 764 * so that it can send and receive frames, but performs the 765 * following special functions: 766 * - Puts receiver in promiscuous mode 767 * - Enables digital loopback mode 768 * - Leaves interrupts turned off 769 */ 770 771 ifp->if_flags |= IFF_PROMISC; 772 sc->rl_testmode = 1; 773 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 774 re_init_locked(sc); 775 sc->rl_flags |= RL_FLAG_LINK; 776 if (sc->rl_type == RL_8169) 777 phyaddr = 1; 778 else 779 phyaddr = 0; 780 781 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 782 for (i = 0; i < RL_TIMEOUT; i++) { 783 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 784 if (!(status & BMCR_RESET)) 785 break; 786 } 787 788 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 789 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 790 791 DELAY(100000); 792 793 /* Put some data in the mbuf */ 794 795 eh = mtod(m0, struct ether_header *); 796 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 797 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 798 eh->ether_type = htons(ETHERTYPE_IP); 799 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 800 801 /* 802 * Queue the packet, start transmission. 803 * Note: IF_HANDOFF() ultimately calls re_start() for us. 804 */ 805 806 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 807 RL_UNLOCK(sc); 808 /* XXX: re_diag must not be called when in ALTQ mode */ 809 IF_HANDOFF(&ifp->if_snd, m0, ifp); 810 RL_LOCK(sc); 811 m0 = NULL; 812 813 /* Wait for it to propagate through the chip */ 814 815 DELAY(100000); 816 for (i = 0; i < RL_TIMEOUT; i++) { 817 status = CSR_READ_2(sc, RL_ISR); 818 CSR_WRITE_2(sc, RL_ISR, status); 819 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 820 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 821 break; 822 DELAY(10); 823 } 824 825 if (i == RL_TIMEOUT) { 826 device_printf(sc->rl_dev, 827 "diagnostic failed, failed to receive packet in" 828 " loopback mode\n"); 829 error = EIO; 830 goto done; 831 } 832 833 /* 834 * The packet should have been dumped into the first 835 * entry in the RX DMA ring. Grab it from there. 836 */ 837 838 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 839 sc->rl_ldata.rl_rx_list_map, 840 BUS_DMASYNC_POSTREAD); 841 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 842 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 843 BUS_DMASYNC_POSTREAD); 844 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 845 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 846 847 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 848 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 849 eh = mtod(m0, struct ether_header *); 850 851 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 852 total_len = RL_RXBYTES(cur_rx); 853 rxstat = le32toh(cur_rx->rl_cmdstat); 854 855 if (total_len != ETHER_MIN_LEN) { 856 device_printf(sc->rl_dev, 857 "diagnostic failed, received short packet\n"); 858 error = EIO; 859 goto done; 860 } 861 862 /* Test that the received packet data matches what we sent. */ 863 864 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 865 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 866 ntohs(eh->ether_type) != ETHERTYPE_IP) { 867 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 868 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 869 dst, ":", src, ":", ETHERTYPE_IP); 870 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 871 eh->ether_dhost, ":", eh->ether_shost, ":", 872 ntohs(eh->ether_type)); 873 device_printf(sc->rl_dev, "You may have a defective 32-bit " 874 "NIC plugged into a 64-bit PCI slot.\n"); 875 device_printf(sc->rl_dev, "Please re-install the NIC in a " 876 "32-bit slot for proper operation.\n"); 877 device_printf(sc->rl_dev, "Read the re(4) man page for more " 878 "details.\n"); 879 error = EIO; 880 } 881 882done: 883 /* Turn interface off, release resources */ 884 885 sc->rl_testmode = 0; 886 sc->rl_flags &= ~RL_FLAG_LINK; 887 ifp->if_flags &= ~IFF_PROMISC; 888 re_stop(sc); 889 if (m0 != NULL) 890 m_freem(m0); 891 892 RL_UNLOCK(sc); 893 894 return (error); 895} 896 897#endif 898 899/* 900 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 901 * IDs against our list and return a device name if we find a match. 902 */ 903static int 904re_probe(device_t dev) 905{ 906 struct rl_type *t; 907 uint16_t devid, vendor; 908 uint16_t revid, sdevid; 909 int i; 910 911 vendor = pci_get_vendor(dev); 912 devid = pci_get_device(dev); 913 revid = pci_get_revid(dev); 914 sdevid = pci_get_subdevice(dev); 915 916 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 917 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 918 /* 919 * Only attach to rev. 3 of the Linksys EG1032 adapter. 920 * Rev. 2 is supported by sk(4). 921 */ 922 return (ENXIO); 923 } 924 } 925 926 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 927 if (revid != 0x20) { 928 /* 8139, let rl(4) take care of this device. */ 929 return (ENXIO); 930 } 931 } 932 933 t = re_devs; 934 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 935 if (vendor == t->rl_vid && devid == t->rl_did) { 936 device_set_desc(dev, t->rl_name); 937 return (BUS_PROBE_DEFAULT); 938 } 939 } 940 941 return (ENXIO); 942} 943 944/* 945 * Map a single buffer address. 946 */ 947 948static void 949re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 950{ 951 bus_addr_t *addr; 952 953 if (error) 954 return; 955 956 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 957 addr = arg; 958 *addr = segs->ds_addr; 959} 960 961static int 962re_allocmem(device_t dev, struct rl_softc *sc) 963{ 964 bus_addr_t lowaddr; 965 bus_size_t rx_list_size, tx_list_size; 966 int error; 967 int i; 968 969 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 970 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 971 972 /* 973 * Allocate the parent bus DMA tag appropriate for PCI. 974 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 975 * register should be set. However some RealTek chips are known 976 * to be buggy on DAC handling, therefore disable DAC by limiting 977 * DMA address space to 32bit. PCIe variants of RealTek chips 978 * may not have the limitation. 979 */ 980 lowaddr = BUS_SPACE_MAXADDR; 981 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 982 lowaddr = BUS_SPACE_MAXADDR_32BIT; 983 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 984 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 985 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 986 NULL, NULL, &sc->rl_parent_tag); 987 if (error) { 988 device_printf(dev, "could not allocate parent DMA tag\n"); 989 return (error); 990 } 991 992 /* 993 * Allocate map for TX mbufs. 994 */ 995 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 996 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 997 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 998 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 999 if (error) { 1000 device_printf(dev, "could not allocate TX DMA tag\n"); 1001 return (error); 1002 } 1003 1004 /* 1005 * Allocate map for RX mbufs. 1006 */ 1007 1008 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1009 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1010 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1011 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1012 &sc->rl_ldata.rl_jrx_mtag); 1013 if (error) { 1014 device_printf(dev, 1015 "could not allocate jumbo RX DMA tag\n"); 1016 return (error); 1017 } 1018 } 1019 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1020 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1021 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1022 if (error) { 1023 device_printf(dev, "could not allocate RX DMA tag\n"); 1024 return (error); 1025 } 1026 1027 /* 1028 * Allocate map for TX descriptor list. 1029 */ 1030 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1031 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1032 NULL, tx_list_size, 1, tx_list_size, 0, 1033 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1034 if (error) { 1035 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1036 return (error); 1037 } 1038 1039 /* Allocate DMA'able memory for the TX ring */ 1040 1041 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1042 (void **)&sc->rl_ldata.rl_tx_list, 1043 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1044 &sc->rl_ldata.rl_tx_list_map); 1045 if (error) { 1046 device_printf(dev, "could not allocate TX DMA ring\n"); 1047 return (error); 1048 } 1049 1050 /* Load the map for the TX ring. */ 1051 1052 sc->rl_ldata.rl_tx_list_addr = 0; 1053 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1054 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1055 tx_list_size, re_dma_map_addr, 1056 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1057 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1058 device_printf(dev, "could not load TX DMA ring\n"); 1059 return (ENOMEM); 1060 } 1061 1062 /* Create DMA maps for TX buffers */ 1063 1064 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1065 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1066 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1067 if (error) { 1068 device_printf(dev, "could not create DMA map for TX\n"); 1069 return (error); 1070 } 1071 } 1072 1073 /* 1074 * Allocate map for RX descriptor list. 1075 */ 1076 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1077 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1078 NULL, rx_list_size, 1, rx_list_size, 0, 1079 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1080 if (error) { 1081 device_printf(dev, "could not create RX DMA ring tag\n"); 1082 return (error); 1083 } 1084 1085 /* Allocate DMA'able memory for the RX ring */ 1086 1087 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1088 (void **)&sc->rl_ldata.rl_rx_list, 1089 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1090 &sc->rl_ldata.rl_rx_list_map); 1091 if (error) { 1092 device_printf(dev, "could not allocate RX DMA ring\n"); 1093 return (error); 1094 } 1095 1096 /* Load the map for the RX ring. */ 1097 1098 sc->rl_ldata.rl_rx_list_addr = 0; 1099 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1100 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1101 rx_list_size, re_dma_map_addr, 1102 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1103 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1104 device_printf(dev, "could not load RX DMA ring\n"); 1105 return (ENOMEM); 1106 } 1107 1108 /* Create DMA maps for RX buffers */ 1109 1110 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1111 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1112 &sc->rl_ldata.rl_jrx_sparemap); 1113 if (error) { 1114 device_printf(dev, 1115 "could not create spare DMA map for jumbo RX\n"); 1116 return (error); 1117 } 1118 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1119 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1120 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1121 if (error) { 1122 device_printf(dev, 1123 "could not create DMA map for jumbo RX\n"); 1124 return (error); 1125 } 1126 } 1127 } 1128 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1129 &sc->rl_ldata.rl_rx_sparemap); 1130 if (error) { 1131 device_printf(dev, "could not create spare DMA map for RX\n"); 1132 return (error); 1133 } 1134 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1135 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1136 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1137 if (error) { 1138 device_printf(dev, "could not create DMA map for RX\n"); 1139 return (error); 1140 } 1141 } 1142 1143 /* Create DMA map for statistics. */ 1144 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1145 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1146 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1147 &sc->rl_ldata.rl_stag); 1148 if (error) { 1149 device_printf(dev, "could not create statistics DMA tag\n"); 1150 return (error); 1151 } 1152 /* Allocate DMA'able memory for statistics. */ 1153 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1154 (void **)&sc->rl_ldata.rl_stats, 1155 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1156 &sc->rl_ldata.rl_smap); 1157 if (error) { 1158 device_printf(dev, 1159 "could not allocate statistics DMA memory\n"); 1160 return (error); 1161 } 1162 /* Load the map for statistics. */ 1163 sc->rl_ldata.rl_stats_addr = 0; 1164 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1165 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1166 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1167 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1168 device_printf(dev, "could not load statistics DMA memory\n"); 1169 return (ENOMEM); 1170 } 1171 1172 return (0); 1173} 1174 1175/* 1176 * Attach the interface. Allocate softc structures, do ifmedia 1177 * setup and ethernet/BPF attach. 1178 */ 1179static int 1180re_attach(device_t dev) 1181{ 1182 u_char eaddr[ETHER_ADDR_LEN]; 1183 u_int16_t as[ETHER_ADDR_LEN / 2]; 1184 struct rl_softc *sc; 1185 struct ifnet *ifp; 1186 struct rl_hwrev *hw_rev; 1187 u_int32_t cap, ctl; 1188 int hwrev; 1189 u_int16_t devid, re_did = 0; 1190 int error = 0, i, phy, rid; 1191 int msic, msixc, reg; 1192 uint8_t cfg; 1193 1194 sc = device_get_softc(dev); 1195 sc->rl_dev = dev; 1196 1197 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1198 MTX_DEF); 1199 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1200 1201 /* 1202 * Map control/status registers. 1203 */ 1204 pci_enable_busmaster(dev); 1205 1206 devid = pci_get_device(dev); 1207 /* 1208 * Prefer memory space register mapping over IO space. 1209 * Because RTL8169SC does not seem to work when memory mapping 1210 * is used always activate io mapping. 1211 */ 1212 if (devid == RT_DEVICEID_8169SC) 1213 prefer_iomap = 1; 1214 if (prefer_iomap == 0) { 1215 sc->rl_res_id = PCIR_BAR(1); 1216 sc->rl_res_type = SYS_RES_MEMORY; 1217 /* RTL8168/8101E seems to use different BARs. */ 1218 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1219 sc->rl_res_id = PCIR_BAR(2); 1220 } else { 1221 sc->rl_res_id = PCIR_BAR(0); 1222 sc->rl_res_type = SYS_RES_IOPORT; 1223 } 1224 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1225 &sc->rl_res_id, RF_ACTIVE); 1226 if (sc->rl_res == NULL && prefer_iomap == 0) { 1227 sc->rl_res_id = PCIR_BAR(0); 1228 sc->rl_res_type = SYS_RES_IOPORT; 1229 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1230 &sc->rl_res_id, RF_ACTIVE); 1231 } 1232 if (sc->rl_res == NULL) { 1233 device_printf(dev, "couldn't map ports/memory\n"); 1234 error = ENXIO; 1235 goto fail; 1236 } 1237 1238 sc->rl_btag = rman_get_bustag(sc->rl_res); 1239 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1240 1241 msic = pci_msi_count(dev); 1242 msixc = pci_msix_count(dev); 1243 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1244 sc->rl_flags |= RL_FLAG_PCIE; 1245 sc->rl_expcap = reg; 1246 } 1247 if (bootverbose) { 1248 device_printf(dev, "MSI count : %d\n", msic); 1249 device_printf(dev, "MSI-X count : %d\n", msixc); 1250 } 1251 if (msix_disable > 0) 1252 msixc = 0; 1253 if (msi_disable > 0) 1254 msic = 0; 1255 /* Prefer MSI-X to MSI. */ 1256 if (msixc > 0) { 1257 msixc = 1; 1258 rid = PCIR_BAR(4); 1259 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1260 &rid, RF_ACTIVE); 1261 if (sc->rl_res_pba == NULL) { 1262 device_printf(sc->rl_dev, 1263 "could not allocate MSI-X PBA resource\n"); 1264 } 1265 if (sc->rl_res_pba != NULL && 1266 pci_alloc_msix(dev, &msixc) == 0) { 1267 if (msixc == 1) { 1268 device_printf(dev, "Using %d MSI-X message\n", 1269 msixc); 1270 sc->rl_flags |= RL_FLAG_MSIX; 1271 } else 1272 pci_release_msi(dev); 1273 } 1274 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1275 if (sc->rl_res_pba != NULL) 1276 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1277 sc->rl_res_pba); 1278 sc->rl_res_pba = NULL; 1279 msixc = 0; 1280 } 1281 } 1282 /* Prefer MSI to INTx. */ 1283 if (msixc == 0 && msic > 0) { 1284 msic = 1; 1285 if (pci_alloc_msi(dev, &msic) == 0) { 1286 if (msic == RL_MSI_MESSAGES) { 1287 device_printf(dev, "Using %d MSI message\n", 1288 msic); 1289 sc->rl_flags |= RL_FLAG_MSI; 1290 /* Explicitly set MSI enable bit. */ 1291 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1292 cfg = CSR_READ_1(sc, RL_CFG2); 1293 cfg |= RL_CFG2_MSI; 1294 CSR_WRITE_1(sc, RL_CFG2, cfg); 1295 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1296 } else 1297 pci_release_msi(dev); 1298 } 1299 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1300 msic = 0; 1301 } 1302 1303 /* Allocate interrupt */ 1304 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1305 rid = 0; 1306 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1307 RF_SHAREABLE | RF_ACTIVE); 1308 if (sc->rl_irq[0] == NULL) { 1309 device_printf(dev, "couldn't allocate IRQ resources\n"); 1310 error = ENXIO; 1311 goto fail; 1312 } 1313 } else { 1314 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1315 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1316 SYS_RES_IRQ, &rid, RF_ACTIVE); 1317 if (sc->rl_irq[i] == NULL) { 1318 device_printf(dev, 1319 "couldn't llocate IRQ resources for " 1320 "message %d\n", rid); 1321 error = ENXIO; 1322 goto fail; 1323 } 1324 } 1325 } 1326 1327 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1328 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1329 cfg = CSR_READ_1(sc, RL_CFG2); 1330 if ((cfg & RL_CFG2_MSI) != 0) { 1331 device_printf(dev, "turning off MSI enable bit.\n"); 1332 cfg &= ~RL_CFG2_MSI; 1333 CSR_WRITE_1(sc, RL_CFG2, cfg); 1334 } 1335 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1336 } 1337 1338 /* Disable ASPM L0S/L1. */ 1339 if (sc->rl_expcap != 0) { 1340 cap = pci_read_config(dev, sc->rl_expcap + 1341 PCIR_EXPRESS_LINK_CAP, 2); 1342 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 1343 ctl = pci_read_config(dev, sc->rl_expcap + 1344 PCIR_EXPRESS_LINK_CTL, 2); 1345 if ((ctl & 0x0003) != 0) { 1346 ctl &= ~0x0003; 1347 pci_write_config(dev, sc->rl_expcap + 1348 PCIR_EXPRESS_LINK_CTL, ctl, 2); 1349 device_printf(dev, "ASPM disabled\n"); 1350 } 1351 } else 1352 device_printf(dev, "no ASPM capability\n"); 1353 } 1354 1355 hw_rev = re_hwrevs; 1356 hwrev = CSR_READ_4(sc, RL_TXCFG); 1357 switch (hwrev & 0x70000000) { 1358 case 0x00000000: 1359 case 0x10000000: 1360 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1361 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1362 break; 1363 default: 1364 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1365 hwrev &= RL_TXCFG_HWREV; 1366 break; 1367 } 1368 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1369 while (hw_rev->rl_desc != NULL) { 1370 if (hw_rev->rl_rev == hwrev) { 1371 sc->rl_type = hw_rev->rl_type; 1372 sc->rl_hwrev = hw_rev; 1373 break; 1374 } 1375 hw_rev++; 1376 } 1377 if (hw_rev->rl_desc == NULL) { 1378 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1379 error = ENXIO; 1380 goto fail; 1381 } 1382 1383 switch (hw_rev->rl_rev) { 1384 case RL_HWREV_8139CPLUS: 1385 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1386 break; 1387 case RL_HWREV_8100E: 1388 case RL_HWREV_8101E: 1389 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1390 break; 1391 case RL_HWREV_8102E: 1392 case RL_HWREV_8102EL: 1393 case RL_HWREV_8102EL_SPIN1: 1394 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1395 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1396 RL_FLAG_AUTOPAD; 1397 break; 1398 case RL_HWREV_8103E: 1399 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1400 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1401 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1402 break; 1403 case RL_HWREV_8401E: 1404 case RL_HWREV_8402: 1405 case RL_HWREV_8105E: 1406 case RL_HWREV_8105E_SPIN1: 1407 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1408 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1409 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1410 break; 1411 case RL_HWREV_8168B_SPIN1: 1412 case RL_HWREV_8168B_SPIN2: 1413 sc->rl_flags |= RL_FLAG_WOLRXENB; 1414 /* FALLTHROUGH */ 1415 case RL_HWREV_8168B_SPIN3: 1416 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1417 break; 1418 case RL_HWREV_8168C_SPIN2: 1419 sc->rl_flags |= RL_FLAG_MACSLEEP; 1420 /* FALLTHROUGH */ 1421 case RL_HWREV_8168C: 1422 if ((hwrev & 0x00700000) == 0x00200000) 1423 sc->rl_flags |= RL_FLAG_MACSLEEP; 1424 /* FALLTHROUGH */ 1425 case RL_HWREV_8168CP: 1426 case RL_HWREV_8168D: 1427 case RL_HWREV_8168DP: 1428 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1429 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1430 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1431 break; 1432 case RL_HWREV_8168E: 1433 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1434 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1435 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1436 break; 1437 case RL_HWREV_8168E_VL: 1438 case RL_HWREV_8168F: 1439 case RL_HWREV_8411: 1440 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1441 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1442 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1443 break; 1444 case RL_HWREV_8169_8110SB: 1445 case RL_HWREV_8169_8110SBL: 1446 case RL_HWREV_8169_8110SC: 1447 case RL_HWREV_8169_8110SCE: 1448 sc->rl_flags |= RL_FLAG_PHYWAKE; 1449 /* FALLTHROUGH */ 1450 case RL_HWREV_8169: 1451 case RL_HWREV_8169S: 1452 case RL_HWREV_8110S: 1453 sc->rl_flags |= RL_FLAG_MACRESET; 1454 break; 1455 default: 1456 break; 1457 } 1458 1459 /* Reset the adapter. */ 1460 RL_LOCK(sc); 1461 re_reset(sc); 1462 RL_UNLOCK(sc); 1463 1464 /* Enable PME. */ 1465 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1466 cfg = CSR_READ_1(sc, RL_CFG1); 1467 cfg |= RL_CFG1_PME; 1468 CSR_WRITE_1(sc, RL_CFG1, cfg); 1469 cfg = CSR_READ_1(sc, RL_CFG5); 1470 cfg &= RL_CFG5_PME_STS; 1471 CSR_WRITE_1(sc, RL_CFG5, cfg); 1472 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1473 1474 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1475 /* 1476 * XXX Should have a better way to extract station 1477 * address from EEPROM. 1478 */ 1479 for (i = 0; i < ETHER_ADDR_LEN; i++) 1480 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1481 } else { 1482 sc->rl_eewidth = RL_9356_ADDR_LEN; 1483 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1484 if (re_did != 0x8129) 1485 sc->rl_eewidth = RL_9346_ADDR_LEN; 1486 1487 /* 1488 * Get station address from the EEPROM. 1489 */ 1490 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1491 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1492 as[i] = le16toh(as[i]); 1493 bcopy(as, eaddr, sizeof(eaddr)); 1494 } 1495 1496 if (sc->rl_type == RL_8169) { 1497 /* Set RX length mask and number of descriptors. */ 1498 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1499 sc->rl_txstart = RL_GTXSTART; 1500 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1501 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1502 } else { 1503 /* Set RX length mask and number of descriptors. */ 1504 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1505 sc->rl_txstart = RL_TXSTART; 1506 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1507 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1508 } 1509 1510 error = re_allocmem(dev, sc); 1511 if (error) 1512 goto fail; 1513 re_add_sysctls(sc); 1514 1515 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1516 if (ifp == NULL) { 1517 device_printf(dev, "can not if_alloc()\n"); 1518 error = ENOSPC; 1519 goto fail; 1520 } 1521 1522 /* Take controller out of deep sleep mode. */ 1523 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1524 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1525 CSR_WRITE_1(sc, RL_GPIO, 1526 CSR_READ_1(sc, RL_GPIO) | 0x01); 1527 else 1528 CSR_WRITE_1(sc, RL_GPIO, 1529 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1530 } 1531 1532 /* Take PHY out of power down mode. */ 1533 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1534 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1535 if (hw_rev->rl_rev == RL_HWREV_8401E) 1536 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1537 } 1538 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1539 re_gmii_writereg(dev, 1, 0x1f, 0); 1540 re_gmii_writereg(dev, 1, 0x0e, 0); 1541 } 1542 1543#define RE_PHYAD_INTERNAL 0 1544 1545 /* Do MII setup. */ 1546 phy = RE_PHYAD_INTERNAL; 1547 if (sc->rl_type == RL_8169) 1548 phy = 1; 1549 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1550 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1551 if (error != 0) { 1552 device_printf(dev, "attaching PHYs failed\n"); 1553 goto fail; 1554 } 1555 1556 ifp->if_softc = sc; 1557 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1558 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1559 ifp->if_ioctl = re_ioctl; 1560 ifp->if_start = re_start; 1561 /* 1562 * RTL8168/8111C generates wrong IP checksummed frame if the 1563 * packet has IP options so disable TX IP checksum offloading. 1564 */ 1565 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1566 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2) 1567 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1568 else 1569 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1570 ifp->if_hwassist |= CSUM_TSO; 1571 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1572 ifp->if_capenable = ifp->if_capabilities; 1573 ifp->if_init = re_init; 1574 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1575 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1576 IFQ_SET_READY(&ifp->if_snd); 1577 1578 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1579 1580 /* 1581 * Call MI attach routine. 1582 */ 1583 ether_ifattach(ifp, eaddr); 1584 1585 /* VLAN capability setup */ 1586 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1587 if (ifp->if_capabilities & IFCAP_HWCSUM) 1588 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1589 /* Enable WOL if PM is supported. */ 1590 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1591 ifp->if_capabilities |= IFCAP_WOL; 1592 ifp->if_capenable = ifp->if_capabilities; 1593 /* 1594 * Don't enable TSO by default. It is known to generate 1595 * corrupted TCP segments(bad TCP options) under certain 1596 * circumtances. 1597 */ 1598 ifp->if_hwassist &= ~CSUM_TSO; 1599 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1600#ifdef DEVICE_POLLING 1601 ifp->if_capabilities |= IFCAP_POLLING; 1602#endif 1603 /* 1604 * Tell the upper layer(s) we support long frames. 1605 * Must appear after the call to ether_ifattach() because 1606 * ether_ifattach() sets ifi_hdrlen to the default value. 1607 */ 1608 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1609 1610#ifdef RE_DIAG 1611 /* 1612 * Perform hardware diagnostic on the original RTL8169. 1613 * Some 32-bit cards were incorrectly wired and would 1614 * malfunction if plugged into a 64-bit slot. 1615 */ 1616 1617 if (hwrev == RL_HWREV_8169) { 1618 error = re_diag(sc); 1619 if (error) { 1620 device_printf(dev, 1621 "attach aborted due to hardware diag failure\n"); 1622 ether_ifdetach(ifp); 1623 goto fail; 1624 } 1625 } 1626#endif 1627 1628#ifdef RE_TX_MODERATION 1629 intr_filter = 1; 1630#endif 1631 /* Hook interrupt last to avoid having to lock softc */ 1632 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1633 intr_filter == 0) { 1634 error = bus_setup_intr(dev, sc->rl_irq[0], 1635 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1636 &sc->rl_intrhand[0]); 1637 } else { 1638 error = bus_setup_intr(dev, sc->rl_irq[0], 1639 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1640 &sc->rl_intrhand[0]); 1641 } 1642 if (error) { 1643 device_printf(dev, "couldn't set up irq\n"); 1644 ether_ifdetach(ifp); 1645 } 1646 1647fail: 1648 1649 if (error) 1650 re_detach(dev); 1651 1652 return (error); 1653} 1654 1655/* 1656 * Shutdown hardware and free up resources. This can be called any 1657 * time after the mutex has been initialized. It is called in both 1658 * the error case in attach and the normal detach case so it needs 1659 * to be careful about only freeing resources that have actually been 1660 * allocated. 1661 */ 1662static int 1663re_detach(device_t dev) 1664{ 1665 struct rl_softc *sc; 1666 struct ifnet *ifp; 1667 int i, rid; 1668 1669 sc = device_get_softc(dev); 1670 ifp = sc->rl_ifp; 1671 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1672 1673 /* These should only be active if attach succeeded */ 1674 if (device_is_attached(dev)) { 1675#ifdef DEVICE_POLLING 1676 if (ifp->if_capenable & IFCAP_POLLING) 1677 ether_poll_deregister(ifp); 1678#endif 1679 RL_LOCK(sc); 1680#if 0 1681 sc->suspended = 1; 1682#endif 1683 re_stop(sc); 1684 RL_UNLOCK(sc); 1685 callout_drain(&sc->rl_stat_callout); 1686 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1687 /* 1688 * Force off the IFF_UP flag here, in case someone 1689 * still had a BPF descriptor attached to this 1690 * interface. If they do, ether_ifdetach() will cause 1691 * the BPF code to try and clear the promisc mode 1692 * flag, which will bubble down to re_ioctl(), 1693 * which will try to call re_init() again. This will 1694 * turn the NIC back on and restart the MII ticker, 1695 * which will panic the system when the kernel tries 1696 * to invoke the re_tick() function that isn't there 1697 * anymore. 1698 */ 1699 ifp->if_flags &= ~IFF_UP; 1700 ether_ifdetach(ifp); 1701 } 1702 if (sc->rl_miibus) 1703 device_delete_child(dev, sc->rl_miibus); 1704 bus_generic_detach(dev); 1705 1706 /* 1707 * The rest is resource deallocation, so we should already be 1708 * stopped here. 1709 */ 1710 1711 if (sc->rl_intrhand[0] != NULL) { 1712 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1713 sc->rl_intrhand[0] = NULL; 1714 } 1715 if (ifp != NULL) 1716 if_free(ifp); 1717 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1718 rid = 0; 1719 else 1720 rid = 1; 1721 if (sc->rl_irq[0] != NULL) { 1722 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1723 sc->rl_irq[0] = NULL; 1724 } 1725 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1726 pci_release_msi(dev); 1727 if (sc->rl_res_pba) { 1728 rid = PCIR_BAR(4); 1729 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1730 } 1731 if (sc->rl_res) 1732 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1733 sc->rl_res); 1734 1735 /* Unload and free the RX DMA ring memory and map */ 1736 1737 if (sc->rl_ldata.rl_rx_list_tag) { 1738 if (sc->rl_ldata.rl_rx_list_map) 1739 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1740 sc->rl_ldata.rl_rx_list_map); 1741 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1742 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1743 sc->rl_ldata.rl_rx_list, 1744 sc->rl_ldata.rl_rx_list_map); 1745 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1746 } 1747 1748 /* Unload and free the TX DMA ring memory and map */ 1749 1750 if (sc->rl_ldata.rl_tx_list_tag) { 1751 if (sc->rl_ldata.rl_tx_list_map) 1752 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1753 sc->rl_ldata.rl_tx_list_map); 1754 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1755 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1756 sc->rl_ldata.rl_tx_list, 1757 sc->rl_ldata.rl_tx_list_map); 1758 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1759 } 1760 1761 /* Destroy all the RX and TX buffer maps */ 1762 1763 if (sc->rl_ldata.rl_tx_mtag) { 1764 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1765 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1766 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1767 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1768 } 1769 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1770 } 1771 if (sc->rl_ldata.rl_rx_mtag) { 1772 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1773 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1774 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1775 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1776 } 1777 if (sc->rl_ldata.rl_rx_sparemap) 1778 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1779 sc->rl_ldata.rl_rx_sparemap); 1780 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1781 } 1782 if (sc->rl_ldata.rl_jrx_mtag) { 1783 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1784 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1785 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1786 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1787 } 1788 if (sc->rl_ldata.rl_jrx_sparemap) 1789 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1790 sc->rl_ldata.rl_jrx_sparemap); 1791 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1792 } 1793 /* Unload and free the stats buffer and map */ 1794 1795 if (sc->rl_ldata.rl_stag) { 1796 if (sc->rl_ldata.rl_smap) 1797 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1798 sc->rl_ldata.rl_smap); 1799 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1800 bus_dmamem_free(sc->rl_ldata.rl_stag, 1801 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1802 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1803 } 1804 1805 if (sc->rl_parent_tag) 1806 bus_dma_tag_destroy(sc->rl_parent_tag); 1807 1808 mtx_destroy(&sc->rl_mtx); 1809 1810 return (0); 1811} 1812 1813static __inline void 1814re_discard_rxbuf(struct rl_softc *sc, int idx) 1815{ 1816 struct rl_desc *desc; 1817 struct rl_rxdesc *rxd; 1818 uint32_t cmdstat; 1819 1820 if (sc->rl_ifp->if_mtu > RL_MTU && 1821 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1822 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1823 else 1824 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1825 desc = &sc->rl_ldata.rl_rx_list[idx]; 1826 desc->rl_vlanctl = 0; 1827 cmdstat = rxd->rx_size; 1828 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1829 cmdstat |= RL_RDESC_CMD_EOR; 1830 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1831} 1832 1833static int 1834re_newbuf(struct rl_softc *sc, int idx) 1835{ 1836 struct mbuf *m; 1837 struct rl_rxdesc *rxd; 1838 bus_dma_segment_t segs[1]; 1839 bus_dmamap_t map; 1840 struct rl_desc *desc; 1841 uint32_t cmdstat; 1842 int error, nsegs; 1843 1844 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1845 if (m == NULL) 1846 return (ENOBUFS); 1847 1848 m->m_len = m->m_pkthdr.len = MCLBYTES; 1849#ifdef RE_FIXUP_RX 1850 /* 1851 * This is part of an evil trick to deal with non-x86 platforms. 1852 * The RealTek chip requires RX buffers to be aligned on 64-bit 1853 * boundaries, but that will hose non-x86 machines. To get around 1854 * this, we leave some empty space at the start of each buffer 1855 * and for non-x86 hosts, we copy the buffer back six bytes 1856 * to achieve word alignment. This is slightly more efficient 1857 * than allocating a new buffer, copying the contents, and 1858 * discarding the old buffer. 1859 */ 1860 m_adj(m, RE_ETHER_ALIGN); 1861#endif 1862 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1863 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1864 if (error != 0) { 1865 m_freem(m); 1866 return (ENOBUFS); 1867 } 1868 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1869 1870 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1871 if (rxd->rx_m != NULL) { 1872 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1873 BUS_DMASYNC_POSTREAD); 1874 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1875 } 1876 1877 rxd->rx_m = m; 1878 map = rxd->rx_dmamap; 1879 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1880 rxd->rx_size = segs[0].ds_len; 1881 sc->rl_ldata.rl_rx_sparemap = map; 1882 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1883 BUS_DMASYNC_PREREAD); 1884 1885 desc = &sc->rl_ldata.rl_rx_list[idx]; 1886 desc->rl_vlanctl = 0; 1887 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1888 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1889 cmdstat = segs[0].ds_len; 1890 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1891 cmdstat |= RL_RDESC_CMD_EOR; 1892 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1893 1894 return (0); 1895} 1896 1897static int 1898re_jumbo_newbuf(struct rl_softc *sc, int idx) 1899{ 1900 struct mbuf *m; 1901 struct rl_rxdesc *rxd; 1902 bus_dma_segment_t segs[1]; 1903 bus_dmamap_t map; 1904 struct rl_desc *desc; 1905 uint32_t cmdstat; 1906 int error, nsegs; 1907 1908 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1909 if (m == NULL) 1910 return (ENOBUFS); 1911 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1912#ifdef RE_FIXUP_RX 1913 m_adj(m, RE_ETHER_ALIGN); 1914#endif 1915 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1916 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1917 if (error != 0) { 1918 m_freem(m); 1919 return (ENOBUFS); 1920 } 1921 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1922 1923 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1924 if (rxd->rx_m != NULL) { 1925 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1926 BUS_DMASYNC_POSTREAD); 1927 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1928 } 1929 1930 rxd->rx_m = m; 1931 map = rxd->rx_dmamap; 1932 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 1933 rxd->rx_size = segs[0].ds_len; 1934 sc->rl_ldata.rl_jrx_sparemap = map; 1935 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1936 BUS_DMASYNC_PREREAD); 1937 1938 desc = &sc->rl_ldata.rl_rx_list[idx]; 1939 desc->rl_vlanctl = 0; 1940 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1941 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1942 cmdstat = segs[0].ds_len; 1943 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1944 cmdstat |= RL_RDESC_CMD_EOR; 1945 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1946 1947 return (0); 1948} 1949 1950#ifdef RE_FIXUP_RX 1951static __inline void 1952re_fixup_rx(struct mbuf *m) 1953{ 1954 int i; 1955 uint16_t *src, *dst; 1956 1957 src = mtod(m, uint16_t *); 1958 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1959 1960 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1961 *dst++ = *src++; 1962 1963 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1964} 1965#endif 1966 1967static int 1968re_tx_list_init(struct rl_softc *sc) 1969{ 1970 struct rl_desc *desc; 1971 int i; 1972 1973 RL_LOCK_ASSERT(sc); 1974 1975 bzero(sc->rl_ldata.rl_tx_list, 1976 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1977 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1978 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1979 /* Set EOR. */ 1980 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1981 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1982 1983 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1984 sc->rl_ldata.rl_tx_list_map, 1985 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1986 1987 sc->rl_ldata.rl_tx_prodidx = 0; 1988 sc->rl_ldata.rl_tx_considx = 0; 1989 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1990 1991 return (0); 1992} 1993 1994static int 1995re_rx_list_init(struct rl_softc *sc) 1996{ 1997 int error, i; 1998 1999 bzero(sc->rl_ldata.rl_rx_list, 2000 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2001 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2002 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2003 if ((error = re_newbuf(sc, i)) != 0) 2004 return (error); 2005 } 2006 2007 /* Flush the RX descriptors */ 2008 2009 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2010 sc->rl_ldata.rl_rx_list_map, 2011 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2012 2013 sc->rl_ldata.rl_rx_prodidx = 0; 2014 sc->rl_head = sc->rl_tail = NULL; 2015 sc->rl_int_rx_act = 0; 2016 2017 return (0); 2018} 2019 2020static int 2021re_jrx_list_init(struct rl_softc *sc) 2022{ 2023 int error, i; 2024 2025 bzero(sc->rl_ldata.rl_rx_list, 2026 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2027 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2028 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2029 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2030 return (error); 2031 } 2032 2033 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2034 sc->rl_ldata.rl_rx_list_map, 2035 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2036 2037 sc->rl_ldata.rl_rx_prodidx = 0; 2038 sc->rl_head = sc->rl_tail = NULL; 2039 sc->rl_int_rx_act = 0; 2040 2041 return (0); 2042} 2043 2044/* 2045 * RX handler for C+ and 8169. For the gigE chips, we support 2046 * the reception of jumbo frames that have been fragmented 2047 * across multiple 2K mbuf cluster buffers. 2048 */ 2049static int 2050re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2051{ 2052 struct mbuf *m; 2053 struct ifnet *ifp; 2054 int i, rxerr, total_len; 2055 struct rl_desc *cur_rx; 2056 u_int32_t rxstat, rxvlan; 2057 int jumbo, maxpkt = 16, rx_npkts = 0; 2058 2059 RL_LOCK_ASSERT(sc); 2060 2061 ifp = sc->rl_ifp; 2062 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2063 jumbo = 1; 2064 else 2065 jumbo = 0; 2066 2067 /* Invalidate the descriptor memory */ 2068 2069 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2070 sc->rl_ldata.rl_rx_list_map, 2071 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2072 2073 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2074 i = RL_RX_DESC_NXT(sc, i)) { 2075 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2076 break; 2077 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2078 rxstat = le32toh(cur_rx->rl_cmdstat); 2079 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2080 break; 2081 total_len = rxstat & sc->rl_rxlenmask; 2082 rxvlan = le32toh(cur_rx->rl_vlanctl); 2083 if (jumbo != 0) 2084 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2085 else 2086 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2087 2088 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2089 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2090 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2091 /* 2092 * RTL8168C or later controllers do not 2093 * support multi-fragment packet. 2094 */ 2095 re_discard_rxbuf(sc, i); 2096 continue; 2097 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2098 if (re_newbuf(sc, i) != 0) { 2099 /* 2100 * If this is part of a multi-fragment packet, 2101 * discard all the pieces. 2102 */ 2103 if (sc->rl_head != NULL) { 2104 m_freem(sc->rl_head); 2105 sc->rl_head = sc->rl_tail = NULL; 2106 } 2107 re_discard_rxbuf(sc, i); 2108 continue; 2109 } 2110 m->m_len = RE_RX_DESC_BUFLEN; 2111 if (sc->rl_head == NULL) 2112 sc->rl_head = sc->rl_tail = m; 2113 else { 2114 m->m_flags &= ~M_PKTHDR; 2115 sc->rl_tail->m_next = m; 2116 sc->rl_tail = m; 2117 } 2118 continue; 2119 } 2120 2121 /* 2122 * NOTE: for the 8139C+, the frame length field 2123 * is always 12 bits in size, but for the gigE chips, 2124 * it is 13 bits (since the max RX frame length is 16K). 2125 * Unfortunately, all 32 bits in the status word 2126 * were already used, so to make room for the extra 2127 * length bit, RealTek took out the 'frame alignment 2128 * error' bit and shifted the other status bits 2129 * over one slot. The OWN, EOR, FS and LS bits are 2130 * still in the same places. We have already extracted 2131 * the frame length and checked the OWN bit, so rather 2132 * than using an alternate bit mapping, we shift the 2133 * status bits one space to the right so we can evaluate 2134 * them using the 8169 status as though it was in the 2135 * same format as that of the 8139C+. 2136 */ 2137 if (sc->rl_type == RL_8169) 2138 rxstat >>= 1; 2139 2140 /* 2141 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2142 * set, but if CRC is clear, it will still be a valid frame. 2143 */ 2144 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2145 rxerr = 1; 2146 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2147 total_len > 8191 && 2148 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2149 rxerr = 0; 2150 if (rxerr != 0) { 2151 ifp->if_ierrors++; 2152 /* 2153 * If this is part of a multi-fragment packet, 2154 * discard all the pieces. 2155 */ 2156 if (sc->rl_head != NULL) { 2157 m_freem(sc->rl_head); 2158 sc->rl_head = sc->rl_tail = NULL; 2159 } 2160 re_discard_rxbuf(sc, i); 2161 continue; 2162 } 2163 } 2164 2165 /* 2166 * If allocating a replacement mbuf fails, 2167 * reload the current one. 2168 */ 2169 if (jumbo != 0) 2170 rxerr = re_jumbo_newbuf(sc, i); 2171 else 2172 rxerr = re_newbuf(sc, i); 2173 if (rxerr != 0) { 2174 ifp->if_iqdrops++; 2175 if (sc->rl_head != NULL) { 2176 m_freem(sc->rl_head); 2177 sc->rl_head = sc->rl_tail = NULL; 2178 } 2179 re_discard_rxbuf(sc, i); 2180 continue; 2181 } 2182 2183 if (sc->rl_head != NULL) { 2184 if (jumbo != 0) 2185 m->m_len = total_len; 2186 else { 2187 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2188 if (m->m_len == 0) 2189 m->m_len = RE_RX_DESC_BUFLEN; 2190 } 2191 /* 2192 * Special case: if there's 4 bytes or less 2193 * in this buffer, the mbuf can be discarded: 2194 * the last 4 bytes is the CRC, which we don't 2195 * care about anyway. 2196 */ 2197 if (m->m_len <= ETHER_CRC_LEN) { 2198 sc->rl_tail->m_len -= 2199 (ETHER_CRC_LEN - m->m_len); 2200 m_freem(m); 2201 } else { 2202 m->m_len -= ETHER_CRC_LEN; 2203 m->m_flags &= ~M_PKTHDR; 2204 sc->rl_tail->m_next = m; 2205 } 2206 m = sc->rl_head; 2207 sc->rl_head = sc->rl_tail = NULL; 2208 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2209 } else 2210 m->m_pkthdr.len = m->m_len = 2211 (total_len - ETHER_CRC_LEN); 2212 2213#ifdef RE_FIXUP_RX 2214 re_fixup_rx(m); 2215#endif 2216 ifp->if_ipackets++; 2217 m->m_pkthdr.rcvif = ifp; 2218 2219 /* Do RX checksumming if enabled */ 2220 2221 if (ifp->if_capenable & IFCAP_RXCSUM) { 2222 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2223 /* Check IP header checksum */ 2224 if (rxstat & RL_RDESC_STAT_PROTOID) 2225 m->m_pkthdr.csum_flags |= 2226 CSUM_IP_CHECKED; 2227 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2228 m->m_pkthdr.csum_flags |= 2229 CSUM_IP_VALID; 2230 2231 /* Check TCP/UDP checksum */ 2232 if ((RL_TCPPKT(rxstat) && 2233 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2234 (RL_UDPPKT(rxstat) && 2235 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2236 m->m_pkthdr.csum_flags |= 2237 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2238 m->m_pkthdr.csum_data = 0xffff; 2239 } 2240 } else { 2241 /* 2242 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2243 */ 2244 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2245 (rxvlan & RL_RDESC_IPV4)) 2246 m->m_pkthdr.csum_flags |= 2247 CSUM_IP_CHECKED; 2248 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2249 (rxvlan & RL_RDESC_IPV4)) 2250 m->m_pkthdr.csum_flags |= 2251 CSUM_IP_VALID; 2252 if (((rxstat & RL_RDESC_STAT_TCP) && 2253 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2254 ((rxstat & RL_RDESC_STAT_UDP) && 2255 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2256 m->m_pkthdr.csum_flags |= 2257 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2258 m->m_pkthdr.csum_data = 0xffff; 2259 } 2260 } 2261 } 2262 maxpkt--; 2263 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2264 m->m_pkthdr.ether_vtag = 2265 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2266 m->m_flags |= M_VLANTAG; 2267 } 2268 RL_UNLOCK(sc); 2269 (*ifp->if_input)(ifp, m); 2270 RL_LOCK(sc); 2271 rx_npkts++; 2272 } 2273 2274 /* Flush the RX DMA ring */ 2275 2276 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2277 sc->rl_ldata.rl_rx_list_map, 2278 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2279 2280 sc->rl_ldata.rl_rx_prodidx = i; 2281 2282 if (rx_npktsp != NULL) 2283 *rx_npktsp = rx_npkts; 2284 if (maxpkt) 2285 return (EAGAIN); 2286 2287 return (0); 2288} 2289 2290static void 2291re_txeof(struct rl_softc *sc) 2292{ 2293 struct ifnet *ifp; 2294 struct rl_txdesc *txd; 2295 u_int32_t txstat; 2296 int cons; 2297 2298 cons = sc->rl_ldata.rl_tx_considx; 2299 if (cons == sc->rl_ldata.rl_tx_prodidx) 2300 return; 2301 2302 ifp = sc->rl_ifp; 2303 /* Invalidate the TX descriptor list */ 2304 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2305 sc->rl_ldata.rl_tx_list_map, 2306 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2307 2308 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2309 cons = RL_TX_DESC_NXT(sc, cons)) { 2310 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2311 if (txstat & RL_TDESC_STAT_OWN) 2312 break; 2313 /* 2314 * We only stash mbufs in the last descriptor 2315 * in a fragment chain, which also happens to 2316 * be the only place where the TX status bits 2317 * are valid. 2318 */ 2319 if (txstat & RL_TDESC_CMD_EOF) { 2320 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2321 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2322 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2323 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2324 txd->tx_dmamap); 2325 KASSERT(txd->tx_m != NULL, 2326 ("%s: freeing NULL mbufs!", __func__)); 2327 m_freem(txd->tx_m); 2328 txd->tx_m = NULL; 2329 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2330 RL_TDESC_STAT_COLCNT)) 2331 ifp->if_collisions++; 2332 if (txstat & RL_TDESC_STAT_TXERRSUM) 2333 ifp->if_oerrors++; 2334 else 2335 ifp->if_opackets++; 2336 } 2337 sc->rl_ldata.rl_tx_free++; 2338 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2339 } 2340 sc->rl_ldata.rl_tx_considx = cons; 2341 2342 /* No changes made to the TX ring, so no flush needed */ 2343 2344 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2345#ifdef RE_TX_MODERATION 2346 /* 2347 * If not all descriptors have been reaped yet, reload 2348 * the timer so that we will eventually get another 2349 * interrupt that will cause us to re-enter this routine. 2350 * This is done in case the transmitter has gone idle. 2351 */ 2352 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2353#endif 2354 } else 2355 sc->rl_watchdog_timer = 0; 2356} 2357 2358static void 2359re_tick(void *xsc) 2360{ 2361 struct rl_softc *sc; 2362 struct mii_data *mii; 2363 2364 sc = xsc; 2365 2366 RL_LOCK_ASSERT(sc); 2367 2368 mii = device_get_softc(sc->rl_miibus); 2369 mii_tick(mii); 2370 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2371 re_miibus_statchg(sc->rl_dev); 2372 /* 2373 * Reclaim transmitted frames here. Technically it is not 2374 * necessary to do here but it ensures periodic reclamation 2375 * regardless of Tx completion interrupt which seems to be 2376 * lost on PCIe based controllers under certain situations. 2377 */ 2378 re_txeof(sc); 2379 re_watchdog(sc); 2380 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2381} 2382 2383#ifdef DEVICE_POLLING 2384static int 2385re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2386{ 2387 struct rl_softc *sc = ifp->if_softc; 2388 int rx_npkts = 0; 2389 2390 RL_LOCK(sc); 2391 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2392 rx_npkts = re_poll_locked(ifp, cmd, count); 2393 RL_UNLOCK(sc); 2394 return (rx_npkts); 2395} 2396 2397static int 2398re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2399{ 2400 struct rl_softc *sc = ifp->if_softc; 2401 int rx_npkts; 2402 2403 RL_LOCK_ASSERT(sc); 2404 2405 sc->rxcycles = count; 2406 re_rxeof(sc, &rx_npkts); 2407 re_txeof(sc); 2408 2409 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2410 re_start_locked(ifp); 2411 2412 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2413 u_int16_t status; 2414 2415 status = CSR_READ_2(sc, RL_ISR); 2416 if (status == 0xffff) 2417 return (rx_npkts); 2418 if (status) 2419 CSR_WRITE_2(sc, RL_ISR, status); 2420 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2421 (sc->rl_flags & RL_FLAG_PCIE)) 2422 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2423 2424 /* 2425 * XXX check behaviour on receiver stalls. 2426 */ 2427 2428 if (status & RL_ISR_SYSTEM_ERR) { 2429 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2430 re_init_locked(sc); 2431 } 2432 } 2433 return (rx_npkts); 2434} 2435#endif /* DEVICE_POLLING */ 2436 2437static int 2438re_intr(void *arg) 2439{ 2440 struct rl_softc *sc; 2441 uint16_t status; 2442 2443 sc = arg; 2444 2445 status = CSR_READ_2(sc, RL_ISR); 2446 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2447 return (FILTER_STRAY); 2448 CSR_WRITE_2(sc, RL_IMR, 0); 2449 2450 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2451 2452 return (FILTER_HANDLED); 2453} 2454 2455static void 2456re_int_task(void *arg, int npending) 2457{ 2458 struct rl_softc *sc; 2459 struct ifnet *ifp; 2460 u_int16_t status; 2461 int rval = 0; 2462 2463 sc = arg; 2464 ifp = sc->rl_ifp; 2465 2466 RL_LOCK(sc); 2467 2468 status = CSR_READ_2(sc, RL_ISR); 2469 CSR_WRITE_2(sc, RL_ISR, status); 2470 2471 if (sc->suspended || 2472 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2473 RL_UNLOCK(sc); 2474 return; 2475 } 2476 2477#ifdef DEVICE_POLLING 2478 if (ifp->if_capenable & IFCAP_POLLING) { 2479 RL_UNLOCK(sc); 2480 return; 2481 } 2482#endif 2483 2484 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2485 rval = re_rxeof(sc, NULL); 2486 2487 /* 2488 * Some chips will ignore a second TX request issued 2489 * while an existing transmission is in progress. If 2490 * the transmitter goes idle but there are still 2491 * packets waiting to be sent, we need to restart the 2492 * channel here to flush them out. This only seems to 2493 * be required with the PCIe devices. 2494 */ 2495 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2496 (sc->rl_flags & RL_FLAG_PCIE)) 2497 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2498 if (status & ( 2499#ifdef RE_TX_MODERATION 2500 RL_ISR_TIMEOUT_EXPIRED| 2501#else 2502 RL_ISR_TX_OK| 2503#endif 2504 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2505 re_txeof(sc); 2506 2507 if (status & RL_ISR_SYSTEM_ERR) { 2508 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2509 re_init_locked(sc); 2510 } 2511 2512 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2513 re_start_locked(ifp); 2514 2515 RL_UNLOCK(sc); 2516 2517 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2518 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2519 return; 2520 } 2521 2522 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2523} 2524 2525static void 2526re_intr_msi(void *xsc) 2527{ 2528 struct rl_softc *sc; 2529 struct ifnet *ifp; 2530 uint16_t intrs, status; 2531 2532 sc = xsc; 2533 RL_LOCK(sc); 2534 2535 ifp = sc->rl_ifp; 2536#ifdef DEVICE_POLLING 2537 if (ifp->if_capenable & IFCAP_POLLING) { 2538 RL_UNLOCK(sc); 2539 return; 2540 } 2541#endif 2542 /* Disable interrupts. */ 2543 CSR_WRITE_2(sc, RL_IMR, 0); 2544 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2545 RL_UNLOCK(sc); 2546 return; 2547 } 2548 2549 intrs = RL_INTRS_CPLUS; 2550 status = CSR_READ_2(sc, RL_ISR); 2551 CSR_WRITE_2(sc, RL_ISR, status); 2552 if (sc->rl_int_rx_act > 0) { 2553 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2554 RL_ISR_RX_OVERRUN); 2555 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2556 RL_ISR_RX_OVERRUN); 2557 } 2558 2559 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2560 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2561 re_rxeof(sc, NULL); 2562 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2563 if (sc->rl_int_rx_mod != 0 && 2564 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2565 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2566 /* Rearm one-shot timer. */ 2567 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2568 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2569 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2570 sc->rl_int_rx_act = 1; 2571 } else { 2572 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2573 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2574 sc->rl_int_rx_act = 0; 2575 } 2576 } 2577 } 2578 2579 /* 2580 * Some chips will ignore a second TX request issued 2581 * while an existing transmission is in progress. If 2582 * the transmitter goes idle but there are still 2583 * packets waiting to be sent, we need to restart the 2584 * channel here to flush them out. This only seems to 2585 * be required with the PCIe devices. 2586 */ 2587 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2588 (sc->rl_flags & RL_FLAG_PCIE)) 2589 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2590 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2591 re_txeof(sc); 2592 2593 if (status & RL_ISR_SYSTEM_ERR) { 2594 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2595 re_init_locked(sc); 2596 } 2597 2598 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2599 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2600 re_start_locked(ifp); 2601 CSR_WRITE_2(sc, RL_IMR, intrs); 2602 } 2603 RL_UNLOCK(sc); 2604} 2605 2606static int 2607re_encap(struct rl_softc *sc, struct mbuf **m_head) 2608{ 2609 struct rl_txdesc *txd, *txd_last; 2610 bus_dma_segment_t segs[RL_NTXSEGS]; 2611 bus_dmamap_t map; 2612 struct mbuf *m_new; 2613 struct rl_desc *desc; 2614 int nsegs, prod; 2615 int i, error, ei, si; 2616 int padlen; 2617 uint32_t cmdstat, csum_flags, vlanctl; 2618 2619 RL_LOCK_ASSERT(sc); 2620 M_ASSERTPKTHDR((*m_head)); 2621 2622 /* 2623 * With some of the RealTek chips, using the checksum offload 2624 * support in conjunction with the autopadding feature results 2625 * in the transmission of corrupt frames. For example, if we 2626 * need to send a really small IP fragment that's less than 60 2627 * bytes in size, and IP header checksumming is enabled, the 2628 * resulting ethernet frame that appears on the wire will 2629 * have garbled payload. To work around this, if TX IP checksum 2630 * offload is enabled, we always manually pad short frames out 2631 * to the minimum ethernet frame size. 2632 */ 2633 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2634 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2635 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2636 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2637 if (M_WRITABLE(*m_head) == 0) { 2638 /* Get a writable copy. */ 2639 m_new = m_dup(*m_head, M_DONTWAIT); 2640 m_freem(*m_head); 2641 if (m_new == NULL) { 2642 *m_head = NULL; 2643 return (ENOBUFS); 2644 } 2645 *m_head = m_new; 2646 } 2647 if ((*m_head)->m_next != NULL || 2648 M_TRAILINGSPACE(*m_head) < padlen) { 2649 m_new = m_defrag(*m_head, M_DONTWAIT); 2650 if (m_new == NULL) { 2651 m_freem(*m_head); 2652 *m_head = NULL; 2653 return (ENOBUFS); 2654 } 2655 } else 2656 m_new = *m_head; 2657 2658 /* 2659 * Manually pad short frames, and zero the pad space 2660 * to avoid leaking data. 2661 */ 2662 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2663 m_new->m_pkthdr.len += padlen; 2664 m_new->m_len = m_new->m_pkthdr.len; 2665 *m_head = m_new; 2666 } 2667 2668 prod = sc->rl_ldata.rl_tx_prodidx; 2669 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2670 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2671 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2672 if (error == EFBIG) { 2673 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2674 if (m_new == NULL) { 2675 m_freem(*m_head); 2676 *m_head = NULL; 2677 return (ENOBUFS); 2678 } 2679 *m_head = m_new; 2680 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2681 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2682 if (error != 0) { 2683 m_freem(*m_head); 2684 *m_head = NULL; 2685 return (error); 2686 } 2687 } else if (error != 0) 2688 return (error); 2689 if (nsegs == 0) { 2690 m_freem(*m_head); 2691 *m_head = NULL; 2692 return (EIO); 2693 } 2694 2695 /* Check for number of available descriptors. */ 2696 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2697 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2698 return (ENOBUFS); 2699 } 2700 2701 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2702 BUS_DMASYNC_PREWRITE); 2703 2704 /* 2705 * Set up checksum offload. Note: checksum offload bits must 2706 * appear in all descriptors of a multi-descriptor transmit 2707 * attempt. This is according to testing done with an 8169 2708 * chip. This is a requirement. 2709 */ 2710 vlanctl = 0; 2711 csum_flags = 0; 2712 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2713 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2714 csum_flags |= RL_TDESC_CMD_LGSEND; 2715 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2716 RL_TDESC_CMD_MSSVALV2_SHIFT); 2717 } else { 2718 csum_flags |= RL_TDESC_CMD_LGSEND | 2719 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2720 RL_TDESC_CMD_MSSVAL_SHIFT); 2721 } 2722 } else { 2723 /* 2724 * Unconditionally enable IP checksum if TCP or UDP 2725 * checksum is required. Otherwise, TCP/UDP checksum 2726 * does't make effects. 2727 */ 2728 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2729 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2730 csum_flags |= RL_TDESC_CMD_IPCSUM; 2731 if (((*m_head)->m_pkthdr.csum_flags & 2732 CSUM_TCP) != 0) 2733 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2734 if (((*m_head)->m_pkthdr.csum_flags & 2735 CSUM_UDP) != 0) 2736 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2737 } else { 2738 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2739 if (((*m_head)->m_pkthdr.csum_flags & 2740 CSUM_TCP) != 0) 2741 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2742 if (((*m_head)->m_pkthdr.csum_flags & 2743 CSUM_UDP) != 0) 2744 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2745 } 2746 } 2747 } 2748 2749 /* 2750 * Set up hardware VLAN tagging. Note: vlan tag info must 2751 * appear in all descriptors of a multi-descriptor 2752 * transmission attempt. 2753 */ 2754 if ((*m_head)->m_flags & M_VLANTAG) 2755 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2756 RL_TDESC_VLANCTL_TAG; 2757 2758 si = prod; 2759 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2760 desc = &sc->rl_ldata.rl_tx_list[prod]; 2761 desc->rl_vlanctl = htole32(vlanctl); 2762 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2763 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2764 cmdstat = segs[i].ds_len; 2765 if (i != 0) 2766 cmdstat |= RL_TDESC_CMD_OWN; 2767 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2768 cmdstat |= RL_TDESC_CMD_EOR; 2769 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2770 sc->rl_ldata.rl_tx_free--; 2771 } 2772 /* Update producer index. */ 2773 sc->rl_ldata.rl_tx_prodidx = prod; 2774 2775 /* Set EOF on the last descriptor. */ 2776 ei = RL_TX_DESC_PRV(sc, prod); 2777 desc = &sc->rl_ldata.rl_tx_list[ei]; 2778 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2779 2780 desc = &sc->rl_ldata.rl_tx_list[si]; 2781 /* Set SOF and transfer ownership of packet to the chip. */ 2782 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2783 2784 /* 2785 * Insure that the map for this transmission 2786 * is placed at the array index of the last descriptor 2787 * in this chain. (Swap last and first dmamaps.) 2788 */ 2789 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2790 map = txd->tx_dmamap; 2791 txd->tx_dmamap = txd_last->tx_dmamap; 2792 txd_last->tx_dmamap = map; 2793 txd_last->tx_m = *m_head; 2794 2795 return (0); 2796} 2797 2798static void 2799re_start(struct ifnet *ifp) 2800{ 2801 struct rl_softc *sc; 2802 2803 sc = ifp->if_softc; 2804 RL_LOCK(sc); 2805 re_start_locked(ifp); 2806 RL_UNLOCK(sc); 2807} 2808 2809/* 2810 * Main transmit routine for C+ and gigE NICs. 2811 */ 2812static void 2813re_start_locked(struct ifnet *ifp) 2814{ 2815 struct rl_softc *sc; 2816 struct mbuf *m_head; 2817 int queued; 2818 2819 sc = ifp->if_softc; 2820 2821 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2822 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2823 return; 2824 2825 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2826 sc->rl_ldata.rl_tx_free > 1;) { 2827 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2828 if (m_head == NULL) 2829 break; 2830 2831 if (re_encap(sc, &m_head) != 0) { 2832 if (m_head == NULL) 2833 break; 2834 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2835 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2836 break; 2837 } 2838 2839 /* 2840 * If there's a BPF listener, bounce a copy of this frame 2841 * to him. 2842 */ 2843 ETHER_BPF_MTAP(ifp, m_head); 2844 2845 queued++; 2846 } 2847 2848 if (queued == 0) { 2849#ifdef RE_TX_MODERATION 2850 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2851 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2852#endif 2853 return; 2854 } 2855 2856 /* Flush the TX descriptors */ 2857 2858 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2859 sc->rl_ldata.rl_tx_list_map, 2860 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2861 2862 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2863 2864#ifdef RE_TX_MODERATION 2865 /* 2866 * Use the countdown timer for interrupt moderation. 2867 * 'TX done' interrupts are disabled. Instead, we reset the 2868 * countdown timer, which will begin counting until it hits 2869 * the value in the TIMERINT register, and then trigger an 2870 * interrupt. Each time we write to the TIMERCNT register, 2871 * the timer count is reset to 0. 2872 */ 2873 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2874#endif 2875 2876 /* 2877 * Set a timeout in case the chip goes out to lunch. 2878 */ 2879 sc->rl_watchdog_timer = 5; 2880} 2881 2882static void 2883re_set_jumbo(struct rl_softc *sc, int jumbo) 2884{ 2885 2886 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2887 pci_set_max_read_req(sc->rl_dev, 4096); 2888 return; 2889 } 2890 2891 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2892 if (jumbo != 0) { 2893 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) | 2894 RL_CFG3_JUMBO_EN0); 2895 switch (sc->rl_hwrev->rl_rev) { 2896 case RL_HWREV_8168DP: 2897 break; 2898 case RL_HWREV_8168E: 2899 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2900 0x01); 2901 break; 2902 default: 2903 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2904 RL_CFG4_JUMBO_EN1); 2905 } 2906 } else { 2907 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) & 2908 ~RL_CFG3_JUMBO_EN0); 2909 switch (sc->rl_hwrev->rl_rev) { 2910 case RL_HWREV_8168DP: 2911 break; 2912 case RL_HWREV_8168E: 2913 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2914 ~0x01); 2915 break; 2916 default: 2917 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2918 ~RL_CFG4_JUMBO_EN1); 2919 } 2920 } 2921 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2922 2923 switch (sc->rl_hwrev->rl_rev) { 2924 case RL_HWREV_8168DP: 2925 pci_set_max_read_req(sc->rl_dev, 4096); 2926 break; 2927 default: 2928 if (jumbo != 0) 2929 pci_set_max_read_req(sc->rl_dev, 512); 2930 else 2931 pci_set_max_read_req(sc->rl_dev, 4096); 2932 } 2933} 2934 2935static void 2936re_init(void *xsc) 2937{ 2938 struct rl_softc *sc = xsc; 2939 2940 RL_LOCK(sc); 2941 re_init_locked(sc); 2942 RL_UNLOCK(sc); 2943} 2944 2945static void 2946re_init_locked(struct rl_softc *sc) 2947{ 2948 struct ifnet *ifp = sc->rl_ifp; 2949 struct mii_data *mii; 2950 uint32_t reg; 2951 uint16_t cfg; 2952 union { 2953 uint32_t align_dummy; 2954 u_char eaddr[ETHER_ADDR_LEN]; 2955 } eaddr; 2956 2957 RL_LOCK_ASSERT(sc); 2958 2959 mii = device_get_softc(sc->rl_miibus); 2960 2961 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2962 return; 2963 2964 /* 2965 * Cancel pending I/O and free all RX/TX buffers. 2966 */ 2967 re_stop(sc); 2968 2969 /* Put controller into known state. */ 2970 re_reset(sc); 2971 2972 /* 2973 * For C+ mode, initialize the RX descriptors and mbufs. 2974 */ 2975 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 2976 if (ifp->if_mtu > RL_MTU) { 2977 if (re_jrx_list_init(sc) != 0) { 2978 device_printf(sc->rl_dev, 2979 "no memory for jumbo RX buffers\n"); 2980 re_stop(sc); 2981 return; 2982 } 2983 /* Disable checksum offloading for jumbo frames. */ 2984 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 2985 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 2986 } else { 2987 if (re_rx_list_init(sc) != 0) { 2988 device_printf(sc->rl_dev, 2989 "no memory for RX buffers\n"); 2990 re_stop(sc); 2991 return; 2992 } 2993 } 2994 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 2995 } else { 2996 if (re_rx_list_init(sc) != 0) { 2997 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 2998 re_stop(sc); 2999 return; 3000 } 3001 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3002 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3003 if (ifp->if_mtu > RL_MTU) 3004 pci_set_max_read_req(sc->rl_dev, 512); 3005 else 3006 pci_set_max_read_req(sc->rl_dev, 4096); 3007 } 3008 } 3009 re_tx_list_init(sc); 3010 3011 /* 3012 * Enable C+ RX and TX mode, as well as VLAN stripping and 3013 * RX checksum offload. We must configure the C+ register 3014 * before all others. 3015 */ 3016 cfg = RL_CPLUSCMD_PCI_MRW; 3017 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3018 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3019 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3020 cfg |= RL_CPLUSCMD_VLANSTRIP; 3021 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3022 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3023 /* XXX magic. */ 3024 cfg |= 0x0001; 3025 } else 3026 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3027 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3028 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3029 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3030 reg = 0x000fff00; 3031 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 3032 reg |= 0x000000ff; 3033 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3034 reg |= 0x00f00000; 3035 CSR_WRITE_4(sc, 0x7c, reg); 3036 /* Disable interrupt mitigation. */ 3037 CSR_WRITE_2(sc, 0xe2, 0); 3038 } 3039 /* 3040 * Disable TSO if interface MTU size is greater than MSS 3041 * allowed in controller. 3042 */ 3043 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3044 ifp->if_capenable &= ~IFCAP_TSO4; 3045 ifp->if_hwassist &= ~CSUM_TSO; 3046 } 3047 3048 /* 3049 * Init our MAC address. Even though the chipset 3050 * documentation doesn't mention it, we need to enter "Config 3051 * register write enable" mode to modify the ID registers. 3052 */ 3053 /* Copy MAC address on stack to align. */ 3054 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3055 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3056 CSR_WRITE_4(sc, RL_IDR0, 3057 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3058 CSR_WRITE_4(sc, RL_IDR4, 3059 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3060 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3061 3062 /* 3063 * Load the addresses of the RX and TX lists into the chip. 3064 */ 3065 3066 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3067 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3068 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3069 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3070 3071 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3072 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3073 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3074 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3075 3076 /* 3077 * Enable transmit and receive. 3078 */ 3079 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3080 3081 /* 3082 * Set the initial TX configuration. 3083 */ 3084 if (sc->rl_testmode) { 3085 if (sc->rl_type == RL_8169) 3086 CSR_WRITE_4(sc, RL_TXCFG, 3087 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3088 else 3089 CSR_WRITE_4(sc, RL_TXCFG, 3090 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3091 } else 3092 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3093 3094 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3095 3096 /* 3097 * Set the initial RX configuration. 3098 */ 3099 re_set_rxmode(sc); 3100 3101 /* Configure interrupt moderation. */ 3102 if (sc->rl_type == RL_8169) { 3103 /* Magic from vendor. */ 3104 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3105 } 3106 3107#ifdef DEVICE_POLLING 3108 /* 3109 * Disable interrupts if we are polling. 3110 */ 3111 if (ifp->if_capenable & IFCAP_POLLING) 3112 CSR_WRITE_2(sc, RL_IMR, 0); 3113 else /* otherwise ... */ 3114#endif 3115 3116 /* 3117 * Enable interrupts. 3118 */ 3119 if (sc->rl_testmode) 3120 CSR_WRITE_2(sc, RL_IMR, 0); 3121 else 3122 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3123 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3124 3125 /* Set initial TX threshold */ 3126 sc->rl_txthresh = RL_TX_THRESH_INIT; 3127 3128 /* Start RX/TX process. */ 3129 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3130#ifdef notdef 3131 /* Enable receiver and transmitter. */ 3132 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3133#endif 3134 3135 /* 3136 * Initialize the timer interrupt register so that 3137 * a timer interrupt will be generated once the timer 3138 * reaches a certain number of ticks. The timer is 3139 * reloaded on each transmit. 3140 */ 3141#ifdef RE_TX_MODERATION 3142 /* 3143 * Use timer interrupt register to moderate TX interrupt 3144 * moderation, which dramatically improves TX frame rate. 3145 */ 3146 if (sc->rl_type == RL_8169) 3147 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3148 else 3149 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3150#else 3151 /* 3152 * Use timer interrupt register to moderate RX interrupt 3153 * moderation. 3154 */ 3155 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3156 intr_filter == 0) { 3157 if (sc->rl_type == RL_8169) 3158 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3159 RL_USECS(sc->rl_int_rx_mod)); 3160 } else { 3161 if (sc->rl_type == RL_8169) 3162 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3163 } 3164#endif 3165 3166 /* 3167 * For 8169 gigE NICs, set the max allowed RX packet 3168 * size so we can receive jumbo frames. 3169 */ 3170 if (sc->rl_type == RL_8169) { 3171 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3172 /* 3173 * For controllers that use new jumbo frame scheme, 3174 * set maximum size of jumbo frame depedning on 3175 * controller revisions. 3176 */ 3177 if (ifp->if_mtu > RL_MTU) 3178 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3179 sc->rl_hwrev->rl_max_mtu + 3180 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3181 ETHER_CRC_LEN); 3182 else 3183 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3184 RE_RX_DESC_BUFLEN); 3185 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3186 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3187 /* RTL810x has no jumbo frame support. */ 3188 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3189 } else 3190 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3191 } 3192 3193 if (sc->rl_testmode) 3194 return; 3195 3196 mii_mediachg(mii); 3197 3198 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 3199 3200 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3201 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3202 3203 sc->rl_flags &= ~RL_FLAG_LINK; 3204 sc->rl_watchdog_timer = 0; 3205 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3206} 3207 3208/* 3209 * Set media options. 3210 */ 3211static int 3212re_ifmedia_upd(struct ifnet *ifp) 3213{ 3214 struct rl_softc *sc; 3215 struct mii_data *mii; 3216 int error; 3217 3218 sc = ifp->if_softc; 3219 mii = device_get_softc(sc->rl_miibus); 3220 RL_LOCK(sc); 3221 error = mii_mediachg(mii); 3222 RL_UNLOCK(sc); 3223 3224 return (error); 3225} 3226 3227/* 3228 * Report current media status. 3229 */ 3230static void 3231re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3232{ 3233 struct rl_softc *sc; 3234 struct mii_data *mii; 3235 3236 sc = ifp->if_softc; 3237 mii = device_get_softc(sc->rl_miibus); 3238 3239 RL_LOCK(sc); 3240 mii_pollstat(mii); 3241 ifmr->ifm_active = mii->mii_media_active; 3242 ifmr->ifm_status = mii->mii_media_status; 3243 RL_UNLOCK(sc); 3244} 3245 3246static int 3247re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3248{ 3249 struct rl_softc *sc = ifp->if_softc; 3250 struct ifreq *ifr = (struct ifreq *) data; 3251 struct mii_data *mii; 3252 uint32_t rev; 3253 int error = 0; 3254 3255 switch (command) { 3256 case SIOCSIFMTU: 3257 if (ifr->ifr_mtu < ETHERMIN || 3258 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) { 3259 error = EINVAL; 3260 break; 3261 } 3262 RL_LOCK(sc); 3263 if (ifp->if_mtu != ifr->ifr_mtu) { 3264 ifp->if_mtu = ifr->ifr_mtu; 3265 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3266 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3267 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3268 re_init_locked(sc); 3269 } 3270 if (ifp->if_mtu > RL_TSO_MTU && 3271 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3272 ifp->if_capenable &= ~(IFCAP_TSO4 | 3273 IFCAP_VLAN_HWTSO); 3274 ifp->if_hwassist &= ~CSUM_TSO; 3275 } 3276 VLAN_CAPABILITIES(ifp); 3277 } 3278 RL_UNLOCK(sc); 3279 break; 3280 case SIOCSIFFLAGS: 3281 RL_LOCK(sc); 3282 if ((ifp->if_flags & IFF_UP) != 0) { 3283 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3284 if (((ifp->if_flags ^ sc->rl_if_flags) 3285 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3286 re_set_rxmode(sc); 3287 } else 3288 re_init_locked(sc); 3289 } else { 3290 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3291 re_stop(sc); 3292 } 3293 sc->rl_if_flags = ifp->if_flags; 3294 RL_UNLOCK(sc); 3295 break; 3296 case SIOCADDMULTI: 3297 case SIOCDELMULTI: 3298 RL_LOCK(sc); 3299 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3300 re_set_rxmode(sc); 3301 RL_UNLOCK(sc); 3302 break; 3303 case SIOCGIFMEDIA: 3304 case SIOCSIFMEDIA: 3305 mii = device_get_softc(sc->rl_miibus); 3306 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3307 break; 3308 case SIOCSIFCAP: 3309 { 3310 int mask, reinit; 3311 3312 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3313 reinit = 0; 3314#ifdef DEVICE_POLLING 3315 if (mask & IFCAP_POLLING) { 3316 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3317 error = ether_poll_register(re_poll, ifp); 3318 if (error) 3319 return (error); 3320 RL_LOCK(sc); 3321 /* Disable interrupts */ 3322 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3323 ifp->if_capenable |= IFCAP_POLLING; 3324 RL_UNLOCK(sc); 3325 } else { 3326 error = ether_poll_deregister(ifp); 3327 /* Enable interrupts. */ 3328 RL_LOCK(sc); 3329 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3330 ifp->if_capenable &= ~IFCAP_POLLING; 3331 RL_UNLOCK(sc); 3332 } 3333 } 3334#endif /* DEVICE_POLLING */ 3335 RL_LOCK(sc); 3336 if ((mask & IFCAP_TXCSUM) != 0 && 3337 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3338 ifp->if_capenable ^= IFCAP_TXCSUM; 3339 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3340 rev = sc->rl_hwrev->rl_rev; 3341 if (rev == RL_HWREV_8168C || 3342 rev == RL_HWREV_8168C_SPIN2) 3343 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3344 else 3345 ifp->if_hwassist |= RE_CSUM_FEATURES; 3346 } else 3347 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3348 reinit = 1; 3349 } 3350 if ((mask & IFCAP_RXCSUM) != 0 && 3351 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3352 ifp->if_capenable ^= IFCAP_RXCSUM; 3353 reinit = 1; 3354 } 3355 if ((mask & IFCAP_TSO4) != 0 && 3356 (ifp->if_capabilities & IFCAP_TSO) != 0) { 3357 ifp->if_capenable ^= IFCAP_TSO4; 3358 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3359 ifp->if_hwassist |= CSUM_TSO; 3360 else 3361 ifp->if_hwassist &= ~CSUM_TSO; 3362 if (ifp->if_mtu > RL_TSO_MTU && 3363 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3364 ifp->if_capenable &= ~IFCAP_TSO4; 3365 ifp->if_hwassist &= ~CSUM_TSO; 3366 } 3367 } 3368 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3369 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3370 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3371 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3372 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3373 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3374 /* TSO over VLAN requires VLAN hardware tagging. */ 3375 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3376 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3377 reinit = 1; 3378 } 3379 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3380 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3381 IFCAP_VLAN_HWTSO)) != 0) 3382 reinit = 1; 3383 if ((mask & IFCAP_WOL) != 0 && 3384 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3385 if ((mask & IFCAP_WOL_UCAST) != 0) 3386 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3387 if ((mask & IFCAP_WOL_MCAST) != 0) 3388 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3389 if ((mask & IFCAP_WOL_MAGIC) != 0) 3390 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3391 } 3392 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3393 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3394 re_init_locked(sc); 3395 } 3396 RL_UNLOCK(sc); 3397 VLAN_CAPABILITIES(ifp); 3398 } 3399 break; 3400 default: 3401 error = ether_ioctl(ifp, command, data); 3402 break; 3403 } 3404 3405 return (error); 3406} 3407 3408static void 3409re_watchdog(struct rl_softc *sc) 3410{ 3411 struct ifnet *ifp; 3412 3413 RL_LOCK_ASSERT(sc); 3414 3415 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3416 return; 3417 3418 ifp = sc->rl_ifp; 3419 re_txeof(sc); 3420 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3421 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3422 "-- recovering\n"); 3423 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3424 re_start_locked(ifp); 3425 return; 3426 } 3427 3428 if_printf(ifp, "watchdog timeout\n"); 3429 ifp->if_oerrors++; 3430 3431 re_rxeof(sc, NULL); 3432 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3433 re_init_locked(sc); 3434 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3435 re_start_locked(ifp); 3436} 3437 3438/* 3439 * Stop the adapter and free any mbufs allocated to the 3440 * RX and TX lists. 3441 */ 3442static void 3443re_stop(struct rl_softc *sc) 3444{ 3445 int i; 3446 struct ifnet *ifp; 3447 struct rl_txdesc *txd; 3448 struct rl_rxdesc *rxd; 3449 3450 RL_LOCK_ASSERT(sc); 3451 3452 ifp = sc->rl_ifp; 3453 3454 sc->rl_watchdog_timer = 0; 3455 callout_stop(&sc->rl_stat_callout); 3456 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3457 3458 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 3459 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3460 RL_CMD_RX_ENB); 3461 else 3462 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3463 DELAY(1000); 3464 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3465 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3466 3467 if (sc->rl_head != NULL) { 3468 m_freem(sc->rl_head); 3469 sc->rl_head = sc->rl_tail = NULL; 3470 } 3471 3472 /* Free the TX list buffers. */ 3473 3474 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3475 txd = &sc->rl_ldata.rl_tx_desc[i]; 3476 if (txd->tx_m != NULL) { 3477 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3478 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3479 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3480 txd->tx_dmamap); 3481 m_freem(txd->tx_m); 3482 txd->tx_m = NULL; 3483 } 3484 } 3485 3486 /* Free the RX list buffers. */ 3487 3488 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3489 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3490 if (rxd->rx_m != NULL) { 3491 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3492 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3493 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3494 rxd->rx_dmamap); 3495 m_freem(rxd->rx_m); 3496 rxd->rx_m = NULL; 3497 } 3498 } 3499} 3500 3501/* 3502 * Device suspend routine. Stop the interface and save some PCI 3503 * settings in case the BIOS doesn't restore them properly on 3504 * resume. 3505 */ 3506static int 3507re_suspend(device_t dev) 3508{ 3509 struct rl_softc *sc; 3510 3511 sc = device_get_softc(dev); 3512 3513 RL_LOCK(sc); 3514 re_stop(sc); 3515 re_setwol(sc); 3516 sc->suspended = 1; 3517 RL_UNLOCK(sc); 3518 3519 return (0); 3520} 3521 3522/* 3523 * Device resume routine. Restore some PCI settings in case the BIOS 3524 * doesn't, re-enable busmastering, and restart the interface if 3525 * appropriate. 3526 */ 3527static int 3528re_resume(device_t dev) 3529{ 3530 struct rl_softc *sc; 3531 struct ifnet *ifp; 3532 3533 sc = device_get_softc(dev); 3534 3535 RL_LOCK(sc); 3536 3537 ifp = sc->rl_ifp; 3538 /* Take controller out of sleep mode. */ 3539 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3540 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3541 CSR_WRITE_1(sc, RL_GPIO, 3542 CSR_READ_1(sc, RL_GPIO) | 0x01); 3543 } 3544 3545 /* 3546 * Clear WOL matching such that normal Rx filtering 3547 * wouldn't interfere with WOL patterns. 3548 */ 3549 re_clrwol(sc); 3550 3551 /* reinitialize interface if necessary */ 3552 if (ifp->if_flags & IFF_UP) 3553 re_init_locked(sc); 3554 3555 sc->suspended = 0; 3556 RL_UNLOCK(sc); 3557 3558 return (0); 3559} 3560 3561/* 3562 * Stop all chip I/O so that the kernel's probe routines don't 3563 * get confused by errant DMAs when rebooting. 3564 */ 3565static int 3566re_shutdown(device_t dev) 3567{ 3568 struct rl_softc *sc; 3569 3570 sc = device_get_softc(dev); 3571 3572 RL_LOCK(sc); 3573 re_stop(sc); 3574 /* 3575 * Mark interface as down since otherwise we will panic if 3576 * interrupt comes in later on, which can happen in some 3577 * cases. 3578 */ 3579 sc->rl_ifp->if_flags &= ~IFF_UP; 3580 re_setwol(sc); 3581 RL_UNLOCK(sc); 3582 3583 return (0); 3584} 3585 3586static void 3587re_setwol(struct rl_softc *sc) 3588{ 3589 struct ifnet *ifp; 3590 int pmc; 3591 uint16_t pmstat; 3592 uint8_t v; 3593 3594 RL_LOCK_ASSERT(sc); 3595 3596 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3597 return; 3598 3599 ifp = sc->rl_ifp; 3600 /* Put controller into sleep mode. */ 3601 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3602 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3603 CSR_WRITE_1(sc, RL_GPIO, 3604 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3605 } 3606 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3607 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3608 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3609 /* Enable config register write. */ 3610 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3611 3612 /* Enable PME. */ 3613 v = CSR_READ_1(sc, RL_CFG1); 3614 v &= ~RL_CFG1_PME; 3615 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3616 v |= RL_CFG1_PME; 3617 CSR_WRITE_1(sc, RL_CFG1, v); 3618 3619 v = CSR_READ_1(sc, RL_CFG3); 3620 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3621 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3622 v |= RL_CFG3_WOL_MAGIC; 3623 CSR_WRITE_1(sc, RL_CFG3, v); 3624 3625 /* Config register write done. */ 3626 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3627 3628 v = CSR_READ_1(sc, RL_CFG5); 3629 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3630 v &= ~RL_CFG5_WOL_LANWAKE; 3631 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3632 v |= RL_CFG5_WOL_UCAST; 3633 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3634 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3635 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3636 v |= RL_CFG5_WOL_LANWAKE; 3637 CSR_WRITE_1(sc, RL_CFG5, v); 3638 3639 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3640 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3641 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3642 /* 3643 * It seems that hardware resets its link speed to 100Mbps in 3644 * power down mode so switching to 100Mbps in driver is not 3645 * needed. 3646 */ 3647 3648 /* Request PME if WOL is requested. */ 3649 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3650 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3651 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3652 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3653 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3654} 3655 3656static void 3657re_clrwol(struct rl_softc *sc) 3658{ 3659 int pmc; 3660 uint8_t v; 3661 3662 RL_LOCK_ASSERT(sc); 3663 3664 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3665 return; 3666 3667 /* Enable config register write. */ 3668 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3669 3670 v = CSR_READ_1(sc, RL_CFG3); 3671 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3672 CSR_WRITE_1(sc, RL_CFG3, v); 3673 3674 /* Config register write done. */ 3675 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3676 3677 v = CSR_READ_1(sc, RL_CFG5); 3678 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3679 v &= ~RL_CFG5_WOL_LANWAKE; 3680 CSR_WRITE_1(sc, RL_CFG5, v); 3681} 3682 3683static void 3684re_add_sysctls(struct rl_softc *sc) 3685{ 3686 struct sysctl_ctx_list *ctx; 3687 struct sysctl_oid_list *children; 3688 int error; 3689 3690 ctx = device_get_sysctl_ctx(sc->rl_dev); 3691 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3692 3693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3694 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3695 "Statistics Information"); 3696 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3697 return; 3698 3699 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3700 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3701 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3702 /* Pull in device tunables. */ 3703 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3704 error = resource_int_value(device_get_name(sc->rl_dev), 3705 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3706 if (error == 0) { 3707 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3708 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3709 device_printf(sc->rl_dev, "int_rx_mod value out of " 3710 "range; using default: %d\n", 3711 RL_TIMER_DEFAULT); 3712 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3713 } 3714 } 3715 3716} 3717 3718static int 3719re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3720{ 3721 struct rl_softc *sc; 3722 struct rl_stats *stats; 3723 int error, i, result; 3724 3725 result = -1; 3726 error = sysctl_handle_int(oidp, &result, 0, req); 3727 if (error || req->newptr == NULL) 3728 return (error); 3729 3730 if (result == 1) { 3731 sc = (struct rl_softc *)arg1; 3732 RL_LOCK(sc); 3733 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3734 RL_UNLOCK(sc); 3735 goto done; 3736 } 3737 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3738 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3739 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3740 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3741 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3742 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3743 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3744 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3745 RL_DUMPSTATS_START)); 3746 for (i = RL_TIMEOUT; i > 0; i--) { 3747 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3748 RL_DUMPSTATS_START) == 0) 3749 break; 3750 DELAY(1000); 3751 } 3752 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3753 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3754 RL_UNLOCK(sc); 3755 if (i == 0) { 3756 device_printf(sc->rl_dev, 3757 "DUMP statistics request timedout\n"); 3758 return (ETIMEDOUT); 3759 } 3760done: 3761 stats = sc->rl_ldata.rl_stats; 3762 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3763 printf("Tx frames : %ju\n", 3764 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3765 printf("Rx frames : %ju\n", 3766 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3767 printf("Tx errors : %ju\n", 3768 (uintmax_t)le64toh(stats->rl_tx_errs)); 3769 printf("Rx errors : %u\n", 3770 le32toh(stats->rl_rx_errs)); 3771 printf("Rx missed frames : %u\n", 3772 (uint32_t)le16toh(stats->rl_missed_pkts)); 3773 printf("Rx frame alignment errs : %u\n", 3774 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3775 printf("Tx single collisions : %u\n", 3776 le32toh(stats->rl_tx_onecoll)); 3777 printf("Tx multiple collisions : %u\n", 3778 le32toh(stats->rl_tx_multicolls)); 3779 printf("Rx unicast frames : %ju\n", 3780 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3781 printf("Rx broadcast frames : %ju\n", 3782 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3783 printf("Rx multicast frames : %u\n", 3784 le32toh(stats->rl_rx_mcasts)); 3785 printf("Tx aborts : %u\n", 3786 (uint32_t)le16toh(stats->rl_tx_aborts)); 3787 printf("Tx underruns : %u\n", 3788 (uint32_t)le16toh(stats->rl_rx_underruns)); 3789 } 3790 3791 return (error); 3792} 3793 3794static int 3795sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3796{ 3797 int error, value; 3798 3799 if (arg1 == NULL) 3800 return (EINVAL); 3801 value = *(int *)arg1; 3802 error = sysctl_handle_int(oidp, &value, 0, req); 3803 if (error || req->newptr == NULL) 3804 return (error); 3805 if (value < low || value > high) 3806 return (EINVAL); 3807 *(int *)arg1 = value; 3808 3809 return (0); 3810} 3811 3812static int 3813sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 3814{ 3815 3816 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 3817 RL_TIMER_MAX)); 3818} 3819