if_re.c revision 217766
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 217766 2011-01-24 00:01:06Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/sysctl.h> 127#include <sys/taskqueue.h> 128 129#include <net/if.h> 130#include <net/if_arp.h> 131#include <net/ethernet.h> 132#include <net/if_dl.h> 133#include <net/if_media.h> 134#include <net/if_types.h> 135#include <net/if_vlan_var.h> 136 137#include <net/bpf.h> 138 139#include <machine/bus.h> 140#include <machine/resource.h> 141#include <sys/bus.h> 142#include <sys/rman.h> 143 144#include <dev/mii/mii.h> 145#include <dev/mii/miivar.h> 146 147#include <dev/pci/pcireg.h> 148#include <dev/pci/pcivar.h> 149 150#include <pci/if_rlreg.h> 151 152MODULE_DEPEND(re, pci, 1, 1, 1); 153MODULE_DEPEND(re, ether, 1, 1, 1); 154MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156/* "device miibus" required. See GENERIC if you get errors here. */ 157#include "miibus_if.h" 158 159/* Tunables. */ 160static int msi_disable = 0; 161TUNABLE_INT("hw.re.msi_disable", &msi_disable); 162static int prefer_iomap = 0; 163TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 164 165#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 166 167/* 168 * Various supported device vendors/types and their names. 169 */ 170static struct rl_type re_devs[] = { 171 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 172 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 173 { RT_VENDORID, RT_DEVICEID_8139, 0, 174 "RealTek 8139C+ 10/100BaseTX" }, 175 { RT_VENDORID, RT_DEVICEID_8101E, 0, 176 "RealTek 8101E/8102E/8102EL/8103E PCIe 10/100baseTX" }, 177 { RT_VENDORID, RT_DEVICEID_8168, 0, 178 "RealTek 8168/8111 B/C/CP/D/DP/E PCIe Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, 0, 180 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 184 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 185 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 186 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 187 { USR_VENDORID, USR_DEVICEID_997902, 0, 188 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 189}; 190 191static struct rl_hwrev re_hwrevs[] = { 192 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 193 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 194 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 195 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 196 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 197 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 198 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 199 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 200 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 201 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 202 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 203 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 204 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 205 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 206 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 207 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 208 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 209 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 210 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 211 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 212 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 213 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 214 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 215 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 216 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 217 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 218 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 219 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 220 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 221 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 222 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 223 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 224 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 225 { 0, 0, NULL, 0 } 226}; 227 228static int re_probe (device_t); 229static int re_attach (device_t); 230static int re_detach (device_t); 231 232static int re_encap (struct rl_softc *, struct mbuf **); 233 234static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 235static int re_allocmem (device_t, struct rl_softc *); 236static __inline void re_discard_rxbuf 237 (struct rl_softc *, int); 238static int re_newbuf (struct rl_softc *, int); 239static int re_jumbo_newbuf (struct rl_softc *, int); 240static int re_rx_list_init (struct rl_softc *); 241static int re_jrx_list_init (struct rl_softc *); 242static int re_tx_list_init (struct rl_softc *); 243#ifdef RE_FIXUP_RX 244static __inline void re_fixup_rx 245 (struct mbuf *); 246#endif 247static int re_rxeof (struct rl_softc *, int *); 248static void re_txeof (struct rl_softc *); 249#ifdef DEVICE_POLLING 250static int re_poll (struct ifnet *, enum poll_cmd, int); 251static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 252#endif 253static int re_intr (void *); 254static void re_tick (void *); 255static void re_tx_task (void *, int); 256static void re_int_task (void *, int); 257static void re_start (struct ifnet *); 258static int re_ioctl (struct ifnet *, u_long, caddr_t); 259static void re_init (void *); 260static void re_init_locked (struct rl_softc *); 261static void re_stop (struct rl_softc *); 262static void re_watchdog (struct rl_softc *); 263static int re_suspend (device_t); 264static int re_resume (device_t); 265static int re_shutdown (device_t); 266static int re_ifmedia_upd (struct ifnet *); 267static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 268 269static void re_eeprom_putbyte (struct rl_softc *, int); 270static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 271static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 272static int re_gmii_readreg (device_t, int, int); 273static int re_gmii_writereg (device_t, int, int, int); 274 275static int re_miibus_readreg (device_t, int, int); 276static int re_miibus_writereg (device_t, int, int, int); 277static void re_miibus_statchg (device_t); 278 279static void re_set_jumbo (struct rl_softc *, int); 280static void re_set_rxmode (struct rl_softc *); 281static void re_reset (struct rl_softc *); 282static void re_setwol (struct rl_softc *); 283static void re_clrwol (struct rl_softc *); 284 285#ifdef RE_DIAG 286static int re_diag (struct rl_softc *); 287#endif 288 289static void re_add_sysctls (struct rl_softc *); 290static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 291 292static device_method_t re_methods[] = { 293 /* Device interface */ 294 DEVMETHOD(device_probe, re_probe), 295 DEVMETHOD(device_attach, re_attach), 296 DEVMETHOD(device_detach, re_detach), 297 DEVMETHOD(device_suspend, re_suspend), 298 DEVMETHOD(device_resume, re_resume), 299 DEVMETHOD(device_shutdown, re_shutdown), 300 301 /* bus interface */ 302 DEVMETHOD(bus_print_child, bus_generic_print_child), 303 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 304 305 /* MII interface */ 306 DEVMETHOD(miibus_readreg, re_miibus_readreg), 307 DEVMETHOD(miibus_writereg, re_miibus_writereg), 308 DEVMETHOD(miibus_statchg, re_miibus_statchg), 309 310 { 0, 0 } 311}; 312 313static driver_t re_driver = { 314 "re", 315 re_methods, 316 sizeof(struct rl_softc) 317}; 318 319static devclass_t re_devclass; 320 321DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 322DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 323 324#define EE_SET(x) \ 325 CSR_WRITE_1(sc, RL_EECMD, \ 326 CSR_READ_1(sc, RL_EECMD) | x) 327 328#define EE_CLR(x) \ 329 CSR_WRITE_1(sc, RL_EECMD, \ 330 CSR_READ_1(sc, RL_EECMD) & ~x) 331 332/* 333 * Send a read command and address to the EEPROM, check for ACK. 334 */ 335static void 336re_eeprom_putbyte(struct rl_softc *sc, int addr) 337{ 338 int d, i; 339 340 d = addr | (RL_9346_READ << sc->rl_eewidth); 341 342 /* 343 * Feed in each bit and strobe the clock. 344 */ 345 346 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 347 if (d & i) { 348 EE_SET(RL_EE_DATAIN); 349 } else { 350 EE_CLR(RL_EE_DATAIN); 351 } 352 DELAY(100); 353 EE_SET(RL_EE_CLK); 354 DELAY(150); 355 EE_CLR(RL_EE_CLK); 356 DELAY(100); 357 } 358} 359 360/* 361 * Read a word of data stored in the EEPROM at address 'addr.' 362 */ 363static void 364re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 365{ 366 int i; 367 u_int16_t word = 0; 368 369 /* 370 * Send address of word we want to read. 371 */ 372 re_eeprom_putbyte(sc, addr); 373 374 /* 375 * Start reading bits from EEPROM. 376 */ 377 for (i = 0x8000; i; i >>= 1) { 378 EE_SET(RL_EE_CLK); 379 DELAY(100); 380 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 381 word |= i; 382 EE_CLR(RL_EE_CLK); 383 DELAY(100); 384 } 385 386 *dest = word; 387} 388 389/* 390 * Read a sequence of words from the EEPROM. 391 */ 392static void 393re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 394{ 395 int i; 396 u_int16_t word = 0, *ptr; 397 398 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 399 400 DELAY(100); 401 402 for (i = 0; i < cnt; i++) { 403 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 404 re_eeprom_getword(sc, off + i, &word); 405 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 406 ptr = (u_int16_t *)(dest + (i * 2)); 407 *ptr = word; 408 } 409 410 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 411} 412 413static int 414re_gmii_readreg(device_t dev, int phy, int reg) 415{ 416 struct rl_softc *sc; 417 u_int32_t rval; 418 int i; 419 420 sc = device_get_softc(dev); 421 422 /* Let the rgephy driver read the GMEDIASTAT register */ 423 424 if (reg == RL_GMEDIASTAT) { 425 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 426 return (rval); 427 } 428 429 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 430 431 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 432 rval = CSR_READ_4(sc, RL_PHYAR); 433 if (rval & RL_PHYAR_BUSY) 434 break; 435 DELAY(25); 436 } 437 438 if (i == RL_PHY_TIMEOUT) { 439 device_printf(sc->rl_dev, "PHY read failed\n"); 440 return (0); 441 } 442 443 /* 444 * Controller requires a 20us delay to process next MDIO request. 445 */ 446 DELAY(20); 447 448 return (rval & RL_PHYAR_PHYDATA); 449} 450 451static int 452re_gmii_writereg(device_t dev, int phy, int reg, int data) 453{ 454 struct rl_softc *sc; 455 u_int32_t rval; 456 int i; 457 458 sc = device_get_softc(dev); 459 460 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 461 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 462 463 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 464 rval = CSR_READ_4(sc, RL_PHYAR); 465 if (!(rval & RL_PHYAR_BUSY)) 466 break; 467 DELAY(25); 468 } 469 470 if (i == RL_PHY_TIMEOUT) { 471 device_printf(sc->rl_dev, "PHY write failed\n"); 472 return (0); 473 } 474 475 /* 476 * Controller requires a 20us delay to process next MDIO request. 477 */ 478 DELAY(20); 479 480 return (0); 481} 482 483static int 484re_miibus_readreg(device_t dev, int phy, int reg) 485{ 486 struct rl_softc *sc; 487 u_int16_t rval = 0; 488 u_int16_t re8139_reg = 0; 489 490 sc = device_get_softc(dev); 491 492 if (sc->rl_type == RL_8169) { 493 rval = re_gmii_readreg(dev, phy, reg); 494 return (rval); 495 } 496 497 switch (reg) { 498 case MII_BMCR: 499 re8139_reg = RL_BMCR; 500 break; 501 case MII_BMSR: 502 re8139_reg = RL_BMSR; 503 break; 504 case MII_ANAR: 505 re8139_reg = RL_ANAR; 506 break; 507 case MII_ANER: 508 re8139_reg = RL_ANER; 509 break; 510 case MII_ANLPAR: 511 re8139_reg = RL_LPAR; 512 break; 513 case MII_PHYIDR1: 514 case MII_PHYIDR2: 515 return (0); 516 /* 517 * Allow the rlphy driver to read the media status 518 * register. If we have a link partner which does not 519 * support NWAY, this is the register which will tell 520 * us the results of parallel detection. 521 */ 522 case RL_MEDIASTAT: 523 rval = CSR_READ_1(sc, RL_MEDIASTAT); 524 return (rval); 525 default: 526 device_printf(sc->rl_dev, "bad phy register\n"); 527 return (0); 528 } 529 rval = CSR_READ_2(sc, re8139_reg); 530 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 531 /* 8139C+ has different bit layout. */ 532 rval &= ~(BMCR_LOOP | BMCR_ISO); 533 } 534 return (rval); 535} 536 537static int 538re_miibus_writereg(device_t dev, int phy, int reg, int data) 539{ 540 struct rl_softc *sc; 541 u_int16_t re8139_reg = 0; 542 int rval = 0; 543 544 sc = device_get_softc(dev); 545 546 if (sc->rl_type == RL_8169) { 547 rval = re_gmii_writereg(dev, phy, reg, data); 548 return (rval); 549 } 550 551 switch (reg) { 552 case MII_BMCR: 553 re8139_reg = RL_BMCR; 554 if (sc->rl_type == RL_8139CPLUS) { 555 /* 8139C+ has different bit layout. */ 556 data &= ~(BMCR_LOOP | BMCR_ISO); 557 } 558 break; 559 case MII_BMSR: 560 re8139_reg = RL_BMSR; 561 break; 562 case MII_ANAR: 563 re8139_reg = RL_ANAR; 564 break; 565 case MII_ANER: 566 re8139_reg = RL_ANER; 567 break; 568 case MII_ANLPAR: 569 re8139_reg = RL_LPAR; 570 break; 571 case MII_PHYIDR1: 572 case MII_PHYIDR2: 573 return (0); 574 break; 575 default: 576 device_printf(sc->rl_dev, "bad phy register\n"); 577 return (0); 578 } 579 CSR_WRITE_2(sc, re8139_reg, data); 580 return (0); 581} 582 583static void 584re_miibus_statchg(device_t dev) 585{ 586 struct rl_softc *sc; 587 struct ifnet *ifp; 588 struct mii_data *mii; 589 590 sc = device_get_softc(dev); 591 mii = device_get_softc(sc->rl_miibus); 592 ifp = sc->rl_ifp; 593 if (mii == NULL || ifp == NULL || 594 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 595 return; 596 597 sc->rl_flags &= ~RL_FLAG_LINK; 598 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 599 (IFM_ACTIVE | IFM_AVALID)) { 600 switch (IFM_SUBTYPE(mii->mii_media_active)) { 601 case IFM_10_T: 602 case IFM_100_TX: 603 sc->rl_flags |= RL_FLAG_LINK; 604 break; 605 case IFM_1000_T: 606 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 607 break; 608 sc->rl_flags |= RL_FLAG_LINK; 609 break; 610 default: 611 break; 612 } 613 } 614 /* 615 * RealTek controllers does not provide any interface to 616 * Tx/Rx MACs for resolved speed, duplex and flow-control 617 * parameters. 618 */ 619} 620 621/* 622 * Set the RX configuration and 64-bit multicast hash filter. 623 */ 624static void 625re_set_rxmode(struct rl_softc *sc) 626{ 627 struct ifnet *ifp; 628 struct ifmultiaddr *ifma; 629 uint32_t hashes[2] = { 0, 0 }; 630 uint32_t h, rxfilt; 631 632 RL_LOCK_ASSERT(sc); 633 634 ifp = sc->rl_ifp; 635 636 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 637 638 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 639 if (ifp->if_flags & IFF_PROMISC) 640 rxfilt |= RL_RXCFG_RX_ALLPHYS; 641 /* 642 * Unlike other hardwares, we have to explicitly set 643 * RL_RXCFG_RX_MULTI to receive multicast frames in 644 * promiscuous mode. 645 */ 646 rxfilt |= RL_RXCFG_RX_MULTI; 647 hashes[0] = hashes[1] = 0xffffffff; 648 goto done; 649 } 650 651 if_maddr_rlock(ifp); 652 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 653 if (ifma->ifma_addr->sa_family != AF_LINK) 654 continue; 655 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 656 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 657 if (h < 32) 658 hashes[0] |= (1 << h); 659 else 660 hashes[1] |= (1 << (h - 32)); 661 } 662 if_maddr_runlock(ifp); 663 664 if (hashes[0] != 0 || hashes[1] != 0) { 665 /* 666 * For some unfathomable reason, RealTek decided to 667 * reverse the order of the multicast hash registers 668 * in the PCI Express parts. This means we have to 669 * write the hash pattern in reverse order for those 670 * devices. 671 */ 672 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 673 h = bswap32(hashes[0]); 674 hashes[0] = bswap32(hashes[1]); 675 hashes[1] = h; 676 } 677 rxfilt |= RL_RXCFG_RX_MULTI; 678 } 679 680done: 681 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 682 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 683 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 684} 685 686static void 687re_reset(struct rl_softc *sc) 688{ 689 int i; 690 691 RL_LOCK_ASSERT(sc); 692 693 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 694 695 for (i = 0; i < RL_TIMEOUT; i++) { 696 DELAY(10); 697 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 698 break; 699 } 700 if (i == RL_TIMEOUT) 701 device_printf(sc->rl_dev, "reset never completed!\n"); 702 703 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 704 CSR_WRITE_1(sc, 0x82, 1); 705 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 706 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 707} 708 709#ifdef RE_DIAG 710 711/* 712 * The following routine is designed to test for a defect on some 713 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 714 * lines connected to the bus, however for a 32-bit only card, they 715 * should be pulled high. The result of this defect is that the 716 * NIC will not work right if you plug it into a 64-bit slot: DMA 717 * operations will be done with 64-bit transfers, which will fail 718 * because the 64-bit data lines aren't connected. 719 * 720 * There's no way to work around this (short of talking a soldering 721 * iron to the board), however we can detect it. The method we use 722 * here is to put the NIC into digital loopback mode, set the receiver 723 * to promiscuous mode, and then try to send a frame. We then compare 724 * the frame data we sent to what was received. If the data matches, 725 * then the NIC is working correctly, otherwise we know the user has 726 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 727 * slot. In the latter case, there's no way the NIC can work correctly, 728 * so we print out a message on the console and abort the device attach. 729 */ 730 731static int 732re_diag(struct rl_softc *sc) 733{ 734 struct ifnet *ifp = sc->rl_ifp; 735 struct mbuf *m0; 736 struct ether_header *eh; 737 struct rl_desc *cur_rx; 738 u_int16_t status; 739 u_int32_t rxstat; 740 int total_len, i, error = 0, phyaddr; 741 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 742 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 743 744 /* Allocate a single mbuf */ 745 MGETHDR(m0, M_DONTWAIT, MT_DATA); 746 if (m0 == NULL) 747 return (ENOBUFS); 748 749 RL_LOCK(sc); 750 751 /* 752 * Initialize the NIC in test mode. This sets the chip up 753 * so that it can send and receive frames, but performs the 754 * following special functions: 755 * - Puts receiver in promiscuous mode 756 * - Enables digital loopback mode 757 * - Leaves interrupts turned off 758 */ 759 760 ifp->if_flags |= IFF_PROMISC; 761 sc->rl_testmode = 1; 762 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 763 re_init_locked(sc); 764 sc->rl_flags |= RL_FLAG_LINK; 765 if (sc->rl_type == RL_8169) 766 phyaddr = 1; 767 else 768 phyaddr = 0; 769 770 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 771 for (i = 0; i < RL_TIMEOUT; i++) { 772 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 773 if (!(status & BMCR_RESET)) 774 break; 775 } 776 777 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 778 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 779 780 DELAY(100000); 781 782 /* Put some data in the mbuf */ 783 784 eh = mtod(m0, struct ether_header *); 785 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 786 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 787 eh->ether_type = htons(ETHERTYPE_IP); 788 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 789 790 /* 791 * Queue the packet, start transmission. 792 * Note: IF_HANDOFF() ultimately calls re_start() for us. 793 */ 794 795 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 796 RL_UNLOCK(sc); 797 /* XXX: re_diag must not be called when in ALTQ mode */ 798 IF_HANDOFF(&ifp->if_snd, m0, ifp); 799 RL_LOCK(sc); 800 m0 = NULL; 801 802 /* Wait for it to propagate through the chip */ 803 804 DELAY(100000); 805 for (i = 0; i < RL_TIMEOUT; i++) { 806 status = CSR_READ_2(sc, RL_ISR); 807 CSR_WRITE_2(sc, RL_ISR, status); 808 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 809 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 810 break; 811 DELAY(10); 812 } 813 814 if (i == RL_TIMEOUT) { 815 device_printf(sc->rl_dev, 816 "diagnostic failed, failed to receive packet in" 817 " loopback mode\n"); 818 error = EIO; 819 goto done; 820 } 821 822 /* 823 * The packet should have been dumped into the first 824 * entry in the RX DMA ring. Grab it from there. 825 */ 826 827 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 828 sc->rl_ldata.rl_rx_list_map, 829 BUS_DMASYNC_POSTREAD); 830 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 831 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 832 BUS_DMASYNC_POSTREAD); 833 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 834 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 835 836 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 837 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 838 eh = mtod(m0, struct ether_header *); 839 840 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 841 total_len = RL_RXBYTES(cur_rx); 842 rxstat = le32toh(cur_rx->rl_cmdstat); 843 844 if (total_len != ETHER_MIN_LEN) { 845 device_printf(sc->rl_dev, 846 "diagnostic failed, received short packet\n"); 847 error = EIO; 848 goto done; 849 } 850 851 /* Test that the received packet data matches what we sent. */ 852 853 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 854 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 855 ntohs(eh->ether_type) != ETHERTYPE_IP) { 856 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 857 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 858 dst, ":", src, ":", ETHERTYPE_IP); 859 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 860 eh->ether_dhost, ":", eh->ether_shost, ":", 861 ntohs(eh->ether_type)); 862 device_printf(sc->rl_dev, "You may have a defective 32-bit " 863 "NIC plugged into a 64-bit PCI slot.\n"); 864 device_printf(sc->rl_dev, "Please re-install the NIC in a " 865 "32-bit slot for proper operation.\n"); 866 device_printf(sc->rl_dev, "Read the re(4) man page for more " 867 "details.\n"); 868 error = EIO; 869 } 870 871done: 872 /* Turn interface off, release resources */ 873 874 sc->rl_testmode = 0; 875 sc->rl_flags &= ~RL_FLAG_LINK; 876 ifp->if_flags &= ~IFF_PROMISC; 877 re_stop(sc); 878 if (m0 != NULL) 879 m_freem(m0); 880 881 RL_UNLOCK(sc); 882 883 return (error); 884} 885 886#endif 887 888/* 889 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 890 * IDs against our list and return a device name if we find a match. 891 */ 892static int 893re_probe(device_t dev) 894{ 895 struct rl_type *t; 896 uint16_t devid, vendor; 897 uint16_t revid, sdevid; 898 int i; 899 900 vendor = pci_get_vendor(dev); 901 devid = pci_get_device(dev); 902 revid = pci_get_revid(dev); 903 sdevid = pci_get_subdevice(dev); 904 905 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 906 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 907 /* 908 * Only attach to rev. 3 of the Linksys EG1032 adapter. 909 * Rev. 2 is supported by sk(4). 910 */ 911 return (ENXIO); 912 } 913 } 914 915 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 916 if (revid != 0x20) { 917 /* 8139, let rl(4) take care of this device. */ 918 return (ENXIO); 919 } 920 } 921 922 t = re_devs; 923 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 924 if (vendor == t->rl_vid && devid == t->rl_did) { 925 device_set_desc(dev, t->rl_name); 926 return (BUS_PROBE_DEFAULT); 927 } 928 } 929 930 return (ENXIO); 931} 932 933/* 934 * Map a single buffer address. 935 */ 936 937static void 938re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 939{ 940 bus_addr_t *addr; 941 942 if (error) 943 return; 944 945 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 946 addr = arg; 947 *addr = segs->ds_addr; 948} 949 950static int 951re_allocmem(device_t dev, struct rl_softc *sc) 952{ 953 bus_addr_t lowaddr; 954 bus_size_t rx_list_size, tx_list_size; 955 int error; 956 int i; 957 958 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 959 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 960 961 /* 962 * Allocate the parent bus DMA tag appropriate for PCI. 963 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 964 * register should be set. However some RealTek chips are known 965 * to be buggy on DAC handling, therefore disable DAC by limiting 966 * DMA address space to 32bit. PCIe variants of RealTek chips 967 * may not have the limitation. 968 */ 969 lowaddr = BUS_SPACE_MAXADDR; 970 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 971 lowaddr = BUS_SPACE_MAXADDR_32BIT; 972 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 973 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 974 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 975 NULL, NULL, &sc->rl_parent_tag); 976 if (error) { 977 device_printf(dev, "could not allocate parent DMA tag\n"); 978 return (error); 979 } 980 981 /* 982 * Allocate map for TX mbufs. 983 */ 984 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 985 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 986 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 987 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 988 if (error) { 989 device_printf(dev, "could not allocate TX DMA tag\n"); 990 return (error); 991 } 992 993 /* 994 * Allocate map for RX mbufs. 995 */ 996 997 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 998 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 999 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1000 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1001 &sc->rl_ldata.rl_jrx_mtag); 1002 if (error) { 1003 device_printf(dev, 1004 "could not allocate jumbo RX DMA tag\n"); 1005 return (error); 1006 } 1007 } 1008 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1009 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1010 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1011 if (error) { 1012 device_printf(dev, "could not allocate RX DMA tag\n"); 1013 return (error); 1014 } 1015 1016 /* 1017 * Allocate map for TX descriptor list. 1018 */ 1019 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1020 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1021 NULL, tx_list_size, 1, tx_list_size, 0, 1022 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1023 if (error) { 1024 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1025 return (error); 1026 } 1027 1028 /* Allocate DMA'able memory for the TX ring */ 1029 1030 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1031 (void **)&sc->rl_ldata.rl_tx_list, 1032 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1033 &sc->rl_ldata.rl_tx_list_map); 1034 if (error) { 1035 device_printf(dev, "could not allocate TX DMA ring\n"); 1036 return (error); 1037 } 1038 1039 /* Load the map for the TX ring. */ 1040 1041 sc->rl_ldata.rl_tx_list_addr = 0; 1042 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1043 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1044 tx_list_size, re_dma_map_addr, 1045 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1046 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1047 device_printf(dev, "could not load TX DMA ring\n"); 1048 return (ENOMEM); 1049 } 1050 1051 /* Create DMA maps for TX buffers */ 1052 1053 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1054 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1055 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1056 if (error) { 1057 device_printf(dev, "could not create DMA map for TX\n"); 1058 return (error); 1059 } 1060 } 1061 1062 /* 1063 * Allocate map for RX descriptor list. 1064 */ 1065 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1066 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1067 NULL, rx_list_size, 1, rx_list_size, 0, 1068 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1069 if (error) { 1070 device_printf(dev, "could not create RX DMA ring tag\n"); 1071 return (error); 1072 } 1073 1074 /* Allocate DMA'able memory for the RX ring */ 1075 1076 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1077 (void **)&sc->rl_ldata.rl_rx_list, 1078 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1079 &sc->rl_ldata.rl_rx_list_map); 1080 if (error) { 1081 device_printf(dev, "could not allocate RX DMA ring\n"); 1082 return (error); 1083 } 1084 1085 /* Load the map for the RX ring. */ 1086 1087 sc->rl_ldata.rl_rx_list_addr = 0; 1088 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1089 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1090 rx_list_size, re_dma_map_addr, 1091 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1092 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1093 device_printf(dev, "could not load RX DMA ring\n"); 1094 return (ENOMEM); 1095 } 1096 1097 /* Create DMA maps for RX buffers */ 1098 1099 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1100 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1101 &sc->rl_ldata.rl_jrx_sparemap); 1102 if (error) { 1103 device_printf(dev, 1104 "could not create spare DMA map for jumbo RX\n"); 1105 return (error); 1106 } 1107 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1108 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1109 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1110 if (error) { 1111 device_printf(dev, 1112 "could not create DMA map for jumbo RX\n"); 1113 return (error); 1114 } 1115 } 1116 } 1117 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1118 &sc->rl_ldata.rl_rx_sparemap); 1119 if (error) { 1120 device_printf(dev, "could not create spare DMA map for RX\n"); 1121 return (error); 1122 } 1123 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1124 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1125 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1126 if (error) { 1127 device_printf(dev, "could not create DMA map for RX\n"); 1128 return (error); 1129 } 1130 } 1131 1132 /* Create DMA map for statistics. */ 1133 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1134 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1135 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1136 &sc->rl_ldata.rl_stag); 1137 if (error) { 1138 device_printf(dev, "could not create statistics DMA tag\n"); 1139 return (error); 1140 } 1141 /* Allocate DMA'able memory for statistics. */ 1142 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1143 (void **)&sc->rl_ldata.rl_stats, 1144 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1145 &sc->rl_ldata.rl_smap); 1146 if (error) { 1147 device_printf(dev, 1148 "could not allocate statistics DMA memory\n"); 1149 return (error); 1150 } 1151 /* Load the map for statistics. */ 1152 sc->rl_ldata.rl_stats_addr = 0; 1153 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1154 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1155 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1156 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1157 device_printf(dev, "could not load statistics DMA memory\n"); 1158 return (ENOMEM); 1159 } 1160 1161 return (0); 1162} 1163 1164/* 1165 * Attach the interface. Allocate softc structures, do ifmedia 1166 * setup and ethernet/BPF attach. 1167 */ 1168static int 1169re_attach(device_t dev) 1170{ 1171 u_char eaddr[ETHER_ADDR_LEN]; 1172 u_int16_t as[ETHER_ADDR_LEN / 2]; 1173 struct rl_softc *sc; 1174 struct ifnet *ifp; 1175 struct rl_hwrev *hw_rev; 1176 int hwrev; 1177 u_int16_t devid, re_did = 0; 1178 int error = 0, i, phy, rid; 1179 int msic, reg; 1180 uint8_t cfg; 1181 1182 sc = device_get_softc(dev); 1183 sc->rl_dev = dev; 1184 1185 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1186 MTX_DEF); 1187 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1188 1189 /* 1190 * Map control/status registers. 1191 */ 1192 pci_enable_busmaster(dev); 1193 1194 devid = pci_get_device(dev); 1195 /* 1196 * Prefer memory space register mapping over IO space. 1197 * Because RTL8169SC does not seem to work when memory mapping 1198 * is used always activate io mapping. 1199 */ 1200 if (devid == RT_DEVICEID_8169SC) 1201 prefer_iomap = 1; 1202 if (prefer_iomap == 0) { 1203 sc->rl_res_id = PCIR_BAR(1); 1204 sc->rl_res_type = SYS_RES_MEMORY; 1205 /* RTL8168/8101E seems to use different BARs. */ 1206 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1207 sc->rl_res_id = PCIR_BAR(2); 1208 } else { 1209 sc->rl_res_id = PCIR_BAR(0); 1210 sc->rl_res_type = SYS_RES_IOPORT; 1211 } 1212 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1213 &sc->rl_res_id, RF_ACTIVE); 1214 if (sc->rl_res == NULL && prefer_iomap == 0) { 1215 sc->rl_res_id = PCIR_BAR(0); 1216 sc->rl_res_type = SYS_RES_IOPORT; 1217 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1218 &sc->rl_res_id, RF_ACTIVE); 1219 } 1220 if (sc->rl_res == NULL) { 1221 device_printf(dev, "couldn't map ports/memory\n"); 1222 error = ENXIO; 1223 goto fail; 1224 } 1225 1226 sc->rl_btag = rman_get_bustag(sc->rl_res); 1227 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1228 1229 msic = 0; 1230 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1231 sc->rl_flags |= RL_FLAG_PCIE; 1232 msic = pci_msi_count(dev); 1233 if (bootverbose) 1234 device_printf(dev, "MSI count : %d\n", msic); 1235 } 1236 if (msic > 0 && msi_disable == 0) { 1237 msic = 1; 1238 if (pci_alloc_msi(dev, &msic) == 0) { 1239 if (msic == RL_MSI_MESSAGES) { 1240 device_printf(dev, "Using %d MSI messages\n", 1241 msic); 1242 sc->rl_flags |= RL_FLAG_MSI; 1243 /* Explicitly set MSI enable bit. */ 1244 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1245 cfg = CSR_READ_1(sc, RL_CFG2); 1246 cfg |= RL_CFG2_MSI; 1247 CSR_WRITE_1(sc, RL_CFG2, cfg); 1248 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1249 } else 1250 pci_release_msi(dev); 1251 } 1252 } 1253 1254 /* Allocate interrupt */ 1255 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1256 rid = 0; 1257 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1258 RF_SHAREABLE | RF_ACTIVE); 1259 if (sc->rl_irq[0] == NULL) { 1260 device_printf(dev, "couldn't allocate IRQ resources\n"); 1261 error = ENXIO; 1262 goto fail; 1263 } 1264 } else { 1265 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1266 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1267 SYS_RES_IRQ, &rid, RF_ACTIVE); 1268 if (sc->rl_irq[i] == NULL) { 1269 device_printf(dev, 1270 "couldn't llocate IRQ resources for " 1271 "message %d\n", rid); 1272 error = ENXIO; 1273 goto fail; 1274 } 1275 } 1276 } 1277 1278 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1279 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1280 cfg = CSR_READ_1(sc, RL_CFG2); 1281 if ((cfg & RL_CFG2_MSI) != 0) { 1282 device_printf(dev, "turning off MSI enable bit.\n"); 1283 cfg &= ~RL_CFG2_MSI; 1284 CSR_WRITE_1(sc, RL_CFG2, cfg); 1285 } 1286 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1287 } 1288 1289 hw_rev = re_hwrevs; 1290 hwrev = CSR_READ_4(sc, RL_TXCFG); 1291 switch (hwrev & 0x70000000) { 1292 case 0x00000000: 1293 case 0x10000000: 1294 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1295 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1296 break; 1297 default: 1298 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1299 hwrev &= RL_TXCFG_HWREV; 1300 break; 1301 } 1302 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1303 while (hw_rev->rl_desc != NULL) { 1304 if (hw_rev->rl_rev == hwrev) { 1305 sc->rl_type = hw_rev->rl_type; 1306 sc->rl_hwrev = hw_rev; 1307 break; 1308 } 1309 hw_rev++; 1310 } 1311 if (hw_rev->rl_desc == NULL) { 1312 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1313 error = ENXIO; 1314 goto fail; 1315 } 1316 1317 switch (hw_rev->rl_rev) { 1318 case RL_HWREV_8139CPLUS: 1319 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1320 break; 1321 case RL_HWREV_8100E: 1322 case RL_HWREV_8101E: 1323 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1324 break; 1325 case RL_HWREV_8102E: 1326 case RL_HWREV_8102EL: 1327 case RL_HWREV_8102EL_SPIN1: 1328 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1329 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1330 RL_FLAG_AUTOPAD; 1331 break; 1332 case RL_HWREV_8103E: 1333 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1334 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1335 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1336 break; 1337 case RL_HWREV_8168B_SPIN1: 1338 case RL_HWREV_8168B_SPIN2: 1339 sc->rl_flags |= RL_FLAG_WOLRXENB; 1340 /* FALLTHROUGH */ 1341 case RL_HWREV_8168B_SPIN3: 1342 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1343 break; 1344 case RL_HWREV_8168C_SPIN2: 1345 sc->rl_flags |= RL_FLAG_MACSLEEP; 1346 /* FALLTHROUGH */ 1347 case RL_HWREV_8168C: 1348 if ((hwrev & 0x00700000) == 0x00200000) 1349 sc->rl_flags |= RL_FLAG_MACSLEEP; 1350 /* FALLTHROUGH */ 1351 case RL_HWREV_8168CP: 1352 case RL_HWREV_8168D: 1353 case RL_HWREV_8168DP: 1354 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1355 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1356 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1357 break; 1358 case RL_HWREV_8168E: 1359 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1360 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1361 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1362 break; 1363 case RL_HWREV_8168E_VL: 1364 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1365 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1366 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1367 break; 1368 case RL_HWREV_8169_8110SB: 1369 case RL_HWREV_8169_8110SBL: 1370 case RL_HWREV_8169_8110SC: 1371 case RL_HWREV_8169_8110SCE: 1372 sc->rl_flags |= RL_FLAG_PHYWAKE; 1373 /* FALLTHROUGH */ 1374 case RL_HWREV_8169: 1375 case RL_HWREV_8169S: 1376 case RL_HWREV_8110S: 1377 sc->rl_flags |= RL_FLAG_MACRESET; 1378 break; 1379 default: 1380 break; 1381 } 1382 1383 /* Reset the adapter. */ 1384 RL_LOCK(sc); 1385 re_reset(sc); 1386 RL_UNLOCK(sc); 1387 1388 /* Enable PME. */ 1389 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1390 cfg = CSR_READ_1(sc, RL_CFG1); 1391 cfg |= RL_CFG1_PME; 1392 CSR_WRITE_1(sc, RL_CFG1, cfg); 1393 cfg = CSR_READ_1(sc, RL_CFG5); 1394 cfg &= RL_CFG5_PME_STS; 1395 CSR_WRITE_1(sc, RL_CFG5, cfg); 1396 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1397 1398 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1399 /* 1400 * XXX Should have a better way to extract station 1401 * address from EEPROM. 1402 */ 1403 for (i = 0; i < ETHER_ADDR_LEN; i++) 1404 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1405 } else { 1406 sc->rl_eewidth = RL_9356_ADDR_LEN; 1407 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1408 if (re_did != 0x8129) 1409 sc->rl_eewidth = RL_9346_ADDR_LEN; 1410 1411 /* 1412 * Get station address from the EEPROM. 1413 */ 1414 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1415 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1416 as[i] = le16toh(as[i]); 1417 bcopy(as, eaddr, sizeof(eaddr)); 1418 } 1419 1420 if (sc->rl_type == RL_8169) { 1421 /* Set RX length mask and number of descriptors. */ 1422 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1423 sc->rl_txstart = RL_GTXSTART; 1424 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1425 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1426 } else { 1427 /* Set RX length mask and number of descriptors. */ 1428 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1429 sc->rl_txstart = RL_TXSTART; 1430 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1431 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1432 } 1433 1434 error = re_allocmem(dev, sc); 1435 if (error) 1436 goto fail; 1437 re_add_sysctls(sc); 1438 1439 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1440 if (ifp == NULL) { 1441 device_printf(dev, "can not if_alloc()\n"); 1442 error = ENOSPC; 1443 goto fail; 1444 } 1445 1446 /* Take controller out of deep sleep mode. */ 1447 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1448 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1449 CSR_WRITE_1(sc, RL_GPIO, 1450 CSR_READ_1(sc, RL_GPIO) | 0x01); 1451 else 1452 CSR_WRITE_1(sc, RL_GPIO, 1453 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1454 } 1455 1456 /* Take PHY out of power down mode. */ 1457 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 1458 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1459 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1460 re_gmii_writereg(dev, 1, 0x1f, 0); 1461 re_gmii_writereg(dev, 1, 0x0e, 0); 1462 } 1463 1464#define RE_PHYAD_INTERNAL 0 1465 1466 /* Do MII setup. */ 1467 phy = RE_PHYAD_INTERNAL; 1468 if (sc->rl_type == RL_8169) 1469 phy = 1; 1470 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1471 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1472 if (error != 0) { 1473 device_printf(dev, "attaching PHYs failed\n"); 1474 goto fail; 1475 } 1476 1477 ifp->if_softc = sc; 1478 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1479 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1480 ifp->if_ioctl = re_ioctl; 1481 ifp->if_start = re_start; 1482 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1483 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1484 ifp->if_capenable = ifp->if_capabilities; 1485 ifp->if_init = re_init; 1486 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1487 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1488 IFQ_SET_READY(&ifp->if_snd); 1489 1490 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1491 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1492 1493 /* 1494 * Call MI attach routine. 1495 */ 1496 ether_ifattach(ifp, eaddr); 1497 1498 /* VLAN capability setup */ 1499 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1500 if (ifp->if_capabilities & IFCAP_HWCSUM) 1501 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1502 /* Enable WOL if PM is supported. */ 1503 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1504 ifp->if_capabilities |= IFCAP_WOL; 1505 ifp->if_capenable = ifp->if_capabilities; 1506 /* 1507 * Don't enable TSO by default for old controllers. Under 1508 * certain circumtances the controller generated corrupted 1509 * packets in TSO size. 1510 */ 1511 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1512 ifp->if_hwassist &= ~CSUM_TSO; 1513 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1514 } 1515#ifdef DEVICE_POLLING 1516 ifp->if_capabilities |= IFCAP_POLLING; 1517#endif 1518 /* 1519 * Tell the upper layer(s) we support long frames. 1520 * Must appear after the call to ether_ifattach() because 1521 * ether_ifattach() sets ifi_hdrlen to the default value. 1522 */ 1523 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1524 1525#ifdef RE_DIAG 1526 /* 1527 * Perform hardware diagnostic on the original RTL8169. 1528 * Some 32-bit cards were incorrectly wired and would 1529 * malfunction if plugged into a 64-bit slot. 1530 */ 1531 1532 if (hwrev == RL_HWREV_8169) { 1533 error = re_diag(sc); 1534 if (error) { 1535 device_printf(dev, 1536 "attach aborted due to hardware diag failure\n"); 1537 ether_ifdetach(ifp); 1538 goto fail; 1539 } 1540 } 1541#endif 1542 1543 /* Hook interrupt last to avoid having to lock softc */ 1544 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1545 error = bus_setup_intr(dev, sc->rl_irq[0], 1546 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1547 &sc->rl_intrhand[0]); 1548 else { 1549 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1550 error = bus_setup_intr(dev, sc->rl_irq[i], 1551 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1552 &sc->rl_intrhand[i]); 1553 if (error != 0) 1554 break; 1555 } 1556 } 1557 if (error) { 1558 device_printf(dev, "couldn't set up irq\n"); 1559 ether_ifdetach(ifp); 1560 } 1561 1562fail: 1563 1564 if (error) 1565 re_detach(dev); 1566 1567 return (error); 1568} 1569 1570/* 1571 * Shutdown hardware and free up resources. This can be called any 1572 * time after the mutex has been initialized. It is called in both 1573 * the error case in attach and the normal detach case so it needs 1574 * to be careful about only freeing resources that have actually been 1575 * allocated. 1576 */ 1577static int 1578re_detach(device_t dev) 1579{ 1580 struct rl_softc *sc; 1581 struct ifnet *ifp; 1582 int i, rid; 1583 1584 sc = device_get_softc(dev); 1585 ifp = sc->rl_ifp; 1586 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1587 1588 /* These should only be active if attach succeeded */ 1589 if (device_is_attached(dev)) { 1590#ifdef DEVICE_POLLING 1591 if (ifp->if_capenable & IFCAP_POLLING) 1592 ether_poll_deregister(ifp); 1593#endif 1594 RL_LOCK(sc); 1595#if 0 1596 sc->suspended = 1; 1597#endif 1598 re_stop(sc); 1599 RL_UNLOCK(sc); 1600 callout_drain(&sc->rl_stat_callout); 1601 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1602 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1603 /* 1604 * Force off the IFF_UP flag here, in case someone 1605 * still had a BPF descriptor attached to this 1606 * interface. If they do, ether_ifdetach() will cause 1607 * the BPF code to try and clear the promisc mode 1608 * flag, which will bubble down to re_ioctl(), 1609 * which will try to call re_init() again. This will 1610 * turn the NIC back on and restart the MII ticker, 1611 * which will panic the system when the kernel tries 1612 * to invoke the re_tick() function that isn't there 1613 * anymore. 1614 */ 1615 ifp->if_flags &= ~IFF_UP; 1616 ether_ifdetach(ifp); 1617 } 1618 if (sc->rl_miibus) 1619 device_delete_child(dev, sc->rl_miibus); 1620 bus_generic_detach(dev); 1621 1622 /* 1623 * The rest is resource deallocation, so we should already be 1624 * stopped here. 1625 */ 1626 1627 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1628 if (sc->rl_intrhand[i] != NULL) { 1629 bus_teardown_intr(dev, sc->rl_irq[i], 1630 sc->rl_intrhand[i]); 1631 sc->rl_intrhand[i] = NULL; 1632 } 1633 } 1634 if (ifp != NULL) 1635 if_free(ifp); 1636 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1637 if (sc->rl_irq[0] != NULL) { 1638 bus_release_resource(dev, SYS_RES_IRQ, 0, 1639 sc->rl_irq[0]); 1640 sc->rl_irq[0] = NULL; 1641 } 1642 } else { 1643 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1644 if (sc->rl_irq[i] != NULL) { 1645 bus_release_resource(dev, SYS_RES_IRQ, rid, 1646 sc->rl_irq[i]); 1647 sc->rl_irq[i] = NULL; 1648 } 1649 } 1650 pci_release_msi(dev); 1651 } 1652 if (sc->rl_res) 1653 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1654 sc->rl_res); 1655 1656 /* Unload and free the RX DMA ring memory and map */ 1657 1658 if (sc->rl_ldata.rl_rx_list_tag) { 1659 if (sc->rl_ldata.rl_rx_list_map) 1660 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1661 sc->rl_ldata.rl_rx_list_map); 1662 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1663 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1664 sc->rl_ldata.rl_rx_list, 1665 sc->rl_ldata.rl_rx_list_map); 1666 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1667 } 1668 1669 /* Unload and free the TX DMA ring memory and map */ 1670 1671 if (sc->rl_ldata.rl_tx_list_tag) { 1672 if (sc->rl_ldata.rl_tx_list_map) 1673 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1674 sc->rl_ldata.rl_tx_list_map); 1675 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1676 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1677 sc->rl_ldata.rl_tx_list, 1678 sc->rl_ldata.rl_tx_list_map); 1679 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1680 } 1681 1682 /* Destroy all the RX and TX buffer maps */ 1683 1684 if (sc->rl_ldata.rl_tx_mtag) { 1685 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1686 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1687 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1688 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1689 } 1690 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1691 } 1692 if (sc->rl_ldata.rl_rx_mtag) { 1693 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1694 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1695 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1696 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1697 } 1698 if (sc->rl_ldata.rl_rx_sparemap) 1699 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1700 sc->rl_ldata.rl_rx_sparemap); 1701 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1702 } 1703 if (sc->rl_ldata.rl_jrx_mtag) { 1704 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1705 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1706 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1707 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1708 } 1709 if (sc->rl_ldata.rl_jrx_sparemap) 1710 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1711 sc->rl_ldata.rl_jrx_sparemap); 1712 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1713 } 1714 /* Unload and free the stats buffer and map */ 1715 1716 if (sc->rl_ldata.rl_stag) { 1717 if (sc->rl_ldata.rl_smap) 1718 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1719 sc->rl_ldata.rl_smap); 1720 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1721 bus_dmamem_free(sc->rl_ldata.rl_stag, 1722 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1723 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1724 } 1725 1726 if (sc->rl_parent_tag) 1727 bus_dma_tag_destroy(sc->rl_parent_tag); 1728 1729 mtx_destroy(&sc->rl_mtx); 1730 1731 return (0); 1732} 1733 1734static __inline void 1735re_discard_rxbuf(struct rl_softc *sc, int idx) 1736{ 1737 struct rl_desc *desc; 1738 struct rl_rxdesc *rxd; 1739 uint32_t cmdstat; 1740 1741 if (sc->rl_ifp->if_mtu > RL_MTU && 1742 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1743 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1744 else 1745 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1746 desc = &sc->rl_ldata.rl_rx_list[idx]; 1747 desc->rl_vlanctl = 0; 1748 cmdstat = rxd->rx_size; 1749 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1750 cmdstat |= RL_RDESC_CMD_EOR; 1751 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1752} 1753 1754static int 1755re_newbuf(struct rl_softc *sc, int idx) 1756{ 1757 struct mbuf *m; 1758 struct rl_rxdesc *rxd; 1759 bus_dma_segment_t segs[1]; 1760 bus_dmamap_t map; 1761 struct rl_desc *desc; 1762 uint32_t cmdstat; 1763 int error, nsegs; 1764 1765 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1766 if (m == NULL) 1767 return (ENOBUFS); 1768 1769 m->m_len = m->m_pkthdr.len = MCLBYTES; 1770#ifdef RE_FIXUP_RX 1771 /* 1772 * This is part of an evil trick to deal with non-x86 platforms. 1773 * The RealTek chip requires RX buffers to be aligned on 64-bit 1774 * boundaries, but that will hose non-x86 machines. To get around 1775 * this, we leave some empty space at the start of each buffer 1776 * and for non-x86 hosts, we copy the buffer back six bytes 1777 * to achieve word alignment. This is slightly more efficient 1778 * than allocating a new buffer, copying the contents, and 1779 * discarding the old buffer. 1780 */ 1781 m_adj(m, RE_ETHER_ALIGN); 1782#endif 1783 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1784 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1785 if (error != 0) { 1786 m_freem(m); 1787 return (ENOBUFS); 1788 } 1789 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1790 1791 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1792 if (rxd->rx_m != NULL) { 1793 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1794 BUS_DMASYNC_POSTREAD); 1795 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1796 } 1797 1798 rxd->rx_m = m; 1799 map = rxd->rx_dmamap; 1800 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1801 rxd->rx_size = segs[0].ds_len; 1802 sc->rl_ldata.rl_rx_sparemap = map; 1803 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1804 BUS_DMASYNC_PREREAD); 1805 1806 desc = &sc->rl_ldata.rl_rx_list[idx]; 1807 desc->rl_vlanctl = 0; 1808 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1809 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1810 cmdstat = segs[0].ds_len; 1811 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1812 cmdstat |= RL_RDESC_CMD_EOR; 1813 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1814 1815 return (0); 1816} 1817 1818static int 1819re_jumbo_newbuf(struct rl_softc *sc, int idx) 1820{ 1821 struct mbuf *m; 1822 struct rl_rxdesc *rxd; 1823 bus_dma_segment_t segs[1]; 1824 bus_dmamap_t map; 1825 struct rl_desc *desc; 1826 uint32_t cmdstat; 1827 int error, nsegs; 1828 1829 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1830 if (m == NULL) 1831 return (ENOBUFS); 1832 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1833#ifdef RE_FIXUP_RX 1834 m_adj(m, RE_ETHER_ALIGN); 1835#endif 1836 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1837 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1838 if (error != 0) { 1839 m_freem(m); 1840 return (ENOBUFS); 1841 } 1842 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1843 1844 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1845 if (rxd->rx_m != NULL) { 1846 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1847 BUS_DMASYNC_POSTREAD); 1848 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1849 } 1850 1851 rxd->rx_m = m; 1852 map = rxd->rx_dmamap; 1853 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 1854 rxd->rx_size = segs[0].ds_len; 1855 sc->rl_ldata.rl_jrx_sparemap = map; 1856 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1857 BUS_DMASYNC_PREREAD); 1858 1859 desc = &sc->rl_ldata.rl_rx_list[idx]; 1860 desc->rl_vlanctl = 0; 1861 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1862 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1863 cmdstat = segs[0].ds_len; 1864 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1865 cmdstat |= RL_RDESC_CMD_EOR; 1866 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1867 1868 return (0); 1869} 1870 1871#ifdef RE_FIXUP_RX 1872static __inline void 1873re_fixup_rx(struct mbuf *m) 1874{ 1875 int i; 1876 uint16_t *src, *dst; 1877 1878 src = mtod(m, uint16_t *); 1879 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1880 1881 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1882 *dst++ = *src++; 1883 1884 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1885} 1886#endif 1887 1888static int 1889re_tx_list_init(struct rl_softc *sc) 1890{ 1891 struct rl_desc *desc; 1892 int i; 1893 1894 RL_LOCK_ASSERT(sc); 1895 1896 bzero(sc->rl_ldata.rl_tx_list, 1897 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1898 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1899 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1900 /* Set EOR. */ 1901 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1902 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1903 1904 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1905 sc->rl_ldata.rl_tx_list_map, 1906 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1907 1908 sc->rl_ldata.rl_tx_prodidx = 0; 1909 sc->rl_ldata.rl_tx_considx = 0; 1910 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1911 1912 return (0); 1913} 1914 1915static int 1916re_rx_list_init(struct rl_softc *sc) 1917{ 1918 int error, i; 1919 1920 bzero(sc->rl_ldata.rl_rx_list, 1921 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1922 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1923 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1924 if ((error = re_newbuf(sc, i)) != 0) 1925 return (error); 1926 } 1927 1928 /* Flush the RX descriptors */ 1929 1930 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1931 sc->rl_ldata.rl_rx_list_map, 1932 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1933 1934 sc->rl_ldata.rl_rx_prodidx = 0; 1935 sc->rl_head = sc->rl_tail = NULL; 1936 1937 return (0); 1938} 1939 1940static int 1941re_jrx_list_init(struct rl_softc *sc) 1942{ 1943 int error, i; 1944 1945 bzero(sc->rl_ldata.rl_rx_list, 1946 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1947 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1948 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 1949 if ((error = re_jumbo_newbuf(sc, i)) != 0) 1950 return (error); 1951 } 1952 1953 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1954 sc->rl_ldata.rl_rx_list_map, 1955 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1956 1957 sc->rl_ldata.rl_rx_prodidx = 0; 1958 sc->rl_head = sc->rl_tail = NULL; 1959 1960 return (0); 1961} 1962 1963/* 1964 * RX handler for C+ and 8169. For the gigE chips, we support 1965 * the reception of jumbo frames that have been fragmented 1966 * across multiple 2K mbuf cluster buffers. 1967 */ 1968static int 1969re_rxeof(struct rl_softc *sc, int *rx_npktsp) 1970{ 1971 struct mbuf *m; 1972 struct ifnet *ifp; 1973 int i, rxerr, total_len; 1974 struct rl_desc *cur_rx; 1975 u_int32_t rxstat, rxvlan; 1976 int jumbo, maxpkt = 16, rx_npkts = 0; 1977 1978 RL_LOCK_ASSERT(sc); 1979 1980 ifp = sc->rl_ifp; 1981 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1982 jumbo = 1; 1983 else 1984 jumbo = 0; 1985 1986 /* Invalidate the descriptor memory */ 1987 1988 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1989 sc->rl_ldata.rl_rx_list_map, 1990 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1991 1992 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1993 i = RL_RX_DESC_NXT(sc, i)) { 1994 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1995 break; 1996 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1997 rxstat = le32toh(cur_rx->rl_cmdstat); 1998 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1999 break; 2000 total_len = rxstat & sc->rl_rxlenmask; 2001 rxvlan = le32toh(cur_rx->rl_vlanctl); 2002 if (jumbo != 0) 2003 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2004 else 2005 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2006 2007 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2008 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2009 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2010 /* 2011 * RTL8168C or later controllers do not 2012 * support multi-fragment packet. 2013 */ 2014 re_discard_rxbuf(sc, i); 2015 continue; 2016 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2017 if (re_newbuf(sc, i) != 0) { 2018 /* 2019 * If this is part of a multi-fragment packet, 2020 * discard all the pieces. 2021 */ 2022 if (sc->rl_head != NULL) { 2023 m_freem(sc->rl_head); 2024 sc->rl_head = sc->rl_tail = NULL; 2025 } 2026 re_discard_rxbuf(sc, i); 2027 continue; 2028 } 2029 m->m_len = RE_RX_DESC_BUFLEN; 2030 if (sc->rl_head == NULL) 2031 sc->rl_head = sc->rl_tail = m; 2032 else { 2033 m->m_flags &= ~M_PKTHDR; 2034 sc->rl_tail->m_next = m; 2035 sc->rl_tail = m; 2036 } 2037 continue; 2038 } 2039 2040 /* 2041 * NOTE: for the 8139C+, the frame length field 2042 * is always 12 bits in size, but for the gigE chips, 2043 * it is 13 bits (since the max RX frame length is 16K). 2044 * Unfortunately, all 32 bits in the status word 2045 * were already used, so to make room for the extra 2046 * length bit, RealTek took out the 'frame alignment 2047 * error' bit and shifted the other status bits 2048 * over one slot. The OWN, EOR, FS and LS bits are 2049 * still in the same places. We have already extracted 2050 * the frame length and checked the OWN bit, so rather 2051 * than using an alternate bit mapping, we shift the 2052 * status bits one space to the right so we can evaluate 2053 * them using the 8169 status as though it was in the 2054 * same format as that of the 8139C+. 2055 */ 2056 if (sc->rl_type == RL_8169) 2057 rxstat >>= 1; 2058 2059 /* 2060 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2061 * set, but if CRC is clear, it will still be a valid frame. 2062 */ 2063 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2064 rxerr = 1; 2065 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2066 total_len > 8191 && 2067 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2068 rxerr = 0; 2069 if (rxerr != 0) { 2070 ifp->if_ierrors++; 2071 /* 2072 * If this is part of a multi-fragment packet, 2073 * discard all the pieces. 2074 */ 2075 if (sc->rl_head != NULL) { 2076 m_freem(sc->rl_head); 2077 sc->rl_head = sc->rl_tail = NULL; 2078 } 2079 re_discard_rxbuf(sc, i); 2080 continue; 2081 } 2082 } 2083 2084 /* 2085 * If allocating a replacement mbuf fails, 2086 * reload the current one. 2087 */ 2088 if (jumbo != 0) 2089 rxerr = re_jumbo_newbuf(sc, i); 2090 else 2091 rxerr = re_newbuf(sc, i); 2092 if (rxerr != 0) { 2093 ifp->if_iqdrops++; 2094 if (sc->rl_head != NULL) { 2095 m_freem(sc->rl_head); 2096 sc->rl_head = sc->rl_tail = NULL; 2097 } 2098 re_discard_rxbuf(sc, i); 2099 continue; 2100 } 2101 2102 if (sc->rl_head != NULL) { 2103 if (jumbo != 0) 2104 m->m_len = total_len; 2105 else { 2106 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2107 if (m->m_len == 0) 2108 m->m_len = RE_RX_DESC_BUFLEN; 2109 } 2110 /* 2111 * Special case: if there's 4 bytes or less 2112 * in this buffer, the mbuf can be discarded: 2113 * the last 4 bytes is the CRC, which we don't 2114 * care about anyway. 2115 */ 2116 if (m->m_len <= ETHER_CRC_LEN) { 2117 sc->rl_tail->m_len -= 2118 (ETHER_CRC_LEN - m->m_len); 2119 m_freem(m); 2120 } else { 2121 m->m_len -= ETHER_CRC_LEN; 2122 m->m_flags &= ~M_PKTHDR; 2123 sc->rl_tail->m_next = m; 2124 } 2125 m = sc->rl_head; 2126 sc->rl_head = sc->rl_tail = NULL; 2127 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2128 } else 2129 m->m_pkthdr.len = m->m_len = 2130 (total_len - ETHER_CRC_LEN); 2131 2132#ifdef RE_FIXUP_RX 2133 re_fixup_rx(m); 2134#endif 2135 ifp->if_ipackets++; 2136 m->m_pkthdr.rcvif = ifp; 2137 2138 /* Do RX checksumming if enabled */ 2139 2140 if (ifp->if_capenable & IFCAP_RXCSUM) { 2141 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2142 /* Check IP header checksum */ 2143 if (rxstat & RL_RDESC_STAT_PROTOID) 2144 m->m_pkthdr.csum_flags |= 2145 CSUM_IP_CHECKED; 2146 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2147 m->m_pkthdr.csum_flags |= 2148 CSUM_IP_VALID; 2149 2150 /* Check TCP/UDP checksum */ 2151 if ((RL_TCPPKT(rxstat) && 2152 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2153 (RL_UDPPKT(rxstat) && 2154 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2155 m->m_pkthdr.csum_flags |= 2156 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2157 m->m_pkthdr.csum_data = 0xffff; 2158 } 2159 } else { 2160 /* 2161 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2162 */ 2163 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2164 (rxvlan & RL_RDESC_IPV4)) 2165 m->m_pkthdr.csum_flags |= 2166 CSUM_IP_CHECKED; 2167 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2168 (rxvlan & RL_RDESC_IPV4)) 2169 m->m_pkthdr.csum_flags |= 2170 CSUM_IP_VALID; 2171 if (((rxstat & RL_RDESC_STAT_TCP) && 2172 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2173 ((rxstat & RL_RDESC_STAT_UDP) && 2174 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2175 m->m_pkthdr.csum_flags |= 2176 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2177 m->m_pkthdr.csum_data = 0xffff; 2178 } 2179 } 2180 } 2181 maxpkt--; 2182 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2183 m->m_pkthdr.ether_vtag = 2184 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2185 m->m_flags |= M_VLANTAG; 2186 } 2187 RL_UNLOCK(sc); 2188 (*ifp->if_input)(ifp, m); 2189 RL_LOCK(sc); 2190 rx_npkts++; 2191 } 2192 2193 /* Flush the RX DMA ring */ 2194 2195 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2196 sc->rl_ldata.rl_rx_list_map, 2197 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2198 2199 sc->rl_ldata.rl_rx_prodidx = i; 2200 2201 if (rx_npktsp != NULL) 2202 *rx_npktsp = rx_npkts; 2203 if (maxpkt) 2204 return (EAGAIN); 2205 2206 return (0); 2207} 2208 2209static void 2210re_txeof(struct rl_softc *sc) 2211{ 2212 struct ifnet *ifp; 2213 struct rl_txdesc *txd; 2214 u_int32_t txstat; 2215 int cons; 2216 2217 cons = sc->rl_ldata.rl_tx_considx; 2218 if (cons == sc->rl_ldata.rl_tx_prodidx) 2219 return; 2220 2221 ifp = sc->rl_ifp; 2222 /* Invalidate the TX descriptor list */ 2223 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2224 sc->rl_ldata.rl_tx_list_map, 2225 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2226 2227 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2228 cons = RL_TX_DESC_NXT(sc, cons)) { 2229 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2230 if (txstat & RL_TDESC_STAT_OWN) 2231 break; 2232 /* 2233 * We only stash mbufs in the last descriptor 2234 * in a fragment chain, which also happens to 2235 * be the only place where the TX status bits 2236 * are valid. 2237 */ 2238 if (txstat & RL_TDESC_CMD_EOF) { 2239 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2240 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2241 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2242 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2243 txd->tx_dmamap); 2244 KASSERT(txd->tx_m != NULL, 2245 ("%s: freeing NULL mbufs!", __func__)); 2246 m_freem(txd->tx_m); 2247 txd->tx_m = NULL; 2248 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2249 RL_TDESC_STAT_COLCNT)) 2250 ifp->if_collisions++; 2251 if (txstat & RL_TDESC_STAT_TXERRSUM) 2252 ifp->if_oerrors++; 2253 else 2254 ifp->if_opackets++; 2255 } 2256 sc->rl_ldata.rl_tx_free++; 2257 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2258 } 2259 sc->rl_ldata.rl_tx_considx = cons; 2260 2261 /* No changes made to the TX ring, so no flush needed */ 2262 2263 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2264#ifdef RE_TX_MODERATION 2265 /* 2266 * If not all descriptors have been reaped yet, reload 2267 * the timer so that we will eventually get another 2268 * interrupt that will cause us to re-enter this routine. 2269 * This is done in case the transmitter has gone idle. 2270 */ 2271 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2272#endif 2273 } else 2274 sc->rl_watchdog_timer = 0; 2275} 2276 2277static void 2278re_tick(void *xsc) 2279{ 2280 struct rl_softc *sc; 2281 struct mii_data *mii; 2282 2283 sc = xsc; 2284 2285 RL_LOCK_ASSERT(sc); 2286 2287 mii = device_get_softc(sc->rl_miibus); 2288 mii_tick(mii); 2289 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2290 re_miibus_statchg(sc->rl_dev); 2291 /* 2292 * Reclaim transmitted frames here. Technically it is not 2293 * necessary to do here but it ensures periodic reclamation 2294 * regardless of Tx completion interrupt which seems to be 2295 * lost on PCIe based controllers under certain situations. 2296 */ 2297 re_txeof(sc); 2298 re_watchdog(sc); 2299 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2300} 2301 2302#ifdef DEVICE_POLLING 2303static int 2304re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2305{ 2306 struct rl_softc *sc = ifp->if_softc; 2307 int rx_npkts = 0; 2308 2309 RL_LOCK(sc); 2310 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2311 rx_npkts = re_poll_locked(ifp, cmd, count); 2312 RL_UNLOCK(sc); 2313 return (rx_npkts); 2314} 2315 2316static int 2317re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2318{ 2319 struct rl_softc *sc = ifp->if_softc; 2320 int rx_npkts; 2321 2322 RL_LOCK_ASSERT(sc); 2323 2324 sc->rxcycles = count; 2325 re_rxeof(sc, &rx_npkts); 2326 re_txeof(sc); 2327 2328 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2329 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2330 2331 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2332 u_int16_t status; 2333 2334 status = CSR_READ_2(sc, RL_ISR); 2335 if (status == 0xffff) 2336 return (rx_npkts); 2337 if (status) 2338 CSR_WRITE_2(sc, RL_ISR, status); 2339 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2340 (sc->rl_flags & RL_FLAG_PCIE)) 2341 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2342 2343 /* 2344 * XXX check behaviour on receiver stalls. 2345 */ 2346 2347 if (status & RL_ISR_SYSTEM_ERR) { 2348 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2349 re_init_locked(sc); 2350 } 2351 } 2352 return (rx_npkts); 2353} 2354#endif /* DEVICE_POLLING */ 2355 2356static int 2357re_intr(void *arg) 2358{ 2359 struct rl_softc *sc; 2360 uint16_t status; 2361 2362 sc = arg; 2363 2364 status = CSR_READ_2(sc, RL_ISR); 2365 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2366 return (FILTER_STRAY); 2367 CSR_WRITE_2(sc, RL_IMR, 0); 2368 2369 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2370 2371 return (FILTER_HANDLED); 2372} 2373 2374static void 2375re_int_task(void *arg, int npending) 2376{ 2377 struct rl_softc *sc; 2378 struct ifnet *ifp; 2379 u_int16_t status; 2380 int rval = 0; 2381 2382 sc = arg; 2383 ifp = sc->rl_ifp; 2384 2385 RL_LOCK(sc); 2386 2387 status = CSR_READ_2(sc, RL_ISR); 2388 CSR_WRITE_2(sc, RL_ISR, status); 2389 2390 if (sc->suspended || 2391 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2392 RL_UNLOCK(sc); 2393 return; 2394 } 2395 2396#ifdef DEVICE_POLLING 2397 if (ifp->if_capenable & IFCAP_POLLING) { 2398 RL_UNLOCK(sc); 2399 return; 2400 } 2401#endif 2402 2403 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2404 rval = re_rxeof(sc, NULL); 2405 2406 /* 2407 * Some chips will ignore a second TX request issued 2408 * while an existing transmission is in progress. If 2409 * the transmitter goes idle but there are still 2410 * packets waiting to be sent, we need to restart the 2411 * channel here to flush them out. This only seems to 2412 * be required with the PCIe devices. 2413 */ 2414 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2415 (sc->rl_flags & RL_FLAG_PCIE)) 2416 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2417 if (status & ( 2418#ifdef RE_TX_MODERATION 2419 RL_ISR_TIMEOUT_EXPIRED| 2420#else 2421 RL_ISR_TX_OK| 2422#endif 2423 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2424 re_txeof(sc); 2425 2426 if (status & RL_ISR_SYSTEM_ERR) { 2427 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2428 re_init_locked(sc); 2429 } 2430 2431 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2432 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2433 2434 RL_UNLOCK(sc); 2435 2436 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2437 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2438 return; 2439 } 2440 2441 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2442} 2443 2444static int 2445re_encap(struct rl_softc *sc, struct mbuf **m_head) 2446{ 2447 struct rl_txdesc *txd, *txd_last; 2448 bus_dma_segment_t segs[RL_NTXSEGS]; 2449 bus_dmamap_t map; 2450 struct mbuf *m_new; 2451 struct rl_desc *desc; 2452 int nsegs, prod; 2453 int i, error, ei, si; 2454 int padlen; 2455 uint32_t cmdstat, csum_flags, vlanctl; 2456 2457 RL_LOCK_ASSERT(sc); 2458 M_ASSERTPKTHDR((*m_head)); 2459 2460 /* 2461 * With some of the RealTek chips, using the checksum offload 2462 * support in conjunction with the autopadding feature results 2463 * in the transmission of corrupt frames. For example, if we 2464 * need to send a really small IP fragment that's less than 60 2465 * bytes in size, and IP header checksumming is enabled, the 2466 * resulting ethernet frame that appears on the wire will 2467 * have garbled payload. To work around this, if TX IP checksum 2468 * offload is enabled, we always manually pad short frames out 2469 * to the minimum ethernet frame size. 2470 */ 2471 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2472 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2473 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2474 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2475 if (M_WRITABLE(*m_head) == 0) { 2476 /* Get a writable copy. */ 2477 m_new = m_dup(*m_head, M_DONTWAIT); 2478 m_freem(*m_head); 2479 if (m_new == NULL) { 2480 *m_head = NULL; 2481 return (ENOBUFS); 2482 } 2483 *m_head = m_new; 2484 } 2485 if ((*m_head)->m_next != NULL || 2486 M_TRAILINGSPACE(*m_head) < padlen) { 2487 m_new = m_defrag(*m_head, M_DONTWAIT); 2488 if (m_new == NULL) { 2489 m_freem(*m_head); 2490 *m_head = NULL; 2491 return (ENOBUFS); 2492 } 2493 } else 2494 m_new = *m_head; 2495 2496 /* 2497 * Manually pad short frames, and zero the pad space 2498 * to avoid leaking data. 2499 */ 2500 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2501 m_new->m_pkthdr.len += padlen; 2502 m_new->m_len = m_new->m_pkthdr.len; 2503 *m_head = m_new; 2504 } 2505 2506 prod = sc->rl_ldata.rl_tx_prodidx; 2507 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2508 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2509 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2510 if (error == EFBIG) { 2511 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2512 if (m_new == NULL) { 2513 m_freem(*m_head); 2514 *m_head = NULL; 2515 return (ENOBUFS); 2516 } 2517 *m_head = m_new; 2518 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2519 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2520 if (error != 0) { 2521 m_freem(*m_head); 2522 *m_head = NULL; 2523 return (error); 2524 } 2525 } else if (error != 0) 2526 return (error); 2527 if (nsegs == 0) { 2528 m_freem(*m_head); 2529 *m_head = NULL; 2530 return (EIO); 2531 } 2532 2533 /* Check for number of available descriptors. */ 2534 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2535 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2536 return (ENOBUFS); 2537 } 2538 2539 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2540 BUS_DMASYNC_PREWRITE); 2541 2542 /* 2543 * Set up checksum offload. Note: checksum offload bits must 2544 * appear in all descriptors of a multi-descriptor transmit 2545 * attempt. This is according to testing done with an 8169 2546 * chip. This is a requirement. 2547 */ 2548 vlanctl = 0; 2549 csum_flags = 0; 2550 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2551 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2552 csum_flags |= RL_TDESC_CMD_LGSEND; 2553 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2554 RL_TDESC_CMD_MSSVALV2_SHIFT); 2555 } else { 2556 csum_flags |= RL_TDESC_CMD_LGSEND | 2557 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2558 RL_TDESC_CMD_MSSVAL_SHIFT); 2559 } 2560 } else { 2561 /* 2562 * Unconditionally enable IP checksum if TCP or UDP 2563 * checksum is required. Otherwise, TCP/UDP checksum 2564 * does't make effects. 2565 */ 2566 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2567 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2568 csum_flags |= RL_TDESC_CMD_IPCSUM; 2569 if (((*m_head)->m_pkthdr.csum_flags & 2570 CSUM_TCP) != 0) 2571 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2572 if (((*m_head)->m_pkthdr.csum_flags & 2573 CSUM_UDP) != 0) 2574 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2575 } else { 2576 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2577 if (((*m_head)->m_pkthdr.csum_flags & 2578 CSUM_TCP) != 0) 2579 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2580 if (((*m_head)->m_pkthdr.csum_flags & 2581 CSUM_UDP) != 0) 2582 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2583 } 2584 } 2585 } 2586 2587 /* 2588 * Set up hardware VLAN tagging. Note: vlan tag info must 2589 * appear in all descriptors of a multi-descriptor 2590 * transmission attempt. 2591 */ 2592 if ((*m_head)->m_flags & M_VLANTAG) 2593 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2594 RL_TDESC_VLANCTL_TAG; 2595 2596 si = prod; 2597 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2598 desc = &sc->rl_ldata.rl_tx_list[prod]; 2599 desc->rl_vlanctl = htole32(vlanctl); 2600 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2601 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2602 cmdstat = segs[i].ds_len; 2603 if (i != 0) 2604 cmdstat |= RL_TDESC_CMD_OWN; 2605 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2606 cmdstat |= RL_TDESC_CMD_EOR; 2607 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2608 sc->rl_ldata.rl_tx_free--; 2609 } 2610 /* Update producer index. */ 2611 sc->rl_ldata.rl_tx_prodidx = prod; 2612 2613 /* Set EOF on the last descriptor. */ 2614 ei = RL_TX_DESC_PRV(sc, prod); 2615 desc = &sc->rl_ldata.rl_tx_list[ei]; 2616 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2617 2618 desc = &sc->rl_ldata.rl_tx_list[si]; 2619 /* Set SOF and transfer ownership of packet to the chip. */ 2620 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2621 2622 /* 2623 * Insure that the map for this transmission 2624 * is placed at the array index of the last descriptor 2625 * in this chain. (Swap last and first dmamaps.) 2626 */ 2627 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2628 map = txd->tx_dmamap; 2629 txd->tx_dmamap = txd_last->tx_dmamap; 2630 txd_last->tx_dmamap = map; 2631 txd_last->tx_m = *m_head; 2632 2633 return (0); 2634} 2635 2636static void 2637re_tx_task(void *arg, int npending) 2638{ 2639 struct ifnet *ifp; 2640 2641 ifp = arg; 2642 re_start(ifp); 2643} 2644 2645/* 2646 * Main transmit routine for C+ and gigE NICs. 2647 */ 2648static void 2649re_start(struct ifnet *ifp) 2650{ 2651 struct rl_softc *sc; 2652 struct mbuf *m_head; 2653 int queued; 2654 2655 sc = ifp->if_softc; 2656 2657 RL_LOCK(sc); 2658 2659 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2660 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2661 RL_UNLOCK(sc); 2662 return; 2663 } 2664 2665 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2666 sc->rl_ldata.rl_tx_free > 1;) { 2667 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2668 if (m_head == NULL) 2669 break; 2670 2671 if (re_encap(sc, &m_head) != 0) { 2672 if (m_head == NULL) 2673 break; 2674 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2675 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2676 break; 2677 } 2678 2679 /* 2680 * If there's a BPF listener, bounce a copy of this frame 2681 * to him. 2682 */ 2683 ETHER_BPF_MTAP(ifp, m_head); 2684 2685 queued++; 2686 } 2687 2688 if (queued == 0) { 2689#ifdef RE_TX_MODERATION 2690 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2691 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2692#endif 2693 RL_UNLOCK(sc); 2694 return; 2695 } 2696 2697 /* Flush the TX descriptors */ 2698 2699 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2700 sc->rl_ldata.rl_tx_list_map, 2701 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2702 2703 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2704 2705#ifdef RE_TX_MODERATION 2706 /* 2707 * Use the countdown timer for interrupt moderation. 2708 * 'TX done' interrupts are disabled. Instead, we reset the 2709 * countdown timer, which will begin counting until it hits 2710 * the value in the TIMERINT register, and then trigger an 2711 * interrupt. Each time we write to the TIMERCNT register, 2712 * the timer count is reset to 0. 2713 */ 2714 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2715#endif 2716 2717 /* 2718 * Set a timeout in case the chip goes out to lunch. 2719 */ 2720 sc->rl_watchdog_timer = 5; 2721 2722 RL_UNLOCK(sc); 2723} 2724 2725static void 2726re_set_jumbo(struct rl_softc *sc, int jumbo) 2727{ 2728 2729 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2730 pci_set_max_read_req(sc->rl_dev, 4096); 2731 return; 2732 } 2733 2734 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2735 if (jumbo != 0) { 2736 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) | 2737 RL_CFG3_JUMBO_EN0); 2738 switch (sc->rl_hwrev->rl_rev) { 2739 case RL_HWREV_8168DP: 2740 break; 2741 case RL_HWREV_8168E: 2742 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2743 0x01); 2744 break; 2745 default: 2746 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2747 RL_CFG4_JUMBO_EN1); 2748 } 2749 } else { 2750 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) & 2751 ~RL_CFG3_JUMBO_EN0); 2752 switch (sc->rl_hwrev->rl_rev) { 2753 case RL_HWREV_8168DP: 2754 break; 2755 case RL_HWREV_8168E: 2756 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2757 ~0x01); 2758 break; 2759 default: 2760 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2761 ~RL_CFG4_JUMBO_EN1); 2762 } 2763 } 2764 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2765 2766 switch (sc->rl_hwrev->rl_rev) { 2767 case RL_HWREV_8168DP: 2768 pci_set_max_read_req(sc->rl_dev, 4096); 2769 break; 2770 default: 2771 if (jumbo != 0) 2772 pci_set_max_read_req(sc->rl_dev, 512); 2773 else 2774 pci_set_max_read_req(sc->rl_dev, 4096); 2775 } 2776} 2777 2778static void 2779re_init(void *xsc) 2780{ 2781 struct rl_softc *sc = xsc; 2782 2783 RL_LOCK(sc); 2784 re_init_locked(sc); 2785 RL_UNLOCK(sc); 2786} 2787 2788static void 2789re_init_locked(struct rl_softc *sc) 2790{ 2791 struct ifnet *ifp = sc->rl_ifp; 2792 struct mii_data *mii; 2793 uint32_t reg; 2794 uint16_t cfg; 2795 union { 2796 uint32_t align_dummy; 2797 u_char eaddr[ETHER_ADDR_LEN]; 2798 } eaddr; 2799 2800 RL_LOCK_ASSERT(sc); 2801 2802 mii = device_get_softc(sc->rl_miibus); 2803 2804 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2805 return; 2806 2807 /* 2808 * Cancel pending I/O and free all RX/TX buffers. 2809 */ 2810 re_stop(sc); 2811 2812 /* Put controller into known state. */ 2813 re_reset(sc); 2814 2815 /* 2816 * For C+ mode, initialize the RX descriptors and mbufs. 2817 */ 2818 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 2819 if (ifp->if_mtu > RL_MTU) { 2820 if (re_jrx_list_init(sc) != 0) { 2821 device_printf(sc->rl_dev, 2822 "no memory for jumbo RX buffers\n"); 2823 re_stop(sc); 2824 return; 2825 } 2826 /* Disable checksum offloading for jumbo frames. */ 2827 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 2828 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 2829 } else { 2830 if (re_rx_list_init(sc) != 0) { 2831 device_printf(sc->rl_dev, 2832 "no memory for RX buffers\n"); 2833 re_stop(sc); 2834 return; 2835 } 2836 } 2837 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 2838 } else { 2839 if (re_rx_list_init(sc) != 0) { 2840 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 2841 re_stop(sc); 2842 return; 2843 } 2844 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 2845 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 2846 if (ifp->if_mtu > RL_MTU) 2847 pci_set_max_read_req(sc->rl_dev, 512); 2848 else 2849 pci_set_max_read_req(sc->rl_dev, 4096); 2850 } 2851 } 2852 re_tx_list_init(sc); 2853 2854 /* 2855 * Enable C+ RX and TX mode, as well as VLAN stripping and 2856 * RX checksum offload. We must configure the C+ register 2857 * before all others. 2858 */ 2859 cfg = RL_CPLUSCMD_PCI_MRW; 2860 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2861 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2862 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2863 cfg |= RL_CPLUSCMD_VLANSTRIP; 2864 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2865 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2866 /* XXX magic. */ 2867 cfg |= 0x0001; 2868 } else 2869 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2870 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2871 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 2872 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 2873 reg = 0x000fff00; 2874 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2875 reg |= 0x000000ff; 2876 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 2877 reg |= 0x00f00000; 2878 CSR_WRITE_4(sc, 0x7c, reg); 2879 /* Disable interrupt mitigation. */ 2880 CSR_WRITE_2(sc, 0xe2, 0); 2881 } 2882 /* 2883 * Disable TSO if interface MTU size is greater than MSS 2884 * allowed in controller. 2885 */ 2886 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2887 ifp->if_capenable &= ~IFCAP_TSO4; 2888 ifp->if_hwassist &= ~CSUM_TSO; 2889 } 2890 2891 /* 2892 * Init our MAC address. Even though the chipset 2893 * documentation doesn't mention it, we need to enter "Config 2894 * register write enable" mode to modify the ID registers. 2895 */ 2896 /* Copy MAC address on stack to align. */ 2897 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2898 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2899 CSR_WRITE_4(sc, RL_IDR0, 2900 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2901 CSR_WRITE_4(sc, RL_IDR4, 2902 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2903 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2904 2905 /* 2906 * Load the addresses of the RX and TX lists into the chip. 2907 */ 2908 2909 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2910 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2911 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2912 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2913 2914 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2915 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2916 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2917 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2918 2919 /* 2920 * Enable transmit and receive. 2921 */ 2922 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2923 2924 /* 2925 * Set the initial TX configuration. 2926 */ 2927 if (sc->rl_testmode) { 2928 if (sc->rl_type == RL_8169) 2929 CSR_WRITE_4(sc, RL_TXCFG, 2930 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2931 else 2932 CSR_WRITE_4(sc, RL_TXCFG, 2933 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2934 } else 2935 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2936 2937 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2938 2939 /* 2940 * Set the initial RX configuration. 2941 */ 2942 re_set_rxmode(sc); 2943 2944 /* Configure interrupt moderation. */ 2945 if (sc->rl_type == RL_8169) { 2946 /* Magic from vendor. */ 2947 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 2948 } 2949 2950#ifdef DEVICE_POLLING 2951 /* 2952 * Disable interrupts if we are polling. 2953 */ 2954 if (ifp->if_capenable & IFCAP_POLLING) 2955 CSR_WRITE_2(sc, RL_IMR, 0); 2956 else /* otherwise ... */ 2957#endif 2958 2959 /* 2960 * Enable interrupts. 2961 */ 2962 if (sc->rl_testmode) 2963 CSR_WRITE_2(sc, RL_IMR, 0); 2964 else 2965 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2966 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2967 2968 /* Set initial TX threshold */ 2969 sc->rl_txthresh = RL_TX_THRESH_INIT; 2970 2971 /* Start RX/TX process. */ 2972 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2973#ifdef notdef 2974 /* Enable receiver and transmitter. */ 2975 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2976#endif 2977 2978#ifdef RE_TX_MODERATION 2979 /* 2980 * Initialize the timer interrupt register so that 2981 * a timer interrupt will be generated once the timer 2982 * reaches a certain number of ticks. The timer is 2983 * reloaded on each transmit. This gives us TX interrupt 2984 * moderation, which dramatically improves TX frame rate. 2985 */ 2986 if (sc->rl_type == RL_8169) 2987 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2988 else 2989 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2990#endif 2991 2992 /* 2993 * For 8169 gigE NICs, set the max allowed RX packet 2994 * size so we can receive jumbo frames. 2995 */ 2996 if (sc->rl_type == RL_8169) { 2997 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 2998 /* 2999 * For controllers that use new jumbo frame scheme, 3000 * set maximum size of jumbo frame depedning on 3001 * controller revisions. 3002 */ 3003 if (ifp->if_mtu > RL_MTU) 3004 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3005 sc->rl_hwrev->rl_max_mtu + 3006 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3007 ETHER_CRC_LEN); 3008 else 3009 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3010 RE_RX_DESC_BUFLEN); 3011 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3012 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3013 /* RTL810x has no jumbo frame support. */ 3014 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3015 } else 3016 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3017 } 3018 3019 if (sc->rl_testmode) 3020 return; 3021 3022 mii_mediachg(mii); 3023 3024 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 3025 3026 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3027 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3028 3029 sc->rl_flags &= ~RL_FLAG_LINK; 3030 sc->rl_watchdog_timer = 0; 3031 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3032} 3033 3034/* 3035 * Set media options. 3036 */ 3037static int 3038re_ifmedia_upd(struct ifnet *ifp) 3039{ 3040 struct rl_softc *sc; 3041 struct mii_data *mii; 3042 int error; 3043 3044 sc = ifp->if_softc; 3045 mii = device_get_softc(sc->rl_miibus); 3046 RL_LOCK(sc); 3047 error = mii_mediachg(mii); 3048 RL_UNLOCK(sc); 3049 3050 return (error); 3051} 3052 3053/* 3054 * Report current media status. 3055 */ 3056static void 3057re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3058{ 3059 struct rl_softc *sc; 3060 struct mii_data *mii; 3061 3062 sc = ifp->if_softc; 3063 mii = device_get_softc(sc->rl_miibus); 3064 3065 RL_LOCK(sc); 3066 mii_pollstat(mii); 3067 RL_UNLOCK(sc); 3068 ifmr->ifm_active = mii->mii_media_active; 3069 ifmr->ifm_status = mii->mii_media_status; 3070} 3071 3072static int 3073re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3074{ 3075 struct rl_softc *sc = ifp->if_softc; 3076 struct ifreq *ifr = (struct ifreq *) data; 3077 struct mii_data *mii; 3078 int error = 0; 3079 3080 switch (command) { 3081 case SIOCSIFMTU: 3082 if (ifr->ifr_mtu < ETHERMIN || 3083 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) { 3084 error = EINVAL; 3085 break; 3086 } 3087 RL_LOCK(sc); 3088 if (ifp->if_mtu != ifr->ifr_mtu) { 3089 ifp->if_mtu = ifr->ifr_mtu; 3090 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3091 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3092 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3093 re_init_locked(sc); 3094 } 3095 if (ifp->if_mtu > RL_TSO_MTU && 3096 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3097 ifp->if_capenable &= ~(IFCAP_TSO4 | 3098 IFCAP_VLAN_HWTSO); 3099 ifp->if_hwassist &= ~CSUM_TSO; 3100 } 3101 VLAN_CAPABILITIES(ifp); 3102 } 3103 RL_UNLOCK(sc); 3104 break; 3105 case SIOCSIFFLAGS: 3106 RL_LOCK(sc); 3107 if ((ifp->if_flags & IFF_UP) != 0) { 3108 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3109 if (((ifp->if_flags ^ sc->rl_if_flags) 3110 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3111 re_set_rxmode(sc); 3112 } else 3113 re_init_locked(sc); 3114 } else { 3115 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3116 re_stop(sc); 3117 } 3118 sc->rl_if_flags = ifp->if_flags; 3119 RL_UNLOCK(sc); 3120 break; 3121 case SIOCADDMULTI: 3122 case SIOCDELMULTI: 3123 RL_LOCK(sc); 3124 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3125 re_set_rxmode(sc); 3126 RL_UNLOCK(sc); 3127 break; 3128 case SIOCGIFMEDIA: 3129 case SIOCSIFMEDIA: 3130 mii = device_get_softc(sc->rl_miibus); 3131 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3132 break; 3133 case SIOCSIFCAP: 3134 { 3135 int mask, reinit; 3136 3137 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3138 reinit = 0; 3139#ifdef DEVICE_POLLING 3140 if (mask & IFCAP_POLLING) { 3141 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3142 error = ether_poll_register(re_poll, ifp); 3143 if (error) 3144 return (error); 3145 RL_LOCK(sc); 3146 /* Disable interrupts */ 3147 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3148 ifp->if_capenable |= IFCAP_POLLING; 3149 RL_UNLOCK(sc); 3150 } else { 3151 error = ether_poll_deregister(ifp); 3152 /* Enable interrupts. */ 3153 RL_LOCK(sc); 3154 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3155 ifp->if_capenable &= ~IFCAP_POLLING; 3156 RL_UNLOCK(sc); 3157 } 3158 } 3159#endif /* DEVICE_POLLING */ 3160 if ((mask & IFCAP_TXCSUM) != 0 && 3161 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3162 ifp->if_capenable ^= IFCAP_TXCSUM; 3163 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3164 ifp->if_hwassist |= RE_CSUM_FEATURES; 3165 else 3166 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3167 reinit = 1; 3168 } 3169 if ((mask & IFCAP_RXCSUM) != 0 && 3170 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3171 ifp->if_capenable ^= IFCAP_RXCSUM; 3172 reinit = 1; 3173 } 3174 if ((mask & IFCAP_TSO4) != 0 && 3175 (ifp->if_capabilities & IFCAP_TSO) != 0) { 3176 ifp->if_capenable ^= IFCAP_TSO4; 3177 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3178 ifp->if_hwassist |= CSUM_TSO; 3179 else 3180 ifp->if_hwassist &= ~CSUM_TSO; 3181 if (ifp->if_mtu > RL_TSO_MTU && 3182 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3183 ifp->if_capenable &= ~IFCAP_TSO4; 3184 ifp->if_hwassist &= ~CSUM_TSO; 3185 } 3186 } 3187 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3188 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3189 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3190 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3191 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3192 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3193 /* TSO over VLAN requires VLAN hardware tagging. */ 3194 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3195 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3196 reinit = 1; 3197 } 3198 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3199 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3200 IFCAP_VLAN_HWTSO)) != 0) 3201 reinit = 1; 3202 if ((mask & IFCAP_WOL) != 0 && 3203 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3204 if ((mask & IFCAP_WOL_UCAST) != 0) 3205 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3206 if ((mask & IFCAP_WOL_MCAST) != 0) 3207 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3208 if ((mask & IFCAP_WOL_MAGIC) != 0) 3209 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3210 } 3211 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3212 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3213 re_init(sc); 3214 } 3215 VLAN_CAPABILITIES(ifp); 3216 } 3217 break; 3218 default: 3219 error = ether_ioctl(ifp, command, data); 3220 break; 3221 } 3222 3223 return (error); 3224} 3225 3226static void 3227re_watchdog(struct rl_softc *sc) 3228{ 3229 struct ifnet *ifp; 3230 3231 RL_LOCK_ASSERT(sc); 3232 3233 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3234 return; 3235 3236 ifp = sc->rl_ifp; 3237 re_txeof(sc); 3238 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3239 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3240 "-- recovering\n"); 3241 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3242 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 3243 return; 3244 } 3245 3246 if_printf(ifp, "watchdog timeout\n"); 3247 ifp->if_oerrors++; 3248 3249 re_rxeof(sc, NULL); 3250 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3251 re_init_locked(sc); 3252 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3253 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 3254} 3255 3256/* 3257 * Stop the adapter and free any mbufs allocated to the 3258 * RX and TX lists. 3259 */ 3260static void 3261re_stop(struct rl_softc *sc) 3262{ 3263 int i; 3264 struct ifnet *ifp; 3265 struct rl_txdesc *txd; 3266 struct rl_rxdesc *rxd; 3267 3268 RL_LOCK_ASSERT(sc); 3269 3270 ifp = sc->rl_ifp; 3271 3272 sc->rl_watchdog_timer = 0; 3273 callout_stop(&sc->rl_stat_callout); 3274 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3275 3276 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 3277 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3278 RL_CMD_RX_ENB); 3279 else 3280 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3281 DELAY(1000); 3282 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3283 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3284 3285 if (sc->rl_head != NULL) { 3286 m_freem(sc->rl_head); 3287 sc->rl_head = sc->rl_tail = NULL; 3288 } 3289 3290 /* Free the TX list buffers. */ 3291 3292 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3293 txd = &sc->rl_ldata.rl_tx_desc[i]; 3294 if (txd->tx_m != NULL) { 3295 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3296 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3297 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3298 txd->tx_dmamap); 3299 m_freem(txd->tx_m); 3300 txd->tx_m = NULL; 3301 } 3302 } 3303 3304 /* Free the RX list buffers. */ 3305 3306 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3307 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3308 if (rxd->rx_m != NULL) { 3309 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3310 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3311 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3312 rxd->rx_dmamap); 3313 m_freem(rxd->rx_m); 3314 rxd->rx_m = NULL; 3315 } 3316 } 3317} 3318 3319/* 3320 * Device suspend routine. Stop the interface and save some PCI 3321 * settings in case the BIOS doesn't restore them properly on 3322 * resume. 3323 */ 3324static int 3325re_suspend(device_t dev) 3326{ 3327 struct rl_softc *sc; 3328 3329 sc = device_get_softc(dev); 3330 3331 RL_LOCK(sc); 3332 re_stop(sc); 3333 re_setwol(sc); 3334 sc->suspended = 1; 3335 RL_UNLOCK(sc); 3336 3337 return (0); 3338} 3339 3340/* 3341 * Device resume routine. Restore some PCI settings in case the BIOS 3342 * doesn't, re-enable busmastering, and restart the interface if 3343 * appropriate. 3344 */ 3345static int 3346re_resume(device_t dev) 3347{ 3348 struct rl_softc *sc; 3349 struct ifnet *ifp; 3350 3351 sc = device_get_softc(dev); 3352 3353 RL_LOCK(sc); 3354 3355 ifp = sc->rl_ifp; 3356 /* Take controller out of sleep mode. */ 3357 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3358 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3359 CSR_WRITE_1(sc, RL_GPIO, 3360 CSR_READ_1(sc, RL_GPIO) | 0x01); 3361 } 3362 3363 /* 3364 * Clear WOL matching such that normal Rx filtering 3365 * wouldn't interfere with WOL patterns. 3366 */ 3367 re_clrwol(sc); 3368 3369 /* reinitialize interface if necessary */ 3370 if (ifp->if_flags & IFF_UP) 3371 re_init_locked(sc); 3372 3373 sc->suspended = 0; 3374 RL_UNLOCK(sc); 3375 3376 return (0); 3377} 3378 3379/* 3380 * Stop all chip I/O so that the kernel's probe routines don't 3381 * get confused by errant DMAs when rebooting. 3382 */ 3383static int 3384re_shutdown(device_t dev) 3385{ 3386 struct rl_softc *sc; 3387 3388 sc = device_get_softc(dev); 3389 3390 RL_LOCK(sc); 3391 re_stop(sc); 3392 /* 3393 * Mark interface as down since otherwise we will panic if 3394 * interrupt comes in later on, which can happen in some 3395 * cases. 3396 */ 3397 sc->rl_ifp->if_flags &= ~IFF_UP; 3398 re_setwol(sc); 3399 RL_UNLOCK(sc); 3400 3401 return (0); 3402} 3403 3404static void 3405re_setwol(struct rl_softc *sc) 3406{ 3407 struct ifnet *ifp; 3408 int pmc; 3409 uint16_t pmstat; 3410 uint8_t v; 3411 3412 RL_LOCK_ASSERT(sc); 3413 3414 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3415 return; 3416 3417 ifp = sc->rl_ifp; 3418 /* Put controller into sleep mode. */ 3419 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3420 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3421 CSR_WRITE_1(sc, RL_GPIO, 3422 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3423 } 3424 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3425 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3426 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3427 /* Enable config register write. */ 3428 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3429 3430 /* Enable PME. */ 3431 v = CSR_READ_1(sc, RL_CFG1); 3432 v &= ~RL_CFG1_PME; 3433 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3434 v |= RL_CFG1_PME; 3435 CSR_WRITE_1(sc, RL_CFG1, v); 3436 3437 v = CSR_READ_1(sc, RL_CFG3); 3438 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3439 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3440 v |= RL_CFG3_WOL_MAGIC; 3441 CSR_WRITE_1(sc, RL_CFG3, v); 3442 3443 /* Config register write done. */ 3444 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3445 3446 v = CSR_READ_1(sc, RL_CFG5); 3447 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3448 v &= ~RL_CFG5_WOL_LANWAKE; 3449 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3450 v |= RL_CFG5_WOL_UCAST; 3451 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3452 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3453 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3454 v |= RL_CFG5_WOL_LANWAKE; 3455 CSR_WRITE_1(sc, RL_CFG5, v); 3456 3457 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3458 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3459 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3460 /* 3461 * It seems that hardware resets its link speed to 100Mbps in 3462 * power down mode so switching to 100Mbps in driver is not 3463 * needed. 3464 */ 3465 3466 /* Request PME if WOL is requested. */ 3467 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3468 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3469 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3470 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3471 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3472} 3473 3474static void 3475re_clrwol(struct rl_softc *sc) 3476{ 3477 int pmc; 3478 uint8_t v; 3479 3480 RL_LOCK_ASSERT(sc); 3481 3482 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3483 return; 3484 3485 /* Enable config register write. */ 3486 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3487 3488 v = CSR_READ_1(sc, RL_CFG3); 3489 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3490 CSR_WRITE_1(sc, RL_CFG3, v); 3491 3492 /* Config register write done. */ 3493 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3494 3495 v = CSR_READ_1(sc, RL_CFG5); 3496 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3497 v &= ~RL_CFG5_WOL_LANWAKE; 3498 CSR_WRITE_1(sc, RL_CFG5, v); 3499} 3500 3501static void 3502re_add_sysctls(struct rl_softc *sc) 3503{ 3504 struct sysctl_ctx_list *ctx; 3505 struct sysctl_oid_list *children; 3506 3507 ctx = device_get_sysctl_ctx(sc->rl_dev); 3508 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3509 3510 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3511 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3512 "Statistics Information"); 3513} 3514 3515static int 3516re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3517{ 3518 struct rl_softc *sc; 3519 struct rl_stats *stats; 3520 int error, i, result; 3521 3522 result = -1; 3523 error = sysctl_handle_int(oidp, &result, 0, req); 3524 if (error || req->newptr == NULL) 3525 return (error); 3526 3527 if (result == 1) { 3528 sc = (struct rl_softc *)arg1; 3529 RL_LOCK(sc); 3530 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3531 RL_UNLOCK(sc); 3532 goto done; 3533 } 3534 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3535 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3536 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3537 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3538 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3539 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3540 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3541 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3542 RL_DUMPSTATS_START)); 3543 for (i = RL_TIMEOUT; i > 0; i--) { 3544 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3545 RL_DUMPSTATS_START) == 0) 3546 break; 3547 DELAY(1000); 3548 } 3549 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3550 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3551 RL_UNLOCK(sc); 3552 if (i == 0) { 3553 device_printf(sc->rl_dev, 3554 "DUMP statistics request timedout\n"); 3555 return (ETIMEDOUT); 3556 } 3557done: 3558 stats = sc->rl_ldata.rl_stats; 3559 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3560 printf("Tx frames : %ju\n", 3561 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3562 printf("Rx frames : %ju\n", 3563 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3564 printf("Tx errors : %ju\n", 3565 (uintmax_t)le64toh(stats->rl_tx_errs)); 3566 printf("Rx errors : %u\n", 3567 le32toh(stats->rl_rx_errs)); 3568 printf("Rx missed frames : %u\n", 3569 (uint32_t)le16toh(stats->rl_missed_pkts)); 3570 printf("Rx frame alignment errs : %u\n", 3571 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3572 printf("Tx single collisions : %u\n", 3573 le32toh(stats->rl_tx_onecoll)); 3574 printf("Tx multiple collisions : %u\n", 3575 le32toh(stats->rl_tx_multicolls)); 3576 printf("Rx unicast frames : %ju\n", 3577 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3578 printf("Rx broadcast frames : %ju\n", 3579 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3580 printf("Rx multicast frames : %u\n", 3581 le32toh(stats->rl_rx_mcasts)); 3582 printf("Tx aborts : %u\n", 3583 (uint32_t)le16toh(stats->rl_tx_aborts)); 3584 printf("Tx underruns : %u\n", 3585 (uint32_t)le16toh(stats->rl_rx_underruns)); 3586 } 3587 3588 return (error); 3589} 3590