if_re.c revision 217246
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 217246 2011-01-10 23:28:46Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/sysctl.h> 127#include <sys/taskqueue.h> 128 129#include <net/if.h> 130#include <net/if_arp.h> 131#include <net/ethernet.h> 132#include <net/if_dl.h> 133#include <net/if_media.h> 134#include <net/if_types.h> 135#include <net/if_vlan_var.h> 136 137#include <net/bpf.h> 138 139#include <machine/bus.h> 140#include <machine/resource.h> 141#include <sys/bus.h> 142#include <sys/rman.h> 143 144#include <dev/mii/mii.h> 145#include <dev/mii/miivar.h> 146 147#include <dev/pci/pcireg.h> 148#include <dev/pci/pcivar.h> 149 150#include <pci/if_rlreg.h> 151 152MODULE_DEPEND(re, pci, 1, 1, 1); 153MODULE_DEPEND(re, ether, 1, 1, 1); 154MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156/* "device miibus" required. See GENERIC if you get errors here. */ 157#include "miibus_if.h" 158 159/* Tunables. */ 160static int msi_disable = 0; 161TUNABLE_INT("hw.re.msi_disable", &msi_disable); 162static int prefer_iomap = 0; 163TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 164 165#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 166 167/* 168 * Various supported device vendors/types and their names. 169 */ 170static struct rl_type re_devs[] = { 171 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 172 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 173 { RT_VENDORID, RT_DEVICEID_8139, 0, 174 "RealTek 8139C+ 10/100BaseTX" }, 175 { RT_VENDORID, RT_DEVICEID_8101E, 0, 176 "RealTek 8101E/8102E/8102EL/8103E PCIe 10/100baseTX" }, 177 { RT_VENDORID, RT_DEVICEID_8168, 0, 178 "RealTek 8168/8111 B/C/CP/D/DP/E PCIe Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, 0, 180 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 184 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 185 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 186 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 187 { USR_VENDORID, USR_DEVICEID_997902, 0, 188 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 189}; 190 191static struct rl_hwrev re_hwrevs[] = { 192 { RL_HWREV_8139, RL_8139, "" }, 193 { RL_HWREV_8139A, RL_8139, "A" }, 194 { RL_HWREV_8139AG, RL_8139, "A-G" }, 195 { RL_HWREV_8139B, RL_8139, "B" }, 196 { RL_HWREV_8130, RL_8139, "8130" }, 197 { RL_HWREV_8139C, RL_8139, "C" }, 198 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 199 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 200 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 201 { RL_HWREV_8169, RL_8169, "8169"}, 202 { RL_HWREV_8169S, RL_8169, "8169S"}, 203 { RL_HWREV_8110S, RL_8169, "8110S"}, 204 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 205 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 206 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 207 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, 208 { RL_HWREV_8100, RL_8139, "8100"}, 209 { RL_HWREV_8101, RL_8139, "8101"}, 210 { RL_HWREV_8100E, RL_8169, "8100E"}, 211 { RL_HWREV_8101E, RL_8169, "8101E"}, 212 { RL_HWREV_8102E, RL_8169, "8102E"}, 213 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 214 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL"}, 215 { RL_HWREV_8103E, RL_8169, "8103E"}, 216 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 217 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 218 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 219 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 220 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 221 { RL_HWREV_8168D, RL_8169, "8168D/8111D"}, 222 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP"}, 223 { RL_HWREV_8168E, RL_8169, "8168E/8111E"}, 224 { 0, 0, NULL } 225}; 226 227static int re_probe (device_t); 228static int re_attach (device_t); 229static int re_detach (device_t); 230 231static int re_encap (struct rl_softc *, struct mbuf **); 232 233static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 234static int re_allocmem (device_t, struct rl_softc *); 235static __inline void re_discard_rxbuf 236 (struct rl_softc *, int); 237static int re_newbuf (struct rl_softc *, int); 238static int re_rx_list_init (struct rl_softc *); 239static int re_tx_list_init (struct rl_softc *); 240#ifdef RE_FIXUP_RX 241static __inline void re_fixup_rx 242 (struct mbuf *); 243#endif 244static int re_rxeof (struct rl_softc *, int *); 245static void re_txeof (struct rl_softc *); 246#ifdef DEVICE_POLLING 247static int re_poll (struct ifnet *, enum poll_cmd, int); 248static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 249#endif 250static int re_intr (void *); 251static void re_tick (void *); 252static void re_tx_task (void *, int); 253static void re_int_task (void *, int); 254static void re_start (struct ifnet *); 255static int re_ioctl (struct ifnet *, u_long, caddr_t); 256static void re_init (void *); 257static void re_init_locked (struct rl_softc *); 258static void re_stop (struct rl_softc *); 259static void re_watchdog (struct rl_softc *); 260static int re_suspend (device_t); 261static int re_resume (device_t); 262static int re_shutdown (device_t); 263static int re_ifmedia_upd (struct ifnet *); 264static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 265 266static void re_eeprom_putbyte (struct rl_softc *, int); 267static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 268static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 269static int re_gmii_readreg (device_t, int, int); 270static int re_gmii_writereg (device_t, int, int, int); 271 272static int re_miibus_readreg (device_t, int, int); 273static int re_miibus_writereg (device_t, int, int, int); 274static void re_miibus_statchg (device_t); 275 276static void re_set_rxmode (struct rl_softc *); 277static void re_reset (struct rl_softc *); 278static void re_setwol (struct rl_softc *); 279static void re_clrwol (struct rl_softc *); 280 281#ifdef RE_DIAG 282static int re_diag (struct rl_softc *); 283#endif 284 285static void re_add_sysctls (struct rl_softc *); 286static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 287 288static device_method_t re_methods[] = { 289 /* Device interface */ 290 DEVMETHOD(device_probe, re_probe), 291 DEVMETHOD(device_attach, re_attach), 292 DEVMETHOD(device_detach, re_detach), 293 DEVMETHOD(device_suspend, re_suspend), 294 DEVMETHOD(device_resume, re_resume), 295 DEVMETHOD(device_shutdown, re_shutdown), 296 297 /* bus interface */ 298 DEVMETHOD(bus_print_child, bus_generic_print_child), 299 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 300 301 /* MII interface */ 302 DEVMETHOD(miibus_readreg, re_miibus_readreg), 303 DEVMETHOD(miibus_writereg, re_miibus_writereg), 304 DEVMETHOD(miibus_statchg, re_miibus_statchg), 305 306 { 0, 0 } 307}; 308 309static driver_t re_driver = { 310 "re", 311 re_methods, 312 sizeof(struct rl_softc) 313}; 314 315static devclass_t re_devclass; 316 317DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 318DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 319 320#define EE_SET(x) \ 321 CSR_WRITE_1(sc, RL_EECMD, \ 322 CSR_READ_1(sc, RL_EECMD) | x) 323 324#define EE_CLR(x) \ 325 CSR_WRITE_1(sc, RL_EECMD, \ 326 CSR_READ_1(sc, RL_EECMD) & ~x) 327 328/* 329 * Send a read command and address to the EEPROM, check for ACK. 330 */ 331static void 332re_eeprom_putbyte(struct rl_softc *sc, int addr) 333{ 334 int d, i; 335 336 d = addr | (RL_9346_READ << sc->rl_eewidth); 337 338 /* 339 * Feed in each bit and strobe the clock. 340 */ 341 342 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 343 if (d & i) { 344 EE_SET(RL_EE_DATAIN); 345 } else { 346 EE_CLR(RL_EE_DATAIN); 347 } 348 DELAY(100); 349 EE_SET(RL_EE_CLK); 350 DELAY(150); 351 EE_CLR(RL_EE_CLK); 352 DELAY(100); 353 } 354} 355 356/* 357 * Read a word of data stored in the EEPROM at address 'addr.' 358 */ 359static void 360re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 361{ 362 int i; 363 u_int16_t word = 0; 364 365 /* 366 * Send address of word we want to read. 367 */ 368 re_eeprom_putbyte(sc, addr); 369 370 /* 371 * Start reading bits from EEPROM. 372 */ 373 for (i = 0x8000; i; i >>= 1) { 374 EE_SET(RL_EE_CLK); 375 DELAY(100); 376 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 377 word |= i; 378 EE_CLR(RL_EE_CLK); 379 DELAY(100); 380 } 381 382 *dest = word; 383} 384 385/* 386 * Read a sequence of words from the EEPROM. 387 */ 388static void 389re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 390{ 391 int i; 392 u_int16_t word = 0, *ptr; 393 394 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 395 396 DELAY(100); 397 398 for (i = 0; i < cnt; i++) { 399 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 400 re_eeprom_getword(sc, off + i, &word); 401 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 402 ptr = (u_int16_t *)(dest + (i * 2)); 403 *ptr = word; 404 } 405 406 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 407} 408 409static int 410re_gmii_readreg(device_t dev, int phy, int reg) 411{ 412 struct rl_softc *sc; 413 u_int32_t rval; 414 int i; 415 416 sc = device_get_softc(dev); 417 418 /* Let the rgephy driver read the GMEDIASTAT register */ 419 420 if (reg == RL_GMEDIASTAT) { 421 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 422 return (rval); 423 } 424 425 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 426 427 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 428 rval = CSR_READ_4(sc, RL_PHYAR); 429 if (rval & RL_PHYAR_BUSY) 430 break; 431 DELAY(25); 432 } 433 434 if (i == RL_PHY_TIMEOUT) { 435 device_printf(sc->rl_dev, "PHY read failed\n"); 436 return (0); 437 } 438 439 /* 440 * Controller requires a 20us delay to process next MDIO request. 441 */ 442 DELAY(20); 443 444 return (rval & RL_PHYAR_PHYDATA); 445} 446 447static int 448re_gmii_writereg(device_t dev, int phy, int reg, int data) 449{ 450 struct rl_softc *sc; 451 u_int32_t rval; 452 int i; 453 454 sc = device_get_softc(dev); 455 456 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 457 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 458 459 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 460 rval = CSR_READ_4(sc, RL_PHYAR); 461 if (!(rval & RL_PHYAR_BUSY)) 462 break; 463 DELAY(25); 464 } 465 466 if (i == RL_PHY_TIMEOUT) { 467 device_printf(sc->rl_dev, "PHY write failed\n"); 468 return (0); 469 } 470 471 /* 472 * Controller requires a 20us delay to process next MDIO request. 473 */ 474 DELAY(20); 475 476 return (0); 477} 478 479static int 480re_miibus_readreg(device_t dev, int phy, int reg) 481{ 482 struct rl_softc *sc; 483 u_int16_t rval = 0; 484 u_int16_t re8139_reg = 0; 485 486 sc = device_get_softc(dev); 487 488 if (sc->rl_type == RL_8169) { 489 rval = re_gmii_readreg(dev, phy, reg); 490 return (rval); 491 } 492 493 switch (reg) { 494 case MII_BMCR: 495 re8139_reg = RL_BMCR; 496 break; 497 case MII_BMSR: 498 re8139_reg = RL_BMSR; 499 break; 500 case MII_ANAR: 501 re8139_reg = RL_ANAR; 502 break; 503 case MII_ANER: 504 re8139_reg = RL_ANER; 505 break; 506 case MII_ANLPAR: 507 re8139_reg = RL_LPAR; 508 break; 509 case MII_PHYIDR1: 510 case MII_PHYIDR2: 511 return (0); 512 /* 513 * Allow the rlphy driver to read the media status 514 * register. If we have a link partner which does not 515 * support NWAY, this is the register which will tell 516 * us the results of parallel detection. 517 */ 518 case RL_MEDIASTAT: 519 rval = CSR_READ_1(sc, RL_MEDIASTAT); 520 return (rval); 521 default: 522 device_printf(sc->rl_dev, "bad phy register\n"); 523 return (0); 524 } 525 rval = CSR_READ_2(sc, re8139_reg); 526 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 527 /* 8139C+ has different bit layout. */ 528 rval &= ~(BMCR_LOOP | BMCR_ISO); 529 } 530 return (rval); 531} 532 533static int 534re_miibus_writereg(device_t dev, int phy, int reg, int data) 535{ 536 struct rl_softc *sc; 537 u_int16_t re8139_reg = 0; 538 int rval = 0; 539 540 sc = device_get_softc(dev); 541 542 if (sc->rl_type == RL_8169) { 543 rval = re_gmii_writereg(dev, phy, reg, data); 544 return (rval); 545 } 546 547 switch (reg) { 548 case MII_BMCR: 549 re8139_reg = RL_BMCR; 550 if (sc->rl_type == RL_8139CPLUS) { 551 /* 8139C+ has different bit layout. */ 552 data &= ~(BMCR_LOOP | BMCR_ISO); 553 } 554 break; 555 case MII_BMSR: 556 re8139_reg = RL_BMSR; 557 break; 558 case MII_ANAR: 559 re8139_reg = RL_ANAR; 560 break; 561 case MII_ANER: 562 re8139_reg = RL_ANER; 563 break; 564 case MII_ANLPAR: 565 re8139_reg = RL_LPAR; 566 break; 567 case MII_PHYIDR1: 568 case MII_PHYIDR2: 569 return (0); 570 break; 571 default: 572 device_printf(sc->rl_dev, "bad phy register\n"); 573 return (0); 574 } 575 CSR_WRITE_2(sc, re8139_reg, data); 576 return (0); 577} 578 579static void 580re_miibus_statchg(device_t dev) 581{ 582 struct rl_softc *sc; 583 struct ifnet *ifp; 584 struct mii_data *mii; 585 586 sc = device_get_softc(dev); 587 mii = device_get_softc(sc->rl_miibus); 588 ifp = sc->rl_ifp; 589 if (mii == NULL || ifp == NULL || 590 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 591 return; 592 593 sc->rl_flags &= ~RL_FLAG_LINK; 594 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 595 (IFM_ACTIVE | IFM_AVALID)) { 596 switch (IFM_SUBTYPE(mii->mii_media_active)) { 597 case IFM_10_T: 598 case IFM_100_TX: 599 sc->rl_flags |= RL_FLAG_LINK; 600 break; 601 case IFM_1000_T: 602 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 603 break; 604 sc->rl_flags |= RL_FLAG_LINK; 605 break; 606 default: 607 break; 608 } 609 } 610 /* 611 * RealTek controllers does not provide any interface to 612 * Tx/Rx MACs for resolved speed, duplex and flow-control 613 * parameters. 614 */ 615} 616 617/* 618 * Set the RX configuration and 64-bit multicast hash filter. 619 */ 620static void 621re_set_rxmode(struct rl_softc *sc) 622{ 623 struct ifnet *ifp; 624 struct ifmultiaddr *ifma; 625 uint32_t hashes[2] = { 0, 0 }; 626 uint32_t h, rxfilt; 627 628 RL_LOCK_ASSERT(sc); 629 630 ifp = sc->rl_ifp; 631 632 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 633 634 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 635 if (ifp->if_flags & IFF_PROMISC) 636 rxfilt |= RL_RXCFG_RX_ALLPHYS; 637 /* 638 * Unlike other hardwares, we have to explicitly set 639 * RL_RXCFG_RX_MULTI to receive multicast frames in 640 * promiscuous mode. 641 */ 642 rxfilt |= RL_RXCFG_RX_MULTI; 643 hashes[0] = hashes[1] = 0xffffffff; 644 goto done; 645 } 646 647 if_maddr_rlock(ifp); 648 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 649 if (ifma->ifma_addr->sa_family != AF_LINK) 650 continue; 651 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 652 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 653 if (h < 32) 654 hashes[0] |= (1 << h); 655 else 656 hashes[1] |= (1 << (h - 32)); 657 } 658 if_maddr_runlock(ifp); 659 660 if (hashes[0] != 0 || hashes[1] != 0) { 661 /* 662 * For some unfathomable reason, RealTek decided to 663 * reverse the order of the multicast hash registers 664 * in the PCI Express parts. This means we have to 665 * write the hash pattern in reverse order for those 666 * devices. 667 */ 668 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 669 h = bswap32(hashes[0]); 670 hashes[0] = bswap32(hashes[1]); 671 hashes[1] = h; 672 } 673 rxfilt |= RL_RXCFG_RX_MULTI; 674 } 675 676done: 677 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 678 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 679 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 680} 681 682static void 683re_reset(struct rl_softc *sc) 684{ 685 int i; 686 687 RL_LOCK_ASSERT(sc); 688 689 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 690 691 for (i = 0; i < RL_TIMEOUT; i++) { 692 DELAY(10); 693 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 694 break; 695 } 696 if (i == RL_TIMEOUT) 697 device_printf(sc->rl_dev, "reset never completed!\n"); 698 699 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 700 CSR_WRITE_1(sc, 0x82, 1); 701 if (sc->rl_hwrev == RL_HWREV_8169S) 702 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 703} 704 705#ifdef RE_DIAG 706 707/* 708 * The following routine is designed to test for a defect on some 709 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 710 * lines connected to the bus, however for a 32-bit only card, they 711 * should be pulled high. The result of this defect is that the 712 * NIC will not work right if you plug it into a 64-bit slot: DMA 713 * operations will be done with 64-bit transfers, which will fail 714 * because the 64-bit data lines aren't connected. 715 * 716 * There's no way to work around this (short of talking a soldering 717 * iron to the board), however we can detect it. The method we use 718 * here is to put the NIC into digital loopback mode, set the receiver 719 * to promiscuous mode, and then try to send a frame. We then compare 720 * the frame data we sent to what was received. If the data matches, 721 * then the NIC is working correctly, otherwise we know the user has 722 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 723 * slot. In the latter case, there's no way the NIC can work correctly, 724 * so we print out a message on the console and abort the device attach. 725 */ 726 727static int 728re_diag(struct rl_softc *sc) 729{ 730 struct ifnet *ifp = sc->rl_ifp; 731 struct mbuf *m0; 732 struct ether_header *eh; 733 struct rl_desc *cur_rx; 734 u_int16_t status; 735 u_int32_t rxstat; 736 int total_len, i, error = 0, phyaddr; 737 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 738 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 739 740 /* Allocate a single mbuf */ 741 MGETHDR(m0, M_DONTWAIT, MT_DATA); 742 if (m0 == NULL) 743 return (ENOBUFS); 744 745 RL_LOCK(sc); 746 747 /* 748 * Initialize the NIC in test mode. This sets the chip up 749 * so that it can send and receive frames, but performs the 750 * following special functions: 751 * - Puts receiver in promiscuous mode 752 * - Enables digital loopback mode 753 * - Leaves interrupts turned off 754 */ 755 756 ifp->if_flags |= IFF_PROMISC; 757 sc->rl_testmode = 1; 758 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 759 re_init_locked(sc); 760 sc->rl_flags |= RL_FLAG_LINK; 761 if (sc->rl_type == RL_8169) 762 phyaddr = 1; 763 else 764 phyaddr = 0; 765 766 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 767 for (i = 0; i < RL_TIMEOUT; i++) { 768 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 769 if (!(status & BMCR_RESET)) 770 break; 771 } 772 773 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 774 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 775 776 DELAY(100000); 777 778 /* Put some data in the mbuf */ 779 780 eh = mtod(m0, struct ether_header *); 781 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 782 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 783 eh->ether_type = htons(ETHERTYPE_IP); 784 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 785 786 /* 787 * Queue the packet, start transmission. 788 * Note: IF_HANDOFF() ultimately calls re_start() for us. 789 */ 790 791 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 792 RL_UNLOCK(sc); 793 /* XXX: re_diag must not be called when in ALTQ mode */ 794 IF_HANDOFF(&ifp->if_snd, m0, ifp); 795 RL_LOCK(sc); 796 m0 = NULL; 797 798 /* Wait for it to propagate through the chip */ 799 800 DELAY(100000); 801 for (i = 0; i < RL_TIMEOUT; i++) { 802 status = CSR_READ_2(sc, RL_ISR); 803 CSR_WRITE_2(sc, RL_ISR, status); 804 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 805 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 806 break; 807 DELAY(10); 808 } 809 810 if (i == RL_TIMEOUT) { 811 device_printf(sc->rl_dev, 812 "diagnostic failed, failed to receive packet in" 813 " loopback mode\n"); 814 error = EIO; 815 goto done; 816 } 817 818 /* 819 * The packet should have been dumped into the first 820 * entry in the RX DMA ring. Grab it from there. 821 */ 822 823 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 824 sc->rl_ldata.rl_rx_list_map, 825 BUS_DMASYNC_POSTREAD); 826 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 827 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 828 BUS_DMASYNC_POSTREAD); 829 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 830 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 831 832 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 833 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 834 eh = mtod(m0, struct ether_header *); 835 836 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 837 total_len = RL_RXBYTES(cur_rx); 838 rxstat = le32toh(cur_rx->rl_cmdstat); 839 840 if (total_len != ETHER_MIN_LEN) { 841 device_printf(sc->rl_dev, 842 "diagnostic failed, received short packet\n"); 843 error = EIO; 844 goto done; 845 } 846 847 /* Test that the received packet data matches what we sent. */ 848 849 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 850 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 851 ntohs(eh->ether_type) != ETHERTYPE_IP) { 852 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 853 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 854 dst, ":", src, ":", ETHERTYPE_IP); 855 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 856 eh->ether_dhost, ":", eh->ether_shost, ":", 857 ntohs(eh->ether_type)); 858 device_printf(sc->rl_dev, "You may have a defective 32-bit " 859 "NIC plugged into a 64-bit PCI slot.\n"); 860 device_printf(sc->rl_dev, "Please re-install the NIC in a " 861 "32-bit slot for proper operation.\n"); 862 device_printf(sc->rl_dev, "Read the re(4) man page for more " 863 "details.\n"); 864 error = EIO; 865 } 866 867done: 868 /* Turn interface off, release resources */ 869 870 sc->rl_testmode = 0; 871 sc->rl_flags &= ~RL_FLAG_LINK; 872 ifp->if_flags &= ~IFF_PROMISC; 873 re_stop(sc); 874 if (m0 != NULL) 875 m_freem(m0); 876 877 RL_UNLOCK(sc); 878 879 return (error); 880} 881 882#endif 883 884/* 885 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 886 * IDs against our list and return a device name if we find a match. 887 */ 888static int 889re_probe(device_t dev) 890{ 891 struct rl_type *t; 892 uint16_t devid, vendor; 893 uint16_t revid, sdevid; 894 int i; 895 896 vendor = pci_get_vendor(dev); 897 devid = pci_get_device(dev); 898 revid = pci_get_revid(dev); 899 sdevid = pci_get_subdevice(dev); 900 901 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 902 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 903 /* 904 * Only attach to rev. 3 of the Linksys EG1032 adapter. 905 * Rev. 2 is supported by sk(4). 906 */ 907 return (ENXIO); 908 } 909 } 910 911 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 912 if (revid != 0x20) { 913 /* 8139, let rl(4) take care of this device. */ 914 return (ENXIO); 915 } 916 } 917 918 t = re_devs; 919 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 920 if (vendor == t->rl_vid && devid == t->rl_did) { 921 device_set_desc(dev, t->rl_name); 922 return (BUS_PROBE_DEFAULT); 923 } 924 } 925 926 return (ENXIO); 927} 928 929/* 930 * Map a single buffer address. 931 */ 932 933static void 934re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 935{ 936 bus_addr_t *addr; 937 938 if (error) 939 return; 940 941 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 942 addr = arg; 943 *addr = segs->ds_addr; 944} 945 946static int 947re_allocmem(device_t dev, struct rl_softc *sc) 948{ 949 bus_addr_t lowaddr; 950 bus_size_t rx_list_size, tx_list_size; 951 int error; 952 int i; 953 954 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 955 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 956 957 /* 958 * Allocate the parent bus DMA tag appropriate for PCI. 959 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 960 * register should be set. However some RealTek chips are known 961 * to be buggy on DAC handling, therefore disable DAC by limiting 962 * DMA address space to 32bit. PCIe variants of RealTek chips 963 * may not have the limitation. 964 */ 965 lowaddr = BUS_SPACE_MAXADDR; 966 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 967 lowaddr = BUS_SPACE_MAXADDR_32BIT; 968 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 969 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 970 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 971 NULL, NULL, &sc->rl_parent_tag); 972 if (error) { 973 device_printf(dev, "could not allocate parent DMA tag\n"); 974 return (error); 975 } 976 977 /* 978 * Allocate map for TX mbufs. 979 */ 980 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 981 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 982 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 983 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 984 if (error) { 985 device_printf(dev, "could not allocate TX DMA tag\n"); 986 return (error); 987 } 988 989 /* 990 * Allocate map for RX mbufs. 991 */ 992 993 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 994 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 995 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 996 if (error) { 997 device_printf(dev, "could not allocate RX DMA tag\n"); 998 return (error); 999 } 1000 1001 /* 1002 * Allocate map for TX descriptor list. 1003 */ 1004 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1005 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1006 NULL, tx_list_size, 1, tx_list_size, 0, 1007 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1008 if (error) { 1009 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1010 return (error); 1011 } 1012 1013 /* Allocate DMA'able memory for the TX ring */ 1014 1015 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1016 (void **)&sc->rl_ldata.rl_tx_list, 1017 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1018 &sc->rl_ldata.rl_tx_list_map); 1019 if (error) { 1020 device_printf(dev, "could not allocate TX DMA ring\n"); 1021 return (error); 1022 } 1023 1024 /* Load the map for the TX ring. */ 1025 1026 sc->rl_ldata.rl_tx_list_addr = 0; 1027 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1028 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1029 tx_list_size, re_dma_map_addr, 1030 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1031 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1032 device_printf(dev, "could not load TX DMA ring\n"); 1033 return (ENOMEM); 1034 } 1035 1036 /* Create DMA maps for TX buffers */ 1037 1038 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1039 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1040 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1041 if (error) { 1042 device_printf(dev, "could not create DMA map for TX\n"); 1043 return (error); 1044 } 1045 } 1046 1047 /* 1048 * Allocate map for RX descriptor list. 1049 */ 1050 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1051 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1052 NULL, rx_list_size, 1, rx_list_size, 0, 1053 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1054 if (error) { 1055 device_printf(dev, "could not create RX DMA ring tag\n"); 1056 return (error); 1057 } 1058 1059 /* Allocate DMA'able memory for the RX ring */ 1060 1061 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1062 (void **)&sc->rl_ldata.rl_rx_list, 1063 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1064 &sc->rl_ldata.rl_rx_list_map); 1065 if (error) { 1066 device_printf(dev, "could not allocate RX DMA ring\n"); 1067 return (error); 1068 } 1069 1070 /* Load the map for the RX ring. */ 1071 1072 sc->rl_ldata.rl_rx_list_addr = 0; 1073 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1074 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1075 rx_list_size, re_dma_map_addr, 1076 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1077 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1078 device_printf(dev, "could not load RX DMA ring\n"); 1079 return (ENOMEM); 1080 } 1081 1082 /* Create DMA maps for RX buffers */ 1083 1084 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1085 &sc->rl_ldata.rl_rx_sparemap); 1086 if (error) { 1087 device_printf(dev, "could not create spare DMA map for RX\n"); 1088 return (error); 1089 } 1090 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1091 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1092 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1093 if (error) { 1094 device_printf(dev, "could not create DMA map for RX\n"); 1095 return (error); 1096 } 1097 } 1098 1099 /* Create DMA map for statistics. */ 1100 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1101 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1102 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1103 &sc->rl_ldata.rl_stag); 1104 if (error) { 1105 device_printf(dev, "could not create statistics DMA tag\n"); 1106 return (error); 1107 } 1108 /* Allocate DMA'able memory for statistics. */ 1109 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1110 (void **)&sc->rl_ldata.rl_stats, 1111 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1112 &sc->rl_ldata.rl_smap); 1113 if (error) { 1114 device_printf(dev, 1115 "could not allocate statistics DMA memory\n"); 1116 return (error); 1117 } 1118 /* Load the map for statistics. */ 1119 sc->rl_ldata.rl_stats_addr = 0; 1120 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1121 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1122 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1123 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1124 device_printf(dev, "could not load statistics DMA memory\n"); 1125 return (ENOMEM); 1126 } 1127 1128 return (0); 1129} 1130 1131/* 1132 * Attach the interface. Allocate softc structures, do ifmedia 1133 * setup and ethernet/BPF attach. 1134 */ 1135static int 1136re_attach(device_t dev) 1137{ 1138 u_char eaddr[ETHER_ADDR_LEN]; 1139 u_int16_t as[ETHER_ADDR_LEN / 2]; 1140 struct rl_softc *sc; 1141 struct ifnet *ifp; 1142 struct rl_hwrev *hw_rev; 1143 int hwrev; 1144 u_int16_t devid, re_did = 0; 1145 int error = 0, i, phy, rid; 1146 int msic, reg; 1147 uint8_t cfg; 1148 1149 sc = device_get_softc(dev); 1150 sc->rl_dev = dev; 1151 1152 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1153 MTX_DEF); 1154 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1155 1156 /* 1157 * Map control/status registers. 1158 */ 1159 pci_enable_busmaster(dev); 1160 1161 devid = pci_get_device(dev); 1162 /* 1163 * Prefer memory space register mapping over IO space. 1164 * Because RTL8169SC does not seem to work when memory mapping 1165 * is used always activate io mapping. 1166 */ 1167 if (devid == RT_DEVICEID_8169SC) 1168 prefer_iomap = 1; 1169 if (prefer_iomap == 0) { 1170 sc->rl_res_id = PCIR_BAR(1); 1171 sc->rl_res_type = SYS_RES_MEMORY; 1172 /* RTL8168/8101E seems to use different BARs. */ 1173 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1174 sc->rl_res_id = PCIR_BAR(2); 1175 } else { 1176 sc->rl_res_id = PCIR_BAR(0); 1177 sc->rl_res_type = SYS_RES_IOPORT; 1178 } 1179 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1180 &sc->rl_res_id, RF_ACTIVE); 1181 if (sc->rl_res == NULL && prefer_iomap == 0) { 1182 sc->rl_res_id = PCIR_BAR(0); 1183 sc->rl_res_type = SYS_RES_IOPORT; 1184 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1185 &sc->rl_res_id, RF_ACTIVE); 1186 } 1187 if (sc->rl_res == NULL) { 1188 device_printf(dev, "couldn't map ports/memory\n"); 1189 error = ENXIO; 1190 goto fail; 1191 } 1192 1193 sc->rl_btag = rman_get_bustag(sc->rl_res); 1194 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1195 1196 msic = 0; 1197 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1198 sc->rl_flags |= RL_FLAG_PCIE; 1199 if (devid != RT_DEVICEID_8101E) { 1200 /* Set PCIe maximum read request size to 2048. */ 1201 if (pci_get_max_read_req(dev) < 2048) 1202 pci_set_max_read_req(dev, 2048); 1203 } 1204 msic = pci_msi_count(dev); 1205 if (bootverbose) 1206 device_printf(dev, "MSI count : %d\n", msic); 1207 } 1208 if (msic > 0 && msi_disable == 0) { 1209 msic = 1; 1210 if (pci_alloc_msi(dev, &msic) == 0) { 1211 if (msic == RL_MSI_MESSAGES) { 1212 device_printf(dev, "Using %d MSI messages\n", 1213 msic); 1214 sc->rl_flags |= RL_FLAG_MSI; 1215 /* Explicitly set MSI enable bit. */ 1216 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1217 cfg = CSR_READ_1(sc, RL_CFG2); 1218 cfg |= RL_CFG2_MSI; 1219 CSR_WRITE_1(sc, RL_CFG2, cfg); 1220 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1221 } else 1222 pci_release_msi(dev); 1223 } 1224 } 1225 1226 /* Allocate interrupt */ 1227 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1228 rid = 0; 1229 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1230 RF_SHAREABLE | RF_ACTIVE); 1231 if (sc->rl_irq[0] == NULL) { 1232 device_printf(dev, "couldn't allocate IRQ resources\n"); 1233 error = ENXIO; 1234 goto fail; 1235 } 1236 } else { 1237 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1238 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1239 SYS_RES_IRQ, &rid, RF_ACTIVE); 1240 if (sc->rl_irq[i] == NULL) { 1241 device_printf(dev, 1242 "couldn't llocate IRQ resources for " 1243 "message %d\n", rid); 1244 error = ENXIO; 1245 goto fail; 1246 } 1247 } 1248 } 1249 1250 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1251 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1252 cfg = CSR_READ_1(sc, RL_CFG2); 1253 if ((cfg & RL_CFG2_MSI) != 0) { 1254 device_printf(dev, "turning off MSI enable bit.\n"); 1255 cfg &= ~RL_CFG2_MSI; 1256 CSR_WRITE_1(sc, RL_CFG2, cfg); 1257 } 1258 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1259 } 1260 1261 /* Reset the adapter. */ 1262 RL_LOCK(sc); 1263 re_reset(sc); 1264 RL_UNLOCK(sc); 1265 1266 hw_rev = re_hwrevs; 1267 hwrev = CSR_READ_4(sc, RL_TXCFG); 1268 switch (hwrev & 0x70000000) { 1269 case 0x00000000: 1270 case 0x10000000: 1271 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1272 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1273 break; 1274 default: 1275 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1276 hwrev &= RL_TXCFG_HWREV; 1277 break; 1278 } 1279 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1280 while (hw_rev->rl_desc != NULL) { 1281 if (hw_rev->rl_rev == hwrev) { 1282 sc->rl_type = hw_rev->rl_type; 1283 sc->rl_hwrev = hw_rev->rl_rev; 1284 break; 1285 } 1286 hw_rev++; 1287 } 1288 if (hw_rev->rl_desc == NULL) { 1289 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1290 error = ENXIO; 1291 goto fail; 1292 } 1293 1294 switch (hw_rev->rl_rev) { 1295 case RL_HWREV_8139CPLUS: 1296 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER | 1297 RL_FLAG_AUTOPAD; 1298 break; 1299 case RL_HWREV_8100E: 1300 case RL_HWREV_8101E: 1301 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1302 RL_FLAG_FASTETHER; 1303 break; 1304 case RL_HWREV_8102E: 1305 case RL_HWREV_8102EL: 1306 case RL_HWREV_8102EL_SPIN1: 1307 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1308 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1309 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1310 break; 1311 case RL_HWREV_8103E: 1312 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1313 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1314 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1315 RL_FLAG_MACSLEEP; 1316 break; 1317 case RL_HWREV_8168_SPIN1: 1318 case RL_HWREV_8168_SPIN2: 1319 sc->rl_flags |= RL_FLAG_WOLRXENB; 1320 /* FALLTHROUGH */ 1321 case RL_HWREV_8168_SPIN3: 1322 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1323 break; 1324 case RL_HWREV_8168C_SPIN2: 1325 sc->rl_flags |= RL_FLAG_MACSLEEP; 1326 /* FALLTHROUGH */ 1327 case RL_HWREV_8168C: 1328 if ((hwrev & 0x00700000) == 0x00200000) 1329 sc->rl_flags |= RL_FLAG_MACSLEEP; 1330 /* FALLTHROUGH */ 1331 case RL_HWREV_8168CP: 1332 case RL_HWREV_8168D: 1333 case RL_HWREV_8168DP: 1334 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1335 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1336 RL_FLAG_AUTOPAD; 1337 /* 1338 * These controllers support jumbo frame but it seems 1339 * that enabling it requires touching additional magic 1340 * registers. Depending on MAC revisions some 1341 * controllers need to disable checksum offload. So 1342 * disable jumbo frame until I have better idea what 1343 * it really requires to make it support. 1344 * RTL8168C/CP : supports up to 6KB jumbo frame. 1345 * RTL8111C/CP : supports up to 9KB jumbo frame. 1346 */ 1347 sc->rl_flags |= RL_FLAG_NOJUMBO; 1348 break; 1349 case RL_HWREV_8168E: 1350 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1351 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1352 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_NOJUMBO; 1353 break; 1354 case RL_HWREV_8169_8110SB: 1355 case RL_HWREV_8169_8110SBL: 1356 case RL_HWREV_8169_8110SC: 1357 case RL_HWREV_8169_8110SCE: 1358 sc->rl_flags |= RL_FLAG_PHYWAKE; 1359 /* FALLTHROUGH */ 1360 case RL_HWREV_8169: 1361 case RL_HWREV_8169S: 1362 case RL_HWREV_8110S: 1363 sc->rl_flags |= RL_FLAG_MACRESET; 1364 break; 1365 default: 1366 break; 1367 } 1368 1369 /* Enable PME. */ 1370 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1371 cfg = CSR_READ_1(sc, RL_CFG1); 1372 cfg |= RL_CFG1_PME; 1373 CSR_WRITE_1(sc, RL_CFG1, cfg); 1374 cfg = CSR_READ_1(sc, RL_CFG5); 1375 cfg &= RL_CFG5_PME_STS; 1376 CSR_WRITE_1(sc, RL_CFG5, cfg); 1377 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1378 1379 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1380 /* 1381 * XXX Should have a better way to extract station 1382 * address from EEPROM. 1383 */ 1384 for (i = 0; i < ETHER_ADDR_LEN; i++) 1385 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1386 } else { 1387 sc->rl_eewidth = RL_9356_ADDR_LEN; 1388 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1389 if (re_did != 0x8129) 1390 sc->rl_eewidth = RL_9346_ADDR_LEN; 1391 1392 /* 1393 * Get station address from the EEPROM. 1394 */ 1395 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1396 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1397 as[i] = le16toh(as[i]); 1398 bcopy(as, eaddr, sizeof(eaddr)); 1399 } 1400 1401 if (sc->rl_type == RL_8169) { 1402 /* Set RX length mask and number of descriptors. */ 1403 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1404 sc->rl_txstart = RL_GTXSTART; 1405 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1406 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1407 } else { 1408 /* Set RX length mask and number of descriptors. */ 1409 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1410 sc->rl_txstart = RL_TXSTART; 1411 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1412 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1413 } 1414 1415 error = re_allocmem(dev, sc); 1416 if (error) 1417 goto fail; 1418 re_add_sysctls(sc); 1419 1420 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1421 if (ifp == NULL) { 1422 device_printf(dev, "can not if_alloc()\n"); 1423 error = ENOSPC; 1424 goto fail; 1425 } 1426 1427 /* Take controller out of deep sleep mode. */ 1428 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1429 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1430 CSR_WRITE_1(sc, RL_GPIO, 1431 CSR_READ_1(sc, RL_GPIO) | 0x01); 1432 else 1433 CSR_WRITE_1(sc, RL_GPIO, 1434 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1435 } 1436 1437 /* Take PHY out of power down mode. */ 1438 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 1439 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1440 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1441 re_gmii_writereg(dev, 1, 0x1f, 0); 1442 re_gmii_writereg(dev, 1, 0x0e, 0); 1443 } 1444 1445#define RE_PHYAD_INTERNAL 0 1446 1447 /* Do MII setup. */ 1448 phy = RE_PHYAD_INTERNAL; 1449 if (sc->rl_type == RL_8169) 1450 phy = 1; 1451 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1452 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1453 if (error != 0) { 1454 device_printf(dev, "attaching PHYs failed\n"); 1455 goto fail; 1456 } 1457 1458 ifp->if_softc = sc; 1459 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1460 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1461 ifp->if_ioctl = re_ioctl; 1462 ifp->if_start = re_start; 1463 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1464 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1465 ifp->if_capenable = ifp->if_capabilities; 1466 ifp->if_init = re_init; 1467 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1468 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1469 IFQ_SET_READY(&ifp->if_snd); 1470 1471 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1472 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1473 1474 /* 1475 * Call MI attach routine. 1476 */ 1477 ether_ifattach(ifp, eaddr); 1478 1479 /* VLAN capability setup */ 1480 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1481 if (ifp->if_capabilities & IFCAP_HWCSUM) 1482 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1483 /* Enable WOL if PM is supported. */ 1484 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1485 ifp->if_capabilities |= IFCAP_WOL; 1486 ifp->if_capenable = ifp->if_capabilities; 1487 /* 1488 * Don't enable TSO by default for old controllers. Under 1489 * certain circumtances the controller generated corrupted 1490 * packets in TSO size. 1491 */ 1492 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1493 ifp->if_hwassist &= ~CSUM_TSO; 1494 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1495 } 1496#ifdef DEVICE_POLLING 1497 ifp->if_capabilities |= IFCAP_POLLING; 1498#endif 1499 /* 1500 * Tell the upper layer(s) we support long frames. 1501 * Must appear after the call to ether_ifattach() because 1502 * ether_ifattach() sets ifi_hdrlen to the default value. 1503 */ 1504 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1505 1506#ifdef RE_DIAG 1507 /* 1508 * Perform hardware diagnostic on the original RTL8169. 1509 * Some 32-bit cards were incorrectly wired and would 1510 * malfunction if plugged into a 64-bit slot. 1511 */ 1512 1513 if (hwrev == RL_HWREV_8169) { 1514 error = re_diag(sc); 1515 if (error) { 1516 device_printf(dev, 1517 "attach aborted due to hardware diag failure\n"); 1518 ether_ifdetach(ifp); 1519 goto fail; 1520 } 1521 } 1522#endif 1523 1524 /* Hook interrupt last to avoid having to lock softc */ 1525 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1526 error = bus_setup_intr(dev, sc->rl_irq[0], 1527 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1528 &sc->rl_intrhand[0]); 1529 else { 1530 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1531 error = bus_setup_intr(dev, sc->rl_irq[i], 1532 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1533 &sc->rl_intrhand[i]); 1534 if (error != 0) 1535 break; 1536 } 1537 } 1538 if (error) { 1539 device_printf(dev, "couldn't set up irq\n"); 1540 ether_ifdetach(ifp); 1541 } 1542 1543fail: 1544 1545 if (error) 1546 re_detach(dev); 1547 1548 return (error); 1549} 1550 1551/* 1552 * Shutdown hardware and free up resources. This can be called any 1553 * time after the mutex has been initialized. It is called in both 1554 * the error case in attach and the normal detach case so it needs 1555 * to be careful about only freeing resources that have actually been 1556 * allocated. 1557 */ 1558static int 1559re_detach(device_t dev) 1560{ 1561 struct rl_softc *sc; 1562 struct ifnet *ifp; 1563 int i, rid; 1564 1565 sc = device_get_softc(dev); 1566 ifp = sc->rl_ifp; 1567 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1568 1569 /* These should only be active if attach succeeded */ 1570 if (device_is_attached(dev)) { 1571#ifdef DEVICE_POLLING 1572 if (ifp->if_capenable & IFCAP_POLLING) 1573 ether_poll_deregister(ifp); 1574#endif 1575 RL_LOCK(sc); 1576#if 0 1577 sc->suspended = 1; 1578#endif 1579 re_stop(sc); 1580 RL_UNLOCK(sc); 1581 callout_drain(&sc->rl_stat_callout); 1582 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1583 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1584 /* 1585 * Force off the IFF_UP flag here, in case someone 1586 * still had a BPF descriptor attached to this 1587 * interface. If they do, ether_ifdetach() will cause 1588 * the BPF code to try and clear the promisc mode 1589 * flag, which will bubble down to re_ioctl(), 1590 * which will try to call re_init() again. This will 1591 * turn the NIC back on and restart the MII ticker, 1592 * which will panic the system when the kernel tries 1593 * to invoke the re_tick() function that isn't there 1594 * anymore. 1595 */ 1596 ifp->if_flags &= ~IFF_UP; 1597 ether_ifdetach(ifp); 1598 } 1599 if (sc->rl_miibus) 1600 device_delete_child(dev, sc->rl_miibus); 1601 bus_generic_detach(dev); 1602 1603 /* 1604 * The rest is resource deallocation, so we should already be 1605 * stopped here. 1606 */ 1607 1608 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1609 if (sc->rl_intrhand[i] != NULL) { 1610 bus_teardown_intr(dev, sc->rl_irq[i], 1611 sc->rl_intrhand[i]); 1612 sc->rl_intrhand[i] = NULL; 1613 } 1614 } 1615 if (ifp != NULL) 1616 if_free(ifp); 1617 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1618 if (sc->rl_irq[0] != NULL) { 1619 bus_release_resource(dev, SYS_RES_IRQ, 0, 1620 sc->rl_irq[0]); 1621 sc->rl_irq[0] = NULL; 1622 } 1623 } else { 1624 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1625 if (sc->rl_irq[i] != NULL) { 1626 bus_release_resource(dev, SYS_RES_IRQ, rid, 1627 sc->rl_irq[i]); 1628 sc->rl_irq[i] = NULL; 1629 } 1630 } 1631 pci_release_msi(dev); 1632 } 1633 if (sc->rl_res) 1634 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1635 sc->rl_res); 1636 1637 /* Unload and free the RX DMA ring memory and map */ 1638 1639 if (sc->rl_ldata.rl_rx_list_tag) { 1640 if (sc->rl_ldata.rl_rx_list_map) 1641 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1642 sc->rl_ldata.rl_rx_list_map); 1643 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1644 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1645 sc->rl_ldata.rl_rx_list, 1646 sc->rl_ldata.rl_rx_list_map); 1647 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1648 } 1649 1650 /* Unload and free the TX DMA ring memory and map */ 1651 1652 if (sc->rl_ldata.rl_tx_list_tag) { 1653 if (sc->rl_ldata.rl_tx_list_map) 1654 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1655 sc->rl_ldata.rl_tx_list_map); 1656 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1657 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1658 sc->rl_ldata.rl_tx_list, 1659 sc->rl_ldata.rl_tx_list_map); 1660 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1661 } 1662 1663 /* Destroy all the RX and TX buffer maps */ 1664 1665 if (sc->rl_ldata.rl_tx_mtag) { 1666 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1667 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1668 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1669 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1670 } 1671 if (sc->rl_ldata.rl_rx_mtag) { 1672 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1673 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1674 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1675 if (sc->rl_ldata.rl_rx_sparemap) 1676 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1677 sc->rl_ldata.rl_rx_sparemap); 1678 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1679 } 1680 1681 /* Unload and free the stats buffer and map */ 1682 1683 if (sc->rl_ldata.rl_stag) { 1684 if (sc->rl_ldata.rl_smap) 1685 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1686 sc->rl_ldata.rl_smap); 1687 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1688 bus_dmamem_free(sc->rl_ldata.rl_stag, 1689 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1690 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1691 } 1692 1693 if (sc->rl_parent_tag) 1694 bus_dma_tag_destroy(sc->rl_parent_tag); 1695 1696 mtx_destroy(&sc->rl_mtx); 1697 1698 return (0); 1699} 1700 1701static __inline void 1702re_discard_rxbuf(struct rl_softc *sc, int idx) 1703{ 1704 struct rl_desc *desc; 1705 struct rl_rxdesc *rxd; 1706 uint32_t cmdstat; 1707 1708 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1709 desc = &sc->rl_ldata.rl_rx_list[idx]; 1710 desc->rl_vlanctl = 0; 1711 cmdstat = rxd->rx_size; 1712 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1713 cmdstat |= RL_RDESC_CMD_EOR; 1714 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1715} 1716 1717static int 1718re_newbuf(struct rl_softc *sc, int idx) 1719{ 1720 struct mbuf *m; 1721 struct rl_rxdesc *rxd; 1722 bus_dma_segment_t segs[1]; 1723 bus_dmamap_t map; 1724 struct rl_desc *desc; 1725 uint32_t cmdstat; 1726 int error, nsegs; 1727 1728 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1729 if (m == NULL) 1730 return (ENOBUFS); 1731 1732 m->m_len = m->m_pkthdr.len = MCLBYTES; 1733#ifdef RE_FIXUP_RX 1734 /* 1735 * This is part of an evil trick to deal with non-x86 platforms. 1736 * The RealTek chip requires RX buffers to be aligned on 64-bit 1737 * boundaries, but that will hose non-x86 machines. To get around 1738 * this, we leave some empty space at the start of each buffer 1739 * and for non-x86 hosts, we copy the buffer back six bytes 1740 * to achieve word alignment. This is slightly more efficient 1741 * than allocating a new buffer, copying the contents, and 1742 * discarding the old buffer. 1743 */ 1744 m_adj(m, RE_ETHER_ALIGN); 1745#endif 1746 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1747 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1748 if (error != 0) { 1749 m_freem(m); 1750 return (ENOBUFS); 1751 } 1752 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1753 1754 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1755 if (rxd->rx_m != NULL) { 1756 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1757 BUS_DMASYNC_POSTREAD); 1758 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1759 } 1760 1761 rxd->rx_m = m; 1762 map = rxd->rx_dmamap; 1763 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1764 rxd->rx_size = segs[0].ds_len; 1765 sc->rl_ldata.rl_rx_sparemap = map; 1766 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1767 BUS_DMASYNC_PREREAD); 1768 1769 desc = &sc->rl_ldata.rl_rx_list[idx]; 1770 desc->rl_vlanctl = 0; 1771 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1772 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1773 cmdstat = segs[0].ds_len; 1774 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1775 cmdstat |= RL_RDESC_CMD_EOR; 1776 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1777 1778 return (0); 1779} 1780 1781#ifdef RE_FIXUP_RX 1782static __inline void 1783re_fixup_rx(struct mbuf *m) 1784{ 1785 int i; 1786 uint16_t *src, *dst; 1787 1788 src = mtod(m, uint16_t *); 1789 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1790 1791 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1792 *dst++ = *src++; 1793 1794 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1795} 1796#endif 1797 1798static int 1799re_tx_list_init(struct rl_softc *sc) 1800{ 1801 struct rl_desc *desc; 1802 int i; 1803 1804 RL_LOCK_ASSERT(sc); 1805 1806 bzero(sc->rl_ldata.rl_tx_list, 1807 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1808 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1809 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1810 /* Set EOR. */ 1811 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1812 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1813 1814 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1815 sc->rl_ldata.rl_tx_list_map, 1816 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1817 1818 sc->rl_ldata.rl_tx_prodidx = 0; 1819 sc->rl_ldata.rl_tx_considx = 0; 1820 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1821 1822 return (0); 1823} 1824 1825static int 1826re_rx_list_init(struct rl_softc *sc) 1827{ 1828 int error, i; 1829 1830 bzero(sc->rl_ldata.rl_rx_list, 1831 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1832 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1833 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1834 if ((error = re_newbuf(sc, i)) != 0) 1835 return (error); 1836 } 1837 1838 /* Flush the RX descriptors */ 1839 1840 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1841 sc->rl_ldata.rl_rx_list_map, 1842 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1843 1844 sc->rl_ldata.rl_rx_prodidx = 0; 1845 sc->rl_head = sc->rl_tail = NULL; 1846 1847 return (0); 1848} 1849 1850/* 1851 * RX handler for C+ and 8169. For the gigE chips, we support 1852 * the reception of jumbo frames that have been fragmented 1853 * across multiple 2K mbuf cluster buffers. 1854 */ 1855static int 1856re_rxeof(struct rl_softc *sc, int *rx_npktsp) 1857{ 1858 struct mbuf *m; 1859 struct ifnet *ifp; 1860 int i, total_len; 1861 struct rl_desc *cur_rx; 1862 u_int32_t rxstat, rxvlan; 1863 int maxpkt = 16, rx_npkts = 0; 1864 1865 RL_LOCK_ASSERT(sc); 1866 1867 ifp = sc->rl_ifp; 1868 1869 /* Invalidate the descriptor memory */ 1870 1871 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1872 sc->rl_ldata.rl_rx_list_map, 1873 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1874 1875 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1876 i = RL_RX_DESC_NXT(sc, i)) { 1877 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1878 break; 1879 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1880 rxstat = le32toh(cur_rx->rl_cmdstat); 1881 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1882 break; 1883 total_len = rxstat & sc->rl_rxlenmask; 1884 rxvlan = le32toh(cur_rx->rl_vlanctl); 1885 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1886 1887 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1888 if (re_newbuf(sc, i) != 0) { 1889 /* 1890 * If this is part of a multi-fragment packet, 1891 * discard all the pieces. 1892 */ 1893 if (sc->rl_head != NULL) { 1894 m_freem(sc->rl_head); 1895 sc->rl_head = sc->rl_tail = NULL; 1896 } 1897 re_discard_rxbuf(sc, i); 1898 continue; 1899 } 1900 m->m_len = RE_RX_DESC_BUFLEN; 1901 if (sc->rl_head == NULL) 1902 sc->rl_head = sc->rl_tail = m; 1903 else { 1904 m->m_flags &= ~M_PKTHDR; 1905 sc->rl_tail->m_next = m; 1906 sc->rl_tail = m; 1907 } 1908 continue; 1909 } 1910 1911 /* 1912 * NOTE: for the 8139C+, the frame length field 1913 * is always 12 bits in size, but for the gigE chips, 1914 * it is 13 bits (since the max RX frame length is 16K). 1915 * Unfortunately, all 32 bits in the status word 1916 * were already used, so to make room for the extra 1917 * length bit, RealTek took out the 'frame alignment 1918 * error' bit and shifted the other status bits 1919 * over one slot. The OWN, EOR, FS and LS bits are 1920 * still in the same places. We have already extracted 1921 * the frame length and checked the OWN bit, so rather 1922 * than using an alternate bit mapping, we shift the 1923 * status bits one space to the right so we can evaluate 1924 * them using the 8169 status as though it was in the 1925 * same format as that of the 8139C+. 1926 */ 1927 if (sc->rl_type == RL_8169) 1928 rxstat >>= 1; 1929 1930 /* 1931 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1932 * set, but if CRC is clear, it will still be a valid frame. 1933 */ 1934 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1935 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1936 ifp->if_ierrors++; 1937 /* 1938 * If this is part of a multi-fragment packet, 1939 * discard all the pieces. 1940 */ 1941 if (sc->rl_head != NULL) { 1942 m_freem(sc->rl_head); 1943 sc->rl_head = sc->rl_tail = NULL; 1944 } 1945 re_discard_rxbuf(sc, i); 1946 continue; 1947 } 1948 1949 /* 1950 * If allocating a replacement mbuf fails, 1951 * reload the current one. 1952 */ 1953 1954 if (re_newbuf(sc, i) != 0) { 1955 ifp->if_iqdrops++; 1956 if (sc->rl_head != NULL) { 1957 m_freem(sc->rl_head); 1958 sc->rl_head = sc->rl_tail = NULL; 1959 } 1960 re_discard_rxbuf(sc, i); 1961 continue; 1962 } 1963 1964 if (sc->rl_head != NULL) { 1965 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1966 if (m->m_len == 0) 1967 m->m_len = RE_RX_DESC_BUFLEN; 1968 /* 1969 * Special case: if there's 4 bytes or less 1970 * in this buffer, the mbuf can be discarded: 1971 * the last 4 bytes is the CRC, which we don't 1972 * care about anyway. 1973 */ 1974 if (m->m_len <= ETHER_CRC_LEN) { 1975 sc->rl_tail->m_len -= 1976 (ETHER_CRC_LEN - m->m_len); 1977 m_freem(m); 1978 } else { 1979 m->m_len -= ETHER_CRC_LEN; 1980 m->m_flags &= ~M_PKTHDR; 1981 sc->rl_tail->m_next = m; 1982 } 1983 m = sc->rl_head; 1984 sc->rl_head = sc->rl_tail = NULL; 1985 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1986 } else 1987 m->m_pkthdr.len = m->m_len = 1988 (total_len - ETHER_CRC_LEN); 1989 1990#ifdef RE_FIXUP_RX 1991 re_fixup_rx(m); 1992#endif 1993 ifp->if_ipackets++; 1994 m->m_pkthdr.rcvif = ifp; 1995 1996 /* Do RX checksumming if enabled */ 1997 1998 if (ifp->if_capenable & IFCAP_RXCSUM) { 1999 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2000 /* Check IP header checksum */ 2001 if (rxstat & RL_RDESC_STAT_PROTOID) 2002 m->m_pkthdr.csum_flags |= 2003 CSUM_IP_CHECKED; 2004 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2005 m->m_pkthdr.csum_flags |= 2006 CSUM_IP_VALID; 2007 2008 /* Check TCP/UDP checksum */ 2009 if ((RL_TCPPKT(rxstat) && 2010 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2011 (RL_UDPPKT(rxstat) && 2012 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2013 m->m_pkthdr.csum_flags |= 2014 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2015 m->m_pkthdr.csum_data = 0xffff; 2016 } 2017 } else { 2018 /* 2019 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2020 */ 2021 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2022 (rxvlan & RL_RDESC_IPV4)) 2023 m->m_pkthdr.csum_flags |= 2024 CSUM_IP_CHECKED; 2025 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2026 (rxvlan & RL_RDESC_IPV4)) 2027 m->m_pkthdr.csum_flags |= 2028 CSUM_IP_VALID; 2029 if (((rxstat & RL_RDESC_STAT_TCP) && 2030 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2031 ((rxstat & RL_RDESC_STAT_UDP) && 2032 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2033 m->m_pkthdr.csum_flags |= 2034 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2035 m->m_pkthdr.csum_data = 0xffff; 2036 } 2037 } 2038 } 2039 maxpkt--; 2040 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2041 m->m_pkthdr.ether_vtag = 2042 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2043 m->m_flags |= M_VLANTAG; 2044 } 2045 RL_UNLOCK(sc); 2046 (*ifp->if_input)(ifp, m); 2047 RL_LOCK(sc); 2048 rx_npkts++; 2049 } 2050 2051 /* Flush the RX DMA ring */ 2052 2053 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2054 sc->rl_ldata.rl_rx_list_map, 2055 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2056 2057 sc->rl_ldata.rl_rx_prodidx = i; 2058 2059 if (rx_npktsp != NULL) 2060 *rx_npktsp = rx_npkts; 2061 if (maxpkt) 2062 return (EAGAIN); 2063 2064 return (0); 2065} 2066 2067static void 2068re_txeof(struct rl_softc *sc) 2069{ 2070 struct ifnet *ifp; 2071 struct rl_txdesc *txd; 2072 u_int32_t txstat; 2073 int cons; 2074 2075 cons = sc->rl_ldata.rl_tx_considx; 2076 if (cons == sc->rl_ldata.rl_tx_prodidx) 2077 return; 2078 2079 ifp = sc->rl_ifp; 2080 /* Invalidate the TX descriptor list */ 2081 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2082 sc->rl_ldata.rl_tx_list_map, 2083 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2084 2085 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2086 cons = RL_TX_DESC_NXT(sc, cons)) { 2087 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2088 if (txstat & RL_TDESC_STAT_OWN) 2089 break; 2090 /* 2091 * We only stash mbufs in the last descriptor 2092 * in a fragment chain, which also happens to 2093 * be the only place where the TX status bits 2094 * are valid. 2095 */ 2096 if (txstat & RL_TDESC_CMD_EOF) { 2097 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2098 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2099 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2100 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2101 txd->tx_dmamap); 2102 KASSERT(txd->tx_m != NULL, 2103 ("%s: freeing NULL mbufs!", __func__)); 2104 m_freem(txd->tx_m); 2105 txd->tx_m = NULL; 2106 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2107 RL_TDESC_STAT_COLCNT)) 2108 ifp->if_collisions++; 2109 if (txstat & RL_TDESC_STAT_TXERRSUM) 2110 ifp->if_oerrors++; 2111 else 2112 ifp->if_opackets++; 2113 } 2114 sc->rl_ldata.rl_tx_free++; 2115 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2116 } 2117 sc->rl_ldata.rl_tx_considx = cons; 2118 2119 /* No changes made to the TX ring, so no flush needed */ 2120 2121 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2122#ifdef RE_TX_MODERATION 2123 /* 2124 * If not all descriptors have been reaped yet, reload 2125 * the timer so that we will eventually get another 2126 * interrupt that will cause us to re-enter this routine. 2127 * This is done in case the transmitter has gone idle. 2128 */ 2129 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2130#endif 2131 } else 2132 sc->rl_watchdog_timer = 0; 2133} 2134 2135static void 2136re_tick(void *xsc) 2137{ 2138 struct rl_softc *sc; 2139 struct mii_data *mii; 2140 2141 sc = xsc; 2142 2143 RL_LOCK_ASSERT(sc); 2144 2145 mii = device_get_softc(sc->rl_miibus); 2146 mii_tick(mii); 2147 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2148 re_miibus_statchg(sc->rl_dev); 2149 /* 2150 * Reclaim transmitted frames here. Technically it is not 2151 * necessary to do here but it ensures periodic reclamation 2152 * regardless of Tx completion interrupt which seems to be 2153 * lost on PCIe based controllers under certain situations. 2154 */ 2155 re_txeof(sc); 2156 re_watchdog(sc); 2157 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2158} 2159 2160#ifdef DEVICE_POLLING 2161static int 2162re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2163{ 2164 struct rl_softc *sc = ifp->if_softc; 2165 int rx_npkts = 0; 2166 2167 RL_LOCK(sc); 2168 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2169 rx_npkts = re_poll_locked(ifp, cmd, count); 2170 RL_UNLOCK(sc); 2171 return (rx_npkts); 2172} 2173 2174static int 2175re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2176{ 2177 struct rl_softc *sc = ifp->if_softc; 2178 int rx_npkts; 2179 2180 RL_LOCK_ASSERT(sc); 2181 2182 sc->rxcycles = count; 2183 re_rxeof(sc, &rx_npkts); 2184 re_txeof(sc); 2185 2186 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2187 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2188 2189 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2190 u_int16_t status; 2191 2192 status = CSR_READ_2(sc, RL_ISR); 2193 if (status == 0xffff) 2194 return (rx_npkts); 2195 if (status) 2196 CSR_WRITE_2(sc, RL_ISR, status); 2197 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2198 (sc->rl_flags & RL_FLAG_PCIE)) 2199 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2200 2201 /* 2202 * XXX check behaviour on receiver stalls. 2203 */ 2204 2205 if (status & RL_ISR_SYSTEM_ERR) { 2206 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2207 re_init_locked(sc); 2208 } 2209 } 2210 return (rx_npkts); 2211} 2212#endif /* DEVICE_POLLING */ 2213 2214static int 2215re_intr(void *arg) 2216{ 2217 struct rl_softc *sc; 2218 uint16_t status; 2219 2220 sc = arg; 2221 2222 status = CSR_READ_2(sc, RL_ISR); 2223 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2224 return (FILTER_STRAY); 2225 CSR_WRITE_2(sc, RL_IMR, 0); 2226 2227 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2228 2229 return (FILTER_HANDLED); 2230} 2231 2232static void 2233re_int_task(void *arg, int npending) 2234{ 2235 struct rl_softc *sc; 2236 struct ifnet *ifp; 2237 u_int16_t status; 2238 int rval = 0; 2239 2240 sc = arg; 2241 ifp = sc->rl_ifp; 2242 2243 RL_LOCK(sc); 2244 2245 status = CSR_READ_2(sc, RL_ISR); 2246 CSR_WRITE_2(sc, RL_ISR, status); 2247 2248 if (sc->suspended || 2249 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2250 RL_UNLOCK(sc); 2251 return; 2252 } 2253 2254#ifdef DEVICE_POLLING 2255 if (ifp->if_capenable & IFCAP_POLLING) { 2256 RL_UNLOCK(sc); 2257 return; 2258 } 2259#endif 2260 2261 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2262 rval = re_rxeof(sc, NULL); 2263 2264 /* 2265 * Some chips will ignore a second TX request issued 2266 * while an existing transmission is in progress. If 2267 * the transmitter goes idle but there are still 2268 * packets waiting to be sent, we need to restart the 2269 * channel here to flush them out. This only seems to 2270 * be required with the PCIe devices. 2271 */ 2272 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2273 (sc->rl_flags & RL_FLAG_PCIE)) 2274 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2275 if (status & ( 2276#ifdef RE_TX_MODERATION 2277 RL_ISR_TIMEOUT_EXPIRED| 2278#else 2279 RL_ISR_TX_OK| 2280#endif 2281 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2282 re_txeof(sc); 2283 2284 if (status & RL_ISR_SYSTEM_ERR) { 2285 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2286 re_init_locked(sc); 2287 } 2288 2289 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2290 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2291 2292 RL_UNLOCK(sc); 2293 2294 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2295 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2296 return; 2297 } 2298 2299 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2300} 2301 2302static int 2303re_encap(struct rl_softc *sc, struct mbuf **m_head) 2304{ 2305 struct rl_txdesc *txd, *txd_last; 2306 bus_dma_segment_t segs[RL_NTXSEGS]; 2307 bus_dmamap_t map; 2308 struct mbuf *m_new; 2309 struct rl_desc *desc; 2310 int nsegs, prod; 2311 int i, error, ei, si; 2312 int padlen; 2313 uint32_t cmdstat, csum_flags, vlanctl; 2314 2315 RL_LOCK_ASSERT(sc); 2316 M_ASSERTPKTHDR((*m_head)); 2317 2318 /* 2319 * With some of the RealTek chips, using the checksum offload 2320 * support in conjunction with the autopadding feature results 2321 * in the transmission of corrupt frames. For example, if we 2322 * need to send a really small IP fragment that's less than 60 2323 * bytes in size, and IP header checksumming is enabled, the 2324 * resulting ethernet frame that appears on the wire will 2325 * have garbled payload. To work around this, if TX IP checksum 2326 * offload is enabled, we always manually pad short frames out 2327 * to the minimum ethernet frame size. 2328 */ 2329 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2330 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2331 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2332 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2333 if (M_WRITABLE(*m_head) == 0) { 2334 /* Get a writable copy. */ 2335 m_new = m_dup(*m_head, M_DONTWAIT); 2336 m_freem(*m_head); 2337 if (m_new == NULL) { 2338 *m_head = NULL; 2339 return (ENOBUFS); 2340 } 2341 *m_head = m_new; 2342 } 2343 if ((*m_head)->m_next != NULL || 2344 M_TRAILINGSPACE(*m_head) < padlen) { 2345 m_new = m_defrag(*m_head, M_DONTWAIT); 2346 if (m_new == NULL) { 2347 m_freem(*m_head); 2348 *m_head = NULL; 2349 return (ENOBUFS); 2350 } 2351 } else 2352 m_new = *m_head; 2353 2354 /* 2355 * Manually pad short frames, and zero the pad space 2356 * to avoid leaking data. 2357 */ 2358 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2359 m_new->m_pkthdr.len += padlen; 2360 m_new->m_len = m_new->m_pkthdr.len; 2361 *m_head = m_new; 2362 } 2363 2364 prod = sc->rl_ldata.rl_tx_prodidx; 2365 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2366 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2367 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2368 if (error == EFBIG) { 2369 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2370 if (m_new == NULL) { 2371 m_freem(*m_head); 2372 *m_head = NULL; 2373 return (ENOBUFS); 2374 } 2375 *m_head = m_new; 2376 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2377 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2378 if (error != 0) { 2379 m_freem(*m_head); 2380 *m_head = NULL; 2381 return (error); 2382 } 2383 } else if (error != 0) 2384 return (error); 2385 if (nsegs == 0) { 2386 m_freem(*m_head); 2387 *m_head = NULL; 2388 return (EIO); 2389 } 2390 2391 /* Check for number of available descriptors. */ 2392 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2393 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2394 return (ENOBUFS); 2395 } 2396 2397 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2398 BUS_DMASYNC_PREWRITE); 2399 2400 /* 2401 * Set up checksum offload. Note: checksum offload bits must 2402 * appear in all descriptors of a multi-descriptor transmit 2403 * attempt. This is according to testing done with an 8169 2404 * chip. This is a requirement. 2405 */ 2406 vlanctl = 0; 2407 csum_flags = 0; 2408 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2409 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2410 csum_flags |= RL_TDESC_CMD_LGSEND; 2411 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2412 RL_TDESC_CMD_MSSVALV2_SHIFT); 2413 } else { 2414 csum_flags |= RL_TDESC_CMD_LGSEND | 2415 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2416 RL_TDESC_CMD_MSSVAL_SHIFT); 2417 } 2418 } else { 2419 /* 2420 * Unconditionally enable IP checksum if TCP or UDP 2421 * checksum is required. Otherwise, TCP/UDP checksum 2422 * does't make effects. 2423 */ 2424 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2425 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2426 csum_flags |= RL_TDESC_CMD_IPCSUM; 2427 if (((*m_head)->m_pkthdr.csum_flags & 2428 CSUM_TCP) != 0) 2429 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2430 if (((*m_head)->m_pkthdr.csum_flags & 2431 CSUM_UDP) != 0) 2432 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2433 } else { 2434 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2435 if (((*m_head)->m_pkthdr.csum_flags & 2436 CSUM_TCP) != 0) 2437 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2438 if (((*m_head)->m_pkthdr.csum_flags & 2439 CSUM_UDP) != 0) 2440 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2441 } 2442 } 2443 } 2444 2445 /* 2446 * Set up hardware VLAN tagging. Note: vlan tag info must 2447 * appear in all descriptors of a multi-descriptor 2448 * transmission attempt. 2449 */ 2450 if ((*m_head)->m_flags & M_VLANTAG) 2451 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2452 RL_TDESC_VLANCTL_TAG; 2453 2454 si = prod; 2455 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2456 desc = &sc->rl_ldata.rl_tx_list[prod]; 2457 desc->rl_vlanctl = htole32(vlanctl); 2458 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2459 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2460 cmdstat = segs[i].ds_len; 2461 if (i != 0) 2462 cmdstat |= RL_TDESC_CMD_OWN; 2463 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2464 cmdstat |= RL_TDESC_CMD_EOR; 2465 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2466 sc->rl_ldata.rl_tx_free--; 2467 } 2468 /* Update producer index. */ 2469 sc->rl_ldata.rl_tx_prodidx = prod; 2470 2471 /* Set EOF on the last descriptor. */ 2472 ei = RL_TX_DESC_PRV(sc, prod); 2473 desc = &sc->rl_ldata.rl_tx_list[ei]; 2474 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2475 2476 desc = &sc->rl_ldata.rl_tx_list[si]; 2477 /* Set SOF and transfer ownership of packet to the chip. */ 2478 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2479 2480 /* 2481 * Insure that the map for this transmission 2482 * is placed at the array index of the last descriptor 2483 * in this chain. (Swap last and first dmamaps.) 2484 */ 2485 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2486 map = txd->tx_dmamap; 2487 txd->tx_dmamap = txd_last->tx_dmamap; 2488 txd_last->tx_dmamap = map; 2489 txd_last->tx_m = *m_head; 2490 2491 return (0); 2492} 2493 2494static void 2495re_tx_task(void *arg, int npending) 2496{ 2497 struct ifnet *ifp; 2498 2499 ifp = arg; 2500 re_start(ifp); 2501} 2502 2503/* 2504 * Main transmit routine for C+ and gigE NICs. 2505 */ 2506static void 2507re_start(struct ifnet *ifp) 2508{ 2509 struct rl_softc *sc; 2510 struct mbuf *m_head; 2511 int queued; 2512 2513 sc = ifp->if_softc; 2514 2515 RL_LOCK(sc); 2516 2517 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2518 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2519 RL_UNLOCK(sc); 2520 return; 2521 } 2522 2523 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2524 sc->rl_ldata.rl_tx_free > 1;) { 2525 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2526 if (m_head == NULL) 2527 break; 2528 2529 if (re_encap(sc, &m_head) != 0) { 2530 if (m_head == NULL) 2531 break; 2532 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2533 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2534 break; 2535 } 2536 2537 /* 2538 * If there's a BPF listener, bounce a copy of this frame 2539 * to him. 2540 */ 2541 ETHER_BPF_MTAP(ifp, m_head); 2542 2543 queued++; 2544 } 2545 2546 if (queued == 0) { 2547#ifdef RE_TX_MODERATION 2548 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2549 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2550#endif 2551 RL_UNLOCK(sc); 2552 return; 2553 } 2554 2555 /* Flush the TX descriptors */ 2556 2557 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2558 sc->rl_ldata.rl_tx_list_map, 2559 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2560 2561 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2562 2563#ifdef RE_TX_MODERATION 2564 /* 2565 * Use the countdown timer for interrupt moderation. 2566 * 'TX done' interrupts are disabled. Instead, we reset the 2567 * countdown timer, which will begin counting until it hits 2568 * the value in the TIMERINT register, and then trigger an 2569 * interrupt. Each time we write to the TIMERCNT register, 2570 * the timer count is reset to 0. 2571 */ 2572 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2573#endif 2574 2575 /* 2576 * Set a timeout in case the chip goes out to lunch. 2577 */ 2578 sc->rl_watchdog_timer = 5; 2579 2580 RL_UNLOCK(sc); 2581} 2582 2583static void 2584re_init(void *xsc) 2585{ 2586 struct rl_softc *sc = xsc; 2587 2588 RL_LOCK(sc); 2589 re_init_locked(sc); 2590 RL_UNLOCK(sc); 2591} 2592 2593static void 2594re_init_locked(struct rl_softc *sc) 2595{ 2596 struct ifnet *ifp = sc->rl_ifp; 2597 struct mii_data *mii; 2598 uint32_t reg; 2599 uint16_t cfg; 2600 union { 2601 uint32_t align_dummy; 2602 u_char eaddr[ETHER_ADDR_LEN]; 2603 } eaddr; 2604 2605 RL_LOCK_ASSERT(sc); 2606 2607 mii = device_get_softc(sc->rl_miibus); 2608 2609 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2610 return; 2611 2612 /* 2613 * Cancel pending I/O and free all RX/TX buffers. 2614 */ 2615 re_stop(sc); 2616 2617 /* Put controller into known state. */ 2618 re_reset(sc); 2619 2620 /* 2621 * Enable C+ RX and TX mode, as well as VLAN stripping and 2622 * RX checksum offload. We must configure the C+ register 2623 * before all others. 2624 */ 2625 cfg = RL_CPLUSCMD_PCI_MRW; 2626 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2627 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2628 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2629 cfg |= RL_CPLUSCMD_VLANSTRIP; 2630 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2631 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2632 /* XXX magic. */ 2633 cfg |= 0x0001; 2634 } else 2635 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2636 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2637 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2638 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2639 reg = 0x000fff00; 2640 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2641 reg |= 0x000000ff; 2642 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2643 reg |= 0x00f00000; 2644 CSR_WRITE_4(sc, 0x7c, reg); 2645 /* Disable interrupt mitigation. */ 2646 CSR_WRITE_2(sc, 0xe2, 0); 2647 } 2648 /* 2649 * Disable TSO if interface MTU size is greater than MSS 2650 * allowed in controller. 2651 */ 2652 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2653 ifp->if_capenable &= ~IFCAP_TSO4; 2654 ifp->if_hwassist &= ~CSUM_TSO; 2655 } 2656 2657 /* 2658 * Init our MAC address. Even though the chipset 2659 * documentation doesn't mention it, we need to enter "Config 2660 * register write enable" mode to modify the ID registers. 2661 */ 2662 /* Copy MAC address on stack to align. */ 2663 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2664 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2665 CSR_WRITE_4(sc, RL_IDR0, 2666 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2667 CSR_WRITE_4(sc, RL_IDR4, 2668 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2669 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2670 2671 /* 2672 * For C+ mode, initialize the RX descriptors and mbufs. 2673 */ 2674 re_rx_list_init(sc); 2675 re_tx_list_init(sc); 2676 2677 /* 2678 * Load the addresses of the RX and TX lists into the chip. 2679 */ 2680 2681 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2682 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2683 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2684 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2685 2686 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2687 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2688 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2689 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2690 2691 /* 2692 * Enable transmit and receive. 2693 */ 2694 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2695 2696 /* 2697 * Set the initial TX configuration. 2698 */ 2699 if (sc->rl_testmode) { 2700 if (sc->rl_type == RL_8169) 2701 CSR_WRITE_4(sc, RL_TXCFG, 2702 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2703 else 2704 CSR_WRITE_4(sc, RL_TXCFG, 2705 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2706 } else 2707 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2708 2709 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2710 2711 /* 2712 * Set the initial RX configuration. 2713 */ 2714 re_set_rxmode(sc); 2715 2716 /* Configure interrupt moderation. */ 2717 if (sc->rl_type == RL_8169) { 2718 switch (sc->rl_hwrev) { 2719 case RL_HWREV_8100E: 2720 case RL_HWREV_8101E: 2721 case RL_HWREV_8102E: 2722 case RL_HWREV_8102EL: 2723 case RL_HWREV_8102EL_SPIN1: 2724 case RL_HWREV_8103E: 2725 CSR_WRITE_2(sc, RL_INTRMOD, 0); 2726 break; 2727 default: 2728 /* Magic from vendor. */ 2729 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 2730 break; 2731 } 2732 } 2733 2734#ifdef DEVICE_POLLING 2735 /* 2736 * Disable interrupts if we are polling. 2737 */ 2738 if (ifp->if_capenable & IFCAP_POLLING) 2739 CSR_WRITE_2(sc, RL_IMR, 0); 2740 else /* otherwise ... */ 2741#endif 2742 2743 /* 2744 * Enable interrupts. 2745 */ 2746 if (sc->rl_testmode) 2747 CSR_WRITE_2(sc, RL_IMR, 0); 2748 else 2749 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2750 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2751 2752 /* Set initial TX threshold */ 2753 sc->rl_txthresh = RL_TX_THRESH_INIT; 2754 2755 /* Start RX/TX process. */ 2756 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2757#ifdef notdef 2758 /* Enable receiver and transmitter. */ 2759 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2760#endif 2761 2762#ifdef RE_TX_MODERATION 2763 /* 2764 * Initialize the timer interrupt register so that 2765 * a timer interrupt will be generated once the timer 2766 * reaches a certain number of ticks. The timer is 2767 * reloaded on each transmit. This gives us TX interrupt 2768 * moderation, which dramatically improves TX frame rate. 2769 */ 2770 if (sc->rl_type == RL_8169) 2771 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2772 else 2773 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2774#endif 2775 2776 /* 2777 * For 8169 gigE NICs, set the max allowed RX packet 2778 * size so we can receive jumbo frames. 2779 */ 2780 if (sc->rl_type == RL_8169) 2781 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2782 2783 if (sc->rl_testmode) 2784 return; 2785 2786 mii_mediachg(mii); 2787 2788 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2789 2790 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2791 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2792 2793 sc->rl_flags &= ~RL_FLAG_LINK; 2794 sc->rl_watchdog_timer = 0; 2795 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2796} 2797 2798/* 2799 * Set media options. 2800 */ 2801static int 2802re_ifmedia_upd(struct ifnet *ifp) 2803{ 2804 struct rl_softc *sc; 2805 struct mii_data *mii; 2806 int error; 2807 2808 sc = ifp->if_softc; 2809 mii = device_get_softc(sc->rl_miibus); 2810 RL_LOCK(sc); 2811 error = mii_mediachg(mii); 2812 RL_UNLOCK(sc); 2813 2814 return (error); 2815} 2816 2817/* 2818 * Report current media status. 2819 */ 2820static void 2821re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2822{ 2823 struct rl_softc *sc; 2824 struct mii_data *mii; 2825 2826 sc = ifp->if_softc; 2827 mii = device_get_softc(sc->rl_miibus); 2828 2829 RL_LOCK(sc); 2830 mii_pollstat(mii); 2831 RL_UNLOCK(sc); 2832 ifmr->ifm_active = mii->mii_media_active; 2833 ifmr->ifm_status = mii->mii_media_status; 2834} 2835 2836static int 2837re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2838{ 2839 struct rl_softc *sc = ifp->if_softc; 2840 struct ifreq *ifr = (struct ifreq *) data; 2841 struct mii_data *mii; 2842 int error = 0; 2843 2844 switch (command) { 2845 case SIOCSIFMTU: 2846 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2847 error = EINVAL; 2848 break; 2849 } 2850 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2851 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2852 error = EINVAL; 2853 break; 2854 } 2855 RL_LOCK(sc); 2856 if (ifp->if_mtu != ifr->ifr_mtu) 2857 ifp->if_mtu = ifr->ifr_mtu; 2858 if (ifp->if_mtu > RL_TSO_MTU && 2859 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2860 ifp->if_capenable &= ~IFCAP_TSO4; 2861 ifp->if_hwassist &= ~CSUM_TSO; 2862 VLAN_CAPABILITIES(ifp); 2863 } 2864 RL_UNLOCK(sc); 2865 break; 2866 case SIOCSIFFLAGS: 2867 RL_LOCK(sc); 2868 if ((ifp->if_flags & IFF_UP) != 0) { 2869 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2870 if (((ifp->if_flags ^ sc->rl_if_flags) 2871 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2872 re_set_rxmode(sc); 2873 } else 2874 re_init_locked(sc); 2875 } else { 2876 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2877 re_stop(sc); 2878 } 2879 sc->rl_if_flags = ifp->if_flags; 2880 RL_UNLOCK(sc); 2881 break; 2882 case SIOCADDMULTI: 2883 case SIOCDELMULTI: 2884 RL_LOCK(sc); 2885 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2886 re_set_rxmode(sc); 2887 RL_UNLOCK(sc); 2888 break; 2889 case SIOCGIFMEDIA: 2890 case SIOCSIFMEDIA: 2891 mii = device_get_softc(sc->rl_miibus); 2892 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2893 break; 2894 case SIOCSIFCAP: 2895 { 2896 int mask, reinit; 2897 2898 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2899 reinit = 0; 2900#ifdef DEVICE_POLLING 2901 if (mask & IFCAP_POLLING) { 2902 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2903 error = ether_poll_register(re_poll, ifp); 2904 if (error) 2905 return (error); 2906 RL_LOCK(sc); 2907 /* Disable interrupts */ 2908 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2909 ifp->if_capenable |= IFCAP_POLLING; 2910 RL_UNLOCK(sc); 2911 } else { 2912 error = ether_poll_deregister(ifp); 2913 /* Enable interrupts. */ 2914 RL_LOCK(sc); 2915 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2916 ifp->if_capenable &= ~IFCAP_POLLING; 2917 RL_UNLOCK(sc); 2918 } 2919 } 2920#endif /* DEVICE_POLLING */ 2921 if (mask & IFCAP_HWCSUM) { 2922 ifp->if_capenable ^= IFCAP_HWCSUM; 2923 if (ifp->if_capenable & IFCAP_TXCSUM) 2924 ifp->if_hwassist |= RE_CSUM_FEATURES; 2925 else 2926 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2927 reinit = 1; 2928 } 2929 if ((mask & IFCAP_TSO4) != 0 && 2930 (ifp->if_capabilities & IFCAP_TSO) != 0) { 2931 ifp->if_capenable ^= IFCAP_TSO4; 2932 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 2933 ifp->if_hwassist |= CSUM_TSO; 2934 else 2935 ifp->if_hwassist &= ~CSUM_TSO; 2936 if (ifp->if_mtu > RL_TSO_MTU && 2937 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2938 ifp->if_capenable &= ~IFCAP_TSO4; 2939 ifp->if_hwassist &= ~CSUM_TSO; 2940 } 2941 } 2942 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2943 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2944 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2945 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2946 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2947 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2948 /* TSO over VLAN requires VLAN hardware tagging. */ 2949 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2950 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2951 reinit = 1; 2952 } 2953 if ((mask & IFCAP_WOL) != 0 && 2954 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2955 if ((mask & IFCAP_WOL_UCAST) != 0) 2956 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2957 if ((mask & IFCAP_WOL_MCAST) != 0) 2958 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2959 if ((mask & IFCAP_WOL_MAGIC) != 0) 2960 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2961 } 2962 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 2963 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2964 re_init(sc); 2965 } 2966 VLAN_CAPABILITIES(ifp); 2967 } 2968 break; 2969 default: 2970 error = ether_ioctl(ifp, command, data); 2971 break; 2972 } 2973 2974 return (error); 2975} 2976 2977static void 2978re_watchdog(struct rl_softc *sc) 2979{ 2980 struct ifnet *ifp; 2981 2982 RL_LOCK_ASSERT(sc); 2983 2984 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2985 return; 2986 2987 ifp = sc->rl_ifp; 2988 re_txeof(sc); 2989 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2990 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2991 "-- recovering\n"); 2992 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2993 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2994 return; 2995 } 2996 2997 if_printf(ifp, "watchdog timeout\n"); 2998 ifp->if_oerrors++; 2999 3000 re_rxeof(sc, NULL); 3001 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3002 re_init_locked(sc); 3003 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3004 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 3005} 3006 3007/* 3008 * Stop the adapter and free any mbufs allocated to the 3009 * RX and TX lists. 3010 */ 3011static void 3012re_stop(struct rl_softc *sc) 3013{ 3014 int i; 3015 struct ifnet *ifp; 3016 struct rl_txdesc *txd; 3017 struct rl_rxdesc *rxd; 3018 3019 RL_LOCK_ASSERT(sc); 3020 3021 ifp = sc->rl_ifp; 3022 3023 sc->rl_watchdog_timer = 0; 3024 callout_stop(&sc->rl_stat_callout); 3025 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3026 3027 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 3028 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3029 RL_CMD_RX_ENB); 3030 else 3031 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3032 DELAY(1000); 3033 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3034 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3035 3036 if (sc->rl_head != NULL) { 3037 m_freem(sc->rl_head); 3038 sc->rl_head = sc->rl_tail = NULL; 3039 } 3040 3041 /* Free the TX list buffers. */ 3042 3043 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3044 txd = &sc->rl_ldata.rl_tx_desc[i]; 3045 if (txd->tx_m != NULL) { 3046 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3047 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3048 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3049 txd->tx_dmamap); 3050 m_freem(txd->tx_m); 3051 txd->tx_m = NULL; 3052 } 3053 } 3054 3055 /* Free the RX list buffers. */ 3056 3057 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3058 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3059 if (rxd->rx_m != NULL) { 3060 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3061 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3062 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3063 rxd->rx_dmamap); 3064 m_freem(rxd->rx_m); 3065 rxd->rx_m = NULL; 3066 } 3067 } 3068} 3069 3070/* 3071 * Device suspend routine. Stop the interface and save some PCI 3072 * settings in case the BIOS doesn't restore them properly on 3073 * resume. 3074 */ 3075static int 3076re_suspend(device_t dev) 3077{ 3078 struct rl_softc *sc; 3079 3080 sc = device_get_softc(dev); 3081 3082 RL_LOCK(sc); 3083 re_stop(sc); 3084 re_setwol(sc); 3085 sc->suspended = 1; 3086 RL_UNLOCK(sc); 3087 3088 return (0); 3089} 3090 3091/* 3092 * Device resume routine. Restore some PCI settings in case the BIOS 3093 * doesn't, re-enable busmastering, and restart the interface if 3094 * appropriate. 3095 */ 3096static int 3097re_resume(device_t dev) 3098{ 3099 struct rl_softc *sc; 3100 struct ifnet *ifp; 3101 3102 sc = device_get_softc(dev); 3103 3104 RL_LOCK(sc); 3105 3106 ifp = sc->rl_ifp; 3107 /* Take controller out of sleep mode. */ 3108 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3109 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3110 CSR_WRITE_1(sc, RL_GPIO, 3111 CSR_READ_1(sc, RL_GPIO) | 0x01); 3112 } 3113 3114 /* 3115 * Clear WOL matching such that normal Rx filtering 3116 * wouldn't interfere with WOL patterns. 3117 */ 3118 re_clrwol(sc); 3119 3120 /* reinitialize interface if necessary */ 3121 if (ifp->if_flags & IFF_UP) 3122 re_init_locked(sc); 3123 3124 sc->suspended = 0; 3125 RL_UNLOCK(sc); 3126 3127 return (0); 3128} 3129 3130/* 3131 * Stop all chip I/O so that the kernel's probe routines don't 3132 * get confused by errant DMAs when rebooting. 3133 */ 3134static int 3135re_shutdown(device_t dev) 3136{ 3137 struct rl_softc *sc; 3138 3139 sc = device_get_softc(dev); 3140 3141 RL_LOCK(sc); 3142 re_stop(sc); 3143 /* 3144 * Mark interface as down since otherwise we will panic if 3145 * interrupt comes in later on, which can happen in some 3146 * cases. 3147 */ 3148 sc->rl_ifp->if_flags &= ~IFF_UP; 3149 re_setwol(sc); 3150 RL_UNLOCK(sc); 3151 3152 return (0); 3153} 3154 3155static void 3156re_setwol(struct rl_softc *sc) 3157{ 3158 struct ifnet *ifp; 3159 int pmc; 3160 uint16_t pmstat; 3161 uint8_t v; 3162 3163 RL_LOCK_ASSERT(sc); 3164 3165 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3166 return; 3167 3168 ifp = sc->rl_ifp; 3169 /* Put controller into sleep mode. */ 3170 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3171 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3172 CSR_WRITE_1(sc, RL_GPIO, 3173 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3174 } 3175 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3176 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3177 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3178 /* Enable config register write. */ 3179 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3180 3181 /* Enable PME. */ 3182 v = CSR_READ_1(sc, RL_CFG1); 3183 v &= ~RL_CFG1_PME; 3184 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3185 v |= RL_CFG1_PME; 3186 CSR_WRITE_1(sc, RL_CFG1, v); 3187 3188 v = CSR_READ_1(sc, RL_CFG3); 3189 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3190 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3191 v |= RL_CFG3_WOL_MAGIC; 3192 CSR_WRITE_1(sc, RL_CFG3, v); 3193 3194 /* Config register write done. */ 3195 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3196 3197 v = CSR_READ_1(sc, RL_CFG5); 3198 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3199 v &= ~RL_CFG5_WOL_LANWAKE; 3200 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3201 v |= RL_CFG5_WOL_UCAST; 3202 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3203 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3204 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3205 v |= RL_CFG5_WOL_LANWAKE; 3206 CSR_WRITE_1(sc, RL_CFG5, v); 3207 3208 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3209 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3210 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3211 /* 3212 * It seems that hardware resets its link speed to 100Mbps in 3213 * power down mode so switching to 100Mbps in driver is not 3214 * needed. 3215 */ 3216 3217 /* Request PME if WOL is requested. */ 3218 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3219 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3220 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3221 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3222 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3223} 3224 3225static void 3226re_clrwol(struct rl_softc *sc) 3227{ 3228 int pmc; 3229 uint8_t v; 3230 3231 RL_LOCK_ASSERT(sc); 3232 3233 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3234 return; 3235 3236 /* Enable config register write. */ 3237 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3238 3239 v = CSR_READ_1(sc, RL_CFG3); 3240 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3241 CSR_WRITE_1(sc, RL_CFG3, v); 3242 3243 /* Config register write done. */ 3244 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3245 3246 v = CSR_READ_1(sc, RL_CFG5); 3247 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3248 v &= ~RL_CFG5_WOL_LANWAKE; 3249 CSR_WRITE_1(sc, RL_CFG5, v); 3250} 3251 3252static void 3253re_add_sysctls(struct rl_softc *sc) 3254{ 3255 struct sysctl_ctx_list *ctx; 3256 struct sysctl_oid_list *children; 3257 3258 ctx = device_get_sysctl_ctx(sc->rl_dev); 3259 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3260 3261 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3262 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3263 "Statistics Information"); 3264} 3265 3266static int 3267re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3268{ 3269 struct rl_softc *sc; 3270 struct rl_stats *stats; 3271 int error, i, result; 3272 3273 result = -1; 3274 error = sysctl_handle_int(oidp, &result, 0, req); 3275 if (error || req->newptr == NULL) 3276 return (error); 3277 3278 if (result == 1) { 3279 sc = (struct rl_softc *)arg1; 3280 RL_LOCK(sc); 3281 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3282 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3283 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3284 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3285 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3286 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3287 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3288 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3289 RL_DUMPSTATS_START)); 3290 for (i = RL_TIMEOUT; i > 0; i--) { 3291 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3292 RL_DUMPSTATS_START) == 0) 3293 break; 3294 DELAY(1000); 3295 } 3296 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3297 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3298 RL_UNLOCK(sc); 3299 if (i == 0) { 3300 device_printf(sc->rl_dev, 3301 "DUMP statistics request timedout\n"); 3302 return (ETIMEDOUT); 3303 } 3304 stats = sc->rl_ldata.rl_stats; 3305 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3306 printf("Tx frames : %ju\n", 3307 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3308 printf("Rx frames : %ju\n", 3309 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3310 printf("Tx errors : %ju\n", 3311 (uintmax_t)le64toh(stats->rl_tx_errs)); 3312 printf("Rx errors : %u\n", 3313 le32toh(stats->rl_rx_errs)); 3314 printf("Rx missed frames : %u\n", 3315 (uint32_t)le16toh(stats->rl_missed_pkts)); 3316 printf("Rx frame alignment errs : %u\n", 3317 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3318 printf("Tx single collisions : %u\n", 3319 le32toh(stats->rl_tx_onecoll)); 3320 printf("Tx multiple collisions : %u\n", 3321 le32toh(stats->rl_tx_multicolls)); 3322 printf("Rx unicast frames : %ju\n", 3323 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3324 printf("Rx broadcast frames : %ju\n", 3325 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3326 printf("Rx multicast frames : %u\n", 3327 le32toh(stats->rl_rx_mcasts)); 3328 printf("Tx aborts : %u\n", 3329 (uint32_t)le16toh(stats->rl_tx_aborts)); 3330 printf("Tx underruns : %u\n", 3331 (uint32_t)le16toh(stats->rl_rx_underruns)); 3332 } 3333 3334 return (error); 3335} 3336