if_re.c revision 214842
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 214842 2010-11-05 18:24:50Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* Tunables. */ 159static int msi_disable = 0; 160TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161static int prefer_iomap = 0; 162TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 163 164#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 165 166/* 167 * Various supported device vendors/types and their names. 168 */ 169static struct rl_type re_devs[] = { 170 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 171 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 172 { RT_VENDORID, RT_DEVICEID_8139, 0, 173 "RealTek 8139C+ 10/100BaseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8101E, 0, 175 "RealTek 8101E/8102E/8102EL/8103E PCIe 10/100baseTX" }, 176 { RT_VENDORID, RT_DEVICEID_8168, 0, 177 "RealTek 8168/8111 B/C/CP/D/DP/E PCIe Gigabit Ethernet" }, 178 { RT_VENDORID, RT_DEVICEID_8169, 0, 179 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 180 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 181 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 182 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 183 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 184 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 185 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 186 { USR_VENDORID, USR_DEVICEID_997902, 0, 187 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 188}; 189 190static struct rl_hwrev re_hwrevs[] = { 191 { RL_HWREV_8139, RL_8139, "" }, 192 { RL_HWREV_8139A, RL_8139, "A" }, 193 { RL_HWREV_8139AG, RL_8139, "A-G" }, 194 { RL_HWREV_8139B, RL_8139, "B" }, 195 { RL_HWREV_8130, RL_8139, "8130" }, 196 { RL_HWREV_8139C, RL_8139, "C" }, 197 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 198 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 199 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 200 { RL_HWREV_8169, RL_8169, "8169"}, 201 { RL_HWREV_8169S, RL_8169, "8169S"}, 202 { RL_HWREV_8110S, RL_8169, "8110S"}, 203 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 204 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 205 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 206 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, 207 { RL_HWREV_8100, RL_8139, "8100"}, 208 { RL_HWREV_8101, RL_8139, "8101"}, 209 { RL_HWREV_8100E, RL_8169, "8100E"}, 210 { RL_HWREV_8101E, RL_8169, "8101E"}, 211 { RL_HWREV_8102E, RL_8169, "8102E"}, 212 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 213 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL"}, 214 { RL_HWREV_8103E, RL_8169, "8103E"}, 215 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 216 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 217 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 218 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 219 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 220 { RL_HWREV_8168D, RL_8169, "8168D/8111D"}, 221 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP"}, 222 { RL_HWREV_8168E, RL_8169, "8168E/8111E"}, 223 { 0, 0, NULL } 224}; 225 226static int re_probe (device_t); 227static int re_attach (device_t); 228static int re_detach (device_t); 229 230static int re_encap (struct rl_softc *, struct mbuf **); 231 232static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 233static int re_allocmem (device_t, struct rl_softc *); 234static __inline void re_discard_rxbuf 235 (struct rl_softc *, int); 236static int re_newbuf (struct rl_softc *, int); 237static int re_rx_list_init (struct rl_softc *); 238static int re_tx_list_init (struct rl_softc *); 239#ifdef RE_FIXUP_RX 240static __inline void re_fixup_rx 241 (struct mbuf *); 242#endif 243static int re_rxeof (struct rl_softc *, int *); 244static void re_txeof (struct rl_softc *); 245#ifdef DEVICE_POLLING 246static int re_poll (struct ifnet *, enum poll_cmd, int); 247static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 248#endif 249static int re_intr (void *); 250static void re_tick (void *); 251static void re_tx_task (void *, int); 252static void re_int_task (void *, int); 253static void re_start (struct ifnet *); 254static int re_ioctl (struct ifnet *, u_long, caddr_t); 255static void re_init (void *); 256static void re_init_locked (struct rl_softc *); 257static void re_stop (struct rl_softc *); 258static void re_watchdog (struct rl_softc *); 259static int re_suspend (device_t); 260static int re_resume (device_t); 261static int re_shutdown (device_t); 262static int re_ifmedia_upd (struct ifnet *); 263static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 264 265static void re_eeprom_putbyte (struct rl_softc *, int); 266static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 267static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 268static int re_gmii_readreg (device_t, int, int); 269static int re_gmii_writereg (device_t, int, int, int); 270 271static int re_miibus_readreg (device_t, int, int); 272static int re_miibus_writereg (device_t, int, int, int); 273static void re_miibus_statchg (device_t); 274 275static void re_set_rxmode (struct rl_softc *); 276static void re_reset (struct rl_softc *); 277static void re_setwol (struct rl_softc *); 278static void re_clrwol (struct rl_softc *); 279 280#ifdef RE_DIAG 281static int re_diag (struct rl_softc *); 282#endif 283 284static device_method_t re_methods[] = { 285 /* Device interface */ 286 DEVMETHOD(device_probe, re_probe), 287 DEVMETHOD(device_attach, re_attach), 288 DEVMETHOD(device_detach, re_detach), 289 DEVMETHOD(device_suspend, re_suspend), 290 DEVMETHOD(device_resume, re_resume), 291 DEVMETHOD(device_shutdown, re_shutdown), 292 293 /* bus interface */ 294 DEVMETHOD(bus_print_child, bus_generic_print_child), 295 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 296 297 /* MII interface */ 298 DEVMETHOD(miibus_readreg, re_miibus_readreg), 299 DEVMETHOD(miibus_writereg, re_miibus_writereg), 300 DEVMETHOD(miibus_statchg, re_miibus_statchg), 301 302 { 0, 0 } 303}; 304 305static driver_t re_driver = { 306 "re", 307 re_methods, 308 sizeof(struct rl_softc) 309}; 310 311static devclass_t re_devclass; 312 313DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 314DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 315 316#define EE_SET(x) \ 317 CSR_WRITE_1(sc, RL_EECMD, \ 318 CSR_READ_1(sc, RL_EECMD) | x) 319 320#define EE_CLR(x) \ 321 CSR_WRITE_1(sc, RL_EECMD, \ 322 CSR_READ_1(sc, RL_EECMD) & ~x) 323 324/* 325 * Send a read command and address to the EEPROM, check for ACK. 326 */ 327static void 328re_eeprom_putbyte(struct rl_softc *sc, int addr) 329{ 330 int d, i; 331 332 d = addr | (RL_9346_READ << sc->rl_eewidth); 333 334 /* 335 * Feed in each bit and strobe the clock. 336 */ 337 338 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 339 if (d & i) { 340 EE_SET(RL_EE_DATAIN); 341 } else { 342 EE_CLR(RL_EE_DATAIN); 343 } 344 DELAY(100); 345 EE_SET(RL_EE_CLK); 346 DELAY(150); 347 EE_CLR(RL_EE_CLK); 348 DELAY(100); 349 } 350} 351 352/* 353 * Read a word of data stored in the EEPROM at address 'addr.' 354 */ 355static void 356re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 357{ 358 int i; 359 u_int16_t word = 0; 360 361 /* 362 * Send address of word we want to read. 363 */ 364 re_eeprom_putbyte(sc, addr); 365 366 /* 367 * Start reading bits from EEPROM. 368 */ 369 for (i = 0x8000; i; i >>= 1) { 370 EE_SET(RL_EE_CLK); 371 DELAY(100); 372 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 373 word |= i; 374 EE_CLR(RL_EE_CLK); 375 DELAY(100); 376 } 377 378 *dest = word; 379} 380 381/* 382 * Read a sequence of words from the EEPROM. 383 */ 384static void 385re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 386{ 387 int i; 388 u_int16_t word = 0, *ptr; 389 390 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 391 392 DELAY(100); 393 394 for (i = 0; i < cnt; i++) { 395 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 396 re_eeprom_getword(sc, off + i, &word); 397 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 398 ptr = (u_int16_t *)(dest + (i * 2)); 399 *ptr = word; 400 } 401 402 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 403} 404 405static int 406re_gmii_readreg(device_t dev, int phy, int reg) 407{ 408 struct rl_softc *sc; 409 u_int32_t rval; 410 int i; 411 412 sc = device_get_softc(dev); 413 414 /* Let the rgephy driver read the GMEDIASTAT register */ 415 416 if (reg == RL_GMEDIASTAT) { 417 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 418 return (rval); 419 } 420 421 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 422 DELAY(1000); 423 424 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 425 rval = CSR_READ_4(sc, RL_PHYAR); 426 if (rval & RL_PHYAR_BUSY) 427 break; 428 DELAY(100); 429 } 430 431 if (i == RL_PHY_TIMEOUT) { 432 device_printf(sc->rl_dev, "PHY read failed\n"); 433 return (0); 434 } 435 436 return (rval & RL_PHYAR_PHYDATA); 437} 438 439static int 440re_gmii_writereg(device_t dev, int phy, int reg, int data) 441{ 442 struct rl_softc *sc; 443 u_int32_t rval; 444 int i; 445 446 sc = device_get_softc(dev); 447 448 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 449 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 450 DELAY(1000); 451 452 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 453 rval = CSR_READ_4(sc, RL_PHYAR); 454 if (!(rval & RL_PHYAR_BUSY)) 455 break; 456 DELAY(100); 457 } 458 459 if (i == RL_PHY_TIMEOUT) { 460 device_printf(sc->rl_dev, "PHY write failed\n"); 461 return (0); 462 } 463 464 return (0); 465} 466 467static int 468re_miibus_readreg(device_t dev, int phy, int reg) 469{ 470 struct rl_softc *sc; 471 u_int16_t rval = 0; 472 u_int16_t re8139_reg = 0; 473 474 sc = device_get_softc(dev); 475 476 if (sc->rl_type == RL_8169) { 477 rval = re_gmii_readreg(dev, phy, reg); 478 return (rval); 479 } 480 481 switch (reg) { 482 case MII_BMCR: 483 re8139_reg = RL_BMCR; 484 break; 485 case MII_BMSR: 486 re8139_reg = RL_BMSR; 487 break; 488 case MII_ANAR: 489 re8139_reg = RL_ANAR; 490 break; 491 case MII_ANER: 492 re8139_reg = RL_ANER; 493 break; 494 case MII_ANLPAR: 495 re8139_reg = RL_LPAR; 496 break; 497 case MII_PHYIDR1: 498 case MII_PHYIDR2: 499 return (0); 500 /* 501 * Allow the rlphy driver to read the media status 502 * register. If we have a link partner which does not 503 * support NWAY, this is the register which will tell 504 * us the results of parallel detection. 505 */ 506 case RL_MEDIASTAT: 507 rval = CSR_READ_1(sc, RL_MEDIASTAT); 508 return (rval); 509 default: 510 device_printf(sc->rl_dev, "bad phy register\n"); 511 return (0); 512 } 513 rval = CSR_READ_2(sc, re8139_reg); 514 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 515 /* 8139C+ has different bit layout. */ 516 rval &= ~(BMCR_LOOP | BMCR_ISO); 517 } 518 return (rval); 519} 520 521static int 522re_miibus_writereg(device_t dev, int phy, int reg, int data) 523{ 524 struct rl_softc *sc; 525 u_int16_t re8139_reg = 0; 526 int rval = 0; 527 528 sc = device_get_softc(dev); 529 530 if (sc->rl_type == RL_8169) { 531 rval = re_gmii_writereg(dev, phy, reg, data); 532 return (rval); 533 } 534 535 switch (reg) { 536 case MII_BMCR: 537 re8139_reg = RL_BMCR; 538 if (sc->rl_type == RL_8139CPLUS) { 539 /* 8139C+ has different bit layout. */ 540 data &= ~(BMCR_LOOP | BMCR_ISO); 541 } 542 break; 543 case MII_BMSR: 544 re8139_reg = RL_BMSR; 545 break; 546 case MII_ANAR: 547 re8139_reg = RL_ANAR; 548 break; 549 case MII_ANER: 550 re8139_reg = RL_ANER; 551 break; 552 case MII_ANLPAR: 553 re8139_reg = RL_LPAR; 554 break; 555 case MII_PHYIDR1: 556 case MII_PHYIDR2: 557 return (0); 558 break; 559 default: 560 device_printf(sc->rl_dev, "bad phy register\n"); 561 return (0); 562 } 563 CSR_WRITE_2(sc, re8139_reg, data); 564 return (0); 565} 566 567static void 568re_miibus_statchg(device_t dev) 569{ 570 struct rl_softc *sc; 571 struct ifnet *ifp; 572 struct mii_data *mii; 573 574 sc = device_get_softc(dev); 575 mii = device_get_softc(sc->rl_miibus); 576 ifp = sc->rl_ifp; 577 if (mii == NULL || ifp == NULL || 578 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 579 return; 580 581 sc->rl_flags &= ~RL_FLAG_LINK; 582 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 583 (IFM_ACTIVE | IFM_AVALID)) { 584 switch (IFM_SUBTYPE(mii->mii_media_active)) { 585 case IFM_10_T: 586 case IFM_100_TX: 587 sc->rl_flags |= RL_FLAG_LINK; 588 break; 589 case IFM_1000_T: 590 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 591 break; 592 sc->rl_flags |= RL_FLAG_LINK; 593 break; 594 default: 595 break; 596 } 597 } 598 /* 599 * RealTek controllers does not provide any interface to 600 * Tx/Rx MACs for resolved speed, duplex and flow-control 601 * parameters. 602 */ 603} 604 605/* 606 * Set the RX configuration and 64-bit multicast hash filter. 607 */ 608static void 609re_set_rxmode(struct rl_softc *sc) 610{ 611 struct ifnet *ifp; 612 struct ifmultiaddr *ifma; 613 uint32_t hashes[2] = { 0, 0 }; 614 uint32_t h, rxfilt; 615 616 RL_LOCK_ASSERT(sc); 617 618 ifp = sc->rl_ifp; 619 620 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 621 622 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 623 if (ifp->if_flags & IFF_PROMISC) 624 rxfilt |= RL_RXCFG_RX_ALLPHYS; 625 /* 626 * Unlike other hardwares, we have to explicitly set 627 * RL_RXCFG_RX_MULTI to receive multicast frames in 628 * promiscuous mode. 629 */ 630 rxfilt |= RL_RXCFG_RX_MULTI; 631 hashes[0] = hashes[1] = 0xffffffff; 632 goto done; 633 } 634 635 if_maddr_rlock(ifp); 636 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 637 if (ifma->ifma_addr->sa_family != AF_LINK) 638 continue; 639 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 640 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 641 if (h < 32) 642 hashes[0] |= (1 << h); 643 else 644 hashes[1] |= (1 << (h - 32)); 645 } 646 if_maddr_runlock(ifp); 647 648 if (hashes[0] != 0 || hashes[1] != 0) { 649 /* 650 * For some unfathomable reason, RealTek decided to 651 * reverse the order of the multicast hash registers 652 * in the PCI Express parts. This means we have to 653 * write the hash pattern in reverse order for those 654 * devices. 655 */ 656 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 657 h = bswap32(hashes[0]); 658 hashes[0] = bswap32(hashes[1]); 659 hashes[1] = h; 660 } 661 rxfilt |= RL_RXCFG_RX_MULTI; 662 } 663 664done: 665 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 666 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 667 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 668} 669 670static void 671re_reset(struct rl_softc *sc) 672{ 673 int i; 674 675 RL_LOCK_ASSERT(sc); 676 677 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 678 679 for (i = 0; i < RL_TIMEOUT; i++) { 680 DELAY(10); 681 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 682 break; 683 } 684 if (i == RL_TIMEOUT) 685 device_printf(sc->rl_dev, "reset never completed!\n"); 686 687 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 688 CSR_WRITE_1(sc, 0x82, 1); 689 if (sc->rl_hwrev == RL_HWREV_8169S) 690 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 691} 692 693#ifdef RE_DIAG 694 695/* 696 * The following routine is designed to test for a defect on some 697 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 698 * lines connected to the bus, however for a 32-bit only card, they 699 * should be pulled high. The result of this defect is that the 700 * NIC will not work right if you plug it into a 64-bit slot: DMA 701 * operations will be done with 64-bit transfers, which will fail 702 * because the 64-bit data lines aren't connected. 703 * 704 * There's no way to work around this (short of talking a soldering 705 * iron to the board), however we can detect it. The method we use 706 * here is to put the NIC into digital loopback mode, set the receiver 707 * to promiscuous mode, and then try to send a frame. We then compare 708 * the frame data we sent to what was received. If the data matches, 709 * then the NIC is working correctly, otherwise we know the user has 710 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 711 * slot. In the latter case, there's no way the NIC can work correctly, 712 * so we print out a message on the console and abort the device attach. 713 */ 714 715static int 716re_diag(struct rl_softc *sc) 717{ 718 struct ifnet *ifp = sc->rl_ifp; 719 struct mbuf *m0; 720 struct ether_header *eh; 721 struct rl_desc *cur_rx; 722 u_int16_t status; 723 u_int32_t rxstat; 724 int total_len, i, error = 0, phyaddr; 725 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 726 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 727 728 /* Allocate a single mbuf */ 729 MGETHDR(m0, M_DONTWAIT, MT_DATA); 730 if (m0 == NULL) 731 return (ENOBUFS); 732 733 RL_LOCK(sc); 734 735 /* 736 * Initialize the NIC in test mode. This sets the chip up 737 * so that it can send and receive frames, but performs the 738 * following special functions: 739 * - Puts receiver in promiscuous mode 740 * - Enables digital loopback mode 741 * - Leaves interrupts turned off 742 */ 743 744 ifp->if_flags |= IFF_PROMISC; 745 sc->rl_testmode = 1; 746 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 747 re_init_locked(sc); 748 sc->rl_flags |= RL_FLAG_LINK; 749 if (sc->rl_type == RL_8169) 750 phyaddr = 1; 751 else 752 phyaddr = 0; 753 754 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 755 for (i = 0; i < RL_TIMEOUT; i++) { 756 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 757 if (!(status & BMCR_RESET)) 758 break; 759 } 760 761 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 762 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 763 764 DELAY(100000); 765 766 /* Put some data in the mbuf */ 767 768 eh = mtod(m0, struct ether_header *); 769 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 770 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 771 eh->ether_type = htons(ETHERTYPE_IP); 772 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 773 774 /* 775 * Queue the packet, start transmission. 776 * Note: IF_HANDOFF() ultimately calls re_start() for us. 777 */ 778 779 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 780 RL_UNLOCK(sc); 781 /* XXX: re_diag must not be called when in ALTQ mode */ 782 IF_HANDOFF(&ifp->if_snd, m0, ifp); 783 RL_LOCK(sc); 784 m0 = NULL; 785 786 /* Wait for it to propagate through the chip */ 787 788 DELAY(100000); 789 for (i = 0; i < RL_TIMEOUT; i++) { 790 status = CSR_READ_2(sc, RL_ISR); 791 CSR_WRITE_2(sc, RL_ISR, status); 792 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 793 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 794 break; 795 DELAY(10); 796 } 797 798 if (i == RL_TIMEOUT) { 799 device_printf(sc->rl_dev, 800 "diagnostic failed, failed to receive packet in" 801 " loopback mode\n"); 802 error = EIO; 803 goto done; 804 } 805 806 /* 807 * The packet should have been dumped into the first 808 * entry in the RX DMA ring. Grab it from there. 809 */ 810 811 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 812 sc->rl_ldata.rl_rx_list_map, 813 BUS_DMASYNC_POSTREAD); 814 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 815 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 816 BUS_DMASYNC_POSTREAD); 817 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 818 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 819 820 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 821 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 822 eh = mtod(m0, struct ether_header *); 823 824 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 825 total_len = RL_RXBYTES(cur_rx); 826 rxstat = le32toh(cur_rx->rl_cmdstat); 827 828 if (total_len != ETHER_MIN_LEN) { 829 device_printf(sc->rl_dev, 830 "diagnostic failed, received short packet\n"); 831 error = EIO; 832 goto done; 833 } 834 835 /* Test that the received packet data matches what we sent. */ 836 837 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 838 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 839 ntohs(eh->ether_type) != ETHERTYPE_IP) { 840 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 841 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 842 dst, ":", src, ":", ETHERTYPE_IP); 843 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 844 eh->ether_dhost, ":", eh->ether_shost, ":", 845 ntohs(eh->ether_type)); 846 device_printf(sc->rl_dev, "You may have a defective 32-bit " 847 "NIC plugged into a 64-bit PCI slot.\n"); 848 device_printf(sc->rl_dev, "Please re-install the NIC in a " 849 "32-bit slot for proper operation.\n"); 850 device_printf(sc->rl_dev, "Read the re(4) man page for more " 851 "details.\n"); 852 error = EIO; 853 } 854 855done: 856 /* Turn interface off, release resources */ 857 858 sc->rl_testmode = 0; 859 sc->rl_flags &= ~RL_FLAG_LINK; 860 ifp->if_flags &= ~IFF_PROMISC; 861 re_stop(sc); 862 if (m0 != NULL) 863 m_freem(m0); 864 865 RL_UNLOCK(sc); 866 867 return (error); 868} 869 870#endif 871 872/* 873 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 874 * IDs against our list and return a device name if we find a match. 875 */ 876static int 877re_probe(device_t dev) 878{ 879 struct rl_type *t; 880 uint16_t devid, vendor; 881 uint16_t revid, sdevid; 882 int i; 883 884 vendor = pci_get_vendor(dev); 885 devid = pci_get_device(dev); 886 revid = pci_get_revid(dev); 887 sdevid = pci_get_subdevice(dev); 888 889 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 890 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 891 /* 892 * Only attach to rev. 3 of the Linksys EG1032 adapter. 893 * Rev. 2 is supported by sk(4). 894 */ 895 return (ENXIO); 896 } 897 } 898 899 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 900 if (revid != 0x20) { 901 /* 8139, let rl(4) take care of this device. */ 902 return (ENXIO); 903 } 904 } 905 906 t = re_devs; 907 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 908 if (vendor == t->rl_vid && devid == t->rl_did) { 909 device_set_desc(dev, t->rl_name); 910 return (BUS_PROBE_DEFAULT); 911 } 912 } 913 914 return (ENXIO); 915} 916 917/* 918 * Map a single buffer address. 919 */ 920 921static void 922re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 923{ 924 bus_addr_t *addr; 925 926 if (error) 927 return; 928 929 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 930 addr = arg; 931 *addr = segs->ds_addr; 932} 933 934static int 935re_allocmem(device_t dev, struct rl_softc *sc) 936{ 937 bus_addr_t lowaddr; 938 bus_size_t rx_list_size, tx_list_size; 939 int error; 940 int i; 941 942 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 943 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 944 945 /* 946 * Allocate the parent bus DMA tag appropriate for PCI. 947 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 948 * register should be set. However some RealTek chips are known 949 * to be buggy on DAC handling, therefore disable DAC by limiting 950 * DMA address space to 32bit. PCIe variants of RealTek chips 951 * may not have the limitation. 952 */ 953 lowaddr = BUS_SPACE_MAXADDR; 954 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 955 lowaddr = BUS_SPACE_MAXADDR_32BIT; 956 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 957 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 958 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 959 NULL, NULL, &sc->rl_parent_tag); 960 if (error) { 961 device_printf(dev, "could not allocate parent DMA tag\n"); 962 return (error); 963 } 964 965 /* 966 * Allocate map for TX mbufs. 967 */ 968 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 969 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 970 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 971 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 972 if (error) { 973 device_printf(dev, "could not allocate TX DMA tag\n"); 974 return (error); 975 } 976 977 /* 978 * Allocate map for RX mbufs. 979 */ 980 981 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 982 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 983 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 984 if (error) { 985 device_printf(dev, "could not allocate RX DMA tag\n"); 986 return (error); 987 } 988 989 /* 990 * Allocate map for TX descriptor list. 991 */ 992 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 993 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 994 NULL, tx_list_size, 1, tx_list_size, 0, 995 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 996 if (error) { 997 device_printf(dev, "could not allocate TX DMA ring tag\n"); 998 return (error); 999 } 1000 1001 /* Allocate DMA'able memory for the TX ring */ 1002 1003 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1004 (void **)&sc->rl_ldata.rl_tx_list, 1005 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1006 &sc->rl_ldata.rl_tx_list_map); 1007 if (error) { 1008 device_printf(dev, "could not allocate TX DMA ring\n"); 1009 return (error); 1010 } 1011 1012 /* Load the map for the TX ring. */ 1013 1014 sc->rl_ldata.rl_tx_list_addr = 0; 1015 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1016 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1017 tx_list_size, re_dma_map_addr, 1018 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1019 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1020 device_printf(dev, "could not load TX DMA ring\n"); 1021 return (ENOMEM); 1022 } 1023 1024 /* Create DMA maps for TX buffers */ 1025 1026 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1027 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1028 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1029 if (error) { 1030 device_printf(dev, "could not create DMA map for TX\n"); 1031 return (error); 1032 } 1033 } 1034 1035 /* 1036 * Allocate map for RX descriptor list. 1037 */ 1038 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1039 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1040 NULL, rx_list_size, 1, rx_list_size, 0, 1041 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1042 if (error) { 1043 device_printf(dev, "could not create RX DMA ring tag\n"); 1044 return (error); 1045 } 1046 1047 /* Allocate DMA'able memory for the RX ring */ 1048 1049 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1050 (void **)&sc->rl_ldata.rl_rx_list, 1051 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1052 &sc->rl_ldata.rl_rx_list_map); 1053 if (error) { 1054 device_printf(dev, "could not allocate RX DMA ring\n"); 1055 return (error); 1056 } 1057 1058 /* Load the map for the RX ring. */ 1059 1060 sc->rl_ldata.rl_rx_list_addr = 0; 1061 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1062 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1063 rx_list_size, re_dma_map_addr, 1064 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1065 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1066 device_printf(dev, "could not load RX DMA ring\n"); 1067 return (ENOMEM); 1068 } 1069 1070 /* Create DMA maps for RX buffers */ 1071 1072 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1073 &sc->rl_ldata.rl_rx_sparemap); 1074 if (error) { 1075 device_printf(dev, "could not create spare DMA map for RX\n"); 1076 return (error); 1077 } 1078 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1079 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1080 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1081 if (error) { 1082 device_printf(dev, "could not create DMA map for RX\n"); 1083 return (error); 1084 } 1085 } 1086 1087 return (0); 1088} 1089 1090/* 1091 * Attach the interface. Allocate softc structures, do ifmedia 1092 * setup and ethernet/BPF attach. 1093 */ 1094static int 1095re_attach(device_t dev) 1096{ 1097 u_char eaddr[ETHER_ADDR_LEN]; 1098 u_int16_t as[ETHER_ADDR_LEN / 2]; 1099 struct rl_softc *sc; 1100 struct ifnet *ifp; 1101 struct rl_hwrev *hw_rev; 1102 int hwrev; 1103 u_int16_t devid, re_did = 0; 1104 int error = 0, i, phy, rid; 1105 int msic, reg; 1106 uint8_t cfg; 1107 1108 sc = device_get_softc(dev); 1109 sc->rl_dev = dev; 1110 1111 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1112 MTX_DEF); 1113 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1114 1115 /* 1116 * Map control/status registers. 1117 */ 1118 pci_enable_busmaster(dev); 1119 1120 devid = pci_get_device(dev); 1121 /* 1122 * Prefer memory space register mapping over IO space. 1123 * Because RTL8169SC does not seem to work when memory mapping 1124 * is used always activate io mapping. 1125 */ 1126 if (devid == RT_DEVICEID_8169SC) 1127 prefer_iomap = 1; 1128 if (prefer_iomap == 0) { 1129 sc->rl_res_id = PCIR_BAR(1); 1130 sc->rl_res_type = SYS_RES_MEMORY; 1131 /* RTL8168/8101E seems to use different BARs. */ 1132 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1133 sc->rl_res_id = PCIR_BAR(2); 1134 } else { 1135 sc->rl_res_id = PCIR_BAR(0); 1136 sc->rl_res_type = SYS_RES_IOPORT; 1137 } 1138 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1139 &sc->rl_res_id, RF_ACTIVE); 1140 if (sc->rl_res == NULL && prefer_iomap == 0) { 1141 sc->rl_res_id = PCIR_BAR(0); 1142 sc->rl_res_type = SYS_RES_IOPORT; 1143 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1144 &sc->rl_res_id, RF_ACTIVE); 1145 } 1146 if (sc->rl_res == NULL) { 1147 device_printf(dev, "couldn't map ports/memory\n"); 1148 error = ENXIO; 1149 goto fail; 1150 } 1151 1152 sc->rl_btag = rman_get_bustag(sc->rl_res); 1153 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1154 1155 msic = 0; 1156 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1157 sc->rl_flags |= RL_FLAG_PCIE; 1158 if (devid != RT_DEVICEID_8101E) { 1159 /* Set PCIe maximum read request size to 2048. */ 1160 if (pci_get_max_read_req(dev) < 2048) 1161 pci_set_max_read_req(dev, 2048); 1162 } 1163 msic = pci_msi_count(dev); 1164 if (bootverbose) 1165 device_printf(dev, "MSI count : %d\n", msic); 1166 } 1167 if (msic > 0 && msi_disable == 0) { 1168 msic = 1; 1169 if (pci_alloc_msi(dev, &msic) == 0) { 1170 if (msic == RL_MSI_MESSAGES) { 1171 device_printf(dev, "Using %d MSI messages\n", 1172 msic); 1173 sc->rl_flags |= RL_FLAG_MSI; 1174 /* Explicitly set MSI enable bit. */ 1175 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1176 cfg = CSR_READ_1(sc, RL_CFG2); 1177 cfg |= RL_CFG2_MSI; 1178 CSR_WRITE_1(sc, RL_CFG2, cfg); 1179 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1180 } else 1181 pci_release_msi(dev); 1182 } 1183 } 1184 1185 /* Allocate interrupt */ 1186 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1187 rid = 0; 1188 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1189 RF_SHAREABLE | RF_ACTIVE); 1190 if (sc->rl_irq[0] == NULL) { 1191 device_printf(dev, "couldn't allocate IRQ resources\n"); 1192 error = ENXIO; 1193 goto fail; 1194 } 1195 } else { 1196 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1197 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1198 SYS_RES_IRQ, &rid, RF_ACTIVE); 1199 if (sc->rl_irq[i] == NULL) { 1200 device_printf(dev, 1201 "couldn't llocate IRQ resources for " 1202 "message %d\n", rid); 1203 error = ENXIO; 1204 goto fail; 1205 } 1206 } 1207 } 1208 1209 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1210 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1211 cfg = CSR_READ_1(sc, RL_CFG2); 1212 if ((cfg & RL_CFG2_MSI) != 0) { 1213 device_printf(dev, "turning off MSI enable bit.\n"); 1214 cfg &= ~RL_CFG2_MSI; 1215 CSR_WRITE_1(sc, RL_CFG2, cfg); 1216 } 1217 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1218 } 1219 1220 /* Reset the adapter. */ 1221 RL_LOCK(sc); 1222 re_reset(sc); 1223 RL_UNLOCK(sc); 1224 1225 hw_rev = re_hwrevs; 1226 hwrev = CSR_READ_4(sc, RL_TXCFG); 1227 switch (hwrev & 0x70000000) { 1228 case 0x00000000: 1229 case 0x10000000: 1230 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1231 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1232 break; 1233 default: 1234 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1235 hwrev &= RL_TXCFG_HWREV; 1236 break; 1237 } 1238 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1239 while (hw_rev->rl_desc != NULL) { 1240 if (hw_rev->rl_rev == hwrev) { 1241 sc->rl_type = hw_rev->rl_type; 1242 sc->rl_hwrev = hw_rev->rl_rev; 1243 break; 1244 } 1245 hw_rev++; 1246 } 1247 if (hw_rev->rl_desc == NULL) { 1248 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1249 error = ENXIO; 1250 goto fail; 1251 } 1252 1253 switch (hw_rev->rl_rev) { 1254 case RL_HWREV_8139CPLUS: 1255 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER | 1256 RL_FLAG_AUTOPAD; 1257 break; 1258 case RL_HWREV_8100E: 1259 case RL_HWREV_8101E: 1260 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1261 RL_FLAG_FASTETHER; 1262 break; 1263 case RL_HWREV_8102E: 1264 case RL_HWREV_8102EL: 1265 case RL_HWREV_8102EL_SPIN1: 1266 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1267 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1268 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1269 break; 1270 case RL_HWREV_8103E: 1271 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1272 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1273 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1274 RL_FLAG_MACSLEEP; 1275 break; 1276 case RL_HWREV_8168_SPIN1: 1277 case RL_HWREV_8168_SPIN2: 1278 sc->rl_flags |= RL_FLAG_WOLRXENB; 1279 /* FALLTHROUGH */ 1280 case RL_HWREV_8168_SPIN3: 1281 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1282 break; 1283 case RL_HWREV_8168C_SPIN2: 1284 sc->rl_flags |= RL_FLAG_MACSLEEP; 1285 /* FALLTHROUGH */ 1286 case RL_HWREV_8168C: 1287 if ((hwrev & 0x00700000) == 0x00200000) 1288 sc->rl_flags |= RL_FLAG_MACSLEEP; 1289 /* FALLTHROUGH */ 1290 case RL_HWREV_8168CP: 1291 case RL_HWREV_8168D: 1292 case RL_HWREV_8168DP: 1293 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1294 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1295 RL_FLAG_AUTOPAD; 1296 /* 1297 * These controllers support jumbo frame but it seems 1298 * that enabling it requires touching additional magic 1299 * registers. Depending on MAC revisions some 1300 * controllers need to disable checksum offload. So 1301 * disable jumbo frame until I have better idea what 1302 * it really requires to make it support. 1303 * RTL8168C/CP : supports up to 6KB jumbo frame. 1304 * RTL8111C/CP : supports up to 9KB jumbo frame. 1305 */ 1306 sc->rl_flags |= RL_FLAG_NOJUMBO; 1307 break; 1308 case RL_HWREV_8168E: 1309 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1310 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1311 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_NOJUMBO; 1312 break; 1313 case RL_HWREV_8169_8110SB: 1314 case RL_HWREV_8169_8110SBL: 1315 case RL_HWREV_8169_8110SC: 1316 case RL_HWREV_8169_8110SCE: 1317 sc->rl_flags |= RL_FLAG_PHYWAKE; 1318 /* FALLTHROUGH */ 1319 case RL_HWREV_8169: 1320 case RL_HWREV_8169S: 1321 case RL_HWREV_8110S: 1322 sc->rl_flags |= RL_FLAG_MACRESET; 1323 break; 1324 default: 1325 break; 1326 } 1327 1328 /* Enable PME. */ 1329 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1330 cfg = CSR_READ_1(sc, RL_CFG1); 1331 cfg |= RL_CFG1_PME; 1332 CSR_WRITE_1(sc, RL_CFG1, cfg); 1333 cfg = CSR_READ_1(sc, RL_CFG5); 1334 cfg &= RL_CFG5_PME_STS; 1335 CSR_WRITE_1(sc, RL_CFG5, cfg); 1336 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1337 1338 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1339 /* 1340 * XXX Should have a better way to extract station 1341 * address from EEPROM. 1342 */ 1343 for (i = 0; i < ETHER_ADDR_LEN; i++) 1344 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1345 } else { 1346 sc->rl_eewidth = RL_9356_ADDR_LEN; 1347 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1348 if (re_did != 0x8129) 1349 sc->rl_eewidth = RL_9346_ADDR_LEN; 1350 1351 /* 1352 * Get station address from the EEPROM. 1353 */ 1354 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1355 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1356 as[i] = le16toh(as[i]); 1357 bcopy(as, eaddr, sizeof(eaddr)); 1358 } 1359 1360 if (sc->rl_type == RL_8169) { 1361 /* Set RX length mask and number of descriptors. */ 1362 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1363 sc->rl_txstart = RL_GTXSTART; 1364 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1365 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1366 } else { 1367 /* Set RX length mask and number of descriptors. */ 1368 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1369 sc->rl_txstart = RL_TXSTART; 1370 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1371 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1372 } 1373 1374 error = re_allocmem(dev, sc); 1375 if (error) 1376 goto fail; 1377 1378 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1379 if (ifp == NULL) { 1380 device_printf(dev, "can not if_alloc()\n"); 1381 error = ENOSPC; 1382 goto fail; 1383 } 1384 1385 /* Take controller out of deep sleep mode. */ 1386 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1387 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1388 CSR_WRITE_1(sc, RL_GPIO, 1389 CSR_READ_1(sc, RL_GPIO) | 0x01); 1390 else 1391 CSR_WRITE_1(sc, RL_GPIO, 1392 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1393 } 1394 1395 /* Take PHY out of power down mode. */ 1396 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 1397 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1398 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1399 re_gmii_writereg(dev, 1, 0x1f, 0); 1400 re_gmii_writereg(dev, 1, 0x0e, 0); 1401 } 1402 1403#define RE_PHYAD_INTERNAL 0 1404 1405 /* Do MII setup. */ 1406 phy = RE_PHYAD_INTERNAL; 1407 if (sc->rl_type == RL_8169) 1408 phy = 1; 1409 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1410 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1411 if (error != 0) { 1412 device_printf(dev, "attaching PHYs failed\n"); 1413 goto fail; 1414 } 1415 1416 ifp->if_softc = sc; 1417 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1418 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1419 ifp->if_ioctl = re_ioctl; 1420 ifp->if_start = re_start; 1421 ifp->if_hwassist = RE_CSUM_FEATURES; 1422 ifp->if_capabilities = IFCAP_HWCSUM; 1423 ifp->if_capenable = ifp->if_capabilities; 1424 ifp->if_init = re_init; 1425 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1426 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1427 IFQ_SET_READY(&ifp->if_snd); 1428 1429 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1430 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1431 1432 /* 1433 * XXX 1434 * Still have no idea how to make TSO work on 8168C, 8168CP, 1435 * 8111C and 8111CP. 1436 */ 1437 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1438 ifp->if_hwassist |= CSUM_TSO; 1439 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 1440 } 1441 1442 /* 1443 * Call MI attach routine. 1444 */ 1445 ether_ifattach(ifp, eaddr); 1446 1447 /* VLAN capability setup */ 1448 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1449 if (ifp->if_capabilities & IFCAP_HWCSUM) 1450 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1451 /* Enable WOL if PM is supported. */ 1452 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1453 ifp->if_capabilities |= IFCAP_WOL; 1454 ifp->if_capenable = ifp->if_capabilities; 1455 /* 1456 * Don't enable TSO by default. Under certain 1457 * circumtances the controller generated corrupted 1458 * packets in TSO size. 1459 */ 1460 ifp->if_hwassist &= ~CSUM_TSO; 1461 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1462#ifdef DEVICE_POLLING 1463 ifp->if_capabilities |= IFCAP_POLLING; 1464#endif 1465 /* 1466 * Tell the upper layer(s) we support long frames. 1467 * Must appear after the call to ether_ifattach() because 1468 * ether_ifattach() sets ifi_hdrlen to the default value. 1469 */ 1470 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1471 1472#ifdef RE_DIAG 1473 /* 1474 * Perform hardware diagnostic on the original RTL8169. 1475 * Some 32-bit cards were incorrectly wired and would 1476 * malfunction if plugged into a 64-bit slot. 1477 */ 1478 1479 if (hwrev == RL_HWREV_8169) { 1480 error = re_diag(sc); 1481 if (error) { 1482 device_printf(dev, 1483 "attach aborted due to hardware diag failure\n"); 1484 ether_ifdetach(ifp); 1485 goto fail; 1486 } 1487 } 1488#endif 1489 1490 /* Hook interrupt last to avoid having to lock softc */ 1491 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1492 error = bus_setup_intr(dev, sc->rl_irq[0], 1493 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1494 &sc->rl_intrhand[0]); 1495 else { 1496 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1497 error = bus_setup_intr(dev, sc->rl_irq[i], 1498 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1499 &sc->rl_intrhand[i]); 1500 if (error != 0) 1501 break; 1502 } 1503 } 1504 if (error) { 1505 device_printf(dev, "couldn't set up irq\n"); 1506 ether_ifdetach(ifp); 1507 } 1508 1509fail: 1510 1511 if (error) 1512 re_detach(dev); 1513 1514 return (error); 1515} 1516 1517/* 1518 * Shutdown hardware and free up resources. This can be called any 1519 * time after the mutex has been initialized. It is called in both 1520 * the error case in attach and the normal detach case so it needs 1521 * to be careful about only freeing resources that have actually been 1522 * allocated. 1523 */ 1524static int 1525re_detach(device_t dev) 1526{ 1527 struct rl_softc *sc; 1528 struct ifnet *ifp; 1529 int i, rid; 1530 1531 sc = device_get_softc(dev); 1532 ifp = sc->rl_ifp; 1533 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1534 1535 /* These should only be active if attach succeeded */ 1536 if (device_is_attached(dev)) { 1537#ifdef DEVICE_POLLING 1538 if (ifp->if_capenable & IFCAP_POLLING) 1539 ether_poll_deregister(ifp); 1540#endif 1541 RL_LOCK(sc); 1542#if 0 1543 sc->suspended = 1; 1544#endif 1545 re_stop(sc); 1546 RL_UNLOCK(sc); 1547 callout_drain(&sc->rl_stat_callout); 1548 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1549 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1550 /* 1551 * Force off the IFF_UP flag here, in case someone 1552 * still had a BPF descriptor attached to this 1553 * interface. If they do, ether_ifdetach() will cause 1554 * the BPF code to try and clear the promisc mode 1555 * flag, which will bubble down to re_ioctl(), 1556 * which will try to call re_init() again. This will 1557 * turn the NIC back on and restart the MII ticker, 1558 * which will panic the system when the kernel tries 1559 * to invoke the re_tick() function that isn't there 1560 * anymore. 1561 */ 1562 ifp->if_flags &= ~IFF_UP; 1563 ether_ifdetach(ifp); 1564 } 1565 if (sc->rl_miibus) 1566 device_delete_child(dev, sc->rl_miibus); 1567 bus_generic_detach(dev); 1568 1569 /* 1570 * The rest is resource deallocation, so we should already be 1571 * stopped here. 1572 */ 1573 1574 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1575 if (sc->rl_intrhand[i] != NULL) { 1576 bus_teardown_intr(dev, sc->rl_irq[i], 1577 sc->rl_intrhand[i]); 1578 sc->rl_intrhand[i] = NULL; 1579 } 1580 } 1581 if (ifp != NULL) 1582 if_free(ifp); 1583 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1584 if (sc->rl_irq[0] != NULL) { 1585 bus_release_resource(dev, SYS_RES_IRQ, 0, 1586 sc->rl_irq[0]); 1587 sc->rl_irq[0] = NULL; 1588 } 1589 } else { 1590 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1591 if (sc->rl_irq[i] != NULL) { 1592 bus_release_resource(dev, SYS_RES_IRQ, rid, 1593 sc->rl_irq[i]); 1594 sc->rl_irq[i] = NULL; 1595 } 1596 } 1597 pci_release_msi(dev); 1598 } 1599 if (sc->rl_res) 1600 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1601 sc->rl_res); 1602 1603 /* Unload and free the RX DMA ring memory and map */ 1604 1605 if (sc->rl_ldata.rl_rx_list_tag) { 1606 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1607 sc->rl_ldata.rl_rx_list_map); 1608 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1609 sc->rl_ldata.rl_rx_list, 1610 sc->rl_ldata.rl_rx_list_map); 1611 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1612 } 1613 1614 /* Unload and free the TX DMA ring memory and map */ 1615 1616 if (sc->rl_ldata.rl_tx_list_tag) { 1617 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1618 sc->rl_ldata.rl_tx_list_map); 1619 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1620 sc->rl_ldata.rl_tx_list, 1621 sc->rl_ldata.rl_tx_list_map); 1622 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1623 } 1624 1625 /* Destroy all the RX and TX buffer maps */ 1626 1627 if (sc->rl_ldata.rl_tx_mtag) { 1628 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1629 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1630 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1631 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1632 } 1633 if (sc->rl_ldata.rl_rx_mtag) { 1634 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1635 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1636 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1637 if (sc->rl_ldata.rl_rx_sparemap) 1638 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1639 sc->rl_ldata.rl_rx_sparemap); 1640 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1641 } 1642 1643 /* Unload and free the stats buffer and map */ 1644 1645 if (sc->rl_ldata.rl_stag) { 1646 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1647 sc->rl_ldata.rl_rx_list_map); 1648 bus_dmamem_free(sc->rl_ldata.rl_stag, 1649 sc->rl_ldata.rl_stats, 1650 sc->rl_ldata.rl_smap); 1651 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1652 } 1653 1654 if (sc->rl_parent_tag) 1655 bus_dma_tag_destroy(sc->rl_parent_tag); 1656 1657 mtx_destroy(&sc->rl_mtx); 1658 1659 return (0); 1660} 1661 1662static __inline void 1663re_discard_rxbuf(struct rl_softc *sc, int idx) 1664{ 1665 struct rl_desc *desc; 1666 struct rl_rxdesc *rxd; 1667 uint32_t cmdstat; 1668 1669 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1670 desc = &sc->rl_ldata.rl_rx_list[idx]; 1671 desc->rl_vlanctl = 0; 1672 cmdstat = rxd->rx_size; 1673 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1674 cmdstat |= RL_RDESC_CMD_EOR; 1675 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1676} 1677 1678static int 1679re_newbuf(struct rl_softc *sc, int idx) 1680{ 1681 struct mbuf *m; 1682 struct rl_rxdesc *rxd; 1683 bus_dma_segment_t segs[1]; 1684 bus_dmamap_t map; 1685 struct rl_desc *desc; 1686 uint32_t cmdstat; 1687 int error, nsegs; 1688 1689 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1690 if (m == NULL) 1691 return (ENOBUFS); 1692 1693 m->m_len = m->m_pkthdr.len = MCLBYTES; 1694#ifdef RE_FIXUP_RX 1695 /* 1696 * This is part of an evil trick to deal with non-x86 platforms. 1697 * The RealTek chip requires RX buffers to be aligned on 64-bit 1698 * boundaries, but that will hose non-x86 machines. To get around 1699 * this, we leave some empty space at the start of each buffer 1700 * and for non-x86 hosts, we copy the buffer back six bytes 1701 * to achieve word alignment. This is slightly more efficient 1702 * than allocating a new buffer, copying the contents, and 1703 * discarding the old buffer. 1704 */ 1705 m_adj(m, RE_ETHER_ALIGN); 1706#endif 1707 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1708 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1709 if (error != 0) { 1710 m_freem(m); 1711 return (ENOBUFS); 1712 } 1713 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1714 1715 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1716 if (rxd->rx_m != NULL) { 1717 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1718 BUS_DMASYNC_POSTREAD); 1719 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1720 } 1721 1722 rxd->rx_m = m; 1723 map = rxd->rx_dmamap; 1724 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1725 rxd->rx_size = segs[0].ds_len; 1726 sc->rl_ldata.rl_rx_sparemap = map; 1727 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1728 BUS_DMASYNC_PREREAD); 1729 1730 desc = &sc->rl_ldata.rl_rx_list[idx]; 1731 desc->rl_vlanctl = 0; 1732 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1733 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1734 cmdstat = segs[0].ds_len; 1735 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1736 cmdstat |= RL_RDESC_CMD_EOR; 1737 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1738 1739 return (0); 1740} 1741 1742#ifdef RE_FIXUP_RX 1743static __inline void 1744re_fixup_rx(struct mbuf *m) 1745{ 1746 int i; 1747 uint16_t *src, *dst; 1748 1749 src = mtod(m, uint16_t *); 1750 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1751 1752 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1753 *dst++ = *src++; 1754 1755 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1756} 1757#endif 1758 1759static int 1760re_tx_list_init(struct rl_softc *sc) 1761{ 1762 struct rl_desc *desc; 1763 int i; 1764 1765 RL_LOCK_ASSERT(sc); 1766 1767 bzero(sc->rl_ldata.rl_tx_list, 1768 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1769 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1770 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1771 /* Set EOR. */ 1772 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1773 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1774 1775 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1776 sc->rl_ldata.rl_tx_list_map, 1777 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1778 1779 sc->rl_ldata.rl_tx_prodidx = 0; 1780 sc->rl_ldata.rl_tx_considx = 0; 1781 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1782 1783 return (0); 1784} 1785 1786static int 1787re_rx_list_init(struct rl_softc *sc) 1788{ 1789 int error, i; 1790 1791 bzero(sc->rl_ldata.rl_rx_list, 1792 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1793 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1794 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1795 if ((error = re_newbuf(sc, i)) != 0) 1796 return (error); 1797 } 1798 1799 /* Flush the RX descriptors */ 1800 1801 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1802 sc->rl_ldata.rl_rx_list_map, 1803 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1804 1805 sc->rl_ldata.rl_rx_prodidx = 0; 1806 sc->rl_head = sc->rl_tail = NULL; 1807 1808 return (0); 1809} 1810 1811/* 1812 * RX handler for C+ and 8169. For the gigE chips, we support 1813 * the reception of jumbo frames that have been fragmented 1814 * across multiple 2K mbuf cluster buffers. 1815 */ 1816static int 1817re_rxeof(struct rl_softc *sc, int *rx_npktsp) 1818{ 1819 struct mbuf *m; 1820 struct ifnet *ifp; 1821 int i, total_len; 1822 struct rl_desc *cur_rx; 1823 u_int32_t rxstat, rxvlan; 1824 int maxpkt = 16, rx_npkts = 0; 1825 1826 RL_LOCK_ASSERT(sc); 1827 1828 ifp = sc->rl_ifp; 1829 1830 /* Invalidate the descriptor memory */ 1831 1832 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1833 sc->rl_ldata.rl_rx_list_map, 1834 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1835 1836 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1837 i = RL_RX_DESC_NXT(sc, i)) { 1838 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1839 break; 1840 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1841 rxstat = le32toh(cur_rx->rl_cmdstat); 1842 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1843 break; 1844 total_len = rxstat & sc->rl_rxlenmask; 1845 rxvlan = le32toh(cur_rx->rl_vlanctl); 1846 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1847 1848 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1849 if (re_newbuf(sc, i) != 0) { 1850 /* 1851 * If this is part of a multi-fragment packet, 1852 * discard all the pieces. 1853 */ 1854 if (sc->rl_head != NULL) { 1855 m_freem(sc->rl_head); 1856 sc->rl_head = sc->rl_tail = NULL; 1857 } 1858 re_discard_rxbuf(sc, i); 1859 continue; 1860 } 1861 m->m_len = RE_RX_DESC_BUFLEN; 1862 if (sc->rl_head == NULL) 1863 sc->rl_head = sc->rl_tail = m; 1864 else { 1865 m->m_flags &= ~M_PKTHDR; 1866 sc->rl_tail->m_next = m; 1867 sc->rl_tail = m; 1868 } 1869 continue; 1870 } 1871 1872 /* 1873 * NOTE: for the 8139C+, the frame length field 1874 * is always 12 bits in size, but for the gigE chips, 1875 * it is 13 bits (since the max RX frame length is 16K). 1876 * Unfortunately, all 32 bits in the status word 1877 * were already used, so to make room for the extra 1878 * length bit, RealTek took out the 'frame alignment 1879 * error' bit and shifted the other status bits 1880 * over one slot. The OWN, EOR, FS and LS bits are 1881 * still in the same places. We have already extracted 1882 * the frame length and checked the OWN bit, so rather 1883 * than using an alternate bit mapping, we shift the 1884 * status bits one space to the right so we can evaluate 1885 * them using the 8169 status as though it was in the 1886 * same format as that of the 8139C+. 1887 */ 1888 if (sc->rl_type == RL_8169) 1889 rxstat >>= 1; 1890 1891 /* 1892 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1893 * set, but if CRC is clear, it will still be a valid frame. 1894 */ 1895 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1896 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1897 ifp->if_ierrors++; 1898 /* 1899 * If this is part of a multi-fragment packet, 1900 * discard all the pieces. 1901 */ 1902 if (sc->rl_head != NULL) { 1903 m_freem(sc->rl_head); 1904 sc->rl_head = sc->rl_tail = NULL; 1905 } 1906 re_discard_rxbuf(sc, i); 1907 continue; 1908 } 1909 1910 /* 1911 * If allocating a replacement mbuf fails, 1912 * reload the current one. 1913 */ 1914 1915 if (re_newbuf(sc, i) != 0) { 1916 ifp->if_iqdrops++; 1917 if (sc->rl_head != NULL) { 1918 m_freem(sc->rl_head); 1919 sc->rl_head = sc->rl_tail = NULL; 1920 } 1921 re_discard_rxbuf(sc, i); 1922 continue; 1923 } 1924 1925 if (sc->rl_head != NULL) { 1926 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1927 if (m->m_len == 0) 1928 m->m_len = RE_RX_DESC_BUFLEN; 1929 /* 1930 * Special case: if there's 4 bytes or less 1931 * in this buffer, the mbuf can be discarded: 1932 * the last 4 bytes is the CRC, which we don't 1933 * care about anyway. 1934 */ 1935 if (m->m_len <= ETHER_CRC_LEN) { 1936 sc->rl_tail->m_len -= 1937 (ETHER_CRC_LEN - m->m_len); 1938 m_freem(m); 1939 } else { 1940 m->m_len -= ETHER_CRC_LEN; 1941 m->m_flags &= ~M_PKTHDR; 1942 sc->rl_tail->m_next = m; 1943 } 1944 m = sc->rl_head; 1945 sc->rl_head = sc->rl_tail = NULL; 1946 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1947 } else 1948 m->m_pkthdr.len = m->m_len = 1949 (total_len - ETHER_CRC_LEN); 1950 1951#ifdef RE_FIXUP_RX 1952 re_fixup_rx(m); 1953#endif 1954 ifp->if_ipackets++; 1955 m->m_pkthdr.rcvif = ifp; 1956 1957 /* Do RX checksumming if enabled */ 1958 1959 if (ifp->if_capenable & IFCAP_RXCSUM) { 1960 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1961 /* Check IP header checksum */ 1962 if (rxstat & RL_RDESC_STAT_PROTOID) 1963 m->m_pkthdr.csum_flags |= 1964 CSUM_IP_CHECKED; 1965 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1966 m->m_pkthdr.csum_flags |= 1967 CSUM_IP_VALID; 1968 1969 /* Check TCP/UDP checksum */ 1970 if ((RL_TCPPKT(rxstat) && 1971 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1972 (RL_UDPPKT(rxstat) && 1973 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1974 m->m_pkthdr.csum_flags |= 1975 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1976 m->m_pkthdr.csum_data = 0xffff; 1977 } 1978 } else { 1979 /* 1980 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1981 */ 1982 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1983 (rxvlan & RL_RDESC_IPV4)) 1984 m->m_pkthdr.csum_flags |= 1985 CSUM_IP_CHECKED; 1986 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1987 (rxvlan & RL_RDESC_IPV4)) 1988 m->m_pkthdr.csum_flags |= 1989 CSUM_IP_VALID; 1990 if (((rxstat & RL_RDESC_STAT_TCP) && 1991 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1992 ((rxstat & RL_RDESC_STAT_UDP) && 1993 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1994 m->m_pkthdr.csum_flags |= 1995 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1996 m->m_pkthdr.csum_data = 0xffff; 1997 } 1998 } 1999 } 2000 maxpkt--; 2001 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2002 m->m_pkthdr.ether_vtag = 2003 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2004 m->m_flags |= M_VLANTAG; 2005 } 2006 RL_UNLOCK(sc); 2007 (*ifp->if_input)(ifp, m); 2008 RL_LOCK(sc); 2009 rx_npkts++; 2010 } 2011 2012 /* Flush the RX DMA ring */ 2013 2014 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2015 sc->rl_ldata.rl_rx_list_map, 2016 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2017 2018 sc->rl_ldata.rl_rx_prodidx = i; 2019 2020 if (rx_npktsp != NULL) 2021 *rx_npktsp = rx_npkts; 2022 if (maxpkt) 2023 return (EAGAIN); 2024 2025 return (0); 2026} 2027 2028static void 2029re_txeof(struct rl_softc *sc) 2030{ 2031 struct ifnet *ifp; 2032 struct rl_txdesc *txd; 2033 u_int32_t txstat; 2034 int cons; 2035 2036 cons = sc->rl_ldata.rl_tx_considx; 2037 if (cons == sc->rl_ldata.rl_tx_prodidx) 2038 return; 2039 2040 ifp = sc->rl_ifp; 2041 /* Invalidate the TX descriptor list */ 2042 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2043 sc->rl_ldata.rl_tx_list_map, 2044 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2045 2046 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2047 cons = RL_TX_DESC_NXT(sc, cons)) { 2048 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2049 if (txstat & RL_TDESC_STAT_OWN) 2050 break; 2051 /* 2052 * We only stash mbufs in the last descriptor 2053 * in a fragment chain, which also happens to 2054 * be the only place where the TX status bits 2055 * are valid. 2056 */ 2057 if (txstat & RL_TDESC_CMD_EOF) { 2058 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2059 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2060 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2061 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2062 txd->tx_dmamap); 2063 KASSERT(txd->tx_m != NULL, 2064 ("%s: freeing NULL mbufs!", __func__)); 2065 m_freem(txd->tx_m); 2066 txd->tx_m = NULL; 2067 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2068 RL_TDESC_STAT_COLCNT)) 2069 ifp->if_collisions++; 2070 if (txstat & RL_TDESC_STAT_TXERRSUM) 2071 ifp->if_oerrors++; 2072 else 2073 ifp->if_opackets++; 2074 } 2075 sc->rl_ldata.rl_tx_free++; 2076 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2077 } 2078 sc->rl_ldata.rl_tx_considx = cons; 2079 2080 /* No changes made to the TX ring, so no flush needed */ 2081 2082 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2083#ifdef RE_TX_MODERATION 2084 /* 2085 * If not all descriptors have been reaped yet, reload 2086 * the timer so that we will eventually get another 2087 * interrupt that will cause us to re-enter this routine. 2088 * This is done in case the transmitter has gone idle. 2089 */ 2090 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2091#endif 2092 } else 2093 sc->rl_watchdog_timer = 0; 2094} 2095 2096static void 2097re_tick(void *xsc) 2098{ 2099 struct rl_softc *sc; 2100 struct mii_data *mii; 2101 2102 sc = xsc; 2103 2104 RL_LOCK_ASSERT(sc); 2105 2106 mii = device_get_softc(sc->rl_miibus); 2107 mii_tick(mii); 2108 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2109 re_miibus_statchg(sc->rl_dev); 2110 /* 2111 * Reclaim transmitted frames here. Technically it is not 2112 * necessary to do here but it ensures periodic reclamation 2113 * regardless of Tx completion interrupt which seems to be 2114 * lost on PCIe based controllers under certain situations. 2115 */ 2116 re_txeof(sc); 2117 re_watchdog(sc); 2118 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2119} 2120 2121#ifdef DEVICE_POLLING 2122static int 2123re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2124{ 2125 struct rl_softc *sc = ifp->if_softc; 2126 int rx_npkts = 0; 2127 2128 RL_LOCK(sc); 2129 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2130 rx_npkts = re_poll_locked(ifp, cmd, count); 2131 RL_UNLOCK(sc); 2132 return (rx_npkts); 2133} 2134 2135static int 2136re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2137{ 2138 struct rl_softc *sc = ifp->if_softc; 2139 int rx_npkts; 2140 2141 RL_LOCK_ASSERT(sc); 2142 2143 sc->rxcycles = count; 2144 re_rxeof(sc, &rx_npkts); 2145 re_txeof(sc); 2146 2147 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2148 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2149 2150 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2151 u_int16_t status; 2152 2153 status = CSR_READ_2(sc, RL_ISR); 2154 if (status == 0xffff) 2155 return (rx_npkts); 2156 if (status) 2157 CSR_WRITE_2(sc, RL_ISR, status); 2158 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2159 (sc->rl_flags & RL_FLAG_PCIE)) 2160 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2161 2162 /* 2163 * XXX check behaviour on receiver stalls. 2164 */ 2165 2166 if (status & RL_ISR_SYSTEM_ERR) { 2167 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2168 re_init_locked(sc); 2169 } 2170 } 2171 return (rx_npkts); 2172} 2173#endif /* DEVICE_POLLING */ 2174 2175static int 2176re_intr(void *arg) 2177{ 2178 struct rl_softc *sc; 2179 uint16_t status; 2180 2181 sc = arg; 2182 2183 status = CSR_READ_2(sc, RL_ISR); 2184 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2185 return (FILTER_STRAY); 2186 CSR_WRITE_2(sc, RL_IMR, 0); 2187 2188 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2189 2190 return (FILTER_HANDLED); 2191} 2192 2193static void 2194re_int_task(void *arg, int npending) 2195{ 2196 struct rl_softc *sc; 2197 struct ifnet *ifp; 2198 u_int16_t status; 2199 int rval = 0; 2200 2201 sc = arg; 2202 ifp = sc->rl_ifp; 2203 2204 RL_LOCK(sc); 2205 2206 status = CSR_READ_2(sc, RL_ISR); 2207 CSR_WRITE_2(sc, RL_ISR, status); 2208 2209 if (sc->suspended || 2210 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2211 RL_UNLOCK(sc); 2212 return; 2213 } 2214 2215#ifdef DEVICE_POLLING 2216 if (ifp->if_capenable & IFCAP_POLLING) { 2217 RL_UNLOCK(sc); 2218 return; 2219 } 2220#endif 2221 2222 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2223 rval = re_rxeof(sc, NULL); 2224 2225 /* 2226 * Some chips will ignore a second TX request issued 2227 * while an existing transmission is in progress. If 2228 * the transmitter goes idle but there are still 2229 * packets waiting to be sent, we need to restart the 2230 * channel here to flush them out. This only seems to 2231 * be required with the PCIe devices. 2232 */ 2233 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2234 (sc->rl_flags & RL_FLAG_PCIE)) 2235 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2236 if (status & ( 2237#ifdef RE_TX_MODERATION 2238 RL_ISR_TIMEOUT_EXPIRED| 2239#else 2240 RL_ISR_TX_OK| 2241#endif 2242 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2243 re_txeof(sc); 2244 2245 if (status & RL_ISR_SYSTEM_ERR) { 2246 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2247 re_init_locked(sc); 2248 } 2249 2250 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2251 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2252 2253 RL_UNLOCK(sc); 2254 2255 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2256 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2257 return; 2258 } 2259 2260 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2261} 2262 2263static int 2264re_encap(struct rl_softc *sc, struct mbuf **m_head) 2265{ 2266 struct rl_txdesc *txd, *txd_last; 2267 bus_dma_segment_t segs[RL_NTXSEGS]; 2268 bus_dmamap_t map; 2269 struct mbuf *m_new; 2270 struct rl_desc *desc; 2271 int nsegs, prod; 2272 int i, error, ei, si; 2273 int padlen; 2274 uint32_t cmdstat, csum_flags, vlanctl; 2275 2276 RL_LOCK_ASSERT(sc); 2277 M_ASSERTPKTHDR((*m_head)); 2278 2279 /* 2280 * With some of the RealTek chips, using the checksum offload 2281 * support in conjunction with the autopadding feature results 2282 * in the transmission of corrupt frames. For example, if we 2283 * need to send a really small IP fragment that's less than 60 2284 * bytes in size, and IP header checksumming is enabled, the 2285 * resulting ethernet frame that appears on the wire will 2286 * have garbled payload. To work around this, if TX IP checksum 2287 * offload is enabled, we always manually pad short frames out 2288 * to the minimum ethernet frame size. 2289 */ 2290 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2291 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2292 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2293 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2294 if (M_WRITABLE(*m_head) == 0) { 2295 /* Get a writable copy. */ 2296 m_new = m_dup(*m_head, M_DONTWAIT); 2297 m_freem(*m_head); 2298 if (m_new == NULL) { 2299 *m_head = NULL; 2300 return (ENOBUFS); 2301 } 2302 *m_head = m_new; 2303 } 2304 if ((*m_head)->m_next != NULL || 2305 M_TRAILINGSPACE(*m_head) < padlen) { 2306 m_new = m_defrag(*m_head, M_DONTWAIT); 2307 if (m_new == NULL) { 2308 m_freem(*m_head); 2309 *m_head = NULL; 2310 return (ENOBUFS); 2311 } 2312 } else 2313 m_new = *m_head; 2314 2315 /* 2316 * Manually pad short frames, and zero the pad space 2317 * to avoid leaking data. 2318 */ 2319 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2320 m_new->m_pkthdr.len += padlen; 2321 m_new->m_len = m_new->m_pkthdr.len; 2322 *m_head = m_new; 2323 } 2324 2325 prod = sc->rl_ldata.rl_tx_prodidx; 2326 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2327 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2328 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2329 if (error == EFBIG) { 2330 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2331 if (m_new == NULL) { 2332 m_freem(*m_head); 2333 *m_head = NULL; 2334 return (ENOBUFS); 2335 } 2336 *m_head = m_new; 2337 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2338 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2339 if (error != 0) { 2340 m_freem(*m_head); 2341 *m_head = NULL; 2342 return (error); 2343 } 2344 } else if (error != 0) 2345 return (error); 2346 if (nsegs == 0) { 2347 m_freem(*m_head); 2348 *m_head = NULL; 2349 return (EIO); 2350 } 2351 2352 /* Check for number of available descriptors. */ 2353 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2354 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2355 return (ENOBUFS); 2356 } 2357 2358 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2359 BUS_DMASYNC_PREWRITE); 2360 2361 /* 2362 * Set up checksum offload. Note: checksum offload bits must 2363 * appear in all descriptors of a multi-descriptor transmit 2364 * attempt. This is according to testing done with an 8169 2365 * chip. This is a requirement. 2366 */ 2367 vlanctl = 0; 2368 csum_flags = 0; 2369 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2370 csum_flags = RL_TDESC_CMD_LGSEND | 2371 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2372 RL_TDESC_CMD_MSSVAL_SHIFT); 2373 else { 2374 /* 2375 * Unconditionally enable IP checksum if TCP or UDP 2376 * checksum is required. Otherwise, TCP/UDP checksum 2377 * does't make effects. 2378 */ 2379 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2380 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2381 csum_flags |= RL_TDESC_CMD_IPCSUM; 2382 if (((*m_head)->m_pkthdr.csum_flags & 2383 CSUM_TCP) != 0) 2384 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2385 if (((*m_head)->m_pkthdr.csum_flags & 2386 CSUM_UDP) != 0) 2387 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2388 } else { 2389 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2390 if (((*m_head)->m_pkthdr.csum_flags & 2391 CSUM_TCP) != 0) 2392 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2393 if (((*m_head)->m_pkthdr.csum_flags & 2394 CSUM_UDP) != 0) 2395 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2396 } 2397 } 2398 } 2399 2400 /* 2401 * Set up hardware VLAN tagging. Note: vlan tag info must 2402 * appear in all descriptors of a multi-descriptor 2403 * transmission attempt. 2404 */ 2405 if ((*m_head)->m_flags & M_VLANTAG) 2406 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2407 RL_TDESC_VLANCTL_TAG; 2408 2409 si = prod; 2410 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2411 desc = &sc->rl_ldata.rl_tx_list[prod]; 2412 desc->rl_vlanctl = htole32(vlanctl); 2413 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2414 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2415 cmdstat = segs[i].ds_len; 2416 if (i != 0) 2417 cmdstat |= RL_TDESC_CMD_OWN; 2418 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2419 cmdstat |= RL_TDESC_CMD_EOR; 2420 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2421 sc->rl_ldata.rl_tx_free--; 2422 } 2423 /* Update producer index. */ 2424 sc->rl_ldata.rl_tx_prodidx = prod; 2425 2426 /* Set EOF on the last descriptor. */ 2427 ei = RL_TX_DESC_PRV(sc, prod); 2428 desc = &sc->rl_ldata.rl_tx_list[ei]; 2429 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2430 2431 desc = &sc->rl_ldata.rl_tx_list[si]; 2432 /* Set SOF and transfer ownership of packet to the chip. */ 2433 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2434 2435 /* 2436 * Insure that the map for this transmission 2437 * is placed at the array index of the last descriptor 2438 * in this chain. (Swap last and first dmamaps.) 2439 */ 2440 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2441 map = txd->tx_dmamap; 2442 txd->tx_dmamap = txd_last->tx_dmamap; 2443 txd_last->tx_dmamap = map; 2444 txd_last->tx_m = *m_head; 2445 2446 return (0); 2447} 2448 2449static void 2450re_tx_task(void *arg, int npending) 2451{ 2452 struct ifnet *ifp; 2453 2454 ifp = arg; 2455 re_start(ifp); 2456} 2457 2458/* 2459 * Main transmit routine for C+ and gigE NICs. 2460 */ 2461static void 2462re_start(struct ifnet *ifp) 2463{ 2464 struct rl_softc *sc; 2465 struct mbuf *m_head; 2466 int queued; 2467 2468 sc = ifp->if_softc; 2469 2470 RL_LOCK(sc); 2471 2472 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2473 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2474 RL_UNLOCK(sc); 2475 return; 2476 } 2477 2478 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2479 sc->rl_ldata.rl_tx_free > 1;) { 2480 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2481 if (m_head == NULL) 2482 break; 2483 2484 if (re_encap(sc, &m_head) != 0) { 2485 if (m_head == NULL) 2486 break; 2487 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2488 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2489 break; 2490 } 2491 2492 /* 2493 * If there's a BPF listener, bounce a copy of this frame 2494 * to him. 2495 */ 2496 ETHER_BPF_MTAP(ifp, m_head); 2497 2498 queued++; 2499 } 2500 2501 if (queued == 0) { 2502#ifdef RE_TX_MODERATION 2503 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2504 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2505#endif 2506 RL_UNLOCK(sc); 2507 return; 2508 } 2509 2510 /* Flush the TX descriptors */ 2511 2512 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2513 sc->rl_ldata.rl_tx_list_map, 2514 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2515 2516 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2517 2518#ifdef RE_TX_MODERATION 2519 /* 2520 * Use the countdown timer for interrupt moderation. 2521 * 'TX done' interrupts are disabled. Instead, we reset the 2522 * countdown timer, which will begin counting until it hits 2523 * the value in the TIMERINT register, and then trigger an 2524 * interrupt. Each time we write to the TIMERCNT register, 2525 * the timer count is reset to 0. 2526 */ 2527 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2528#endif 2529 2530 /* 2531 * Set a timeout in case the chip goes out to lunch. 2532 */ 2533 sc->rl_watchdog_timer = 5; 2534 2535 RL_UNLOCK(sc); 2536} 2537 2538static void 2539re_init(void *xsc) 2540{ 2541 struct rl_softc *sc = xsc; 2542 2543 RL_LOCK(sc); 2544 re_init_locked(sc); 2545 RL_UNLOCK(sc); 2546} 2547 2548static void 2549re_init_locked(struct rl_softc *sc) 2550{ 2551 struct ifnet *ifp = sc->rl_ifp; 2552 struct mii_data *mii; 2553 uint32_t reg; 2554 uint16_t cfg; 2555 union { 2556 uint32_t align_dummy; 2557 u_char eaddr[ETHER_ADDR_LEN]; 2558 } eaddr; 2559 2560 RL_LOCK_ASSERT(sc); 2561 2562 mii = device_get_softc(sc->rl_miibus); 2563 2564 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2565 return; 2566 2567 /* 2568 * Cancel pending I/O and free all RX/TX buffers. 2569 */ 2570 re_stop(sc); 2571 2572 /* Put controller into known state. */ 2573 re_reset(sc); 2574 2575 /* 2576 * Enable C+ RX and TX mode, as well as VLAN stripping and 2577 * RX checksum offload. We must configure the C+ register 2578 * before all others. 2579 */ 2580 cfg = RL_CPLUSCMD_PCI_MRW; 2581 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2582 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2583 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2584 cfg |= RL_CPLUSCMD_VLANSTRIP; 2585 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2586 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2587 /* XXX magic. */ 2588 cfg |= 0x0001; 2589 } else 2590 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2591 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2592 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2593 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2594 reg = 0x000fff00; 2595 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2596 reg |= 0x000000ff; 2597 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2598 reg |= 0x00f00000; 2599 CSR_WRITE_4(sc, 0x7c, reg); 2600 /* Disable interrupt mitigation. */ 2601 CSR_WRITE_2(sc, 0xe2, 0); 2602 } 2603 /* 2604 * Disable TSO if interface MTU size is greater than MSS 2605 * allowed in controller. 2606 */ 2607 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2608 ifp->if_capenable &= ~IFCAP_TSO4; 2609 ifp->if_hwassist &= ~CSUM_TSO; 2610 } 2611 2612 /* 2613 * Init our MAC address. Even though the chipset 2614 * documentation doesn't mention it, we need to enter "Config 2615 * register write enable" mode to modify the ID registers. 2616 */ 2617 /* Copy MAC address on stack to align. */ 2618 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2619 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2620 CSR_WRITE_4(sc, RL_IDR0, 2621 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2622 CSR_WRITE_4(sc, RL_IDR4, 2623 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2624 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2625 2626 /* 2627 * For C+ mode, initialize the RX descriptors and mbufs. 2628 */ 2629 re_rx_list_init(sc); 2630 re_tx_list_init(sc); 2631 2632 /* 2633 * Load the addresses of the RX and TX lists into the chip. 2634 */ 2635 2636 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2637 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2638 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2639 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2640 2641 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2642 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2643 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2644 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2645 2646 /* 2647 * Enable transmit and receive. 2648 */ 2649 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2650 2651 /* 2652 * Set the initial TX configuration. 2653 */ 2654 if (sc->rl_testmode) { 2655 if (sc->rl_type == RL_8169) 2656 CSR_WRITE_4(sc, RL_TXCFG, 2657 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2658 else 2659 CSR_WRITE_4(sc, RL_TXCFG, 2660 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2661 } else 2662 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2663 2664 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2665 2666 /* 2667 * Set the initial RX configuration. 2668 */ 2669 re_set_rxmode(sc); 2670 2671#ifdef DEVICE_POLLING 2672 /* 2673 * Disable interrupts if we are polling. 2674 */ 2675 if (ifp->if_capenable & IFCAP_POLLING) 2676 CSR_WRITE_2(sc, RL_IMR, 0); 2677 else /* otherwise ... */ 2678#endif 2679 2680 /* 2681 * Enable interrupts. 2682 */ 2683 if (sc->rl_testmode) 2684 CSR_WRITE_2(sc, RL_IMR, 0); 2685 else 2686 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2687 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2688 2689 /* Set initial TX threshold */ 2690 sc->rl_txthresh = RL_TX_THRESH_INIT; 2691 2692 /* Start RX/TX process. */ 2693 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2694#ifdef notdef 2695 /* Enable receiver and transmitter. */ 2696 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2697#endif 2698 2699#ifdef RE_TX_MODERATION 2700 /* 2701 * Initialize the timer interrupt register so that 2702 * a timer interrupt will be generated once the timer 2703 * reaches a certain number of ticks. The timer is 2704 * reloaded on each transmit. This gives us TX interrupt 2705 * moderation, which dramatically improves TX frame rate. 2706 */ 2707 if (sc->rl_type == RL_8169) 2708 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2709 else 2710 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2711#endif 2712 2713 /* 2714 * For 8169 gigE NICs, set the max allowed RX packet 2715 * size so we can receive jumbo frames. 2716 */ 2717 if (sc->rl_type == RL_8169) 2718 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2719 2720 if (sc->rl_testmode) 2721 return; 2722 2723 mii_mediachg(mii); 2724 2725 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2726 2727 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2728 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2729 2730 sc->rl_flags &= ~RL_FLAG_LINK; 2731 sc->rl_watchdog_timer = 0; 2732 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2733} 2734 2735/* 2736 * Set media options. 2737 */ 2738static int 2739re_ifmedia_upd(struct ifnet *ifp) 2740{ 2741 struct rl_softc *sc; 2742 struct mii_data *mii; 2743 int error; 2744 2745 sc = ifp->if_softc; 2746 mii = device_get_softc(sc->rl_miibus); 2747 RL_LOCK(sc); 2748 error = mii_mediachg(mii); 2749 RL_UNLOCK(sc); 2750 2751 return (error); 2752} 2753 2754/* 2755 * Report current media status. 2756 */ 2757static void 2758re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2759{ 2760 struct rl_softc *sc; 2761 struct mii_data *mii; 2762 2763 sc = ifp->if_softc; 2764 mii = device_get_softc(sc->rl_miibus); 2765 2766 RL_LOCK(sc); 2767 mii_pollstat(mii); 2768 RL_UNLOCK(sc); 2769 ifmr->ifm_active = mii->mii_media_active; 2770 ifmr->ifm_status = mii->mii_media_status; 2771} 2772 2773static int 2774re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2775{ 2776 struct rl_softc *sc = ifp->if_softc; 2777 struct ifreq *ifr = (struct ifreq *) data; 2778 struct mii_data *mii; 2779 int error = 0; 2780 2781 switch (command) { 2782 case SIOCSIFMTU: 2783 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2784 error = EINVAL; 2785 break; 2786 } 2787 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2788 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2789 error = EINVAL; 2790 break; 2791 } 2792 RL_LOCK(sc); 2793 if (ifp->if_mtu != ifr->ifr_mtu) 2794 ifp->if_mtu = ifr->ifr_mtu; 2795 if (ifp->if_mtu > RL_TSO_MTU && 2796 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2797 ifp->if_capenable &= ~IFCAP_TSO4; 2798 ifp->if_hwassist &= ~CSUM_TSO; 2799 VLAN_CAPABILITIES(ifp); 2800 } 2801 RL_UNLOCK(sc); 2802 break; 2803 case SIOCSIFFLAGS: 2804 RL_LOCK(sc); 2805 if ((ifp->if_flags & IFF_UP) != 0) { 2806 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2807 if (((ifp->if_flags ^ sc->rl_if_flags) 2808 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2809 re_set_rxmode(sc); 2810 } else 2811 re_init_locked(sc); 2812 } else { 2813 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2814 re_stop(sc); 2815 } 2816 sc->rl_if_flags = ifp->if_flags; 2817 RL_UNLOCK(sc); 2818 break; 2819 case SIOCADDMULTI: 2820 case SIOCDELMULTI: 2821 RL_LOCK(sc); 2822 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2823 re_set_rxmode(sc); 2824 RL_UNLOCK(sc); 2825 break; 2826 case SIOCGIFMEDIA: 2827 case SIOCSIFMEDIA: 2828 mii = device_get_softc(sc->rl_miibus); 2829 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2830 break; 2831 case SIOCSIFCAP: 2832 { 2833 int mask, reinit; 2834 2835 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2836 reinit = 0; 2837#ifdef DEVICE_POLLING 2838 if (mask & IFCAP_POLLING) { 2839 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2840 error = ether_poll_register(re_poll, ifp); 2841 if (error) 2842 return (error); 2843 RL_LOCK(sc); 2844 /* Disable interrupts */ 2845 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2846 ifp->if_capenable |= IFCAP_POLLING; 2847 RL_UNLOCK(sc); 2848 } else { 2849 error = ether_poll_deregister(ifp); 2850 /* Enable interrupts. */ 2851 RL_LOCK(sc); 2852 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2853 ifp->if_capenable &= ~IFCAP_POLLING; 2854 RL_UNLOCK(sc); 2855 } 2856 } 2857#endif /* DEVICE_POLLING */ 2858 if (mask & IFCAP_HWCSUM) { 2859 ifp->if_capenable ^= IFCAP_HWCSUM; 2860 if (ifp->if_capenable & IFCAP_TXCSUM) 2861 ifp->if_hwassist |= RE_CSUM_FEATURES; 2862 else 2863 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2864 reinit = 1; 2865 } 2866 if ((mask & IFCAP_TSO4) != 0 && 2867 (ifp->if_capabilities & IFCAP_TSO) != 0) { 2868 ifp->if_capenable ^= IFCAP_TSO4; 2869 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 2870 ifp->if_hwassist |= CSUM_TSO; 2871 else 2872 ifp->if_hwassist &= ~CSUM_TSO; 2873 if (ifp->if_mtu > RL_TSO_MTU && 2874 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2875 ifp->if_capenable &= ~IFCAP_TSO4; 2876 ifp->if_hwassist &= ~CSUM_TSO; 2877 } 2878 } 2879 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2880 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2881 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2882 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2883 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2884 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2885 /* TSO over VLAN requires VLAN hardware tagging. */ 2886 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2887 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2888 reinit = 1; 2889 } 2890 if ((mask & IFCAP_WOL) != 0 && 2891 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2892 if ((mask & IFCAP_WOL_UCAST) != 0) 2893 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2894 if ((mask & IFCAP_WOL_MCAST) != 0) 2895 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2896 if ((mask & IFCAP_WOL_MAGIC) != 0) 2897 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2898 } 2899 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 2900 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2901 re_init(sc); 2902 } 2903 VLAN_CAPABILITIES(ifp); 2904 } 2905 break; 2906 default: 2907 error = ether_ioctl(ifp, command, data); 2908 break; 2909 } 2910 2911 return (error); 2912} 2913 2914static void 2915re_watchdog(struct rl_softc *sc) 2916{ 2917 struct ifnet *ifp; 2918 2919 RL_LOCK_ASSERT(sc); 2920 2921 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2922 return; 2923 2924 ifp = sc->rl_ifp; 2925 re_txeof(sc); 2926 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2927 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2928 "-- recovering\n"); 2929 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2930 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2931 return; 2932 } 2933 2934 if_printf(ifp, "watchdog timeout\n"); 2935 ifp->if_oerrors++; 2936 2937 re_rxeof(sc, NULL); 2938 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2939 re_init_locked(sc); 2940 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2941 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2942} 2943 2944/* 2945 * Stop the adapter and free any mbufs allocated to the 2946 * RX and TX lists. 2947 */ 2948static void 2949re_stop(struct rl_softc *sc) 2950{ 2951 int i; 2952 struct ifnet *ifp; 2953 struct rl_txdesc *txd; 2954 struct rl_rxdesc *rxd; 2955 2956 RL_LOCK_ASSERT(sc); 2957 2958 ifp = sc->rl_ifp; 2959 2960 sc->rl_watchdog_timer = 0; 2961 callout_stop(&sc->rl_stat_callout); 2962 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2963 2964 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 2965 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 2966 RL_CMD_RX_ENB); 2967 else 2968 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2969 DELAY(1000); 2970 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2971 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2972 2973 if (sc->rl_head != NULL) { 2974 m_freem(sc->rl_head); 2975 sc->rl_head = sc->rl_tail = NULL; 2976 } 2977 2978 /* Free the TX list buffers. */ 2979 2980 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2981 txd = &sc->rl_ldata.rl_tx_desc[i]; 2982 if (txd->tx_m != NULL) { 2983 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2984 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2985 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2986 txd->tx_dmamap); 2987 m_freem(txd->tx_m); 2988 txd->tx_m = NULL; 2989 } 2990 } 2991 2992 /* Free the RX list buffers. */ 2993 2994 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2995 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2996 if (rxd->rx_m != NULL) { 2997 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2998 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2999 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3000 rxd->rx_dmamap); 3001 m_freem(rxd->rx_m); 3002 rxd->rx_m = NULL; 3003 } 3004 } 3005} 3006 3007/* 3008 * Device suspend routine. Stop the interface and save some PCI 3009 * settings in case the BIOS doesn't restore them properly on 3010 * resume. 3011 */ 3012static int 3013re_suspend(device_t dev) 3014{ 3015 struct rl_softc *sc; 3016 3017 sc = device_get_softc(dev); 3018 3019 RL_LOCK(sc); 3020 re_stop(sc); 3021 re_setwol(sc); 3022 sc->suspended = 1; 3023 RL_UNLOCK(sc); 3024 3025 return (0); 3026} 3027 3028/* 3029 * Device resume routine. Restore some PCI settings in case the BIOS 3030 * doesn't, re-enable busmastering, and restart the interface if 3031 * appropriate. 3032 */ 3033static int 3034re_resume(device_t dev) 3035{ 3036 struct rl_softc *sc; 3037 struct ifnet *ifp; 3038 3039 sc = device_get_softc(dev); 3040 3041 RL_LOCK(sc); 3042 3043 ifp = sc->rl_ifp; 3044 /* Take controller out of sleep mode. */ 3045 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3046 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3047 CSR_WRITE_1(sc, RL_GPIO, 3048 CSR_READ_1(sc, RL_GPIO) | 0x01); 3049 } 3050 3051 /* 3052 * Clear WOL matching such that normal Rx filtering 3053 * wouldn't interfere with WOL patterns. 3054 */ 3055 re_clrwol(sc); 3056 3057 /* reinitialize interface if necessary */ 3058 if (ifp->if_flags & IFF_UP) 3059 re_init_locked(sc); 3060 3061 sc->suspended = 0; 3062 RL_UNLOCK(sc); 3063 3064 return (0); 3065} 3066 3067/* 3068 * Stop all chip I/O so that the kernel's probe routines don't 3069 * get confused by errant DMAs when rebooting. 3070 */ 3071static int 3072re_shutdown(device_t dev) 3073{ 3074 struct rl_softc *sc; 3075 3076 sc = device_get_softc(dev); 3077 3078 RL_LOCK(sc); 3079 re_stop(sc); 3080 /* 3081 * Mark interface as down since otherwise we will panic if 3082 * interrupt comes in later on, which can happen in some 3083 * cases. 3084 */ 3085 sc->rl_ifp->if_flags &= ~IFF_UP; 3086 re_setwol(sc); 3087 RL_UNLOCK(sc); 3088 3089 return (0); 3090} 3091 3092static void 3093re_setwol(struct rl_softc *sc) 3094{ 3095 struct ifnet *ifp; 3096 int pmc; 3097 uint16_t pmstat; 3098 uint8_t v; 3099 3100 RL_LOCK_ASSERT(sc); 3101 3102 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3103 return; 3104 3105 ifp = sc->rl_ifp; 3106 /* Put controller into sleep mode. */ 3107 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3108 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3109 CSR_WRITE_1(sc, RL_GPIO, 3110 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3111 } 3112 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3113 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3114 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3115 /* Enable config register write. */ 3116 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3117 3118 /* Enable PME. */ 3119 v = CSR_READ_1(sc, RL_CFG1); 3120 v &= ~RL_CFG1_PME; 3121 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3122 v |= RL_CFG1_PME; 3123 CSR_WRITE_1(sc, RL_CFG1, v); 3124 3125 v = CSR_READ_1(sc, RL_CFG3); 3126 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3127 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3128 v |= RL_CFG3_WOL_MAGIC; 3129 CSR_WRITE_1(sc, RL_CFG3, v); 3130 3131 /* Config register write done. */ 3132 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3133 3134 v = CSR_READ_1(sc, RL_CFG5); 3135 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3136 v &= ~RL_CFG5_WOL_LANWAKE; 3137 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3138 v |= RL_CFG5_WOL_UCAST; 3139 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3140 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3141 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3142 v |= RL_CFG5_WOL_LANWAKE; 3143 CSR_WRITE_1(sc, RL_CFG5, v); 3144 3145 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3146 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3147 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3148 /* 3149 * It seems that hardware resets its link speed to 100Mbps in 3150 * power down mode so switching to 100Mbps in driver is not 3151 * needed. 3152 */ 3153 3154 /* Request PME if WOL is requested. */ 3155 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3156 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3157 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3158 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3159 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3160} 3161 3162static void 3163re_clrwol(struct rl_softc *sc) 3164{ 3165 int pmc; 3166 uint8_t v; 3167 3168 RL_LOCK_ASSERT(sc); 3169 3170 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3171 return; 3172 3173 /* Enable config register write. */ 3174 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3175 3176 v = CSR_READ_1(sc, RL_CFG3); 3177 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3178 CSR_WRITE_1(sc, RL_CFG3, v); 3179 3180 /* Config register write done. */ 3181 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3182 3183 v = CSR_READ_1(sc, RL_CFG5); 3184 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3185 v &= ~RL_CFG5_WOL_LANWAKE; 3186 CSR_WRITE_1(sc, RL_CFG5, v); 3187} 3188