if_re.c revision 199565
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 199565 2009-11-19 23:14:40Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* Tunables. */ 159static int msi_disable = 0; 160TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161static int prefer_iomap = 0; 162TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 163 164#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 165 166/* 167 * Various supported device vendors/types and their names. 168 */ 169static struct rl_type re_devs[] = { 170 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 171 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 172 { RT_VENDORID, RT_DEVICEID_8139, 0, 173 "RealTek 8139C+ 10/100BaseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8101E, 0, 175 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 176 { RT_VENDORID, RT_DEVICEID_8168, 0, 177 "RealTek 8168/8168B/8168C/8168CP/8168D/8168DP/" 178 "8111B/8111C/8111CP/8111DP PCIe Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, 0, 180 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 184 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 185 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 186 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 187 { USR_VENDORID, USR_DEVICEID_997902, 0, 188 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 189}; 190 191static struct rl_hwrev re_hwrevs[] = { 192 { RL_HWREV_8139, RL_8139, "" }, 193 { RL_HWREV_8139A, RL_8139, "A" }, 194 { RL_HWREV_8139AG, RL_8139, "A-G" }, 195 { RL_HWREV_8139B, RL_8139, "B" }, 196 { RL_HWREV_8130, RL_8139, "8130" }, 197 { RL_HWREV_8139C, RL_8139, "C" }, 198 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 199 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 200 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 201 { RL_HWREV_8169, RL_8169, "8169"}, 202 { RL_HWREV_8169S, RL_8169, "8169S"}, 203 { RL_HWREV_8110S, RL_8169, "8110S"}, 204 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 205 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 206 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 207 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, 208 { RL_HWREV_8100, RL_8139, "8100"}, 209 { RL_HWREV_8101, RL_8139, "8101"}, 210 { RL_HWREV_8100E, RL_8169, "8100E"}, 211 { RL_HWREV_8101E, RL_8169, "8101E"}, 212 { RL_HWREV_8102E, RL_8169, "8102E"}, 213 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 214 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL"}, 215 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 216 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 217 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 218 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 219 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 220 { RL_HWREV_8168D, RL_8169, "8168D/8111D"}, 221 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP"}, 222 { 0, 0, NULL } 223}; 224 225static int re_probe (device_t); 226static int re_attach (device_t); 227static int re_detach (device_t); 228 229static int re_encap (struct rl_softc *, struct mbuf **); 230 231static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 232static int re_allocmem (device_t, struct rl_softc *); 233static __inline void re_discard_rxbuf 234 (struct rl_softc *, int); 235static int re_newbuf (struct rl_softc *, int); 236static int re_rx_list_init (struct rl_softc *); 237static int re_tx_list_init (struct rl_softc *); 238#ifdef RE_FIXUP_RX 239static __inline void re_fixup_rx 240 (struct mbuf *); 241#endif 242static int re_rxeof (struct rl_softc *, int *); 243static void re_txeof (struct rl_softc *); 244#ifdef DEVICE_POLLING 245static int re_poll (struct ifnet *, enum poll_cmd, int); 246static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 247#endif 248static int re_intr (void *); 249static void re_tick (void *); 250static void re_tx_task (void *, int); 251static void re_int_task (void *, int); 252static void re_start (struct ifnet *); 253static int re_ioctl (struct ifnet *, u_long, caddr_t); 254static void re_init (void *); 255static void re_init_locked (struct rl_softc *); 256static void re_stop (struct rl_softc *); 257static void re_watchdog (struct rl_softc *); 258static int re_suspend (device_t); 259static int re_resume (device_t); 260static int re_shutdown (device_t); 261static int re_ifmedia_upd (struct ifnet *); 262static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 263 264static void re_eeprom_putbyte (struct rl_softc *, int); 265static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 266static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 267static int re_gmii_readreg (device_t, int, int); 268static int re_gmii_writereg (device_t, int, int, int); 269 270static int re_miibus_readreg (device_t, int, int); 271static int re_miibus_writereg (device_t, int, int, int); 272static void re_miibus_statchg (device_t); 273 274static void re_set_rxmode (struct rl_softc *); 275static void re_reset (struct rl_softc *); 276static void re_setwol (struct rl_softc *); 277static void re_clrwol (struct rl_softc *); 278 279#ifdef RE_DIAG 280static int re_diag (struct rl_softc *); 281#endif 282 283static device_method_t re_methods[] = { 284 /* Device interface */ 285 DEVMETHOD(device_probe, re_probe), 286 DEVMETHOD(device_attach, re_attach), 287 DEVMETHOD(device_detach, re_detach), 288 DEVMETHOD(device_suspend, re_suspend), 289 DEVMETHOD(device_resume, re_resume), 290 DEVMETHOD(device_shutdown, re_shutdown), 291 292 /* bus interface */ 293 DEVMETHOD(bus_print_child, bus_generic_print_child), 294 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 295 296 /* MII interface */ 297 DEVMETHOD(miibus_readreg, re_miibus_readreg), 298 DEVMETHOD(miibus_writereg, re_miibus_writereg), 299 DEVMETHOD(miibus_statchg, re_miibus_statchg), 300 301 { 0, 0 } 302}; 303 304static driver_t re_driver = { 305 "re", 306 re_methods, 307 sizeof(struct rl_softc) 308}; 309 310static devclass_t re_devclass; 311 312DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 313DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 314 315#define EE_SET(x) \ 316 CSR_WRITE_1(sc, RL_EECMD, \ 317 CSR_READ_1(sc, RL_EECMD) | x) 318 319#define EE_CLR(x) \ 320 CSR_WRITE_1(sc, RL_EECMD, \ 321 CSR_READ_1(sc, RL_EECMD) & ~x) 322 323/* 324 * Send a read command and address to the EEPROM, check for ACK. 325 */ 326static void 327re_eeprom_putbyte(struct rl_softc *sc, int addr) 328{ 329 int d, i; 330 331 d = addr | (RL_9346_READ << sc->rl_eewidth); 332 333 /* 334 * Feed in each bit and strobe the clock. 335 */ 336 337 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 338 if (d & i) { 339 EE_SET(RL_EE_DATAIN); 340 } else { 341 EE_CLR(RL_EE_DATAIN); 342 } 343 DELAY(100); 344 EE_SET(RL_EE_CLK); 345 DELAY(150); 346 EE_CLR(RL_EE_CLK); 347 DELAY(100); 348 } 349} 350 351/* 352 * Read a word of data stored in the EEPROM at address 'addr.' 353 */ 354static void 355re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 356{ 357 int i; 358 u_int16_t word = 0; 359 360 /* 361 * Send address of word we want to read. 362 */ 363 re_eeprom_putbyte(sc, addr); 364 365 /* 366 * Start reading bits from EEPROM. 367 */ 368 for (i = 0x8000; i; i >>= 1) { 369 EE_SET(RL_EE_CLK); 370 DELAY(100); 371 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 372 word |= i; 373 EE_CLR(RL_EE_CLK); 374 DELAY(100); 375 } 376 377 *dest = word; 378} 379 380/* 381 * Read a sequence of words from the EEPROM. 382 */ 383static void 384re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 385{ 386 int i; 387 u_int16_t word = 0, *ptr; 388 389 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 390 391 DELAY(100); 392 393 for (i = 0; i < cnt; i++) { 394 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 395 re_eeprom_getword(sc, off + i, &word); 396 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 397 ptr = (u_int16_t *)(dest + (i * 2)); 398 *ptr = word; 399 } 400 401 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 402} 403 404static int 405re_gmii_readreg(device_t dev, int phy, int reg) 406{ 407 struct rl_softc *sc; 408 u_int32_t rval; 409 int i; 410 411 if (phy != 1) 412 return (0); 413 414 sc = device_get_softc(dev); 415 416 /* Let the rgephy driver read the GMEDIASTAT register */ 417 418 if (reg == RL_GMEDIASTAT) { 419 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 420 return (rval); 421 } 422 423 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 424 DELAY(1000); 425 426 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 427 rval = CSR_READ_4(sc, RL_PHYAR); 428 if (rval & RL_PHYAR_BUSY) 429 break; 430 DELAY(100); 431 } 432 433 if (i == RL_PHY_TIMEOUT) { 434 device_printf(sc->rl_dev, "PHY read failed\n"); 435 return (0); 436 } 437 438 return (rval & RL_PHYAR_PHYDATA); 439} 440 441static int 442re_gmii_writereg(device_t dev, int phy, int reg, int data) 443{ 444 struct rl_softc *sc; 445 u_int32_t rval; 446 int i; 447 448 sc = device_get_softc(dev); 449 450 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 451 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 452 DELAY(1000); 453 454 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 455 rval = CSR_READ_4(sc, RL_PHYAR); 456 if (!(rval & RL_PHYAR_BUSY)) 457 break; 458 DELAY(100); 459 } 460 461 if (i == RL_PHY_TIMEOUT) { 462 device_printf(sc->rl_dev, "PHY write failed\n"); 463 return (0); 464 } 465 466 return (0); 467} 468 469static int 470re_miibus_readreg(device_t dev, int phy, int reg) 471{ 472 struct rl_softc *sc; 473 u_int16_t rval = 0; 474 u_int16_t re8139_reg = 0; 475 476 sc = device_get_softc(dev); 477 478 if (sc->rl_type == RL_8169) { 479 rval = re_gmii_readreg(dev, phy, reg); 480 return (rval); 481 } 482 483 /* Pretend the internal PHY is only at address 0 */ 484 if (phy) { 485 return (0); 486 } 487 switch (reg) { 488 case MII_BMCR: 489 re8139_reg = RL_BMCR; 490 break; 491 case MII_BMSR: 492 re8139_reg = RL_BMSR; 493 break; 494 case MII_ANAR: 495 re8139_reg = RL_ANAR; 496 break; 497 case MII_ANER: 498 re8139_reg = RL_ANER; 499 break; 500 case MII_ANLPAR: 501 re8139_reg = RL_LPAR; 502 break; 503 case MII_PHYIDR1: 504 case MII_PHYIDR2: 505 return (0); 506 /* 507 * Allow the rlphy driver to read the media status 508 * register. If we have a link partner which does not 509 * support NWAY, this is the register which will tell 510 * us the results of parallel detection. 511 */ 512 case RL_MEDIASTAT: 513 rval = CSR_READ_1(sc, RL_MEDIASTAT); 514 return (rval); 515 default: 516 device_printf(sc->rl_dev, "bad phy register\n"); 517 return (0); 518 } 519 rval = CSR_READ_2(sc, re8139_reg); 520 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 521 /* 8139C+ has different bit layout. */ 522 rval &= ~(BMCR_LOOP | BMCR_ISO); 523 } 524 return (rval); 525} 526 527static int 528re_miibus_writereg(device_t dev, int phy, int reg, int data) 529{ 530 struct rl_softc *sc; 531 u_int16_t re8139_reg = 0; 532 int rval = 0; 533 534 sc = device_get_softc(dev); 535 536 if (sc->rl_type == RL_8169) { 537 rval = re_gmii_writereg(dev, phy, reg, data); 538 return (rval); 539 } 540 541 /* Pretend the internal PHY is only at address 0 */ 542 if (phy) 543 return (0); 544 545 switch (reg) { 546 case MII_BMCR: 547 re8139_reg = RL_BMCR; 548 if (sc->rl_type == RL_8139CPLUS) { 549 /* 8139C+ has different bit layout. */ 550 data &= ~(BMCR_LOOP | BMCR_ISO); 551 } 552 break; 553 case MII_BMSR: 554 re8139_reg = RL_BMSR; 555 break; 556 case MII_ANAR: 557 re8139_reg = RL_ANAR; 558 break; 559 case MII_ANER: 560 re8139_reg = RL_ANER; 561 break; 562 case MII_ANLPAR: 563 re8139_reg = RL_LPAR; 564 break; 565 case MII_PHYIDR1: 566 case MII_PHYIDR2: 567 return (0); 568 break; 569 default: 570 device_printf(sc->rl_dev, "bad phy register\n"); 571 return (0); 572 } 573 CSR_WRITE_2(sc, re8139_reg, data); 574 return (0); 575} 576 577static void 578re_miibus_statchg(device_t dev) 579{ 580 struct rl_softc *sc; 581 struct ifnet *ifp; 582 struct mii_data *mii; 583 584 sc = device_get_softc(dev); 585 mii = device_get_softc(sc->rl_miibus); 586 ifp = sc->rl_ifp; 587 if (mii == NULL || ifp == NULL || 588 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 589 return; 590 591 sc->rl_flags &= ~RL_FLAG_LINK; 592 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 593 (IFM_ACTIVE | IFM_AVALID)) { 594 switch (IFM_SUBTYPE(mii->mii_media_active)) { 595 case IFM_10_T: 596 case IFM_100_TX: 597 sc->rl_flags |= RL_FLAG_LINK; 598 break; 599 case IFM_1000_T: 600 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 601 break; 602 sc->rl_flags |= RL_FLAG_LINK; 603 break; 604 default: 605 break; 606 } 607 } 608 /* 609 * RealTek controllers does not provide any interface to 610 * Tx/Rx MACs for resolved speed, duplex and flow-control 611 * parameters. 612 */ 613} 614 615/* 616 * Set the RX configuration and 64-bit multicast hash filter. 617 */ 618static void 619re_set_rxmode(struct rl_softc *sc) 620{ 621 struct ifnet *ifp; 622 struct ifmultiaddr *ifma; 623 uint32_t hashes[2] = { 0, 0 }; 624 uint32_t h, rxfilt; 625 626 RL_LOCK_ASSERT(sc); 627 628 ifp = sc->rl_ifp; 629 630 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 631 632 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 633 if (ifp->if_flags & IFF_PROMISC) 634 rxfilt |= RL_RXCFG_RX_ALLPHYS; 635 /* 636 * Unlike other hardwares, we have to explicitly set 637 * RL_RXCFG_RX_MULTI to receive multicast frames in 638 * promiscuous mode. 639 */ 640 rxfilt |= RL_RXCFG_RX_MULTI; 641 hashes[0] = hashes[1] = 0xffffffff; 642 goto done; 643 } 644 645 if_maddr_rlock(ifp); 646 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 647 if (ifma->ifma_addr->sa_family != AF_LINK) 648 continue; 649 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 650 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 651 if (h < 32) 652 hashes[0] |= (1 << h); 653 else 654 hashes[1] |= (1 << (h - 32)); 655 } 656 if_maddr_runlock(ifp); 657 658 if (hashes[0] != 0 || hashes[1] != 0) { 659 /* 660 * For some unfathomable reason, RealTek decided to 661 * reverse the order of the multicast hash registers 662 * in the PCI Express parts. This means we have to 663 * write the hash pattern in reverse order for those 664 * devices. 665 */ 666 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 667 h = bswap32(hashes[0]); 668 hashes[0] = bswap32(hashes[1]); 669 hashes[1] = h; 670 } 671 rxfilt |= RL_RXCFG_RX_MULTI; 672 } 673 674done: 675 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 676 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 677 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 678} 679 680static void 681re_reset(struct rl_softc *sc) 682{ 683 int i; 684 685 RL_LOCK_ASSERT(sc); 686 687 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 688 689 for (i = 0; i < RL_TIMEOUT; i++) { 690 DELAY(10); 691 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 692 break; 693 } 694 if (i == RL_TIMEOUT) 695 device_printf(sc->rl_dev, "reset never completed!\n"); 696 697 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 698 CSR_WRITE_1(sc, 0x82, 1); 699 if (sc->rl_hwrev == RL_HWREV_8169S) 700 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 701} 702 703#ifdef RE_DIAG 704 705/* 706 * The following routine is designed to test for a defect on some 707 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 708 * lines connected to the bus, however for a 32-bit only card, they 709 * should be pulled high. The result of this defect is that the 710 * NIC will not work right if you plug it into a 64-bit slot: DMA 711 * operations will be done with 64-bit transfers, which will fail 712 * because the 64-bit data lines aren't connected. 713 * 714 * There's no way to work around this (short of talking a soldering 715 * iron to the board), however we can detect it. The method we use 716 * here is to put the NIC into digital loopback mode, set the receiver 717 * to promiscuous mode, and then try to send a frame. We then compare 718 * the frame data we sent to what was received. If the data matches, 719 * then the NIC is working correctly, otherwise we know the user has 720 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 721 * slot. In the latter case, there's no way the NIC can work correctly, 722 * so we print out a message on the console and abort the device attach. 723 */ 724 725static int 726re_diag(struct rl_softc *sc) 727{ 728 struct ifnet *ifp = sc->rl_ifp; 729 struct mbuf *m0; 730 struct ether_header *eh; 731 struct rl_desc *cur_rx; 732 u_int16_t status; 733 u_int32_t rxstat; 734 int total_len, i, error = 0, phyaddr; 735 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 736 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 737 738 /* Allocate a single mbuf */ 739 MGETHDR(m0, M_DONTWAIT, MT_DATA); 740 if (m0 == NULL) 741 return (ENOBUFS); 742 743 RL_LOCK(sc); 744 745 /* 746 * Initialize the NIC in test mode. This sets the chip up 747 * so that it can send and receive frames, but performs the 748 * following special functions: 749 * - Puts receiver in promiscuous mode 750 * - Enables digital loopback mode 751 * - Leaves interrupts turned off 752 */ 753 754 ifp->if_flags |= IFF_PROMISC; 755 sc->rl_testmode = 1; 756 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 757 re_init_locked(sc); 758 sc->rl_flags |= RL_FLAG_LINK; 759 if (sc->rl_type == RL_8169) 760 phyaddr = 1; 761 else 762 phyaddr = 0; 763 764 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 765 for (i = 0; i < RL_TIMEOUT; i++) { 766 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 767 if (!(status & BMCR_RESET)) 768 break; 769 } 770 771 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 772 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 773 774 DELAY(100000); 775 776 /* Put some data in the mbuf */ 777 778 eh = mtod(m0, struct ether_header *); 779 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 780 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 781 eh->ether_type = htons(ETHERTYPE_IP); 782 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 783 784 /* 785 * Queue the packet, start transmission. 786 * Note: IF_HANDOFF() ultimately calls re_start() for us. 787 */ 788 789 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 790 RL_UNLOCK(sc); 791 /* XXX: re_diag must not be called when in ALTQ mode */ 792 IF_HANDOFF(&ifp->if_snd, m0, ifp); 793 RL_LOCK(sc); 794 m0 = NULL; 795 796 /* Wait for it to propagate through the chip */ 797 798 DELAY(100000); 799 for (i = 0; i < RL_TIMEOUT; i++) { 800 status = CSR_READ_2(sc, RL_ISR); 801 CSR_WRITE_2(sc, RL_ISR, status); 802 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 803 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 804 break; 805 DELAY(10); 806 } 807 808 if (i == RL_TIMEOUT) { 809 device_printf(sc->rl_dev, 810 "diagnostic failed, failed to receive packet in" 811 " loopback mode\n"); 812 error = EIO; 813 goto done; 814 } 815 816 /* 817 * The packet should have been dumped into the first 818 * entry in the RX DMA ring. Grab it from there. 819 */ 820 821 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 822 sc->rl_ldata.rl_rx_list_map, 823 BUS_DMASYNC_POSTREAD); 824 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 825 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 826 BUS_DMASYNC_POSTREAD); 827 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 828 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 829 830 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 831 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 832 eh = mtod(m0, struct ether_header *); 833 834 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 835 total_len = RL_RXBYTES(cur_rx); 836 rxstat = le32toh(cur_rx->rl_cmdstat); 837 838 if (total_len != ETHER_MIN_LEN) { 839 device_printf(sc->rl_dev, 840 "diagnostic failed, received short packet\n"); 841 error = EIO; 842 goto done; 843 } 844 845 /* Test that the received packet data matches what we sent. */ 846 847 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 848 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 849 ntohs(eh->ether_type) != ETHERTYPE_IP) { 850 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 851 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 852 dst, ":", src, ":", ETHERTYPE_IP); 853 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 854 eh->ether_dhost, ":", eh->ether_shost, ":", 855 ntohs(eh->ether_type)); 856 device_printf(sc->rl_dev, "You may have a defective 32-bit " 857 "NIC plugged into a 64-bit PCI slot.\n"); 858 device_printf(sc->rl_dev, "Please re-install the NIC in a " 859 "32-bit slot for proper operation.\n"); 860 device_printf(sc->rl_dev, "Read the re(4) man page for more " 861 "details.\n"); 862 error = EIO; 863 } 864 865done: 866 /* Turn interface off, release resources */ 867 868 sc->rl_testmode = 0; 869 sc->rl_flags &= ~RL_FLAG_LINK; 870 ifp->if_flags &= ~IFF_PROMISC; 871 re_stop(sc); 872 if (m0 != NULL) 873 m_freem(m0); 874 875 RL_UNLOCK(sc); 876 877 return (error); 878} 879 880#endif 881 882/* 883 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 884 * IDs against our list and return a device name if we find a match. 885 */ 886static int 887re_probe(device_t dev) 888{ 889 struct rl_type *t; 890 uint16_t devid, vendor; 891 uint16_t revid, sdevid; 892 int i; 893 894 vendor = pci_get_vendor(dev); 895 devid = pci_get_device(dev); 896 revid = pci_get_revid(dev); 897 sdevid = pci_get_subdevice(dev); 898 899 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 900 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 901 /* 902 * Only attach to rev. 3 of the Linksys EG1032 adapter. 903 * Rev. 2 is supported by sk(4). 904 */ 905 return (ENXIO); 906 } 907 } 908 909 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 910 if (revid != 0x20) { 911 /* 8139, let rl(4) take care of this device. */ 912 return (ENXIO); 913 } 914 } 915 916 t = re_devs; 917 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 918 if (vendor == t->rl_vid && devid == t->rl_did) { 919 device_set_desc(dev, t->rl_name); 920 return (BUS_PROBE_DEFAULT); 921 } 922 } 923 924 return (ENXIO); 925} 926 927/* 928 * Map a single buffer address. 929 */ 930 931static void 932re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 933{ 934 bus_addr_t *addr; 935 936 if (error) 937 return; 938 939 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 940 addr = arg; 941 *addr = segs->ds_addr; 942} 943 944static int 945re_allocmem(device_t dev, struct rl_softc *sc) 946{ 947 bus_size_t rx_list_size, tx_list_size; 948 int error; 949 int i; 950 951 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 952 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 953 954 /* 955 * Allocate the parent bus DMA tag appropriate for PCI. 956 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 957 * register should be set. However some RealTek chips are known 958 * to be buggy on DAC handling, therefore disable DAC by limiting 959 * DMA address space to 32bit. PCIe variants of RealTek chips 960 * may not have the limitation but I took safer path. 961 */ 962 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 963 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 964 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 965 NULL, NULL, &sc->rl_parent_tag); 966 if (error) { 967 device_printf(dev, "could not allocate parent DMA tag\n"); 968 return (error); 969 } 970 971 /* 972 * Allocate map for TX mbufs. 973 */ 974 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 975 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 976 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 977 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 978 if (error) { 979 device_printf(dev, "could not allocate TX DMA tag\n"); 980 return (error); 981 } 982 983 /* 984 * Allocate map for RX mbufs. 985 */ 986 987 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 988 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 989 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 990 if (error) { 991 device_printf(dev, "could not allocate RX DMA tag\n"); 992 return (error); 993 } 994 995 /* 996 * Allocate map for TX descriptor list. 997 */ 998 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 999 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1000 NULL, tx_list_size, 1, tx_list_size, 0, 1001 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1002 if (error) { 1003 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1004 return (error); 1005 } 1006 1007 /* Allocate DMA'able memory for the TX ring */ 1008 1009 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1010 (void **)&sc->rl_ldata.rl_tx_list, 1011 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1012 &sc->rl_ldata.rl_tx_list_map); 1013 if (error) { 1014 device_printf(dev, "could not allocate TX DMA ring\n"); 1015 return (error); 1016 } 1017 1018 /* Load the map for the TX ring. */ 1019 1020 sc->rl_ldata.rl_tx_list_addr = 0; 1021 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1022 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1023 tx_list_size, re_dma_map_addr, 1024 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1025 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1026 device_printf(dev, "could not load TX DMA ring\n"); 1027 return (ENOMEM); 1028 } 1029 1030 /* Create DMA maps for TX buffers */ 1031 1032 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1033 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1034 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1035 if (error) { 1036 device_printf(dev, "could not create DMA map for TX\n"); 1037 return (error); 1038 } 1039 } 1040 1041 /* 1042 * Allocate map for RX descriptor list. 1043 */ 1044 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1045 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1046 NULL, rx_list_size, 1, rx_list_size, 0, 1047 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1048 if (error) { 1049 device_printf(dev, "could not create RX DMA ring tag\n"); 1050 return (error); 1051 } 1052 1053 /* Allocate DMA'able memory for the RX ring */ 1054 1055 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1056 (void **)&sc->rl_ldata.rl_rx_list, 1057 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1058 &sc->rl_ldata.rl_rx_list_map); 1059 if (error) { 1060 device_printf(dev, "could not allocate RX DMA ring\n"); 1061 return (error); 1062 } 1063 1064 /* Load the map for the RX ring. */ 1065 1066 sc->rl_ldata.rl_rx_list_addr = 0; 1067 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1068 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1069 rx_list_size, re_dma_map_addr, 1070 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1071 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1072 device_printf(dev, "could not load RX DMA ring\n"); 1073 return (ENOMEM); 1074 } 1075 1076 /* Create DMA maps for RX buffers */ 1077 1078 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1079 &sc->rl_ldata.rl_rx_sparemap); 1080 if (error) { 1081 device_printf(dev, "could not create spare DMA map for RX\n"); 1082 return (error); 1083 } 1084 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1085 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1086 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1087 if (error) { 1088 device_printf(dev, "could not create DMA map for RX\n"); 1089 return (error); 1090 } 1091 } 1092 1093 return (0); 1094} 1095 1096/* 1097 * Attach the interface. Allocate softc structures, do ifmedia 1098 * setup and ethernet/BPF attach. 1099 */ 1100static int 1101re_attach(device_t dev) 1102{ 1103 u_char eaddr[ETHER_ADDR_LEN]; 1104 u_int16_t as[ETHER_ADDR_LEN / 2]; 1105 struct rl_softc *sc; 1106 struct ifnet *ifp; 1107 struct rl_hwrev *hw_rev; 1108 int hwrev; 1109 u_int16_t devid, re_did = 0; 1110 int error = 0, rid, i; 1111 int msic, reg; 1112 uint8_t cfg; 1113 1114 sc = device_get_softc(dev); 1115 sc->rl_dev = dev; 1116 1117 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1118 MTX_DEF); 1119 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1120 1121 /* 1122 * Map control/status registers. 1123 */ 1124 pci_enable_busmaster(dev); 1125 1126 devid = pci_get_device(dev); 1127 /* 1128 * Prefer memory space register mapping over IO space. 1129 * Because RTL8169SC does not seem to work when memory mapping 1130 * is used always activate io mapping. 1131 */ 1132 if (devid == RT_DEVICEID_8169SC) 1133 prefer_iomap = 1; 1134 if (prefer_iomap == 0) { 1135 sc->rl_res_id = PCIR_BAR(1); 1136 sc->rl_res_type = SYS_RES_MEMORY; 1137 /* RTL8168/8101E seems to use different BARs. */ 1138 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1139 sc->rl_res_id = PCIR_BAR(2); 1140 } else { 1141 sc->rl_res_id = PCIR_BAR(0); 1142 sc->rl_res_type = SYS_RES_IOPORT; 1143 } 1144 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1145 &sc->rl_res_id, RF_ACTIVE); 1146 if (sc->rl_res == NULL && prefer_iomap == 0) { 1147 sc->rl_res_id = PCIR_BAR(0); 1148 sc->rl_res_type = SYS_RES_IOPORT; 1149 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1150 &sc->rl_res_id, RF_ACTIVE); 1151 } 1152 if (sc->rl_res == NULL) { 1153 device_printf(dev, "couldn't map ports/memory\n"); 1154 error = ENXIO; 1155 goto fail; 1156 } 1157 1158 sc->rl_btag = rman_get_bustag(sc->rl_res); 1159 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1160 1161 msic = 0; 1162 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1163 sc->rl_flags |= RL_FLAG_PCIE; 1164 msic = pci_msi_count(dev); 1165 if (bootverbose) 1166 device_printf(dev, "MSI count : %d\n", msic); 1167 } 1168 if (msic > 0 && msi_disable == 0) { 1169 msic = 1; 1170 if (pci_alloc_msi(dev, &msic) == 0) { 1171 if (msic == RL_MSI_MESSAGES) { 1172 device_printf(dev, "Using %d MSI messages\n", 1173 msic); 1174 sc->rl_flags |= RL_FLAG_MSI; 1175 /* Explicitly set MSI enable bit. */ 1176 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1177 cfg = CSR_READ_1(sc, RL_CFG2); 1178 cfg |= RL_CFG2_MSI; 1179 CSR_WRITE_1(sc, RL_CFG2, cfg); 1180 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1181 } else 1182 pci_release_msi(dev); 1183 } 1184 } 1185 1186 /* Allocate interrupt */ 1187 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1188 rid = 0; 1189 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1190 RF_SHAREABLE | RF_ACTIVE); 1191 if (sc->rl_irq[0] == NULL) { 1192 device_printf(dev, "couldn't allocate IRQ resources\n"); 1193 error = ENXIO; 1194 goto fail; 1195 } 1196 } else { 1197 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1198 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1199 SYS_RES_IRQ, &rid, RF_ACTIVE); 1200 if (sc->rl_irq[i] == NULL) { 1201 device_printf(dev, 1202 "couldn't llocate IRQ resources for " 1203 "message %d\n", rid); 1204 error = ENXIO; 1205 goto fail; 1206 } 1207 } 1208 } 1209 1210 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1211 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1212 cfg = CSR_READ_1(sc, RL_CFG2); 1213 if ((cfg & RL_CFG2_MSI) != 0) { 1214 device_printf(dev, "turning off MSI enable bit.\n"); 1215 cfg &= ~RL_CFG2_MSI; 1216 CSR_WRITE_1(sc, RL_CFG2, cfg); 1217 } 1218 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1219 } 1220 1221 /* Reset the adapter. */ 1222 RL_LOCK(sc); 1223 re_reset(sc); 1224 RL_UNLOCK(sc); 1225 1226 hw_rev = re_hwrevs; 1227 hwrev = CSR_READ_4(sc, RL_TXCFG); 1228 switch (hwrev & 0x70000000) { 1229 case 0x00000000: 1230 case 0x10000000: 1231 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1232 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1233 break; 1234 default: 1235 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1236 hwrev &= RL_TXCFG_HWREV; 1237 break; 1238 } 1239 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1240 while (hw_rev->rl_desc != NULL) { 1241 if (hw_rev->rl_rev == hwrev) { 1242 sc->rl_type = hw_rev->rl_type; 1243 sc->rl_hwrev = hw_rev->rl_rev; 1244 break; 1245 } 1246 hw_rev++; 1247 } 1248 if (hw_rev->rl_desc == NULL) { 1249 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1250 error = ENXIO; 1251 goto fail; 1252 } 1253 1254 switch (hw_rev->rl_rev) { 1255 case RL_HWREV_8139CPLUS: 1256 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER | 1257 RL_FLAG_AUTOPAD; 1258 break; 1259 case RL_HWREV_8100E: 1260 case RL_HWREV_8101E: 1261 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1262 RL_FLAG_FASTETHER; 1263 break; 1264 case RL_HWREV_8102E: 1265 case RL_HWREV_8102EL: 1266 case RL_HWREV_8102EL_SPIN1: 1267 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1268 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1269 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1270 break; 1271 case RL_HWREV_8168_SPIN1: 1272 case RL_HWREV_8168_SPIN2: 1273 sc->rl_flags |= RL_FLAG_WOLRXENB; 1274 /* FALLTHROUGH */ 1275 case RL_HWREV_8168_SPIN3: 1276 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1277 break; 1278 case RL_HWREV_8168C_SPIN2: 1279 sc->rl_flags |= RL_FLAG_MACSLEEP; 1280 /* FALLTHROUGH */ 1281 case RL_HWREV_8168C: 1282 if ((hwrev & 0x00700000) == 0x00200000) 1283 sc->rl_flags |= RL_FLAG_MACSLEEP; 1284 /* FALLTHROUGH */ 1285 case RL_HWREV_8168CP: 1286 case RL_HWREV_8168D: 1287 case RL_HWREV_8168DP: 1288 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1289 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1290 RL_FLAG_AUTOPAD; 1291 /* 1292 * These controllers support jumbo frame but it seems 1293 * that enabling it requires touching additional magic 1294 * registers. Depending on MAC revisions some 1295 * controllers need to disable checksum offload. So 1296 * disable jumbo frame until I have better idea what 1297 * it really requires to make it support. 1298 * RTL8168C/CP : supports up to 6KB jumbo frame. 1299 * RTL8111C/CP : supports up to 9KB jumbo frame. 1300 */ 1301 sc->rl_flags |= RL_FLAG_NOJUMBO; 1302 break; 1303 case RL_HWREV_8169_8110SB: 1304 case RL_HWREV_8169_8110SBL: 1305 case RL_HWREV_8169_8110SC: 1306 case RL_HWREV_8169_8110SCE: 1307 sc->rl_flags |= RL_FLAG_PHYWAKE; 1308 /* FALLTHROUGH */ 1309 case RL_HWREV_8169: 1310 case RL_HWREV_8169S: 1311 case RL_HWREV_8110S: 1312 sc->rl_flags |= RL_FLAG_MACRESET; 1313 break; 1314 default: 1315 break; 1316 } 1317 1318 /* Enable PME. */ 1319 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1320 cfg = CSR_READ_1(sc, RL_CFG1); 1321 cfg |= RL_CFG1_PME; 1322 CSR_WRITE_1(sc, RL_CFG1, cfg); 1323 cfg = CSR_READ_1(sc, RL_CFG5); 1324 cfg &= RL_CFG5_PME_STS; 1325 CSR_WRITE_1(sc, RL_CFG5, cfg); 1326 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1327 1328 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1329 /* 1330 * XXX Should have a better way to extract station 1331 * address from EEPROM. 1332 */ 1333 for (i = 0; i < ETHER_ADDR_LEN; i++) 1334 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1335 } else { 1336 sc->rl_eewidth = RL_9356_ADDR_LEN; 1337 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1338 if (re_did != 0x8129) 1339 sc->rl_eewidth = RL_9346_ADDR_LEN; 1340 1341 /* 1342 * Get station address from the EEPROM. 1343 */ 1344 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1345 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1346 as[i] = le16toh(as[i]); 1347 bcopy(as, eaddr, sizeof(eaddr)); 1348 } 1349 1350 if (sc->rl_type == RL_8169) { 1351 /* Set RX length mask and number of descriptors. */ 1352 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1353 sc->rl_txstart = RL_GTXSTART; 1354 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1355 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1356 } else { 1357 /* Set RX length mask and number of descriptors. */ 1358 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1359 sc->rl_txstart = RL_TXSTART; 1360 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1361 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1362 } 1363 1364 error = re_allocmem(dev, sc); 1365 if (error) 1366 goto fail; 1367 1368 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1369 if (ifp == NULL) { 1370 device_printf(dev, "can not if_alloc()\n"); 1371 error = ENOSPC; 1372 goto fail; 1373 } 1374 1375 /* Take controller out of deep sleep mode. */ 1376 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1377 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1378 CSR_WRITE_1(sc, RL_GPIO, 1379 CSR_READ_1(sc, RL_GPIO) | 0x01); 1380 else 1381 CSR_WRITE_1(sc, RL_GPIO, 1382 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1383 } 1384 1385 /* Take PHY out of power down mode. */ 1386 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1387 re_gmii_writereg(dev, 1, 0x1f, 0); 1388 re_gmii_writereg(dev, 1, 0x0e, 0); 1389 } 1390 1391 /* Do MII setup */ 1392 if (mii_phy_probe(dev, &sc->rl_miibus, 1393 re_ifmedia_upd, re_ifmedia_sts)) { 1394 device_printf(dev, "MII without any phy!\n"); 1395 error = ENXIO; 1396 goto fail; 1397 } 1398 1399 ifp->if_softc = sc; 1400 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1401 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1402 ifp->if_ioctl = re_ioctl; 1403 ifp->if_start = re_start; 1404 ifp->if_hwassist = RE_CSUM_FEATURES; 1405 ifp->if_capabilities = IFCAP_HWCSUM; 1406 ifp->if_capenable = ifp->if_capabilities; 1407 ifp->if_init = re_init; 1408 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1409 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1410 IFQ_SET_READY(&ifp->if_snd); 1411 1412 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1413 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1414 1415 /* 1416 * XXX 1417 * Still have no idea how to make TSO work on 8168C, 8168CP, 1418 * 8111C and 8111CP. 1419 */ 1420 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1421 ifp->if_hwassist |= CSUM_TSO; 1422 ifp->if_capabilities |= IFCAP_TSO4; 1423 } 1424 1425 /* 1426 * Call MI attach routine. 1427 */ 1428 ether_ifattach(ifp, eaddr); 1429 1430 /* VLAN capability setup */ 1431 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1432 if (ifp->if_capabilities & IFCAP_HWCSUM) 1433 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1434 /* Enable WOL if PM is supported. */ 1435 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1436 ifp->if_capabilities |= IFCAP_WOL; 1437 ifp->if_capenable = ifp->if_capabilities; 1438 /* 1439 * Don't enable TSO by default. Under certain 1440 * circumtances the controller generated corrupted 1441 * packets in TSO size. 1442 */ 1443 ifp->if_hwassist &= ~CSUM_TSO; 1444 ifp->if_capenable &= ~IFCAP_TSO4; 1445#ifdef DEVICE_POLLING 1446 ifp->if_capabilities |= IFCAP_POLLING; 1447#endif 1448 /* 1449 * Tell the upper layer(s) we support long frames. 1450 * Must appear after the call to ether_ifattach() because 1451 * ether_ifattach() sets ifi_hdrlen to the default value. 1452 */ 1453 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1454 1455#ifdef RE_DIAG 1456 /* 1457 * Perform hardware diagnostic on the original RTL8169. 1458 * Some 32-bit cards were incorrectly wired and would 1459 * malfunction if plugged into a 64-bit slot. 1460 */ 1461 1462 if (hwrev == RL_HWREV_8169) { 1463 error = re_diag(sc); 1464 if (error) { 1465 device_printf(dev, 1466 "attach aborted due to hardware diag failure\n"); 1467 ether_ifdetach(ifp); 1468 goto fail; 1469 } 1470 } 1471#endif 1472 1473 /* Hook interrupt last to avoid having to lock softc */ 1474 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1475 error = bus_setup_intr(dev, sc->rl_irq[0], 1476 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1477 &sc->rl_intrhand[0]); 1478 else { 1479 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1480 error = bus_setup_intr(dev, sc->rl_irq[i], 1481 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1482 &sc->rl_intrhand[i]); 1483 if (error != 0) 1484 break; 1485 } 1486 } 1487 if (error) { 1488 device_printf(dev, "couldn't set up irq\n"); 1489 ether_ifdetach(ifp); 1490 } 1491 1492fail: 1493 1494 if (error) 1495 re_detach(dev); 1496 1497 return (error); 1498} 1499 1500/* 1501 * Shutdown hardware and free up resources. This can be called any 1502 * time after the mutex has been initialized. It is called in both 1503 * the error case in attach and the normal detach case so it needs 1504 * to be careful about only freeing resources that have actually been 1505 * allocated. 1506 */ 1507static int 1508re_detach(device_t dev) 1509{ 1510 struct rl_softc *sc; 1511 struct ifnet *ifp; 1512 int i, rid; 1513 1514 sc = device_get_softc(dev); 1515 ifp = sc->rl_ifp; 1516 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1517 1518 /* These should only be active if attach succeeded */ 1519 if (device_is_attached(dev)) { 1520#ifdef DEVICE_POLLING 1521 if (ifp->if_capenable & IFCAP_POLLING) 1522 ether_poll_deregister(ifp); 1523#endif 1524 RL_LOCK(sc); 1525#if 0 1526 sc->suspended = 1; 1527#endif 1528 re_stop(sc); 1529 RL_UNLOCK(sc); 1530 callout_drain(&sc->rl_stat_callout); 1531 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1532 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1533 /* 1534 * Force off the IFF_UP flag here, in case someone 1535 * still had a BPF descriptor attached to this 1536 * interface. If they do, ether_ifdetach() will cause 1537 * the BPF code to try and clear the promisc mode 1538 * flag, which will bubble down to re_ioctl(), 1539 * which will try to call re_init() again. This will 1540 * turn the NIC back on and restart the MII ticker, 1541 * which will panic the system when the kernel tries 1542 * to invoke the re_tick() function that isn't there 1543 * anymore. 1544 */ 1545 ifp->if_flags &= ~IFF_UP; 1546 ether_ifdetach(ifp); 1547 } 1548 if (sc->rl_miibus) 1549 device_delete_child(dev, sc->rl_miibus); 1550 bus_generic_detach(dev); 1551 1552 /* 1553 * The rest is resource deallocation, so we should already be 1554 * stopped here. 1555 */ 1556 1557 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1558 if (sc->rl_intrhand[i] != NULL) { 1559 bus_teardown_intr(dev, sc->rl_irq[i], 1560 sc->rl_intrhand[i]); 1561 sc->rl_intrhand[i] = NULL; 1562 } 1563 } 1564 if (ifp != NULL) 1565 if_free(ifp); 1566 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1567 if (sc->rl_irq[0] != NULL) { 1568 bus_release_resource(dev, SYS_RES_IRQ, 0, 1569 sc->rl_irq[0]); 1570 sc->rl_irq[0] = NULL; 1571 } 1572 } else { 1573 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1574 if (sc->rl_irq[i] != NULL) { 1575 bus_release_resource(dev, SYS_RES_IRQ, rid, 1576 sc->rl_irq[i]); 1577 sc->rl_irq[i] = NULL; 1578 } 1579 } 1580 pci_release_msi(dev); 1581 } 1582 if (sc->rl_res) 1583 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1584 sc->rl_res); 1585 1586 /* Unload and free the RX DMA ring memory and map */ 1587 1588 if (sc->rl_ldata.rl_rx_list_tag) { 1589 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1590 sc->rl_ldata.rl_rx_list_map); 1591 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1592 sc->rl_ldata.rl_rx_list, 1593 sc->rl_ldata.rl_rx_list_map); 1594 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1595 } 1596 1597 /* Unload and free the TX DMA ring memory and map */ 1598 1599 if (sc->rl_ldata.rl_tx_list_tag) { 1600 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1601 sc->rl_ldata.rl_tx_list_map); 1602 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1603 sc->rl_ldata.rl_tx_list, 1604 sc->rl_ldata.rl_tx_list_map); 1605 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1606 } 1607 1608 /* Destroy all the RX and TX buffer maps */ 1609 1610 if (sc->rl_ldata.rl_tx_mtag) { 1611 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1612 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1613 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1614 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1615 } 1616 if (sc->rl_ldata.rl_rx_mtag) { 1617 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1618 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1619 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1620 if (sc->rl_ldata.rl_rx_sparemap) 1621 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1622 sc->rl_ldata.rl_rx_sparemap); 1623 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1624 } 1625 1626 /* Unload and free the stats buffer and map */ 1627 1628 if (sc->rl_ldata.rl_stag) { 1629 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1630 sc->rl_ldata.rl_rx_list_map); 1631 bus_dmamem_free(sc->rl_ldata.rl_stag, 1632 sc->rl_ldata.rl_stats, 1633 sc->rl_ldata.rl_smap); 1634 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1635 } 1636 1637 if (sc->rl_parent_tag) 1638 bus_dma_tag_destroy(sc->rl_parent_tag); 1639 1640 mtx_destroy(&sc->rl_mtx); 1641 1642 return (0); 1643} 1644 1645static __inline void 1646re_discard_rxbuf(struct rl_softc *sc, int idx) 1647{ 1648 struct rl_desc *desc; 1649 struct rl_rxdesc *rxd; 1650 uint32_t cmdstat; 1651 1652 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1653 desc = &sc->rl_ldata.rl_rx_list[idx]; 1654 desc->rl_vlanctl = 0; 1655 cmdstat = rxd->rx_size; 1656 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1657 cmdstat |= RL_RDESC_CMD_EOR; 1658 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1659} 1660 1661static int 1662re_newbuf(struct rl_softc *sc, int idx) 1663{ 1664 struct mbuf *m; 1665 struct rl_rxdesc *rxd; 1666 bus_dma_segment_t segs[1]; 1667 bus_dmamap_t map; 1668 struct rl_desc *desc; 1669 uint32_t cmdstat; 1670 int error, nsegs; 1671 1672 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1673 if (m == NULL) 1674 return (ENOBUFS); 1675 1676 m->m_len = m->m_pkthdr.len = MCLBYTES; 1677#ifdef RE_FIXUP_RX 1678 /* 1679 * This is part of an evil trick to deal with non-x86 platforms. 1680 * The RealTek chip requires RX buffers to be aligned on 64-bit 1681 * boundaries, but that will hose non-x86 machines. To get around 1682 * this, we leave some empty space at the start of each buffer 1683 * and for non-x86 hosts, we copy the buffer back six bytes 1684 * to achieve word alignment. This is slightly more efficient 1685 * than allocating a new buffer, copying the contents, and 1686 * discarding the old buffer. 1687 */ 1688 m_adj(m, RE_ETHER_ALIGN); 1689#endif 1690 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1691 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1692 if (error != 0) { 1693 m_freem(m); 1694 return (ENOBUFS); 1695 } 1696 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1697 1698 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1699 if (rxd->rx_m != NULL) { 1700 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1701 BUS_DMASYNC_POSTREAD); 1702 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1703 } 1704 1705 rxd->rx_m = m; 1706 map = rxd->rx_dmamap; 1707 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1708 rxd->rx_size = segs[0].ds_len; 1709 sc->rl_ldata.rl_rx_sparemap = map; 1710 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1711 BUS_DMASYNC_PREREAD); 1712 1713 desc = &sc->rl_ldata.rl_rx_list[idx]; 1714 desc->rl_vlanctl = 0; 1715 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1716 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1717 cmdstat = segs[0].ds_len; 1718 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1719 cmdstat |= RL_RDESC_CMD_EOR; 1720 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1721 1722 return (0); 1723} 1724 1725#ifdef RE_FIXUP_RX 1726static __inline void 1727re_fixup_rx(struct mbuf *m) 1728{ 1729 int i; 1730 uint16_t *src, *dst; 1731 1732 src = mtod(m, uint16_t *); 1733 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1734 1735 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1736 *dst++ = *src++; 1737 1738 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1739} 1740#endif 1741 1742static int 1743re_tx_list_init(struct rl_softc *sc) 1744{ 1745 struct rl_desc *desc; 1746 int i; 1747 1748 RL_LOCK_ASSERT(sc); 1749 1750 bzero(sc->rl_ldata.rl_tx_list, 1751 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1752 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1753 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1754 /* Set EOR. */ 1755 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1756 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1757 1758 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1759 sc->rl_ldata.rl_tx_list_map, 1760 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1761 1762 sc->rl_ldata.rl_tx_prodidx = 0; 1763 sc->rl_ldata.rl_tx_considx = 0; 1764 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1765 1766 return (0); 1767} 1768 1769static int 1770re_rx_list_init(struct rl_softc *sc) 1771{ 1772 int error, i; 1773 1774 bzero(sc->rl_ldata.rl_rx_list, 1775 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1776 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1777 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1778 if ((error = re_newbuf(sc, i)) != 0) 1779 return (error); 1780 } 1781 1782 /* Flush the RX descriptors */ 1783 1784 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1785 sc->rl_ldata.rl_rx_list_map, 1786 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1787 1788 sc->rl_ldata.rl_rx_prodidx = 0; 1789 sc->rl_head = sc->rl_tail = NULL; 1790 1791 return (0); 1792} 1793 1794/* 1795 * RX handler for C+ and 8169. For the gigE chips, we support 1796 * the reception of jumbo frames that have been fragmented 1797 * across multiple 2K mbuf cluster buffers. 1798 */ 1799static int 1800re_rxeof(struct rl_softc *sc, int *rx_npktsp) 1801{ 1802 struct mbuf *m; 1803 struct ifnet *ifp; 1804 int i, total_len; 1805 struct rl_desc *cur_rx; 1806 u_int32_t rxstat, rxvlan; 1807 int maxpkt = 16, rx_npkts = 0; 1808 1809 RL_LOCK_ASSERT(sc); 1810 1811 ifp = sc->rl_ifp; 1812 1813 /* Invalidate the descriptor memory */ 1814 1815 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1816 sc->rl_ldata.rl_rx_list_map, 1817 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1818 1819 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1820 i = RL_RX_DESC_NXT(sc, i)) { 1821 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1822 break; 1823 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1824 rxstat = le32toh(cur_rx->rl_cmdstat); 1825 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1826 break; 1827 total_len = rxstat & sc->rl_rxlenmask; 1828 rxvlan = le32toh(cur_rx->rl_vlanctl); 1829 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1830 1831 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1832 if (re_newbuf(sc, i) != 0) { 1833 /* 1834 * If this is part of a multi-fragment packet, 1835 * discard all the pieces. 1836 */ 1837 if (sc->rl_head != NULL) { 1838 m_freem(sc->rl_head); 1839 sc->rl_head = sc->rl_tail = NULL; 1840 } 1841 re_discard_rxbuf(sc, i); 1842 continue; 1843 } 1844 m->m_len = RE_RX_DESC_BUFLEN; 1845 if (sc->rl_head == NULL) 1846 sc->rl_head = sc->rl_tail = m; 1847 else { 1848 m->m_flags &= ~M_PKTHDR; 1849 sc->rl_tail->m_next = m; 1850 sc->rl_tail = m; 1851 } 1852 continue; 1853 } 1854 1855 /* 1856 * NOTE: for the 8139C+, the frame length field 1857 * is always 12 bits in size, but for the gigE chips, 1858 * it is 13 bits (since the max RX frame length is 16K). 1859 * Unfortunately, all 32 bits in the status word 1860 * were already used, so to make room for the extra 1861 * length bit, RealTek took out the 'frame alignment 1862 * error' bit and shifted the other status bits 1863 * over one slot. The OWN, EOR, FS and LS bits are 1864 * still in the same places. We have already extracted 1865 * the frame length and checked the OWN bit, so rather 1866 * than using an alternate bit mapping, we shift the 1867 * status bits one space to the right so we can evaluate 1868 * them using the 8169 status as though it was in the 1869 * same format as that of the 8139C+. 1870 */ 1871 if (sc->rl_type == RL_8169) 1872 rxstat >>= 1; 1873 1874 /* 1875 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1876 * set, but if CRC is clear, it will still be a valid frame. 1877 */ 1878 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1879 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1880 ifp->if_ierrors++; 1881 /* 1882 * If this is part of a multi-fragment packet, 1883 * discard all the pieces. 1884 */ 1885 if (sc->rl_head != NULL) { 1886 m_freem(sc->rl_head); 1887 sc->rl_head = sc->rl_tail = NULL; 1888 } 1889 re_discard_rxbuf(sc, i); 1890 continue; 1891 } 1892 1893 /* 1894 * If allocating a replacement mbuf fails, 1895 * reload the current one. 1896 */ 1897 1898 if (re_newbuf(sc, i) != 0) { 1899 ifp->if_iqdrops++; 1900 if (sc->rl_head != NULL) { 1901 m_freem(sc->rl_head); 1902 sc->rl_head = sc->rl_tail = NULL; 1903 } 1904 re_discard_rxbuf(sc, i); 1905 continue; 1906 } 1907 1908 if (sc->rl_head != NULL) { 1909 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1910 if (m->m_len == 0) 1911 m->m_len = RE_RX_DESC_BUFLEN; 1912 /* 1913 * Special case: if there's 4 bytes or less 1914 * in this buffer, the mbuf can be discarded: 1915 * the last 4 bytes is the CRC, which we don't 1916 * care about anyway. 1917 */ 1918 if (m->m_len <= ETHER_CRC_LEN) { 1919 sc->rl_tail->m_len -= 1920 (ETHER_CRC_LEN - m->m_len); 1921 m_freem(m); 1922 } else { 1923 m->m_len -= ETHER_CRC_LEN; 1924 m->m_flags &= ~M_PKTHDR; 1925 sc->rl_tail->m_next = m; 1926 } 1927 m = sc->rl_head; 1928 sc->rl_head = sc->rl_tail = NULL; 1929 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1930 } else 1931 m->m_pkthdr.len = m->m_len = 1932 (total_len - ETHER_CRC_LEN); 1933 1934#ifdef RE_FIXUP_RX 1935 re_fixup_rx(m); 1936#endif 1937 ifp->if_ipackets++; 1938 m->m_pkthdr.rcvif = ifp; 1939 1940 /* Do RX checksumming if enabled */ 1941 1942 if (ifp->if_capenable & IFCAP_RXCSUM) { 1943 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1944 /* Check IP header checksum */ 1945 if (rxstat & RL_RDESC_STAT_PROTOID) 1946 m->m_pkthdr.csum_flags |= 1947 CSUM_IP_CHECKED; 1948 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1949 m->m_pkthdr.csum_flags |= 1950 CSUM_IP_VALID; 1951 1952 /* Check TCP/UDP checksum */ 1953 if ((RL_TCPPKT(rxstat) && 1954 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1955 (RL_UDPPKT(rxstat) && 1956 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1957 m->m_pkthdr.csum_flags |= 1958 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1959 m->m_pkthdr.csum_data = 0xffff; 1960 } 1961 } else { 1962 /* 1963 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1964 */ 1965 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1966 (rxvlan & RL_RDESC_IPV4)) 1967 m->m_pkthdr.csum_flags |= 1968 CSUM_IP_CHECKED; 1969 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1970 (rxvlan & RL_RDESC_IPV4)) 1971 m->m_pkthdr.csum_flags |= 1972 CSUM_IP_VALID; 1973 if (((rxstat & RL_RDESC_STAT_TCP) && 1974 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1975 ((rxstat & RL_RDESC_STAT_UDP) && 1976 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1977 m->m_pkthdr.csum_flags |= 1978 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1979 m->m_pkthdr.csum_data = 0xffff; 1980 } 1981 } 1982 } 1983 maxpkt--; 1984 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1985 m->m_pkthdr.ether_vtag = 1986 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 1987 m->m_flags |= M_VLANTAG; 1988 } 1989 RL_UNLOCK(sc); 1990 (*ifp->if_input)(ifp, m); 1991 RL_LOCK(sc); 1992 rx_npkts++; 1993 } 1994 1995 /* Flush the RX DMA ring */ 1996 1997 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1998 sc->rl_ldata.rl_rx_list_map, 1999 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2000 2001 sc->rl_ldata.rl_rx_prodidx = i; 2002 2003 if (rx_npktsp != NULL) 2004 *rx_npktsp = rx_npkts; 2005 if (maxpkt) 2006 return(EAGAIN); 2007 2008 return(0); 2009} 2010 2011static void 2012re_txeof(struct rl_softc *sc) 2013{ 2014 struct ifnet *ifp; 2015 struct rl_txdesc *txd; 2016 u_int32_t txstat; 2017 int cons; 2018 2019 cons = sc->rl_ldata.rl_tx_considx; 2020 if (cons == sc->rl_ldata.rl_tx_prodidx) 2021 return; 2022 2023 ifp = sc->rl_ifp; 2024 /* Invalidate the TX descriptor list */ 2025 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2026 sc->rl_ldata.rl_tx_list_map, 2027 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2028 2029 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2030 cons = RL_TX_DESC_NXT(sc, cons)) { 2031 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2032 if (txstat & RL_TDESC_STAT_OWN) 2033 break; 2034 /* 2035 * We only stash mbufs in the last descriptor 2036 * in a fragment chain, which also happens to 2037 * be the only place where the TX status bits 2038 * are valid. 2039 */ 2040 if (txstat & RL_TDESC_CMD_EOF) { 2041 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2042 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2043 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2044 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2045 txd->tx_dmamap); 2046 KASSERT(txd->tx_m != NULL, 2047 ("%s: freeing NULL mbufs!", __func__)); 2048 m_freem(txd->tx_m); 2049 txd->tx_m = NULL; 2050 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2051 RL_TDESC_STAT_COLCNT)) 2052 ifp->if_collisions++; 2053 if (txstat & RL_TDESC_STAT_TXERRSUM) 2054 ifp->if_oerrors++; 2055 else 2056 ifp->if_opackets++; 2057 } 2058 sc->rl_ldata.rl_tx_free++; 2059 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2060 } 2061 sc->rl_ldata.rl_tx_considx = cons; 2062 2063 /* No changes made to the TX ring, so no flush needed */ 2064 2065 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2066#ifdef RE_TX_MODERATION 2067 /* 2068 * If not all descriptors have been reaped yet, reload 2069 * the timer so that we will eventually get another 2070 * interrupt that will cause us to re-enter this routine. 2071 * This is done in case the transmitter has gone idle. 2072 */ 2073 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2074#endif 2075 } else 2076 sc->rl_watchdog_timer = 0; 2077} 2078 2079static void 2080re_tick(void *xsc) 2081{ 2082 struct rl_softc *sc; 2083 struct mii_data *mii; 2084 2085 sc = xsc; 2086 2087 RL_LOCK_ASSERT(sc); 2088 2089 mii = device_get_softc(sc->rl_miibus); 2090 mii_tick(mii); 2091 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2092 re_miibus_statchg(sc->rl_dev); 2093 /* 2094 * Reclaim transmitted frames here. Technically it is not 2095 * necessary to do here but it ensures periodic reclamation 2096 * regardless of Tx completion interrupt which seems to be 2097 * lost on PCIe based controllers under certain situations. 2098 */ 2099 re_txeof(sc); 2100 re_watchdog(sc); 2101 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2102} 2103 2104#ifdef DEVICE_POLLING 2105static int 2106re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2107{ 2108 struct rl_softc *sc = ifp->if_softc; 2109 int rx_npkts = 0; 2110 2111 RL_LOCK(sc); 2112 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2113 rx_npkts = re_poll_locked(ifp, cmd, count); 2114 RL_UNLOCK(sc); 2115 return (rx_npkts); 2116} 2117 2118static int 2119re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2120{ 2121 struct rl_softc *sc = ifp->if_softc; 2122 int rx_npkts; 2123 2124 RL_LOCK_ASSERT(sc); 2125 2126 sc->rxcycles = count; 2127 re_rxeof(sc, &rx_npkts); 2128 re_txeof(sc); 2129 2130 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2131 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2132 2133 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2134 u_int16_t status; 2135 2136 status = CSR_READ_2(sc, RL_ISR); 2137 if (status == 0xffff) 2138 return (rx_npkts); 2139 if (status) 2140 CSR_WRITE_2(sc, RL_ISR, status); 2141 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2142 (sc->rl_flags & RL_FLAG_PCIE)) 2143 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2144 2145 /* 2146 * XXX check behaviour on receiver stalls. 2147 */ 2148 2149 if (status & RL_ISR_SYSTEM_ERR) { 2150 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2151 re_init_locked(sc); 2152 } 2153 } 2154 return (rx_npkts); 2155} 2156#endif /* DEVICE_POLLING */ 2157 2158static int 2159re_intr(void *arg) 2160{ 2161 struct rl_softc *sc; 2162 uint16_t status; 2163 2164 sc = arg; 2165 2166 status = CSR_READ_2(sc, RL_ISR); 2167 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2168 return (FILTER_STRAY); 2169 CSR_WRITE_2(sc, RL_IMR, 0); 2170 2171 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2172 2173 return (FILTER_HANDLED); 2174} 2175 2176static void 2177re_int_task(void *arg, int npending) 2178{ 2179 struct rl_softc *sc; 2180 struct ifnet *ifp; 2181 u_int16_t status; 2182 int rval = 0; 2183 2184 sc = arg; 2185 ifp = sc->rl_ifp; 2186 2187 RL_LOCK(sc); 2188 2189 status = CSR_READ_2(sc, RL_ISR); 2190 CSR_WRITE_2(sc, RL_ISR, status); 2191 2192 if (sc->suspended || 2193 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2194 RL_UNLOCK(sc); 2195 return; 2196 } 2197 2198#ifdef DEVICE_POLLING 2199 if (ifp->if_capenable & IFCAP_POLLING) { 2200 RL_UNLOCK(sc); 2201 return; 2202 } 2203#endif 2204 2205 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2206 rval = re_rxeof(sc, NULL); 2207 2208 /* 2209 * Some chips will ignore a second TX request issued 2210 * while an existing transmission is in progress. If 2211 * the transmitter goes idle but there are still 2212 * packets waiting to be sent, we need to restart the 2213 * channel here to flush them out. This only seems to 2214 * be required with the PCIe devices. 2215 */ 2216 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2217 (sc->rl_flags & RL_FLAG_PCIE)) 2218 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2219 if (status & ( 2220#ifdef RE_TX_MODERATION 2221 RL_ISR_TIMEOUT_EXPIRED| 2222#else 2223 RL_ISR_TX_OK| 2224#endif 2225 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2226 re_txeof(sc); 2227 2228 if (status & RL_ISR_SYSTEM_ERR) { 2229 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2230 re_init_locked(sc); 2231 } 2232 2233 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2234 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2235 2236 RL_UNLOCK(sc); 2237 2238 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2239 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2240 return; 2241 } 2242 2243 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2244} 2245 2246static int 2247re_encap(struct rl_softc *sc, struct mbuf **m_head) 2248{ 2249 struct rl_txdesc *txd, *txd_last; 2250 bus_dma_segment_t segs[RL_NTXSEGS]; 2251 bus_dmamap_t map; 2252 struct mbuf *m_new; 2253 struct rl_desc *desc; 2254 int nsegs, prod; 2255 int i, error, ei, si; 2256 int padlen; 2257 uint32_t cmdstat, csum_flags, vlanctl; 2258 2259 RL_LOCK_ASSERT(sc); 2260 M_ASSERTPKTHDR((*m_head)); 2261 2262 /* 2263 * With some of the RealTek chips, using the checksum offload 2264 * support in conjunction with the autopadding feature results 2265 * in the transmission of corrupt frames. For example, if we 2266 * need to send a really small IP fragment that's less than 60 2267 * bytes in size, and IP header checksumming is enabled, the 2268 * resulting ethernet frame that appears on the wire will 2269 * have garbled payload. To work around this, if TX IP checksum 2270 * offload is enabled, we always manually pad short frames out 2271 * to the minimum ethernet frame size. 2272 */ 2273 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2274 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2275 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2276 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2277 if (M_WRITABLE(*m_head) == 0) { 2278 /* Get a writable copy. */ 2279 m_new = m_dup(*m_head, M_DONTWAIT); 2280 m_freem(*m_head); 2281 if (m_new == NULL) { 2282 *m_head = NULL; 2283 return (ENOBUFS); 2284 } 2285 *m_head = m_new; 2286 } 2287 if ((*m_head)->m_next != NULL || 2288 M_TRAILINGSPACE(*m_head) < padlen) { 2289 m_new = m_defrag(*m_head, M_DONTWAIT); 2290 if (m_new == NULL) { 2291 m_freem(*m_head); 2292 *m_head = NULL; 2293 return (ENOBUFS); 2294 } 2295 } else 2296 m_new = *m_head; 2297 2298 /* 2299 * Manually pad short frames, and zero the pad space 2300 * to avoid leaking data. 2301 */ 2302 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2303 m_new->m_pkthdr.len += padlen; 2304 m_new->m_len = m_new->m_pkthdr.len; 2305 *m_head = m_new; 2306 } 2307 2308 prod = sc->rl_ldata.rl_tx_prodidx; 2309 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2310 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2311 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2312 if (error == EFBIG) { 2313 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2314 if (m_new == NULL) { 2315 m_freem(*m_head); 2316 *m_head = NULL; 2317 return (ENOBUFS); 2318 } 2319 *m_head = m_new; 2320 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2321 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2322 if (error != 0) { 2323 m_freem(*m_head); 2324 *m_head = NULL; 2325 return (error); 2326 } 2327 } else if (error != 0) 2328 return (error); 2329 if (nsegs == 0) { 2330 m_freem(*m_head); 2331 *m_head = NULL; 2332 return (EIO); 2333 } 2334 2335 /* Check for number of available descriptors. */ 2336 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2337 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2338 return (ENOBUFS); 2339 } 2340 2341 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2342 BUS_DMASYNC_PREWRITE); 2343 2344 /* 2345 * Set up checksum offload. Note: checksum offload bits must 2346 * appear in all descriptors of a multi-descriptor transmit 2347 * attempt. This is according to testing done with an 8169 2348 * chip. This is a requirement. 2349 */ 2350 vlanctl = 0; 2351 csum_flags = 0; 2352 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2353 csum_flags = RL_TDESC_CMD_LGSEND | 2354 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2355 RL_TDESC_CMD_MSSVAL_SHIFT); 2356 else { 2357 /* 2358 * Unconditionally enable IP checksum if TCP or UDP 2359 * checksum is required. Otherwise, TCP/UDP checksum 2360 * does't make effects. 2361 */ 2362 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2363 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2364 csum_flags |= RL_TDESC_CMD_IPCSUM; 2365 if (((*m_head)->m_pkthdr.csum_flags & 2366 CSUM_TCP) != 0) 2367 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2368 if (((*m_head)->m_pkthdr.csum_flags & 2369 CSUM_UDP) != 0) 2370 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2371 } else { 2372 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2373 if (((*m_head)->m_pkthdr.csum_flags & 2374 CSUM_TCP) != 0) 2375 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2376 if (((*m_head)->m_pkthdr.csum_flags & 2377 CSUM_UDP) != 0) 2378 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2379 } 2380 } 2381 } 2382 2383 /* 2384 * Set up hardware VLAN tagging. Note: vlan tag info must 2385 * appear in all descriptors of a multi-descriptor 2386 * transmission attempt. 2387 */ 2388 if ((*m_head)->m_flags & M_VLANTAG) 2389 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2390 RL_TDESC_VLANCTL_TAG; 2391 2392 si = prod; 2393 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2394 desc = &sc->rl_ldata.rl_tx_list[prod]; 2395 desc->rl_vlanctl = htole32(vlanctl); 2396 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2397 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2398 cmdstat = segs[i].ds_len; 2399 if (i != 0) 2400 cmdstat |= RL_TDESC_CMD_OWN; 2401 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2402 cmdstat |= RL_TDESC_CMD_EOR; 2403 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2404 sc->rl_ldata.rl_tx_free--; 2405 } 2406 /* Update producer index. */ 2407 sc->rl_ldata.rl_tx_prodidx = prod; 2408 2409 /* Set EOF on the last descriptor. */ 2410 ei = RL_TX_DESC_PRV(sc, prod); 2411 desc = &sc->rl_ldata.rl_tx_list[ei]; 2412 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2413 2414 desc = &sc->rl_ldata.rl_tx_list[si]; 2415 /* Set SOF and transfer ownership of packet to the chip. */ 2416 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2417 2418 /* 2419 * Insure that the map for this transmission 2420 * is placed at the array index of the last descriptor 2421 * in this chain. (Swap last and first dmamaps.) 2422 */ 2423 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2424 map = txd->tx_dmamap; 2425 txd->tx_dmamap = txd_last->tx_dmamap; 2426 txd_last->tx_dmamap = map; 2427 txd_last->tx_m = *m_head; 2428 2429 return (0); 2430} 2431 2432static void 2433re_tx_task(void *arg, int npending) 2434{ 2435 struct ifnet *ifp; 2436 2437 ifp = arg; 2438 re_start(ifp); 2439} 2440 2441/* 2442 * Main transmit routine for C+ and gigE NICs. 2443 */ 2444static void 2445re_start(struct ifnet *ifp) 2446{ 2447 struct rl_softc *sc; 2448 struct mbuf *m_head; 2449 int queued; 2450 2451 sc = ifp->if_softc; 2452 2453 RL_LOCK(sc); 2454 2455 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2456 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2457 RL_UNLOCK(sc); 2458 return; 2459 } 2460 2461 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2462 sc->rl_ldata.rl_tx_free > 1;) { 2463 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2464 if (m_head == NULL) 2465 break; 2466 2467 if (re_encap(sc, &m_head) != 0) { 2468 if (m_head == NULL) 2469 break; 2470 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2471 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2472 break; 2473 } 2474 2475 /* 2476 * If there's a BPF listener, bounce a copy of this frame 2477 * to him. 2478 */ 2479 ETHER_BPF_MTAP(ifp, m_head); 2480 2481 queued++; 2482 } 2483 2484 if (queued == 0) { 2485#ifdef RE_TX_MODERATION 2486 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2487 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2488#endif 2489 RL_UNLOCK(sc); 2490 return; 2491 } 2492 2493 /* Flush the TX descriptors */ 2494 2495 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2496 sc->rl_ldata.rl_tx_list_map, 2497 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2498 2499 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2500 2501#ifdef RE_TX_MODERATION 2502 /* 2503 * Use the countdown timer for interrupt moderation. 2504 * 'TX done' interrupts are disabled. Instead, we reset the 2505 * countdown timer, which will begin counting until it hits 2506 * the value in the TIMERINT register, and then trigger an 2507 * interrupt. Each time we write to the TIMERCNT register, 2508 * the timer count is reset to 0. 2509 */ 2510 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2511#endif 2512 2513 /* 2514 * Set a timeout in case the chip goes out to lunch. 2515 */ 2516 sc->rl_watchdog_timer = 5; 2517 2518 RL_UNLOCK(sc); 2519} 2520 2521static void 2522re_init(void *xsc) 2523{ 2524 struct rl_softc *sc = xsc; 2525 2526 RL_LOCK(sc); 2527 re_init_locked(sc); 2528 RL_UNLOCK(sc); 2529} 2530 2531static void 2532re_init_locked(struct rl_softc *sc) 2533{ 2534 struct ifnet *ifp = sc->rl_ifp; 2535 struct mii_data *mii; 2536 uint32_t reg; 2537 uint16_t cfg; 2538 union { 2539 uint32_t align_dummy; 2540 u_char eaddr[ETHER_ADDR_LEN]; 2541 } eaddr; 2542 2543 RL_LOCK_ASSERT(sc); 2544 2545 mii = device_get_softc(sc->rl_miibus); 2546 2547 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2548 return; 2549 2550 /* 2551 * Cancel pending I/O and free all RX/TX buffers. 2552 */ 2553 re_stop(sc); 2554 2555 /* Put controller into known state. */ 2556 re_reset(sc); 2557 2558 /* 2559 * Enable C+ RX and TX mode, as well as VLAN stripping and 2560 * RX checksum offload. We must configure the C+ register 2561 * before all others. 2562 */ 2563 cfg = RL_CPLUSCMD_PCI_MRW; 2564 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2565 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2566 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2567 cfg |= RL_CPLUSCMD_VLANSTRIP; 2568 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2569 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2570 /* XXX magic. */ 2571 cfg |= 0x0001; 2572 } else 2573 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2574 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2575 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2576 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2577 reg = 0x000fff00; 2578 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2579 reg |= 0x000000ff; 2580 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2581 reg |= 0x00f00000; 2582 CSR_WRITE_4(sc, 0x7c, reg); 2583 /* Disable interrupt mitigation. */ 2584 CSR_WRITE_2(sc, 0xe2, 0); 2585 } 2586 /* 2587 * Disable TSO if interface MTU size is greater than MSS 2588 * allowed in controller. 2589 */ 2590 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2591 ifp->if_capenable &= ~IFCAP_TSO4; 2592 ifp->if_hwassist &= ~CSUM_TSO; 2593 } 2594 2595 /* 2596 * Init our MAC address. Even though the chipset 2597 * documentation doesn't mention it, we need to enter "Config 2598 * register write enable" mode to modify the ID registers. 2599 */ 2600 /* Copy MAC address on stack to align. */ 2601 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2602 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2603 CSR_WRITE_4(sc, RL_IDR0, 2604 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2605 CSR_WRITE_4(sc, RL_IDR4, 2606 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2607 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2608 2609 /* 2610 * For C+ mode, initialize the RX descriptors and mbufs. 2611 */ 2612 re_rx_list_init(sc); 2613 re_tx_list_init(sc); 2614 2615 /* 2616 * Load the addresses of the RX and TX lists into the chip. 2617 */ 2618 2619 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2620 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2621 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2622 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2623 2624 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2625 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2626 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2627 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2628 2629 /* 2630 * Enable transmit and receive. 2631 */ 2632 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2633 2634 /* 2635 * Set the initial TX configuration. 2636 */ 2637 if (sc->rl_testmode) { 2638 if (sc->rl_type == RL_8169) 2639 CSR_WRITE_4(sc, RL_TXCFG, 2640 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2641 else 2642 CSR_WRITE_4(sc, RL_TXCFG, 2643 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2644 } else 2645 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2646 2647 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2648 2649 /* 2650 * Set the initial RX configuration. 2651 */ 2652 re_set_rxmode(sc); 2653 2654#ifdef DEVICE_POLLING 2655 /* 2656 * Disable interrupts if we are polling. 2657 */ 2658 if (ifp->if_capenable & IFCAP_POLLING) 2659 CSR_WRITE_2(sc, RL_IMR, 0); 2660 else /* otherwise ... */ 2661#endif 2662 2663 /* 2664 * Enable interrupts. 2665 */ 2666 if (sc->rl_testmode) 2667 CSR_WRITE_2(sc, RL_IMR, 0); 2668 else 2669 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2670 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2671 2672 /* Set initial TX threshold */ 2673 sc->rl_txthresh = RL_TX_THRESH_INIT; 2674 2675 /* Start RX/TX process. */ 2676 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2677#ifdef notdef 2678 /* Enable receiver and transmitter. */ 2679 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2680#endif 2681 2682#ifdef RE_TX_MODERATION 2683 /* 2684 * Initialize the timer interrupt register so that 2685 * a timer interrupt will be generated once the timer 2686 * reaches a certain number of ticks. The timer is 2687 * reloaded on each transmit. This gives us TX interrupt 2688 * moderation, which dramatically improves TX frame rate. 2689 */ 2690 if (sc->rl_type == RL_8169) 2691 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2692 else 2693 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2694#endif 2695 2696 /* 2697 * For 8169 gigE NICs, set the max allowed RX packet 2698 * size so we can receive jumbo frames. 2699 */ 2700 if (sc->rl_type == RL_8169) 2701 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2702 2703 if (sc->rl_testmode) 2704 return; 2705 2706 mii_mediachg(mii); 2707 2708 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2709 2710 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2711 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2712 2713 sc->rl_flags &= ~RL_FLAG_LINK; 2714 sc->rl_watchdog_timer = 0; 2715 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2716} 2717 2718/* 2719 * Set media options. 2720 */ 2721static int 2722re_ifmedia_upd(struct ifnet *ifp) 2723{ 2724 struct rl_softc *sc; 2725 struct mii_data *mii; 2726 int error; 2727 2728 sc = ifp->if_softc; 2729 mii = device_get_softc(sc->rl_miibus); 2730 RL_LOCK(sc); 2731 error = mii_mediachg(mii); 2732 RL_UNLOCK(sc); 2733 2734 return (error); 2735} 2736 2737/* 2738 * Report current media status. 2739 */ 2740static void 2741re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2742{ 2743 struct rl_softc *sc; 2744 struct mii_data *mii; 2745 2746 sc = ifp->if_softc; 2747 mii = device_get_softc(sc->rl_miibus); 2748 2749 RL_LOCK(sc); 2750 mii_pollstat(mii); 2751 RL_UNLOCK(sc); 2752 ifmr->ifm_active = mii->mii_media_active; 2753 ifmr->ifm_status = mii->mii_media_status; 2754} 2755 2756static int 2757re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2758{ 2759 struct rl_softc *sc = ifp->if_softc; 2760 struct ifreq *ifr = (struct ifreq *) data; 2761 struct mii_data *mii; 2762 int error = 0; 2763 2764 switch (command) { 2765 case SIOCSIFMTU: 2766 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2767 error = EINVAL; 2768 break; 2769 } 2770 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2771 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2772 error = EINVAL; 2773 break; 2774 } 2775 RL_LOCK(sc); 2776 if (ifp->if_mtu != ifr->ifr_mtu) 2777 ifp->if_mtu = ifr->ifr_mtu; 2778 if (ifp->if_mtu > RL_TSO_MTU && 2779 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2780 ifp->if_capenable &= ~IFCAP_TSO4; 2781 ifp->if_hwassist &= ~CSUM_TSO; 2782 } 2783 RL_UNLOCK(sc); 2784 break; 2785 case SIOCSIFFLAGS: 2786 RL_LOCK(sc); 2787 if ((ifp->if_flags & IFF_UP) != 0) { 2788 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2789 if (((ifp->if_flags ^ sc->rl_if_flags) 2790 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2791 re_set_rxmode(sc); 2792 } else 2793 re_init_locked(sc); 2794 } else { 2795 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2796 re_stop(sc); 2797 } 2798 sc->rl_if_flags = ifp->if_flags; 2799 RL_UNLOCK(sc); 2800 break; 2801 case SIOCADDMULTI: 2802 case SIOCDELMULTI: 2803 RL_LOCK(sc); 2804 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2805 re_set_rxmode(sc); 2806 RL_UNLOCK(sc); 2807 break; 2808 case SIOCGIFMEDIA: 2809 case SIOCSIFMEDIA: 2810 mii = device_get_softc(sc->rl_miibus); 2811 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2812 break; 2813 case SIOCSIFCAP: 2814 { 2815 int mask, reinit; 2816 2817 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2818 reinit = 0; 2819#ifdef DEVICE_POLLING 2820 if (mask & IFCAP_POLLING) { 2821 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2822 error = ether_poll_register(re_poll, ifp); 2823 if (error) 2824 return(error); 2825 RL_LOCK(sc); 2826 /* Disable interrupts */ 2827 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2828 ifp->if_capenable |= IFCAP_POLLING; 2829 RL_UNLOCK(sc); 2830 } else { 2831 error = ether_poll_deregister(ifp); 2832 /* Enable interrupts. */ 2833 RL_LOCK(sc); 2834 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2835 ifp->if_capenable &= ~IFCAP_POLLING; 2836 RL_UNLOCK(sc); 2837 } 2838 } 2839#endif /* DEVICE_POLLING */ 2840 if (mask & IFCAP_HWCSUM) { 2841 ifp->if_capenable ^= IFCAP_HWCSUM; 2842 if (ifp->if_capenable & IFCAP_TXCSUM) 2843 ifp->if_hwassist |= RE_CSUM_FEATURES; 2844 else 2845 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2846 reinit = 1; 2847 } 2848 if (mask & IFCAP_VLAN_HWTAGGING) { 2849 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2850 reinit = 1; 2851 } 2852 if (mask & IFCAP_TSO4) { 2853 ifp->if_capenable ^= IFCAP_TSO4; 2854 if ((IFCAP_TSO4 & ifp->if_capenable) && 2855 (IFCAP_TSO4 & ifp->if_capabilities)) 2856 ifp->if_hwassist |= CSUM_TSO; 2857 else 2858 ifp->if_hwassist &= ~CSUM_TSO; 2859 if (ifp->if_mtu > RL_TSO_MTU && 2860 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2861 ifp->if_capenable &= ~IFCAP_TSO4; 2862 ifp->if_hwassist &= ~CSUM_TSO; 2863 } 2864 } 2865 if ((mask & IFCAP_WOL) != 0 && 2866 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2867 if ((mask & IFCAP_WOL_UCAST) != 0) 2868 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2869 if ((mask & IFCAP_WOL_MCAST) != 0) 2870 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2871 if ((mask & IFCAP_WOL_MAGIC) != 0) 2872 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2873 } 2874 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 2875 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2876 re_init(sc); 2877 } 2878 VLAN_CAPABILITIES(ifp); 2879 } 2880 break; 2881 default: 2882 error = ether_ioctl(ifp, command, data); 2883 break; 2884 } 2885 2886 return (error); 2887} 2888 2889static void 2890re_watchdog(struct rl_softc *sc) 2891{ 2892 struct ifnet *ifp; 2893 2894 RL_LOCK_ASSERT(sc); 2895 2896 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2897 return; 2898 2899 ifp = sc->rl_ifp; 2900 re_txeof(sc); 2901 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2902 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2903 "-- recovering\n"); 2904 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2905 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2906 return; 2907 } 2908 2909 if_printf(ifp, "watchdog timeout\n"); 2910 ifp->if_oerrors++; 2911 2912 re_rxeof(sc, NULL); 2913 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2914 re_init_locked(sc); 2915 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2916 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2917} 2918 2919/* 2920 * Stop the adapter and free any mbufs allocated to the 2921 * RX and TX lists. 2922 */ 2923static void 2924re_stop(struct rl_softc *sc) 2925{ 2926 int i; 2927 struct ifnet *ifp; 2928 struct rl_txdesc *txd; 2929 struct rl_rxdesc *rxd; 2930 2931 RL_LOCK_ASSERT(sc); 2932 2933 ifp = sc->rl_ifp; 2934 2935 sc->rl_watchdog_timer = 0; 2936 callout_stop(&sc->rl_stat_callout); 2937 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2938 2939 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 2940 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 2941 RL_CMD_RX_ENB); 2942 else 2943 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2944 DELAY(1000); 2945 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2946 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2947 2948 if (sc->rl_head != NULL) { 2949 m_freem(sc->rl_head); 2950 sc->rl_head = sc->rl_tail = NULL; 2951 } 2952 2953 /* Free the TX list buffers. */ 2954 2955 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2956 txd = &sc->rl_ldata.rl_tx_desc[i]; 2957 if (txd->tx_m != NULL) { 2958 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2959 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2960 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2961 txd->tx_dmamap); 2962 m_freem(txd->tx_m); 2963 txd->tx_m = NULL; 2964 } 2965 } 2966 2967 /* Free the RX list buffers. */ 2968 2969 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2970 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2971 if (rxd->rx_m != NULL) { 2972 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2973 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2974 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2975 rxd->rx_dmamap); 2976 m_freem(rxd->rx_m); 2977 rxd->rx_m = NULL; 2978 } 2979 } 2980} 2981 2982/* 2983 * Device suspend routine. Stop the interface and save some PCI 2984 * settings in case the BIOS doesn't restore them properly on 2985 * resume. 2986 */ 2987static int 2988re_suspend(device_t dev) 2989{ 2990 struct rl_softc *sc; 2991 2992 sc = device_get_softc(dev); 2993 2994 RL_LOCK(sc); 2995 re_stop(sc); 2996 re_setwol(sc); 2997 sc->suspended = 1; 2998 RL_UNLOCK(sc); 2999 3000 return (0); 3001} 3002 3003/* 3004 * Device resume routine. Restore some PCI settings in case the BIOS 3005 * doesn't, re-enable busmastering, and restart the interface if 3006 * appropriate. 3007 */ 3008static int 3009re_resume(device_t dev) 3010{ 3011 struct rl_softc *sc; 3012 struct ifnet *ifp; 3013 3014 sc = device_get_softc(dev); 3015 3016 RL_LOCK(sc); 3017 3018 ifp = sc->rl_ifp; 3019 /* Take controller out of sleep mode. */ 3020 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3021 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3022 CSR_WRITE_1(sc, RL_GPIO, 3023 CSR_READ_1(sc, RL_GPIO) | 0x01); 3024 } 3025 3026 /* 3027 * Clear WOL matching such that normal Rx filtering 3028 * wouldn't interfere with WOL patterns. 3029 */ 3030 re_clrwol(sc); 3031 3032 /* reinitialize interface if necessary */ 3033 if (ifp->if_flags & IFF_UP) 3034 re_init_locked(sc); 3035 3036 sc->suspended = 0; 3037 RL_UNLOCK(sc); 3038 3039 return (0); 3040} 3041 3042/* 3043 * Stop all chip I/O so that the kernel's probe routines don't 3044 * get confused by errant DMAs when rebooting. 3045 */ 3046static int 3047re_shutdown(device_t dev) 3048{ 3049 struct rl_softc *sc; 3050 3051 sc = device_get_softc(dev); 3052 3053 RL_LOCK(sc); 3054 re_stop(sc); 3055 /* 3056 * Mark interface as down since otherwise we will panic if 3057 * interrupt comes in later on, which can happen in some 3058 * cases. 3059 */ 3060 sc->rl_ifp->if_flags &= ~IFF_UP; 3061 re_setwol(sc); 3062 RL_UNLOCK(sc); 3063 3064 return (0); 3065} 3066 3067static void 3068re_setwol(struct rl_softc *sc) 3069{ 3070 struct ifnet *ifp; 3071 int pmc; 3072 uint16_t pmstat; 3073 uint8_t v; 3074 3075 RL_LOCK_ASSERT(sc); 3076 3077 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3078 return; 3079 3080 ifp = sc->rl_ifp; 3081 /* Put controller into sleep mode. */ 3082 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3083 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3084 CSR_WRITE_1(sc, RL_GPIO, 3085 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3086 } 3087 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3088 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3089 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3090 /* Enable config register write. */ 3091 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3092 3093 /* Enable PME. */ 3094 v = CSR_READ_1(sc, RL_CFG1); 3095 v &= ~RL_CFG1_PME; 3096 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3097 v |= RL_CFG1_PME; 3098 CSR_WRITE_1(sc, RL_CFG1, v); 3099 3100 v = CSR_READ_1(sc, RL_CFG3); 3101 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3102 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3103 v |= RL_CFG3_WOL_MAGIC; 3104 CSR_WRITE_1(sc, RL_CFG3, v); 3105 3106 /* Config register write done. */ 3107 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3108 3109 v = CSR_READ_1(sc, RL_CFG5); 3110 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3111 v &= ~RL_CFG5_WOL_LANWAKE; 3112 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3113 v |= RL_CFG5_WOL_UCAST; 3114 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3115 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3116 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3117 v |= RL_CFG5_WOL_LANWAKE; 3118 CSR_WRITE_1(sc, RL_CFG5, v); 3119 3120 /* 3121 * It seems that hardware resets its link speed to 100Mbps in 3122 * power down mode so switching to 100Mbps in driver is not 3123 * needed. 3124 */ 3125 3126 /* Request PME if WOL is requested. */ 3127 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3128 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3129 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3130 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3131 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3132} 3133 3134static void 3135re_clrwol(struct rl_softc *sc) 3136{ 3137 int pmc; 3138 uint8_t v; 3139 3140 RL_LOCK_ASSERT(sc); 3141 3142 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3143 return; 3144 3145 /* Enable config register write. */ 3146 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3147 3148 v = CSR_READ_1(sc, RL_CFG3); 3149 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3150 CSR_WRITE_1(sc, RL_CFG3, v); 3151 3152 /* Config register write done. */ 3153 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3154 3155 v = CSR_READ_1(sc, RL_CFG5); 3156 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3157 v &= ~RL_CFG5_WOL_LANWAKE; 3158 CSR_WRITE_1(sc, RL_CFG5, v); 3159} 3160