if_re.c revision 189576
120253Sjoerg/*- 220302Sjoerg * Copyright (c) 1997, 1998-2003 320302Sjoerg * Bill Paul <wpaul@windriver.com>. All rights reserved. 420253Sjoerg * 520253Sjoerg * Redistribution and use in source and binary forms, with or without 620253Sjoerg * modification, are permitted provided that the following conditions 720253Sjoerg * are met: 820253Sjoerg * 1. Redistributions of source code must retain the above copyright 920302Sjoerg * notice, this list of conditions and the following disclaimer. 1020253Sjoerg * 2. Redistributions in binary form must reproduce the above copyright 1120253Sjoerg * notice, this list of conditions and the following disclaimer in the 1220253Sjoerg * documentation and/or other materials provided with the distribution. 1320253Sjoerg * 3. All advertising materials mentioning features or use of this software 1420302Sjoerg * must display the following acknowledgement: 1520253Sjoerg * This product includes software developed by Bill Paul. 1620253Sjoerg * 4. Neither the name of the author nor the names of any co-contributors 1720302Sjoerg * may be used to endorse or promote products derived from this software 1820253Sjoerg * without specific prior written permission. 1920253Sjoerg * 2020253Sjoerg * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2120253Sjoerg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2220253Sjoerg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2320253Sjoerg * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2420253Sjoerg * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2544229Sdavidn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2620253Sjoerg * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2720253Sjoerg * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2830259Scharnier * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2930259Scharnier * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3050479Speter * THE POSSIBILITY OF SUCH DAMAGE. 3130259Scharnier */ 3230259Scharnier 3330259Scharnier#include <sys/cdefs.h> 3430259Scharnier__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 189576 2009-03-09 13:25:34Z imp $"); 3520253Sjoerg 3620253Sjoerg/* 3720253Sjoerg * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 3830259Scharnier * 3920253Sjoerg * Written by Bill Paul <wpaul@windriver.com> 4020555Sdavidn * Senior Networking Software Engineer 4120555Sdavidn * Wind River Systems 4220555Sdavidn */ 4364918Sgreen 44242349Sbapt/* 45242349Sbapt * This driver is designed to support RealTek's next generation of 46242349Sbapt * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 4720253Sjoerg * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 4820253Sjoerg * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 4920253Sjoerg * 5023318Sache * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 5122394Sdavidn * with the older 8139 family, however it also supports a special 5252512Sdavidn * C+ mode of operation that provides several new performance enhancing 5324214Sache * features. These include: 54284111Sbapt * 55284128Sbapt * o Descriptor based DMA mechanism. Each descriptor represents 56284124Sbapt * a single packet fragment. Data buffers may be aligned on 57284133Sbapt * any byte boundary. 58284118Sbapt * 5920253Sjoerg * o 64-bit DMA 6020253Sjoerg * 6120253Sjoerg * o TCP/IP checksum offload for both RX and TX 6220253Sjoerg * 6320253Sjoerg * o High and normal priority transmit DMA rings 6420253Sjoerg * 6520253Sjoerg * o VLAN tag insertion and extraction 6685145Sache * 6720253Sjoerg * o TCP large send (segmentation offload) 68283961Sbapt * 69284118Sbapt * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70283961Sbapt * programming API is fairly straightforward. The RX filtering, EEPROM 71283961Sbapt * access and PHY access is the same as it is on the older 8139 series 72284118Sbapt * chips. 73283961Sbapt * 74283961Sbapt * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75283961Sbapt * same programming API and feature set as the 8139C+ with the following 76284118Sbapt * differences and additions: 77284118Sbapt * 78283961Sbapt * o 1000Mbps mode 79283961Sbapt * 80284118Sbapt * o Jumbo frames 81283961Sbapt * 82283961Sbapt * o GMII and TBI ports/registers for interfacing with copper 83283961Sbapt * or fiber PHYs 84283961Sbapt * 85283961Sbapt * o RX and TX DMA rings can have up to 1024 descriptors 86283961Sbapt * (the 8139C+ allows a maximum of 64) 87283961Sbapt * 88283961Sbapt * o Slight differences in register layout from the 8139C+ 8920253Sjoerg * 9020253Sjoerg * The TX start and timer interrupt registers are at different locations 9120253Sjoerg * on the 8169 than they are on the 8139C+. Also, the status word in the 9220253Sjoerg * RX descriptor has a slightly different bit layout. The 8169 does not 9320253Sjoerg * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 9420253Sjoerg * copper gigE PHY. 9520253Sjoerg * 9620253Sjoerg * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 9720253Sjoerg * (the 'S' stands for 'single-chip'). These devices have the same 9820253Sjoerg * programming API as the older 8169, but also have some vendor-specific 9920253Sjoerg * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 10020253Sjoerg * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 10120253Sjoerg * 10220253Sjoerg * This driver takes advantage of the RX and TX checksum offload and 10320253Sjoerg * VLAN tag insertion/extraction features. It also implements TX 10420253Sjoerg * interrupt moderation using the timer interrupt registers, which 10520253Sjoerg * significantly reduces TX interrupt load. There is also support 106124382Siedowse * for jumbo frames, however the 8169/8169S/8110S can not transmit 10720253Sjoerg * jumbo frames larger than 7440, so the max MTU possible with this 10820253Sjoerg * driver is 7422 bytes. 10920253Sjoerg */ 11020253Sjoerg 11120253Sjoerg#ifdef HAVE_KERNEL_OPTION_HEADERS 11220253Sjoerg#include "opt_device_polling.h" 11320253Sjoerg#endif 11420253Sjoerg 11520253Sjoerg#include <sys/param.h> 11620253Sjoerg#include <sys/endian.h> 11720253Sjoerg#include <sys/systm.h> 11820253Sjoerg#include <sys/sockio.h> 11920253Sjoerg#include <sys/mbuf.h> 12020253Sjoerg#include <sys/malloc.h> 12120253Sjoerg#include <sys/module.h> 122284128Sbapt#include <sys/kernel.h> 12320253Sjoerg#include <sys/socket.h> 12452527Sdavidn#include <sys/lock.h> 12520253Sjoerg#include <sys/mutex.h> 12652512Sdavidn#include <sys/taskqueue.h> 12720253Sjoerg 12820253Sjoerg#include <net/if.h> 12920253Sjoerg#include <net/if_arp.h> 13020253Sjoerg#include <net/ethernet.h> 131284118Sbapt#include <net/if_dl.h> 13220747Sdavidn#include <net/if_media.h> 133283961Sbapt#include <net/if_types.h> 13482868Sdd#include <net/if_vlan_var.h> 135167919Sle 136167919Sle#include <net/bpf.h> 13720253Sjoerg 13820253Sjoerg#include <machine/bus.h> 13920253Sjoerg#include <machine/resource.h> 14020253Sjoerg#include <sys/bus.h> 14120253Sjoerg#include <sys/rman.h> 14220253Sjoerg 14320253Sjoerg#include <dev/mii/mii.h> 14420253Sjoerg#include <dev/mii/miivar.h> 14520253Sjoerg 14620253Sjoerg#include <dev/pci/pcireg.h> 14756000Sdavidn#include <dev/pci/pcivar.h> 14820253Sjoerg 14920253Sjoerg#include <pci/if_rlreg.h> 15056000Sdavidn 15156000SdavidnMODULE_DEPEND(re, pci, 1, 1, 1); 15256000SdavidnMODULE_DEPEND(re, ether, 1, 1, 1); 15320253SjoergMODULE_DEPEND(re, miibus, 1, 1, 1); 15420253Sjoerg 155284118Sbapt/* "device miibus" required. See GENERIC if you get errors here. */ 15652512Sdavidn#include "miibus_if.h" 15720253Sjoerg 15820267Sjoerg/* Tunables. */ 15920267Sjoergstatic int msi_disable = 0; 16020267SjoergTUNABLE_INT("hw.re.msi_disable", &msi_disable); 16120267Sjoergstatic int prefer_iomap = 0; 16220267SjoergTUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 163284133Sbapt 16420267Sjoerg#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 16520267Sjoerg 166283842Sbapt/* 167284128Sbapt * Various supported device vendors/types and their names. 16820267Sjoerg */ 16920267Sjoergstatic struct rl_type re_devs[] = { 17020267Sjoerg { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 17120267Sjoerg "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 17220253Sjoerg { RT_VENDORID, RT_DEVICEID_8139, 0, 17320253Sjoerg "RealTek 8139C+ 10/100BaseTX" }, 17420253Sjoerg { RT_VENDORID, RT_DEVICEID_8101E, 0, 17520253Sjoerg "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 17620267Sjoerg { RT_VENDORID, RT_DEVICEID_8168, 0, 17720253Sjoerg "RealTek 8168/8168B/8168C/8168CP/8168D/8111B/8111C/8111CP PCIe " 17821052Sdavidn "Gigabit Ethernet" }, 179167919Sle { RT_VENDORID, RT_DEVICEID_8169, 0, 180167919Sle "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 181167919Sle { RT_VENDORID, RT_DEVICEID_8169SC, 0, 182167919Sle "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183167919Sle { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 184219408Sjkim "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 185167919Sle { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 186168044Sle "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 187167919Sle { USR_VENDORID, USR_DEVICEID_997902, 0, 18821052Sdavidn "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 18921052Sdavidn}; 19021052Sdavidn 19121052Sdavidnstatic struct rl_hwrev re_hwrevs[] = { 192224535Sdelphij { RL_HWREV_8139, RL_8139, "" }, 19321052Sdavidn { RL_HWREV_8139A, RL_8139, "A" }, 19421052Sdavidn { RL_HWREV_8139AG, RL_8139, "A-G" }, 19521052Sdavidn { RL_HWREV_8139B, RL_8139, "B" }, 19621052Sdavidn { RL_HWREV_8130, RL_8139, "8130" }, 19721052Sdavidn { RL_HWREV_8139C, RL_8139, "C" }, 19821052Sdavidn { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 19930259Scharnier { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 20021052Sdavidn { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 20121052Sdavidn { RL_HWREV_8169, RL_8169, "8169"}, 20221052Sdavidn { RL_HWREV_8169S, RL_8169, "8169S"}, 20321052Sdavidn { RL_HWREV_8110S, RL_8169, "8110S"}, 20421242Sdavidn { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 20521242Sdavidn { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 20621242Sdavidn { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 20721242Sdavidn { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, 20821242Sdavidn { RL_HWREV_8100, RL_8139, "8100"}, 20921242Sdavidn { RL_HWREV_8101, RL_8139, "8101"}, 21021242Sdavidn { RL_HWREV_8100E, RL_8169, "8100E"}, 211282683Sbapt { RL_HWREV_8101E, RL_8169, "8101E"}, 212219408Sjkim { RL_HWREV_8102E, RL_8169, "8102E"}, 21321242Sdavidn { RL_HWREV_8102EL, RL_8169, "8102EL"}, 214148584Spjd { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 215148584Spjd { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 216148584Spjd { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 217148584Spjd { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 218148584Spjd { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 21921242Sdavidn { RL_HWREV_8168D, RL_8169, "8168D"}, 22021242Sdavidn { 0, 0, NULL } 22121242Sdavidn}; 222130633Srobert 223130633Srobertstatic int re_probe (device_t); 22421242Sdavidnstatic int re_attach (device_t); 225252377Skientzlestatic int re_detach (device_t); 22621242Sdavidn 22721242Sdavidnstatic int re_encap (struct rl_softc *, struct mbuf **); 228219408Sjkim 22921242Sdavidnstatic void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 23021242Sdavidnstatic int re_allocmem (device_t, struct rl_softc *); 23121242Sdavidnstatic __inline void re_discard_rxbuf 23230259Scharnier (struct rl_softc *, int); 23321242Sdavidnstatic int re_newbuf (struct rl_softc *, int); 23421242Sdavidnstatic int re_rx_list_init (struct rl_softc *); 23521052Sdavidnstatic int re_tx_list_init (struct rl_softc *); 23621242Sdavidn#ifdef RE_FIXUP_RX 237219408Sjkimstatic __inline void re_fixup_rx 23830259Scharnier (struct mbuf *); 23921052Sdavidn#endif 24021052Sdavidnstatic int re_rxeof (struct rl_softc *); 24121052Sdavidnstatic void re_txeof (struct rl_softc *); 24221052Sdavidn#ifdef DEVICE_POLLING 24330259Scharnierstatic void re_poll (struct ifnet *, enum poll_cmd, int); 24421052Sdavidnstatic void re_poll_locked (struct ifnet *, enum poll_cmd, int); 24521052Sdavidn#endif 24620253Sjoergstatic int re_intr (void *); 24720253Sjoergstatic void re_tick (void *); 24820253Sjoergstatic void re_tx_task (void *, int); 24921330Sdavidnstatic void re_int_task (void *, int); 25021330Sdavidnstatic void re_start (struct ifnet *); 25121330Sdavidnstatic int re_ioctl (struct ifnet *, u_long, caddr_t); 25220253Sjoergstatic void re_init (void *); 25320253Sjoergstatic void re_init_locked (struct rl_softc *); 25420253Sjoergstatic void re_stop (struct rl_softc *); 25520253Sjoergstatic void re_watchdog (struct rl_softc *); 25663596Sdavidnstatic int re_suspend (device_t); 25763596Sdavidnstatic int re_resume (device_t); 25863596Sdavidnstatic int re_shutdown (device_t); 25963596Sdavidnstatic int re_ifmedia_upd (struct ifnet *); 26063596Sdavidnstatic void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 26163596Sdavidn 26263596Sdavidnstatic void re_eeprom_putbyte (struct rl_softc *, int); 26363596Sdavidnstatic void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 26420253Sjoergstatic void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 26520253Sjoergstatic int re_gmii_readreg (device_t, int, int); 26620253Sjoergstatic int re_gmii_writereg (device_t, int, int, int); 267284110Sbapt 26820253Sjoergstatic int re_miibus_readreg (device_t, int, int); 26920253Sjoergstatic int re_miibus_writereg (device_t, int, int, int); 27052527Sdavidnstatic void re_miibus_statchg (device_t); 27120253Sjoerg 27220747Sdavidnstatic void re_set_rxmode (struct rl_softc *); 27344229Sdavidnstatic void re_reset (struct rl_softc *); 27461957Sachestatic void re_setwol (struct rl_softc *); 27530259Scharnierstatic void re_clrwol (struct rl_softc *); 27620253Sjoerg 27720747Sdavidn#ifdef RE_DIAG 27820747Sdavidnstatic int re_diag (struct rl_softc *); 27920253Sjoerg#endif 28020747Sdavidn 28120253Sjoergstatic device_method_t re_methods[] = { 28220253Sjoerg /* Device interface */ 28352527Sdavidn DEVMETHOD(device_probe, re_probe), 28420253Sjoerg DEVMETHOD(device_attach, re_attach), 28526088Sdavidn DEVMETHOD(device_detach, re_detach), 28630259Scharnier DEVMETHOD(device_suspend, re_suspend), 28720253Sjoerg DEVMETHOD(device_resume, re_resume), 28852527Sdavidn DEVMETHOD(device_shutdown, re_shutdown), 28920253Sjoerg 29020253Sjoerg /* bus interface */ 29120253Sjoerg DEVMETHOD(bus_print_child, bus_generic_print_child), 29263600Sdavidn DEVMETHOD(bus_driver_added, bus_generic_driver_added), 29363600Sdavidn 29420253Sjoerg /* MII interface */ 29520253Sjoerg DEVMETHOD(miibus_readreg, re_miibus_readreg), 29630259Scharnier DEVMETHOD(miibus_writereg, re_miibus_writereg), 29720253Sjoerg DEVMETHOD(miibus_statchg, re_miibus_statchg), 29820253Sjoerg 29920253Sjoerg { 0, 0 } 30020253Sjoerg}; 30120253Sjoerg 30220253Sjoergstatic driver_t re_driver = { 30320253Sjoerg "re", 30420253Sjoerg re_methods, 30520253Sjoerg sizeof(struct rl_softc) 30620253Sjoerg}; 30720253Sjoerg 30820253Sjoergstatic devclass_t re_devclass; 30920253Sjoerg 31020253SjoergDRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 31120253SjoergDRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 31220267Sjoerg 313283814Sbapt#define EE_SET(x) \ 31420253Sjoerg CSR_WRITE_1(sc, RL_EECMD, \ 31552527Sdavidn CSR_READ_1(sc, RL_EECMD) | x) 31620253Sjoerg 31744229Sdavidn#define EE_CLR(x) \ 31844229Sdavidn CSR_WRITE_1(sc, RL_EECMD, \ 319284124Sbapt CSR_READ_1(sc, RL_EECMD) & ~x) 32044229Sdavidn 32120267Sjoerg/* 32220253Sjoerg * Send a read command and address to the EEPROM, check for ACK. 32352527Sdavidn */ 324284128Sbaptstatic void 325284128Sbaptre_eeprom_putbyte(struct rl_softc *sc, int addr) 32620253Sjoerg{ 327284128Sbapt int d, i; 328284128Sbapt 32920253Sjoerg d = addr | (RL_9346_READ << sc->rl_eewidth); 33020253Sjoerg 33120253Sjoerg /* 33220253Sjoerg * Feed in each bit and strobe the clock. 33352512Sdavidn */ 33452512Sdavidn 33552527Sdavidn for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 336284128Sbapt if (d & i) { 337284128Sbapt EE_SET(RL_EE_DATAIN); 33820253Sjoerg } else { 33920253Sjoerg EE_CLR(RL_EE_DATAIN); 34020253Sjoerg } 341284128Sbapt DELAY(100); 342284128Sbapt EE_SET(RL_EE_CLK); 343284126Sbapt DELAY(150); 34420253Sjoerg EE_CLR(RL_EE_CLK); 345284128Sbapt DELAY(100); 346284128Sbapt } 347284128Sbapt} 34820253Sjoerg 34952527Sdavidn/* 350284128Sbapt * Read a word of data stored in the EEPROM at address 'addr.' 351284128Sbapt */ 35220253Sjoergstatic void 35320253Sjoergre_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 35452512Sdavidn{ 35552512Sdavidn int i; 35652512Sdavidn u_int16_t word = 0; 35752512Sdavidn 35852512Sdavidn /* 35952512Sdavidn * Send address of word we want to read. 36052512Sdavidn */ 36152512Sdavidn re_eeprom_putbyte(sc, addr); 36252512Sdavidn 36352512Sdavidn /* 36452512Sdavidn * Start reading bits from EEPROM. 36552512Sdavidn */ 366282685Sbapt for (i = 0x8000; i; i >>= 1) { 36752512Sdavidn EE_SET(RL_EE_CLK); 36852512Sdavidn DELAY(100); 36952512Sdavidn if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 37052527Sdavidn word |= i; 37152512Sdavidn EE_CLR(RL_EE_CLK); 37252512Sdavidn DELAY(100); 37352512Sdavidn } 37452512Sdavidn 37552527Sdavidn *dest = word; 376284111Sbapt} 377284128Sbapt 378284111Sbapt/* 379284111Sbapt * Read a sequence of words from the EEPROM. 380284126Sbapt */ 38120253Sjoergstatic void 38220253Sjoergre_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 38320253Sjoerg{ 38420253Sjoerg int i; 385284129Sbapt u_int16_t word = 0, *ptr; 38620253Sjoerg 38730259Scharnier CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 388284129Sbapt 38952527Sdavidn DELAY(100); 39020253Sjoerg 39152527Sdavidn for (i = 0; i < cnt; i++) { 392284133Sbapt CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 393284133Sbapt re_eeprom_getword(sc, off + i, &word); 39452527Sdavidn CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 39520253Sjoerg ptr = (u_int16_t *)(dest + (i * 2)); 39630259Scharnier *ptr = word; 39720253Sjoerg } 39830259Scharnier 39920253Sjoerg CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 40020253Sjoerg} 40152527Sdavidn 40252527Sdavidnstatic int 40352527Sdavidnre_gmii_readreg(device_t dev, int phy, int reg) 40452527Sdavidn{ 40561762Sdavidn struct rl_softc *sc; 40652527Sdavidn u_int32_t rval; 40752527Sdavidn int i; 40852527Sdavidn 40920253Sjoerg if (phy != 1) 41052527Sdavidn return (0); 41152527Sdavidn 41252527Sdavidn sc = device_get_softc(dev); 41352527Sdavidn 41452527Sdavidn /* Let the rgephy driver read the GMEDIASTAT register */ 41552527Sdavidn 41620253Sjoerg if (reg == RL_GMEDIASTAT) { 41720253Sjoerg rval = CSR_READ_1(sc, RL_GMEDIASTAT); 41820253Sjoerg return (rval); 41920253Sjoerg } 42052527Sdavidn 42152527Sdavidn CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 42252527Sdavidn 42352527Sdavidn for (i = 0; i < RL_PHY_TIMEOUT; i++) { 42420253Sjoerg rval = CSR_READ_4(sc, RL_PHYAR); 42520253Sjoerg if (rval & RL_PHYAR_BUSY) 42652527Sdavidn break; 42720267Sjoerg DELAY(100); 42852527Sdavidn } 42952527Sdavidn 43052527Sdavidn if (i == RL_PHY_TIMEOUT) { 43152527Sdavidn device_printf(sc->rl_dev, "PHY read failed\n"); 43252527Sdavidn return (0); 43352527Sdavidn } 43420253Sjoerg 43520253Sjoerg return (rval & RL_PHYAR_PHYDATA); 43620253Sjoerg} 43720253Sjoerg 43852527Sdavidnstatic int 43952527Sdavidnre_gmii_writereg(device_t dev, int phy, int reg, int data) 44052527Sdavidn{ 44152527Sdavidn struct rl_softc *sc; 44220253Sjoerg u_int32_t rval; 44320253Sjoerg int i; 44420253Sjoerg 44552527Sdavidn sc = device_get_softc(dev); 44652527Sdavidn 44752527Sdavidn CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 44852527Sdavidn (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 44952527Sdavidn 45052527Sdavidn for (i = 0; i < RL_PHY_TIMEOUT; i++) { 45152527Sdavidn rval = CSR_READ_4(sc, RL_PHYAR); 45252527Sdavidn if (!(rval & RL_PHYAR_BUSY)) 45352527Sdavidn break; 45420253Sjoerg DELAY(100); 45552527Sdavidn } 45652527Sdavidn 45752527Sdavidn if (i == RL_PHY_TIMEOUT) { 45852527Sdavidn device_printf(sc->rl_dev, "PHY write failed\n"); 45952527Sdavidn return (0); 46052527Sdavidn } 46152527Sdavidn 46252527Sdavidn return (0); 46352527Sdavidn} 46420747Sdavidn 465130629Srobertstatic int 466130629Srobertre_miibus_readreg(device_t dev, int phy, int reg) 46720747Sdavidn{ 46820747Sdavidn struct rl_softc *sc; 46930259Scharnier u_int16_t rval = 0; 47020747Sdavidn u_int16_t re8139_reg = 0; 47130259Scharnier 47220747Sdavidn sc = device_get_softc(dev); 47320747Sdavidn 474124382Siedowse if (sc->rl_type == RL_8169) { 475124382Siedowse rval = re_gmii_readreg(dev, phy, reg); 47664918Sgreen return (rval); 47764918Sgreen } 47864918Sgreen 47964918Sgreen /* Pretend the internal PHY is only at address 0 */ 480252688Sdes if (phy) { 48164918Sgreen return (0); 48264918Sgreen } 48320267Sjoerg switch (reg) { 48452527Sdavidn case MII_BMCR: 48552527Sdavidn re8139_reg = RL_BMCR; 48620267Sjoerg break; 48720253Sjoerg case MII_BMSR: 48864918Sgreen re8139_reg = RL_BMSR; 48952527Sdavidn break; 49052527Sdavidn case MII_ANAR: 49152527Sdavidn re8139_reg = RL_ANAR; 49252527Sdavidn break; 49352527Sdavidn case MII_ANER: 494284128Sbapt re8139_reg = RL_ANER; 49530259Scharnier break; 496284128Sbapt case MII_ANLPAR: 497284128Sbapt re8139_reg = RL_LPAR; 49820253Sjoerg break; 49920253Sjoerg case MII_PHYIDR1: 50020253Sjoerg case MII_PHYIDR2: 50120253Sjoerg return (0); 50220253Sjoerg /* 503284128Sbapt * Allow the rlphy driver to read the media status 50420253Sjoerg * register. If we have a link partner which does not 505284133Sbapt * support NWAY, this is the register which will tell 506284118Sbapt * us the results of parallel detection. 50720253Sjoerg */ 50820253Sjoerg case RL_MEDIASTAT: 50920253Sjoerg rval = CSR_READ_1(sc, RL_MEDIASTAT); 51020253Sjoerg return (rval); 51164918Sgreen default: 512272833Sdes device_printf(sc->rl_dev, "bad phy register\n"); 51364918Sgreen return (0); 51464918Sgreen } 51564918Sgreen rval = CSR_READ_2(sc, re8139_reg); 51652527Sdavidn if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 51720253Sjoerg /* 8139C+ has different bit layout. */ 51820253Sjoerg rval &= ~(BMCR_LOOP | BMCR_ISO); 51930259Scharnier } 52020253Sjoerg return (rval); 52120253Sjoerg} 52220253Sjoerg 52320253Sjoergstatic int 52420253Sjoergre_miibus_writereg(device_t dev, int phy, int reg, int data) 52552527Sdavidn{ 526284110Sbapt struct rl_softc *sc; 52752527Sdavidn u_int16_t re8139_reg = 0; 52852527Sdavidn int rval = 0; 52952527Sdavidn 53052527Sdavidn sc = device_get_softc(dev); 53152527Sdavidn 53220253Sjoerg if (sc->rl_type == RL_8169) { 533124382Siedowse rval = re_gmii_writereg(dev, phy, reg, data); 534124382Siedowse return (rval); 53563572Sdavidn } 53663572Sdavidn 53763572Sdavidn /* Pretend the internal PHY is only at address 0 */ 53863572Sdavidn if (phy) 53963572Sdavidn return (0); 54063572Sdavidn 54120253Sjoerg switch (reg) { 542124382Siedowse case MII_BMCR: 54320253Sjoerg re8139_reg = RL_BMCR; 54420253Sjoerg if (sc->rl_type == RL_8139CPLUS) { 54520253Sjoerg /* 8139C+ has different bit layout. */ 54664918Sgreen data &= ~(BMCR_LOOP | BMCR_ISO); 54720253Sjoerg } 54820253Sjoerg break; 54920253Sjoerg case MII_BMSR: 55020253Sjoerg re8139_reg = RL_BMSR; 55120253Sjoerg break; 55220253Sjoerg case MII_ANAR: 55320253Sjoerg re8139_reg = RL_ANAR; 55420253Sjoerg break; 55520253Sjoerg case MII_ANER: 55620253Sjoerg re8139_reg = RL_ANER; 557124382Siedowse break; 558124382Siedowse case MII_ANLPAR: 559124382Siedowse re8139_reg = RL_LPAR; 560124382Siedowse break; 56120253Sjoerg case MII_PHYIDR1: 56220253Sjoerg case MII_PHYIDR2: 56320253Sjoerg return (0); 56420253Sjoerg break; 56520253Sjoerg default: 56620253Sjoerg device_printf(sc->rl_dev, "bad phy register\n"); 56720253Sjoerg return (0); 56820253Sjoerg } 56920253Sjoerg CSR_WRITE_2(sc, re8139_reg, data); 570283814Sbapt return (0); 571283814Sbapt} 572283814Sbapt 57320253Sjoergstatic void 574168045Slere_miibus_statchg(device_t dev) 57520253Sjoerg{ 57620253Sjoerg struct rl_softc *sc; 57730259Scharnier struct ifnet *ifp; 578124382Siedowse struct mii_data *mii; 579124382Siedowse 580124382Siedowse sc = device_get_softc(dev); 581124382Siedowse mii = device_get_softc(sc->rl_miibus); 582124382Siedowse ifp = sc->rl_ifp; 583124382Siedowse if (mii == NULL || ifp == NULL || 584124382Siedowse (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 585272833Sdes return; 586124382Siedowse 587124382Siedowse sc->rl_flags &= ~RL_FLAG_LINK; 588124382Siedowse if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 589124382Siedowse (IFM_ACTIVE | IFM_AVALID)) { 59052527Sdavidn switch (IFM_SUBTYPE(mii->mii_media_active)) { 59120253Sjoerg case IFM_10_T: 59220253Sjoerg case IFM_100_TX: 59320267Sjoerg sc->rl_flags |= RL_FLAG_LINK; 59420267Sjoerg break; 59520267Sjoerg case IFM_1000_T: 59620267Sjoerg if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 597284121Sbapt break; 598284126Sbapt sc->rl_flags |= RL_FLAG_LINK; 59920267Sjoerg break; 60021330Sdavidn default: 60152527Sdavidn break; 60252502Sdavidn } 603283814Sbapt } 604283814Sbapt /* 605283814Sbapt * RealTek controllers does not provide any interface to 606283814Sbapt * Tx/Rx MACs for resolved speed, duplex and flow-control 607283814Sbapt * parameters. 60852502Sdavidn */ 60952502Sdavidn} 61052502Sdavidn 61152502Sdavidn/* 61252502Sdavidn * Set the RX configuration and 64-bit multicast hash filter. 61356000Sdavidn */ 61452502Sdavidnstatic void 61552502Sdavidnre_set_rxmode(struct rl_softc *sc) 61652512Sdavidn{ 61752527Sdavidn struct ifnet *ifp; 618284128Sbapt struct ifmultiaddr *ifma; 619283814Sbapt uint32_t hashes[2] = { 0, 0 }; 620283814Sbapt uint32_t h, rxfilt; 621283814Sbapt 622283814Sbapt RL_LOCK_ASSERT(sc); 62352527Sdavidn 624284128Sbapt ifp = sc->rl_ifp; 62552527Sdavidn 62652527Sdavidn rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 62752527Sdavidn 62856000Sdavidn if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 62952527Sdavidn if (ifp->if_flags & IFF_PROMISC) 63052527Sdavidn rxfilt |= RL_RXCFG_RX_ALLPHYS; 63152502Sdavidn /* 63221330Sdavidn * Unlike other hardwares, we have to explicitly set 63321330Sdavidn * RL_RXCFG_RX_MULTI to receive multicast frames in 63420253Sjoerg * promiscuous mode. 63520253Sjoerg */ 63620253Sjoerg rxfilt |= RL_RXCFG_RX_MULTI; 63720253Sjoerg hashes[0] = hashes[1] = 0xffffffff; 638242349Sbapt goto done; 639273779Sbapt } 640273779Sbapt 641273779Sbapt IF_ADDR_LOCK(ifp); 642273779Sbapt TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 643273779Sbapt if (ifma->ifma_addr->sa_family != AF_LINK) 644273779Sbapt continue; 645273779Sbapt h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 646273779Sbapt ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 647273779Sbapt if (h < 32) 648273779Sbapt hashes[0] |= (1 << h); 649273779Sbapt else 650273779Sbapt hashes[1] |= (1 << (h - 32)); 651273779Sbapt } 652273779Sbapt IF_ADDR_UNLOCK(ifp); 653273779Sbapt 654273779Sbapt if (hashes[0] != 0 || hashes[1] != 0) { 655273779Sbapt /* 656273779Sbapt * For some unfathomable reason, RealTek decided to 657273779Sbapt * reverse the order of the multicast hash registers 658242349Sbapt * in the PCI Express parts. This means we have to 659242349Sbapt * write the hash pattern in reverse order for those 660244737Sbapt * devices. 661244737Sbapt */ 662244737Sbapt if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 663244737Sbapt h = bswap32(hashes[0]); 664244737Sbapt hashes[0] = bswap32(hashes[1]); 665244737Sbapt hashes[1] = h; 666244737Sbapt } 667244737Sbapt rxfilt |= RL_RXCFG_RX_MULTI; 668242349Sbapt } 669242349Sbapt 670245114Smjgdone: 671242349Sbapt CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 672242349Sbapt CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 673242349Sbapt CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 674242349Sbapt} 67561759Sdavidn 676284128Sbaptstatic void 67761759Sdavidnre_reset(struct rl_softc *sc) 67861759Sdavidn{ 679284129Sbapt int i; 680284129Sbapt 681284128Sbapt RL_LOCK_ASSERT(sc); 68261759Sdavidn 68361759Sdavidn CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 68461759Sdavidn 685284128Sbapt for (i = 0; i < RL_TIMEOUT; i++) { 68620253Sjoerg DELAY(10); 68744229Sdavidn if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 688283842Sbapt break; 689283842Sbapt } 690283842Sbapt if (i == RL_TIMEOUT) 69120253Sjoerg device_printf(sc->rl_dev, "reset never completed!\n"); 69220253Sjoerg 69320253Sjoerg if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 69420253Sjoerg CSR_WRITE_1(sc, 0x82, 1); 69520253Sjoerg if (sc->rl_hwrev == RL_HWREV_8169S) 69620253Sjoerg re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 69720253Sjoerg} 69820253Sjoerg 699283961Sbapt#ifdef RE_DIAG 700283961Sbapt 701283961Sbapt/* 702283961Sbapt * The following routine is designed to test for a defect on some 703283961Sbapt * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 70444229Sdavidn * lines connected to the bus, however for a 32-bit only card, they 705283961Sbapt * should be pulled high. The result of this defect is that the 70620253Sjoerg * NIC will not work right if you plug it into a 64-bit slot: DMA 70720253Sjoerg * operations will be done with 64-bit transfers, which will fail 70852527Sdavidn * because the 64-bit data lines aren't connected. 70920253Sjoerg * 71082868Sdd * There's no way to work around this (short of talking a soldering 71120253Sjoerg * iron to the board), however we can detect it. The method we use 71220253Sjoerg * here is to put the NIC into digital loopback mode, set the receiver 71320253Sjoerg * to promiscuous mode, and then try to send a frame. We then compare 714283961Sbapt * the frame data we sent to what was received. If the data matches, 715283961Sbapt * then the NIC is working correctly, otherwise we know the user has 716284118Sbapt * a defective NIC which has been mistakenly plugged into a 64-bit PCI 71752527Sdavidn * slot. In the latter case, there's no way the NIC can work correctly, 71882868Sdd * so we print out a message on the console and abort the device attach. 71982868Sdd */ 72082868Sdd 72182868Sddstatic int 72282868Sddre_diag(struct rl_softc *sc) 72382868Sdd{ 72482868Sdd struct ifnet *ifp = sc->rl_ifp; 72582868Sdd struct mbuf *m0; 72682868Sdd struct ether_header *eh; 72782868Sdd struct rl_desc *cur_rx; 72882868Sdd u_int16_t status; 72982868Sdd u_int32_t rxstat; 73082868Sdd int total_len, i, error = 0, phyaddr; 73182868Sdd u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 73282868Sdd u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 733283842Sbapt 734283842Sbapt /* Allocate a single mbuf */ 73582868Sdd MGETHDR(m0, M_DONTWAIT, MT_DATA); 73682868Sdd if (m0 == NULL) 73782868Sdd return (ENOBUFS); 73882868Sdd 73920267Sjoerg RL_LOCK(sc); 74020253Sjoerg 74120253Sjoerg /* 74220253Sjoerg * Initialize the NIC in test mode. This sets the chip up 74320253Sjoerg * so that it can send and receive frames, but performs the 744284133Sbapt * following special functions: 74520253Sjoerg * - Puts receiver in promiscuous mode 74620253Sjoerg * - Enables digital loopback mode 74720253Sjoerg * - Leaves interrupts turned off 74820253Sjoerg */ 74920253Sjoerg 75020253Sjoerg ifp->if_flags |= IFF_PROMISC; 75120253Sjoerg sc->rl_testmode = 1; 752284133Sbapt re_init_locked(sc); 753284133Sbapt sc->rl_flags |= RL_FLAG_LINK; 75420253Sjoerg if (sc->rl_type == RL_8169) 755284133Sbapt phyaddr = 1; 756283842Sbapt else 75720253Sjoerg phyaddr = 0; 75820253Sjoerg 75920253Sjoerg re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 76020253Sjoerg for (i = 0; i < RL_TIMEOUT; i++) { 76120253Sjoerg status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 76220253Sjoerg if (!(status & BMCR_RESET)) 76320253Sjoerg break; 76420253Sjoerg } 76520253Sjoerg 76620253Sjoerg re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 76720253Sjoerg CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 76820253Sjoerg 76920253Sjoerg DELAY(100000); 77020253Sjoerg 77120253Sjoerg /* Put some data in the mbuf */ 77220253Sjoerg 77320253Sjoerg eh = mtod(m0, struct ether_header *); 77420253Sjoerg bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 77544229Sdavidn bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 77644229Sdavidn eh->ether_type = htons(ETHERTYPE_IP); 77744229Sdavidn m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 77820253Sjoerg 77944229Sdavidn /* 78020253Sjoerg * Queue the packet, start transmission. 78120253Sjoerg * Note: IF_HANDOFF() ultimately calls re_start() for us. 78220253Sjoerg */ 78320253Sjoerg 78420253Sjoerg CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 78520253Sjoerg RL_UNLOCK(sc); 78620253Sjoerg /* XXX: re_diag must not be called when in ALTQ mode */ 78720253Sjoerg IF_HANDOFF(&ifp->if_snd, m0, ifp); 78820253Sjoerg RL_LOCK(sc); 78920253Sjoerg m0 = NULL; 79020253Sjoerg 79130259Scharnier /* Wait for it to propagate through the chip */ 79220253Sjoerg 79320253Sjoerg DELAY(100000); 79420253Sjoerg for (i = 0; i < RL_TIMEOUT; i++) { 79520253Sjoerg status = CSR_READ_2(sc, RL_ISR); 79620253Sjoerg CSR_WRITE_2(sc, RL_ISR, status); 79720253Sjoerg if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 79820253Sjoerg (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 799284118Sbapt break; 80020253Sjoerg DELAY(10); 80120253Sjoerg } 80220253Sjoerg 80320253Sjoerg if (i == RL_TIMEOUT) { 804284118Sbapt device_printf(sc->rl_dev, 80520253Sjoerg "diagnostic failed, failed to receive packet in" 80620253Sjoerg " loopback mode\n"); 80720253Sjoerg error = EIO; 80820253Sjoerg goto done; 80920253Sjoerg } 81020253Sjoerg 81120253Sjoerg /* 81220253Sjoerg * The packet should have been dumped into the first 81320253Sjoerg * entry in the RX DMA ring. Grab it from there. 81420253Sjoerg */ 81544229Sdavidn 81620253Sjoerg bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 81744229Sdavidn sc->rl_ldata.rl_rx_list_map, 81820253Sjoerg BUS_DMASYNC_POSTREAD); 81961957Sache bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 82030259Scharnier sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 82120253Sjoerg BUS_DMASYNC_POSTREAD); 82220253Sjoerg bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 823262865Sjulian sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 824262865Sjulian 82520267Sjoerg m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 82620253Sjoerg sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 82720253Sjoerg eh = mtod(m0, struct ether_header *); 82820253Sjoerg 82920253Sjoerg cur_rx = &sc->rl_ldata.rl_rx_list[0]; 83020253Sjoerg total_len = RL_RXBYTES(cur_rx); 83120253Sjoerg rxstat = le32toh(cur_rx->rl_cmdstat); 83220253Sjoerg 83320253Sjoerg if (total_len != ETHER_MIN_LEN) { 83420253Sjoerg device_printf(sc->rl_dev, 83520253Sjoerg "diagnostic failed, received short packet\n"); 83620253Sjoerg error = EIO; 83720253Sjoerg goto done; 83820253Sjoerg } 83920253Sjoerg 84020253Sjoerg /* Test that the received packet data matches what we sent. */ 84144229Sdavidn 842282700Sbapt if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 84320253Sjoerg bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 84420253Sjoerg ntohs(eh->ether_type) != ETHERTYPE_IP) { 845284121Sbapt device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 84620267Sjoerg device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 847284128Sbapt dst, ":", src, ":", ETHERTYPE_IP); 84820267Sjoerg device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 84920267Sjoerg eh->ether_dhost, ":", eh->ether_shost, ":", 85020267Sjoerg ntohs(eh->ether_type)); 851284128Sbapt device_printf(sc->rl_dev, "You may have a defective 32-bit " 85244229Sdavidn "NIC plugged into a 64-bit PCI slot.\n"); 85320267Sjoerg device_printf(sc->rl_dev, "Please re-install the NIC in a " 85420267Sjoerg "32-bit slot for proper operation.\n"); 85570486Sben device_printf(sc->rl_dev, "Read the re(4) man page for more " 85620253Sjoerg "details.\n"); 85770486Sben error = EIO; 85820253Sjoerg } 85920253Sjoerg 86020253Sjoergdone: 86120253Sjoerg /* Turn interface off, release resources */ 86244229Sdavidn 86320253Sjoerg sc->rl_testmode = 0; 86420253Sjoerg sc->rl_flags &= ~RL_FLAG_LINK; 86520253Sjoerg ifp->if_flags &= ~IFF_PROMISC; 86620253Sjoerg re_stop(sc); 86720253Sjoerg if (m0 != NULL) 86820253Sjoerg m_freem(m0); 86920253Sjoerg 87020253Sjoerg RL_UNLOCK(sc); 87120253Sjoerg 87227831Sdavidn return (error); 87320253Sjoerg} 87420253Sjoerg 87520253Sjoerg#endif 87630259Scharnier 87720253Sjoerg/* 87820253Sjoerg * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 87920253Sjoerg * IDs against our list and return a device name if we find a match. 88020253Sjoerg */ 88120253Sjoergstatic int 88220253Sjoergre_probe(device_t dev) 88320253Sjoerg{ 88420253Sjoerg struct rl_type *t; 88520253Sjoerg uint16_t devid, vendor; 88620253Sjoerg uint16_t revid, sdevid; 88720253Sjoerg int i; 88820253Sjoerg 88920253Sjoerg vendor = pci_get_vendor(dev); 89020253Sjoerg devid = pci_get_device(dev); 89120253Sjoerg revid = pci_get_revid(dev); 89230259Scharnier sdevid = pci_get_subdevice(dev); 89320253Sjoerg 89420253Sjoerg if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 89520253Sjoerg if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 89620253Sjoerg /* 89720253Sjoerg * Only attach to rev. 3 of the Linksys EG1032 adapter. 89820253Sjoerg * Rev. 2 is supported by sk(4). 89920253Sjoerg */ 90020253Sjoerg return (ENXIO); 90120253Sjoerg } 90220253Sjoerg } 903282699Sbapt 90420253Sjoerg if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 90520253Sjoerg if (revid != 0x20) { 906282699Sbapt /* 8139, let rl(4) take care of this device. */ 90720253Sjoerg return (ENXIO); 908282699Sbapt } 909282699Sbapt } 910282699Sbapt 911282699Sbapt t = re_devs; 912282699Sbapt for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 91320253Sjoerg if (vendor == t->rl_vid && devid == t->rl_did) { 91420253Sjoerg device_set_desc(dev, t->rl_name); 91520253Sjoerg return (BUS_PROBE_DEFAULT); 91620253Sjoerg } 91720253Sjoerg } 91820253Sjoerg 91920253Sjoerg return (ENXIO); 92020253Sjoerg} 92120253Sjoerg 92220253Sjoerg/* 92320253Sjoerg * Map a single buffer address. 92420253Sjoerg */ 92520253Sjoerg 92620253Sjoergstatic void 927130633Srobertre_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 92820253Sjoerg{ 92920253Sjoerg bus_addr_t *addr; 93020253Sjoerg 93120253Sjoerg if (error) 93220253Sjoerg return; 933282700Sbapt 93420253Sjoerg KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 93520253Sjoerg addr = arg; 93620253Sjoerg *addr = segs->ds_addr; 93720253Sjoerg} 938282700Sbapt 93920253Sjoergstatic int 94020253Sjoergre_allocmem(device_t dev, struct rl_softc *sc) 94120253Sjoerg{ 94220253Sjoerg bus_size_t rx_list_size, tx_list_size; 94320253Sjoerg int error; 94430259Scharnier int i; 94530259Scharnier 94620253Sjoerg rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 94720253Sjoerg tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 94820253Sjoerg 94920253Sjoerg /* 95020253Sjoerg * Allocate the parent bus DMA tag appropriate for PCI. 95120253Sjoerg * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 95220253Sjoerg * register should be set. However some RealTek chips are known 95320253Sjoerg * to be buggy on DAC handling, therefore disable DAC by limiting 95420253Sjoerg * DMA address space to 32bit. PCIe variants of RealTek chips 95520253Sjoerg * may not have the limitation but I took safer path. 95620253Sjoerg */ 95720253Sjoerg error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 95820253Sjoerg BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 95920253Sjoerg BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 96020253Sjoerg NULL, NULL, &sc->rl_parent_tag); 96120253Sjoerg if (error) { 962179365Santoine device_printf(dev, "could not allocate parent DMA tag\n"); 96320253Sjoerg return (error); 964179365Santoine } 965179365Santoine 96620253Sjoerg /* 96720253Sjoerg * Allocate map for TX mbufs. 96820253Sjoerg */ 96920253Sjoerg error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 970179365Santoine BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 971231994Skevlo NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 97220253Sjoerg NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 97320253Sjoerg if (error) { 97420253Sjoerg device_printf(dev, "could not allocate TX DMA tag\n"); 97520253Sjoerg return (error); 97620253Sjoerg } 97720253Sjoerg 978179365Santoine /* 979181785Sache * Allocate map for RX mbufs. 980179365Santoine */ 98120253Sjoerg 982231994Skevlo error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 983231994Skevlo BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 984231994Skevlo MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 985231994Skevlo if (error) { 98620253Sjoerg device_printf(dev, "could not allocate RX DMA tag\n"); 98720253Sjoerg return (error); 98820590Sdavidn } 98920253Sjoerg 99020253Sjoerg /* 99120253Sjoerg * Allocate map for TX descriptor list. 99220253Sjoerg */ 99320253Sjoerg error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 99420253Sjoerg 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 99520253Sjoerg NULL, tx_list_size, 1, tx_list_size, 0, 99620253Sjoerg NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 99773563Skris if (error) { 99820253Sjoerg device_printf(dev, "could not allocate TX DMA ring tag\n"); 999181785Sache return (error); 100020253Sjoerg } 100120253Sjoerg 100220253Sjoerg /* Allocate DMA'able memory for the TX ring */ 100320253Sjoerg 100420253Sjoerg error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1005124382Siedowse (void **)&sc->rl_ldata.rl_tx_list, 1006284121Sbapt BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 100761957Sache &sc->rl_ldata.rl_tx_list_map); 100820712Sdavidn if (error) { 100920253Sjoerg device_printf(dev, "could not allocate TX DMA ring\n"); 101020253Sjoerg return (error); 101120253Sjoerg } 101220253Sjoerg 101320253Sjoerg /* Load the map for the TX ring. */ 101420253Sjoerg 101520253Sjoerg sc->rl_ldata.rl_tx_list_addr = 0; 101620253Sjoerg error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 101720253Sjoerg sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 101820253Sjoerg tx_list_size, re_dma_map_addr, 101920253Sjoerg &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 102020253Sjoerg if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 102120253Sjoerg device_printf(dev, "could not load TX DMA ring\n"); 1022130633Srobert return (ENOMEM); 102320253Sjoerg } 102420253Sjoerg 102520253Sjoerg /* Create DMA maps for TX buffers */ 102620253Sjoerg 102720253Sjoerg for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1028284111Sbapt error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1029284128Sbapt &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1030284111Sbapt if (error) { 1031284111Sbapt device_printf(dev, "could not create DMA map for TX\n"); 1032284111Sbapt return (error); 1033284111Sbapt } 1034284111Sbapt } 1035284111Sbapt 1036284111Sbapt /* 1037284111Sbapt * Allocate map for RX descriptor list. 1038284111Sbapt */ 103920253Sjoerg error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1040284111Sbapt 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1041284111Sbapt NULL, rx_list_size, 1, rx_list_size, 0, 1042284111Sbapt NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1043284111Sbapt if (error) { 1044284111Sbapt device_printf(dev, "could not create RX DMA ring tag\n"); 1045284111Sbapt return (error); 1046284111Sbapt } 1047284111Sbapt 1048284111Sbapt /* Allocate DMA'able memory for the RX ring */ 1049284111Sbapt 1050284111Sbapt error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1051284111Sbapt (void **)&sc->rl_ldata.rl_rx_list, 1052284111Sbapt BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1053284111Sbapt &sc->rl_ldata.rl_rx_list_map); 1054284111Sbapt if (error) { 1055284111Sbapt device_printf(dev, "could not allocate RX DMA ring\n"); 1056284111Sbapt return (error); 1057284111Sbapt } 1058284111Sbapt 1059284111Sbapt /* Load the map for the RX ring. */ 1060284111Sbapt 1061284111Sbapt sc->rl_ldata.rl_rx_list_addr = 0; 1062284111Sbapt error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1063284111Sbapt sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1064284111Sbapt rx_list_size, re_dma_map_addr, 1065284111Sbapt &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1066284111Sbapt if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1067284111Sbapt device_printf(dev, "could not load RX DMA ring\n"); 1068284111Sbapt return (ENOMEM); 1069284111Sbapt } 1070284111Sbapt 1071284111Sbapt /* Create DMA maps for RX buffers */ 1072284111Sbapt 1073284111Sbapt error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1074284111Sbapt &sc->rl_ldata.rl_rx_sparemap); 1075284111Sbapt if (error) { 1076284111Sbapt device_printf(dev, "could not create spare DMA map for RX\n"); 1077284111Sbapt return (error); 1078284128Sbapt } 1079284111Sbapt for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1080284111Sbapt error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1081284111Sbapt &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1082284111Sbapt if (error) { 1083284111Sbapt device_printf(dev, "could not create DMA map for RX\n"); 1084284111Sbapt return (error); 1085284111Sbapt } 1086284128Sbapt } 1087284111Sbapt 1088284111Sbapt return (0); 1089284128Sbapt} 1090284128Sbapt 1091284111Sbapt/* 1092284111Sbapt * Attach the interface. Allocate softc structures, do ifmedia 1093284111Sbapt * setup and ethernet/BPF attach. 1094284111Sbapt */ 1095284113Sbaptstatic int 1096284113Sbaptre_attach(device_t dev) 1097284113Sbapt{ 1098284113Sbapt u_char eaddr[ETHER_ADDR_LEN]; 1099284128Sbapt u_int16_t as[ETHER_ADDR_LEN / 2]; 1100284113Sbapt struct rl_softc *sc; 1101284113Sbapt struct ifnet *ifp; 1102284113Sbapt struct rl_hwrev *hw_rev; 1103284113Sbapt int hwrev; 1104284113Sbapt u_int16_t devid, re_did = 0; 1105284113Sbapt int error = 0, rid, i; 1106284111Sbapt int msic, reg; 1107284111Sbapt uint8_t cfg; 1108284111Sbapt 1109284111Sbapt sc = device_get_softc(dev); 1110284128Sbapt sc->rl_dev = dev; 1111284111Sbapt 1112284117Sbapt mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1113284111Sbapt MTX_DEF); 1114284111Sbapt callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1115284111Sbapt 1116284111Sbapt /* 1117284111Sbapt * Map control/status registers. 1118284111Sbapt */ 1119284111Sbapt pci_enable_busmaster(dev); 1120284111Sbapt 1121284111Sbapt devid = pci_get_device(dev); 1122284111Sbapt /* 1123284111Sbapt * Prefer memory space register mapping over IO space. 1124284111Sbapt * Because RTL8169SC does not seem to work when memory mapping 1125284111Sbapt * is used always activate io mapping. 1126284111Sbapt */ 1127284112Sbapt if (devid == RT_DEVICEID_8169SC) 1128284112Sbapt prefer_iomap = 1; 1129284112Sbapt if (prefer_iomap == 0) { 1130284112Sbapt sc->rl_res_id = PCIR_BAR(1); 1131284128Sbapt sc->rl_res_type = SYS_RES_MEMORY; 1132284112Sbapt /* RTL8168/8101E seems to use different BARs. */ 1133284111Sbapt if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1134284111Sbapt sc->rl_res_id = PCIR_BAR(2); 1135284111Sbapt } else { 1136284111Sbapt sc->rl_res_id = PCIR_BAR(0); 1137284111Sbapt sc->rl_res_type = SYS_RES_IOPORT; 1138284111Sbapt } 113920253Sjoerg sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1140284124Sbapt &sc->rl_res_id, RF_ACTIVE); 114120253Sjoerg if (sc->rl_res == NULL && prefer_iomap == 0) { 1142284122Sbapt sc->rl_res_id = PCIR_BAR(0); 1143242349Sbapt sc->rl_res_type = SYS_RES_IOPORT; 114420253Sjoerg sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1145284124Sbapt &sc->rl_res_id, RF_ACTIVE); 1146242349Sbapt } 1147242349Sbapt if (sc->rl_res == NULL) { 114820253Sjoerg device_printf(dev, "couldn't map ports/memory\n"); 114920267Sjoerg error = ENXIO; 115020253Sjoerg goto fail; 115144229Sdavidn } 115220253Sjoerg 115320253Sjoerg sc->rl_btag = rman_get_bustag(sc->rl_res); 115420590Sdavidn sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 115520590Sdavidn 115620253Sjoerg msic = 0; 115720253Sjoerg if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1158130633Srobert sc->rl_flags |= RL_FLAG_PCIE; 115920253Sjoerg msic = pci_msi_count(dev); 1160130633Srobert if (bootverbose) 116120253Sjoerg device_printf(dev, "MSI count : %d\n", msic); 1162130633Srobert } 116320253Sjoerg if (msic > 0 && msi_disable == 0) { 1164130633Srobert msic = 1; 1165130633Srobert if (pci_alloc_msi(dev, &msic) == 0) { 116620253Sjoerg if (msic == RL_MSI_MESSAGES) { 116720253Sjoerg device_printf(dev, "Using %d MSI messages\n", 116820253Sjoerg msic); 116920253Sjoerg sc->rl_flags |= RL_FLAG_MSI; 117020253Sjoerg /* Explicitly set MSI enable bit. */ 117120253Sjoerg CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 117220253Sjoerg cfg = CSR_READ_1(sc, RL_CFG2); 117320253Sjoerg cfg |= RL_CFG2_MSI; 117420253Sjoerg CSR_WRITE_1(sc, RL_CFG2, cfg); 117520253Sjoerg CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 117620253Sjoerg } else 117720253Sjoerg pci_release_msi(dev); 117820253Sjoerg } 117961957Sache } 118020253Sjoerg 118120590Sdavidn /* Allocate interrupt */ 118274569Sache if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 118361957Sache rid = 0; 118474569Sache sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1185283842Sbapt RF_SHAREABLE | RF_ACTIVE); 118620747Sdavidn if (sc->rl_irq[0] == NULL) { 118720747Sdavidn device_printf(dev, "couldn't allocate IRQ resources\n"); 118820747Sdavidn error = ENXIO; 118920747Sdavidn goto fail; 119020747Sdavidn } 1191283842Sbapt } else { 1192283842Sbapt for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 119320253Sjoerg sc->rl_irq[i] = bus_alloc_resource_any(dev, 119420590Sdavidn SYS_RES_IRQ, &rid, RF_ACTIVE); 119520590Sdavidn if (sc->rl_irq[i] == NULL) { 119644229Sdavidn device_printf(dev, 119720267Sjoerg "couldn't llocate IRQ resources for " 119844229Sdavidn "message %d\n", rid); 119920267Sjoerg error = ENXIO; 120020267Sjoerg goto fail; 1201262865Sjulian } 1202262865Sjulian } 120320267Sjoerg } 1204262865Sjulian 1205262865Sjulian if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1206262865Sjulian CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1207262865Sjulian cfg = CSR_READ_1(sc, RL_CFG2); 1208262865Sjulian if ((cfg & RL_CFG2_MSI) != 0) { 1209262865Sjulian device_printf(dev, "turning off MSI enable bit.\n"); 121020267Sjoerg cfg &= ~RL_CFG2_MSI; 121120267Sjoerg CSR_WRITE_1(sc, RL_CFG2, cfg); 121220267Sjoerg } 121344229Sdavidn CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 121461957Sache } 121520253Sjoerg 121620267Sjoerg /* Reset the adapter. */ 121720253Sjoerg RL_LOCK(sc); 121820253Sjoerg re_reset(sc); 1219284110Sbapt RL_UNLOCK(sc); 1220284110Sbapt 122120253Sjoerg hw_rev = re_hwrevs; 1222109961Sgad hwrev = CSR_READ_4(sc, RL_TXCFG); 1223284110Sbapt switch (hwrev & 0x70000000) { 1224109961Sgad case 0x00000000: 122520253Sjoerg case 0x10000000: 1226109961Sgad device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1227109961Sgad hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1228109961Sgad break; 1229109961Sgad default: 1230109961Sgad device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1231109961Sgad hwrev &= RL_TXCFG_HWREV; 1232109961Sgad break; 1233109961Sgad } 1234109961Sgad device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1235109961Sgad while (hw_rev->rl_desc != NULL) { 1236109961Sgad if (hw_rev->rl_rev == hwrev) { 1237109961Sgad sc->rl_type = hw_rev->rl_type; 1238109961Sgad sc->rl_hwrev = hw_rev->rl_rev; 123920253Sjoerg break; 1240109961Sgad } 1241109961Sgad hw_rev++; 1242109961Sgad } 1243109961Sgad if (hw_rev->rl_desc == NULL) { 1244109961Sgad device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1245109961Sgad error = ENXIO; 1246109961Sgad goto fail; 1247109961Sgad } 1248109961Sgad 1249109961Sgad switch (hw_rev->rl_rev) { 1250109961Sgad case RL_HWREV_8139CPLUS: 1251109961Sgad sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER; 1252109961Sgad break; 1253109961Sgad case RL_HWREV_8100E: 1254109961Sgad case RL_HWREV_8101E: 1255109961Sgad sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1256109961Sgad RL_FLAG_FASTETHER; 1257109961Sgad break; 1258109961Sgad case RL_HWREV_8102E: 1259109961Sgad case RL_HWREV_8102EL: 1260109961Sgad sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1261109961Sgad RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1262109961Sgad RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP; 1263109961Sgad break; 1264109961Sgad case RL_HWREV_8168_SPIN1: 1265109961Sgad case RL_HWREV_8168_SPIN2: 1266109961Sgad sc->rl_flags |= RL_FLAG_WOLRXENB; 1267109961Sgad /* FALLTHROUGH */ 1268228673Sdim case RL_HWREV_8168_SPIN3: 1269109961Sgad sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1270109961Sgad break; 1271109961Sgad case RL_HWREV_8168C_SPIN2: 1272109961Sgad sc->rl_flags |= RL_FLAG_MACSLEEP; 1273109961Sgad /* FALLTHROUGH */ 1274284110Sbapt case RL_HWREV_8168C: 1275284110Sbapt if ((hwrev & 0x00700000) == 0x00200000) 127620253Sjoerg sc->rl_flags |= RL_FLAG_MACSLEEP; 127720253Sjoerg /* FALLTHROUGH */ 127820253Sjoerg case RL_HWREV_8168CP: 127920253Sjoerg case RL_HWREV_8168D: 128020253Sjoerg sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 128120253Sjoerg RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP; 128220253Sjoerg /* 128320253Sjoerg * These controllers support jumbo frame but it seems 128420253Sjoerg * that enabling it requires touching additional magic 128520253Sjoerg * registers. Depending on MAC revisions some 128620253Sjoerg * controllers need to disable checksum offload. So 128720253Sjoerg * disable jumbo frame until I have better idea what 128820253Sjoerg * it really requires to make it support. 128920253Sjoerg * RTL8168C/CP : supports up to 6KB jumbo frame. 129020253Sjoerg * RTL8111C/CP : supports up to 9KB jumbo frame. 129120253Sjoerg */ 129220253Sjoerg sc->rl_flags |= RL_FLAG_NOJUMBO; 129320253Sjoerg break; 129420253Sjoerg case RL_HWREV_8169_8110SB: 129520253Sjoerg case RL_HWREV_8169_8110SBL: 1296282700Sbapt case RL_HWREV_8169_8110SC: 129720253Sjoerg case RL_HWREV_8169_8110SCE: 129820253Sjoerg sc->rl_flags |= RL_FLAG_PHYWAKE; 129920253Sjoerg /* FALLTHROUGH */ 130020253Sjoerg case RL_HWREV_8169: 130120253Sjoerg case RL_HWREV_8169S: 130220253Sjoerg case RL_HWREV_8110S: 130320747Sdavidn sc->rl_flags |= RL_FLAG_MACRESET; 130420747Sdavidn break; 130585145Sache default: 130620747Sdavidn break; 130785145Sache } 130885145Sache 130920747Sdavidn /* Enable PME. */ 131021052Sdavidn CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 131121052Sdavidn cfg = CSR_READ_1(sc, RL_CFG1); 131221052Sdavidn cfg |= RL_CFG1_PME; 131321052Sdavidn CSR_WRITE_1(sc, RL_CFG1, cfg); 131420747Sdavidn cfg = CSR_READ_1(sc, RL_CFG5); 131521052Sdavidn cfg &= RL_CFG5_PME_STS; 131621052Sdavidn CSR_WRITE_1(sc, RL_CFG5, cfg); 131721052Sdavidn CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 131821052Sdavidn 131921052Sdavidn if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 132021052Sdavidn /* 132120747Sdavidn * XXX Should have a better way to extract station 132221052Sdavidn * address from EEPROM. 132320747Sdavidn */ 132421052Sdavidn for (i = 0; i < ETHER_ADDR_LEN; i++) 132521052Sdavidn eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 132621052Sdavidn } else { 132721052Sdavidn sc->rl_eewidth = RL_9356_ADDR_LEN; 132820747Sdavidn re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 132920747Sdavidn if (re_did != 0x8129) 133020747Sdavidn sc->rl_eewidth = RL_9346_ADDR_LEN; 1331 1332 /* 1333 * Get station address from the EEPROM. 1334 */ 1335 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1336 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1337 as[i] = le16toh(as[i]); 1338 bcopy(as, eaddr, sizeof(eaddr)); 1339 } 1340 1341 if (sc->rl_type == RL_8169) { 1342 /* Set RX length mask and number of descriptors. */ 1343 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1344 sc->rl_txstart = RL_GTXSTART; 1345 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1346 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1347 } else { 1348 /* Set RX length mask and number of descriptors. */ 1349 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1350 sc->rl_txstart = RL_TXSTART; 1351 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1352 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1353 } 1354 1355 error = re_allocmem(dev, sc); 1356 if (error) 1357 goto fail; 1358 1359 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1360 if (ifp == NULL) { 1361 device_printf(dev, "can not if_alloc()\n"); 1362 error = ENOSPC; 1363 goto fail; 1364 } 1365 1366 /* Take controller out of deep sleep mode. */ 1367 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1368 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1369 CSR_WRITE_1(sc, RL_GPIO, 1370 CSR_READ_1(sc, RL_GPIO) | 0x01); 1371 else 1372 CSR_WRITE_1(sc, RL_GPIO, 1373 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1374 } 1375 1376 /* Take PHY out of power down mode. */ 1377 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1378 re_gmii_writereg(dev, 1, 0x1f, 0); 1379 re_gmii_writereg(dev, 1, 0x0e, 0); 1380 } 1381 1382 /* Do MII setup */ 1383 if (mii_phy_probe(dev, &sc->rl_miibus, 1384 re_ifmedia_upd, re_ifmedia_sts)) { 1385 device_printf(dev, "MII without any phy!\n"); 1386 error = ENXIO; 1387 goto fail; 1388 } 1389 1390 ifp->if_softc = sc; 1391 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1392 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1393 ifp->if_ioctl = re_ioctl; 1394 ifp->if_start = re_start; 1395 ifp->if_hwassist = RE_CSUM_FEATURES; 1396 ifp->if_capabilities = IFCAP_HWCSUM; 1397 ifp->if_capenable = ifp->if_capabilities; 1398 ifp->if_init = re_init; 1399 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1400 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1401 IFQ_SET_READY(&ifp->if_snd); 1402 1403 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1404 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1405 1406 /* 1407 * XXX 1408 * Still have no idea how to make TSO work on 8168C, 8168CP, 1409 * 8111C and 8111CP. 1410 */ 1411 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1412 ifp->if_hwassist |= CSUM_TSO; 1413 ifp->if_capabilities |= IFCAP_TSO4; 1414 } 1415 1416 /* 1417 * Call MI attach routine. 1418 */ 1419 ether_ifattach(ifp, eaddr); 1420 1421 /* VLAN capability setup */ 1422 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1423 if (ifp->if_capabilities & IFCAP_HWCSUM) 1424 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1425 /* Enable WOL if PM is supported. */ 1426 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1427 ifp->if_capabilities |= IFCAP_WOL; 1428 ifp->if_capenable = ifp->if_capabilities; 1429 /* 1430 * Don't enable TSO by default. Under certain 1431 * circumtances the controller generated corrupted 1432 * packets in TSO size. 1433 */ 1434 ifp->if_hwassist &= ~CSUM_TSO; 1435 ifp->if_capenable &= ~IFCAP_TSO4; 1436#ifdef DEVICE_POLLING 1437 ifp->if_capabilities |= IFCAP_POLLING; 1438#endif 1439 /* 1440 * Tell the upper layer(s) we support long frames. 1441 * Must appear after the call to ether_ifattach() because 1442 * ether_ifattach() sets ifi_hdrlen to the default value. 1443 */ 1444 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1445 1446#ifdef RE_DIAG 1447 /* 1448 * Perform hardware diagnostic on the original RTL8169. 1449 * Some 32-bit cards were incorrectly wired and would 1450 * malfunction if plugged into a 64-bit slot. 1451 */ 1452 1453 if (hwrev == RL_HWREV_8169) { 1454 error = re_diag(sc); 1455 if (error) { 1456 device_printf(dev, 1457 "attach aborted due to hardware diag failure\n"); 1458 ether_ifdetach(ifp); 1459 goto fail; 1460 } 1461 } 1462#endif 1463 1464 /* Hook interrupt last to avoid having to lock softc */ 1465 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1466 error = bus_setup_intr(dev, sc->rl_irq[0], 1467 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1468 &sc->rl_intrhand[0]); 1469 else { 1470 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1471 error = bus_setup_intr(dev, sc->rl_irq[i], 1472 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1473 &sc->rl_intrhand[i]); 1474 if (error != 0) 1475 break; 1476 } 1477 } 1478 if (error) { 1479 device_printf(dev, "couldn't set up irq\n"); 1480 ether_ifdetach(ifp); 1481 } 1482 1483fail: 1484 1485 if (error) 1486 re_detach(dev); 1487 1488 return (error); 1489} 1490 1491/* 1492 * Shutdown hardware and free up resources. This can be called any 1493 * time after the mutex has been initialized. It is called in both 1494 * the error case in attach and the normal detach case so it needs 1495 * to be careful about only freeing resources that have actually been 1496 * allocated. 1497 */ 1498static int 1499re_detach(device_t dev) 1500{ 1501 struct rl_softc *sc; 1502 struct ifnet *ifp; 1503 int i, rid; 1504 1505 sc = device_get_softc(dev); 1506 ifp = sc->rl_ifp; 1507 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1508 1509 /* These should only be active if attach succeeded */ 1510 if (device_is_attached(dev)) { 1511#ifdef DEVICE_POLLING 1512 if (ifp->if_capenable & IFCAP_POLLING) 1513 ether_poll_deregister(ifp); 1514#endif 1515 RL_LOCK(sc); 1516#if 0 1517 sc->suspended = 1; 1518#endif 1519 re_stop(sc); 1520 RL_UNLOCK(sc); 1521 callout_drain(&sc->rl_stat_callout); 1522 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1523 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1524 /* 1525 * Force off the IFF_UP flag here, in case someone 1526 * still had a BPF descriptor attached to this 1527 * interface. If they do, ether_ifdetach() will cause 1528 * the BPF code to try and clear the promisc mode 1529 * flag, which will bubble down to re_ioctl(), 1530 * which will try to call re_init() again. This will 1531 * turn the NIC back on and restart the MII ticker, 1532 * which will panic the system when the kernel tries 1533 * to invoke the re_tick() function that isn't there 1534 * anymore. 1535 */ 1536 ifp->if_flags &= ~IFF_UP; 1537 ether_ifdetach(ifp); 1538 } 1539 if (sc->rl_miibus) 1540 device_delete_child(dev, sc->rl_miibus); 1541 bus_generic_detach(dev); 1542 1543 /* 1544 * The rest is resource deallocation, so we should already be 1545 * stopped here. 1546 */ 1547 1548 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1549 if (sc->rl_intrhand[i] != NULL) { 1550 bus_teardown_intr(dev, sc->rl_irq[i], 1551 sc->rl_intrhand[i]); 1552 sc->rl_intrhand[i] = NULL; 1553 } 1554 } 1555 if (ifp != NULL) 1556 if_free(ifp); 1557 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1558 if (sc->rl_irq[0] != NULL) { 1559 bus_release_resource(dev, SYS_RES_IRQ, 0, 1560 sc->rl_irq[0]); 1561 sc->rl_irq[0] = NULL; 1562 } 1563 } else { 1564 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1565 if (sc->rl_irq[i] != NULL) { 1566 bus_release_resource(dev, SYS_RES_IRQ, rid, 1567 sc->rl_irq[i]); 1568 sc->rl_irq[i] = NULL; 1569 } 1570 } 1571 pci_release_msi(dev); 1572 } 1573 if (sc->rl_res) 1574 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1575 sc->rl_res); 1576 1577 /* Unload and free the RX DMA ring memory and map */ 1578 1579 if (sc->rl_ldata.rl_rx_list_tag) { 1580 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1581 sc->rl_ldata.rl_rx_list_map); 1582 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1583 sc->rl_ldata.rl_rx_list, 1584 sc->rl_ldata.rl_rx_list_map); 1585 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1586 } 1587 1588 /* Unload and free the TX DMA ring memory and map */ 1589 1590 if (sc->rl_ldata.rl_tx_list_tag) { 1591 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1592 sc->rl_ldata.rl_tx_list_map); 1593 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1594 sc->rl_ldata.rl_tx_list, 1595 sc->rl_ldata.rl_tx_list_map); 1596 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1597 } 1598 1599 /* Destroy all the RX and TX buffer maps */ 1600 1601 if (sc->rl_ldata.rl_tx_mtag) { 1602 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1603 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1604 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1605 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1606 } 1607 if (sc->rl_ldata.rl_rx_mtag) { 1608 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1609 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1610 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1611 if (sc->rl_ldata.rl_rx_sparemap) 1612 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1613 sc->rl_ldata.rl_rx_sparemap); 1614 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1615 } 1616 1617 /* Unload and free the stats buffer and map */ 1618 1619 if (sc->rl_ldata.rl_stag) { 1620 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1621 sc->rl_ldata.rl_rx_list_map); 1622 bus_dmamem_free(sc->rl_ldata.rl_stag, 1623 sc->rl_ldata.rl_stats, 1624 sc->rl_ldata.rl_smap); 1625 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1626 } 1627 1628 if (sc->rl_parent_tag) 1629 bus_dma_tag_destroy(sc->rl_parent_tag); 1630 1631 mtx_destroy(&sc->rl_mtx); 1632 1633 return (0); 1634} 1635 1636static __inline void 1637re_discard_rxbuf(struct rl_softc *sc, int idx) 1638{ 1639 struct rl_desc *desc; 1640 struct rl_rxdesc *rxd; 1641 uint32_t cmdstat; 1642 1643 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1644 desc = &sc->rl_ldata.rl_rx_list[idx]; 1645 desc->rl_vlanctl = 0; 1646 cmdstat = rxd->rx_size; 1647 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1648 cmdstat |= RL_RDESC_CMD_EOR; 1649 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1650} 1651 1652static int 1653re_newbuf(struct rl_softc *sc, int idx) 1654{ 1655 struct mbuf *m; 1656 struct rl_rxdesc *rxd; 1657 bus_dma_segment_t segs[1]; 1658 bus_dmamap_t map; 1659 struct rl_desc *desc; 1660 uint32_t cmdstat; 1661 int error, nsegs; 1662 1663 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1664 if (m == NULL) 1665 return (ENOBUFS); 1666 1667 m->m_len = m->m_pkthdr.len = MCLBYTES; 1668#ifdef RE_FIXUP_RX 1669 /* 1670 * This is part of an evil trick to deal with non-x86 platforms. 1671 * The RealTek chip requires RX buffers to be aligned on 64-bit 1672 * boundaries, but that will hose non-x86 machines. To get around 1673 * this, we leave some empty space at the start of each buffer 1674 * and for non-x86 hosts, we copy the buffer back six bytes 1675 * to achieve word alignment. This is slightly more efficient 1676 * than allocating a new buffer, copying the contents, and 1677 * discarding the old buffer. 1678 */ 1679 m_adj(m, RE_ETHER_ALIGN); 1680#endif 1681 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1682 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1683 if (error != 0) { 1684 m_freem(m); 1685 return (ENOBUFS); 1686 } 1687 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1688 1689 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1690 if (rxd->rx_m != NULL) { 1691 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1692 BUS_DMASYNC_POSTREAD); 1693 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1694 } 1695 1696 rxd->rx_m = m; 1697 map = rxd->rx_dmamap; 1698 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1699 rxd->rx_size = segs[0].ds_len; 1700 sc->rl_ldata.rl_rx_sparemap = map; 1701 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1702 BUS_DMASYNC_PREREAD); 1703 1704 desc = &sc->rl_ldata.rl_rx_list[idx]; 1705 desc->rl_vlanctl = 0; 1706 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1707 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1708 cmdstat = segs[0].ds_len; 1709 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1710 cmdstat |= RL_RDESC_CMD_EOR; 1711 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1712 1713 return (0); 1714} 1715 1716#ifdef RE_FIXUP_RX 1717static __inline void 1718re_fixup_rx(struct mbuf *m) 1719{ 1720 int i; 1721 uint16_t *src, *dst; 1722 1723 src = mtod(m, uint16_t *); 1724 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1725 1726 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1727 *dst++ = *src++; 1728 1729 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1730} 1731#endif 1732 1733static int 1734re_tx_list_init(struct rl_softc *sc) 1735{ 1736 struct rl_desc *desc; 1737 int i; 1738 1739 RL_LOCK_ASSERT(sc); 1740 1741 bzero(sc->rl_ldata.rl_tx_list, 1742 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1743 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1744 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1745 /* Set EOR. */ 1746 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1747 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1748 1749 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1750 sc->rl_ldata.rl_tx_list_map, 1751 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1752 1753 sc->rl_ldata.rl_tx_prodidx = 0; 1754 sc->rl_ldata.rl_tx_considx = 0; 1755 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1756 1757 return (0); 1758} 1759 1760static int 1761re_rx_list_init(struct rl_softc *sc) 1762{ 1763 int error, i; 1764 1765 bzero(sc->rl_ldata.rl_rx_list, 1766 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1767 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1768 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1769 if ((error = re_newbuf(sc, i)) != 0) 1770 return (error); 1771 } 1772 1773 /* Flush the RX descriptors */ 1774 1775 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1776 sc->rl_ldata.rl_rx_list_map, 1777 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1778 1779 sc->rl_ldata.rl_rx_prodidx = 0; 1780 sc->rl_head = sc->rl_tail = NULL; 1781 1782 return (0); 1783} 1784 1785/* 1786 * RX handler for C+ and 8169. For the gigE chips, we support 1787 * the reception of jumbo frames that have been fragmented 1788 * across multiple 2K mbuf cluster buffers. 1789 */ 1790static int 1791re_rxeof(struct rl_softc *sc) 1792{ 1793 struct mbuf *m; 1794 struct ifnet *ifp; 1795 int i, total_len; 1796 struct rl_desc *cur_rx; 1797 u_int32_t rxstat, rxvlan; 1798 int maxpkt = 16; 1799 1800 RL_LOCK_ASSERT(sc); 1801 1802 ifp = sc->rl_ifp; 1803 1804 /* Invalidate the descriptor memory */ 1805 1806 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1807 sc->rl_ldata.rl_rx_list_map, 1808 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1809 1810 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1811 i = RL_RX_DESC_NXT(sc, i)) { 1812 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1813 rxstat = le32toh(cur_rx->rl_cmdstat); 1814 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1815 break; 1816 total_len = rxstat & sc->rl_rxlenmask; 1817 rxvlan = le32toh(cur_rx->rl_vlanctl); 1818 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1819 1820 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1821 if (re_newbuf(sc, i) != 0) { 1822 /* 1823 * If this is part of a multi-fragment packet, 1824 * discard all the pieces. 1825 */ 1826 if (sc->rl_head != NULL) { 1827 m_freem(sc->rl_head); 1828 sc->rl_head = sc->rl_tail = NULL; 1829 } 1830 re_discard_rxbuf(sc, i); 1831 continue; 1832 } 1833 m->m_len = RE_RX_DESC_BUFLEN; 1834 if (sc->rl_head == NULL) 1835 sc->rl_head = sc->rl_tail = m; 1836 else { 1837 m->m_flags &= ~M_PKTHDR; 1838 sc->rl_tail->m_next = m; 1839 sc->rl_tail = m; 1840 } 1841 continue; 1842 } 1843 1844 /* 1845 * NOTE: for the 8139C+, the frame length field 1846 * is always 12 bits in size, but for the gigE chips, 1847 * it is 13 bits (since the max RX frame length is 16K). 1848 * Unfortunately, all 32 bits in the status word 1849 * were already used, so to make room for the extra 1850 * length bit, RealTek took out the 'frame alignment 1851 * error' bit and shifted the other status bits 1852 * over one slot. The OWN, EOR, FS and LS bits are 1853 * still in the same places. We have already extracted 1854 * the frame length and checked the OWN bit, so rather 1855 * than using an alternate bit mapping, we shift the 1856 * status bits one space to the right so we can evaluate 1857 * them using the 8169 status as though it was in the 1858 * same format as that of the 8139C+. 1859 */ 1860 if (sc->rl_type == RL_8169) 1861 rxstat >>= 1; 1862 1863 /* 1864 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1865 * set, but if CRC is clear, it will still be a valid frame. 1866 */ 1867 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1868 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1869 ifp->if_ierrors++; 1870 /* 1871 * If this is part of a multi-fragment packet, 1872 * discard all the pieces. 1873 */ 1874 if (sc->rl_head != NULL) { 1875 m_freem(sc->rl_head); 1876 sc->rl_head = sc->rl_tail = NULL; 1877 } 1878 re_discard_rxbuf(sc, i); 1879 continue; 1880 } 1881 1882 /* 1883 * If allocating a replacement mbuf fails, 1884 * reload the current one. 1885 */ 1886 1887 if (re_newbuf(sc, i) != 0) { 1888 ifp->if_iqdrops++; 1889 if (sc->rl_head != NULL) { 1890 m_freem(sc->rl_head); 1891 sc->rl_head = sc->rl_tail = NULL; 1892 } 1893 re_discard_rxbuf(sc, i); 1894 continue; 1895 } 1896 1897 if (sc->rl_head != NULL) { 1898 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1899 if (m->m_len == 0) 1900 m->m_len = RE_RX_DESC_BUFLEN; 1901 /* 1902 * Special case: if there's 4 bytes or less 1903 * in this buffer, the mbuf can be discarded: 1904 * the last 4 bytes is the CRC, which we don't 1905 * care about anyway. 1906 */ 1907 if (m->m_len <= ETHER_CRC_LEN) { 1908 sc->rl_tail->m_len -= 1909 (ETHER_CRC_LEN - m->m_len); 1910 m_freem(m); 1911 } else { 1912 m->m_len -= ETHER_CRC_LEN; 1913 m->m_flags &= ~M_PKTHDR; 1914 sc->rl_tail->m_next = m; 1915 } 1916 m = sc->rl_head; 1917 sc->rl_head = sc->rl_tail = NULL; 1918 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1919 } else 1920 m->m_pkthdr.len = m->m_len = 1921 (total_len - ETHER_CRC_LEN); 1922 1923#ifdef RE_FIXUP_RX 1924 re_fixup_rx(m); 1925#endif 1926 ifp->if_ipackets++; 1927 m->m_pkthdr.rcvif = ifp; 1928 1929 /* Do RX checksumming if enabled */ 1930 1931 if (ifp->if_capenable & IFCAP_RXCSUM) { 1932 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1933 /* Check IP header checksum */ 1934 if (rxstat & RL_RDESC_STAT_PROTOID) 1935 m->m_pkthdr.csum_flags |= 1936 CSUM_IP_CHECKED; 1937 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1938 m->m_pkthdr.csum_flags |= 1939 CSUM_IP_VALID; 1940 1941 /* Check TCP/UDP checksum */ 1942 if ((RL_TCPPKT(rxstat) && 1943 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1944 (RL_UDPPKT(rxstat) && 1945 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1946 m->m_pkthdr.csum_flags |= 1947 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1948 m->m_pkthdr.csum_data = 0xffff; 1949 } 1950 } else { 1951 /* 1952 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1953 */ 1954 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1955 (rxvlan & RL_RDESC_IPV4)) 1956 m->m_pkthdr.csum_flags |= 1957 CSUM_IP_CHECKED; 1958 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1959 (rxvlan & RL_RDESC_IPV4)) 1960 m->m_pkthdr.csum_flags |= 1961 CSUM_IP_VALID; 1962 if (((rxstat & RL_RDESC_STAT_TCP) && 1963 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1964 ((rxstat & RL_RDESC_STAT_UDP) && 1965 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1966 m->m_pkthdr.csum_flags |= 1967 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1968 m->m_pkthdr.csum_data = 0xffff; 1969 } 1970 } 1971 } 1972 maxpkt--; 1973 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1974 m->m_pkthdr.ether_vtag = 1975 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 1976 m->m_flags |= M_VLANTAG; 1977 } 1978 RL_UNLOCK(sc); 1979 (*ifp->if_input)(ifp, m); 1980 RL_LOCK(sc); 1981 } 1982 1983 /* Flush the RX DMA ring */ 1984 1985 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1986 sc->rl_ldata.rl_rx_list_map, 1987 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1988 1989 sc->rl_ldata.rl_rx_prodidx = i; 1990 1991 if (maxpkt) 1992 return(EAGAIN); 1993 1994 return(0); 1995} 1996 1997static void 1998re_txeof(struct rl_softc *sc) 1999{ 2000 struct ifnet *ifp; 2001 struct rl_txdesc *txd; 2002 u_int32_t txstat; 2003 int cons; 2004 2005 cons = sc->rl_ldata.rl_tx_considx; 2006 if (cons == sc->rl_ldata.rl_tx_prodidx) 2007 return; 2008 2009 ifp = sc->rl_ifp; 2010 /* Invalidate the TX descriptor list */ 2011 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2012 sc->rl_ldata.rl_tx_list_map, 2013 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2014 2015 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2016 cons = RL_TX_DESC_NXT(sc, cons)) { 2017 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2018 if (txstat & RL_TDESC_STAT_OWN) 2019 break; 2020 /* 2021 * We only stash mbufs in the last descriptor 2022 * in a fragment chain, which also happens to 2023 * be the only place where the TX status bits 2024 * are valid. 2025 */ 2026 if (txstat & RL_TDESC_CMD_EOF) { 2027 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2028 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2029 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2030 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2031 txd->tx_dmamap); 2032 KASSERT(txd->tx_m != NULL, 2033 ("%s: freeing NULL mbufs!", __func__)); 2034 m_freem(txd->tx_m); 2035 txd->tx_m = NULL; 2036 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2037 RL_TDESC_STAT_COLCNT)) 2038 ifp->if_collisions++; 2039 if (txstat & RL_TDESC_STAT_TXERRSUM) 2040 ifp->if_oerrors++; 2041 else 2042 ifp->if_opackets++; 2043 } 2044 sc->rl_ldata.rl_tx_free++; 2045 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2046 } 2047 sc->rl_ldata.rl_tx_considx = cons; 2048 2049 /* No changes made to the TX ring, so no flush needed */ 2050 2051 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2052#ifdef RE_TX_MODERATION 2053 /* 2054 * If not all descriptors have been reaped yet, reload 2055 * the timer so that we will eventually get another 2056 * interrupt that will cause us to re-enter this routine. 2057 * This is done in case the transmitter has gone idle. 2058 */ 2059 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2060#endif 2061 } else 2062 sc->rl_watchdog_timer = 0; 2063} 2064 2065static void 2066re_tick(void *xsc) 2067{ 2068 struct rl_softc *sc; 2069 struct mii_data *mii; 2070 2071 sc = xsc; 2072 2073 RL_LOCK_ASSERT(sc); 2074 2075 mii = device_get_softc(sc->rl_miibus); 2076 mii_tick(mii); 2077 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2078 re_miibus_statchg(sc->rl_dev); 2079 /* 2080 * Reclaim transmitted frames here. Technically it is not 2081 * necessary to do here but it ensures periodic reclamation 2082 * regardless of Tx completion interrupt which seems to be 2083 * lost on PCIe based controllers under certain situations. 2084 */ 2085 re_txeof(sc); 2086 re_watchdog(sc); 2087 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2088} 2089 2090#ifdef DEVICE_POLLING 2091static void 2092re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2093{ 2094 struct rl_softc *sc = ifp->if_softc; 2095 2096 RL_LOCK(sc); 2097 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2098 re_poll_locked(ifp, cmd, count); 2099 RL_UNLOCK(sc); 2100} 2101 2102static void 2103re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2104{ 2105 struct rl_softc *sc = ifp->if_softc; 2106 2107 RL_LOCK_ASSERT(sc); 2108 2109 sc->rxcycles = count; 2110 re_rxeof(sc); 2111 re_txeof(sc); 2112 2113 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2114 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2115 2116 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2117 u_int16_t status; 2118 2119 status = CSR_READ_2(sc, RL_ISR); 2120 if (status == 0xffff) 2121 return; 2122 if (status) 2123 CSR_WRITE_2(sc, RL_ISR, status); 2124 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2125 (sc->rl_flags & RL_FLAG_PCIE)) 2126 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2127 2128 /* 2129 * XXX check behaviour on receiver stalls. 2130 */ 2131 2132 if (status & RL_ISR_SYSTEM_ERR) 2133 re_init_locked(sc); 2134 } 2135} 2136#endif /* DEVICE_POLLING */ 2137 2138static int 2139re_intr(void *arg) 2140{ 2141 struct rl_softc *sc; 2142 uint16_t status; 2143 2144 sc = arg; 2145 2146 status = CSR_READ_2(sc, RL_ISR); 2147 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2148 return (FILTER_STRAY); 2149 CSR_WRITE_2(sc, RL_IMR, 0); 2150 2151 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2152 2153 return (FILTER_HANDLED); 2154} 2155 2156static void 2157re_int_task(void *arg, int npending) 2158{ 2159 struct rl_softc *sc; 2160 struct ifnet *ifp; 2161 u_int16_t status; 2162 int rval = 0; 2163 2164 sc = arg; 2165 ifp = sc->rl_ifp; 2166 2167 RL_LOCK(sc); 2168 2169 status = CSR_READ_2(sc, RL_ISR); 2170 CSR_WRITE_2(sc, RL_ISR, status); 2171 2172 if (sc->suspended || 2173 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2174 RL_UNLOCK(sc); 2175 return; 2176 } 2177 2178#ifdef DEVICE_POLLING 2179 if (ifp->if_capenable & IFCAP_POLLING) { 2180 RL_UNLOCK(sc); 2181 return; 2182 } 2183#endif 2184 2185 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2186 rval = re_rxeof(sc); 2187 2188 /* 2189 * Some chips will ignore a second TX request issued 2190 * while an existing transmission is in progress. If 2191 * the transmitter goes idle but there are still 2192 * packets waiting to be sent, we need to restart the 2193 * channel here to flush them out. This only seems to 2194 * be required with the PCIe devices. 2195 */ 2196 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2197 (sc->rl_flags & RL_FLAG_PCIE)) 2198 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2199 if (status & ( 2200#ifdef RE_TX_MODERATION 2201 RL_ISR_TIMEOUT_EXPIRED| 2202#else 2203 RL_ISR_TX_OK| 2204#endif 2205 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2206 re_txeof(sc); 2207 2208 if (status & RL_ISR_SYSTEM_ERR) 2209 re_init_locked(sc); 2210 2211 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2212 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2213 2214 RL_UNLOCK(sc); 2215 2216 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2217 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2218 return; 2219 } 2220 2221 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2222} 2223 2224static int 2225re_encap(struct rl_softc *sc, struct mbuf **m_head) 2226{ 2227 struct rl_txdesc *txd, *txd_last; 2228 bus_dma_segment_t segs[RL_NTXSEGS]; 2229 bus_dmamap_t map; 2230 struct mbuf *m_new; 2231 struct rl_desc *desc; 2232 int nsegs, prod; 2233 int i, error, ei, si; 2234 int padlen; 2235 uint32_t cmdstat, csum_flags, vlanctl; 2236 2237 RL_LOCK_ASSERT(sc); 2238 M_ASSERTPKTHDR((*m_head)); 2239 2240 /* 2241 * With some of the RealTek chips, using the checksum offload 2242 * support in conjunction with the autopadding feature results 2243 * in the transmission of corrupt frames. For example, if we 2244 * need to send a really small IP fragment that's less than 60 2245 * bytes in size, and IP header checksumming is enabled, the 2246 * resulting ethernet frame that appears on the wire will 2247 * have garbled payload. To work around this, if TX IP checksum 2248 * offload is enabled, we always manually pad short frames out 2249 * to the minimum ethernet frame size. 2250 */ 2251 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2252 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2253 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2254 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2255 if (M_WRITABLE(*m_head) == 0) { 2256 /* Get a writable copy. */ 2257 m_new = m_dup(*m_head, M_DONTWAIT); 2258 m_freem(*m_head); 2259 if (m_new == NULL) { 2260 *m_head = NULL; 2261 return (ENOBUFS); 2262 } 2263 *m_head = m_new; 2264 } 2265 if ((*m_head)->m_next != NULL || 2266 M_TRAILINGSPACE(*m_head) < padlen) { 2267 m_new = m_defrag(*m_head, M_DONTWAIT); 2268 if (m_new == NULL) { 2269 m_freem(*m_head); 2270 *m_head = NULL; 2271 return (ENOBUFS); 2272 } 2273 } else 2274 m_new = *m_head; 2275 2276 /* 2277 * Manually pad short frames, and zero the pad space 2278 * to avoid leaking data. 2279 */ 2280 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2281 m_new->m_pkthdr.len += padlen; 2282 m_new->m_len = m_new->m_pkthdr.len; 2283 *m_head = m_new; 2284 } 2285 2286 prod = sc->rl_ldata.rl_tx_prodidx; 2287 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2288 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2289 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2290 if (error == EFBIG) { 2291 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2292 if (m_new == NULL) { 2293 m_freem(*m_head); 2294 *m_head = NULL; 2295 return (ENOBUFS); 2296 } 2297 *m_head = m_new; 2298 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2299 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2300 if (error != 0) { 2301 m_freem(*m_head); 2302 *m_head = NULL; 2303 return (error); 2304 } 2305 } else if (error != 0) 2306 return (error); 2307 if (nsegs == 0) { 2308 m_freem(*m_head); 2309 *m_head = NULL; 2310 return (EIO); 2311 } 2312 2313 /* Check for number of available descriptors. */ 2314 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2315 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2316 return (ENOBUFS); 2317 } 2318 2319 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2320 BUS_DMASYNC_PREWRITE); 2321 2322 /* 2323 * Set up checksum offload. Note: checksum offload bits must 2324 * appear in all descriptors of a multi-descriptor transmit 2325 * attempt. This is according to testing done with an 8169 2326 * chip. This is a requirement. 2327 */ 2328 vlanctl = 0; 2329 csum_flags = 0; 2330 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2331 csum_flags = RL_TDESC_CMD_LGSEND | 2332 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2333 RL_TDESC_CMD_MSSVAL_SHIFT); 2334 else { 2335 /* 2336 * Unconditionally enable IP checksum if TCP or UDP 2337 * checksum is required. Otherwise, TCP/UDP checksum 2338 * does't make effects. 2339 */ 2340 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2341 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2342 csum_flags |= RL_TDESC_CMD_IPCSUM; 2343 if (((*m_head)->m_pkthdr.csum_flags & 2344 CSUM_TCP) != 0) 2345 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2346 if (((*m_head)->m_pkthdr.csum_flags & 2347 CSUM_UDP) != 0) 2348 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2349 } else { 2350 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2351 if (((*m_head)->m_pkthdr.csum_flags & 2352 CSUM_TCP) != 0) 2353 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2354 if (((*m_head)->m_pkthdr.csum_flags & 2355 CSUM_UDP) != 0) 2356 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2357 } 2358 } 2359 } 2360 2361 /* 2362 * Set up hardware VLAN tagging. Note: vlan tag info must 2363 * appear in all descriptors of a multi-descriptor 2364 * transmission attempt. 2365 */ 2366 if ((*m_head)->m_flags & M_VLANTAG) 2367 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2368 RL_TDESC_VLANCTL_TAG; 2369 2370 si = prod; 2371 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2372 desc = &sc->rl_ldata.rl_tx_list[prod]; 2373 desc->rl_vlanctl = htole32(vlanctl); 2374 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2375 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2376 cmdstat = segs[i].ds_len; 2377 if (i != 0) 2378 cmdstat |= RL_TDESC_CMD_OWN; 2379 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2380 cmdstat |= RL_TDESC_CMD_EOR; 2381 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2382 sc->rl_ldata.rl_tx_free--; 2383 } 2384 /* Update producer index. */ 2385 sc->rl_ldata.rl_tx_prodidx = prod; 2386 2387 /* Set EOF on the last descriptor. */ 2388 ei = RL_TX_DESC_PRV(sc, prod); 2389 desc = &sc->rl_ldata.rl_tx_list[ei]; 2390 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2391 2392 desc = &sc->rl_ldata.rl_tx_list[si]; 2393 /* Set SOF and transfer ownership of packet to the chip. */ 2394 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2395 2396 /* 2397 * Insure that the map for this transmission 2398 * is placed at the array index of the last descriptor 2399 * in this chain. (Swap last and first dmamaps.) 2400 */ 2401 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2402 map = txd->tx_dmamap; 2403 txd->tx_dmamap = txd_last->tx_dmamap; 2404 txd_last->tx_dmamap = map; 2405 txd_last->tx_m = *m_head; 2406 2407 return (0); 2408} 2409 2410static void 2411re_tx_task(void *arg, int npending) 2412{ 2413 struct ifnet *ifp; 2414 2415 ifp = arg; 2416 re_start(ifp); 2417} 2418 2419/* 2420 * Main transmit routine for C+ and gigE NICs. 2421 */ 2422static void 2423re_start(struct ifnet *ifp) 2424{ 2425 struct rl_softc *sc; 2426 struct mbuf *m_head; 2427 int queued; 2428 2429 sc = ifp->if_softc; 2430 2431 RL_LOCK(sc); 2432 2433 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2434 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2435 RL_UNLOCK(sc); 2436 return; 2437 } 2438 2439 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2440 sc->rl_ldata.rl_tx_free > 1;) { 2441 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2442 if (m_head == NULL) 2443 break; 2444 2445 if (re_encap(sc, &m_head) != 0) { 2446 if (m_head == NULL) 2447 break; 2448 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2449 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2450 break; 2451 } 2452 2453 /* 2454 * If there's a BPF listener, bounce a copy of this frame 2455 * to him. 2456 */ 2457 ETHER_BPF_MTAP(ifp, m_head); 2458 2459 queued++; 2460 } 2461 2462 if (queued == 0) { 2463#ifdef RE_TX_MODERATION 2464 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2465 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2466#endif 2467 RL_UNLOCK(sc); 2468 return; 2469 } 2470 2471 /* Flush the TX descriptors */ 2472 2473 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2474 sc->rl_ldata.rl_tx_list_map, 2475 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2476 2477 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2478 2479#ifdef RE_TX_MODERATION 2480 /* 2481 * Use the countdown timer for interrupt moderation. 2482 * 'TX done' interrupts are disabled. Instead, we reset the 2483 * countdown timer, which will begin counting until it hits 2484 * the value in the TIMERINT register, and then trigger an 2485 * interrupt. Each time we write to the TIMERCNT register, 2486 * the timer count is reset to 0. 2487 */ 2488 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2489#endif 2490 2491 /* 2492 * Set a timeout in case the chip goes out to lunch. 2493 */ 2494 sc->rl_watchdog_timer = 5; 2495 2496 RL_UNLOCK(sc); 2497} 2498 2499static void 2500re_init(void *xsc) 2501{ 2502 struct rl_softc *sc = xsc; 2503 2504 RL_LOCK(sc); 2505 re_init_locked(sc); 2506 RL_UNLOCK(sc); 2507} 2508 2509static void 2510re_init_locked(struct rl_softc *sc) 2511{ 2512 struct ifnet *ifp = sc->rl_ifp; 2513 struct mii_data *mii; 2514 uint32_t reg; 2515 uint16_t cfg; 2516 union { 2517 uint32_t align_dummy; 2518 u_char eaddr[ETHER_ADDR_LEN]; 2519 } eaddr; 2520 2521 RL_LOCK_ASSERT(sc); 2522 2523 mii = device_get_softc(sc->rl_miibus); 2524 2525 /* 2526 * Cancel pending I/O and free all RX/TX buffers. 2527 */ 2528 re_stop(sc); 2529 2530 /* Put controller into known state. */ 2531 re_reset(sc); 2532 2533 /* 2534 * Enable C+ RX and TX mode, as well as VLAN stripping and 2535 * RX checksum offload. We must configure the C+ register 2536 * before all others. 2537 */ 2538 cfg = RL_CPLUSCMD_PCI_MRW; 2539 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2540 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2541 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2542 cfg |= RL_CPLUSCMD_VLANSTRIP; 2543 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2544 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2545 /* XXX magic. */ 2546 cfg |= 0x0001; 2547 } else 2548 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2549 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2550 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2551 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2552 reg = 0x000fff00; 2553 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2554 reg |= 0x000000ff; 2555 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2556 reg |= 0x00f00000; 2557 CSR_WRITE_4(sc, 0x7c, reg); 2558 /* Disable interrupt mitigation. */ 2559 CSR_WRITE_2(sc, 0xe2, 0); 2560 } 2561 /* 2562 * Disable TSO if interface MTU size is greater than MSS 2563 * allowed in controller. 2564 */ 2565 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2566 ifp->if_capenable &= ~IFCAP_TSO4; 2567 ifp->if_hwassist &= ~CSUM_TSO; 2568 } 2569 2570 /* 2571 * Init our MAC address. Even though the chipset 2572 * documentation doesn't mention it, we need to enter "Config 2573 * register write enable" mode to modify the ID registers. 2574 */ 2575 /* Copy MAC address on stack to align. */ 2576 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2577 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2578 CSR_WRITE_4(sc, RL_IDR0, 2579 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2580 CSR_WRITE_4(sc, RL_IDR4, 2581 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2582 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2583 2584 /* 2585 * For C+ mode, initialize the RX descriptors and mbufs. 2586 */ 2587 re_rx_list_init(sc); 2588 re_tx_list_init(sc); 2589 2590 /* 2591 * Load the addresses of the RX and TX lists into the chip. 2592 */ 2593 2594 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2595 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2596 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2597 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2598 2599 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2600 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2601 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2602 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2603 2604 /* 2605 * Enable transmit and receive. 2606 */ 2607 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2608 2609 /* 2610 * Set the initial TX configuration. 2611 */ 2612 if (sc->rl_testmode) { 2613 if (sc->rl_type == RL_8169) 2614 CSR_WRITE_4(sc, RL_TXCFG, 2615 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2616 else 2617 CSR_WRITE_4(sc, RL_TXCFG, 2618 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2619 } else 2620 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2621 2622 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2623 2624 /* 2625 * Set the initial RX configuration. 2626 */ 2627 re_set_rxmode(sc); 2628 2629#ifdef DEVICE_POLLING 2630 /* 2631 * Disable interrupts if we are polling. 2632 */ 2633 if (ifp->if_capenable & IFCAP_POLLING) 2634 CSR_WRITE_2(sc, RL_IMR, 0); 2635 else /* otherwise ... */ 2636#endif 2637 2638 /* 2639 * Enable interrupts. 2640 */ 2641 if (sc->rl_testmode) 2642 CSR_WRITE_2(sc, RL_IMR, 0); 2643 else 2644 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2645 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2646 2647 /* Set initial TX threshold */ 2648 sc->rl_txthresh = RL_TX_THRESH_INIT; 2649 2650 /* Start RX/TX process. */ 2651 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2652#ifdef notdef 2653 /* Enable receiver and transmitter. */ 2654 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2655#endif 2656 2657#ifdef RE_TX_MODERATION 2658 /* 2659 * Initialize the timer interrupt register so that 2660 * a timer interrupt will be generated once the timer 2661 * reaches a certain number of ticks. The timer is 2662 * reloaded on each transmit. This gives us TX interrupt 2663 * moderation, which dramatically improves TX frame rate. 2664 */ 2665 if (sc->rl_type == RL_8169) 2666 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2667 else 2668 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2669#endif 2670 2671 /* 2672 * For 8169 gigE NICs, set the max allowed RX packet 2673 * size so we can receive jumbo frames. 2674 */ 2675 if (sc->rl_type == RL_8169) 2676 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2677 2678 if (sc->rl_testmode) 2679 return; 2680 2681 mii_mediachg(mii); 2682 2683 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2684 2685 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2686 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2687 2688 sc->rl_flags &= ~RL_FLAG_LINK; 2689 sc->rl_watchdog_timer = 0; 2690 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2691} 2692 2693/* 2694 * Set media options. 2695 */ 2696static int 2697re_ifmedia_upd(struct ifnet *ifp) 2698{ 2699 struct rl_softc *sc; 2700 struct mii_data *mii; 2701 int error; 2702 2703 sc = ifp->if_softc; 2704 mii = device_get_softc(sc->rl_miibus); 2705 RL_LOCK(sc); 2706 error = mii_mediachg(mii); 2707 RL_UNLOCK(sc); 2708 2709 return (error); 2710} 2711 2712/* 2713 * Report current media status. 2714 */ 2715static void 2716re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2717{ 2718 struct rl_softc *sc; 2719 struct mii_data *mii; 2720 2721 sc = ifp->if_softc; 2722 mii = device_get_softc(sc->rl_miibus); 2723 2724 RL_LOCK(sc); 2725 mii_pollstat(mii); 2726 RL_UNLOCK(sc); 2727 ifmr->ifm_active = mii->mii_media_active; 2728 ifmr->ifm_status = mii->mii_media_status; 2729} 2730 2731static int 2732re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2733{ 2734 struct rl_softc *sc = ifp->if_softc; 2735 struct ifreq *ifr = (struct ifreq *) data; 2736 struct mii_data *mii; 2737 int error = 0; 2738 2739 switch (command) { 2740 case SIOCSIFMTU: 2741 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2742 error = EINVAL; 2743 break; 2744 } 2745 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2746 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2747 error = EINVAL; 2748 break; 2749 } 2750 RL_LOCK(sc); 2751 if (ifp->if_mtu != ifr->ifr_mtu) 2752 ifp->if_mtu = ifr->ifr_mtu; 2753 if (ifp->if_mtu > RL_TSO_MTU && 2754 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2755 ifp->if_capenable &= ~IFCAP_TSO4; 2756 ifp->if_hwassist &= ~CSUM_TSO; 2757 } 2758 RL_UNLOCK(sc); 2759 break; 2760 case SIOCSIFFLAGS: 2761 RL_LOCK(sc); 2762 if ((ifp->if_flags & IFF_UP) != 0) { 2763 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2764 if (((ifp->if_flags ^ sc->rl_if_flags) 2765 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2766 re_set_rxmode(sc); 2767 } else 2768 re_init_locked(sc); 2769 } else { 2770 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2771 re_stop(sc); 2772 } 2773 sc->rl_if_flags = ifp->if_flags; 2774 RL_UNLOCK(sc); 2775 break; 2776 case SIOCADDMULTI: 2777 case SIOCDELMULTI: 2778 RL_LOCK(sc); 2779 re_set_rxmode(sc); 2780 RL_UNLOCK(sc); 2781 break; 2782 case SIOCGIFMEDIA: 2783 case SIOCSIFMEDIA: 2784 mii = device_get_softc(sc->rl_miibus); 2785 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2786 break; 2787 case SIOCSIFCAP: 2788 { 2789 int mask, reinit; 2790 2791 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2792 reinit = 0; 2793#ifdef DEVICE_POLLING 2794 if (mask & IFCAP_POLLING) { 2795 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2796 error = ether_poll_register(re_poll, ifp); 2797 if (error) 2798 return(error); 2799 RL_LOCK(sc); 2800 /* Disable interrupts */ 2801 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2802 ifp->if_capenable |= IFCAP_POLLING; 2803 RL_UNLOCK(sc); 2804 } else { 2805 error = ether_poll_deregister(ifp); 2806 /* Enable interrupts. */ 2807 RL_LOCK(sc); 2808 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2809 ifp->if_capenable &= ~IFCAP_POLLING; 2810 RL_UNLOCK(sc); 2811 } 2812 } 2813#endif /* DEVICE_POLLING */ 2814 if (mask & IFCAP_HWCSUM) { 2815 ifp->if_capenable ^= IFCAP_HWCSUM; 2816 if (ifp->if_capenable & IFCAP_TXCSUM) 2817 ifp->if_hwassist |= RE_CSUM_FEATURES; 2818 else 2819 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2820 reinit = 1; 2821 } 2822 if (mask & IFCAP_VLAN_HWTAGGING) { 2823 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2824 reinit = 1; 2825 } 2826 if (mask & IFCAP_TSO4) { 2827 ifp->if_capenable ^= IFCAP_TSO4; 2828 if ((IFCAP_TSO4 & ifp->if_capenable) && 2829 (IFCAP_TSO4 & ifp->if_capabilities)) 2830 ifp->if_hwassist |= CSUM_TSO; 2831 else 2832 ifp->if_hwassist &= ~CSUM_TSO; 2833 if (ifp->if_mtu > RL_TSO_MTU && 2834 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2835 ifp->if_capenable &= ~IFCAP_TSO4; 2836 ifp->if_hwassist &= ~CSUM_TSO; 2837 } 2838 } 2839 if ((mask & IFCAP_WOL) != 0 && 2840 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2841 if ((mask & IFCAP_WOL_UCAST) != 0) 2842 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2843 if ((mask & IFCAP_WOL_MCAST) != 0) 2844 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2845 if ((mask & IFCAP_WOL_MAGIC) != 0) 2846 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2847 } 2848 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2849 re_init(sc); 2850 VLAN_CAPABILITIES(ifp); 2851 } 2852 break; 2853 default: 2854 error = ether_ioctl(ifp, command, data); 2855 break; 2856 } 2857 2858 return (error); 2859} 2860 2861static void 2862re_watchdog(struct rl_softc *sc) 2863{ 2864 struct ifnet *ifp; 2865 2866 RL_LOCK_ASSERT(sc); 2867 2868 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2869 return; 2870 2871 ifp = sc->rl_ifp; 2872 re_txeof(sc); 2873 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2874 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2875 "-- recovering\n"); 2876 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2877 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2878 return; 2879 } 2880 2881 if_printf(ifp, "watchdog timeout\n"); 2882 ifp->if_oerrors++; 2883 2884 re_rxeof(sc); 2885 re_init_locked(sc); 2886 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2887 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2888} 2889 2890/* 2891 * Stop the adapter and free any mbufs allocated to the 2892 * RX and TX lists. 2893 */ 2894static void 2895re_stop(struct rl_softc *sc) 2896{ 2897 int i; 2898 struct ifnet *ifp; 2899 struct rl_txdesc *txd; 2900 struct rl_rxdesc *rxd; 2901 2902 RL_LOCK_ASSERT(sc); 2903 2904 ifp = sc->rl_ifp; 2905 2906 sc->rl_watchdog_timer = 0; 2907 callout_stop(&sc->rl_stat_callout); 2908 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2909 2910 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 2911 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 2912 RL_CMD_RX_ENB); 2913 else 2914 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2915 DELAY(1000); 2916 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2917 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2918 2919 if (sc->rl_head != NULL) { 2920 m_freem(sc->rl_head); 2921 sc->rl_head = sc->rl_tail = NULL; 2922 } 2923 2924 /* Free the TX list buffers. */ 2925 2926 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2927 txd = &sc->rl_ldata.rl_tx_desc[i]; 2928 if (txd->tx_m != NULL) { 2929 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2930 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2931 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2932 txd->tx_dmamap); 2933 m_freem(txd->tx_m); 2934 txd->tx_m = NULL; 2935 } 2936 } 2937 2938 /* Free the RX list buffers. */ 2939 2940 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2941 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2942 if (rxd->rx_m != NULL) { 2943 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2944 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2945 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2946 rxd->rx_dmamap); 2947 m_freem(rxd->rx_m); 2948 rxd->rx_m = NULL; 2949 } 2950 } 2951} 2952 2953/* 2954 * Device suspend routine. Stop the interface and save some PCI 2955 * settings in case the BIOS doesn't restore them properly on 2956 * resume. 2957 */ 2958static int 2959re_suspend(device_t dev) 2960{ 2961 struct rl_softc *sc; 2962 2963 sc = device_get_softc(dev); 2964 2965 RL_LOCK(sc); 2966 re_stop(sc); 2967 re_setwol(sc); 2968 sc->suspended = 1; 2969 RL_UNLOCK(sc); 2970 2971 return (0); 2972} 2973 2974/* 2975 * Device resume routine. Restore some PCI settings in case the BIOS 2976 * doesn't, re-enable busmastering, and restart the interface if 2977 * appropriate. 2978 */ 2979static int 2980re_resume(device_t dev) 2981{ 2982 struct rl_softc *sc; 2983 struct ifnet *ifp; 2984 2985 sc = device_get_softc(dev); 2986 2987 RL_LOCK(sc); 2988 2989 ifp = sc->rl_ifp; 2990 /* Take controller out of sleep mode. */ 2991 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 2992 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 2993 CSR_WRITE_1(sc, RL_GPIO, 2994 CSR_READ_1(sc, RL_GPIO) | 0x01); 2995 } 2996 2997 /* reinitialize interface if necessary */ 2998 if (ifp->if_flags & IFF_UP) 2999 re_init_locked(sc); 3000 3001 /* 3002 * Clear WOL matching such that normal Rx filtering 3003 * wouldn't interfere with WOL patterns. 3004 */ 3005 re_clrwol(sc); 3006 sc->suspended = 0; 3007 RL_UNLOCK(sc); 3008 3009 return (0); 3010} 3011 3012/* 3013 * Stop all chip I/O so that the kernel's probe routines don't 3014 * get confused by errant DMAs when rebooting. 3015 */ 3016static int 3017re_shutdown(device_t dev) 3018{ 3019 struct rl_softc *sc; 3020 3021 sc = device_get_softc(dev); 3022 3023 RL_LOCK(sc); 3024 re_stop(sc); 3025 /* 3026 * Mark interface as down since otherwise we will panic if 3027 * interrupt comes in later on, which can happen in some 3028 * cases. 3029 */ 3030 sc->rl_ifp->if_flags &= ~IFF_UP; 3031 re_setwol(sc); 3032 RL_UNLOCK(sc); 3033 3034 return (0); 3035} 3036 3037static void 3038re_setwol(struct rl_softc *sc) 3039{ 3040 struct ifnet *ifp; 3041 int pmc; 3042 uint16_t pmstat; 3043 uint8_t v; 3044 3045 RL_LOCK_ASSERT(sc); 3046 3047 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3048 return; 3049 3050 ifp = sc->rl_ifp; 3051 /* Put controller into sleep mode. */ 3052 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3053 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3054 CSR_WRITE_1(sc, RL_GPIO, 3055 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3056 } 3057 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3058 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3059 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3060 /* Enable config register write. */ 3061 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3062 3063 /* Enable PME. */ 3064 v = CSR_READ_1(sc, RL_CFG1); 3065 v &= ~RL_CFG1_PME; 3066 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3067 v |= RL_CFG1_PME; 3068 CSR_WRITE_1(sc, RL_CFG1, v); 3069 3070 v = CSR_READ_1(sc, RL_CFG3); 3071 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3072 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3073 v |= RL_CFG3_WOL_MAGIC; 3074 CSR_WRITE_1(sc, RL_CFG3, v); 3075 3076 /* Config register write done. */ 3077 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3078 3079 v = CSR_READ_1(sc, RL_CFG5); 3080 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3081 v &= ~RL_CFG5_WOL_LANWAKE; 3082 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3083 v |= RL_CFG5_WOL_UCAST; 3084 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3085 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3086 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3087 v |= RL_CFG5_WOL_LANWAKE; 3088 CSR_WRITE_1(sc, RL_CFG5, v); 3089 3090 /* 3091 * It seems that hardware resets its link speed to 100Mbps in 3092 * power down mode so switching to 100Mbps in driver is not 3093 * needed. 3094 */ 3095 3096 /* Request PME if WOL is requested. */ 3097 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3098 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3099 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3100 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3101 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3102} 3103 3104static void 3105re_clrwol(struct rl_softc *sc) 3106{ 3107 int pmc; 3108 uint8_t v; 3109 3110 RL_LOCK_ASSERT(sc); 3111 3112 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3113 return; 3114 3115 /* Enable config register write. */ 3116 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3117 3118 v = CSR_READ_1(sc, RL_CFG3); 3119 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3120 CSR_WRITE_1(sc, RL_CFG3, v); 3121 3122 /* Config register write done. */ 3123 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3124 3125 v = CSR_READ_1(sc, RL_CFG5); 3126 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3127 v &= ~RL_CFG5_WOL_LANWAKE; 3128 CSR_WRITE_1(sc, RL_CFG5, v); 3129} 3130