if_re.c revision 189555
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 189555 2009-03-09 06:02:55Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* Tunables. */ 159static int msi_disable = 0; 160TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161static int prefer_iomap = 0; 162TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 163 164#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 165 166/* 167 * Various supported device vendors/types and their names. 168 */ 169static struct rl_type re_devs[] = { 170 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 171 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 172 { RT_VENDORID, RT_DEVICEID_8139, 0, 173 "RealTek 8139C+ 10/100BaseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8101E, 0, 175 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 176 { RT_VENDORID, RT_DEVICEID_8168, 0, 177 "RealTek 8168/8168B/8168C/8168CP/8168D/8111B/8111C/8111CP PCIe " 178 "Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, 0, 180 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 184 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 185 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 186 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 187 { USR_VENDORID, USR_DEVICEID_997902, 0, 188 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 189}; 190 191static struct rl_hwrev re_hwrevs[] = { 192 { RL_HWREV_8139, RL_8139, "" }, 193 { RL_HWREV_8139A, RL_8139, "A" }, 194 { RL_HWREV_8139AG, RL_8139, "A-G" }, 195 { RL_HWREV_8139B, RL_8139, "B" }, 196 { RL_HWREV_8130, RL_8139, "8130" }, 197 { RL_HWREV_8139C, RL_8139, "C" }, 198 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 199 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 200 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 201 { RL_HWREV_8169, RL_8169, "8169"}, 202 { RL_HWREV_8169S, RL_8169, "8169S"}, 203 { RL_HWREV_8110S, RL_8169, "8110S"}, 204 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 205 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 206 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 207 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, 208 { RL_HWREV_8100, RL_8139, "8100"}, 209 { RL_HWREV_8101, RL_8139, "8101"}, 210 { RL_HWREV_8100E, RL_8169, "8100E"}, 211 { RL_HWREV_8101E, RL_8169, "8101E"}, 212 { RL_HWREV_8102E, RL_8169, "8102E"}, 213 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 214 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 215 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 216 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 217 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 218 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 219 { RL_HWREV_8168D, RL_8169, "8168D"}, 220 { 0, 0, NULL } 221}; 222 223static int re_probe (device_t); 224static int re_attach (device_t); 225static int re_detach (device_t); 226 227static int re_encap (struct rl_softc *, struct mbuf **); 228 229static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 230static int re_allocmem (device_t, struct rl_softc *); 231static __inline void re_discard_rxbuf 232 (struct rl_softc *, int); 233static int re_newbuf (struct rl_softc *, int); 234static int re_rx_list_init (struct rl_softc *); 235static int re_tx_list_init (struct rl_softc *); 236#ifdef RE_FIXUP_RX 237static __inline void re_fixup_rx 238 (struct mbuf *); 239#endif 240static int re_rxeof (struct rl_softc *); 241static void re_txeof (struct rl_softc *); 242#ifdef DEVICE_POLLING 243static void re_poll (struct ifnet *, enum poll_cmd, int); 244static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 245#endif 246static int re_intr (void *); 247static void re_tick (void *); 248static void re_tx_task (void *, int); 249static void re_int_task (void *, int); 250static void re_start (struct ifnet *); 251static int re_ioctl (struct ifnet *, u_long, caddr_t); 252static void re_init (void *); 253static void re_init_locked (struct rl_softc *); 254static void re_stop (struct rl_softc *); 255static void re_watchdog (struct rl_softc *); 256static int re_suspend (device_t); 257static int re_resume (device_t); 258static int re_shutdown (device_t); 259static int re_ifmedia_upd (struct ifnet *); 260static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 261 262static void re_eeprom_putbyte (struct rl_softc *, int); 263static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 264static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 265static int re_gmii_readreg (device_t, int, int); 266static int re_gmii_writereg (device_t, int, int, int); 267 268static int re_miibus_readreg (device_t, int, int); 269static int re_miibus_writereg (device_t, int, int, int); 270static void re_miibus_statchg (device_t); 271 272static void re_set_rxmode (struct rl_softc *); 273static void re_reset (struct rl_softc *); 274static void re_setwol (struct rl_softc *); 275static void re_clrwol (struct rl_softc *); 276 277#ifdef RE_DIAG 278static int re_diag (struct rl_softc *); 279#endif 280 281static device_method_t re_methods[] = { 282 /* Device interface */ 283 DEVMETHOD(device_probe, re_probe), 284 DEVMETHOD(device_attach, re_attach), 285 DEVMETHOD(device_detach, re_detach), 286 DEVMETHOD(device_suspend, re_suspend), 287 DEVMETHOD(device_resume, re_resume), 288 DEVMETHOD(device_shutdown, re_shutdown), 289 290 /* bus interface */ 291 DEVMETHOD(bus_print_child, bus_generic_print_child), 292 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 293 294 /* MII interface */ 295 DEVMETHOD(miibus_readreg, re_miibus_readreg), 296 DEVMETHOD(miibus_writereg, re_miibus_writereg), 297 DEVMETHOD(miibus_statchg, re_miibus_statchg), 298 299 { 0, 0 } 300}; 301 302static driver_t re_driver = { 303 "re", 304 re_methods, 305 sizeof(struct rl_softc) 306}; 307 308static devclass_t re_devclass; 309 310DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 311DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 312DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 313 314#define EE_SET(x) \ 315 CSR_WRITE_1(sc, RL_EECMD, \ 316 CSR_READ_1(sc, RL_EECMD) | x) 317 318#define EE_CLR(x) \ 319 CSR_WRITE_1(sc, RL_EECMD, \ 320 CSR_READ_1(sc, RL_EECMD) & ~x) 321 322/* 323 * Send a read command and address to the EEPROM, check for ACK. 324 */ 325static void 326re_eeprom_putbyte(struct rl_softc *sc, int addr) 327{ 328 int d, i; 329 330 d = addr | (RL_9346_READ << sc->rl_eewidth); 331 332 /* 333 * Feed in each bit and strobe the clock. 334 */ 335 336 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 337 if (d & i) { 338 EE_SET(RL_EE_DATAIN); 339 } else { 340 EE_CLR(RL_EE_DATAIN); 341 } 342 DELAY(100); 343 EE_SET(RL_EE_CLK); 344 DELAY(150); 345 EE_CLR(RL_EE_CLK); 346 DELAY(100); 347 } 348} 349 350/* 351 * Read a word of data stored in the EEPROM at address 'addr.' 352 */ 353static void 354re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 355{ 356 int i; 357 u_int16_t word = 0; 358 359 /* 360 * Send address of word we want to read. 361 */ 362 re_eeprom_putbyte(sc, addr); 363 364 /* 365 * Start reading bits from EEPROM. 366 */ 367 for (i = 0x8000; i; i >>= 1) { 368 EE_SET(RL_EE_CLK); 369 DELAY(100); 370 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 371 word |= i; 372 EE_CLR(RL_EE_CLK); 373 DELAY(100); 374 } 375 376 *dest = word; 377} 378 379/* 380 * Read a sequence of words from the EEPROM. 381 */ 382static void 383re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 384{ 385 int i; 386 u_int16_t word = 0, *ptr; 387 388 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 389 390 DELAY(100); 391 392 for (i = 0; i < cnt; i++) { 393 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 394 re_eeprom_getword(sc, off + i, &word); 395 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 396 ptr = (u_int16_t *)(dest + (i * 2)); 397 *ptr = word; 398 } 399 400 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 401} 402 403static int 404re_gmii_readreg(device_t dev, int phy, int reg) 405{ 406 struct rl_softc *sc; 407 u_int32_t rval; 408 int i; 409 410 if (phy != 1) 411 return (0); 412 413 sc = device_get_softc(dev); 414 415 /* Let the rgephy driver read the GMEDIASTAT register */ 416 417 if (reg == RL_GMEDIASTAT) { 418 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 419 return (rval); 420 } 421 422 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 423 424 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 425 rval = CSR_READ_4(sc, RL_PHYAR); 426 if (rval & RL_PHYAR_BUSY) 427 break; 428 DELAY(100); 429 } 430 431 if (i == RL_PHY_TIMEOUT) { 432 device_printf(sc->rl_dev, "PHY read failed\n"); 433 return (0); 434 } 435 436 return (rval & RL_PHYAR_PHYDATA); 437} 438 439static int 440re_gmii_writereg(device_t dev, int phy, int reg, int data) 441{ 442 struct rl_softc *sc; 443 u_int32_t rval; 444 int i; 445 446 sc = device_get_softc(dev); 447 448 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 449 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 450 451 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 452 rval = CSR_READ_4(sc, RL_PHYAR); 453 if (!(rval & RL_PHYAR_BUSY)) 454 break; 455 DELAY(100); 456 } 457 458 if (i == RL_PHY_TIMEOUT) { 459 device_printf(sc->rl_dev, "PHY write failed\n"); 460 return (0); 461 } 462 463 return (0); 464} 465 466static int 467re_miibus_readreg(device_t dev, int phy, int reg) 468{ 469 struct rl_softc *sc; 470 u_int16_t rval = 0; 471 u_int16_t re8139_reg = 0; 472 473 sc = device_get_softc(dev); 474 475 if (sc->rl_type == RL_8169) { 476 rval = re_gmii_readreg(dev, phy, reg); 477 return (rval); 478 } 479 480 /* Pretend the internal PHY is only at address 0 */ 481 if (phy) { 482 return (0); 483 } 484 switch (reg) { 485 case MII_BMCR: 486 re8139_reg = RL_BMCR; 487 break; 488 case MII_BMSR: 489 re8139_reg = RL_BMSR; 490 break; 491 case MII_ANAR: 492 re8139_reg = RL_ANAR; 493 break; 494 case MII_ANER: 495 re8139_reg = RL_ANER; 496 break; 497 case MII_ANLPAR: 498 re8139_reg = RL_LPAR; 499 break; 500 case MII_PHYIDR1: 501 case MII_PHYIDR2: 502 return (0); 503 /* 504 * Allow the rlphy driver to read the media status 505 * register. If we have a link partner which does not 506 * support NWAY, this is the register which will tell 507 * us the results of parallel detection. 508 */ 509 case RL_MEDIASTAT: 510 rval = CSR_READ_1(sc, RL_MEDIASTAT); 511 return (rval); 512 default: 513 device_printf(sc->rl_dev, "bad phy register\n"); 514 return (0); 515 } 516 rval = CSR_READ_2(sc, re8139_reg); 517 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 518 /* 8139C+ has different bit layout. */ 519 rval &= ~(BMCR_LOOP | BMCR_ISO); 520 } 521 return (rval); 522} 523 524static int 525re_miibus_writereg(device_t dev, int phy, int reg, int data) 526{ 527 struct rl_softc *sc; 528 u_int16_t re8139_reg = 0; 529 int rval = 0; 530 531 sc = device_get_softc(dev); 532 533 if (sc->rl_type == RL_8169) { 534 rval = re_gmii_writereg(dev, phy, reg, data); 535 return (rval); 536 } 537 538 /* Pretend the internal PHY is only at address 0 */ 539 if (phy) 540 return (0); 541 542 switch (reg) { 543 case MII_BMCR: 544 re8139_reg = RL_BMCR; 545 if (sc->rl_type == RL_8139CPLUS) { 546 /* 8139C+ has different bit layout. */ 547 data &= ~(BMCR_LOOP | BMCR_ISO); 548 } 549 break; 550 case MII_BMSR: 551 re8139_reg = RL_BMSR; 552 break; 553 case MII_ANAR: 554 re8139_reg = RL_ANAR; 555 break; 556 case MII_ANER: 557 re8139_reg = RL_ANER; 558 break; 559 case MII_ANLPAR: 560 re8139_reg = RL_LPAR; 561 break; 562 case MII_PHYIDR1: 563 case MII_PHYIDR2: 564 return (0); 565 break; 566 default: 567 device_printf(sc->rl_dev, "bad phy register\n"); 568 return (0); 569 } 570 CSR_WRITE_2(sc, re8139_reg, data); 571 return (0); 572} 573 574static void 575re_miibus_statchg(device_t dev) 576{ 577 struct rl_softc *sc; 578 struct ifnet *ifp; 579 struct mii_data *mii; 580 581 sc = device_get_softc(dev); 582 mii = device_get_softc(sc->rl_miibus); 583 ifp = sc->rl_ifp; 584 if (mii == NULL || ifp == NULL || 585 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 586 return; 587 588 sc->rl_flags &= ~RL_FLAG_LINK; 589 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 590 (IFM_ACTIVE | IFM_AVALID)) { 591 switch (IFM_SUBTYPE(mii->mii_media_active)) { 592 case IFM_10_T: 593 case IFM_100_TX: 594 sc->rl_flags |= RL_FLAG_LINK; 595 break; 596 case IFM_1000_T: 597 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 598 break; 599 sc->rl_flags |= RL_FLAG_LINK; 600 break; 601 default: 602 break; 603 } 604 } 605 /* 606 * RealTek controllers does not provide any interface to 607 * Tx/Rx MACs for resolved speed, duplex and flow-control 608 * parameters. 609 */ 610} 611 612/* 613 * Set the RX configuration and 64-bit multicast hash filter. 614 */ 615static void 616re_set_rxmode(struct rl_softc *sc) 617{ 618 struct ifnet *ifp; 619 struct ifmultiaddr *ifma; 620 uint32_t hashes[2] = { 0, 0 }; 621 uint32_t h, rxfilt; 622 623 RL_LOCK_ASSERT(sc); 624 625 ifp = sc->rl_ifp; 626 627 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 628 629 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 630 if (ifp->if_flags & IFF_PROMISC) 631 rxfilt |= RL_RXCFG_RX_ALLPHYS; 632 /* 633 * Unlike other hardwares, we have to explicitly set 634 * RL_RXCFG_RX_MULTI to receive multicast frames in 635 * promiscuous mode. 636 */ 637 rxfilt |= RL_RXCFG_RX_MULTI; 638 hashes[0] = hashes[1] = 0xffffffff; 639 goto done; 640 } 641 642 IF_ADDR_LOCK(ifp); 643 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 644 if (ifma->ifma_addr->sa_family != AF_LINK) 645 continue; 646 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 647 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 648 if (h < 32) 649 hashes[0] |= (1 << h); 650 else 651 hashes[1] |= (1 << (h - 32)); 652 } 653 IF_ADDR_UNLOCK(ifp); 654 655 if (hashes[0] != 0 || hashes[1] != 0) { 656 /* 657 * For some unfathomable reason, RealTek decided to 658 * reverse the order of the multicast hash registers 659 * in the PCI Express parts. This means we have to 660 * write the hash pattern in reverse order for those 661 * devices. 662 */ 663 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 664 h = bswap32(hashes[0]); 665 hashes[0] = bswap32(hashes[1]); 666 hashes[1] = h; 667 } 668 rxfilt |= RL_RXCFG_RX_MULTI; 669 } 670 671done: 672 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 673 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 674 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 675} 676 677static void 678re_reset(struct rl_softc *sc) 679{ 680 int i; 681 682 RL_LOCK_ASSERT(sc); 683 684 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 685 686 for (i = 0; i < RL_TIMEOUT; i++) { 687 DELAY(10); 688 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 689 break; 690 } 691 if (i == RL_TIMEOUT) 692 device_printf(sc->rl_dev, "reset never completed!\n"); 693 694 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 695 CSR_WRITE_1(sc, 0x82, 1); 696 if (sc->rl_hwrev == RL_HWREV_8169S) 697 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 698} 699 700#ifdef RE_DIAG 701 702/* 703 * The following routine is designed to test for a defect on some 704 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 705 * lines connected to the bus, however for a 32-bit only card, they 706 * should be pulled high. The result of this defect is that the 707 * NIC will not work right if you plug it into a 64-bit slot: DMA 708 * operations will be done with 64-bit transfers, which will fail 709 * because the 64-bit data lines aren't connected. 710 * 711 * There's no way to work around this (short of talking a soldering 712 * iron to the board), however we can detect it. The method we use 713 * here is to put the NIC into digital loopback mode, set the receiver 714 * to promiscuous mode, and then try to send a frame. We then compare 715 * the frame data we sent to what was received. If the data matches, 716 * then the NIC is working correctly, otherwise we know the user has 717 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 718 * slot. In the latter case, there's no way the NIC can work correctly, 719 * so we print out a message on the console and abort the device attach. 720 */ 721 722static int 723re_diag(struct rl_softc *sc) 724{ 725 struct ifnet *ifp = sc->rl_ifp; 726 struct mbuf *m0; 727 struct ether_header *eh; 728 struct rl_desc *cur_rx; 729 u_int16_t status; 730 u_int32_t rxstat; 731 int total_len, i, error = 0, phyaddr; 732 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 733 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 734 735 /* Allocate a single mbuf */ 736 MGETHDR(m0, M_DONTWAIT, MT_DATA); 737 if (m0 == NULL) 738 return (ENOBUFS); 739 740 RL_LOCK(sc); 741 742 /* 743 * Initialize the NIC in test mode. This sets the chip up 744 * so that it can send and receive frames, but performs the 745 * following special functions: 746 * - Puts receiver in promiscuous mode 747 * - Enables digital loopback mode 748 * - Leaves interrupts turned off 749 */ 750 751 ifp->if_flags |= IFF_PROMISC; 752 sc->rl_testmode = 1; 753 re_init_locked(sc); 754 sc->rl_flags |= RL_FLAG_LINK; 755 if (sc->rl_type == RL_8169) 756 phyaddr = 1; 757 else 758 phyaddr = 0; 759 760 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 761 for (i = 0; i < RL_TIMEOUT; i++) { 762 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 763 if (!(status & BMCR_RESET)) 764 break; 765 } 766 767 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 768 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 769 770 DELAY(100000); 771 772 /* Put some data in the mbuf */ 773 774 eh = mtod(m0, struct ether_header *); 775 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 776 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 777 eh->ether_type = htons(ETHERTYPE_IP); 778 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 779 780 /* 781 * Queue the packet, start transmission. 782 * Note: IF_HANDOFF() ultimately calls re_start() for us. 783 */ 784 785 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 786 RL_UNLOCK(sc); 787 /* XXX: re_diag must not be called when in ALTQ mode */ 788 IF_HANDOFF(&ifp->if_snd, m0, ifp); 789 RL_LOCK(sc); 790 m0 = NULL; 791 792 /* Wait for it to propagate through the chip */ 793 794 DELAY(100000); 795 for (i = 0; i < RL_TIMEOUT; i++) { 796 status = CSR_READ_2(sc, RL_ISR); 797 CSR_WRITE_2(sc, RL_ISR, status); 798 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 799 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 800 break; 801 DELAY(10); 802 } 803 804 if (i == RL_TIMEOUT) { 805 device_printf(sc->rl_dev, 806 "diagnostic failed, failed to receive packet in" 807 " loopback mode\n"); 808 error = EIO; 809 goto done; 810 } 811 812 /* 813 * The packet should have been dumped into the first 814 * entry in the RX DMA ring. Grab it from there. 815 */ 816 817 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 818 sc->rl_ldata.rl_rx_list_map, 819 BUS_DMASYNC_POSTREAD); 820 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 821 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 822 BUS_DMASYNC_POSTREAD); 823 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 824 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 825 826 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 827 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 828 eh = mtod(m0, struct ether_header *); 829 830 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 831 total_len = RL_RXBYTES(cur_rx); 832 rxstat = le32toh(cur_rx->rl_cmdstat); 833 834 if (total_len != ETHER_MIN_LEN) { 835 device_printf(sc->rl_dev, 836 "diagnostic failed, received short packet\n"); 837 error = EIO; 838 goto done; 839 } 840 841 /* Test that the received packet data matches what we sent. */ 842 843 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 844 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 845 ntohs(eh->ether_type) != ETHERTYPE_IP) { 846 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 847 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 848 dst, ":", src, ":", ETHERTYPE_IP); 849 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 850 eh->ether_dhost, ":", eh->ether_shost, ":", 851 ntohs(eh->ether_type)); 852 device_printf(sc->rl_dev, "You may have a defective 32-bit " 853 "NIC plugged into a 64-bit PCI slot.\n"); 854 device_printf(sc->rl_dev, "Please re-install the NIC in a " 855 "32-bit slot for proper operation.\n"); 856 device_printf(sc->rl_dev, "Read the re(4) man page for more " 857 "details.\n"); 858 error = EIO; 859 } 860 861done: 862 /* Turn interface off, release resources */ 863 864 sc->rl_testmode = 0; 865 sc->rl_flags &= ~RL_FLAG_LINK; 866 ifp->if_flags &= ~IFF_PROMISC; 867 re_stop(sc); 868 if (m0 != NULL) 869 m_freem(m0); 870 871 RL_UNLOCK(sc); 872 873 return (error); 874} 875 876#endif 877 878/* 879 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 880 * IDs against our list and return a device name if we find a match. 881 */ 882static int 883re_probe(device_t dev) 884{ 885 struct rl_type *t; 886 uint16_t devid, vendor; 887 uint16_t revid, sdevid; 888 int i; 889 890 vendor = pci_get_vendor(dev); 891 devid = pci_get_device(dev); 892 revid = pci_get_revid(dev); 893 sdevid = pci_get_subdevice(dev); 894 895 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 896 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 897 /* 898 * Only attach to rev. 3 of the Linksys EG1032 adapter. 899 * Rev. 2 is supported by sk(4). 900 */ 901 return (ENXIO); 902 } 903 } 904 905 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 906 if (revid != 0x20) { 907 /* 8139, let rl(4) take care of this device. */ 908 return (ENXIO); 909 } 910 } 911 912 t = re_devs; 913 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 914 if (vendor == t->rl_vid && devid == t->rl_did) { 915 device_set_desc(dev, t->rl_name); 916 return (BUS_PROBE_DEFAULT); 917 } 918 } 919 920 return (ENXIO); 921} 922 923/* 924 * Map a single buffer address. 925 */ 926 927static void 928re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 929{ 930 bus_addr_t *addr; 931 932 if (error) 933 return; 934 935 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 936 addr = arg; 937 *addr = segs->ds_addr; 938} 939 940static int 941re_allocmem(device_t dev, struct rl_softc *sc) 942{ 943 bus_size_t rx_list_size, tx_list_size; 944 int error; 945 int i; 946 947 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 948 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 949 950 /* 951 * Allocate the parent bus DMA tag appropriate for PCI. 952 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 953 * register should be set. However some RealTek chips are known 954 * to be buggy on DAC handling, therefore disable DAC by limiting 955 * DMA address space to 32bit. PCIe variants of RealTek chips 956 * may not have the limitation but I took safer path. 957 */ 958 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 959 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 960 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 961 NULL, NULL, &sc->rl_parent_tag); 962 if (error) { 963 device_printf(dev, "could not allocate parent DMA tag\n"); 964 return (error); 965 } 966 967 /* 968 * Allocate map for TX mbufs. 969 */ 970 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 971 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 972 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 973 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 974 if (error) { 975 device_printf(dev, "could not allocate TX DMA tag\n"); 976 return (error); 977 } 978 979 /* 980 * Allocate map for RX mbufs. 981 */ 982 983 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 984 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 985 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 986 if (error) { 987 device_printf(dev, "could not allocate RX DMA tag\n"); 988 return (error); 989 } 990 991 /* 992 * Allocate map for TX descriptor list. 993 */ 994 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 995 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 996 NULL, tx_list_size, 1, tx_list_size, 0, 997 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 998 if (error) { 999 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1000 return (error); 1001 } 1002 1003 /* Allocate DMA'able memory for the TX ring */ 1004 1005 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1006 (void **)&sc->rl_ldata.rl_tx_list, 1007 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1008 &sc->rl_ldata.rl_tx_list_map); 1009 if (error) { 1010 device_printf(dev, "could not allocate TX DMA ring\n"); 1011 return (error); 1012 } 1013 1014 /* Load the map for the TX ring. */ 1015 1016 sc->rl_ldata.rl_tx_list_addr = 0; 1017 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1018 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1019 tx_list_size, re_dma_map_addr, 1020 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1021 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1022 device_printf(dev, "could not load TX DMA ring\n"); 1023 return (ENOMEM); 1024 } 1025 1026 /* Create DMA maps for TX buffers */ 1027 1028 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1029 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1030 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1031 if (error) { 1032 device_printf(dev, "could not create DMA map for TX\n"); 1033 return (error); 1034 } 1035 } 1036 1037 /* 1038 * Allocate map for RX descriptor list. 1039 */ 1040 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1041 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1042 NULL, rx_list_size, 1, rx_list_size, 0, 1043 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1044 if (error) { 1045 device_printf(dev, "could not create RX DMA ring tag\n"); 1046 return (error); 1047 } 1048 1049 /* Allocate DMA'able memory for the RX ring */ 1050 1051 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1052 (void **)&sc->rl_ldata.rl_rx_list, 1053 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1054 &sc->rl_ldata.rl_rx_list_map); 1055 if (error) { 1056 device_printf(dev, "could not allocate RX DMA ring\n"); 1057 return (error); 1058 } 1059 1060 /* Load the map for the RX ring. */ 1061 1062 sc->rl_ldata.rl_rx_list_addr = 0; 1063 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1064 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1065 rx_list_size, re_dma_map_addr, 1066 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1067 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1068 device_printf(dev, "could not load RX DMA ring\n"); 1069 return (ENOMEM); 1070 } 1071 1072 /* Create DMA maps for RX buffers */ 1073 1074 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1075 &sc->rl_ldata.rl_rx_sparemap); 1076 if (error) { 1077 device_printf(dev, "could not create spare DMA map for RX\n"); 1078 return (error); 1079 } 1080 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1081 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1082 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1083 if (error) { 1084 device_printf(dev, "could not create DMA map for RX\n"); 1085 return (error); 1086 } 1087 } 1088 1089 return (0); 1090} 1091 1092/* 1093 * Attach the interface. Allocate softc structures, do ifmedia 1094 * setup and ethernet/BPF attach. 1095 */ 1096static int 1097re_attach(device_t dev) 1098{ 1099 u_char eaddr[ETHER_ADDR_LEN]; 1100 u_int16_t as[ETHER_ADDR_LEN / 2]; 1101 struct rl_softc *sc; 1102 struct ifnet *ifp; 1103 struct rl_hwrev *hw_rev; 1104 int hwrev; 1105 u_int16_t devid, re_did = 0; 1106 int error = 0, rid, i; 1107 int msic, reg; 1108 uint8_t cfg; 1109 1110 sc = device_get_softc(dev); 1111 sc->rl_dev = dev; 1112 1113 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1114 MTX_DEF); 1115 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1116 1117 /* 1118 * Map control/status registers. 1119 */ 1120 pci_enable_busmaster(dev); 1121 1122 devid = pci_get_device(dev); 1123 /* 1124 * Prefer memory space register mapping over IO space. 1125 * Because RTL8169SC does not seem to work when memory mapping 1126 * is used always activate io mapping. 1127 */ 1128 if (devid == RT_DEVICEID_8169SC) 1129 prefer_iomap = 1; 1130 if (prefer_iomap == 0) { 1131 sc->rl_res_id = PCIR_BAR(1); 1132 sc->rl_res_type = SYS_RES_MEMORY; 1133 /* RTL8168/8101E seems to use different BARs. */ 1134 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1135 sc->rl_res_id = PCIR_BAR(2); 1136 } else { 1137 sc->rl_res_id = PCIR_BAR(0); 1138 sc->rl_res_type = SYS_RES_IOPORT; 1139 } 1140 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1141 &sc->rl_res_id, RF_ACTIVE); 1142 if (sc->rl_res == NULL && prefer_iomap == 0) { 1143 sc->rl_res_id = PCIR_BAR(0); 1144 sc->rl_res_type = SYS_RES_IOPORT; 1145 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1146 &sc->rl_res_id, RF_ACTIVE); 1147 } 1148 if (sc->rl_res == NULL) { 1149 device_printf(dev, "couldn't map ports/memory\n"); 1150 error = ENXIO; 1151 goto fail; 1152 } 1153 1154 sc->rl_btag = rman_get_bustag(sc->rl_res); 1155 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1156 1157 msic = 0; 1158 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1159 sc->rl_flags |= RL_FLAG_PCIE; 1160 msic = pci_msi_count(dev); 1161 if (bootverbose) 1162 device_printf(dev, "MSI count : %d\n", msic); 1163 } 1164 if (msic > 0 && msi_disable == 0) { 1165 msic = 1; 1166 if (pci_alloc_msi(dev, &msic) == 0) { 1167 if (msic == RL_MSI_MESSAGES) { 1168 device_printf(dev, "Using %d MSI messages\n", 1169 msic); 1170 sc->rl_flags |= RL_FLAG_MSI; 1171 /* Explicitly set MSI enable bit. */ 1172 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1173 cfg = CSR_READ_1(sc, RL_CFG2); 1174 cfg |= RL_CFG2_MSI; 1175 CSR_WRITE_1(sc, RL_CFG2, cfg); 1176 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1177 } else 1178 pci_release_msi(dev); 1179 } 1180 } 1181 1182 /* Allocate interrupt */ 1183 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1184 rid = 0; 1185 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1186 RF_SHAREABLE | RF_ACTIVE); 1187 if (sc->rl_irq[0] == NULL) { 1188 device_printf(dev, "couldn't allocate IRQ resources\n"); 1189 error = ENXIO; 1190 goto fail; 1191 } 1192 } else { 1193 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1194 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1195 SYS_RES_IRQ, &rid, RF_ACTIVE); 1196 if (sc->rl_irq[i] == NULL) { 1197 device_printf(dev, 1198 "couldn't llocate IRQ resources for " 1199 "message %d\n", rid); 1200 error = ENXIO; 1201 goto fail; 1202 } 1203 } 1204 } 1205 1206 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1207 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1208 cfg = CSR_READ_1(sc, RL_CFG2); 1209 if ((cfg & RL_CFG2_MSI) != 0) { 1210 device_printf(dev, "turning off MSI enable bit.\n"); 1211 cfg &= ~RL_CFG2_MSI; 1212 CSR_WRITE_1(sc, RL_CFG2, cfg); 1213 } 1214 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1215 } 1216 1217 /* Reset the adapter. */ 1218 RL_LOCK(sc); 1219 re_reset(sc); 1220 RL_UNLOCK(sc); 1221 1222 hw_rev = re_hwrevs; 1223 hwrev = CSR_READ_4(sc, RL_TXCFG); 1224 switch (hwrev & 0x70000000) { 1225 case 0x00000000: 1226 case 0x10000000: 1227 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1228 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1229 break; 1230 default: 1231 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1232 hwrev &= RL_TXCFG_HWREV; 1233 break; 1234 } 1235 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1236 while (hw_rev->rl_desc != NULL) { 1237 if (hw_rev->rl_rev == hwrev) { 1238 sc->rl_type = hw_rev->rl_type; 1239 sc->rl_hwrev = hw_rev->rl_rev; 1240 break; 1241 } 1242 hw_rev++; 1243 } 1244 if (hw_rev->rl_desc == NULL) { 1245 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1246 error = ENXIO; 1247 goto fail; 1248 } 1249 1250 switch (hw_rev->rl_rev) { 1251 case RL_HWREV_8139CPLUS: 1252 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER; 1253 break; 1254 case RL_HWREV_8100E: 1255 case RL_HWREV_8101E: 1256 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1257 RL_FLAG_FASTETHER; 1258 break; 1259 case RL_HWREV_8102E: 1260 case RL_HWREV_8102EL: 1261 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1262 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1263 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP; 1264 break; 1265 case RL_HWREV_8168_SPIN1: 1266 case RL_HWREV_8168_SPIN2: 1267 sc->rl_flags |= RL_FLAG_WOLRXENB; 1268 /* FALLTHROUGH */ 1269 case RL_HWREV_8168_SPIN3: 1270 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1271 break; 1272 case RL_HWREV_8168C_SPIN2: 1273 sc->rl_flags |= RL_FLAG_MACSLEEP; 1274 /* FALLTHROUGH */ 1275 case RL_HWREV_8168C: 1276 if ((hwrev & 0x00700000) == 0x00200000) 1277 sc->rl_flags |= RL_FLAG_MACSLEEP; 1278 /* FALLTHROUGH */ 1279 case RL_HWREV_8168CP: 1280 case RL_HWREV_8168D: 1281 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1282 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP; 1283 /* 1284 * These controllers support jumbo frame but it seems 1285 * that enabling it requires touching additional magic 1286 * registers. Depending on MAC revisions some 1287 * controllers need to disable checksum offload. So 1288 * disable jumbo frame until I have better idea what 1289 * it really requires to make it support. 1290 * RTL8168C/CP : supports up to 6KB jumbo frame. 1291 * RTL8111C/CP : supports up to 9KB jumbo frame. 1292 */ 1293 sc->rl_flags |= RL_FLAG_NOJUMBO; 1294 break; 1295 case RL_HWREV_8169_8110SB: 1296 case RL_HWREV_8169_8110SBL: 1297 case RL_HWREV_8169_8110SC: 1298 case RL_HWREV_8169_8110SCE: 1299 sc->rl_flags |= RL_FLAG_PHYWAKE; 1300 /* FALLTHROUGH */ 1301 case RL_HWREV_8169: 1302 case RL_HWREV_8169S: 1303 case RL_HWREV_8110S: 1304 sc->rl_flags |= RL_FLAG_MACRESET; 1305 break; 1306 default: 1307 break; 1308 } 1309 1310 /* Enable PME. */ 1311 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1312 cfg = CSR_READ_1(sc, RL_CFG1); 1313 cfg |= RL_CFG1_PME; 1314 CSR_WRITE_1(sc, RL_CFG1, cfg); 1315 cfg = CSR_READ_1(sc, RL_CFG5); 1316 cfg &= RL_CFG5_PME_STS; 1317 CSR_WRITE_1(sc, RL_CFG5, cfg); 1318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1319 1320 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1321 /* 1322 * XXX Should have a better way to extract station 1323 * address from EEPROM. 1324 */ 1325 for (i = 0; i < ETHER_ADDR_LEN; i++) 1326 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1327 } else { 1328 sc->rl_eewidth = RL_9356_ADDR_LEN; 1329 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1330 if (re_did != 0x8129) 1331 sc->rl_eewidth = RL_9346_ADDR_LEN; 1332 1333 /* 1334 * Get station address from the EEPROM. 1335 */ 1336 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1337 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1338 as[i] = le16toh(as[i]); 1339 bcopy(as, eaddr, sizeof(eaddr)); 1340 } 1341 1342 if (sc->rl_type == RL_8169) { 1343 /* Set RX length mask and number of descriptors. */ 1344 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1345 sc->rl_txstart = RL_GTXSTART; 1346 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1347 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1348 } else { 1349 /* Set RX length mask and number of descriptors. */ 1350 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1351 sc->rl_txstart = RL_TXSTART; 1352 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1353 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1354 } 1355 1356 error = re_allocmem(dev, sc); 1357 if (error) 1358 goto fail; 1359 1360 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1361 if (ifp == NULL) { 1362 device_printf(dev, "can not if_alloc()\n"); 1363 error = ENOSPC; 1364 goto fail; 1365 } 1366 1367 /* Take controller out of deep sleep mode. */ 1368 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1369 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1370 CSR_WRITE_1(sc, RL_GPIO, 1371 CSR_READ_1(sc, RL_GPIO) | 0x01); 1372 else 1373 CSR_WRITE_1(sc, RL_GPIO, 1374 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1375 } 1376 1377 /* Take PHY out of power down mode. */ 1378 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1379 re_gmii_writereg(dev, 1, 0x1f, 0); 1380 re_gmii_writereg(dev, 1, 0x0e, 0); 1381 } 1382 1383 /* Do MII setup */ 1384 if (mii_phy_probe(dev, &sc->rl_miibus, 1385 re_ifmedia_upd, re_ifmedia_sts)) { 1386 device_printf(dev, "MII without any phy!\n"); 1387 error = ENXIO; 1388 goto fail; 1389 } 1390 1391 ifp->if_softc = sc; 1392 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1393 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1394 ifp->if_ioctl = re_ioctl; 1395 ifp->if_start = re_start; 1396 ifp->if_hwassist = RE_CSUM_FEATURES; 1397 ifp->if_capabilities = IFCAP_HWCSUM; 1398 ifp->if_capenable = ifp->if_capabilities; 1399 ifp->if_init = re_init; 1400 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1401 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1402 IFQ_SET_READY(&ifp->if_snd); 1403 1404 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1405 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1406 1407 /* 1408 * XXX 1409 * Still have no idea how to make TSO work on 8168C, 8168CP, 1410 * 8111C and 8111CP. 1411 */ 1412 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1413 ifp->if_hwassist |= CSUM_TSO; 1414 ifp->if_capabilities |= IFCAP_TSO4; 1415 } 1416 1417 /* 1418 * Call MI attach routine. 1419 */ 1420 ether_ifattach(ifp, eaddr); 1421 1422 /* VLAN capability setup */ 1423 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1424 if (ifp->if_capabilities & IFCAP_HWCSUM) 1425 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1426 /* Enable WOL if PM is supported. */ 1427 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1428 ifp->if_capabilities |= IFCAP_WOL; 1429 ifp->if_capenable = ifp->if_capabilities; 1430 /* 1431 * Don't enable TSO by default. Under certain 1432 * circumtances the controller generated corrupted 1433 * packets in TSO size. 1434 */ 1435 ifp->if_hwassist &= ~CSUM_TSO; 1436 ifp->if_capenable &= ~IFCAP_TSO4; 1437#ifdef DEVICE_POLLING 1438 ifp->if_capabilities |= IFCAP_POLLING; 1439#endif 1440 /* 1441 * Tell the upper layer(s) we support long frames. 1442 * Must appear after the call to ether_ifattach() because 1443 * ether_ifattach() sets ifi_hdrlen to the default value. 1444 */ 1445 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1446 1447#ifdef RE_DIAG 1448 /* 1449 * Perform hardware diagnostic on the original RTL8169. 1450 * Some 32-bit cards were incorrectly wired and would 1451 * malfunction if plugged into a 64-bit slot. 1452 */ 1453 1454 if (hwrev == RL_HWREV_8169) { 1455 error = re_diag(sc); 1456 if (error) { 1457 device_printf(dev, 1458 "attach aborted due to hardware diag failure\n"); 1459 ether_ifdetach(ifp); 1460 goto fail; 1461 } 1462 } 1463#endif 1464 1465 /* Hook interrupt last to avoid having to lock softc */ 1466 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1467 error = bus_setup_intr(dev, sc->rl_irq[0], 1468 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1469 &sc->rl_intrhand[0]); 1470 else { 1471 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1472 error = bus_setup_intr(dev, sc->rl_irq[i], 1473 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1474 &sc->rl_intrhand[i]); 1475 if (error != 0) 1476 break; 1477 } 1478 } 1479 if (error) { 1480 device_printf(dev, "couldn't set up irq\n"); 1481 ether_ifdetach(ifp); 1482 } 1483 1484fail: 1485 1486 if (error) 1487 re_detach(dev); 1488 1489 return (error); 1490} 1491 1492/* 1493 * Shutdown hardware and free up resources. This can be called any 1494 * time after the mutex has been initialized. It is called in both 1495 * the error case in attach and the normal detach case so it needs 1496 * to be careful about only freeing resources that have actually been 1497 * allocated. 1498 */ 1499static int 1500re_detach(device_t dev) 1501{ 1502 struct rl_softc *sc; 1503 struct ifnet *ifp; 1504 int i, rid; 1505 1506 sc = device_get_softc(dev); 1507 ifp = sc->rl_ifp; 1508 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1509 1510 /* These should only be active if attach succeeded */ 1511 if (device_is_attached(dev)) { 1512#ifdef DEVICE_POLLING 1513 if (ifp->if_capenable & IFCAP_POLLING) 1514 ether_poll_deregister(ifp); 1515#endif 1516 RL_LOCK(sc); 1517#if 0 1518 sc->suspended = 1; 1519#endif 1520 re_stop(sc); 1521 RL_UNLOCK(sc); 1522 callout_drain(&sc->rl_stat_callout); 1523 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1524 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1525 /* 1526 * Force off the IFF_UP flag here, in case someone 1527 * still had a BPF descriptor attached to this 1528 * interface. If they do, ether_ifdetach() will cause 1529 * the BPF code to try and clear the promisc mode 1530 * flag, which will bubble down to re_ioctl(), 1531 * which will try to call re_init() again. This will 1532 * turn the NIC back on and restart the MII ticker, 1533 * which will panic the system when the kernel tries 1534 * to invoke the re_tick() function that isn't there 1535 * anymore. 1536 */ 1537 ifp->if_flags &= ~IFF_UP; 1538 ether_ifdetach(ifp); 1539 } 1540 if (sc->rl_miibus) 1541 device_delete_child(dev, sc->rl_miibus); 1542 bus_generic_detach(dev); 1543 1544 /* 1545 * The rest is resource deallocation, so we should already be 1546 * stopped here. 1547 */ 1548 1549 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1550 if (sc->rl_intrhand[i] != NULL) { 1551 bus_teardown_intr(dev, sc->rl_irq[i], 1552 sc->rl_intrhand[i]); 1553 sc->rl_intrhand[i] = NULL; 1554 } 1555 } 1556 if (ifp != NULL) 1557 if_free(ifp); 1558 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1559 if (sc->rl_irq[0] != NULL) { 1560 bus_release_resource(dev, SYS_RES_IRQ, 0, 1561 sc->rl_irq[0]); 1562 sc->rl_irq[0] = NULL; 1563 } 1564 } else { 1565 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1566 if (sc->rl_irq[i] != NULL) { 1567 bus_release_resource(dev, SYS_RES_IRQ, rid, 1568 sc->rl_irq[i]); 1569 sc->rl_irq[i] = NULL; 1570 } 1571 } 1572 pci_release_msi(dev); 1573 } 1574 if (sc->rl_res) 1575 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1576 sc->rl_res); 1577 1578 /* Unload and free the RX DMA ring memory and map */ 1579 1580 if (sc->rl_ldata.rl_rx_list_tag) { 1581 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1582 sc->rl_ldata.rl_rx_list_map); 1583 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1584 sc->rl_ldata.rl_rx_list, 1585 sc->rl_ldata.rl_rx_list_map); 1586 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1587 } 1588 1589 /* Unload and free the TX DMA ring memory and map */ 1590 1591 if (sc->rl_ldata.rl_tx_list_tag) { 1592 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1593 sc->rl_ldata.rl_tx_list_map); 1594 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1595 sc->rl_ldata.rl_tx_list, 1596 sc->rl_ldata.rl_tx_list_map); 1597 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1598 } 1599 1600 /* Destroy all the RX and TX buffer maps */ 1601 1602 if (sc->rl_ldata.rl_tx_mtag) { 1603 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1604 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1605 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1606 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1607 } 1608 if (sc->rl_ldata.rl_rx_mtag) { 1609 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1610 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1611 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1612 if (sc->rl_ldata.rl_rx_sparemap) 1613 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1614 sc->rl_ldata.rl_rx_sparemap); 1615 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1616 } 1617 1618 /* Unload and free the stats buffer and map */ 1619 1620 if (sc->rl_ldata.rl_stag) { 1621 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1622 sc->rl_ldata.rl_rx_list_map); 1623 bus_dmamem_free(sc->rl_ldata.rl_stag, 1624 sc->rl_ldata.rl_stats, 1625 sc->rl_ldata.rl_smap); 1626 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1627 } 1628 1629 if (sc->rl_parent_tag) 1630 bus_dma_tag_destroy(sc->rl_parent_tag); 1631 1632 mtx_destroy(&sc->rl_mtx); 1633 1634 return (0); 1635} 1636 1637static __inline void 1638re_discard_rxbuf(struct rl_softc *sc, int idx) 1639{ 1640 struct rl_desc *desc; 1641 struct rl_rxdesc *rxd; 1642 uint32_t cmdstat; 1643 1644 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1645 desc = &sc->rl_ldata.rl_rx_list[idx]; 1646 desc->rl_vlanctl = 0; 1647 cmdstat = rxd->rx_size; 1648 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1649 cmdstat |= RL_RDESC_CMD_EOR; 1650 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1651} 1652 1653static int 1654re_newbuf(struct rl_softc *sc, int idx) 1655{ 1656 struct mbuf *m; 1657 struct rl_rxdesc *rxd; 1658 bus_dma_segment_t segs[1]; 1659 bus_dmamap_t map; 1660 struct rl_desc *desc; 1661 uint32_t cmdstat; 1662 int error, nsegs; 1663 1664 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1665 if (m == NULL) 1666 return (ENOBUFS); 1667 1668 m->m_len = m->m_pkthdr.len = MCLBYTES; 1669#ifdef RE_FIXUP_RX 1670 /* 1671 * This is part of an evil trick to deal with non-x86 platforms. 1672 * The RealTek chip requires RX buffers to be aligned on 64-bit 1673 * boundaries, but that will hose non-x86 machines. To get around 1674 * this, we leave some empty space at the start of each buffer 1675 * and for non-x86 hosts, we copy the buffer back six bytes 1676 * to achieve word alignment. This is slightly more efficient 1677 * than allocating a new buffer, copying the contents, and 1678 * discarding the old buffer. 1679 */ 1680 m_adj(m, RE_ETHER_ALIGN); 1681#endif 1682 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1683 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1684 if (error != 0) { 1685 m_freem(m); 1686 return (ENOBUFS); 1687 } 1688 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1689 1690 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1691 if (rxd->rx_m != NULL) { 1692 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1693 BUS_DMASYNC_POSTREAD); 1694 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1695 } 1696 1697 rxd->rx_m = m; 1698 map = rxd->rx_dmamap; 1699 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1700 rxd->rx_size = segs[0].ds_len; 1701 sc->rl_ldata.rl_rx_sparemap = map; 1702 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1703 BUS_DMASYNC_PREREAD); 1704 1705 desc = &sc->rl_ldata.rl_rx_list[idx]; 1706 desc->rl_vlanctl = 0; 1707 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1708 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1709 cmdstat = segs[0].ds_len; 1710 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1711 cmdstat |= RL_RDESC_CMD_EOR; 1712 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1713 1714 return (0); 1715} 1716 1717#ifdef RE_FIXUP_RX 1718static __inline void 1719re_fixup_rx(struct mbuf *m) 1720{ 1721 int i; 1722 uint16_t *src, *dst; 1723 1724 src = mtod(m, uint16_t *); 1725 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1726 1727 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1728 *dst++ = *src++; 1729 1730 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1731} 1732#endif 1733 1734static int 1735re_tx_list_init(struct rl_softc *sc) 1736{ 1737 struct rl_desc *desc; 1738 int i; 1739 1740 RL_LOCK_ASSERT(sc); 1741 1742 bzero(sc->rl_ldata.rl_tx_list, 1743 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1744 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1745 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1746 /* Set EOR. */ 1747 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1748 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1749 1750 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1751 sc->rl_ldata.rl_tx_list_map, 1752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1753 1754 sc->rl_ldata.rl_tx_prodidx = 0; 1755 sc->rl_ldata.rl_tx_considx = 0; 1756 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1757 1758 return (0); 1759} 1760 1761static int 1762re_rx_list_init(struct rl_softc *sc) 1763{ 1764 int error, i; 1765 1766 bzero(sc->rl_ldata.rl_rx_list, 1767 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1768 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1769 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1770 if ((error = re_newbuf(sc, i)) != 0) 1771 return (error); 1772 } 1773 1774 /* Flush the RX descriptors */ 1775 1776 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1777 sc->rl_ldata.rl_rx_list_map, 1778 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1779 1780 sc->rl_ldata.rl_rx_prodidx = 0; 1781 sc->rl_head = sc->rl_tail = NULL; 1782 1783 return (0); 1784} 1785 1786/* 1787 * RX handler for C+ and 8169. For the gigE chips, we support 1788 * the reception of jumbo frames that have been fragmented 1789 * across multiple 2K mbuf cluster buffers. 1790 */ 1791static int 1792re_rxeof(struct rl_softc *sc) 1793{ 1794 struct mbuf *m; 1795 struct ifnet *ifp; 1796 int i, total_len; 1797 struct rl_desc *cur_rx; 1798 u_int32_t rxstat, rxvlan; 1799 int maxpkt = 16; 1800 1801 RL_LOCK_ASSERT(sc); 1802 1803 ifp = sc->rl_ifp; 1804 1805 /* Invalidate the descriptor memory */ 1806 1807 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1808 sc->rl_ldata.rl_rx_list_map, 1809 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1810 1811 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1812 i = RL_RX_DESC_NXT(sc, i)) { 1813 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1814 rxstat = le32toh(cur_rx->rl_cmdstat); 1815 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1816 break; 1817 total_len = rxstat & sc->rl_rxlenmask; 1818 rxvlan = le32toh(cur_rx->rl_vlanctl); 1819 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1820 1821 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1822 if (re_newbuf(sc, i) != 0) { 1823 /* 1824 * If this is part of a multi-fragment packet, 1825 * discard all the pieces. 1826 */ 1827 if (sc->rl_head != NULL) { 1828 m_freem(sc->rl_head); 1829 sc->rl_head = sc->rl_tail = NULL; 1830 } 1831 re_discard_rxbuf(sc, i); 1832 continue; 1833 } 1834 m->m_len = RE_RX_DESC_BUFLEN; 1835 if (sc->rl_head == NULL) 1836 sc->rl_head = sc->rl_tail = m; 1837 else { 1838 m->m_flags &= ~M_PKTHDR; 1839 sc->rl_tail->m_next = m; 1840 sc->rl_tail = m; 1841 } 1842 continue; 1843 } 1844 1845 /* 1846 * NOTE: for the 8139C+, the frame length field 1847 * is always 12 bits in size, but for the gigE chips, 1848 * it is 13 bits (since the max RX frame length is 16K). 1849 * Unfortunately, all 32 bits in the status word 1850 * were already used, so to make room for the extra 1851 * length bit, RealTek took out the 'frame alignment 1852 * error' bit and shifted the other status bits 1853 * over one slot. The OWN, EOR, FS and LS bits are 1854 * still in the same places. We have already extracted 1855 * the frame length and checked the OWN bit, so rather 1856 * than using an alternate bit mapping, we shift the 1857 * status bits one space to the right so we can evaluate 1858 * them using the 8169 status as though it was in the 1859 * same format as that of the 8139C+. 1860 */ 1861 if (sc->rl_type == RL_8169) 1862 rxstat >>= 1; 1863 1864 /* 1865 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1866 * set, but if CRC is clear, it will still be a valid frame. 1867 */ 1868 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1869 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1870 ifp->if_ierrors++; 1871 /* 1872 * If this is part of a multi-fragment packet, 1873 * discard all the pieces. 1874 */ 1875 if (sc->rl_head != NULL) { 1876 m_freem(sc->rl_head); 1877 sc->rl_head = sc->rl_tail = NULL; 1878 } 1879 re_discard_rxbuf(sc, i); 1880 continue; 1881 } 1882 1883 /* 1884 * If allocating a replacement mbuf fails, 1885 * reload the current one. 1886 */ 1887 1888 if (re_newbuf(sc, i) != 0) { 1889 ifp->if_iqdrops++; 1890 if (sc->rl_head != NULL) { 1891 m_freem(sc->rl_head); 1892 sc->rl_head = sc->rl_tail = NULL; 1893 } 1894 re_discard_rxbuf(sc, i); 1895 continue; 1896 } 1897 1898 if (sc->rl_head != NULL) { 1899 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1900 if (m->m_len == 0) 1901 m->m_len = RE_RX_DESC_BUFLEN; 1902 /* 1903 * Special case: if there's 4 bytes or less 1904 * in this buffer, the mbuf can be discarded: 1905 * the last 4 bytes is the CRC, which we don't 1906 * care about anyway. 1907 */ 1908 if (m->m_len <= ETHER_CRC_LEN) { 1909 sc->rl_tail->m_len -= 1910 (ETHER_CRC_LEN - m->m_len); 1911 m_freem(m); 1912 } else { 1913 m->m_len -= ETHER_CRC_LEN; 1914 m->m_flags &= ~M_PKTHDR; 1915 sc->rl_tail->m_next = m; 1916 } 1917 m = sc->rl_head; 1918 sc->rl_head = sc->rl_tail = NULL; 1919 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1920 } else 1921 m->m_pkthdr.len = m->m_len = 1922 (total_len - ETHER_CRC_LEN); 1923 1924#ifdef RE_FIXUP_RX 1925 re_fixup_rx(m); 1926#endif 1927 ifp->if_ipackets++; 1928 m->m_pkthdr.rcvif = ifp; 1929 1930 /* Do RX checksumming if enabled */ 1931 1932 if (ifp->if_capenable & IFCAP_RXCSUM) { 1933 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1934 /* Check IP header checksum */ 1935 if (rxstat & RL_RDESC_STAT_PROTOID) 1936 m->m_pkthdr.csum_flags |= 1937 CSUM_IP_CHECKED; 1938 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1939 m->m_pkthdr.csum_flags |= 1940 CSUM_IP_VALID; 1941 1942 /* Check TCP/UDP checksum */ 1943 if ((RL_TCPPKT(rxstat) && 1944 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1945 (RL_UDPPKT(rxstat) && 1946 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1947 m->m_pkthdr.csum_flags |= 1948 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1949 m->m_pkthdr.csum_data = 0xffff; 1950 } 1951 } else { 1952 /* 1953 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1954 */ 1955 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1956 (rxvlan & RL_RDESC_IPV4)) 1957 m->m_pkthdr.csum_flags |= 1958 CSUM_IP_CHECKED; 1959 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1960 (rxvlan & RL_RDESC_IPV4)) 1961 m->m_pkthdr.csum_flags |= 1962 CSUM_IP_VALID; 1963 if (((rxstat & RL_RDESC_STAT_TCP) && 1964 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1965 ((rxstat & RL_RDESC_STAT_UDP) && 1966 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1967 m->m_pkthdr.csum_flags |= 1968 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1969 m->m_pkthdr.csum_data = 0xffff; 1970 } 1971 } 1972 } 1973 maxpkt--; 1974 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1975 m->m_pkthdr.ether_vtag = 1976 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 1977 m->m_flags |= M_VLANTAG; 1978 } 1979 RL_UNLOCK(sc); 1980 (*ifp->if_input)(ifp, m); 1981 RL_LOCK(sc); 1982 } 1983 1984 /* Flush the RX DMA ring */ 1985 1986 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1987 sc->rl_ldata.rl_rx_list_map, 1988 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1989 1990 sc->rl_ldata.rl_rx_prodidx = i; 1991 1992 if (maxpkt) 1993 return(EAGAIN); 1994 1995 return(0); 1996} 1997 1998static void 1999re_txeof(struct rl_softc *sc) 2000{ 2001 struct ifnet *ifp; 2002 struct rl_txdesc *txd; 2003 u_int32_t txstat; 2004 int cons; 2005 2006 cons = sc->rl_ldata.rl_tx_considx; 2007 if (cons == sc->rl_ldata.rl_tx_prodidx) 2008 return; 2009 2010 ifp = sc->rl_ifp; 2011 /* Invalidate the TX descriptor list */ 2012 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2013 sc->rl_ldata.rl_tx_list_map, 2014 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2015 2016 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2017 cons = RL_TX_DESC_NXT(sc, cons)) { 2018 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2019 if (txstat & RL_TDESC_STAT_OWN) 2020 break; 2021 /* 2022 * We only stash mbufs in the last descriptor 2023 * in a fragment chain, which also happens to 2024 * be the only place where the TX status bits 2025 * are valid. 2026 */ 2027 if (txstat & RL_TDESC_CMD_EOF) { 2028 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2029 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2030 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2031 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2032 txd->tx_dmamap); 2033 KASSERT(txd->tx_m != NULL, 2034 ("%s: freeing NULL mbufs!", __func__)); 2035 m_freem(txd->tx_m); 2036 txd->tx_m = NULL; 2037 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2038 RL_TDESC_STAT_COLCNT)) 2039 ifp->if_collisions++; 2040 if (txstat & RL_TDESC_STAT_TXERRSUM) 2041 ifp->if_oerrors++; 2042 else 2043 ifp->if_opackets++; 2044 } 2045 sc->rl_ldata.rl_tx_free++; 2046 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2047 } 2048 sc->rl_ldata.rl_tx_considx = cons; 2049 2050 /* No changes made to the TX ring, so no flush needed */ 2051 2052 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2053#ifdef RE_TX_MODERATION 2054 /* 2055 * If not all descriptors have been reaped yet, reload 2056 * the timer so that we will eventually get another 2057 * interrupt that will cause us to re-enter this routine. 2058 * This is done in case the transmitter has gone idle. 2059 */ 2060 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2061#endif 2062 } else 2063 sc->rl_watchdog_timer = 0; 2064} 2065 2066static void 2067re_tick(void *xsc) 2068{ 2069 struct rl_softc *sc; 2070 struct mii_data *mii; 2071 2072 sc = xsc; 2073 2074 RL_LOCK_ASSERT(sc); 2075 2076 mii = device_get_softc(sc->rl_miibus); 2077 mii_tick(mii); 2078 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2079 re_miibus_statchg(sc->rl_dev); 2080 /* 2081 * Reclaim transmitted frames here. Technically it is not 2082 * necessary to do here but it ensures periodic reclamation 2083 * regardless of Tx completion interrupt which seems to be 2084 * lost on PCIe based controllers under certain situations. 2085 */ 2086 re_txeof(sc); 2087 re_watchdog(sc); 2088 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2089} 2090 2091#ifdef DEVICE_POLLING 2092static void 2093re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2094{ 2095 struct rl_softc *sc = ifp->if_softc; 2096 2097 RL_LOCK(sc); 2098 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2099 re_poll_locked(ifp, cmd, count); 2100 RL_UNLOCK(sc); 2101} 2102 2103static void 2104re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2105{ 2106 struct rl_softc *sc = ifp->if_softc; 2107 2108 RL_LOCK_ASSERT(sc); 2109 2110 sc->rxcycles = count; 2111 re_rxeof(sc); 2112 re_txeof(sc); 2113 2114 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2115 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2116 2117 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2118 u_int16_t status; 2119 2120 status = CSR_READ_2(sc, RL_ISR); 2121 if (status == 0xffff) 2122 return; 2123 if (status) 2124 CSR_WRITE_2(sc, RL_ISR, status); 2125 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2126 (sc->rl_flags & RL_FLAG_PCIE)) 2127 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2128 2129 /* 2130 * XXX check behaviour on receiver stalls. 2131 */ 2132 2133 if (status & RL_ISR_SYSTEM_ERR) 2134 re_init_locked(sc); 2135 } 2136} 2137#endif /* DEVICE_POLLING */ 2138 2139static int 2140re_intr(void *arg) 2141{ 2142 struct rl_softc *sc; 2143 uint16_t status; 2144 2145 sc = arg; 2146 2147 status = CSR_READ_2(sc, RL_ISR); 2148 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2149 return (FILTER_STRAY); 2150 CSR_WRITE_2(sc, RL_IMR, 0); 2151 2152 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2153 2154 return (FILTER_HANDLED); 2155} 2156 2157static void 2158re_int_task(void *arg, int npending) 2159{ 2160 struct rl_softc *sc; 2161 struct ifnet *ifp; 2162 u_int16_t status; 2163 int rval = 0; 2164 2165 sc = arg; 2166 ifp = sc->rl_ifp; 2167 2168 RL_LOCK(sc); 2169 2170 status = CSR_READ_2(sc, RL_ISR); 2171 CSR_WRITE_2(sc, RL_ISR, status); 2172 2173 if (sc->suspended || 2174 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2175 RL_UNLOCK(sc); 2176 return; 2177 } 2178 2179#ifdef DEVICE_POLLING 2180 if (ifp->if_capenable & IFCAP_POLLING) { 2181 RL_UNLOCK(sc); 2182 return; 2183 } 2184#endif 2185 2186 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2187 rval = re_rxeof(sc); 2188 2189 /* 2190 * Some chips will ignore a second TX request issued 2191 * while an existing transmission is in progress. If 2192 * the transmitter goes idle but there are still 2193 * packets waiting to be sent, we need to restart the 2194 * channel here to flush them out. This only seems to 2195 * be required with the PCIe devices. 2196 */ 2197 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2198 (sc->rl_flags & RL_FLAG_PCIE)) 2199 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2200 if (status & ( 2201#ifdef RE_TX_MODERATION 2202 RL_ISR_TIMEOUT_EXPIRED| 2203#else 2204 RL_ISR_TX_OK| 2205#endif 2206 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2207 re_txeof(sc); 2208 2209 if (status & RL_ISR_SYSTEM_ERR) 2210 re_init_locked(sc); 2211 2212 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2213 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2214 2215 RL_UNLOCK(sc); 2216 2217 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2218 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2219 return; 2220 } 2221 2222 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2223} 2224 2225static int 2226re_encap(struct rl_softc *sc, struct mbuf **m_head) 2227{ 2228 struct rl_txdesc *txd, *txd_last; 2229 bus_dma_segment_t segs[RL_NTXSEGS]; 2230 bus_dmamap_t map; 2231 struct mbuf *m_new; 2232 struct rl_desc *desc; 2233 int nsegs, prod; 2234 int i, error, ei, si; 2235 int padlen; 2236 uint32_t cmdstat, csum_flags, vlanctl; 2237 2238 RL_LOCK_ASSERT(sc); 2239 M_ASSERTPKTHDR((*m_head)); 2240 2241 /* 2242 * With some of the RealTek chips, using the checksum offload 2243 * support in conjunction with the autopadding feature results 2244 * in the transmission of corrupt frames. For example, if we 2245 * need to send a really small IP fragment that's less than 60 2246 * bytes in size, and IP header checksumming is enabled, the 2247 * resulting ethernet frame that appears on the wire will 2248 * have garbled payload. To work around this, if TX IP checksum 2249 * offload is enabled, we always manually pad short frames out 2250 * to the minimum ethernet frame size. 2251 */ 2252 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2253 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2254 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2255 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2256 if (M_WRITABLE(*m_head) == 0) { 2257 /* Get a writable copy. */ 2258 m_new = m_dup(*m_head, M_DONTWAIT); 2259 m_freem(*m_head); 2260 if (m_new == NULL) { 2261 *m_head = NULL; 2262 return (ENOBUFS); 2263 } 2264 *m_head = m_new; 2265 } 2266 if ((*m_head)->m_next != NULL || 2267 M_TRAILINGSPACE(*m_head) < padlen) { 2268 m_new = m_defrag(*m_head, M_DONTWAIT); 2269 if (m_new == NULL) { 2270 m_freem(*m_head); 2271 *m_head = NULL; 2272 return (ENOBUFS); 2273 } 2274 } else 2275 m_new = *m_head; 2276 2277 /* 2278 * Manually pad short frames, and zero the pad space 2279 * to avoid leaking data. 2280 */ 2281 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2282 m_new->m_pkthdr.len += padlen; 2283 m_new->m_len = m_new->m_pkthdr.len; 2284 *m_head = m_new; 2285 } 2286 2287 prod = sc->rl_ldata.rl_tx_prodidx; 2288 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2289 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2290 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2291 if (error == EFBIG) { 2292 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2293 if (m_new == NULL) { 2294 m_freem(*m_head); 2295 *m_head = NULL; 2296 return (ENOBUFS); 2297 } 2298 *m_head = m_new; 2299 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2300 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2301 if (error != 0) { 2302 m_freem(*m_head); 2303 *m_head = NULL; 2304 return (error); 2305 } 2306 } else if (error != 0) 2307 return (error); 2308 if (nsegs == 0) { 2309 m_freem(*m_head); 2310 *m_head = NULL; 2311 return (EIO); 2312 } 2313 2314 /* Check for number of available descriptors. */ 2315 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2316 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2317 return (ENOBUFS); 2318 } 2319 2320 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2321 BUS_DMASYNC_PREWRITE); 2322 2323 /* 2324 * Set up checksum offload. Note: checksum offload bits must 2325 * appear in all descriptors of a multi-descriptor transmit 2326 * attempt. This is according to testing done with an 8169 2327 * chip. This is a requirement. 2328 */ 2329 vlanctl = 0; 2330 csum_flags = 0; 2331 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2332 csum_flags = RL_TDESC_CMD_LGSEND | 2333 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2334 RL_TDESC_CMD_MSSVAL_SHIFT); 2335 else { 2336 /* 2337 * Unconditionally enable IP checksum if TCP or UDP 2338 * checksum is required. Otherwise, TCP/UDP checksum 2339 * does't make effects. 2340 */ 2341 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2342 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2343 csum_flags |= RL_TDESC_CMD_IPCSUM; 2344 if (((*m_head)->m_pkthdr.csum_flags & 2345 CSUM_TCP) != 0) 2346 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2347 if (((*m_head)->m_pkthdr.csum_flags & 2348 CSUM_UDP) != 0) 2349 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2350 } else { 2351 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2352 if (((*m_head)->m_pkthdr.csum_flags & 2353 CSUM_TCP) != 0) 2354 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2355 if (((*m_head)->m_pkthdr.csum_flags & 2356 CSUM_UDP) != 0) 2357 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2358 } 2359 } 2360 } 2361 2362 /* 2363 * Set up hardware VLAN tagging. Note: vlan tag info must 2364 * appear in all descriptors of a multi-descriptor 2365 * transmission attempt. 2366 */ 2367 if ((*m_head)->m_flags & M_VLANTAG) 2368 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2369 RL_TDESC_VLANCTL_TAG; 2370 2371 si = prod; 2372 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2373 desc = &sc->rl_ldata.rl_tx_list[prod]; 2374 desc->rl_vlanctl = htole32(vlanctl); 2375 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2376 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2377 cmdstat = segs[i].ds_len; 2378 if (i != 0) 2379 cmdstat |= RL_TDESC_CMD_OWN; 2380 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2381 cmdstat |= RL_TDESC_CMD_EOR; 2382 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2383 sc->rl_ldata.rl_tx_free--; 2384 } 2385 /* Update producer index. */ 2386 sc->rl_ldata.rl_tx_prodidx = prod; 2387 2388 /* Set EOF on the last descriptor. */ 2389 ei = RL_TX_DESC_PRV(sc, prod); 2390 desc = &sc->rl_ldata.rl_tx_list[ei]; 2391 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2392 2393 desc = &sc->rl_ldata.rl_tx_list[si]; 2394 /* Set SOF and transfer ownership of packet to the chip. */ 2395 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2396 2397 /* 2398 * Insure that the map for this transmission 2399 * is placed at the array index of the last descriptor 2400 * in this chain. (Swap last and first dmamaps.) 2401 */ 2402 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2403 map = txd->tx_dmamap; 2404 txd->tx_dmamap = txd_last->tx_dmamap; 2405 txd_last->tx_dmamap = map; 2406 txd_last->tx_m = *m_head; 2407 2408 return (0); 2409} 2410 2411static void 2412re_tx_task(void *arg, int npending) 2413{ 2414 struct ifnet *ifp; 2415 2416 ifp = arg; 2417 re_start(ifp); 2418} 2419 2420/* 2421 * Main transmit routine for C+ and gigE NICs. 2422 */ 2423static void 2424re_start(struct ifnet *ifp) 2425{ 2426 struct rl_softc *sc; 2427 struct mbuf *m_head; 2428 int queued; 2429 2430 sc = ifp->if_softc; 2431 2432 RL_LOCK(sc); 2433 2434 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2435 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2436 RL_UNLOCK(sc); 2437 return; 2438 } 2439 2440 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2441 sc->rl_ldata.rl_tx_free > 1;) { 2442 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2443 if (m_head == NULL) 2444 break; 2445 2446 if (re_encap(sc, &m_head) != 0) { 2447 if (m_head == NULL) 2448 break; 2449 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2450 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2451 break; 2452 } 2453 2454 /* 2455 * If there's a BPF listener, bounce a copy of this frame 2456 * to him. 2457 */ 2458 ETHER_BPF_MTAP(ifp, m_head); 2459 2460 queued++; 2461 } 2462 2463 if (queued == 0) { 2464#ifdef RE_TX_MODERATION 2465 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2466 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2467#endif 2468 RL_UNLOCK(sc); 2469 return; 2470 } 2471 2472 /* Flush the TX descriptors */ 2473 2474 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2475 sc->rl_ldata.rl_tx_list_map, 2476 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2477 2478 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2479 2480#ifdef RE_TX_MODERATION 2481 /* 2482 * Use the countdown timer for interrupt moderation. 2483 * 'TX done' interrupts are disabled. Instead, we reset the 2484 * countdown timer, which will begin counting until it hits 2485 * the value in the TIMERINT register, and then trigger an 2486 * interrupt. Each time we write to the TIMERCNT register, 2487 * the timer count is reset to 0. 2488 */ 2489 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2490#endif 2491 2492 /* 2493 * Set a timeout in case the chip goes out to lunch. 2494 */ 2495 sc->rl_watchdog_timer = 5; 2496 2497 RL_UNLOCK(sc); 2498} 2499 2500static void 2501re_init(void *xsc) 2502{ 2503 struct rl_softc *sc = xsc; 2504 2505 RL_LOCK(sc); 2506 re_init_locked(sc); 2507 RL_UNLOCK(sc); 2508} 2509 2510static void 2511re_init_locked(struct rl_softc *sc) 2512{ 2513 struct ifnet *ifp = sc->rl_ifp; 2514 struct mii_data *mii; 2515 uint32_t reg; 2516 uint16_t cfg; 2517 union { 2518 uint32_t align_dummy; 2519 u_char eaddr[ETHER_ADDR_LEN]; 2520 } eaddr; 2521 2522 RL_LOCK_ASSERT(sc); 2523 2524 mii = device_get_softc(sc->rl_miibus); 2525 2526 /* 2527 * Cancel pending I/O and free all RX/TX buffers. 2528 */ 2529 re_stop(sc); 2530 2531 /* Put controller into known state. */ 2532 re_reset(sc); 2533 2534 /* 2535 * Enable C+ RX and TX mode, as well as VLAN stripping and 2536 * RX checksum offload. We must configure the C+ register 2537 * before all others. 2538 */ 2539 cfg = RL_CPLUSCMD_PCI_MRW; 2540 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2541 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2542 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2543 cfg |= RL_CPLUSCMD_VLANSTRIP; 2544 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2545 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2546 /* XXX magic. */ 2547 cfg |= 0x0001; 2548 } else 2549 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2550 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2551 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2552 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2553 reg = 0x000fff00; 2554 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2555 reg |= 0x000000ff; 2556 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2557 reg |= 0x00f00000; 2558 CSR_WRITE_4(sc, 0x7c, reg); 2559 /* Disable interrupt mitigation. */ 2560 CSR_WRITE_2(sc, 0xe2, 0); 2561 } 2562 /* 2563 * Disable TSO if interface MTU size is greater than MSS 2564 * allowed in controller. 2565 */ 2566 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2567 ifp->if_capenable &= ~IFCAP_TSO4; 2568 ifp->if_hwassist &= ~CSUM_TSO; 2569 } 2570 2571 /* 2572 * Init our MAC address. Even though the chipset 2573 * documentation doesn't mention it, we need to enter "Config 2574 * register write enable" mode to modify the ID registers. 2575 */ 2576 /* Copy MAC address on stack to align. */ 2577 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2578 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2579 CSR_WRITE_4(sc, RL_IDR0, 2580 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2581 CSR_WRITE_4(sc, RL_IDR4, 2582 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2583 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2584 2585 /* 2586 * For C+ mode, initialize the RX descriptors and mbufs. 2587 */ 2588 re_rx_list_init(sc); 2589 re_tx_list_init(sc); 2590 2591 /* 2592 * Load the addresses of the RX and TX lists into the chip. 2593 */ 2594 2595 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2596 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2597 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2598 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2599 2600 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2601 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2602 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2603 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2604 2605 /* 2606 * Enable transmit and receive. 2607 */ 2608 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2609 2610 /* 2611 * Set the initial TX configuration. 2612 */ 2613 if (sc->rl_testmode) { 2614 if (sc->rl_type == RL_8169) 2615 CSR_WRITE_4(sc, RL_TXCFG, 2616 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2617 else 2618 CSR_WRITE_4(sc, RL_TXCFG, 2619 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2620 } else 2621 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2622 2623 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2624 2625 /* 2626 * Set the initial RX configuration. 2627 */ 2628 re_set_rxmode(sc); 2629 2630#ifdef DEVICE_POLLING 2631 /* 2632 * Disable interrupts if we are polling. 2633 */ 2634 if (ifp->if_capenable & IFCAP_POLLING) 2635 CSR_WRITE_2(sc, RL_IMR, 0); 2636 else /* otherwise ... */ 2637#endif 2638 2639 /* 2640 * Enable interrupts. 2641 */ 2642 if (sc->rl_testmode) 2643 CSR_WRITE_2(sc, RL_IMR, 0); 2644 else 2645 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2646 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2647 2648 /* Set initial TX threshold */ 2649 sc->rl_txthresh = RL_TX_THRESH_INIT; 2650 2651 /* Start RX/TX process. */ 2652 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2653#ifdef notdef 2654 /* Enable receiver and transmitter. */ 2655 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2656#endif 2657 2658#ifdef RE_TX_MODERATION 2659 /* 2660 * Initialize the timer interrupt register so that 2661 * a timer interrupt will be generated once the timer 2662 * reaches a certain number of ticks. The timer is 2663 * reloaded on each transmit. This gives us TX interrupt 2664 * moderation, which dramatically improves TX frame rate. 2665 */ 2666 if (sc->rl_type == RL_8169) 2667 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2668 else 2669 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2670#endif 2671 2672 /* 2673 * For 8169 gigE NICs, set the max allowed RX packet 2674 * size so we can receive jumbo frames. 2675 */ 2676 if (sc->rl_type == RL_8169) 2677 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2678 2679 if (sc->rl_testmode) 2680 return; 2681 2682 mii_mediachg(mii); 2683 2684 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2685 2686 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2687 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2688 2689 sc->rl_flags &= ~RL_FLAG_LINK; 2690 sc->rl_watchdog_timer = 0; 2691 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2692} 2693 2694/* 2695 * Set media options. 2696 */ 2697static int 2698re_ifmedia_upd(struct ifnet *ifp) 2699{ 2700 struct rl_softc *sc; 2701 struct mii_data *mii; 2702 int error; 2703 2704 sc = ifp->if_softc; 2705 mii = device_get_softc(sc->rl_miibus); 2706 RL_LOCK(sc); 2707 error = mii_mediachg(mii); 2708 RL_UNLOCK(sc); 2709 2710 return (error); 2711} 2712 2713/* 2714 * Report current media status. 2715 */ 2716static void 2717re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2718{ 2719 struct rl_softc *sc; 2720 struct mii_data *mii; 2721 2722 sc = ifp->if_softc; 2723 mii = device_get_softc(sc->rl_miibus); 2724 2725 RL_LOCK(sc); 2726 mii_pollstat(mii); 2727 RL_UNLOCK(sc); 2728 ifmr->ifm_active = mii->mii_media_active; 2729 ifmr->ifm_status = mii->mii_media_status; 2730} 2731 2732static int 2733re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2734{ 2735 struct rl_softc *sc = ifp->if_softc; 2736 struct ifreq *ifr = (struct ifreq *) data; 2737 struct mii_data *mii; 2738 int error = 0; 2739 2740 switch (command) { 2741 case SIOCSIFMTU: 2742 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2743 error = EINVAL; 2744 break; 2745 } 2746 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2747 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2748 error = EINVAL; 2749 break; 2750 } 2751 RL_LOCK(sc); 2752 if (ifp->if_mtu != ifr->ifr_mtu) 2753 ifp->if_mtu = ifr->ifr_mtu; 2754 if (ifp->if_mtu > RL_TSO_MTU && 2755 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2756 ifp->if_capenable &= ~IFCAP_TSO4; 2757 ifp->if_hwassist &= ~CSUM_TSO; 2758 } 2759 RL_UNLOCK(sc); 2760 break; 2761 case SIOCSIFFLAGS: 2762 RL_LOCK(sc); 2763 if ((ifp->if_flags & IFF_UP) != 0) { 2764 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2765 if (((ifp->if_flags ^ sc->rl_if_flags) 2766 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2767 re_set_rxmode(sc); 2768 } else 2769 re_init_locked(sc); 2770 } else { 2771 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2772 re_stop(sc); 2773 } 2774 sc->rl_if_flags = ifp->if_flags; 2775 RL_UNLOCK(sc); 2776 break; 2777 case SIOCADDMULTI: 2778 case SIOCDELMULTI: 2779 RL_LOCK(sc); 2780 re_set_rxmode(sc); 2781 RL_UNLOCK(sc); 2782 break; 2783 case SIOCGIFMEDIA: 2784 case SIOCSIFMEDIA: 2785 mii = device_get_softc(sc->rl_miibus); 2786 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2787 break; 2788 case SIOCSIFCAP: 2789 { 2790 int mask, reinit; 2791 2792 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2793 reinit = 0; 2794#ifdef DEVICE_POLLING 2795 if (mask & IFCAP_POLLING) { 2796 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2797 error = ether_poll_register(re_poll, ifp); 2798 if (error) 2799 return(error); 2800 RL_LOCK(sc); 2801 /* Disable interrupts */ 2802 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2803 ifp->if_capenable |= IFCAP_POLLING; 2804 RL_UNLOCK(sc); 2805 } else { 2806 error = ether_poll_deregister(ifp); 2807 /* Enable interrupts. */ 2808 RL_LOCK(sc); 2809 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2810 ifp->if_capenable &= ~IFCAP_POLLING; 2811 RL_UNLOCK(sc); 2812 } 2813 } 2814#endif /* DEVICE_POLLING */ 2815 if (mask & IFCAP_HWCSUM) { 2816 ifp->if_capenable ^= IFCAP_HWCSUM; 2817 if (ifp->if_capenable & IFCAP_TXCSUM) 2818 ifp->if_hwassist |= RE_CSUM_FEATURES; 2819 else 2820 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2821 reinit = 1; 2822 } 2823 if (mask & IFCAP_VLAN_HWTAGGING) { 2824 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2825 reinit = 1; 2826 } 2827 if (mask & IFCAP_TSO4) { 2828 ifp->if_capenable ^= IFCAP_TSO4; 2829 if ((IFCAP_TSO4 & ifp->if_capenable) && 2830 (IFCAP_TSO4 & ifp->if_capabilities)) 2831 ifp->if_hwassist |= CSUM_TSO; 2832 else 2833 ifp->if_hwassist &= ~CSUM_TSO; 2834 if (ifp->if_mtu > RL_TSO_MTU && 2835 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2836 ifp->if_capenable &= ~IFCAP_TSO4; 2837 ifp->if_hwassist &= ~CSUM_TSO; 2838 } 2839 } 2840 if ((mask & IFCAP_WOL) != 0 && 2841 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2842 if ((mask & IFCAP_WOL_UCAST) != 0) 2843 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2844 if ((mask & IFCAP_WOL_MCAST) != 0) 2845 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2846 if ((mask & IFCAP_WOL_MAGIC) != 0) 2847 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2848 } 2849 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2850 re_init(sc); 2851 VLAN_CAPABILITIES(ifp); 2852 } 2853 break; 2854 default: 2855 error = ether_ioctl(ifp, command, data); 2856 break; 2857 } 2858 2859 return (error); 2860} 2861 2862static void 2863re_watchdog(struct rl_softc *sc) 2864{ 2865 struct ifnet *ifp; 2866 2867 RL_LOCK_ASSERT(sc); 2868 2869 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2870 return; 2871 2872 ifp = sc->rl_ifp; 2873 re_txeof(sc); 2874 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2875 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2876 "-- recovering\n"); 2877 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2878 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2879 return; 2880 } 2881 2882 if_printf(ifp, "watchdog timeout\n"); 2883 ifp->if_oerrors++; 2884 2885 re_rxeof(sc); 2886 re_init_locked(sc); 2887 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2888 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2889} 2890 2891/* 2892 * Stop the adapter and free any mbufs allocated to the 2893 * RX and TX lists. 2894 */ 2895static void 2896re_stop(struct rl_softc *sc) 2897{ 2898 int i; 2899 struct ifnet *ifp; 2900 struct rl_txdesc *txd; 2901 struct rl_rxdesc *rxd; 2902 2903 RL_LOCK_ASSERT(sc); 2904 2905 ifp = sc->rl_ifp; 2906 2907 sc->rl_watchdog_timer = 0; 2908 callout_stop(&sc->rl_stat_callout); 2909 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2910 2911 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 2912 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 2913 RL_CMD_RX_ENB); 2914 else 2915 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2916 DELAY(1000); 2917 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2918 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2919 2920 if (sc->rl_head != NULL) { 2921 m_freem(sc->rl_head); 2922 sc->rl_head = sc->rl_tail = NULL; 2923 } 2924 2925 /* Free the TX list buffers. */ 2926 2927 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2928 txd = &sc->rl_ldata.rl_tx_desc[i]; 2929 if (txd->tx_m != NULL) { 2930 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2931 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2932 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2933 txd->tx_dmamap); 2934 m_freem(txd->tx_m); 2935 txd->tx_m = NULL; 2936 } 2937 } 2938 2939 /* Free the RX list buffers. */ 2940 2941 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2942 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2943 if (rxd->rx_m != NULL) { 2944 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2945 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2946 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2947 rxd->rx_dmamap); 2948 m_freem(rxd->rx_m); 2949 rxd->rx_m = NULL; 2950 } 2951 } 2952} 2953 2954/* 2955 * Device suspend routine. Stop the interface and save some PCI 2956 * settings in case the BIOS doesn't restore them properly on 2957 * resume. 2958 */ 2959static int 2960re_suspend(device_t dev) 2961{ 2962 struct rl_softc *sc; 2963 2964 sc = device_get_softc(dev); 2965 2966 RL_LOCK(sc); 2967 re_stop(sc); 2968 re_setwol(sc); 2969 sc->suspended = 1; 2970 RL_UNLOCK(sc); 2971 2972 return (0); 2973} 2974 2975/* 2976 * Device resume routine. Restore some PCI settings in case the BIOS 2977 * doesn't, re-enable busmastering, and restart the interface if 2978 * appropriate. 2979 */ 2980static int 2981re_resume(device_t dev) 2982{ 2983 struct rl_softc *sc; 2984 struct ifnet *ifp; 2985 2986 sc = device_get_softc(dev); 2987 2988 RL_LOCK(sc); 2989 2990 ifp = sc->rl_ifp; 2991 /* Take controller out of sleep mode. */ 2992 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 2993 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 2994 CSR_WRITE_1(sc, RL_GPIO, 2995 CSR_READ_1(sc, RL_GPIO) | 0x01); 2996 } 2997 2998 /* reinitialize interface if necessary */ 2999 if (ifp->if_flags & IFF_UP) 3000 re_init_locked(sc); 3001 3002 /* 3003 * Clear WOL matching such that normal Rx filtering 3004 * wouldn't interfere with WOL patterns. 3005 */ 3006 re_clrwol(sc); 3007 sc->suspended = 0; 3008 RL_UNLOCK(sc); 3009 3010 return (0); 3011} 3012 3013/* 3014 * Stop all chip I/O so that the kernel's probe routines don't 3015 * get confused by errant DMAs when rebooting. 3016 */ 3017static int 3018re_shutdown(device_t dev) 3019{ 3020 struct rl_softc *sc; 3021 3022 sc = device_get_softc(dev); 3023 3024 RL_LOCK(sc); 3025 re_stop(sc); 3026 /* 3027 * Mark interface as down since otherwise we will panic if 3028 * interrupt comes in later on, which can happen in some 3029 * cases. 3030 */ 3031 sc->rl_ifp->if_flags &= ~IFF_UP; 3032 re_setwol(sc); 3033 RL_UNLOCK(sc); 3034 3035 return (0); 3036} 3037 3038static void 3039re_setwol(struct rl_softc *sc) 3040{ 3041 struct ifnet *ifp; 3042 int pmc; 3043 uint16_t pmstat; 3044 uint8_t v; 3045 3046 RL_LOCK_ASSERT(sc); 3047 3048 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3049 return; 3050 3051 ifp = sc->rl_ifp; 3052 /* Put controller into sleep mode. */ 3053 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3054 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3055 CSR_WRITE_1(sc, RL_GPIO, 3056 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3057 } 3058 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3059 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3060 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3061 /* Enable config register write. */ 3062 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3063 3064 /* Enable PME. */ 3065 v = CSR_READ_1(sc, RL_CFG1); 3066 v &= ~RL_CFG1_PME; 3067 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3068 v |= RL_CFG1_PME; 3069 CSR_WRITE_1(sc, RL_CFG1, v); 3070 3071 v = CSR_READ_1(sc, RL_CFG3); 3072 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3073 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3074 v |= RL_CFG3_WOL_MAGIC; 3075 CSR_WRITE_1(sc, RL_CFG3, v); 3076 3077 /* Config register write done. */ 3078 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3079 3080 v = CSR_READ_1(sc, RL_CFG5); 3081 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3082 v &= ~RL_CFG5_WOL_LANWAKE; 3083 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3084 v |= RL_CFG5_WOL_UCAST; 3085 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3086 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3087 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3088 v |= RL_CFG5_WOL_LANWAKE; 3089 CSR_WRITE_1(sc, RL_CFG5, v); 3090 3091 /* 3092 * It seems that hardware resets its link speed to 100Mbps in 3093 * power down mode so switching to 100Mbps in driver is not 3094 * needed. 3095 */ 3096 3097 /* Request PME if WOL is requested. */ 3098 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3099 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3100 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3101 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3102 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3103} 3104 3105static void 3106re_clrwol(struct rl_softc *sc) 3107{ 3108 int pmc; 3109 uint8_t v; 3110 3111 RL_LOCK_ASSERT(sc); 3112 3113 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3114 return; 3115 3116 /* Enable config register write. */ 3117 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3118 3119 v = CSR_READ_1(sc, RL_CFG3); 3120 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3121 CSR_WRITE_1(sc, RL_CFG3, v); 3122 3123 /* Config register write done. */ 3124 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3125 3126 v = CSR_READ_1(sc, RL_CFG5); 3127 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3128 v &= ~RL_CFG5_WOL_LANWAKE; 3129 CSR_WRITE_1(sc, RL_CFG5, v); 3130} 3131