if_re.c revision 185897
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 185897 2008-12-11 00:46:07Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* Tunables. */ 159static int msi_disable = 1; 160TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164/* 165 * Various supported device vendors/types and their names. 166 */ 167static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8168C/8168CP/8168D/8111B/8111C/8111CP PCIe " 176 "Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8169, 0, 178 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 182 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 183 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 184 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 185 { USR_VENDORID, USR_DEVICEID_997902, 0, 186 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 187}; 188 189static struct rl_hwrev re_hwrevs[] = { 190 { RL_HWREV_8139, RL_8139, "" }, 191 { RL_HWREV_8139A, RL_8139, "A" }, 192 { RL_HWREV_8139AG, RL_8139, "A-G" }, 193 { RL_HWREV_8139B, RL_8139, "B" }, 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 204 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL"}, 205 { RL_HWREV_8100, RL_8139, "8100"}, 206 { RL_HWREV_8101, RL_8139, "8101"}, 207 { RL_HWREV_8100E, RL_8169, "8100E"}, 208 { RL_HWREV_8101E, RL_8169, "8101E"}, 209 { RL_HWREV_8102E, RL_8169, "8102E"}, 210 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 211 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 212 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 213 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 214 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 215 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 216 { RL_HWREV_8168D, RL_8169, "8168D"}, 217 { 0, 0, NULL } 218}; 219 220static int re_probe (device_t); 221static int re_attach (device_t); 222static int re_detach (device_t); 223 224static int re_encap (struct rl_softc *, struct mbuf **); 225 226static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 227static int re_allocmem (device_t, struct rl_softc *); 228static __inline void re_discard_rxbuf 229 (struct rl_softc *, int); 230static int re_newbuf (struct rl_softc *, int); 231static int re_rx_list_init (struct rl_softc *); 232static int re_tx_list_init (struct rl_softc *); 233#ifdef RE_FIXUP_RX 234static __inline void re_fixup_rx 235 (struct mbuf *); 236#endif 237static int re_rxeof (struct rl_softc *); 238static void re_txeof (struct rl_softc *); 239#ifdef DEVICE_POLLING 240static void re_poll (struct ifnet *, enum poll_cmd, int); 241static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 242#endif 243static int re_intr (void *); 244static void re_tick (void *); 245static void re_tx_task (void *, int); 246static void re_int_task (void *, int); 247static void re_start (struct ifnet *); 248static int re_ioctl (struct ifnet *, u_long, caddr_t); 249static void re_init (void *); 250static void re_init_locked (struct rl_softc *); 251static void re_stop (struct rl_softc *); 252static void re_watchdog (struct rl_softc *); 253static int re_suspend (device_t); 254static int re_resume (device_t); 255static int re_shutdown (device_t); 256static int re_ifmedia_upd (struct ifnet *); 257static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 258 259static void re_eeprom_putbyte (struct rl_softc *, int); 260static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 261static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 262static int re_gmii_readreg (device_t, int, int); 263static int re_gmii_writereg (device_t, int, int, int); 264 265static int re_miibus_readreg (device_t, int, int); 266static int re_miibus_writereg (device_t, int, int, int); 267static void re_miibus_statchg (device_t); 268 269static void re_setmulti (struct rl_softc *); 270static void re_reset (struct rl_softc *); 271static void re_setwol (struct rl_softc *); 272static void re_clrwol (struct rl_softc *); 273 274#ifdef RE_DIAG 275static int re_diag (struct rl_softc *); 276#endif 277 278static device_method_t re_methods[] = { 279 /* Device interface */ 280 DEVMETHOD(device_probe, re_probe), 281 DEVMETHOD(device_attach, re_attach), 282 DEVMETHOD(device_detach, re_detach), 283 DEVMETHOD(device_suspend, re_suspend), 284 DEVMETHOD(device_resume, re_resume), 285 DEVMETHOD(device_shutdown, re_shutdown), 286 287 /* bus interface */ 288 DEVMETHOD(bus_print_child, bus_generic_print_child), 289 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 290 291 /* MII interface */ 292 DEVMETHOD(miibus_readreg, re_miibus_readreg), 293 DEVMETHOD(miibus_writereg, re_miibus_writereg), 294 DEVMETHOD(miibus_statchg, re_miibus_statchg), 295 296 { 0, 0 } 297}; 298 299static driver_t re_driver = { 300 "re", 301 re_methods, 302 sizeof(struct rl_softc) 303}; 304 305static devclass_t re_devclass; 306 307DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 308DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 309DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 310 311#define EE_SET(x) \ 312 CSR_WRITE_1(sc, RL_EECMD, \ 313 CSR_READ_1(sc, RL_EECMD) | x) 314 315#define EE_CLR(x) \ 316 CSR_WRITE_1(sc, RL_EECMD, \ 317 CSR_READ_1(sc, RL_EECMD) & ~x) 318 319/* 320 * Send a read command and address to the EEPROM, check for ACK. 321 */ 322static void 323re_eeprom_putbyte(struct rl_softc *sc, int addr) 324{ 325 int d, i; 326 327 d = addr | (RL_9346_READ << sc->rl_eewidth); 328 329 /* 330 * Feed in each bit and strobe the clock. 331 */ 332 333 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 334 if (d & i) { 335 EE_SET(RL_EE_DATAIN); 336 } else { 337 EE_CLR(RL_EE_DATAIN); 338 } 339 DELAY(100); 340 EE_SET(RL_EE_CLK); 341 DELAY(150); 342 EE_CLR(RL_EE_CLK); 343 DELAY(100); 344 } 345} 346 347/* 348 * Read a word of data stored in the EEPROM at address 'addr.' 349 */ 350static void 351re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 352{ 353 int i; 354 u_int16_t word = 0; 355 356 /* 357 * Send address of word we want to read. 358 */ 359 re_eeprom_putbyte(sc, addr); 360 361 /* 362 * Start reading bits from EEPROM. 363 */ 364 for (i = 0x8000; i; i >>= 1) { 365 EE_SET(RL_EE_CLK); 366 DELAY(100); 367 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 368 word |= i; 369 EE_CLR(RL_EE_CLK); 370 DELAY(100); 371 } 372 373 *dest = word; 374} 375 376/* 377 * Read a sequence of words from the EEPROM. 378 */ 379static void 380re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 381{ 382 int i; 383 u_int16_t word = 0, *ptr; 384 385 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 386 387 DELAY(100); 388 389 for (i = 0; i < cnt; i++) { 390 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 391 re_eeprom_getword(sc, off + i, &word); 392 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 393 ptr = (u_int16_t *)(dest + (i * 2)); 394 *ptr = word; 395 } 396 397 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 398} 399 400static int 401re_gmii_readreg(device_t dev, int phy, int reg) 402{ 403 struct rl_softc *sc; 404 u_int32_t rval; 405 int i; 406 407 if (phy != 1) 408 return (0); 409 410 sc = device_get_softc(dev); 411 412 /* Let the rgephy driver read the GMEDIASTAT register */ 413 414 if (reg == RL_GMEDIASTAT) { 415 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 416 return (rval); 417 } 418 419 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 420 421 for (i = 0; i < RL_TIMEOUT; i++) { 422 rval = CSR_READ_4(sc, RL_PHYAR); 423 if (rval & RL_PHYAR_BUSY) 424 break; 425 DELAY(100); 426 } 427 428 if (i == RL_TIMEOUT) { 429 device_printf(sc->rl_dev, "PHY read failed\n"); 430 return (0); 431 } 432 433 return (rval & RL_PHYAR_PHYDATA); 434} 435 436static int 437re_gmii_writereg(device_t dev, int phy, int reg, int data) 438{ 439 struct rl_softc *sc; 440 u_int32_t rval; 441 int i; 442 443 sc = device_get_softc(dev); 444 445 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 446 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 447 448 for (i = 0; i < RL_TIMEOUT; i++) { 449 rval = CSR_READ_4(sc, RL_PHYAR); 450 if (!(rval & RL_PHYAR_BUSY)) 451 break; 452 DELAY(100); 453 } 454 455 if (i == RL_TIMEOUT) { 456 device_printf(sc->rl_dev, "PHY write failed\n"); 457 return (0); 458 } 459 460 return (0); 461} 462 463static int 464re_miibus_readreg(device_t dev, int phy, int reg) 465{ 466 struct rl_softc *sc; 467 u_int16_t rval = 0; 468 u_int16_t re8139_reg = 0; 469 470 sc = device_get_softc(dev); 471 472 if (sc->rl_type == RL_8169) { 473 rval = re_gmii_readreg(dev, phy, reg); 474 return (rval); 475 } 476 477 /* Pretend the internal PHY is only at address 0 */ 478 if (phy) { 479 return (0); 480 } 481 switch (reg) { 482 case MII_BMCR: 483 re8139_reg = RL_BMCR; 484 break; 485 case MII_BMSR: 486 re8139_reg = RL_BMSR; 487 break; 488 case MII_ANAR: 489 re8139_reg = RL_ANAR; 490 break; 491 case MII_ANER: 492 re8139_reg = RL_ANER; 493 break; 494 case MII_ANLPAR: 495 re8139_reg = RL_LPAR; 496 break; 497 case MII_PHYIDR1: 498 case MII_PHYIDR2: 499 return (0); 500 /* 501 * Allow the rlphy driver to read the media status 502 * register. If we have a link partner which does not 503 * support NWAY, this is the register which will tell 504 * us the results of parallel detection. 505 */ 506 case RL_MEDIASTAT: 507 rval = CSR_READ_1(sc, RL_MEDIASTAT); 508 return (rval); 509 default: 510 device_printf(sc->rl_dev, "bad phy register\n"); 511 return (0); 512 } 513 rval = CSR_READ_2(sc, re8139_reg); 514 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 515 /* 8139C+ has different bit layout. */ 516 rval &= ~(BMCR_LOOP | BMCR_ISO); 517 } 518 return (rval); 519} 520 521static int 522re_miibus_writereg(device_t dev, int phy, int reg, int data) 523{ 524 struct rl_softc *sc; 525 u_int16_t re8139_reg = 0; 526 int rval = 0; 527 528 sc = device_get_softc(dev); 529 530 if (sc->rl_type == RL_8169) { 531 rval = re_gmii_writereg(dev, phy, reg, data); 532 return (rval); 533 } 534 535 /* Pretend the internal PHY is only at address 0 */ 536 if (phy) 537 return (0); 538 539 switch (reg) { 540 case MII_BMCR: 541 re8139_reg = RL_BMCR; 542 if (sc->rl_type == RL_8139CPLUS) { 543 /* 8139C+ has different bit layout. */ 544 data &= ~(BMCR_LOOP | BMCR_ISO); 545 } 546 break; 547 case MII_BMSR: 548 re8139_reg = RL_BMSR; 549 break; 550 case MII_ANAR: 551 re8139_reg = RL_ANAR; 552 break; 553 case MII_ANER: 554 re8139_reg = RL_ANER; 555 break; 556 case MII_ANLPAR: 557 re8139_reg = RL_LPAR; 558 break; 559 case MII_PHYIDR1: 560 case MII_PHYIDR2: 561 return (0); 562 break; 563 default: 564 device_printf(sc->rl_dev, "bad phy register\n"); 565 return (0); 566 } 567 CSR_WRITE_2(sc, re8139_reg, data); 568 return (0); 569} 570 571static void 572re_miibus_statchg(device_t dev) 573{ 574 struct rl_softc *sc; 575 struct ifnet *ifp; 576 struct mii_data *mii; 577 578 sc = device_get_softc(dev); 579 mii = device_get_softc(sc->rl_miibus); 580 ifp = sc->rl_ifp; 581 if (mii == NULL || ifp == NULL || 582 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 583 return; 584 585 sc->rl_flags &= ~RL_FLAG_LINK; 586 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 587 (IFM_ACTIVE | IFM_AVALID)) { 588 switch (IFM_SUBTYPE(mii->mii_media_active)) { 589 case IFM_10_T: 590 case IFM_100_TX: 591 sc->rl_flags |= RL_FLAG_LINK; 592 break; 593 case IFM_1000_T: 594 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 595 break; 596 sc->rl_flags |= RL_FLAG_LINK; 597 break; 598 default: 599 break; 600 } 601 } 602 /* 603 * RealTek controllers does not provide any interface to 604 * Tx/Rx MACs for resolved speed, duplex and flow-control 605 * parameters. 606 */ 607} 608 609/* 610 * Program the 64-bit multicast hash filter. 611 */ 612static void 613re_setmulti(struct rl_softc *sc) 614{ 615 struct ifnet *ifp; 616 int h = 0; 617 u_int32_t hashes[2] = { 0, 0 }; 618 struct ifmultiaddr *ifma; 619 u_int32_t rxfilt; 620 int mcnt = 0; 621 622 RL_LOCK_ASSERT(sc); 623 624 ifp = sc->rl_ifp; 625 626 627 rxfilt = CSR_READ_4(sc, RL_RXCFG); 628 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 629 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 630 if (ifp->if_flags & IFF_PROMISC) 631 rxfilt |= RL_RXCFG_RX_ALLPHYS; 632 /* 633 * Unlike other hardwares, we have to explicitly set 634 * RL_RXCFG_RX_MULTI to receive multicast frames in 635 * promiscuous mode. 636 */ 637 rxfilt |= RL_RXCFG_RX_MULTI; 638 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 639 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 640 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 641 return; 642 } 643 644 /* first, zot all the existing hash bits */ 645 CSR_WRITE_4(sc, RL_MAR0, 0); 646 CSR_WRITE_4(sc, RL_MAR4, 0); 647 648 /* now program new ones */ 649 IF_ADDR_LOCK(ifp); 650 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 651 if (ifma->ifma_addr->sa_family != AF_LINK) 652 continue; 653 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 654 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 655 if (h < 32) 656 hashes[0] |= (1 << h); 657 else 658 hashes[1] |= (1 << (h - 32)); 659 mcnt++; 660 } 661 IF_ADDR_UNLOCK(ifp); 662 663 if (mcnt) 664 rxfilt |= RL_RXCFG_RX_MULTI; 665 else 666 rxfilt &= ~RL_RXCFG_RX_MULTI; 667 668 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 669 670 /* 671 * For some unfathomable reason, RealTek decided to reverse 672 * the order of the multicast hash registers in the PCI Express 673 * parts. This means we have to write the hash pattern in reverse 674 * order for those devices. 675 */ 676 677 if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) { 678 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 679 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 680 } else { 681 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 682 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 683 } 684} 685 686static void 687re_reset(struct rl_softc *sc) 688{ 689 int i; 690 691 RL_LOCK_ASSERT(sc); 692 693 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 694 695 for (i = 0; i < RL_TIMEOUT; i++) { 696 DELAY(10); 697 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 698 break; 699 } 700 if (i == RL_TIMEOUT) 701 device_printf(sc->rl_dev, "reset never completed!\n"); 702 703 CSR_WRITE_1(sc, 0x82, 1); 704} 705 706#ifdef RE_DIAG 707 708/* 709 * The following routine is designed to test for a defect on some 710 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 711 * lines connected to the bus, however for a 32-bit only card, they 712 * should be pulled high. The result of this defect is that the 713 * NIC will not work right if you plug it into a 64-bit slot: DMA 714 * operations will be done with 64-bit transfers, which will fail 715 * because the 64-bit data lines aren't connected. 716 * 717 * There's no way to work around this (short of talking a soldering 718 * iron to the board), however we can detect it. The method we use 719 * here is to put the NIC into digital loopback mode, set the receiver 720 * to promiscuous mode, and then try to send a frame. We then compare 721 * the frame data we sent to what was received. If the data matches, 722 * then the NIC is working correctly, otherwise we know the user has 723 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 724 * slot. In the latter case, there's no way the NIC can work correctly, 725 * so we print out a message on the console and abort the device attach. 726 */ 727 728static int 729re_diag(struct rl_softc *sc) 730{ 731 struct ifnet *ifp = sc->rl_ifp; 732 struct mbuf *m0; 733 struct ether_header *eh; 734 struct rl_desc *cur_rx; 735 u_int16_t status; 736 u_int32_t rxstat; 737 int total_len, i, error = 0, phyaddr; 738 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 739 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 740 741 /* Allocate a single mbuf */ 742 MGETHDR(m0, M_DONTWAIT, MT_DATA); 743 if (m0 == NULL) 744 return (ENOBUFS); 745 746 RL_LOCK(sc); 747 748 /* 749 * Initialize the NIC in test mode. This sets the chip up 750 * so that it can send and receive frames, but performs the 751 * following special functions: 752 * - Puts receiver in promiscuous mode 753 * - Enables digital loopback mode 754 * - Leaves interrupts turned off 755 */ 756 757 ifp->if_flags |= IFF_PROMISC; 758 sc->rl_testmode = 1; 759 re_init_locked(sc); 760 sc->rl_flags |= RL_FLAG_LINK; 761 if (sc->rl_type == RL_8169) 762 phyaddr = 1; 763 else 764 phyaddr = 0; 765 766 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 767 for (i = 0; i < RL_TIMEOUT; i++) { 768 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 769 if (!(status & BMCR_RESET)) 770 break; 771 } 772 773 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 774 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 775 776 DELAY(100000); 777 778 /* Put some data in the mbuf */ 779 780 eh = mtod(m0, struct ether_header *); 781 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 782 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 783 eh->ether_type = htons(ETHERTYPE_IP); 784 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 785 786 /* 787 * Queue the packet, start transmission. 788 * Note: IF_HANDOFF() ultimately calls re_start() for us. 789 */ 790 791 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 792 RL_UNLOCK(sc); 793 /* XXX: re_diag must not be called when in ALTQ mode */ 794 IF_HANDOFF(&ifp->if_snd, m0, ifp); 795 RL_LOCK(sc); 796 m0 = NULL; 797 798 /* Wait for it to propagate through the chip */ 799 800 DELAY(100000); 801 for (i = 0; i < RL_TIMEOUT; i++) { 802 status = CSR_READ_2(sc, RL_ISR); 803 CSR_WRITE_2(sc, RL_ISR, status); 804 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 805 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 806 break; 807 DELAY(10); 808 } 809 810 if (i == RL_TIMEOUT) { 811 device_printf(sc->rl_dev, 812 "diagnostic failed, failed to receive packet in" 813 " loopback mode\n"); 814 error = EIO; 815 goto done; 816 } 817 818 /* 819 * The packet should have been dumped into the first 820 * entry in the RX DMA ring. Grab it from there. 821 */ 822 823 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 824 sc->rl_ldata.rl_rx_list_map, 825 BUS_DMASYNC_POSTREAD); 826 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 827 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 828 BUS_DMASYNC_POSTREAD); 829 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 830 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 831 832 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 833 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 834 eh = mtod(m0, struct ether_header *); 835 836 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 837 total_len = RL_RXBYTES(cur_rx); 838 rxstat = le32toh(cur_rx->rl_cmdstat); 839 840 if (total_len != ETHER_MIN_LEN) { 841 device_printf(sc->rl_dev, 842 "diagnostic failed, received short packet\n"); 843 error = EIO; 844 goto done; 845 } 846 847 /* Test that the received packet data matches what we sent. */ 848 849 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 850 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 851 ntohs(eh->ether_type) != ETHERTYPE_IP) { 852 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 853 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 854 dst, ":", src, ":", ETHERTYPE_IP); 855 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 856 eh->ether_dhost, ":", eh->ether_shost, ":", 857 ntohs(eh->ether_type)); 858 device_printf(sc->rl_dev, "You may have a defective 32-bit " 859 "NIC plugged into a 64-bit PCI slot.\n"); 860 device_printf(sc->rl_dev, "Please re-install the NIC in a " 861 "32-bit slot for proper operation.\n"); 862 device_printf(sc->rl_dev, "Read the re(4) man page for more " 863 "details.\n"); 864 error = EIO; 865 } 866 867done: 868 /* Turn interface off, release resources */ 869 870 sc->rl_testmode = 0; 871 sc->rl_flags &= ~RL_FLAG_LINK; 872 ifp->if_flags &= ~IFF_PROMISC; 873 re_stop(sc); 874 if (m0 != NULL) 875 m_freem(m0); 876 877 RL_UNLOCK(sc); 878 879 return (error); 880} 881 882#endif 883 884/* 885 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 886 * IDs against our list and return a device name if we find a match. 887 */ 888static int 889re_probe(device_t dev) 890{ 891 struct rl_type *t; 892 uint16_t devid, vendor; 893 uint16_t revid, sdevid; 894 int i; 895 896 vendor = pci_get_vendor(dev); 897 devid = pci_get_device(dev); 898 revid = pci_get_revid(dev); 899 sdevid = pci_get_subdevice(dev); 900 901 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 902 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 903 /* 904 * Only attach to rev. 3 of the Linksys EG1032 adapter. 905 * Rev. 2 is supported by sk(4). 906 */ 907 return (ENXIO); 908 } 909 } 910 911 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 912 if (revid != 0x20) { 913 /* 8139, let rl(4) take care of this device. */ 914 return (ENXIO); 915 } 916 } 917 918 t = re_devs; 919 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 920 if (vendor == t->rl_vid && devid == t->rl_did) { 921 device_set_desc(dev, t->rl_name); 922 return (BUS_PROBE_DEFAULT); 923 } 924 } 925 926 return (ENXIO); 927} 928 929/* 930 * Map a single buffer address. 931 */ 932 933static void 934re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 935{ 936 bus_addr_t *addr; 937 938 if (error) 939 return; 940 941 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 942 addr = arg; 943 *addr = segs->ds_addr; 944} 945 946static int 947re_allocmem(device_t dev, struct rl_softc *sc) 948{ 949 bus_size_t rx_list_size, tx_list_size; 950 int error; 951 int i; 952 953 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 954 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 955 956 /* 957 * Allocate the parent bus DMA tag appropriate for PCI. 958 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 959 * register should be set. However some RealTek chips are known 960 * to be buggy on DAC handling, therefore disable DAC by limiting 961 * DMA address space to 32bit. PCIe variants of RealTek chips 962 * may not have the limitation but I took safer path. 963 */ 964 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 965 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 966 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 967 NULL, NULL, &sc->rl_parent_tag); 968 if (error) { 969 device_printf(dev, "could not allocate parent DMA tag\n"); 970 return (error); 971 } 972 973 /* 974 * Allocate map for TX mbufs. 975 */ 976 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 977 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 978 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 979 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 980 if (error) { 981 device_printf(dev, "could not allocate TX DMA tag\n"); 982 return (error); 983 } 984 985 /* 986 * Allocate map for RX mbufs. 987 */ 988 989 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 990 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 991 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 992 if (error) { 993 device_printf(dev, "could not allocate RX DMA tag\n"); 994 return (error); 995 } 996 997 /* 998 * Allocate map for TX descriptor list. 999 */ 1000 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1001 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1002 NULL, tx_list_size, 1, tx_list_size, 0, 1003 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1004 if (error) { 1005 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1006 return (error); 1007 } 1008 1009 /* Allocate DMA'able memory for the TX ring */ 1010 1011 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1012 (void **)&sc->rl_ldata.rl_tx_list, 1013 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1014 &sc->rl_ldata.rl_tx_list_map); 1015 if (error) { 1016 device_printf(dev, "could not allocate TX DMA ring\n"); 1017 return (error); 1018 } 1019 1020 /* Load the map for the TX ring. */ 1021 1022 sc->rl_ldata.rl_tx_list_addr = 0; 1023 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1024 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1025 tx_list_size, re_dma_map_addr, 1026 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1027 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1028 device_printf(dev, "could not load TX DMA ring\n"); 1029 return (ENOMEM); 1030 } 1031 1032 /* Create DMA maps for TX buffers */ 1033 1034 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1035 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1036 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1037 if (error) { 1038 device_printf(dev, "could not create DMA map for TX\n"); 1039 return (error); 1040 } 1041 } 1042 1043 /* 1044 * Allocate map for RX descriptor list. 1045 */ 1046 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1047 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1048 NULL, rx_list_size, 1, rx_list_size, 0, 1049 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1050 if (error) { 1051 device_printf(dev, "could not create RX DMA ring tag\n"); 1052 return (error); 1053 } 1054 1055 /* Allocate DMA'able memory for the RX ring */ 1056 1057 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1058 (void **)&sc->rl_ldata.rl_rx_list, 1059 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1060 &sc->rl_ldata.rl_rx_list_map); 1061 if (error) { 1062 device_printf(dev, "could not allocate RX DMA ring\n"); 1063 return (error); 1064 } 1065 1066 /* Load the map for the RX ring. */ 1067 1068 sc->rl_ldata.rl_rx_list_addr = 0; 1069 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1070 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1071 rx_list_size, re_dma_map_addr, 1072 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1073 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1074 device_printf(dev, "could not load RX DMA ring\n"); 1075 return (ENOMEM); 1076 } 1077 1078 /* Create DMA maps for RX buffers */ 1079 1080 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1081 &sc->rl_ldata.rl_rx_sparemap); 1082 if (error) { 1083 device_printf(dev, "could not create spare DMA map for RX\n"); 1084 return (error); 1085 } 1086 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1087 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1088 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1089 if (error) { 1090 device_printf(dev, "could not create DMA map for RX\n"); 1091 return (error); 1092 } 1093 } 1094 1095 return (0); 1096} 1097 1098/* 1099 * Attach the interface. Allocate softc structures, do ifmedia 1100 * setup and ethernet/BPF attach. 1101 */ 1102static int 1103re_attach(device_t dev) 1104{ 1105 u_char eaddr[ETHER_ADDR_LEN]; 1106 u_int16_t as[ETHER_ADDR_LEN / 2]; 1107 struct rl_softc *sc; 1108 struct ifnet *ifp; 1109 struct rl_hwrev *hw_rev; 1110 int hwrev; 1111 u_int16_t devid, re_did = 0; 1112 int error = 0, rid, i; 1113 int msic, reg; 1114 uint8_t cfg; 1115 1116 sc = device_get_softc(dev); 1117 sc->rl_dev = dev; 1118 1119 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1120 MTX_DEF); 1121 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1122 1123 /* 1124 * Map control/status registers. 1125 */ 1126 pci_enable_busmaster(dev); 1127 1128 devid = pci_get_device(dev); 1129 /* Prefer memory space register mapping over IO space. */ 1130 sc->rl_res_id = PCIR_BAR(1); 1131 sc->rl_res_type = SYS_RES_MEMORY; 1132 /* RTL8168/8101E seems to use different BARs. */ 1133 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1134 sc->rl_res_id = PCIR_BAR(2); 1135 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1136 &sc->rl_res_id, RF_ACTIVE); 1137 1138 if (sc->rl_res == NULL) { 1139 sc->rl_res_id = PCIR_BAR(0); 1140 sc->rl_res_type = SYS_RES_IOPORT; 1141 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1142 &sc->rl_res_id, RF_ACTIVE); 1143 if (sc->rl_res == NULL) { 1144 device_printf(dev, "couldn't map ports/memory\n"); 1145 error = ENXIO; 1146 goto fail; 1147 } 1148 } 1149 1150 sc->rl_btag = rman_get_bustag(sc->rl_res); 1151 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1152 1153 msic = 0; 1154 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1155 msic = pci_msi_count(dev); 1156 if (bootverbose) 1157 device_printf(dev, "MSI count : %d\n", msic); 1158 } 1159 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1160 if (pci_alloc_msi(dev, &msic) == 0) { 1161 if (msic == RL_MSI_MESSAGES) { 1162 device_printf(dev, "Using %d MSI messages\n", 1163 msic); 1164 sc->rl_flags |= RL_FLAG_MSI; 1165 /* Explicitly set MSI enable bit. */ 1166 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1167 cfg = CSR_READ_1(sc, RL_CFG2); 1168 cfg |= RL_CFG2_MSI; 1169 CSR_WRITE_1(sc, RL_CFG2, cfg); 1170 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1171 } else 1172 pci_release_msi(dev); 1173 } 1174 } 1175 1176 /* Allocate interrupt */ 1177 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1178 rid = 0; 1179 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1180 RF_SHAREABLE | RF_ACTIVE); 1181 if (sc->rl_irq[0] == NULL) { 1182 device_printf(dev, "couldn't allocate IRQ resources\n"); 1183 error = ENXIO; 1184 goto fail; 1185 } 1186 } else { 1187 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1188 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1189 SYS_RES_IRQ, &rid, RF_ACTIVE); 1190 if (sc->rl_irq[i] == NULL) { 1191 device_printf(dev, 1192 "couldn't llocate IRQ resources for " 1193 "message %d\n", rid); 1194 error = ENXIO; 1195 goto fail; 1196 } 1197 } 1198 } 1199 1200 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1201 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1202 cfg = CSR_READ_1(sc, RL_CFG2); 1203 if ((cfg & RL_CFG2_MSI) != 0) { 1204 device_printf(dev, "turning off MSI enable bit.\n"); 1205 cfg &= ~RL_CFG2_MSI; 1206 CSR_WRITE_1(sc, RL_CFG2, cfg); 1207 } 1208 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1209 } 1210 1211 /* Reset the adapter. */ 1212 RL_LOCK(sc); 1213 re_reset(sc); 1214 RL_UNLOCK(sc); 1215 1216 hw_rev = re_hwrevs; 1217 hwrev = CSR_READ_4(sc, RL_TXCFG); 1218 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1219 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1220 hwrev &= RL_TXCFG_HWREV; 1221 while (hw_rev->rl_desc != NULL) { 1222 if (hw_rev->rl_rev == hwrev) { 1223 sc->rl_type = hw_rev->rl_type; 1224 break; 1225 } 1226 hw_rev++; 1227 } 1228 if (hw_rev->rl_desc == NULL) { 1229 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1230 error = ENXIO; 1231 goto fail; 1232 } 1233 1234 switch (hw_rev->rl_rev) { 1235 case RL_HWREV_8139CPLUS: 1236 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER; 1237 break; 1238 case RL_HWREV_8100E: 1239 case RL_HWREV_8101E: 1240 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1241 RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1242 break; 1243 case RL_HWREV_8102E: 1244 case RL_HWREV_8102EL: 1245 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1246 RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1247 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER; 1248 break; 1249 case RL_HWREV_8168_SPIN1: 1250 case RL_HWREV_8168_SPIN2: 1251 case RL_HWREV_8168_SPIN3: 1252 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1253 RL_FLAG_MACSTAT; 1254 break; 1255 case RL_HWREV_8168C: 1256 case RL_HWREV_8168C_SPIN2: 1257 case RL_HWREV_8168CP: 1258 case RL_HWREV_8168D: 1259 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1260 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; 1261 /* 1262 * These controllers support jumbo frame but it seems 1263 * that enabling it requires touching additional magic 1264 * registers. Depending on MAC revisions some 1265 * controllers need to disable checksum offload. So 1266 * disable jumbo frame until I have better idea what 1267 * it really requires to make it support. 1268 * RTL8168C/CP : supports up to 6KB jumbo frame. 1269 * RTL8111C/CP : supports up to 9KB jumbo frame. 1270 */ 1271 sc->rl_flags |= RL_FLAG_NOJUMBO; 1272 break; 1273 case RL_HWREV_8169_8110SB: 1274 case RL_HWREV_8169_8110SC: 1275 case RL_HWREV_8169_8110SBL: 1276 sc->rl_flags |= RL_FLAG_PHYWAKE; 1277 break; 1278 default: 1279 break; 1280 } 1281 1282 /* Enable PME. */ 1283 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1284 cfg = CSR_READ_1(sc, RL_CFG1); 1285 cfg |= RL_CFG1_PME; 1286 CSR_WRITE_1(sc, RL_CFG1, cfg); 1287 cfg = CSR_READ_1(sc, RL_CFG5); 1288 cfg &= RL_CFG5_PME_STS; 1289 CSR_WRITE_1(sc, RL_CFG5, cfg); 1290 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1291 1292 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1293 /* 1294 * XXX Should have a better way to extract station 1295 * address from EEPROM. 1296 */ 1297 for (i = 0; i < ETHER_ADDR_LEN; i++) 1298 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1299 } else { 1300 sc->rl_eewidth = RL_9356_ADDR_LEN; 1301 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1302 if (re_did != 0x8129) 1303 sc->rl_eewidth = RL_9346_ADDR_LEN; 1304 1305 /* 1306 * Get station address from the EEPROM. 1307 */ 1308 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1309 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1310 as[i] = le16toh(as[i]); 1311 bcopy(as, eaddr, sizeof(eaddr)); 1312 } 1313 1314 if (sc->rl_type == RL_8169) { 1315 /* Set RX length mask and number of descriptors. */ 1316 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1317 sc->rl_txstart = RL_GTXSTART; 1318 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1319 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1320 } else { 1321 /* Set RX length mask and number of descriptors. */ 1322 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1323 sc->rl_txstart = RL_TXSTART; 1324 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1325 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1326 } 1327 1328 error = re_allocmem(dev, sc); 1329 if (error) 1330 goto fail; 1331 1332 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1333 if (ifp == NULL) { 1334 device_printf(dev, "can not if_alloc()\n"); 1335 error = ENOSPC; 1336 goto fail; 1337 } 1338 1339 /* Take PHY out of power down mode. */ 1340 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1341 re_gmii_writereg(dev, 1, 0x1f, 0); 1342 re_gmii_writereg(dev, 1, 0x0e, 0); 1343 } 1344 1345 /* Do MII setup */ 1346 if (mii_phy_probe(dev, &sc->rl_miibus, 1347 re_ifmedia_upd, re_ifmedia_sts)) { 1348 device_printf(dev, "MII without any phy!\n"); 1349 error = ENXIO; 1350 goto fail; 1351 } 1352 1353 ifp->if_softc = sc; 1354 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1355 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1356 ifp->if_ioctl = re_ioctl; 1357 ifp->if_start = re_start; 1358 ifp->if_hwassist = RE_CSUM_FEATURES; 1359 ifp->if_capabilities = IFCAP_HWCSUM; 1360 ifp->if_capenable = ifp->if_capabilities; 1361 ifp->if_init = re_init; 1362 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1363 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1364 IFQ_SET_READY(&ifp->if_snd); 1365 1366 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1367 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1368 1369 /* 1370 * XXX 1371 * Still have no idea how to make TSO work on 8168C, 8168CP, 1372 * 8111C and 8111CP. 1373 */ 1374 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1375 ifp->if_hwassist |= CSUM_TSO; 1376 ifp->if_capabilities |= IFCAP_TSO4; 1377 } 1378 1379 /* 1380 * Call MI attach routine. 1381 */ 1382 ether_ifattach(ifp, eaddr); 1383 1384 /* VLAN capability setup */ 1385 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1386 if (ifp->if_capabilities & IFCAP_HWCSUM) 1387 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1388 /* Enable WOL if PM is supported. */ 1389 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1390 ifp->if_capabilities |= IFCAP_WOL; 1391 ifp->if_capenable = ifp->if_capabilities; 1392 /* 1393 * Don't enable TSO by default. Under certain 1394 * circumtances the controller generated corrupted 1395 * packets in TSO size. 1396 */ 1397 ifp->if_hwassist &= ~CSUM_TSO; 1398 ifp->if_capenable &= ~IFCAP_TSO4; 1399#ifdef DEVICE_POLLING 1400 ifp->if_capabilities |= IFCAP_POLLING; 1401#endif 1402 /* 1403 * Tell the upper layer(s) we support long frames. 1404 * Must appear after the call to ether_ifattach() because 1405 * ether_ifattach() sets ifi_hdrlen to the default value. 1406 */ 1407 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1408 1409#ifdef RE_DIAG 1410 /* 1411 * Perform hardware diagnostic on the original RTL8169. 1412 * Some 32-bit cards were incorrectly wired and would 1413 * malfunction if plugged into a 64-bit slot. 1414 */ 1415 1416 if (hwrev == RL_HWREV_8169) { 1417 error = re_diag(sc); 1418 if (error) { 1419 device_printf(dev, 1420 "attach aborted due to hardware diag failure\n"); 1421 ether_ifdetach(ifp); 1422 goto fail; 1423 } 1424 } 1425#endif 1426 1427 /* Hook interrupt last to avoid having to lock softc */ 1428 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1429 error = bus_setup_intr(dev, sc->rl_irq[0], 1430 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1431 &sc->rl_intrhand[0]); 1432 else { 1433 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1434 error = bus_setup_intr(dev, sc->rl_irq[i], 1435 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1436 &sc->rl_intrhand[i]); 1437 if (error != 0) 1438 break; 1439 } 1440 } 1441 if (error) { 1442 device_printf(dev, "couldn't set up irq\n"); 1443 ether_ifdetach(ifp); 1444 } 1445 1446fail: 1447 1448 if (error) 1449 re_detach(dev); 1450 1451 return (error); 1452} 1453 1454/* 1455 * Shutdown hardware and free up resources. This can be called any 1456 * time after the mutex has been initialized. It is called in both 1457 * the error case in attach and the normal detach case so it needs 1458 * to be careful about only freeing resources that have actually been 1459 * allocated. 1460 */ 1461static int 1462re_detach(device_t dev) 1463{ 1464 struct rl_softc *sc; 1465 struct ifnet *ifp; 1466 int i, rid; 1467 1468 sc = device_get_softc(dev); 1469 ifp = sc->rl_ifp; 1470 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1471 1472 /* These should only be active if attach succeeded */ 1473 if (device_is_attached(dev)) { 1474#ifdef DEVICE_POLLING 1475 if (ifp->if_capenable & IFCAP_POLLING) 1476 ether_poll_deregister(ifp); 1477#endif 1478 RL_LOCK(sc); 1479#if 0 1480 sc->suspended = 1; 1481#endif 1482 re_stop(sc); 1483 RL_UNLOCK(sc); 1484 callout_drain(&sc->rl_stat_callout); 1485 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1486 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1487 /* 1488 * Force off the IFF_UP flag here, in case someone 1489 * still had a BPF descriptor attached to this 1490 * interface. If they do, ether_ifdetach() will cause 1491 * the BPF code to try and clear the promisc mode 1492 * flag, which will bubble down to re_ioctl(), 1493 * which will try to call re_init() again. This will 1494 * turn the NIC back on and restart the MII ticker, 1495 * which will panic the system when the kernel tries 1496 * to invoke the re_tick() function that isn't there 1497 * anymore. 1498 */ 1499 ifp->if_flags &= ~IFF_UP; 1500 ether_ifdetach(ifp); 1501 } 1502 if (sc->rl_miibus) 1503 device_delete_child(dev, sc->rl_miibus); 1504 bus_generic_detach(dev); 1505 1506 /* 1507 * The rest is resource deallocation, so we should already be 1508 * stopped here. 1509 */ 1510 1511 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1512 if (sc->rl_intrhand[i] != NULL) { 1513 bus_teardown_intr(dev, sc->rl_irq[i], 1514 sc->rl_intrhand[i]); 1515 sc->rl_intrhand[i] = NULL; 1516 } 1517 } 1518 if (ifp != NULL) 1519 if_free(ifp); 1520 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1521 if (sc->rl_irq[0] != NULL) { 1522 bus_release_resource(dev, SYS_RES_IRQ, 0, 1523 sc->rl_irq[0]); 1524 sc->rl_irq[0] = NULL; 1525 } 1526 } else { 1527 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1528 if (sc->rl_irq[i] != NULL) { 1529 bus_release_resource(dev, SYS_RES_IRQ, rid, 1530 sc->rl_irq[i]); 1531 sc->rl_irq[i] = NULL; 1532 } 1533 } 1534 pci_release_msi(dev); 1535 } 1536 if (sc->rl_res) 1537 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1538 sc->rl_res); 1539 1540 /* Unload and free the RX DMA ring memory and map */ 1541 1542 if (sc->rl_ldata.rl_rx_list_tag) { 1543 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1544 sc->rl_ldata.rl_rx_list_map); 1545 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1546 sc->rl_ldata.rl_rx_list, 1547 sc->rl_ldata.rl_rx_list_map); 1548 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1549 } 1550 1551 /* Unload and free the TX DMA ring memory and map */ 1552 1553 if (sc->rl_ldata.rl_tx_list_tag) { 1554 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1555 sc->rl_ldata.rl_tx_list_map); 1556 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1557 sc->rl_ldata.rl_tx_list, 1558 sc->rl_ldata.rl_tx_list_map); 1559 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1560 } 1561 1562 /* Destroy all the RX and TX buffer maps */ 1563 1564 if (sc->rl_ldata.rl_tx_mtag) { 1565 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1566 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1567 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1568 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1569 } 1570 if (sc->rl_ldata.rl_rx_mtag) { 1571 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1572 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1573 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1574 if (sc->rl_ldata.rl_rx_sparemap) 1575 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1576 sc->rl_ldata.rl_rx_sparemap); 1577 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1578 } 1579 1580 /* Unload and free the stats buffer and map */ 1581 1582 if (sc->rl_ldata.rl_stag) { 1583 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1584 sc->rl_ldata.rl_rx_list_map); 1585 bus_dmamem_free(sc->rl_ldata.rl_stag, 1586 sc->rl_ldata.rl_stats, 1587 sc->rl_ldata.rl_smap); 1588 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1589 } 1590 1591 if (sc->rl_parent_tag) 1592 bus_dma_tag_destroy(sc->rl_parent_tag); 1593 1594 mtx_destroy(&sc->rl_mtx); 1595 1596 return (0); 1597} 1598 1599static __inline void 1600re_discard_rxbuf(struct rl_softc *sc, int idx) 1601{ 1602 struct rl_desc *desc; 1603 struct rl_rxdesc *rxd; 1604 uint32_t cmdstat; 1605 1606 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1607 desc = &sc->rl_ldata.rl_rx_list[idx]; 1608 desc->rl_vlanctl = 0; 1609 cmdstat = rxd->rx_size; 1610 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1611 cmdstat |= RL_RDESC_CMD_EOR; 1612 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1613} 1614 1615static int 1616re_newbuf(struct rl_softc *sc, int idx) 1617{ 1618 struct mbuf *m; 1619 struct rl_rxdesc *rxd; 1620 bus_dma_segment_t segs[1]; 1621 bus_dmamap_t map; 1622 struct rl_desc *desc; 1623 uint32_t cmdstat; 1624 int error, nsegs; 1625 1626 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1627 if (m == NULL) 1628 return (ENOBUFS); 1629 1630 m->m_len = m->m_pkthdr.len = MCLBYTES; 1631#ifdef RE_FIXUP_RX 1632 /* 1633 * This is part of an evil trick to deal with non-x86 platforms. 1634 * The RealTek chip requires RX buffers to be aligned on 64-bit 1635 * boundaries, but that will hose non-x86 machines. To get around 1636 * this, we leave some empty space at the start of each buffer 1637 * and for non-x86 hosts, we copy the buffer back six bytes 1638 * to achieve word alignment. This is slightly more efficient 1639 * than allocating a new buffer, copying the contents, and 1640 * discarding the old buffer. 1641 */ 1642 m_adj(m, RE_ETHER_ALIGN); 1643#endif 1644 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1645 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1646 if (error != 0) { 1647 m_freem(m); 1648 return (ENOBUFS); 1649 } 1650 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1651 1652 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1653 if (rxd->rx_m != NULL) { 1654 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1655 BUS_DMASYNC_POSTREAD); 1656 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1657 } 1658 1659 rxd->rx_m = m; 1660 map = rxd->rx_dmamap; 1661 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1662 rxd->rx_size = segs[0].ds_len; 1663 sc->rl_ldata.rl_rx_sparemap = map; 1664 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1665 BUS_DMASYNC_PREREAD); 1666 1667 desc = &sc->rl_ldata.rl_rx_list[idx]; 1668 desc->rl_vlanctl = 0; 1669 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1670 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1671 cmdstat = segs[0].ds_len; 1672 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1673 cmdstat |= RL_RDESC_CMD_EOR; 1674 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1675 1676 return (0); 1677} 1678 1679#ifdef RE_FIXUP_RX 1680static __inline void 1681re_fixup_rx(struct mbuf *m) 1682{ 1683 int i; 1684 uint16_t *src, *dst; 1685 1686 src = mtod(m, uint16_t *); 1687 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1688 1689 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1690 *dst++ = *src++; 1691 1692 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1693} 1694#endif 1695 1696static int 1697re_tx_list_init(struct rl_softc *sc) 1698{ 1699 struct rl_desc *desc; 1700 int i; 1701 1702 RL_LOCK_ASSERT(sc); 1703 1704 bzero(sc->rl_ldata.rl_tx_list, 1705 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1706 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1707 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1708 /* Set EOR. */ 1709 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1710 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1711 1712 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1713 sc->rl_ldata.rl_tx_list_map, 1714 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1715 1716 sc->rl_ldata.rl_tx_prodidx = 0; 1717 sc->rl_ldata.rl_tx_considx = 0; 1718 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1719 1720 return (0); 1721} 1722 1723static int 1724re_rx_list_init(struct rl_softc *sc) 1725{ 1726 int error, i; 1727 1728 bzero(sc->rl_ldata.rl_rx_list, 1729 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1730 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1731 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1732 if ((error = re_newbuf(sc, i)) != 0) 1733 return (error); 1734 } 1735 1736 /* Flush the RX descriptors */ 1737 1738 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1739 sc->rl_ldata.rl_rx_list_map, 1740 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1741 1742 sc->rl_ldata.rl_rx_prodidx = 0; 1743 sc->rl_head = sc->rl_tail = NULL; 1744 1745 return (0); 1746} 1747 1748/* 1749 * RX handler for C+ and 8169. For the gigE chips, we support 1750 * the reception of jumbo frames that have been fragmented 1751 * across multiple 2K mbuf cluster buffers. 1752 */ 1753static int 1754re_rxeof(struct rl_softc *sc) 1755{ 1756 struct mbuf *m; 1757 struct ifnet *ifp; 1758 int i, total_len; 1759 struct rl_desc *cur_rx; 1760 u_int32_t rxstat, rxvlan; 1761 int maxpkt = 16; 1762 1763 RL_LOCK_ASSERT(sc); 1764 1765 ifp = sc->rl_ifp; 1766 1767 /* Invalidate the descriptor memory */ 1768 1769 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1770 sc->rl_ldata.rl_rx_list_map, 1771 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1772 1773 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1774 i = RL_RX_DESC_NXT(sc, i)) { 1775 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1776 rxstat = le32toh(cur_rx->rl_cmdstat); 1777 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1778 break; 1779 total_len = rxstat & sc->rl_rxlenmask; 1780 rxvlan = le32toh(cur_rx->rl_vlanctl); 1781 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1782 1783 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1784 if (re_newbuf(sc, i) != 0) { 1785 /* 1786 * If this is part of a multi-fragment packet, 1787 * discard all the pieces. 1788 */ 1789 if (sc->rl_head != NULL) { 1790 m_freem(sc->rl_head); 1791 sc->rl_head = sc->rl_tail = NULL; 1792 } 1793 re_discard_rxbuf(sc, i); 1794 continue; 1795 } 1796 m->m_len = RE_RX_DESC_BUFLEN; 1797 if (sc->rl_head == NULL) 1798 sc->rl_head = sc->rl_tail = m; 1799 else { 1800 m->m_flags &= ~M_PKTHDR; 1801 sc->rl_tail->m_next = m; 1802 sc->rl_tail = m; 1803 } 1804 continue; 1805 } 1806 1807 /* 1808 * NOTE: for the 8139C+, the frame length field 1809 * is always 12 bits in size, but for the gigE chips, 1810 * it is 13 bits (since the max RX frame length is 16K). 1811 * Unfortunately, all 32 bits in the status word 1812 * were already used, so to make room for the extra 1813 * length bit, RealTek took out the 'frame alignment 1814 * error' bit and shifted the other status bits 1815 * over one slot. The OWN, EOR, FS and LS bits are 1816 * still in the same places. We have already extracted 1817 * the frame length and checked the OWN bit, so rather 1818 * than using an alternate bit mapping, we shift the 1819 * status bits one space to the right so we can evaluate 1820 * them using the 8169 status as though it was in the 1821 * same format as that of the 8139C+. 1822 */ 1823 if (sc->rl_type == RL_8169) 1824 rxstat >>= 1; 1825 1826 /* 1827 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1828 * set, but if CRC is clear, it will still be a valid frame. 1829 */ 1830 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1831 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1832 ifp->if_ierrors++; 1833 /* 1834 * If this is part of a multi-fragment packet, 1835 * discard all the pieces. 1836 */ 1837 if (sc->rl_head != NULL) { 1838 m_freem(sc->rl_head); 1839 sc->rl_head = sc->rl_tail = NULL; 1840 } 1841 re_discard_rxbuf(sc, i); 1842 continue; 1843 } 1844 1845 /* 1846 * If allocating a replacement mbuf fails, 1847 * reload the current one. 1848 */ 1849 1850 if (re_newbuf(sc, i) != 0) { 1851 ifp->if_iqdrops++; 1852 if (sc->rl_head != NULL) { 1853 m_freem(sc->rl_head); 1854 sc->rl_head = sc->rl_tail = NULL; 1855 } 1856 re_discard_rxbuf(sc, i); 1857 continue; 1858 } 1859 1860 if (sc->rl_head != NULL) { 1861 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1862 if (m->m_len == 0) 1863 m->m_len = RE_RX_DESC_BUFLEN; 1864 /* 1865 * Special case: if there's 4 bytes or less 1866 * in this buffer, the mbuf can be discarded: 1867 * the last 4 bytes is the CRC, which we don't 1868 * care about anyway. 1869 */ 1870 if (m->m_len <= ETHER_CRC_LEN) { 1871 sc->rl_tail->m_len -= 1872 (ETHER_CRC_LEN - m->m_len); 1873 m_freem(m); 1874 } else { 1875 m->m_len -= ETHER_CRC_LEN; 1876 m->m_flags &= ~M_PKTHDR; 1877 sc->rl_tail->m_next = m; 1878 } 1879 m = sc->rl_head; 1880 sc->rl_head = sc->rl_tail = NULL; 1881 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1882 } else 1883 m->m_pkthdr.len = m->m_len = 1884 (total_len - ETHER_CRC_LEN); 1885 1886#ifdef RE_FIXUP_RX 1887 re_fixup_rx(m); 1888#endif 1889 ifp->if_ipackets++; 1890 m->m_pkthdr.rcvif = ifp; 1891 1892 /* Do RX checksumming if enabled */ 1893 1894 if (ifp->if_capenable & IFCAP_RXCSUM) { 1895 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1896 /* Check IP header checksum */ 1897 if (rxstat & RL_RDESC_STAT_PROTOID) 1898 m->m_pkthdr.csum_flags |= 1899 CSUM_IP_CHECKED; 1900 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1901 m->m_pkthdr.csum_flags |= 1902 CSUM_IP_VALID; 1903 1904 /* Check TCP/UDP checksum */ 1905 if ((RL_TCPPKT(rxstat) && 1906 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1907 (RL_UDPPKT(rxstat) && 1908 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1909 m->m_pkthdr.csum_flags |= 1910 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1911 m->m_pkthdr.csum_data = 0xffff; 1912 } 1913 } else { 1914 /* 1915 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1916 */ 1917 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1918 (rxvlan & RL_RDESC_IPV4)) 1919 m->m_pkthdr.csum_flags |= 1920 CSUM_IP_CHECKED; 1921 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1922 (rxvlan & RL_RDESC_IPV4)) 1923 m->m_pkthdr.csum_flags |= 1924 CSUM_IP_VALID; 1925 if (((rxstat & RL_RDESC_STAT_TCP) && 1926 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1927 ((rxstat & RL_RDESC_STAT_UDP) && 1928 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1929 m->m_pkthdr.csum_flags |= 1930 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1931 m->m_pkthdr.csum_data = 0xffff; 1932 } 1933 } 1934 } 1935 maxpkt--; 1936 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1937 m->m_pkthdr.ether_vtag = 1938 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 1939 m->m_flags |= M_VLANTAG; 1940 } 1941 RL_UNLOCK(sc); 1942 (*ifp->if_input)(ifp, m); 1943 RL_LOCK(sc); 1944 } 1945 1946 /* Flush the RX DMA ring */ 1947 1948 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1949 sc->rl_ldata.rl_rx_list_map, 1950 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1951 1952 sc->rl_ldata.rl_rx_prodidx = i; 1953 1954 if (maxpkt) 1955 return(EAGAIN); 1956 1957 return(0); 1958} 1959 1960static void 1961re_txeof(struct rl_softc *sc) 1962{ 1963 struct ifnet *ifp; 1964 struct rl_txdesc *txd; 1965 u_int32_t txstat; 1966 int cons; 1967 1968 cons = sc->rl_ldata.rl_tx_considx; 1969 if (cons == sc->rl_ldata.rl_tx_prodidx) 1970 return; 1971 1972 ifp = sc->rl_ifp; 1973 /* Invalidate the TX descriptor list */ 1974 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1975 sc->rl_ldata.rl_tx_list_map, 1976 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1977 1978 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1979 cons = RL_TX_DESC_NXT(sc, cons)) { 1980 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1981 if (txstat & RL_TDESC_STAT_OWN) 1982 break; 1983 /* 1984 * We only stash mbufs in the last descriptor 1985 * in a fragment chain, which also happens to 1986 * be the only place where the TX status bits 1987 * are valid. 1988 */ 1989 if (txstat & RL_TDESC_CMD_EOF) { 1990 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1991 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1992 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1993 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1994 txd->tx_dmamap); 1995 KASSERT(txd->tx_m != NULL, 1996 ("%s: freeing NULL mbufs!", __func__)); 1997 m_freem(txd->tx_m); 1998 txd->tx_m = NULL; 1999 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2000 RL_TDESC_STAT_COLCNT)) 2001 ifp->if_collisions++; 2002 if (txstat & RL_TDESC_STAT_TXERRSUM) 2003 ifp->if_oerrors++; 2004 else 2005 ifp->if_opackets++; 2006 } 2007 sc->rl_ldata.rl_tx_free++; 2008 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2009 } 2010 sc->rl_ldata.rl_tx_considx = cons; 2011 2012 /* No changes made to the TX ring, so no flush needed */ 2013 2014 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2015 /* 2016 * Some chips will ignore a second TX request issued 2017 * while an existing transmission is in progress. If 2018 * the transmitter goes idle but there are still 2019 * packets waiting to be sent, we need to restart the 2020 * channel here to flush them out. This only seems to 2021 * be required with the PCIe devices. 2022 */ 2023 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2024 2025#ifdef RE_TX_MODERATION 2026 /* 2027 * If not all descriptors have been reaped yet, reload 2028 * the timer so that we will eventually get another 2029 * interrupt that will cause us to re-enter this routine. 2030 * This is done in case the transmitter has gone idle. 2031 */ 2032 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2033#endif 2034 } else 2035 sc->rl_watchdog_timer = 0; 2036} 2037 2038static void 2039re_tick(void *xsc) 2040{ 2041 struct rl_softc *sc; 2042 struct mii_data *mii; 2043 2044 sc = xsc; 2045 2046 RL_LOCK_ASSERT(sc); 2047 2048 mii = device_get_softc(sc->rl_miibus); 2049 mii_tick(mii); 2050 re_watchdog(sc); 2051 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2052} 2053 2054#ifdef DEVICE_POLLING 2055static void 2056re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2057{ 2058 struct rl_softc *sc = ifp->if_softc; 2059 2060 RL_LOCK(sc); 2061 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2062 re_poll_locked(ifp, cmd, count); 2063 RL_UNLOCK(sc); 2064} 2065 2066static void 2067re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2068{ 2069 struct rl_softc *sc = ifp->if_softc; 2070 2071 RL_LOCK_ASSERT(sc); 2072 2073 sc->rxcycles = count; 2074 re_rxeof(sc); 2075 re_txeof(sc); 2076 2077 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2078 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2079 2080 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2081 u_int16_t status; 2082 2083 status = CSR_READ_2(sc, RL_ISR); 2084 if (status == 0xffff) 2085 return; 2086 if (status) 2087 CSR_WRITE_2(sc, RL_ISR, status); 2088 2089 /* 2090 * XXX check behaviour on receiver stalls. 2091 */ 2092 2093 if (status & RL_ISR_SYSTEM_ERR) 2094 re_init_locked(sc); 2095 } 2096} 2097#endif /* DEVICE_POLLING */ 2098 2099static int 2100re_intr(void *arg) 2101{ 2102 struct rl_softc *sc; 2103 uint16_t status; 2104 2105 sc = arg; 2106 2107 status = CSR_READ_2(sc, RL_ISR); 2108 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2109 return (FILTER_STRAY); 2110 CSR_WRITE_2(sc, RL_IMR, 0); 2111 2112 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2113 2114 return (FILTER_HANDLED); 2115} 2116 2117static void 2118re_int_task(void *arg, int npending) 2119{ 2120 struct rl_softc *sc; 2121 struct ifnet *ifp; 2122 u_int16_t status; 2123 int rval = 0; 2124 2125 sc = arg; 2126 ifp = sc->rl_ifp; 2127 2128 RL_LOCK(sc); 2129 2130 status = CSR_READ_2(sc, RL_ISR); 2131 CSR_WRITE_2(sc, RL_ISR, status); 2132 2133 if (sc->suspended || 2134 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2135 RL_UNLOCK(sc); 2136 return; 2137 } 2138 2139#ifdef DEVICE_POLLING 2140 if (ifp->if_capenable & IFCAP_POLLING) { 2141 RL_UNLOCK(sc); 2142 return; 2143 } 2144#endif 2145 2146 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2147 rval = re_rxeof(sc); 2148 2149 if (status & ( 2150#ifdef RE_TX_MODERATION 2151 RL_ISR_TIMEOUT_EXPIRED| 2152#else 2153 RL_ISR_TX_OK| 2154#endif 2155 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2156 re_txeof(sc); 2157 2158 if (status & RL_ISR_SYSTEM_ERR) 2159 re_init_locked(sc); 2160 2161 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2162 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2163 2164 RL_UNLOCK(sc); 2165 2166 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2167 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2168 return; 2169 } 2170 2171 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2172} 2173 2174static int 2175re_encap(struct rl_softc *sc, struct mbuf **m_head) 2176{ 2177 struct rl_txdesc *txd, *txd_last; 2178 bus_dma_segment_t segs[RL_NTXSEGS]; 2179 bus_dmamap_t map; 2180 struct mbuf *m_new; 2181 struct rl_desc *desc; 2182 int nsegs, prod; 2183 int i, error, ei, si; 2184 int padlen; 2185 uint32_t cmdstat, csum_flags, vlanctl; 2186 2187 RL_LOCK_ASSERT(sc); 2188 M_ASSERTPKTHDR((*m_head)); 2189 2190 /* 2191 * With some of the RealTek chips, using the checksum offload 2192 * support in conjunction with the autopadding feature results 2193 * in the transmission of corrupt frames. For example, if we 2194 * need to send a really small IP fragment that's less than 60 2195 * bytes in size, and IP header checksumming is enabled, the 2196 * resulting ethernet frame that appears on the wire will 2197 * have garbled payload. To work around this, if TX IP checksum 2198 * offload is enabled, we always manually pad short frames out 2199 * to the minimum ethernet frame size. 2200 */ 2201 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2202 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2203 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2204 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2205 if (M_WRITABLE(*m_head) == 0) { 2206 /* Get a writable copy. */ 2207 m_new = m_dup(*m_head, M_DONTWAIT); 2208 m_freem(*m_head); 2209 if (m_new == NULL) { 2210 *m_head = NULL; 2211 return (ENOBUFS); 2212 } 2213 *m_head = m_new; 2214 } 2215 if ((*m_head)->m_next != NULL || 2216 M_TRAILINGSPACE(*m_head) < padlen) { 2217 m_new = m_defrag(*m_head, M_DONTWAIT); 2218 if (m_new == NULL) { 2219 m_freem(*m_head); 2220 *m_head = NULL; 2221 return (ENOBUFS); 2222 } 2223 } else 2224 m_new = *m_head; 2225 2226 /* 2227 * Manually pad short frames, and zero the pad space 2228 * to avoid leaking data. 2229 */ 2230 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2231 m_new->m_pkthdr.len += padlen; 2232 m_new->m_len = m_new->m_pkthdr.len; 2233 *m_head = m_new; 2234 } 2235 2236 prod = sc->rl_ldata.rl_tx_prodidx; 2237 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2238 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2239 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2240 if (error == EFBIG) { 2241 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2242 if (m_new == NULL) { 2243 m_freem(*m_head); 2244 *m_head = NULL; 2245 return (ENOBUFS); 2246 } 2247 *m_head = m_new; 2248 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2249 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2250 if (error != 0) { 2251 m_freem(*m_head); 2252 *m_head = NULL; 2253 return (error); 2254 } 2255 } else if (error != 0) 2256 return (error); 2257 if (nsegs == 0) { 2258 m_freem(*m_head); 2259 *m_head = NULL; 2260 return (EIO); 2261 } 2262 2263 /* Check for number of available descriptors. */ 2264 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2265 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2266 return (ENOBUFS); 2267 } 2268 2269 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2270 BUS_DMASYNC_PREWRITE); 2271 2272 /* 2273 * Set up checksum offload. Note: checksum offload bits must 2274 * appear in all descriptors of a multi-descriptor transmit 2275 * attempt. This is according to testing done with an 8169 2276 * chip. This is a requirement. 2277 */ 2278 vlanctl = 0; 2279 csum_flags = 0; 2280 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2281 csum_flags = RL_TDESC_CMD_LGSEND | 2282 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2283 RL_TDESC_CMD_MSSVAL_SHIFT); 2284 else { 2285 /* 2286 * Unconditionally enable IP checksum if TCP or UDP 2287 * checksum is required. Otherwise, TCP/UDP checksum 2288 * does't make effects. 2289 */ 2290 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2291 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2292 csum_flags |= RL_TDESC_CMD_IPCSUM; 2293 if (((*m_head)->m_pkthdr.csum_flags & 2294 CSUM_TCP) != 0) 2295 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2296 if (((*m_head)->m_pkthdr.csum_flags & 2297 CSUM_UDP) != 0) 2298 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2299 } else { 2300 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2301 if (((*m_head)->m_pkthdr.csum_flags & 2302 CSUM_TCP) != 0) 2303 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2304 if (((*m_head)->m_pkthdr.csum_flags & 2305 CSUM_UDP) != 0) 2306 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2307 } 2308 } 2309 } 2310 2311 /* 2312 * Set up hardware VLAN tagging. Note: vlan tag info must 2313 * appear in all descriptors of a multi-descriptor 2314 * transmission attempt. 2315 */ 2316 if ((*m_head)->m_flags & M_VLANTAG) 2317 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2318 RL_TDESC_VLANCTL_TAG; 2319 2320 si = prod; 2321 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2322 desc = &sc->rl_ldata.rl_tx_list[prod]; 2323 desc->rl_vlanctl = htole32(vlanctl); 2324 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2325 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2326 cmdstat = segs[i].ds_len; 2327 if (i != 0) 2328 cmdstat |= RL_TDESC_CMD_OWN; 2329 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2330 cmdstat |= RL_TDESC_CMD_EOR; 2331 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2332 sc->rl_ldata.rl_tx_free--; 2333 } 2334 /* Update producer index. */ 2335 sc->rl_ldata.rl_tx_prodidx = prod; 2336 2337 /* Set EOF on the last descriptor. */ 2338 ei = RL_TX_DESC_PRV(sc, prod); 2339 desc = &sc->rl_ldata.rl_tx_list[ei]; 2340 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2341 2342 desc = &sc->rl_ldata.rl_tx_list[si]; 2343 /* Set SOF and transfer ownership of packet to the chip. */ 2344 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2345 2346 /* 2347 * Insure that the map for this transmission 2348 * is placed at the array index of the last descriptor 2349 * in this chain. (Swap last and first dmamaps.) 2350 */ 2351 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2352 map = txd->tx_dmamap; 2353 txd->tx_dmamap = txd_last->tx_dmamap; 2354 txd_last->tx_dmamap = map; 2355 txd_last->tx_m = *m_head; 2356 2357 return (0); 2358} 2359 2360static void 2361re_tx_task(void *arg, int npending) 2362{ 2363 struct ifnet *ifp; 2364 2365 ifp = arg; 2366 re_start(ifp); 2367} 2368 2369/* 2370 * Main transmit routine for C+ and gigE NICs. 2371 */ 2372static void 2373re_start(struct ifnet *ifp) 2374{ 2375 struct rl_softc *sc; 2376 struct mbuf *m_head; 2377 int queued; 2378 2379 sc = ifp->if_softc; 2380 2381 RL_LOCK(sc); 2382 2383 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2384 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2385 RL_UNLOCK(sc); 2386 return; 2387 } 2388 2389 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2390 sc->rl_ldata.rl_tx_free > 1;) { 2391 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2392 if (m_head == NULL) 2393 break; 2394 2395 if (re_encap(sc, &m_head) != 0) { 2396 if (m_head == NULL) 2397 break; 2398 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2399 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2400 break; 2401 } 2402 2403 /* 2404 * If there's a BPF listener, bounce a copy of this frame 2405 * to him. 2406 */ 2407 ETHER_BPF_MTAP(ifp, m_head); 2408 2409 queued++; 2410 } 2411 2412 if (queued == 0) { 2413#ifdef RE_TX_MODERATION 2414 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2415 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2416#endif 2417 RL_UNLOCK(sc); 2418 return; 2419 } 2420 2421 /* Flush the TX descriptors */ 2422 2423 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2424 sc->rl_ldata.rl_tx_list_map, 2425 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2426 2427 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2428 2429#ifdef RE_TX_MODERATION 2430 /* 2431 * Use the countdown timer for interrupt moderation. 2432 * 'TX done' interrupts are disabled. Instead, we reset the 2433 * countdown timer, which will begin counting until it hits 2434 * the value in the TIMERINT register, and then trigger an 2435 * interrupt. Each time we write to the TIMERCNT register, 2436 * the timer count is reset to 0. 2437 */ 2438 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2439#endif 2440 2441 /* 2442 * Set a timeout in case the chip goes out to lunch. 2443 */ 2444 sc->rl_watchdog_timer = 5; 2445 2446 RL_UNLOCK(sc); 2447} 2448 2449static void 2450re_init(void *xsc) 2451{ 2452 struct rl_softc *sc = xsc; 2453 2454 RL_LOCK(sc); 2455 re_init_locked(sc); 2456 RL_UNLOCK(sc); 2457} 2458 2459static void 2460re_init_locked(struct rl_softc *sc) 2461{ 2462 struct ifnet *ifp = sc->rl_ifp; 2463 struct mii_data *mii; 2464 u_int32_t rxcfg = 0; 2465 uint16_t cfg; 2466 union { 2467 uint32_t align_dummy; 2468 u_char eaddr[ETHER_ADDR_LEN]; 2469 } eaddr; 2470 2471 RL_LOCK_ASSERT(sc); 2472 2473 mii = device_get_softc(sc->rl_miibus); 2474 2475 /* 2476 * Cancel pending I/O and free all RX/TX buffers. 2477 */ 2478 re_stop(sc); 2479 2480 /* Put controller into known state. */ 2481 re_reset(sc); 2482 2483 /* 2484 * Enable C+ RX and TX mode, as well as VLAN stripping and 2485 * RX checksum offload. We must configure the C+ register 2486 * before all others. 2487 */ 2488 cfg = RL_CPLUSCMD_PCI_MRW; 2489 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2490 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2491 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2492 cfg |= RL_CPLUSCMD_VLANSTRIP; 2493 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2494 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2495 /* XXX magic. */ 2496 cfg |= 0x0001; 2497 } else 2498 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2499 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2500 /* 2501 * Disable TSO if interface MTU size is greater than MSS 2502 * allowed in controller. 2503 */ 2504 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2505 ifp->if_capenable &= ~IFCAP_TSO4; 2506 ifp->if_hwassist &= ~CSUM_TSO; 2507 } 2508 2509 /* 2510 * Init our MAC address. Even though the chipset 2511 * documentation doesn't mention it, we need to enter "Config 2512 * register write enable" mode to modify the ID registers. 2513 */ 2514 /* Copy MAC address on stack to align. */ 2515 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2516 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2517 CSR_WRITE_4(sc, RL_IDR0, 2518 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2519 CSR_WRITE_4(sc, RL_IDR4, 2520 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2521 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2522 2523 /* 2524 * For C+ mode, initialize the RX descriptors and mbufs. 2525 */ 2526 re_rx_list_init(sc); 2527 re_tx_list_init(sc); 2528 2529 /* 2530 * Load the addresses of the RX and TX lists into the chip. 2531 */ 2532 2533 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2534 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2535 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2536 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2537 2538 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2539 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2540 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2541 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2542 2543 /* 2544 * Enable transmit and receive. 2545 */ 2546 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2547 2548 /* 2549 * Set the initial TX and RX configuration. 2550 */ 2551 if (sc->rl_testmode) { 2552 if (sc->rl_type == RL_8169) 2553 CSR_WRITE_4(sc, RL_TXCFG, 2554 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2555 else 2556 CSR_WRITE_4(sc, RL_TXCFG, 2557 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2558 } else 2559 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2560 2561 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2562 2563 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2564 2565 /* Set the individual bit to receive frames for this host only. */ 2566 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2567 rxcfg |= RL_RXCFG_RX_INDIV; 2568 2569 /* If we want promiscuous mode, set the allframes bit. */ 2570 if (ifp->if_flags & IFF_PROMISC) 2571 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2572 else 2573 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2574 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2575 2576 /* 2577 * Set capture broadcast bit to capture broadcast frames. 2578 */ 2579 if (ifp->if_flags & IFF_BROADCAST) 2580 rxcfg |= RL_RXCFG_RX_BROAD; 2581 else 2582 rxcfg &= ~RL_RXCFG_RX_BROAD; 2583 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2584 2585 /* 2586 * Program the multicast filter, if necessary. 2587 */ 2588 re_setmulti(sc); 2589 2590#ifdef DEVICE_POLLING 2591 /* 2592 * Disable interrupts if we are polling. 2593 */ 2594 if (ifp->if_capenable & IFCAP_POLLING) 2595 CSR_WRITE_2(sc, RL_IMR, 0); 2596 else /* otherwise ... */ 2597#endif 2598 2599 /* 2600 * Enable interrupts. 2601 */ 2602 if (sc->rl_testmode) 2603 CSR_WRITE_2(sc, RL_IMR, 0); 2604 else 2605 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2606 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2607 2608 /* Set initial TX threshold */ 2609 sc->rl_txthresh = RL_TX_THRESH_INIT; 2610 2611 /* Start RX/TX process. */ 2612 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2613#ifdef notdef 2614 /* Enable receiver and transmitter. */ 2615 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2616#endif 2617 2618#ifdef RE_TX_MODERATION 2619 /* 2620 * Initialize the timer interrupt register so that 2621 * a timer interrupt will be generated once the timer 2622 * reaches a certain number of ticks. The timer is 2623 * reloaded on each transmit. This gives us TX interrupt 2624 * moderation, which dramatically improves TX frame rate. 2625 */ 2626 if (sc->rl_type == RL_8169) 2627 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2628 else 2629 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2630#endif 2631 2632 /* 2633 * For 8169 gigE NICs, set the max allowed RX packet 2634 * size so we can receive jumbo frames. 2635 */ 2636 if (sc->rl_type == RL_8169) 2637 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2638 2639 if (sc->rl_testmode) 2640 return; 2641 2642 mii_mediachg(mii); 2643 2644 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2645 2646 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2647 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2648 2649 sc->rl_flags &= ~RL_FLAG_LINK; 2650 sc->rl_watchdog_timer = 0; 2651 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2652} 2653 2654/* 2655 * Set media options. 2656 */ 2657static int 2658re_ifmedia_upd(struct ifnet *ifp) 2659{ 2660 struct rl_softc *sc; 2661 struct mii_data *mii; 2662 int error; 2663 2664 sc = ifp->if_softc; 2665 mii = device_get_softc(sc->rl_miibus); 2666 RL_LOCK(sc); 2667 error = mii_mediachg(mii); 2668 RL_UNLOCK(sc); 2669 2670 return (error); 2671} 2672 2673/* 2674 * Report current media status. 2675 */ 2676static void 2677re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2678{ 2679 struct rl_softc *sc; 2680 struct mii_data *mii; 2681 2682 sc = ifp->if_softc; 2683 mii = device_get_softc(sc->rl_miibus); 2684 2685 RL_LOCK(sc); 2686 mii_pollstat(mii); 2687 RL_UNLOCK(sc); 2688 ifmr->ifm_active = mii->mii_media_active; 2689 ifmr->ifm_status = mii->mii_media_status; 2690} 2691 2692static int 2693re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2694{ 2695 struct rl_softc *sc = ifp->if_softc; 2696 struct ifreq *ifr = (struct ifreq *) data; 2697 struct mii_data *mii; 2698 int error = 0; 2699 2700 switch (command) { 2701 case SIOCSIFMTU: 2702 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2703 error = EINVAL; 2704 break; 2705 } 2706 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2707 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2708 error = EINVAL; 2709 break; 2710 } 2711 RL_LOCK(sc); 2712 if (ifp->if_mtu != ifr->ifr_mtu) 2713 ifp->if_mtu = ifr->ifr_mtu; 2714 if (ifp->if_mtu > RL_TSO_MTU && 2715 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2716 ifp->if_capenable &= ~IFCAP_TSO4; 2717 ifp->if_hwassist &= ~CSUM_TSO; 2718 } 2719 RL_UNLOCK(sc); 2720 break; 2721 case SIOCSIFFLAGS: 2722 RL_LOCK(sc); 2723 if ((ifp->if_flags & IFF_UP) != 0) { 2724 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2725 if (((ifp->if_flags ^ sc->rl_if_flags) 2726 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2727 re_setmulti(sc); 2728 } else 2729 re_init_locked(sc); 2730 } else { 2731 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2732 re_stop(sc); 2733 } 2734 sc->rl_if_flags = ifp->if_flags; 2735 RL_UNLOCK(sc); 2736 break; 2737 case SIOCADDMULTI: 2738 case SIOCDELMULTI: 2739 RL_LOCK(sc); 2740 re_setmulti(sc); 2741 RL_UNLOCK(sc); 2742 break; 2743 case SIOCGIFMEDIA: 2744 case SIOCSIFMEDIA: 2745 mii = device_get_softc(sc->rl_miibus); 2746 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2747 break; 2748 case SIOCSIFCAP: 2749 { 2750 int mask, reinit; 2751 2752 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2753 reinit = 0; 2754#ifdef DEVICE_POLLING 2755 if (mask & IFCAP_POLLING) { 2756 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2757 error = ether_poll_register(re_poll, ifp); 2758 if (error) 2759 return(error); 2760 RL_LOCK(sc); 2761 /* Disable interrupts */ 2762 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2763 ifp->if_capenable |= IFCAP_POLLING; 2764 RL_UNLOCK(sc); 2765 } else { 2766 error = ether_poll_deregister(ifp); 2767 /* Enable interrupts. */ 2768 RL_LOCK(sc); 2769 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2770 ifp->if_capenable &= ~IFCAP_POLLING; 2771 RL_UNLOCK(sc); 2772 } 2773 } 2774#endif /* DEVICE_POLLING */ 2775 if (mask & IFCAP_HWCSUM) { 2776 ifp->if_capenable ^= IFCAP_HWCSUM; 2777 if (ifp->if_capenable & IFCAP_TXCSUM) 2778 ifp->if_hwassist |= RE_CSUM_FEATURES; 2779 else 2780 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2781 reinit = 1; 2782 } 2783 if (mask & IFCAP_VLAN_HWTAGGING) { 2784 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2785 reinit = 1; 2786 } 2787 if (mask & IFCAP_TSO4) { 2788 ifp->if_capenable ^= IFCAP_TSO4; 2789 if ((IFCAP_TSO4 & ifp->if_capenable) && 2790 (IFCAP_TSO4 & ifp->if_capabilities)) 2791 ifp->if_hwassist |= CSUM_TSO; 2792 else 2793 ifp->if_hwassist &= ~CSUM_TSO; 2794 if (ifp->if_mtu > RL_TSO_MTU && 2795 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2796 ifp->if_capenable &= ~IFCAP_TSO4; 2797 ifp->if_hwassist &= ~CSUM_TSO; 2798 } 2799 } 2800 if ((mask & IFCAP_WOL) != 0 && 2801 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2802 if ((mask & IFCAP_WOL_UCAST) != 0) 2803 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2804 if ((mask & IFCAP_WOL_MCAST) != 0) 2805 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2806 if ((mask & IFCAP_WOL_MAGIC) != 0) 2807 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2808 } 2809 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2810 re_init(sc); 2811 VLAN_CAPABILITIES(ifp); 2812 } 2813 break; 2814 default: 2815 error = ether_ioctl(ifp, command, data); 2816 break; 2817 } 2818 2819 return (error); 2820} 2821 2822static void 2823re_watchdog(struct rl_softc *sc) 2824{ 2825 struct ifnet *ifp; 2826 2827 RL_LOCK_ASSERT(sc); 2828 2829 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2830 return; 2831 2832 ifp = sc->rl_ifp; 2833 re_txeof(sc); 2834 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2835 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2836 "-- recovering\n"); 2837 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2838 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2839 return; 2840 } 2841 2842 if_printf(ifp, "watchdog timeout\n"); 2843 ifp->if_oerrors++; 2844 2845 re_rxeof(sc); 2846 re_init_locked(sc); 2847 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2848 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2849} 2850 2851/* 2852 * Stop the adapter and free any mbufs allocated to the 2853 * RX and TX lists. 2854 */ 2855static void 2856re_stop(struct rl_softc *sc) 2857{ 2858 int i; 2859 struct ifnet *ifp; 2860 struct rl_txdesc *txd; 2861 struct rl_rxdesc *rxd; 2862 2863 RL_LOCK_ASSERT(sc); 2864 2865 ifp = sc->rl_ifp; 2866 2867 sc->rl_watchdog_timer = 0; 2868 callout_stop(&sc->rl_stat_callout); 2869 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2870 2871 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2872 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2873 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2874 2875 if (sc->rl_head != NULL) { 2876 m_freem(sc->rl_head); 2877 sc->rl_head = sc->rl_tail = NULL; 2878 } 2879 2880 /* Free the TX list buffers. */ 2881 2882 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2883 txd = &sc->rl_ldata.rl_tx_desc[i]; 2884 if (txd->tx_m != NULL) { 2885 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2886 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2887 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2888 txd->tx_dmamap); 2889 m_freem(txd->tx_m); 2890 txd->tx_m = NULL; 2891 } 2892 } 2893 2894 /* Free the RX list buffers. */ 2895 2896 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2897 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2898 if (rxd->rx_m != NULL) { 2899 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2900 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2901 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2902 rxd->rx_dmamap); 2903 m_freem(rxd->rx_m); 2904 rxd->rx_m = NULL; 2905 } 2906 } 2907} 2908 2909/* 2910 * Device suspend routine. Stop the interface and save some PCI 2911 * settings in case the BIOS doesn't restore them properly on 2912 * resume. 2913 */ 2914static int 2915re_suspend(device_t dev) 2916{ 2917 struct rl_softc *sc; 2918 2919 sc = device_get_softc(dev); 2920 2921 RL_LOCK(sc); 2922 re_stop(sc); 2923 re_setwol(sc); 2924 sc->suspended = 1; 2925 RL_UNLOCK(sc); 2926 2927 return (0); 2928} 2929 2930/* 2931 * Device resume routine. Restore some PCI settings in case the BIOS 2932 * doesn't, re-enable busmastering, and restart the interface if 2933 * appropriate. 2934 */ 2935static int 2936re_resume(device_t dev) 2937{ 2938 struct rl_softc *sc; 2939 struct ifnet *ifp; 2940 2941 sc = device_get_softc(dev); 2942 2943 RL_LOCK(sc); 2944 2945 ifp = sc->rl_ifp; 2946 2947 /* reinitialize interface if necessary */ 2948 if (ifp->if_flags & IFF_UP) 2949 re_init_locked(sc); 2950 2951 /* 2952 * Clear WOL matching such that normal Rx filtering 2953 * wouldn't interfere with WOL patterns. 2954 */ 2955 re_clrwol(sc); 2956 sc->suspended = 0; 2957 RL_UNLOCK(sc); 2958 2959 return (0); 2960} 2961 2962/* 2963 * Stop all chip I/O so that the kernel's probe routines don't 2964 * get confused by errant DMAs when rebooting. 2965 */ 2966static int 2967re_shutdown(device_t dev) 2968{ 2969 struct rl_softc *sc; 2970 2971 sc = device_get_softc(dev); 2972 2973 RL_LOCK(sc); 2974 re_stop(sc); 2975 /* 2976 * Mark interface as down since otherwise we will panic if 2977 * interrupt comes in later on, which can happen in some 2978 * cases. 2979 */ 2980 sc->rl_ifp->if_flags &= ~IFF_UP; 2981 re_setwol(sc); 2982 RL_UNLOCK(sc); 2983 2984 return (0); 2985} 2986 2987static void 2988re_setwol(struct rl_softc *sc) 2989{ 2990 struct ifnet *ifp; 2991 int pmc; 2992 uint16_t pmstat; 2993 uint8_t v; 2994 2995 RL_LOCK_ASSERT(sc); 2996 2997 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2998 return; 2999 3000 ifp = sc->rl_ifp; 3001 /* Enable config register write. */ 3002 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3003 3004 /* Enable PME. */ 3005 v = CSR_READ_1(sc, RL_CFG1); 3006 v &= ~RL_CFG1_PME; 3007 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3008 v |= RL_CFG1_PME; 3009 CSR_WRITE_1(sc, RL_CFG1, v); 3010 3011 v = CSR_READ_1(sc, RL_CFG3); 3012 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3013 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3014 v |= RL_CFG3_WOL_MAGIC; 3015 CSR_WRITE_1(sc, RL_CFG3, v); 3016 3017 /* Config register write done. */ 3018 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3019 3020 v = CSR_READ_1(sc, RL_CFG5); 3021 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3022 v &= ~RL_CFG5_WOL_LANWAKE; 3023 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3024 v |= RL_CFG5_WOL_UCAST; 3025 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3026 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3027 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3028 v |= RL_CFG5_WOL_LANWAKE; 3029 CSR_WRITE_1(sc, RL_CFG5, v); 3030 3031 /* 3032 * It seems that hardware resets its link speed to 100Mbps in 3033 * power down mode so switching to 100Mbps in driver is not 3034 * needed. 3035 */ 3036 3037 /* Request PME if WOL is requested. */ 3038 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3039 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3040 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3041 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3042 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3043} 3044 3045static void 3046re_clrwol(struct rl_softc *sc) 3047{ 3048 int pmc; 3049 uint8_t v; 3050 3051 RL_LOCK_ASSERT(sc); 3052 3053 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3054 return; 3055 3056 /* Enable config register write. */ 3057 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3058 3059 v = CSR_READ_1(sc, RL_CFG3); 3060 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3061 CSR_WRITE_1(sc, RL_CFG3, v); 3062 3063 /* Config register write done. */ 3064 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3065 3066 v = CSR_READ_1(sc, RL_CFG5); 3067 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3068 v &= ~RL_CFG5_WOL_LANWAKE; 3069 CSR_WRITE_1(sc, RL_CFG5, v); 3070} 3071