if_re.c revision 181275
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 181275 2008-08-04 04:00:10Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* Tunables. */ 159static int msi_disable = 1; 160TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164/* 165 * Various supported device vendors/types and their names. 166 */ 167static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8168C/8168CP/8111B/8111C/8111CP PCIe " 176 "Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8169, 0, 178 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 182 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 183 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 184 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 185 { USR_VENDORID, USR_DEVICEID_997902, 0, 186 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 187}; 188 189static struct rl_hwrev re_hwrevs[] = { 190 { RL_HWREV_8139, RL_8139, "" }, 191 { RL_HWREV_8139A, RL_8139, "A" }, 192 { RL_HWREV_8139AG, RL_8139, "A-G" }, 193 { RL_HWREV_8139B, RL_8139, "B" }, 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 204 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL"}, 205 { RL_HWREV_8100, RL_8139, "8100"}, 206 { RL_HWREV_8101, RL_8139, "8101"}, 207 { RL_HWREV_8100E, RL_8169, "8100E"}, 208 { RL_HWREV_8101E, RL_8169, "8101E"}, 209 { RL_HWREV_8102E, RL_8169, "8102E"}, 210 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 211 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 212 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 213 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 214 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 215 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 216 { 0, 0, NULL } 217}; 218 219static int re_probe (device_t); 220static int re_attach (device_t); 221static int re_detach (device_t); 222 223static int re_encap (struct rl_softc *, struct mbuf **); 224 225static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 226static int re_allocmem (device_t, struct rl_softc *); 227static __inline void re_discard_rxbuf 228 (struct rl_softc *, int); 229static int re_newbuf (struct rl_softc *, int); 230static int re_rx_list_init (struct rl_softc *); 231static int re_tx_list_init (struct rl_softc *); 232#ifdef RE_FIXUP_RX 233static __inline void re_fixup_rx 234 (struct mbuf *); 235#endif 236static int re_rxeof (struct rl_softc *); 237static void re_txeof (struct rl_softc *); 238#ifdef DEVICE_POLLING 239static void re_poll (struct ifnet *, enum poll_cmd, int); 240static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 241#endif 242static int re_intr (void *); 243static void re_tick (void *); 244static void re_tx_task (void *, int); 245static void re_int_task (void *, int); 246static void re_start (struct ifnet *); 247static int re_ioctl (struct ifnet *, u_long, caddr_t); 248static void re_init (void *); 249static void re_init_locked (struct rl_softc *); 250static void re_stop (struct rl_softc *); 251static void re_watchdog (struct rl_softc *); 252static int re_suspend (device_t); 253static int re_resume (device_t); 254static int re_shutdown (device_t); 255static int re_ifmedia_upd (struct ifnet *); 256static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 257 258static void re_eeprom_putbyte (struct rl_softc *, int); 259static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 260static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 261static int re_gmii_readreg (device_t, int, int); 262static int re_gmii_writereg (device_t, int, int, int); 263 264static int re_miibus_readreg (device_t, int, int); 265static int re_miibus_writereg (device_t, int, int, int); 266static void re_miibus_statchg (device_t); 267 268static void re_setmulti (struct rl_softc *); 269static void re_reset (struct rl_softc *); 270static void re_setwol (struct rl_softc *); 271static void re_clrwol (struct rl_softc *); 272 273#ifdef RE_DIAG 274static int re_diag (struct rl_softc *); 275#endif 276 277static device_method_t re_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, re_probe), 280 DEVMETHOD(device_attach, re_attach), 281 DEVMETHOD(device_detach, re_detach), 282 DEVMETHOD(device_suspend, re_suspend), 283 DEVMETHOD(device_resume, re_resume), 284 DEVMETHOD(device_shutdown, re_shutdown), 285 286 /* bus interface */ 287 DEVMETHOD(bus_print_child, bus_generic_print_child), 288 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 289 290 /* MII interface */ 291 DEVMETHOD(miibus_readreg, re_miibus_readreg), 292 DEVMETHOD(miibus_writereg, re_miibus_writereg), 293 DEVMETHOD(miibus_statchg, re_miibus_statchg), 294 295 { 0, 0 } 296}; 297 298static driver_t re_driver = { 299 "re", 300 re_methods, 301 sizeof(struct rl_softc) 302}; 303 304static devclass_t re_devclass; 305 306DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 307DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 308DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 309 310#define EE_SET(x) \ 311 CSR_WRITE_1(sc, RL_EECMD, \ 312 CSR_READ_1(sc, RL_EECMD) | x) 313 314#define EE_CLR(x) \ 315 CSR_WRITE_1(sc, RL_EECMD, \ 316 CSR_READ_1(sc, RL_EECMD) & ~x) 317 318/* 319 * Send a read command and address to the EEPROM, check for ACK. 320 */ 321static void 322re_eeprom_putbyte(struct rl_softc *sc, int addr) 323{ 324 int d, i; 325 326 d = addr | (RL_9346_READ << sc->rl_eewidth); 327 328 /* 329 * Feed in each bit and strobe the clock. 330 */ 331 332 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 333 if (d & i) { 334 EE_SET(RL_EE_DATAIN); 335 } else { 336 EE_CLR(RL_EE_DATAIN); 337 } 338 DELAY(100); 339 EE_SET(RL_EE_CLK); 340 DELAY(150); 341 EE_CLR(RL_EE_CLK); 342 DELAY(100); 343 } 344} 345 346/* 347 * Read a word of data stored in the EEPROM at address 'addr.' 348 */ 349static void 350re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 351{ 352 int i; 353 u_int16_t word = 0; 354 355 /* 356 * Send address of word we want to read. 357 */ 358 re_eeprom_putbyte(sc, addr); 359 360 /* 361 * Start reading bits from EEPROM. 362 */ 363 for (i = 0x8000; i; i >>= 1) { 364 EE_SET(RL_EE_CLK); 365 DELAY(100); 366 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 367 word |= i; 368 EE_CLR(RL_EE_CLK); 369 DELAY(100); 370 } 371 372 *dest = word; 373} 374 375/* 376 * Read a sequence of words from the EEPROM. 377 */ 378static void 379re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 380{ 381 int i; 382 u_int16_t word = 0, *ptr; 383 384 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 385 386 DELAY(100); 387 388 for (i = 0; i < cnt; i++) { 389 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 390 re_eeprom_getword(sc, off + i, &word); 391 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 392 ptr = (u_int16_t *)(dest + (i * 2)); 393 *ptr = word; 394 } 395 396 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 397} 398 399static int 400re_gmii_readreg(device_t dev, int phy, int reg) 401{ 402 struct rl_softc *sc; 403 u_int32_t rval; 404 int i; 405 406 if (phy != 1) 407 return (0); 408 409 sc = device_get_softc(dev); 410 411 /* Let the rgephy driver read the GMEDIASTAT register */ 412 413 if (reg == RL_GMEDIASTAT) { 414 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 415 return (rval); 416 } 417 418 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 419 DELAY(1000); 420 421 for (i = 0; i < RL_TIMEOUT; i++) { 422 rval = CSR_READ_4(sc, RL_PHYAR); 423 if (rval & RL_PHYAR_BUSY) 424 break; 425 DELAY(100); 426 } 427 428 if (i == RL_TIMEOUT) { 429 device_printf(sc->rl_dev, "PHY read failed\n"); 430 return (0); 431 } 432 433 return (rval & RL_PHYAR_PHYDATA); 434} 435 436static int 437re_gmii_writereg(device_t dev, int phy, int reg, int data) 438{ 439 struct rl_softc *sc; 440 u_int32_t rval; 441 int i; 442 443 sc = device_get_softc(dev); 444 445 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 446 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 447 DELAY(1000); 448 449 for (i = 0; i < RL_TIMEOUT; i++) { 450 rval = CSR_READ_4(sc, RL_PHYAR); 451 if (!(rval & RL_PHYAR_BUSY)) 452 break; 453 DELAY(100); 454 } 455 456 if (i == RL_TIMEOUT) { 457 device_printf(sc->rl_dev, "PHY write failed\n"); 458 return (0); 459 } 460 461 return (0); 462} 463 464static int 465re_miibus_readreg(device_t dev, int phy, int reg) 466{ 467 struct rl_softc *sc; 468 u_int16_t rval = 0; 469 u_int16_t re8139_reg = 0; 470 471 sc = device_get_softc(dev); 472 473 if (sc->rl_type == RL_8169) { 474 rval = re_gmii_readreg(dev, phy, reg); 475 return (rval); 476 } 477 478 /* Pretend the internal PHY is only at address 0 */ 479 if (phy) { 480 return (0); 481 } 482 switch (reg) { 483 case MII_BMCR: 484 re8139_reg = RL_BMCR; 485 break; 486 case MII_BMSR: 487 re8139_reg = RL_BMSR; 488 break; 489 case MII_ANAR: 490 re8139_reg = RL_ANAR; 491 break; 492 case MII_ANER: 493 re8139_reg = RL_ANER; 494 break; 495 case MII_ANLPAR: 496 re8139_reg = RL_LPAR; 497 break; 498 case MII_PHYIDR1: 499 case MII_PHYIDR2: 500 return (0); 501 /* 502 * Allow the rlphy driver to read the media status 503 * register. If we have a link partner which does not 504 * support NWAY, this is the register which will tell 505 * us the results of parallel detection. 506 */ 507 case RL_MEDIASTAT: 508 rval = CSR_READ_1(sc, RL_MEDIASTAT); 509 return (rval); 510 default: 511 device_printf(sc->rl_dev, "bad phy register\n"); 512 return (0); 513 } 514 rval = CSR_READ_2(sc, re8139_reg); 515 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 516 /* 8139C+ has different bit layout. */ 517 rval &= ~(BMCR_LOOP | BMCR_ISO); 518 } 519 return (rval); 520} 521 522static int 523re_miibus_writereg(device_t dev, int phy, int reg, int data) 524{ 525 struct rl_softc *sc; 526 u_int16_t re8139_reg = 0; 527 int rval = 0; 528 529 sc = device_get_softc(dev); 530 531 if (sc->rl_type == RL_8169) { 532 rval = re_gmii_writereg(dev, phy, reg, data); 533 return (rval); 534 } 535 536 /* Pretend the internal PHY is only at address 0 */ 537 if (phy) 538 return (0); 539 540 switch (reg) { 541 case MII_BMCR: 542 re8139_reg = RL_BMCR; 543 if (sc->rl_type == RL_8139CPLUS) { 544 /* 8139C+ has different bit layout. */ 545 data &= ~(BMCR_LOOP | BMCR_ISO); 546 } 547 break; 548 case MII_BMSR: 549 re8139_reg = RL_BMSR; 550 break; 551 case MII_ANAR: 552 re8139_reg = RL_ANAR; 553 break; 554 case MII_ANER: 555 re8139_reg = RL_ANER; 556 break; 557 case MII_ANLPAR: 558 re8139_reg = RL_LPAR; 559 break; 560 case MII_PHYIDR1: 561 case MII_PHYIDR2: 562 return (0); 563 break; 564 default: 565 device_printf(sc->rl_dev, "bad phy register\n"); 566 return (0); 567 } 568 CSR_WRITE_2(sc, re8139_reg, data); 569 return (0); 570} 571 572static void 573re_miibus_statchg(device_t dev) 574{ 575 576} 577 578/* 579 * Program the 64-bit multicast hash filter. 580 */ 581static void 582re_setmulti(struct rl_softc *sc) 583{ 584 struct ifnet *ifp; 585 int h = 0; 586 u_int32_t hashes[2] = { 0, 0 }; 587 struct ifmultiaddr *ifma; 588 u_int32_t rxfilt; 589 int mcnt = 0; 590 591 RL_LOCK_ASSERT(sc); 592 593 ifp = sc->rl_ifp; 594 595 596 rxfilt = CSR_READ_4(sc, RL_RXCFG); 597 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 598 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 599 if (ifp->if_flags & IFF_PROMISC) 600 rxfilt |= RL_RXCFG_RX_ALLPHYS; 601 /* 602 * Unlike other hardwares, we have to explicitly set 603 * RL_RXCFG_RX_MULTI to receive multicast frames in 604 * promiscuous mode. 605 */ 606 rxfilt |= RL_RXCFG_RX_MULTI; 607 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 608 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 609 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 610 return; 611 } 612 613 /* first, zot all the existing hash bits */ 614 CSR_WRITE_4(sc, RL_MAR0, 0); 615 CSR_WRITE_4(sc, RL_MAR4, 0); 616 617 /* now program new ones */ 618 IF_ADDR_LOCK(ifp); 619 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 620 if (ifma->ifma_addr->sa_family != AF_LINK) 621 continue; 622 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 623 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 624 if (h < 32) 625 hashes[0] |= (1 << h); 626 else 627 hashes[1] |= (1 << (h - 32)); 628 mcnt++; 629 } 630 IF_ADDR_UNLOCK(ifp); 631 632 if (mcnt) 633 rxfilt |= RL_RXCFG_RX_MULTI; 634 else 635 rxfilt &= ~RL_RXCFG_RX_MULTI; 636 637 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 638 639 /* 640 * For some unfathomable reason, RealTek decided to reverse 641 * the order of the multicast hash registers in the PCI Express 642 * parts. This means we have to write the hash pattern in reverse 643 * order for those devices. 644 */ 645 646 if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) { 647 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 648 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 649 } else { 650 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 651 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 652 } 653} 654 655static void 656re_reset(struct rl_softc *sc) 657{ 658 int i; 659 660 RL_LOCK_ASSERT(sc); 661 662 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 663 664 for (i = 0; i < RL_TIMEOUT; i++) { 665 DELAY(10); 666 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 667 break; 668 } 669 if (i == RL_TIMEOUT) 670 device_printf(sc->rl_dev, "reset never completed!\n"); 671 672 CSR_WRITE_1(sc, 0x82, 1); 673} 674 675#ifdef RE_DIAG 676 677/* 678 * The following routine is designed to test for a defect on some 679 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 680 * lines connected to the bus, however for a 32-bit only card, they 681 * should be pulled high. The result of this defect is that the 682 * NIC will not work right if you plug it into a 64-bit slot: DMA 683 * operations will be done with 64-bit transfers, which will fail 684 * because the 64-bit data lines aren't connected. 685 * 686 * There's no way to work around this (short of talking a soldering 687 * iron to the board), however we can detect it. The method we use 688 * here is to put the NIC into digital loopback mode, set the receiver 689 * to promiscuous mode, and then try to send a frame. We then compare 690 * the frame data we sent to what was received. If the data matches, 691 * then the NIC is working correctly, otherwise we know the user has 692 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 693 * slot. In the latter case, there's no way the NIC can work correctly, 694 * so we print out a message on the console and abort the device attach. 695 */ 696 697static int 698re_diag(struct rl_softc *sc) 699{ 700 struct ifnet *ifp = sc->rl_ifp; 701 struct mbuf *m0; 702 struct ether_header *eh; 703 struct rl_desc *cur_rx; 704 u_int16_t status; 705 u_int32_t rxstat; 706 int total_len, i, error = 0, phyaddr; 707 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 708 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 709 710 /* Allocate a single mbuf */ 711 MGETHDR(m0, M_DONTWAIT, MT_DATA); 712 if (m0 == NULL) 713 return (ENOBUFS); 714 715 RL_LOCK(sc); 716 717 /* 718 * Initialize the NIC in test mode. This sets the chip up 719 * so that it can send and receive frames, but performs the 720 * following special functions: 721 * - Puts receiver in promiscuous mode 722 * - Enables digital loopback mode 723 * - Leaves interrupts turned off 724 */ 725 726 ifp->if_flags |= IFF_PROMISC; 727 sc->rl_testmode = 1; 728 re_reset(sc); 729 re_init_locked(sc); 730 sc->rl_flags |= RL_FLAG_LINK; 731 if (sc->rl_type == RL_8169) 732 phyaddr = 1; 733 else 734 phyaddr = 0; 735 736 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 737 for (i = 0; i < RL_TIMEOUT; i++) { 738 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 739 if (!(status & BMCR_RESET)) 740 break; 741 } 742 743 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 744 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 745 746 DELAY(100000); 747 748 /* Put some data in the mbuf */ 749 750 eh = mtod(m0, struct ether_header *); 751 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 752 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 753 eh->ether_type = htons(ETHERTYPE_IP); 754 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 755 756 /* 757 * Queue the packet, start transmission. 758 * Note: IF_HANDOFF() ultimately calls re_start() for us. 759 */ 760 761 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 762 RL_UNLOCK(sc); 763 /* XXX: re_diag must not be called when in ALTQ mode */ 764 IF_HANDOFF(&ifp->if_snd, m0, ifp); 765 RL_LOCK(sc); 766 m0 = NULL; 767 768 /* Wait for it to propagate through the chip */ 769 770 DELAY(100000); 771 for (i = 0; i < RL_TIMEOUT; i++) { 772 status = CSR_READ_2(sc, RL_ISR); 773 CSR_WRITE_2(sc, RL_ISR, status); 774 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 775 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 776 break; 777 DELAY(10); 778 } 779 780 if (i == RL_TIMEOUT) { 781 device_printf(sc->rl_dev, 782 "diagnostic failed, failed to receive packet in" 783 " loopback mode\n"); 784 error = EIO; 785 goto done; 786 } 787 788 /* 789 * The packet should have been dumped into the first 790 * entry in the RX DMA ring. Grab it from there. 791 */ 792 793 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 794 sc->rl_ldata.rl_rx_list_map, 795 BUS_DMASYNC_POSTREAD); 796 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 797 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 798 BUS_DMASYNC_POSTREAD); 799 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 800 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 801 802 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 803 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 804 eh = mtod(m0, struct ether_header *); 805 806 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 807 total_len = RL_RXBYTES(cur_rx); 808 rxstat = le32toh(cur_rx->rl_cmdstat); 809 810 if (total_len != ETHER_MIN_LEN) { 811 device_printf(sc->rl_dev, 812 "diagnostic failed, received short packet\n"); 813 error = EIO; 814 goto done; 815 } 816 817 /* Test that the received packet data matches what we sent. */ 818 819 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 820 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 821 ntohs(eh->ether_type) != ETHERTYPE_IP) { 822 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 823 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 824 dst, ":", src, ":", ETHERTYPE_IP); 825 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 826 eh->ether_dhost, ":", eh->ether_shost, ":", 827 ntohs(eh->ether_type)); 828 device_printf(sc->rl_dev, "You may have a defective 32-bit " 829 "NIC plugged into a 64-bit PCI slot.\n"); 830 device_printf(sc->rl_dev, "Please re-install the NIC in a " 831 "32-bit slot for proper operation.\n"); 832 device_printf(sc->rl_dev, "Read the re(4) man page for more " 833 "details.\n"); 834 error = EIO; 835 } 836 837done: 838 /* Turn interface off, release resources */ 839 840 sc->rl_testmode = 0; 841 sc->rl_flags &= ~RL_FLAG_LINK; 842 ifp->if_flags &= ~IFF_PROMISC; 843 re_stop(sc); 844 if (m0 != NULL) 845 m_freem(m0); 846 847 RL_UNLOCK(sc); 848 849 return (error); 850} 851 852#endif 853 854/* 855 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 856 * IDs against our list and return a device name if we find a match. 857 */ 858static int 859re_probe(device_t dev) 860{ 861 struct rl_type *t; 862 uint16_t devid, vendor; 863 uint16_t revid, sdevid; 864 int i; 865 866 vendor = pci_get_vendor(dev); 867 devid = pci_get_device(dev); 868 revid = pci_get_revid(dev); 869 sdevid = pci_get_subdevice(dev); 870 871 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 872 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 873 /* 874 * Only attach to rev. 3 of the Linksys EG1032 adapter. 875 * Rev. 2 is supported by sk(4). 876 */ 877 return (ENXIO); 878 } 879 } 880 881 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 882 if (revid != 0x20) { 883 /* 8139, let rl(4) take care of this device. */ 884 return (ENXIO); 885 } 886 } 887 888 t = re_devs; 889 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 890 if (vendor == t->rl_vid && devid == t->rl_did) { 891 device_set_desc(dev, t->rl_name); 892 return (BUS_PROBE_DEFAULT); 893 } 894 } 895 896 return (ENXIO); 897} 898 899/* 900 * Map a single buffer address. 901 */ 902 903static void 904re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 905{ 906 bus_addr_t *addr; 907 908 if (error) 909 return; 910 911 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 912 addr = arg; 913 *addr = segs->ds_addr; 914} 915 916static int 917re_allocmem(device_t dev, struct rl_softc *sc) 918{ 919 bus_size_t rx_list_size, tx_list_size; 920 int error; 921 int i; 922 923 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 924 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 925 926 /* 927 * Allocate the parent bus DMA tag appropriate for PCI. 928 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 929 * register should be set. However some RealTek chips are known 930 * to be buggy on DAC handling, therefore disable DAC by limiting 931 * DMA address space to 32bit. PCIe variants of RealTek chips 932 * may not have the limitation but I took safer path. 933 */ 934 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 935 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 936 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 937 NULL, NULL, &sc->rl_parent_tag); 938 if (error) { 939 device_printf(dev, "could not allocate parent DMA tag\n"); 940 return (error); 941 } 942 943 /* 944 * Allocate map for TX mbufs. 945 */ 946 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 947 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 948 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 949 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 950 if (error) { 951 device_printf(dev, "could not allocate TX DMA tag\n"); 952 return (error); 953 } 954 955 /* 956 * Allocate map for RX mbufs. 957 */ 958 959 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 960 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 961 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 962 if (error) { 963 device_printf(dev, "could not allocate RX DMA tag\n"); 964 return (error); 965 } 966 967 /* 968 * Allocate map for TX descriptor list. 969 */ 970 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 971 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 972 NULL, tx_list_size, 1, tx_list_size, 0, 973 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 974 if (error) { 975 device_printf(dev, "could not allocate TX DMA ring tag\n"); 976 return (error); 977 } 978 979 /* Allocate DMA'able memory for the TX ring */ 980 981 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 982 (void **)&sc->rl_ldata.rl_tx_list, 983 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 984 &sc->rl_ldata.rl_tx_list_map); 985 if (error) { 986 device_printf(dev, "could not allocate TX DMA ring\n"); 987 return (error); 988 } 989 990 /* Load the map for the TX ring. */ 991 992 sc->rl_ldata.rl_tx_list_addr = 0; 993 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 994 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 995 tx_list_size, re_dma_map_addr, 996 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 997 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 998 device_printf(dev, "could not load TX DMA ring\n"); 999 return (ENOMEM); 1000 } 1001 1002 /* Create DMA maps for TX buffers */ 1003 1004 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1005 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1006 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1007 if (error) { 1008 device_printf(dev, "could not create DMA map for TX\n"); 1009 return (error); 1010 } 1011 } 1012 1013 /* 1014 * Allocate map for RX descriptor list. 1015 */ 1016 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1017 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1018 NULL, rx_list_size, 1, rx_list_size, 0, 1019 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1020 if (error) { 1021 device_printf(dev, "could not create RX DMA ring tag\n"); 1022 return (error); 1023 } 1024 1025 /* Allocate DMA'able memory for the RX ring */ 1026 1027 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1028 (void **)&sc->rl_ldata.rl_rx_list, 1029 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1030 &sc->rl_ldata.rl_rx_list_map); 1031 if (error) { 1032 device_printf(dev, "could not allocate RX DMA ring\n"); 1033 return (error); 1034 } 1035 1036 /* Load the map for the RX ring. */ 1037 1038 sc->rl_ldata.rl_rx_list_addr = 0; 1039 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1040 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1041 rx_list_size, re_dma_map_addr, 1042 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1043 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1044 device_printf(dev, "could not load RX DMA ring\n"); 1045 return (ENOMEM); 1046 } 1047 1048 /* Create DMA maps for RX buffers */ 1049 1050 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1051 &sc->rl_ldata.rl_rx_sparemap); 1052 if (error) { 1053 device_printf(dev, "could not create spare DMA map for RX\n"); 1054 return (error); 1055 } 1056 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1057 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1058 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1059 if (error) { 1060 device_printf(dev, "could not create DMA map for RX\n"); 1061 return (error); 1062 } 1063 } 1064 1065 return (0); 1066} 1067 1068/* 1069 * Attach the interface. Allocate softc structures, do ifmedia 1070 * setup and ethernet/BPF attach. 1071 */ 1072static int 1073re_attach(device_t dev) 1074{ 1075 u_char eaddr[ETHER_ADDR_LEN]; 1076 u_int16_t as[ETHER_ADDR_LEN / 2]; 1077 struct rl_softc *sc; 1078 struct ifnet *ifp; 1079 struct rl_hwrev *hw_rev; 1080 int hwrev; 1081 u_int16_t devid, re_did = 0; 1082 int error = 0, rid, i; 1083 int msic, reg; 1084 uint8_t cfg; 1085 1086 sc = device_get_softc(dev); 1087 sc->rl_dev = dev; 1088 1089 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1090 MTX_DEF); 1091 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1092 1093 /* 1094 * Map control/status registers. 1095 */ 1096 pci_enable_busmaster(dev); 1097 1098 devid = pci_get_device(dev); 1099 /* Prefer memory space register mapping over IO space. */ 1100 sc->rl_res_id = PCIR_BAR(1); 1101 sc->rl_res_type = SYS_RES_MEMORY; 1102 /* RTL8168/8101E seems to use different BARs. */ 1103 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1104 sc->rl_res_id = PCIR_BAR(2); 1105 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1106 &sc->rl_res_id, RF_ACTIVE); 1107 1108 if (sc->rl_res == NULL) { 1109 sc->rl_res_id = PCIR_BAR(0); 1110 sc->rl_res_type = SYS_RES_IOPORT; 1111 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1112 &sc->rl_res_id, RF_ACTIVE); 1113 if (sc->rl_res == NULL) { 1114 device_printf(dev, "couldn't map ports/memory\n"); 1115 error = ENXIO; 1116 goto fail; 1117 } 1118 } 1119 1120 sc->rl_btag = rman_get_bustag(sc->rl_res); 1121 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1122 1123 msic = 0; 1124 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1125 msic = pci_msi_count(dev); 1126 if (bootverbose) 1127 device_printf(dev, "MSI count : %d\n", msic); 1128 } 1129 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1130 if (pci_alloc_msi(dev, &msic) == 0) { 1131 if (msic == RL_MSI_MESSAGES) { 1132 device_printf(dev, "Using %d MSI messages\n", 1133 msic); 1134 sc->rl_flags |= RL_FLAG_MSI; 1135 /* Explicitly set MSI enable bit. */ 1136 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1137 cfg = CSR_READ_1(sc, RL_CFG2); 1138 cfg |= RL_CFG2_MSI; 1139 CSR_WRITE_1(sc, RL_CFG2, cfg); 1140 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1141 } else 1142 pci_release_msi(dev); 1143 } 1144 } 1145 1146 /* Allocate interrupt */ 1147 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1148 rid = 0; 1149 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1150 RF_SHAREABLE | RF_ACTIVE); 1151 if (sc->rl_irq[0] == NULL) { 1152 device_printf(dev, "couldn't allocate IRQ resources\n"); 1153 error = ENXIO; 1154 goto fail; 1155 } 1156 } else { 1157 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1158 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1159 SYS_RES_IRQ, &rid, RF_ACTIVE); 1160 if (sc->rl_irq[i] == NULL) { 1161 device_printf(dev, 1162 "couldn't llocate IRQ resources for " 1163 "message %d\n", rid); 1164 error = ENXIO; 1165 goto fail; 1166 } 1167 } 1168 } 1169 1170 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1171 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1172 cfg = CSR_READ_1(sc, RL_CFG2); 1173 if ((cfg & RL_CFG2_MSI) != 0) { 1174 device_printf(dev, "turning off MSI enable bit.\n"); 1175 cfg &= ~RL_CFG2_MSI; 1176 CSR_WRITE_1(sc, RL_CFG2, cfg); 1177 } 1178 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1179 } 1180 1181 /* Reset the adapter. */ 1182 RL_LOCK(sc); 1183 re_reset(sc); 1184 RL_UNLOCK(sc); 1185 1186 hw_rev = re_hwrevs; 1187 hwrev = CSR_READ_4(sc, RL_TXCFG); 1188 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1189 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1190 hwrev &= RL_TXCFG_HWREV; 1191 while (hw_rev->rl_desc != NULL) { 1192 if (hw_rev->rl_rev == hwrev) { 1193 sc->rl_type = hw_rev->rl_type; 1194 break; 1195 } 1196 hw_rev++; 1197 } 1198 if (hw_rev->rl_desc == NULL) { 1199 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1200 error = ENXIO; 1201 goto fail; 1202 } 1203 1204 switch (hw_rev->rl_rev) { 1205 case RL_HWREV_8139CPLUS: 1206 sc->rl_flags |= RL_FLAG_NOJUMBO; 1207 break; 1208 case RL_HWREV_8100E: 1209 case RL_HWREV_8101E: 1210 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1211 RL_FLAG_PHYWAKE; 1212 break; 1213 case RL_HWREV_8102E: 1214 case RL_HWREV_8102EL: 1215 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1216 RL_FLAG_PHYWAKE | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; 1217 break; 1218 case RL_HWREV_8168_SPIN1: 1219 case RL_HWREV_8168_SPIN2: 1220 case RL_HWREV_8168_SPIN3: 1221 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1222 RL_FLAG_MACSTAT; 1223 break; 1224 case RL_HWREV_8168C: 1225 case RL_HWREV_8168C_SPIN2: 1226 case RL_HWREV_8168CP: 1227 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1228 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; 1229 /* 1230 * These controllers support jumbo frame but it seems 1231 * that enabling it requires touching additional magic 1232 * registers. Depending on MAC revisions some 1233 * controllers need to disable checksum offload. So 1234 * disable jumbo frame until I have better idea what 1235 * it really requires to make it support. 1236 * RTL8168C/CP : supports up to 6KB jumbo frame. 1237 * RTL8111C/CP : supports up to 9KB jumbo frame. 1238 */ 1239 sc->rl_flags |= RL_FLAG_NOJUMBO; 1240 break; 1241 case RL_HWREV_8169_8110SB: 1242 case RL_HWREV_8169_8110SC: 1243 case RL_HWREV_8169_8110SBL: 1244 sc->rl_flags |= RL_FLAG_PHYWAKE; 1245 break; 1246 default: 1247 break; 1248 } 1249 1250 /* Enable PME. */ 1251 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1252 cfg = CSR_READ_1(sc, RL_CFG1); 1253 cfg |= RL_CFG1_PME; 1254 CSR_WRITE_1(sc, RL_CFG1, cfg); 1255 cfg = CSR_READ_1(sc, RL_CFG5); 1256 cfg &= RL_CFG5_PME_STS; 1257 CSR_WRITE_1(sc, RL_CFG5, cfg); 1258 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1259 1260 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1261 /* 1262 * XXX Should have a better way to extract station 1263 * address from EEPROM. 1264 */ 1265 for (i = 0; i < ETHER_ADDR_LEN; i++) 1266 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1267 } else { 1268 sc->rl_eewidth = RL_9356_ADDR_LEN; 1269 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1270 if (re_did != 0x8129) 1271 sc->rl_eewidth = RL_9346_ADDR_LEN; 1272 1273 /* 1274 * Get station address from the EEPROM. 1275 */ 1276 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1277 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1278 as[i] = le16toh(as[i]); 1279 bcopy(as, eaddr, sizeof(eaddr)); 1280 } 1281 1282 if (sc->rl_type == RL_8169) { 1283 /* Set RX length mask and number of descriptors. */ 1284 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1285 sc->rl_txstart = RL_GTXSTART; 1286 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1287 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1288 } else { 1289 /* Set RX length mask and number of descriptors. */ 1290 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1291 sc->rl_txstart = RL_TXSTART; 1292 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1293 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1294 } 1295 1296 error = re_allocmem(dev, sc); 1297 if (error) 1298 goto fail; 1299 1300 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1301 if (ifp == NULL) { 1302 device_printf(dev, "can not if_alloc()\n"); 1303 error = ENOSPC; 1304 goto fail; 1305 } 1306 1307 /* Take PHY out of power down mode. */ 1308 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1309 re_gmii_writereg(dev, 1, 0x1f, 0); 1310 re_gmii_writereg(dev, 1, 0x0e, 0); 1311 } 1312 1313 /* Do MII setup */ 1314 if (mii_phy_probe(dev, &sc->rl_miibus, 1315 re_ifmedia_upd, re_ifmedia_sts)) { 1316 device_printf(dev, "MII without any phy!\n"); 1317 error = ENXIO; 1318 goto fail; 1319 } 1320 1321 ifp->if_softc = sc; 1322 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1324 ifp->if_ioctl = re_ioctl; 1325 ifp->if_start = re_start; 1326 ifp->if_hwassist = RE_CSUM_FEATURES; 1327 ifp->if_capabilities = IFCAP_HWCSUM; 1328 ifp->if_capenable = ifp->if_capabilities; 1329 ifp->if_init = re_init; 1330 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1331 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1332 IFQ_SET_READY(&ifp->if_snd); 1333 1334 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1335 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1336 1337 /* 1338 * XXX 1339 * Still have no idea how to make TSO work on 8168C, 8168CP, 1340 * 8111C and 8111CP. 1341 */ 1342 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1343 ifp->if_hwassist |= CSUM_TSO; 1344 ifp->if_capabilities |= IFCAP_TSO4; 1345 } 1346 1347 /* 1348 * Call MI attach routine. 1349 */ 1350 ether_ifattach(ifp, eaddr); 1351 1352 /* VLAN capability setup */ 1353 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1354 if (ifp->if_capabilities & IFCAP_HWCSUM) 1355 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1356 /* Enable WOL if PM is supported. */ 1357 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1358 ifp->if_capabilities |= IFCAP_WOL; 1359 ifp->if_capenable = ifp->if_capabilities; 1360 /* 1361 * Don't enable TSO by default. Under certain 1362 * circumtances the controller generated corrupted 1363 * packets in TSO size. 1364 */ 1365 ifp->if_hwassist &= ~CSUM_TSO; 1366 ifp->if_capenable &= ~IFCAP_TSO4; 1367#ifdef DEVICE_POLLING 1368 ifp->if_capabilities |= IFCAP_POLLING; 1369#endif 1370 /* 1371 * Tell the upper layer(s) we support long frames. 1372 * Must appear after the call to ether_ifattach() because 1373 * ether_ifattach() sets ifi_hdrlen to the default value. 1374 */ 1375 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1376 1377#ifdef RE_DIAG 1378 /* 1379 * Perform hardware diagnostic on the original RTL8169. 1380 * Some 32-bit cards were incorrectly wired and would 1381 * malfunction if plugged into a 64-bit slot. 1382 */ 1383 1384 if (hwrev == RL_HWREV_8169) { 1385 error = re_diag(sc); 1386 if (error) { 1387 device_printf(dev, 1388 "attach aborted due to hardware diag failure\n"); 1389 ether_ifdetach(ifp); 1390 goto fail; 1391 } 1392 } 1393#endif 1394 1395 /* Hook interrupt last to avoid having to lock softc */ 1396 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1397 error = bus_setup_intr(dev, sc->rl_irq[0], 1398 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1399 &sc->rl_intrhand[0]); 1400 else { 1401 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1402 error = bus_setup_intr(dev, sc->rl_irq[i], 1403 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1404 &sc->rl_intrhand[i]); 1405 if (error != 0) 1406 break; 1407 } 1408 } 1409 if (error) { 1410 device_printf(dev, "couldn't set up irq\n"); 1411 ether_ifdetach(ifp); 1412 } 1413 1414fail: 1415 1416 if (error) 1417 re_detach(dev); 1418 1419 return (error); 1420} 1421 1422/* 1423 * Shutdown hardware and free up resources. This can be called any 1424 * time after the mutex has been initialized. It is called in both 1425 * the error case in attach and the normal detach case so it needs 1426 * to be careful about only freeing resources that have actually been 1427 * allocated. 1428 */ 1429static int 1430re_detach(device_t dev) 1431{ 1432 struct rl_softc *sc; 1433 struct ifnet *ifp; 1434 int i, rid; 1435 1436 sc = device_get_softc(dev); 1437 ifp = sc->rl_ifp; 1438 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1439 1440 /* These should only be active if attach succeeded */ 1441 if (device_is_attached(dev)) { 1442#ifdef DEVICE_POLLING 1443 if (ifp->if_capenable & IFCAP_POLLING) 1444 ether_poll_deregister(ifp); 1445#endif 1446 RL_LOCK(sc); 1447#if 0 1448 sc->suspended = 1; 1449#endif 1450 re_stop(sc); 1451 RL_UNLOCK(sc); 1452 callout_drain(&sc->rl_stat_callout); 1453 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1454 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1455 /* 1456 * Force off the IFF_UP flag here, in case someone 1457 * still had a BPF descriptor attached to this 1458 * interface. If they do, ether_ifdetach() will cause 1459 * the BPF code to try and clear the promisc mode 1460 * flag, which will bubble down to re_ioctl(), 1461 * which will try to call re_init() again. This will 1462 * turn the NIC back on and restart the MII ticker, 1463 * which will panic the system when the kernel tries 1464 * to invoke the re_tick() function that isn't there 1465 * anymore. 1466 */ 1467 ifp->if_flags &= ~IFF_UP; 1468 ether_ifdetach(ifp); 1469 } 1470 if (sc->rl_miibus) 1471 device_delete_child(dev, sc->rl_miibus); 1472 bus_generic_detach(dev); 1473 1474 /* 1475 * The rest is resource deallocation, so we should already be 1476 * stopped here. 1477 */ 1478 1479 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1480 if (sc->rl_intrhand[i] != NULL) { 1481 bus_teardown_intr(dev, sc->rl_irq[i], 1482 sc->rl_intrhand[i]); 1483 sc->rl_intrhand[i] = NULL; 1484 } 1485 } 1486 if (ifp != NULL) 1487 if_free(ifp); 1488 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1489 if (sc->rl_irq[0] != NULL) { 1490 bus_release_resource(dev, SYS_RES_IRQ, 0, 1491 sc->rl_irq[0]); 1492 sc->rl_irq[0] = NULL; 1493 } 1494 } else { 1495 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1496 if (sc->rl_irq[i] != NULL) { 1497 bus_release_resource(dev, SYS_RES_IRQ, rid, 1498 sc->rl_irq[i]); 1499 sc->rl_irq[i] = NULL; 1500 } 1501 } 1502 pci_release_msi(dev); 1503 } 1504 if (sc->rl_res) 1505 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1506 sc->rl_res); 1507 1508 /* Unload and free the RX DMA ring memory and map */ 1509 1510 if (sc->rl_ldata.rl_rx_list_tag) { 1511 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1512 sc->rl_ldata.rl_rx_list_map); 1513 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1514 sc->rl_ldata.rl_rx_list, 1515 sc->rl_ldata.rl_rx_list_map); 1516 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1517 } 1518 1519 /* Unload and free the TX DMA ring memory and map */ 1520 1521 if (sc->rl_ldata.rl_tx_list_tag) { 1522 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1523 sc->rl_ldata.rl_tx_list_map); 1524 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1525 sc->rl_ldata.rl_tx_list, 1526 sc->rl_ldata.rl_tx_list_map); 1527 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1528 } 1529 1530 /* Destroy all the RX and TX buffer maps */ 1531 1532 if (sc->rl_ldata.rl_tx_mtag) { 1533 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1534 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1535 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1536 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1537 } 1538 if (sc->rl_ldata.rl_rx_mtag) { 1539 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1540 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1541 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1542 if (sc->rl_ldata.rl_rx_sparemap) 1543 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1544 sc->rl_ldata.rl_rx_sparemap); 1545 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1546 } 1547 1548 /* Unload and free the stats buffer and map */ 1549 1550 if (sc->rl_ldata.rl_stag) { 1551 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1552 sc->rl_ldata.rl_rx_list_map); 1553 bus_dmamem_free(sc->rl_ldata.rl_stag, 1554 sc->rl_ldata.rl_stats, 1555 sc->rl_ldata.rl_smap); 1556 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1557 } 1558 1559 if (sc->rl_parent_tag) 1560 bus_dma_tag_destroy(sc->rl_parent_tag); 1561 1562 mtx_destroy(&sc->rl_mtx); 1563 1564 return (0); 1565} 1566 1567static __inline void 1568re_discard_rxbuf(struct rl_softc *sc, int idx) 1569{ 1570 struct rl_desc *desc; 1571 struct rl_rxdesc *rxd; 1572 uint32_t cmdstat; 1573 1574 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1575 desc = &sc->rl_ldata.rl_rx_list[idx]; 1576 desc->rl_vlanctl = 0; 1577 cmdstat = rxd->rx_size; 1578 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1579 cmdstat |= RL_RDESC_CMD_EOR; 1580 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1581} 1582 1583static int 1584re_newbuf(struct rl_softc *sc, int idx) 1585{ 1586 struct mbuf *m; 1587 struct rl_rxdesc *rxd; 1588 bus_dma_segment_t segs[1]; 1589 bus_dmamap_t map; 1590 struct rl_desc *desc; 1591 uint32_t cmdstat; 1592 int error, nsegs; 1593 1594 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1595 if (m == NULL) 1596 return (ENOBUFS); 1597 1598 m->m_len = m->m_pkthdr.len = MCLBYTES; 1599#ifdef RE_FIXUP_RX 1600 /* 1601 * This is part of an evil trick to deal with non-x86 platforms. 1602 * The RealTek chip requires RX buffers to be aligned on 64-bit 1603 * boundaries, but that will hose non-x86 machines. To get around 1604 * this, we leave some empty space at the start of each buffer 1605 * and for non-x86 hosts, we copy the buffer back six bytes 1606 * to achieve word alignment. This is slightly more efficient 1607 * than allocating a new buffer, copying the contents, and 1608 * discarding the old buffer. 1609 */ 1610 m_adj(m, RE_ETHER_ALIGN); 1611#endif 1612 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1613 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1614 if (error != 0) { 1615 m_freem(m); 1616 return (ENOBUFS); 1617 } 1618 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1619 1620 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1621 if (rxd->rx_m != NULL) { 1622 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1623 BUS_DMASYNC_POSTREAD); 1624 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1625 } 1626 1627 rxd->rx_m = m; 1628 map = rxd->rx_dmamap; 1629 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1630 rxd->rx_size = segs[0].ds_len; 1631 sc->rl_ldata.rl_rx_sparemap = map; 1632 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1633 BUS_DMASYNC_PREREAD); 1634 1635 desc = &sc->rl_ldata.rl_rx_list[idx]; 1636 desc->rl_vlanctl = 0; 1637 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1638 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1639 cmdstat = segs[0].ds_len; 1640 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1641 cmdstat |= RL_RDESC_CMD_EOR; 1642 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1643 1644 return (0); 1645} 1646 1647#ifdef RE_FIXUP_RX 1648static __inline void 1649re_fixup_rx(struct mbuf *m) 1650{ 1651 int i; 1652 uint16_t *src, *dst; 1653 1654 src = mtod(m, uint16_t *); 1655 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1656 1657 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1658 *dst++ = *src++; 1659 1660 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1661} 1662#endif 1663 1664static int 1665re_tx_list_init(struct rl_softc *sc) 1666{ 1667 struct rl_desc *desc; 1668 int i; 1669 1670 RL_LOCK_ASSERT(sc); 1671 1672 bzero(sc->rl_ldata.rl_tx_list, 1673 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1674 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1675 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1676 /* Set EOR. */ 1677 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1678 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1679 1680 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1681 sc->rl_ldata.rl_tx_list_map, 1682 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1683 1684 sc->rl_ldata.rl_tx_prodidx = 0; 1685 sc->rl_ldata.rl_tx_considx = 0; 1686 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1687 1688 return (0); 1689} 1690 1691static int 1692re_rx_list_init(struct rl_softc *sc) 1693{ 1694 int error, i; 1695 1696 bzero(sc->rl_ldata.rl_rx_list, 1697 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1698 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1699 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1700 if ((error = re_newbuf(sc, i)) != 0) 1701 return (error); 1702 } 1703 1704 /* Flush the RX descriptors */ 1705 1706 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1707 sc->rl_ldata.rl_rx_list_map, 1708 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1709 1710 sc->rl_ldata.rl_rx_prodidx = 0; 1711 sc->rl_head = sc->rl_tail = NULL; 1712 1713 return (0); 1714} 1715 1716/* 1717 * RX handler for C+ and 8169. For the gigE chips, we support 1718 * the reception of jumbo frames that have been fragmented 1719 * across multiple 2K mbuf cluster buffers. 1720 */ 1721static int 1722re_rxeof(struct rl_softc *sc) 1723{ 1724 struct mbuf *m; 1725 struct ifnet *ifp; 1726 int i, total_len; 1727 struct rl_desc *cur_rx; 1728 u_int32_t rxstat, rxvlan; 1729 int maxpkt = 16; 1730 1731 RL_LOCK_ASSERT(sc); 1732 1733 ifp = sc->rl_ifp; 1734 1735 /* Invalidate the descriptor memory */ 1736 1737 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1738 sc->rl_ldata.rl_rx_list_map, 1739 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1740 1741 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1742 i = RL_RX_DESC_NXT(sc, i)) { 1743 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1744 rxstat = le32toh(cur_rx->rl_cmdstat); 1745 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1746 break; 1747 total_len = rxstat & sc->rl_rxlenmask; 1748 rxvlan = le32toh(cur_rx->rl_vlanctl); 1749 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1750 1751 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1752 if (re_newbuf(sc, i) != 0) { 1753 /* 1754 * If this is part of a multi-fragment packet, 1755 * discard all the pieces. 1756 */ 1757 if (sc->rl_head != NULL) { 1758 m_freem(sc->rl_head); 1759 sc->rl_head = sc->rl_tail = NULL; 1760 } 1761 re_discard_rxbuf(sc, i); 1762 continue; 1763 } 1764 m->m_len = RE_RX_DESC_BUFLEN; 1765 if (sc->rl_head == NULL) 1766 sc->rl_head = sc->rl_tail = m; 1767 else { 1768 m->m_flags &= ~M_PKTHDR; 1769 sc->rl_tail->m_next = m; 1770 sc->rl_tail = m; 1771 } 1772 continue; 1773 } 1774 1775 /* 1776 * NOTE: for the 8139C+, the frame length field 1777 * is always 12 bits in size, but for the gigE chips, 1778 * it is 13 bits (since the max RX frame length is 16K). 1779 * Unfortunately, all 32 bits in the status word 1780 * were already used, so to make room for the extra 1781 * length bit, RealTek took out the 'frame alignment 1782 * error' bit and shifted the other status bits 1783 * over one slot. The OWN, EOR, FS and LS bits are 1784 * still in the same places. We have already extracted 1785 * the frame length and checked the OWN bit, so rather 1786 * than using an alternate bit mapping, we shift the 1787 * status bits one space to the right so we can evaluate 1788 * them using the 8169 status as though it was in the 1789 * same format as that of the 8139C+. 1790 */ 1791 if (sc->rl_type == RL_8169) 1792 rxstat >>= 1; 1793 1794 /* 1795 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1796 * set, but if CRC is clear, it will still be a valid frame. 1797 */ 1798 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1799 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1800 ifp->if_ierrors++; 1801 /* 1802 * If this is part of a multi-fragment packet, 1803 * discard all the pieces. 1804 */ 1805 if (sc->rl_head != NULL) { 1806 m_freem(sc->rl_head); 1807 sc->rl_head = sc->rl_tail = NULL; 1808 } 1809 re_discard_rxbuf(sc, i); 1810 continue; 1811 } 1812 1813 /* 1814 * If allocating a replacement mbuf fails, 1815 * reload the current one. 1816 */ 1817 1818 if (re_newbuf(sc, i) != 0) { 1819 ifp->if_iqdrops++; 1820 if (sc->rl_head != NULL) { 1821 m_freem(sc->rl_head); 1822 sc->rl_head = sc->rl_tail = NULL; 1823 } 1824 re_discard_rxbuf(sc, i); 1825 continue; 1826 } 1827 1828 if (sc->rl_head != NULL) { 1829 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1830 if (m->m_len == 0) 1831 m->m_len = RE_RX_DESC_BUFLEN; 1832 /* 1833 * Special case: if there's 4 bytes or less 1834 * in this buffer, the mbuf can be discarded: 1835 * the last 4 bytes is the CRC, which we don't 1836 * care about anyway. 1837 */ 1838 if (m->m_len <= ETHER_CRC_LEN) { 1839 sc->rl_tail->m_len -= 1840 (ETHER_CRC_LEN - m->m_len); 1841 m_freem(m); 1842 } else { 1843 m->m_len -= ETHER_CRC_LEN; 1844 m->m_flags &= ~M_PKTHDR; 1845 sc->rl_tail->m_next = m; 1846 } 1847 m = sc->rl_head; 1848 sc->rl_head = sc->rl_tail = NULL; 1849 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1850 } else 1851 m->m_pkthdr.len = m->m_len = 1852 (total_len - ETHER_CRC_LEN); 1853 1854#ifdef RE_FIXUP_RX 1855 re_fixup_rx(m); 1856#endif 1857 ifp->if_ipackets++; 1858 m->m_pkthdr.rcvif = ifp; 1859 1860 /* Do RX checksumming if enabled */ 1861 1862 if (ifp->if_capenable & IFCAP_RXCSUM) { 1863 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1864 /* Check IP header checksum */ 1865 if (rxstat & RL_RDESC_STAT_PROTOID) 1866 m->m_pkthdr.csum_flags |= 1867 CSUM_IP_CHECKED; 1868 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1869 m->m_pkthdr.csum_flags |= 1870 CSUM_IP_VALID; 1871 1872 /* Check TCP/UDP checksum */ 1873 if ((RL_TCPPKT(rxstat) && 1874 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1875 (RL_UDPPKT(rxstat) && 1876 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1877 m->m_pkthdr.csum_flags |= 1878 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1879 m->m_pkthdr.csum_data = 0xffff; 1880 } 1881 } else { 1882 /* 1883 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1884 */ 1885 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1886 (rxvlan & RL_RDESC_IPV4)) 1887 m->m_pkthdr.csum_flags |= 1888 CSUM_IP_CHECKED; 1889 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1890 (rxvlan & RL_RDESC_IPV4)) 1891 m->m_pkthdr.csum_flags |= 1892 CSUM_IP_VALID; 1893 if (((rxstat & RL_RDESC_STAT_TCP) && 1894 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1895 ((rxstat & RL_RDESC_STAT_UDP) && 1896 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1897 m->m_pkthdr.csum_flags |= 1898 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1899 m->m_pkthdr.csum_data = 0xffff; 1900 } 1901 } 1902 } 1903 maxpkt--; 1904 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1905 m->m_pkthdr.ether_vtag = 1906 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1907 m->m_flags |= M_VLANTAG; 1908 } 1909 RL_UNLOCK(sc); 1910 (*ifp->if_input)(ifp, m); 1911 RL_LOCK(sc); 1912 } 1913 1914 /* Flush the RX DMA ring */ 1915 1916 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1917 sc->rl_ldata.rl_rx_list_map, 1918 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1919 1920 sc->rl_ldata.rl_rx_prodidx = i; 1921 1922 if (maxpkt) 1923 return(EAGAIN); 1924 1925 return(0); 1926} 1927 1928static void 1929re_txeof(struct rl_softc *sc) 1930{ 1931 struct ifnet *ifp; 1932 struct rl_txdesc *txd; 1933 u_int32_t txstat; 1934 int cons; 1935 1936 cons = sc->rl_ldata.rl_tx_considx; 1937 if (cons == sc->rl_ldata.rl_tx_prodidx) 1938 return; 1939 1940 ifp = sc->rl_ifp; 1941 /* Invalidate the TX descriptor list */ 1942 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1943 sc->rl_ldata.rl_tx_list_map, 1944 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1945 1946 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1947 cons = RL_TX_DESC_NXT(sc, cons)) { 1948 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1949 if (txstat & RL_TDESC_STAT_OWN) 1950 break; 1951 /* 1952 * We only stash mbufs in the last descriptor 1953 * in a fragment chain, which also happens to 1954 * be the only place where the TX status bits 1955 * are valid. 1956 */ 1957 if (txstat & RL_TDESC_CMD_EOF) { 1958 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1959 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1960 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1961 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1962 txd->tx_dmamap); 1963 KASSERT(txd->tx_m != NULL, 1964 ("%s: freeing NULL mbufs!", __func__)); 1965 m_freem(txd->tx_m); 1966 txd->tx_m = NULL; 1967 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1968 RL_TDESC_STAT_COLCNT)) 1969 ifp->if_collisions++; 1970 if (txstat & RL_TDESC_STAT_TXERRSUM) 1971 ifp->if_oerrors++; 1972 else 1973 ifp->if_opackets++; 1974 } 1975 sc->rl_ldata.rl_tx_free++; 1976 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1977 } 1978 sc->rl_ldata.rl_tx_considx = cons; 1979 1980 /* No changes made to the TX ring, so no flush needed */ 1981 1982 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1983 /* 1984 * Some chips will ignore a second TX request issued 1985 * while an existing transmission is in progress. If 1986 * the transmitter goes idle but there are still 1987 * packets waiting to be sent, we need to restart the 1988 * channel here to flush them out. This only seems to 1989 * be required with the PCIe devices. 1990 */ 1991 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1992 1993#ifdef RE_TX_MODERATION 1994 /* 1995 * If not all descriptors have been reaped yet, reload 1996 * the timer so that we will eventually get another 1997 * interrupt that will cause us to re-enter this routine. 1998 * This is done in case the transmitter has gone idle. 1999 */ 2000 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2001#endif 2002 } else 2003 sc->rl_watchdog_timer = 0; 2004} 2005 2006static void 2007re_tick(void *xsc) 2008{ 2009 struct rl_softc *sc; 2010 struct mii_data *mii; 2011 struct ifnet *ifp; 2012 2013 sc = xsc; 2014 ifp = sc->rl_ifp; 2015 2016 RL_LOCK_ASSERT(sc); 2017 2018 re_watchdog(sc); 2019 2020 mii = device_get_softc(sc->rl_miibus); 2021 mii_tick(mii); 2022 if ((sc->rl_flags & RL_FLAG_LINK) != 0) { 2023 if (!(mii->mii_media_status & IFM_ACTIVE)) 2024 sc->rl_flags &= ~RL_FLAG_LINK; 2025 } else { 2026 if (mii->mii_media_status & IFM_ACTIVE && 2027 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2028 sc->rl_flags |= RL_FLAG_LINK; 2029 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2030 taskqueue_enqueue_fast(taskqueue_fast, 2031 &sc->rl_txtask); 2032 } 2033 } 2034 2035 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2036} 2037 2038#ifdef DEVICE_POLLING 2039static void 2040re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2041{ 2042 struct rl_softc *sc = ifp->if_softc; 2043 2044 RL_LOCK(sc); 2045 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2046 re_poll_locked(ifp, cmd, count); 2047 RL_UNLOCK(sc); 2048} 2049 2050static void 2051re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2052{ 2053 struct rl_softc *sc = ifp->if_softc; 2054 2055 RL_LOCK_ASSERT(sc); 2056 2057 sc->rxcycles = count; 2058 re_rxeof(sc); 2059 re_txeof(sc); 2060 2061 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2062 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2063 2064 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2065 u_int16_t status; 2066 2067 status = CSR_READ_2(sc, RL_ISR); 2068 if (status == 0xffff) 2069 return; 2070 if (status) 2071 CSR_WRITE_2(sc, RL_ISR, status); 2072 2073 /* 2074 * XXX check behaviour on receiver stalls. 2075 */ 2076 2077 if (status & RL_ISR_SYSTEM_ERR) { 2078 re_reset(sc); 2079 re_init_locked(sc); 2080 } 2081 } 2082} 2083#endif /* DEVICE_POLLING */ 2084 2085static int 2086re_intr(void *arg) 2087{ 2088 struct rl_softc *sc; 2089 uint16_t status; 2090 2091 sc = arg; 2092 2093 status = CSR_READ_2(sc, RL_ISR); 2094 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2095 return (FILTER_STRAY); 2096 CSR_WRITE_2(sc, RL_IMR, 0); 2097 2098 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2099 2100 return (FILTER_HANDLED); 2101} 2102 2103static void 2104re_int_task(void *arg, int npending) 2105{ 2106 struct rl_softc *sc; 2107 struct ifnet *ifp; 2108 u_int16_t status; 2109 int rval = 0; 2110 2111 sc = arg; 2112 ifp = sc->rl_ifp; 2113 2114 RL_LOCK(sc); 2115 2116 status = CSR_READ_2(sc, RL_ISR); 2117 CSR_WRITE_2(sc, RL_ISR, status); 2118 2119 if (sc->suspended || 2120 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2121 RL_UNLOCK(sc); 2122 return; 2123 } 2124 2125#ifdef DEVICE_POLLING 2126 if (ifp->if_capenable & IFCAP_POLLING) { 2127 RL_UNLOCK(sc); 2128 return; 2129 } 2130#endif 2131 2132 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2133 rval = re_rxeof(sc); 2134 2135 if (status & ( 2136#ifdef RE_TX_MODERATION 2137 RL_ISR_TIMEOUT_EXPIRED| 2138#else 2139 RL_ISR_TX_OK| 2140#endif 2141 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2142 re_txeof(sc); 2143 2144 if (status & RL_ISR_SYSTEM_ERR) { 2145 re_reset(sc); 2146 re_init_locked(sc); 2147 } 2148 2149 if (status & RL_ISR_LINKCHG) { 2150 callout_stop(&sc->rl_stat_callout); 2151 re_tick(sc); 2152 } 2153 2154 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2155 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2156 2157 RL_UNLOCK(sc); 2158 2159 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2160 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2161 return; 2162 } 2163 2164 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2165} 2166 2167static int 2168re_encap(struct rl_softc *sc, struct mbuf **m_head) 2169{ 2170 struct rl_txdesc *txd, *txd_last; 2171 bus_dma_segment_t segs[RL_NTXSEGS]; 2172 bus_dmamap_t map; 2173 struct mbuf *m_new; 2174 struct rl_desc *desc; 2175 int nsegs, prod; 2176 int i, error, ei, si; 2177 int padlen; 2178 uint32_t cmdstat, csum_flags, vlanctl; 2179 2180 RL_LOCK_ASSERT(sc); 2181 M_ASSERTPKTHDR((*m_head)); 2182 2183 /* 2184 * With some of the RealTek chips, using the checksum offload 2185 * support in conjunction with the autopadding feature results 2186 * in the transmission of corrupt frames. For example, if we 2187 * need to send a really small IP fragment that's less than 60 2188 * bytes in size, and IP header checksumming is enabled, the 2189 * resulting ethernet frame that appears on the wire will 2190 * have garbled payload. To work around this, if TX IP checksum 2191 * offload is enabled, we always manually pad short frames out 2192 * to the minimum ethernet frame size. 2193 */ 2194 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2195 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2196 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2197 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2198 if (M_WRITABLE(*m_head) == 0) { 2199 /* Get a writable copy. */ 2200 m_new = m_dup(*m_head, M_DONTWAIT); 2201 m_freem(*m_head); 2202 if (m_new == NULL) { 2203 *m_head = NULL; 2204 return (ENOBUFS); 2205 } 2206 *m_head = m_new; 2207 } 2208 if ((*m_head)->m_next != NULL || 2209 M_TRAILINGSPACE(*m_head) < padlen) { 2210 m_new = m_defrag(*m_head, M_DONTWAIT); 2211 if (m_new == NULL) { 2212 m_freem(*m_head); 2213 *m_head = NULL; 2214 return (ENOBUFS); 2215 } 2216 } else 2217 m_new = *m_head; 2218 2219 /* 2220 * Manually pad short frames, and zero the pad space 2221 * to avoid leaking data. 2222 */ 2223 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2224 m_new->m_pkthdr.len += padlen; 2225 m_new->m_len = m_new->m_pkthdr.len; 2226 *m_head = m_new; 2227 } 2228 2229 prod = sc->rl_ldata.rl_tx_prodidx; 2230 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2231 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2232 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2233 if (error == EFBIG) { 2234 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2235 if (m_new == NULL) { 2236 m_freem(*m_head); 2237 *m_head = NULL; 2238 return (ENOBUFS); 2239 } 2240 *m_head = m_new; 2241 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2242 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2243 if (error != 0) { 2244 m_freem(*m_head); 2245 *m_head = NULL; 2246 return (error); 2247 } 2248 } else if (error != 0) 2249 return (error); 2250 if (nsegs == 0) { 2251 m_freem(*m_head); 2252 *m_head = NULL; 2253 return (EIO); 2254 } 2255 2256 /* Check for number of available descriptors. */ 2257 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2258 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2259 return (ENOBUFS); 2260 } 2261 2262 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2263 BUS_DMASYNC_PREWRITE); 2264 2265 /* 2266 * Set up checksum offload. Note: checksum offload bits must 2267 * appear in all descriptors of a multi-descriptor transmit 2268 * attempt. This is according to testing done with an 8169 2269 * chip. This is a requirement. 2270 */ 2271 vlanctl = 0; 2272 csum_flags = 0; 2273 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2274 csum_flags = RL_TDESC_CMD_LGSEND | 2275 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2276 RL_TDESC_CMD_MSSVAL_SHIFT); 2277 else { 2278 /* 2279 * Unconditionally enable IP checksum if TCP or UDP 2280 * checksum is required. Otherwise, TCP/UDP checksum 2281 * does't make effects. 2282 */ 2283 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2284 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2285 csum_flags |= RL_TDESC_CMD_IPCSUM; 2286 if (((*m_head)->m_pkthdr.csum_flags & 2287 CSUM_TCP) != 0) 2288 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2289 if (((*m_head)->m_pkthdr.csum_flags & 2290 CSUM_UDP) != 0) 2291 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2292 } else { 2293 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2294 if (((*m_head)->m_pkthdr.csum_flags & 2295 CSUM_TCP) != 0) 2296 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2297 if (((*m_head)->m_pkthdr.csum_flags & 2298 CSUM_UDP) != 0) 2299 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2300 } 2301 } 2302 } 2303 2304 /* 2305 * Set up hardware VLAN tagging. Note: vlan tag info must 2306 * appear in all descriptors of a multi-descriptor 2307 * transmission attempt. 2308 */ 2309 if ((*m_head)->m_flags & M_VLANTAG) 2310 vlanctl |= htons((*m_head)->m_pkthdr.ether_vtag) | 2311 RL_TDESC_VLANCTL_TAG; 2312 2313 si = prod; 2314 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2315 desc = &sc->rl_ldata.rl_tx_list[prod]; 2316 desc->rl_vlanctl = htole32(vlanctl); 2317 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2318 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2319 cmdstat = segs[i].ds_len; 2320 if (i != 0) 2321 cmdstat |= RL_TDESC_CMD_OWN; 2322 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2323 cmdstat |= RL_TDESC_CMD_EOR; 2324 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2325 sc->rl_ldata.rl_tx_free--; 2326 } 2327 /* Update producer index. */ 2328 sc->rl_ldata.rl_tx_prodidx = prod; 2329 2330 /* Set EOF on the last descriptor. */ 2331 ei = RL_TX_DESC_PRV(sc, prod); 2332 desc = &sc->rl_ldata.rl_tx_list[ei]; 2333 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2334 2335 desc = &sc->rl_ldata.rl_tx_list[si]; 2336 /* Set SOF and transfer ownership of packet to the chip. */ 2337 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2338 2339 /* 2340 * Insure that the map for this transmission 2341 * is placed at the array index of the last descriptor 2342 * in this chain. (Swap last and first dmamaps.) 2343 */ 2344 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2345 map = txd->tx_dmamap; 2346 txd->tx_dmamap = txd_last->tx_dmamap; 2347 txd_last->tx_dmamap = map; 2348 txd_last->tx_m = *m_head; 2349 2350 return (0); 2351} 2352 2353static void 2354re_tx_task(void *arg, int npending) 2355{ 2356 struct ifnet *ifp; 2357 2358 ifp = arg; 2359 re_start(ifp); 2360} 2361 2362/* 2363 * Main transmit routine for C+ and gigE NICs. 2364 */ 2365static void 2366re_start(struct ifnet *ifp) 2367{ 2368 struct rl_softc *sc; 2369 struct mbuf *m_head; 2370 int queued; 2371 2372 sc = ifp->if_softc; 2373 2374 RL_LOCK(sc); 2375 2376 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2377 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2378 RL_UNLOCK(sc); 2379 return; 2380 } 2381 2382 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2383 sc->rl_ldata.rl_tx_free > 1;) { 2384 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2385 if (m_head == NULL) 2386 break; 2387 2388 if (re_encap(sc, &m_head) != 0) { 2389 if (m_head == NULL) 2390 break; 2391 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2392 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2393 break; 2394 } 2395 2396 /* 2397 * If there's a BPF listener, bounce a copy of this frame 2398 * to him. 2399 */ 2400 ETHER_BPF_MTAP(ifp, m_head); 2401 2402 queued++; 2403 } 2404 2405 if (queued == 0) { 2406#ifdef RE_TX_MODERATION 2407 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2408 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2409#endif 2410 RL_UNLOCK(sc); 2411 return; 2412 } 2413 2414 /* Flush the TX descriptors */ 2415 2416 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2417 sc->rl_ldata.rl_tx_list_map, 2418 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2419 2420 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2421 2422#ifdef RE_TX_MODERATION 2423 /* 2424 * Use the countdown timer for interrupt moderation. 2425 * 'TX done' interrupts are disabled. Instead, we reset the 2426 * countdown timer, which will begin counting until it hits 2427 * the value in the TIMERINT register, and then trigger an 2428 * interrupt. Each time we write to the TIMERCNT register, 2429 * the timer count is reset to 0. 2430 */ 2431 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2432#endif 2433 2434 /* 2435 * Set a timeout in case the chip goes out to lunch. 2436 */ 2437 sc->rl_watchdog_timer = 5; 2438 2439 RL_UNLOCK(sc); 2440} 2441 2442static void 2443re_init(void *xsc) 2444{ 2445 struct rl_softc *sc = xsc; 2446 2447 RL_LOCK(sc); 2448 re_init_locked(sc); 2449 RL_UNLOCK(sc); 2450} 2451 2452static void 2453re_init_locked(struct rl_softc *sc) 2454{ 2455 struct ifnet *ifp = sc->rl_ifp; 2456 struct mii_data *mii; 2457 u_int32_t rxcfg = 0; 2458 uint16_t cfg; 2459 union { 2460 uint32_t align_dummy; 2461 u_char eaddr[ETHER_ADDR_LEN]; 2462 } eaddr; 2463 2464 RL_LOCK_ASSERT(sc); 2465 2466 mii = device_get_softc(sc->rl_miibus); 2467 2468 /* 2469 * Cancel pending I/O and free all RX/TX buffers. 2470 */ 2471 re_stop(sc); 2472 2473 /* 2474 * Enable C+ RX and TX mode, as well as VLAN stripping and 2475 * RX checksum offload. We must configure the C+ register 2476 * before all others. 2477 */ 2478 cfg = RL_CPLUSCMD_PCI_MRW; 2479 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2480 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2481 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2482 cfg |= RL_CPLUSCMD_VLANSTRIP; 2483 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2484 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2485 /* XXX magic. */ 2486 cfg |= 0x0001; 2487 } else 2488 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2489 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2490 /* 2491 * Disable TSO if interface MTU size is greater than MSS 2492 * allowed in controller. 2493 */ 2494 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2495 ifp->if_capenable &= ~IFCAP_TSO4; 2496 ifp->if_hwassist &= ~CSUM_TSO; 2497 } 2498 2499 /* 2500 * Init our MAC address. Even though the chipset 2501 * documentation doesn't mention it, we need to enter "Config 2502 * register write enable" mode to modify the ID registers. 2503 */ 2504 /* Copy MAC address on stack to align. */ 2505 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2506 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2507 CSR_WRITE_4(sc, RL_IDR0, 2508 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2509 CSR_WRITE_4(sc, RL_IDR4, 2510 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2511 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2512 2513 /* 2514 * For C+ mode, initialize the RX descriptors and mbufs. 2515 */ 2516 re_rx_list_init(sc); 2517 re_tx_list_init(sc); 2518 2519 /* 2520 * Load the addresses of the RX and TX lists into the chip. 2521 */ 2522 2523 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2524 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2525 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2526 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2527 2528 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2529 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2530 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2531 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2532 2533 /* 2534 * Enable transmit and receive. 2535 */ 2536 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2537 2538 /* 2539 * Set the initial TX and RX configuration. 2540 */ 2541 if (sc->rl_testmode) { 2542 if (sc->rl_type == RL_8169) 2543 CSR_WRITE_4(sc, RL_TXCFG, 2544 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2545 else 2546 CSR_WRITE_4(sc, RL_TXCFG, 2547 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2548 } else 2549 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2550 2551 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2552 2553 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2554 2555 /* Set the individual bit to receive frames for this host only. */ 2556 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2557 rxcfg |= RL_RXCFG_RX_INDIV; 2558 2559 /* If we want promiscuous mode, set the allframes bit. */ 2560 if (ifp->if_flags & IFF_PROMISC) 2561 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2562 else 2563 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2564 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2565 2566 /* 2567 * Set capture broadcast bit to capture broadcast frames. 2568 */ 2569 if (ifp->if_flags & IFF_BROADCAST) 2570 rxcfg |= RL_RXCFG_RX_BROAD; 2571 else 2572 rxcfg &= ~RL_RXCFG_RX_BROAD; 2573 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2574 2575 /* 2576 * Program the multicast filter, if necessary. 2577 */ 2578 re_setmulti(sc); 2579 2580#ifdef DEVICE_POLLING 2581 /* 2582 * Disable interrupts if we are polling. 2583 */ 2584 if (ifp->if_capenable & IFCAP_POLLING) 2585 CSR_WRITE_2(sc, RL_IMR, 0); 2586 else /* otherwise ... */ 2587#endif 2588 2589 /* 2590 * Enable interrupts. 2591 */ 2592 if (sc->rl_testmode) 2593 CSR_WRITE_2(sc, RL_IMR, 0); 2594 else 2595 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2596 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2597 2598 /* Set initial TX threshold */ 2599 sc->rl_txthresh = RL_TX_THRESH_INIT; 2600 2601 /* Start RX/TX process. */ 2602 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2603#ifdef notdef 2604 /* Enable receiver and transmitter. */ 2605 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2606#endif 2607 2608#ifdef RE_TX_MODERATION 2609 /* 2610 * Initialize the timer interrupt register so that 2611 * a timer interrupt will be generated once the timer 2612 * reaches a certain number of ticks. The timer is 2613 * reloaded on each transmit. This gives us TX interrupt 2614 * moderation, which dramatically improves TX frame rate. 2615 */ 2616 if (sc->rl_type == RL_8169) 2617 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2618 else 2619 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2620#endif 2621 2622 /* 2623 * For 8169 gigE NICs, set the max allowed RX packet 2624 * size so we can receive jumbo frames. 2625 */ 2626 if (sc->rl_type == RL_8169) 2627 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2628 2629 if (sc->rl_testmode) 2630 return; 2631 2632 mii_mediachg(mii); 2633 2634 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2635 2636 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2637 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2638 2639 sc->rl_flags &= ~RL_FLAG_LINK; 2640 sc->rl_watchdog_timer = 0; 2641 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2642} 2643 2644/* 2645 * Set media options. 2646 */ 2647static int 2648re_ifmedia_upd(struct ifnet *ifp) 2649{ 2650 struct rl_softc *sc; 2651 struct mii_data *mii; 2652 2653 sc = ifp->if_softc; 2654 mii = device_get_softc(sc->rl_miibus); 2655 RL_LOCK(sc); 2656 mii_mediachg(mii); 2657 RL_UNLOCK(sc); 2658 2659 return (0); 2660} 2661 2662/* 2663 * Report current media status. 2664 */ 2665static void 2666re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2667{ 2668 struct rl_softc *sc; 2669 struct mii_data *mii; 2670 2671 sc = ifp->if_softc; 2672 mii = device_get_softc(sc->rl_miibus); 2673 2674 RL_LOCK(sc); 2675 mii_pollstat(mii); 2676 RL_UNLOCK(sc); 2677 ifmr->ifm_active = mii->mii_media_active; 2678 ifmr->ifm_status = mii->mii_media_status; 2679} 2680 2681static int 2682re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2683{ 2684 struct rl_softc *sc = ifp->if_softc; 2685 struct ifreq *ifr = (struct ifreq *) data; 2686 struct mii_data *mii; 2687 int error = 0; 2688 2689 switch (command) { 2690 case SIOCSIFMTU: 2691 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2692 error = EINVAL; 2693 break; 2694 } 2695 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2696 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2697 error = EINVAL; 2698 break; 2699 } 2700 RL_LOCK(sc); 2701 if (ifp->if_mtu != ifr->ifr_mtu) 2702 ifp->if_mtu = ifr->ifr_mtu; 2703 if (ifp->if_mtu > RL_TSO_MTU && 2704 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2705 ifp->if_capenable &= ~IFCAP_TSO4; 2706 ifp->if_hwassist &= ~CSUM_TSO; 2707 } 2708 RL_UNLOCK(sc); 2709 break; 2710 case SIOCSIFFLAGS: 2711 RL_LOCK(sc); 2712 if ((ifp->if_flags & IFF_UP) != 0) { 2713 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2714 if (((ifp->if_flags ^ sc->rl_if_flags) 2715 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2716 re_setmulti(sc); 2717 } else 2718 re_init_locked(sc); 2719 } else { 2720 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2721 re_stop(sc); 2722 } 2723 sc->rl_if_flags = ifp->if_flags; 2724 RL_UNLOCK(sc); 2725 break; 2726 case SIOCADDMULTI: 2727 case SIOCDELMULTI: 2728 RL_LOCK(sc); 2729 re_setmulti(sc); 2730 RL_UNLOCK(sc); 2731 break; 2732 case SIOCGIFMEDIA: 2733 case SIOCSIFMEDIA: 2734 mii = device_get_softc(sc->rl_miibus); 2735 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2736 break; 2737 case SIOCSIFCAP: 2738 { 2739 int mask, reinit; 2740 2741 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2742 reinit = 0; 2743#ifdef DEVICE_POLLING 2744 if (mask & IFCAP_POLLING) { 2745 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2746 error = ether_poll_register(re_poll, ifp); 2747 if (error) 2748 return(error); 2749 RL_LOCK(sc); 2750 /* Disable interrupts */ 2751 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2752 ifp->if_capenable |= IFCAP_POLLING; 2753 RL_UNLOCK(sc); 2754 } else { 2755 error = ether_poll_deregister(ifp); 2756 /* Enable interrupts. */ 2757 RL_LOCK(sc); 2758 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2759 ifp->if_capenable &= ~IFCAP_POLLING; 2760 RL_UNLOCK(sc); 2761 } 2762 } 2763#endif /* DEVICE_POLLING */ 2764 if (mask & IFCAP_HWCSUM) { 2765 ifp->if_capenable ^= IFCAP_HWCSUM; 2766 if (ifp->if_capenable & IFCAP_TXCSUM) 2767 ifp->if_hwassist |= RE_CSUM_FEATURES; 2768 else 2769 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2770 reinit = 1; 2771 } 2772 if (mask & IFCAP_VLAN_HWTAGGING) { 2773 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2774 reinit = 1; 2775 } 2776 if (mask & IFCAP_TSO4) { 2777 ifp->if_capenable ^= IFCAP_TSO4; 2778 if ((IFCAP_TSO4 & ifp->if_capenable) && 2779 (IFCAP_TSO4 & ifp->if_capabilities)) 2780 ifp->if_hwassist |= CSUM_TSO; 2781 else 2782 ifp->if_hwassist &= ~CSUM_TSO; 2783 if (ifp->if_mtu > RL_TSO_MTU && 2784 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2785 ifp->if_capenable &= ~IFCAP_TSO4; 2786 ifp->if_hwassist &= ~CSUM_TSO; 2787 } 2788 } 2789 if ((mask & IFCAP_WOL) != 0 && 2790 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2791 if ((mask & IFCAP_WOL_UCAST) != 0) 2792 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2793 if ((mask & IFCAP_WOL_MCAST) != 0) 2794 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2795 if ((mask & IFCAP_WOL_MAGIC) != 0) 2796 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2797 } 2798 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2799 re_init(sc); 2800 VLAN_CAPABILITIES(ifp); 2801 } 2802 break; 2803 default: 2804 error = ether_ioctl(ifp, command, data); 2805 break; 2806 } 2807 2808 return (error); 2809} 2810 2811static void 2812re_watchdog(struct rl_softc *sc) 2813{ 2814 2815 RL_LOCK_ASSERT(sc); 2816 2817 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2818 return; 2819 2820 device_printf(sc->rl_dev, "watchdog timeout\n"); 2821 sc->rl_ifp->if_oerrors++; 2822 2823 re_txeof(sc); 2824 re_rxeof(sc); 2825 re_init_locked(sc); 2826} 2827 2828/* 2829 * Stop the adapter and free any mbufs allocated to the 2830 * RX and TX lists. 2831 */ 2832static void 2833re_stop(struct rl_softc *sc) 2834{ 2835 int i; 2836 struct ifnet *ifp; 2837 struct rl_txdesc *txd; 2838 struct rl_rxdesc *rxd; 2839 2840 RL_LOCK_ASSERT(sc); 2841 2842 ifp = sc->rl_ifp; 2843 2844 sc->rl_watchdog_timer = 0; 2845 callout_stop(&sc->rl_stat_callout); 2846 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2847 2848 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2849 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2850 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2851 2852 if (sc->rl_head != NULL) { 2853 m_freem(sc->rl_head); 2854 sc->rl_head = sc->rl_tail = NULL; 2855 } 2856 2857 /* Free the TX list buffers. */ 2858 2859 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2860 txd = &sc->rl_ldata.rl_tx_desc[i]; 2861 if (txd->tx_m != NULL) { 2862 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2863 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2864 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2865 txd->tx_dmamap); 2866 m_freem(txd->tx_m); 2867 txd->tx_m = NULL; 2868 } 2869 } 2870 2871 /* Free the RX list buffers. */ 2872 2873 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2874 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2875 if (rxd->rx_m != NULL) { 2876 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2877 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2878 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2879 rxd->rx_dmamap); 2880 m_freem(rxd->rx_m); 2881 rxd->rx_m = NULL; 2882 } 2883 } 2884} 2885 2886/* 2887 * Device suspend routine. Stop the interface and save some PCI 2888 * settings in case the BIOS doesn't restore them properly on 2889 * resume. 2890 */ 2891static int 2892re_suspend(device_t dev) 2893{ 2894 struct rl_softc *sc; 2895 2896 sc = device_get_softc(dev); 2897 2898 RL_LOCK(sc); 2899 re_stop(sc); 2900 re_setwol(sc); 2901 sc->suspended = 1; 2902 RL_UNLOCK(sc); 2903 2904 return (0); 2905} 2906 2907/* 2908 * Device resume routine. Restore some PCI settings in case the BIOS 2909 * doesn't, re-enable busmastering, and restart the interface if 2910 * appropriate. 2911 */ 2912static int 2913re_resume(device_t dev) 2914{ 2915 struct rl_softc *sc; 2916 struct ifnet *ifp; 2917 2918 sc = device_get_softc(dev); 2919 2920 RL_LOCK(sc); 2921 2922 ifp = sc->rl_ifp; 2923 2924 /* reinitialize interface if necessary */ 2925 if (ifp->if_flags & IFF_UP) 2926 re_init_locked(sc); 2927 2928 /* 2929 * Clear WOL matching such that normal Rx filtering 2930 * wouldn't interfere with WOL patterns. 2931 */ 2932 re_clrwol(sc); 2933 sc->suspended = 0; 2934 RL_UNLOCK(sc); 2935 2936 return (0); 2937} 2938 2939/* 2940 * Stop all chip I/O so that the kernel's probe routines don't 2941 * get confused by errant DMAs when rebooting. 2942 */ 2943static int 2944re_shutdown(device_t dev) 2945{ 2946 struct rl_softc *sc; 2947 2948 sc = device_get_softc(dev); 2949 2950 RL_LOCK(sc); 2951 re_stop(sc); 2952 /* 2953 * Mark interface as down since otherwise we will panic if 2954 * interrupt comes in later on, which can happen in some 2955 * cases. 2956 */ 2957 sc->rl_ifp->if_flags &= ~IFF_UP; 2958 re_setwol(sc); 2959 RL_UNLOCK(sc); 2960 2961 return (0); 2962} 2963 2964static void 2965re_setwol(struct rl_softc *sc) 2966{ 2967 struct ifnet *ifp; 2968 int pmc; 2969 uint16_t pmstat; 2970 uint8_t v; 2971 2972 RL_LOCK_ASSERT(sc); 2973 2974 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2975 return; 2976 2977 ifp = sc->rl_ifp; 2978 /* Enable config register write. */ 2979 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2980 2981 /* Enable PME. */ 2982 v = CSR_READ_1(sc, RL_CFG1); 2983 v &= ~RL_CFG1_PME; 2984 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2985 v |= RL_CFG1_PME; 2986 CSR_WRITE_1(sc, RL_CFG1, v); 2987 2988 v = CSR_READ_1(sc, RL_CFG3); 2989 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2990 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2991 v |= RL_CFG3_WOL_MAGIC; 2992 CSR_WRITE_1(sc, RL_CFG3, v); 2993 2994 /* Config register write done. */ 2995 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2996 2997 v = CSR_READ_1(sc, RL_CFG5); 2998 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2999 v &= ~RL_CFG5_WOL_LANWAKE; 3000 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3001 v |= RL_CFG5_WOL_UCAST; 3002 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3003 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3004 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3005 v |= RL_CFG5_WOL_LANWAKE; 3006 CSR_WRITE_1(sc, RL_CFG5, v); 3007 3008 /* 3009 * It seems that hardware resets its link speed to 100Mbps in 3010 * power down mode so switching to 100Mbps in driver is not 3011 * needed. 3012 */ 3013 3014 /* Request PME if WOL is requested. */ 3015 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3016 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3017 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3018 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3019 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3020} 3021 3022static void 3023re_clrwol(struct rl_softc *sc) 3024{ 3025 int pmc; 3026 uint8_t v; 3027 3028 RL_LOCK_ASSERT(sc); 3029 3030 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3031 return; 3032 3033 /* Enable config register write. */ 3034 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3035 3036 v = CSR_READ_1(sc, RL_CFG3); 3037 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3038 CSR_WRITE_1(sc, RL_CFG3, v); 3039 3040 /* Config register write done. */ 3041 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3042 3043 v = CSR_READ_1(sc, RL_CFG5); 3044 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3045 v &= ~RL_CFG5_WOL_LANWAKE; 3046 CSR_WRITE_1(sc, RL_CFG5, v); 3047} 3048