if_re.c revision 181272
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 181272 2008-08-04 03:45:07Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* Tunables. */ 159static int msi_disable = 1; 160TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164/* 165 * Various supported device vendors/types and their names. 166 */ 167static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8168C/8168CP/8111B/8111C/8111CP PCIe " 176 "Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8169, 0, 178 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 182 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 183 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 184 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 185 { USR_VENDORID, USR_DEVICEID_997902, 0, 186 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 187}; 188 189static struct rl_hwrev re_hwrevs[] = { 190 { RL_HWREV_8139, RL_8139, "" }, 191 { RL_HWREV_8139A, RL_8139, "A" }, 192 { RL_HWREV_8139AG, RL_8139, "A-G" }, 193 { RL_HWREV_8139B, RL_8139, "B" }, 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 204 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL"}, 205 { RL_HWREV_8100, RL_8139, "8100"}, 206 { RL_HWREV_8101, RL_8139, "8101"}, 207 { RL_HWREV_8100E, RL_8169, "8100E"}, 208 { RL_HWREV_8101E, RL_8169, "8101E"}, 209 { RL_HWREV_8102E, RL_8169, "8102E"}, 210 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 211 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 212 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 213 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 214 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 215 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 216 { 0, 0, NULL } 217}; 218 219static int re_probe (device_t); 220static int re_attach (device_t); 221static int re_detach (device_t); 222 223static int re_encap (struct rl_softc *, struct mbuf **); 224 225static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 226static int re_allocmem (device_t, struct rl_softc *); 227static __inline void re_discard_rxbuf 228 (struct rl_softc *, int); 229static int re_newbuf (struct rl_softc *, int); 230static int re_rx_list_init (struct rl_softc *); 231static int re_tx_list_init (struct rl_softc *); 232#ifdef RE_FIXUP_RX 233static __inline void re_fixup_rx 234 (struct mbuf *); 235#endif 236static int re_rxeof (struct rl_softc *); 237static void re_txeof (struct rl_softc *); 238#ifdef DEVICE_POLLING 239static void re_poll (struct ifnet *, enum poll_cmd, int); 240static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 241#endif 242static int re_intr (void *); 243static void re_tick (void *); 244static void re_tx_task (void *, int); 245static void re_int_task (void *, int); 246static void re_start (struct ifnet *); 247static int re_ioctl (struct ifnet *, u_long, caddr_t); 248static void re_init (void *); 249static void re_init_locked (struct rl_softc *); 250static void re_stop (struct rl_softc *); 251static void re_watchdog (struct rl_softc *); 252static int re_suspend (device_t); 253static int re_resume (device_t); 254static int re_shutdown (device_t); 255static int re_ifmedia_upd (struct ifnet *); 256static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 257 258static void re_eeprom_putbyte (struct rl_softc *, int); 259static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 260static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 261static int re_gmii_readreg (device_t, int, int); 262static int re_gmii_writereg (device_t, int, int, int); 263 264static int re_miibus_readreg (device_t, int, int); 265static int re_miibus_writereg (device_t, int, int, int); 266static void re_miibus_statchg (device_t); 267 268static void re_setmulti (struct rl_softc *); 269static void re_reset (struct rl_softc *); 270static void re_setwol (struct rl_softc *); 271static void re_clrwol (struct rl_softc *); 272 273#ifdef RE_DIAG 274static int re_diag (struct rl_softc *); 275#endif 276 277static device_method_t re_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, re_probe), 280 DEVMETHOD(device_attach, re_attach), 281 DEVMETHOD(device_detach, re_detach), 282 DEVMETHOD(device_suspend, re_suspend), 283 DEVMETHOD(device_resume, re_resume), 284 DEVMETHOD(device_shutdown, re_shutdown), 285 286 /* bus interface */ 287 DEVMETHOD(bus_print_child, bus_generic_print_child), 288 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 289 290 /* MII interface */ 291 DEVMETHOD(miibus_readreg, re_miibus_readreg), 292 DEVMETHOD(miibus_writereg, re_miibus_writereg), 293 DEVMETHOD(miibus_statchg, re_miibus_statchg), 294 295 { 0, 0 } 296}; 297 298static driver_t re_driver = { 299 "re", 300 re_methods, 301 sizeof(struct rl_softc) 302}; 303 304static devclass_t re_devclass; 305 306DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 307DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 308DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 309 310#define EE_SET(x) \ 311 CSR_WRITE_1(sc, RL_EECMD, \ 312 CSR_READ_1(sc, RL_EECMD) | x) 313 314#define EE_CLR(x) \ 315 CSR_WRITE_1(sc, RL_EECMD, \ 316 CSR_READ_1(sc, RL_EECMD) & ~x) 317 318/* 319 * Send a read command and address to the EEPROM, check for ACK. 320 */ 321static void 322re_eeprom_putbyte(struct rl_softc *sc, int addr) 323{ 324 register int d, i; 325 326 d = addr | (RL_9346_READ << sc->rl_eewidth); 327 328 /* 329 * Feed in each bit and strobe the clock. 330 */ 331 332 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 333 if (d & i) { 334 EE_SET(RL_EE_DATAIN); 335 } else { 336 EE_CLR(RL_EE_DATAIN); 337 } 338 DELAY(100); 339 EE_SET(RL_EE_CLK); 340 DELAY(150); 341 EE_CLR(RL_EE_CLK); 342 DELAY(100); 343 } 344 345 return; 346} 347 348/* 349 * Read a word of data stored in the EEPROM at address 'addr.' 350 */ 351static void 352re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 353{ 354 register int i; 355 u_int16_t word = 0; 356 357 /* 358 * Send address of word we want to read. 359 */ 360 re_eeprom_putbyte(sc, addr); 361 362 /* 363 * Start reading bits from EEPROM. 364 */ 365 for (i = 0x8000; i; i >>= 1) { 366 EE_SET(RL_EE_CLK); 367 DELAY(100); 368 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 369 word |= i; 370 EE_CLR(RL_EE_CLK); 371 DELAY(100); 372 } 373 374 *dest = word; 375 376 return; 377} 378 379/* 380 * Read a sequence of words from the EEPROM. 381 */ 382static void 383re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 384{ 385 int i; 386 u_int16_t word = 0, *ptr; 387 388 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 389 390 DELAY(100); 391 392 for (i = 0; i < cnt; i++) { 393 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 394 re_eeprom_getword(sc, off + i, &word); 395 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 396 ptr = (u_int16_t *)(dest + (i * 2)); 397 *ptr = word; 398 } 399 400 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 401 402 return; 403} 404 405static int 406re_gmii_readreg(device_t dev, int phy, int reg) 407{ 408 struct rl_softc *sc; 409 u_int32_t rval; 410 int i; 411 412 if (phy != 1) 413 return (0); 414 415 sc = device_get_softc(dev); 416 417 /* Let the rgephy driver read the GMEDIASTAT register */ 418 419 if (reg == RL_GMEDIASTAT) { 420 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 421 return (rval); 422 } 423 424 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 425 DELAY(1000); 426 427 for (i = 0; i < RL_TIMEOUT; i++) { 428 rval = CSR_READ_4(sc, RL_PHYAR); 429 if (rval & RL_PHYAR_BUSY) 430 break; 431 DELAY(100); 432 } 433 434 if (i == RL_TIMEOUT) { 435 device_printf(sc->rl_dev, "PHY read failed\n"); 436 return (0); 437 } 438 439 return (rval & RL_PHYAR_PHYDATA); 440} 441 442static int 443re_gmii_writereg(device_t dev, int phy, int reg, int data) 444{ 445 struct rl_softc *sc; 446 u_int32_t rval; 447 int i; 448 449 sc = device_get_softc(dev); 450 451 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 452 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 453 DELAY(1000); 454 455 for (i = 0; i < RL_TIMEOUT; i++) { 456 rval = CSR_READ_4(sc, RL_PHYAR); 457 if (!(rval & RL_PHYAR_BUSY)) 458 break; 459 DELAY(100); 460 } 461 462 if (i == RL_TIMEOUT) { 463 device_printf(sc->rl_dev, "PHY write failed\n"); 464 return (0); 465 } 466 467 return (0); 468} 469 470static int 471re_miibus_readreg(device_t dev, int phy, int reg) 472{ 473 struct rl_softc *sc; 474 u_int16_t rval = 0; 475 u_int16_t re8139_reg = 0; 476 477 sc = device_get_softc(dev); 478 479 if (sc->rl_type == RL_8169) { 480 rval = re_gmii_readreg(dev, phy, reg); 481 return (rval); 482 } 483 484 /* Pretend the internal PHY is only at address 0 */ 485 if (phy) { 486 return (0); 487 } 488 switch (reg) { 489 case MII_BMCR: 490 re8139_reg = RL_BMCR; 491 break; 492 case MII_BMSR: 493 re8139_reg = RL_BMSR; 494 break; 495 case MII_ANAR: 496 re8139_reg = RL_ANAR; 497 break; 498 case MII_ANER: 499 re8139_reg = RL_ANER; 500 break; 501 case MII_ANLPAR: 502 re8139_reg = RL_LPAR; 503 break; 504 case MII_PHYIDR1: 505 case MII_PHYIDR2: 506 return (0); 507 /* 508 * Allow the rlphy driver to read the media status 509 * register. If we have a link partner which does not 510 * support NWAY, this is the register which will tell 511 * us the results of parallel detection. 512 */ 513 case RL_MEDIASTAT: 514 rval = CSR_READ_1(sc, RL_MEDIASTAT); 515 return (rval); 516 default: 517 device_printf(sc->rl_dev, "bad phy register\n"); 518 return (0); 519 } 520 rval = CSR_READ_2(sc, re8139_reg); 521 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 522 /* 8139C+ has different bit layout. */ 523 rval &= ~(BMCR_LOOP | BMCR_ISO); 524 } 525 return (rval); 526} 527 528static int 529re_miibus_writereg(device_t dev, int phy, int reg, int data) 530{ 531 struct rl_softc *sc; 532 u_int16_t re8139_reg = 0; 533 int rval = 0; 534 535 sc = device_get_softc(dev); 536 537 if (sc->rl_type == RL_8169) { 538 rval = re_gmii_writereg(dev, phy, reg, data); 539 return (rval); 540 } 541 542 /* Pretend the internal PHY is only at address 0 */ 543 if (phy) 544 return (0); 545 546 switch (reg) { 547 case MII_BMCR: 548 re8139_reg = RL_BMCR; 549 if (sc->rl_type == RL_8139CPLUS) { 550 /* 8139C+ has different bit layout. */ 551 data &= ~(BMCR_LOOP | BMCR_ISO); 552 } 553 break; 554 case MII_BMSR: 555 re8139_reg = RL_BMSR; 556 break; 557 case MII_ANAR: 558 re8139_reg = RL_ANAR; 559 break; 560 case MII_ANER: 561 re8139_reg = RL_ANER; 562 break; 563 case MII_ANLPAR: 564 re8139_reg = RL_LPAR; 565 break; 566 case MII_PHYIDR1: 567 case MII_PHYIDR2: 568 return (0); 569 break; 570 default: 571 device_printf(sc->rl_dev, "bad phy register\n"); 572 return (0); 573 } 574 CSR_WRITE_2(sc, re8139_reg, data); 575 return (0); 576} 577 578static void 579re_miibus_statchg(device_t dev) 580{ 581 582} 583 584/* 585 * Program the 64-bit multicast hash filter. 586 */ 587static void 588re_setmulti(struct rl_softc *sc) 589{ 590 struct ifnet *ifp; 591 int h = 0; 592 u_int32_t hashes[2] = { 0, 0 }; 593 struct ifmultiaddr *ifma; 594 u_int32_t rxfilt; 595 int mcnt = 0; 596 597 RL_LOCK_ASSERT(sc); 598 599 ifp = sc->rl_ifp; 600 601 602 rxfilt = CSR_READ_4(sc, RL_RXCFG); 603 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 604 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 605 if (ifp->if_flags & IFF_PROMISC) 606 rxfilt |= RL_RXCFG_RX_ALLPHYS; 607 /* 608 * Unlike other hardwares, we have to explicitly set 609 * RL_RXCFG_RX_MULTI to receive multicast frames in 610 * promiscuous mode. 611 */ 612 rxfilt |= RL_RXCFG_RX_MULTI; 613 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 614 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 615 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 616 return; 617 } 618 619 /* first, zot all the existing hash bits */ 620 CSR_WRITE_4(sc, RL_MAR0, 0); 621 CSR_WRITE_4(sc, RL_MAR4, 0); 622 623 /* now program new ones */ 624 IF_ADDR_LOCK(ifp); 625 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 626 if (ifma->ifma_addr->sa_family != AF_LINK) 627 continue; 628 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 629 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 630 if (h < 32) 631 hashes[0] |= (1 << h); 632 else 633 hashes[1] |= (1 << (h - 32)); 634 mcnt++; 635 } 636 IF_ADDR_UNLOCK(ifp); 637 638 if (mcnt) 639 rxfilt |= RL_RXCFG_RX_MULTI; 640 else 641 rxfilt &= ~RL_RXCFG_RX_MULTI; 642 643 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 644 645 /* 646 * For some unfathomable reason, RealTek decided to reverse 647 * the order of the multicast hash registers in the PCI Express 648 * parts. This means we have to write the hash pattern in reverse 649 * order for those devices. 650 */ 651 652 if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) { 653 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 654 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 655 } else { 656 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 657 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 658 } 659} 660 661static void 662re_reset(struct rl_softc *sc) 663{ 664 register int i; 665 666 RL_LOCK_ASSERT(sc); 667 668 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 669 670 for (i = 0; i < RL_TIMEOUT; i++) { 671 DELAY(10); 672 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 673 break; 674 } 675 if (i == RL_TIMEOUT) 676 device_printf(sc->rl_dev, "reset never completed!\n"); 677 678 CSR_WRITE_1(sc, 0x82, 1); 679} 680 681#ifdef RE_DIAG 682 683/* 684 * The following routine is designed to test for a defect on some 685 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 686 * lines connected to the bus, however for a 32-bit only card, they 687 * should be pulled high. The result of this defect is that the 688 * NIC will not work right if you plug it into a 64-bit slot: DMA 689 * operations will be done with 64-bit transfers, which will fail 690 * because the 64-bit data lines aren't connected. 691 * 692 * There's no way to work around this (short of talking a soldering 693 * iron to the board), however we can detect it. The method we use 694 * here is to put the NIC into digital loopback mode, set the receiver 695 * to promiscuous mode, and then try to send a frame. We then compare 696 * the frame data we sent to what was received. If the data matches, 697 * then the NIC is working correctly, otherwise we know the user has 698 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 699 * slot. In the latter case, there's no way the NIC can work correctly, 700 * so we print out a message on the console and abort the device attach. 701 */ 702 703static int 704re_diag(struct rl_softc *sc) 705{ 706 struct ifnet *ifp = sc->rl_ifp; 707 struct mbuf *m0; 708 struct ether_header *eh; 709 struct rl_desc *cur_rx; 710 u_int16_t status; 711 u_int32_t rxstat; 712 int total_len, i, error = 0, phyaddr; 713 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 714 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 715 716 /* Allocate a single mbuf */ 717 MGETHDR(m0, M_DONTWAIT, MT_DATA); 718 if (m0 == NULL) 719 return (ENOBUFS); 720 721 RL_LOCK(sc); 722 723 /* 724 * Initialize the NIC in test mode. This sets the chip up 725 * so that it can send and receive frames, but performs the 726 * following special functions: 727 * - Puts receiver in promiscuous mode 728 * - Enables digital loopback mode 729 * - Leaves interrupts turned off 730 */ 731 732 ifp->if_flags |= IFF_PROMISC; 733 sc->rl_testmode = 1; 734 re_reset(sc); 735 re_init_locked(sc); 736 sc->rl_flags |= RL_FLAG_LINK; 737 if (sc->rl_type == RL_8169) 738 phyaddr = 1; 739 else 740 phyaddr = 0; 741 742 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 743 for (i = 0; i < RL_TIMEOUT; i++) { 744 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 745 if (!(status & BMCR_RESET)) 746 break; 747 } 748 749 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 750 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 751 752 DELAY(100000); 753 754 /* Put some data in the mbuf */ 755 756 eh = mtod(m0, struct ether_header *); 757 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 758 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 759 eh->ether_type = htons(ETHERTYPE_IP); 760 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 761 762 /* 763 * Queue the packet, start transmission. 764 * Note: IF_HANDOFF() ultimately calls re_start() for us. 765 */ 766 767 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 768 RL_UNLOCK(sc); 769 /* XXX: re_diag must not be called when in ALTQ mode */ 770 IF_HANDOFF(&ifp->if_snd, m0, ifp); 771 RL_LOCK(sc); 772 m0 = NULL; 773 774 /* Wait for it to propagate through the chip */ 775 776 DELAY(100000); 777 for (i = 0; i < RL_TIMEOUT; i++) { 778 status = CSR_READ_2(sc, RL_ISR); 779 CSR_WRITE_2(sc, RL_ISR, status); 780 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 781 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 782 break; 783 DELAY(10); 784 } 785 786 if (i == RL_TIMEOUT) { 787 device_printf(sc->rl_dev, 788 "diagnostic failed, failed to receive packet in" 789 " loopback mode\n"); 790 error = EIO; 791 goto done; 792 } 793 794 /* 795 * The packet should have been dumped into the first 796 * entry in the RX DMA ring. Grab it from there. 797 */ 798 799 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 800 sc->rl_ldata.rl_rx_list_map, 801 BUS_DMASYNC_POSTREAD); 802 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 803 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 804 BUS_DMASYNC_POSTREAD); 805 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 806 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 807 808 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 809 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 810 eh = mtod(m0, struct ether_header *); 811 812 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 813 total_len = RL_RXBYTES(cur_rx); 814 rxstat = le32toh(cur_rx->rl_cmdstat); 815 816 if (total_len != ETHER_MIN_LEN) { 817 device_printf(sc->rl_dev, 818 "diagnostic failed, received short packet\n"); 819 error = EIO; 820 goto done; 821 } 822 823 /* Test that the received packet data matches what we sent. */ 824 825 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 826 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 827 ntohs(eh->ether_type) != ETHERTYPE_IP) { 828 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 829 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 830 dst, ":", src, ":", ETHERTYPE_IP); 831 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 832 eh->ether_dhost, ":", eh->ether_shost, ":", 833 ntohs(eh->ether_type)); 834 device_printf(sc->rl_dev, "You may have a defective 32-bit " 835 "NIC plugged into a 64-bit PCI slot.\n"); 836 device_printf(sc->rl_dev, "Please re-install the NIC in a " 837 "32-bit slot for proper operation.\n"); 838 device_printf(sc->rl_dev, "Read the re(4) man page for more " 839 "details.\n"); 840 error = EIO; 841 } 842 843done: 844 /* Turn interface off, release resources */ 845 846 sc->rl_testmode = 0; 847 sc->rl_flags &= ~RL_FLAG_LINK; 848 ifp->if_flags &= ~IFF_PROMISC; 849 re_stop(sc); 850 if (m0 != NULL) 851 m_freem(m0); 852 853 RL_UNLOCK(sc); 854 855 return (error); 856} 857 858#endif 859 860/* 861 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 862 * IDs against our list and return a device name if we find a match. 863 */ 864static int 865re_probe(device_t dev) 866{ 867 struct rl_type *t; 868 uint16_t devid, vendor; 869 uint16_t revid, sdevid; 870 int i; 871 872 vendor = pci_get_vendor(dev); 873 devid = pci_get_device(dev); 874 revid = pci_get_revid(dev); 875 sdevid = pci_get_subdevice(dev); 876 877 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 878 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 879 /* 880 * Only attach to rev. 3 of the Linksys EG1032 adapter. 881 * Rev. 2 is supported by sk(4). 882 */ 883 return (ENXIO); 884 } 885 } 886 887 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 888 if (revid != 0x20) { 889 /* 8139, let rl(4) take care of this device. */ 890 return (ENXIO); 891 } 892 } 893 894 t = re_devs; 895 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 896 if (vendor == t->rl_vid && devid == t->rl_did) { 897 device_set_desc(dev, t->rl_name); 898 return (BUS_PROBE_DEFAULT); 899 } 900 } 901 902 return (ENXIO); 903} 904 905/* 906 * Map a single buffer address. 907 */ 908 909static void 910re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 911{ 912 bus_addr_t *addr; 913 914 if (error) 915 return; 916 917 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 918 addr = arg; 919 *addr = segs->ds_addr; 920} 921 922static int 923re_allocmem(device_t dev, struct rl_softc *sc) 924{ 925 bus_size_t rx_list_size, tx_list_size; 926 int error; 927 int i; 928 929 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 930 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 931 932 /* 933 * Allocate the parent bus DMA tag appropriate for PCI. 934 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 935 * register should be set. However some RealTek chips are known 936 * to be buggy on DAC handling, therefore disable DAC by limiting 937 * DMA address space to 32bit. PCIe variants of RealTek chips 938 * may not have the limitation but I took safer path. 939 */ 940 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 941 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 942 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 943 NULL, NULL, &sc->rl_parent_tag); 944 if (error) { 945 device_printf(dev, "could not allocate parent DMA tag\n"); 946 return (error); 947 } 948 949 /* 950 * Allocate map for TX mbufs. 951 */ 952 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 953 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 954 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 955 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 956 if (error) { 957 device_printf(dev, "could not allocate TX DMA tag\n"); 958 return (error); 959 } 960 961 /* 962 * Allocate map for RX mbufs. 963 */ 964 965 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 966 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 967 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 968 if (error) { 969 device_printf(dev, "could not allocate RX DMA tag\n"); 970 return (error); 971 } 972 973 /* 974 * Allocate map for TX descriptor list. 975 */ 976 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 977 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 978 NULL, tx_list_size, 1, tx_list_size, 0, 979 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 980 if (error) { 981 device_printf(dev, "could not allocate TX DMA ring tag\n"); 982 return (error); 983 } 984 985 /* Allocate DMA'able memory for the TX ring */ 986 987 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 988 (void **)&sc->rl_ldata.rl_tx_list, 989 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 990 &sc->rl_ldata.rl_tx_list_map); 991 if (error) { 992 device_printf(dev, "could not allocate TX DMA ring\n"); 993 return (error); 994 } 995 996 /* Load the map for the TX ring. */ 997 998 sc->rl_ldata.rl_tx_list_addr = 0; 999 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1000 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1001 tx_list_size, re_dma_map_addr, 1002 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1003 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1004 device_printf(dev, "could not load TX DMA ring\n"); 1005 return (ENOMEM); 1006 } 1007 1008 /* Create DMA maps for TX buffers */ 1009 1010 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1011 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1012 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1013 if (error) { 1014 device_printf(dev, "could not create DMA map for TX\n"); 1015 return (error); 1016 } 1017 } 1018 1019 /* 1020 * Allocate map for RX descriptor list. 1021 */ 1022 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1023 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1024 NULL, rx_list_size, 1, rx_list_size, 0, 1025 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1026 if (error) { 1027 device_printf(dev, "could not create RX DMA ring tag\n"); 1028 return (error); 1029 } 1030 1031 /* Allocate DMA'able memory for the RX ring */ 1032 1033 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1034 (void **)&sc->rl_ldata.rl_rx_list, 1035 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1036 &sc->rl_ldata.rl_rx_list_map); 1037 if (error) { 1038 device_printf(dev, "could not allocate RX DMA ring\n"); 1039 return (error); 1040 } 1041 1042 /* Load the map for the RX ring. */ 1043 1044 sc->rl_ldata.rl_rx_list_addr = 0; 1045 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1046 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1047 rx_list_size, re_dma_map_addr, 1048 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1049 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1050 device_printf(dev, "could not load RX DMA ring\n"); 1051 return (ENOMEM); 1052 } 1053 1054 /* Create DMA maps for RX buffers */ 1055 1056 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1057 &sc->rl_ldata.rl_rx_sparemap); 1058 if (error) { 1059 device_printf(dev, "could not create spare DMA map for RX\n"); 1060 return (error); 1061 } 1062 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1063 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1064 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1065 if (error) { 1066 device_printf(dev, "could not create DMA map for RX\n"); 1067 return (error); 1068 } 1069 } 1070 1071 return (0); 1072} 1073 1074/* 1075 * Attach the interface. Allocate softc structures, do ifmedia 1076 * setup and ethernet/BPF attach. 1077 */ 1078static int 1079re_attach(device_t dev) 1080{ 1081 u_char eaddr[ETHER_ADDR_LEN]; 1082 u_int16_t as[ETHER_ADDR_LEN / 2]; 1083 struct rl_softc *sc; 1084 struct ifnet *ifp; 1085 struct rl_hwrev *hw_rev; 1086 int hwrev; 1087 u_int16_t devid, re_did = 0; 1088 int error = 0, rid, i; 1089 int msic, reg; 1090 uint8_t cfg; 1091 1092 sc = device_get_softc(dev); 1093 sc->rl_dev = dev; 1094 1095 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1096 MTX_DEF); 1097 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1098 1099 /* 1100 * Map control/status registers. 1101 */ 1102 pci_enable_busmaster(dev); 1103 1104 devid = pci_get_device(dev); 1105 /* Prefer memory space register mapping over IO space. */ 1106 sc->rl_res_id = PCIR_BAR(1); 1107 sc->rl_res_type = SYS_RES_MEMORY; 1108 /* RTL8168/8101E seems to use different BARs. */ 1109 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1110 sc->rl_res_id = PCIR_BAR(2); 1111 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1112 &sc->rl_res_id, RF_ACTIVE); 1113 1114 if (sc->rl_res == NULL) { 1115 sc->rl_res_id = PCIR_BAR(0); 1116 sc->rl_res_type = SYS_RES_IOPORT; 1117 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1118 &sc->rl_res_id, RF_ACTIVE); 1119 if (sc->rl_res == NULL) { 1120 device_printf(dev, "couldn't map ports/memory\n"); 1121 error = ENXIO; 1122 goto fail; 1123 } 1124 } 1125 1126 sc->rl_btag = rman_get_bustag(sc->rl_res); 1127 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1128 1129 msic = 0; 1130 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1131 msic = pci_msi_count(dev); 1132 if (bootverbose) 1133 device_printf(dev, "MSI count : %d\n", msic); 1134 } 1135 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1136 if (pci_alloc_msi(dev, &msic) == 0) { 1137 if (msic == RL_MSI_MESSAGES) { 1138 device_printf(dev, "Using %d MSI messages\n", 1139 msic); 1140 sc->rl_flags |= RL_FLAG_MSI; 1141 /* Explicitly set MSI enable bit. */ 1142 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1143 cfg = CSR_READ_1(sc, RL_CFG2); 1144 cfg |= RL_CFG2_MSI; 1145 CSR_WRITE_1(sc, RL_CFG2, cfg); 1146 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1147 } else 1148 pci_release_msi(dev); 1149 } 1150 } 1151 1152 /* Allocate interrupt */ 1153 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1154 rid = 0; 1155 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1156 RF_SHAREABLE | RF_ACTIVE); 1157 if (sc->rl_irq[0] == NULL) { 1158 device_printf(dev, "couldn't allocate IRQ resources\n"); 1159 error = ENXIO; 1160 goto fail; 1161 } 1162 } else { 1163 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1164 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1165 SYS_RES_IRQ, &rid, RF_ACTIVE); 1166 if (sc->rl_irq[i] == NULL) { 1167 device_printf(dev, 1168 "couldn't llocate IRQ resources for " 1169 "message %d\n", rid); 1170 error = ENXIO; 1171 goto fail; 1172 } 1173 } 1174 } 1175 1176 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1177 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1178 cfg = CSR_READ_1(sc, RL_CFG2); 1179 if ((cfg & RL_CFG2_MSI) != 0) { 1180 device_printf(dev, "turning off MSI enable bit.\n"); 1181 cfg &= ~RL_CFG2_MSI; 1182 CSR_WRITE_1(sc, RL_CFG2, cfg); 1183 } 1184 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1185 } 1186 1187 /* Reset the adapter. */ 1188 RL_LOCK(sc); 1189 re_reset(sc); 1190 RL_UNLOCK(sc); 1191 1192 hw_rev = re_hwrevs; 1193 hwrev = CSR_READ_4(sc, RL_TXCFG); 1194 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1195 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1196 hwrev &= RL_TXCFG_HWREV; 1197 while (hw_rev->rl_desc != NULL) { 1198 if (hw_rev->rl_rev == hwrev) { 1199 sc->rl_type = hw_rev->rl_type; 1200 break; 1201 } 1202 hw_rev++; 1203 } 1204 if (hw_rev->rl_desc == NULL) { 1205 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1206 error = ENXIO; 1207 goto fail; 1208 } 1209 1210 switch (hw_rev->rl_rev) { 1211 case RL_HWREV_8139CPLUS: 1212 sc->rl_flags |= RL_FLAG_NOJUMBO; 1213 break; 1214 case RL_HWREV_8100E: 1215 case RL_HWREV_8101E: 1216 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1217 RL_FLAG_PHYWAKE; 1218 break; 1219 case RL_HWREV_8102E: 1220 case RL_HWREV_8102EL: 1221 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1222 RL_FLAG_PHYWAKE | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; 1223 break; 1224 case RL_HWREV_8168_SPIN1: 1225 case RL_HWREV_8168_SPIN2: 1226 case RL_HWREV_8168_SPIN3: 1227 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1228 RL_FLAG_MACSTAT; 1229 break; 1230 case RL_HWREV_8168C: 1231 case RL_HWREV_8168C_SPIN2: 1232 case RL_HWREV_8168CP: 1233 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1234 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; 1235 /* 1236 * These controllers support jumbo frame but it seems 1237 * that enabling it requires touching additional magic 1238 * registers. Depending on MAC revisions some 1239 * controllers need to disable checksum offload. So 1240 * disable jumbo frame until I have better idea what 1241 * it really requires to make it support. 1242 * RTL8168C/CP : supports up to 6KB jumbo frame. 1243 * RTL8111C/CP : supports up to 9KB jumbo frame. 1244 */ 1245 sc->rl_flags |= RL_FLAG_NOJUMBO; 1246 break; 1247 case RL_HWREV_8169_8110SB: 1248 case RL_HWREV_8169_8110SC: 1249 case RL_HWREV_8169_8110SBL: 1250 sc->rl_flags |= RL_FLAG_PHYWAKE; 1251 break; 1252 default: 1253 break; 1254 } 1255 1256 /* Enable PME. */ 1257 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1258 cfg = CSR_READ_1(sc, RL_CFG1); 1259 cfg |= RL_CFG1_PME; 1260 CSR_WRITE_1(sc, RL_CFG1, cfg); 1261 cfg = CSR_READ_1(sc, RL_CFG5); 1262 cfg &= RL_CFG5_PME_STS; 1263 CSR_WRITE_1(sc, RL_CFG5, cfg); 1264 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1265 1266 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1267 /* 1268 * XXX Should have a better way to extract station 1269 * address from EEPROM. 1270 */ 1271 for (i = 0; i < ETHER_ADDR_LEN; i++) 1272 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1273 } else { 1274 sc->rl_eewidth = RL_9356_ADDR_LEN; 1275 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1276 if (re_did != 0x8129) 1277 sc->rl_eewidth = RL_9346_ADDR_LEN; 1278 1279 /* 1280 * Get station address from the EEPROM. 1281 */ 1282 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1283 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1284 as[i] = le16toh(as[i]); 1285 bcopy(as, eaddr, sizeof(eaddr)); 1286 } 1287 1288 if (sc->rl_type == RL_8169) { 1289 /* Set RX length mask and number of descriptors. */ 1290 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1291 sc->rl_txstart = RL_GTXSTART; 1292 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1293 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1294 } else { 1295 /* Set RX length mask and number of descriptors. */ 1296 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1297 sc->rl_txstart = RL_TXSTART; 1298 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1299 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1300 } 1301 1302 error = re_allocmem(dev, sc); 1303 if (error) 1304 goto fail; 1305 1306 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1307 if (ifp == NULL) { 1308 device_printf(dev, "can not if_alloc()\n"); 1309 error = ENOSPC; 1310 goto fail; 1311 } 1312 1313 /* Take PHY out of power down mode. */ 1314 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1315 re_gmii_writereg(dev, 1, 0x1f, 0); 1316 re_gmii_writereg(dev, 1, 0x0e, 0); 1317 } 1318 1319 /* Do MII setup */ 1320 if (mii_phy_probe(dev, &sc->rl_miibus, 1321 re_ifmedia_upd, re_ifmedia_sts)) { 1322 device_printf(dev, "MII without any phy!\n"); 1323 error = ENXIO; 1324 goto fail; 1325 } 1326 1327 ifp->if_softc = sc; 1328 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1329 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1330 ifp->if_ioctl = re_ioctl; 1331 ifp->if_start = re_start; 1332 ifp->if_hwassist = RE_CSUM_FEATURES; 1333 ifp->if_capabilities = IFCAP_HWCSUM; 1334 ifp->if_capenable = ifp->if_capabilities; 1335 ifp->if_init = re_init; 1336 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1337 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1338 IFQ_SET_READY(&ifp->if_snd); 1339 1340 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1341 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1342 1343 /* 1344 * XXX 1345 * Still have no idea how to make TSO work on 8168C, 8168CP, 1346 * 8111C and 8111CP. 1347 */ 1348 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1349 ifp->if_hwassist |= CSUM_TSO; 1350 ifp->if_capabilities |= IFCAP_TSO4; 1351 } 1352 1353 /* 1354 * Call MI attach routine. 1355 */ 1356 ether_ifattach(ifp, eaddr); 1357 1358 /* VLAN capability setup */ 1359 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1360 if (ifp->if_capabilities & IFCAP_HWCSUM) 1361 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1362 /* Enable WOL if PM is supported. */ 1363 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1364 ifp->if_capabilities |= IFCAP_WOL; 1365 ifp->if_capenable = ifp->if_capabilities; 1366 /* 1367 * Don't enable TSO by default. Under certain 1368 * circumtances the controller generated corrupted 1369 * packets in TSO size. 1370 */ 1371 ifp->if_hwassist &= ~CSUM_TSO; 1372 ifp->if_capenable &= ~IFCAP_TSO4; 1373#ifdef DEVICE_POLLING 1374 ifp->if_capabilities |= IFCAP_POLLING; 1375#endif 1376 /* 1377 * Tell the upper layer(s) we support long frames. 1378 * Must appear after the call to ether_ifattach() because 1379 * ether_ifattach() sets ifi_hdrlen to the default value. 1380 */ 1381 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1382 1383#ifdef RE_DIAG 1384 /* 1385 * Perform hardware diagnostic on the original RTL8169. 1386 * Some 32-bit cards were incorrectly wired and would 1387 * malfunction if plugged into a 64-bit slot. 1388 */ 1389 1390 if (hwrev == RL_HWREV_8169) { 1391 error = re_diag(sc); 1392 if (error) { 1393 device_printf(dev, 1394 "attach aborted due to hardware diag failure\n"); 1395 ether_ifdetach(ifp); 1396 goto fail; 1397 } 1398 } 1399#endif 1400 1401 /* Hook interrupt last to avoid having to lock softc */ 1402 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1403 error = bus_setup_intr(dev, sc->rl_irq[0], 1404 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1405 &sc->rl_intrhand[0]); 1406 else { 1407 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1408 error = bus_setup_intr(dev, sc->rl_irq[i], 1409 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1410 &sc->rl_intrhand[i]); 1411 if (error != 0) 1412 break; 1413 } 1414 } 1415 if (error) { 1416 device_printf(dev, "couldn't set up irq\n"); 1417 ether_ifdetach(ifp); 1418 } 1419 1420fail: 1421 1422 if (error) 1423 re_detach(dev); 1424 1425 return (error); 1426} 1427 1428/* 1429 * Shutdown hardware and free up resources. This can be called any 1430 * time after the mutex has been initialized. It is called in both 1431 * the error case in attach and the normal detach case so it needs 1432 * to be careful about only freeing resources that have actually been 1433 * allocated. 1434 */ 1435static int 1436re_detach(device_t dev) 1437{ 1438 struct rl_softc *sc; 1439 struct ifnet *ifp; 1440 int i, rid; 1441 1442 sc = device_get_softc(dev); 1443 ifp = sc->rl_ifp; 1444 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1445 1446 /* These should only be active if attach succeeded */ 1447 if (device_is_attached(dev)) { 1448#ifdef DEVICE_POLLING 1449 if (ifp->if_capenable & IFCAP_POLLING) 1450 ether_poll_deregister(ifp); 1451#endif 1452 RL_LOCK(sc); 1453#if 0 1454 sc->suspended = 1; 1455#endif 1456 re_stop(sc); 1457 RL_UNLOCK(sc); 1458 callout_drain(&sc->rl_stat_callout); 1459 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1460 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1461 /* 1462 * Force off the IFF_UP flag here, in case someone 1463 * still had a BPF descriptor attached to this 1464 * interface. If they do, ether_ifdetach() will cause 1465 * the BPF code to try and clear the promisc mode 1466 * flag, which will bubble down to re_ioctl(), 1467 * which will try to call re_init() again. This will 1468 * turn the NIC back on and restart the MII ticker, 1469 * which will panic the system when the kernel tries 1470 * to invoke the re_tick() function that isn't there 1471 * anymore. 1472 */ 1473 ifp->if_flags &= ~IFF_UP; 1474 ether_ifdetach(ifp); 1475 } 1476 if (sc->rl_miibus) 1477 device_delete_child(dev, sc->rl_miibus); 1478 bus_generic_detach(dev); 1479 1480 /* 1481 * The rest is resource deallocation, so we should already be 1482 * stopped here. 1483 */ 1484 1485 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1486 if (sc->rl_intrhand[i] != NULL) { 1487 bus_teardown_intr(dev, sc->rl_irq[i], 1488 sc->rl_intrhand[i]); 1489 sc->rl_intrhand[i] = NULL; 1490 } 1491 } 1492 if (ifp != NULL) 1493 if_free(ifp); 1494 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1495 if (sc->rl_irq[0] != NULL) { 1496 bus_release_resource(dev, SYS_RES_IRQ, 0, 1497 sc->rl_irq[0]); 1498 sc->rl_irq[0] = NULL; 1499 } 1500 } else { 1501 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1502 if (sc->rl_irq[i] != NULL) { 1503 bus_release_resource(dev, SYS_RES_IRQ, rid, 1504 sc->rl_irq[i]); 1505 sc->rl_irq[i] = NULL; 1506 } 1507 } 1508 pci_release_msi(dev); 1509 } 1510 if (sc->rl_res) 1511 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1512 sc->rl_res); 1513 1514 /* Unload and free the RX DMA ring memory and map */ 1515 1516 if (sc->rl_ldata.rl_rx_list_tag) { 1517 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1518 sc->rl_ldata.rl_rx_list_map); 1519 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1520 sc->rl_ldata.rl_rx_list, 1521 sc->rl_ldata.rl_rx_list_map); 1522 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1523 } 1524 1525 /* Unload and free the TX DMA ring memory and map */ 1526 1527 if (sc->rl_ldata.rl_tx_list_tag) { 1528 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1529 sc->rl_ldata.rl_tx_list_map); 1530 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1531 sc->rl_ldata.rl_tx_list, 1532 sc->rl_ldata.rl_tx_list_map); 1533 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1534 } 1535 1536 /* Destroy all the RX and TX buffer maps */ 1537 1538 if (sc->rl_ldata.rl_tx_mtag) { 1539 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1540 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1541 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1542 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1543 } 1544 if (sc->rl_ldata.rl_rx_mtag) { 1545 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1546 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1547 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1548 if (sc->rl_ldata.rl_rx_sparemap) 1549 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1550 sc->rl_ldata.rl_rx_sparemap); 1551 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1552 } 1553 1554 /* Unload and free the stats buffer and map */ 1555 1556 if (sc->rl_ldata.rl_stag) { 1557 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1558 sc->rl_ldata.rl_rx_list_map); 1559 bus_dmamem_free(sc->rl_ldata.rl_stag, 1560 sc->rl_ldata.rl_stats, 1561 sc->rl_ldata.rl_smap); 1562 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1563 } 1564 1565 if (sc->rl_parent_tag) 1566 bus_dma_tag_destroy(sc->rl_parent_tag); 1567 1568 mtx_destroy(&sc->rl_mtx); 1569 1570 return (0); 1571} 1572 1573static __inline void 1574re_discard_rxbuf(struct rl_softc *sc, int idx) 1575{ 1576 struct rl_desc *desc; 1577 struct rl_rxdesc *rxd; 1578 uint32_t cmdstat; 1579 1580 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1581 desc = &sc->rl_ldata.rl_rx_list[idx]; 1582 desc->rl_vlanctl = 0; 1583 cmdstat = rxd->rx_size; 1584 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1585 cmdstat |= RL_RDESC_CMD_EOR; 1586 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1587} 1588 1589static int 1590re_newbuf(struct rl_softc *sc, int idx) 1591{ 1592 struct mbuf *m; 1593 struct rl_rxdesc *rxd; 1594 bus_dma_segment_t segs[1]; 1595 bus_dmamap_t map; 1596 struct rl_desc *desc; 1597 uint32_t cmdstat; 1598 int error, nsegs; 1599 1600 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1601 if (m == NULL) 1602 return (ENOBUFS); 1603 1604 m->m_len = m->m_pkthdr.len = MCLBYTES; 1605#ifdef RE_FIXUP_RX 1606 /* 1607 * This is part of an evil trick to deal with non-x86 platforms. 1608 * The RealTek chip requires RX buffers to be aligned on 64-bit 1609 * boundaries, but that will hose non-x86 machines. To get around 1610 * this, we leave some empty space at the start of each buffer 1611 * and for non-x86 hosts, we copy the buffer back six bytes 1612 * to achieve word alignment. This is slightly more efficient 1613 * than allocating a new buffer, copying the contents, and 1614 * discarding the old buffer. 1615 */ 1616 m_adj(m, RE_ETHER_ALIGN); 1617#endif 1618 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1619 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1620 if (error != 0) { 1621 m_freem(m); 1622 return (ENOBUFS); 1623 } 1624 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1625 1626 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1627 if (rxd->rx_m != NULL) { 1628 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1629 BUS_DMASYNC_POSTREAD); 1630 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1631 } 1632 1633 rxd->rx_m = m; 1634 map = rxd->rx_dmamap; 1635 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1636 rxd->rx_size = segs[0].ds_len; 1637 sc->rl_ldata.rl_rx_sparemap = map; 1638 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1639 BUS_DMASYNC_PREREAD); 1640 1641 desc = &sc->rl_ldata.rl_rx_list[idx]; 1642 desc->rl_vlanctl = 0; 1643 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1644 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1645 cmdstat = segs[0].ds_len; 1646 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1647 cmdstat |= RL_RDESC_CMD_EOR; 1648 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1649 1650 return (0); 1651} 1652 1653#ifdef RE_FIXUP_RX 1654static __inline void 1655re_fixup_rx(struct mbuf *m) 1656{ 1657 int i; 1658 uint16_t *src, *dst; 1659 1660 src = mtod(m, uint16_t *); 1661 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1662 1663 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1664 *dst++ = *src++; 1665 1666 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1667 1668 return; 1669} 1670#endif 1671 1672static int 1673re_tx_list_init(struct rl_softc *sc) 1674{ 1675 struct rl_desc *desc; 1676 int i; 1677 1678 RL_LOCK_ASSERT(sc); 1679 1680 bzero(sc->rl_ldata.rl_tx_list, 1681 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1682 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1683 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1684 /* Set EOR. */ 1685 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1686 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1687 1688 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1689 sc->rl_ldata.rl_tx_list_map, 1690 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1691 1692 sc->rl_ldata.rl_tx_prodidx = 0; 1693 sc->rl_ldata.rl_tx_considx = 0; 1694 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1695 1696 return (0); 1697} 1698 1699static int 1700re_rx_list_init(struct rl_softc *sc) 1701{ 1702 int error, i; 1703 1704 bzero(sc->rl_ldata.rl_rx_list, 1705 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1706 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1707 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1708 if ((error = re_newbuf(sc, i)) != 0) 1709 return (error); 1710 } 1711 1712 /* Flush the RX descriptors */ 1713 1714 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1715 sc->rl_ldata.rl_rx_list_map, 1716 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1717 1718 sc->rl_ldata.rl_rx_prodidx = 0; 1719 sc->rl_head = sc->rl_tail = NULL; 1720 1721 return (0); 1722} 1723 1724/* 1725 * RX handler for C+ and 8169. For the gigE chips, we support 1726 * the reception of jumbo frames that have been fragmented 1727 * across multiple 2K mbuf cluster buffers. 1728 */ 1729static int 1730re_rxeof(struct rl_softc *sc) 1731{ 1732 struct mbuf *m; 1733 struct ifnet *ifp; 1734 int i, total_len; 1735 struct rl_desc *cur_rx; 1736 u_int32_t rxstat, rxvlan; 1737 int maxpkt = 16; 1738 1739 RL_LOCK_ASSERT(sc); 1740 1741 ifp = sc->rl_ifp; 1742 1743 /* Invalidate the descriptor memory */ 1744 1745 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1746 sc->rl_ldata.rl_rx_list_map, 1747 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1748 1749 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1750 i = RL_RX_DESC_NXT(sc, i)) { 1751 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1752 rxstat = le32toh(cur_rx->rl_cmdstat); 1753 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1754 break; 1755 total_len = rxstat & sc->rl_rxlenmask; 1756 rxvlan = le32toh(cur_rx->rl_vlanctl); 1757 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1758 1759 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1760 if (re_newbuf(sc, i) != 0) { 1761 /* 1762 * If this is part of a multi-fragment packet, 1763 * discard all the pieces. 1764 */ 1765 if (sc->rl_head != NULL) { 1766 m_freem(sc->rl_head); 1767 sc->rl_head = sc->rl_tail = NULL; 1768 } 1769 re_discard_rxbuf(sc, i); 1770 continue; 1771 } 1772 m->m_len = RE_RX_DESC_BUFLEN; 1773 if (sc->rl_head == NULL) 1774 sc->rl_head = sc->rl_tail = m; 1775 else { 1776 m->m_flags &= ~M_PKTHDR; 1777 sc->rl_tail->m_next = m; 1778 sc->rl_tail = m; 1779 } 1780 continue; 1781 } 1782 1783 /* 1784 * NOTE: for the 8139C+, the frame length field 1785 * is always 12 bits in size, but for the gigE chips, 1786 * it is 13 bits (since the max RX frame length is 16K). 1787 * Unfortunately, all 32 bits in the status word 1788 * were already used, so to make room for the extra 1789 * length bit, RealTek took out the 'frame alignment 1790 * error' bit and shifted the other status bits 1791 * over one slot. The OWN, EOR, FS and LS bits are 1792 * still in the same places. We have already extracted 1793 * the frame length and checked the OWN bit, so rather 1794 * than using an alternate bit mapping, we shift the 1795 * status bits one space to the right so we can evaluate 1796 * them using the 8169 status as though it was in the 1797 * same format as that of the 8139C+. 1798 */ 1799 if (sc->rl_type == RL_8169) 1800 rxstat >>= 1; 1801 1802 /* 1803 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1804 * set, but if CRC is clear, it will still be a valid frame. 1805 */ 1806 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1807 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1808 ifp->if_ierrors++; 1809 /* 1810 * If this is part of a multi-fragment packet, 1811 * discard all the pieces. 1812 */ 1813 if (sc->rl_head != NULL) { 1814 m_freem(sc->rl_head); 1815 sc->rl_head = sc->rl_tail = NULL; 1816 } 1817 re_discard_rxbuf(sc, i); 1818 continue; 1819 } 1820 1821 /* 1822 * If allocating a replacement mbuf fails, 1823 * reload the current one. 1824 */ 1825 1826 if (re_newbuf(sc, i) != 0) { 1827 ifp->if_iqdrops++; 1828 if (sc->rl_head != NULL) { 1829 m_freem(sc->rl_head); 1830 sc->rl_head = sc->rl_tail = NULL; 1831 } 1832 re_discard_rxbuf(sc, i); 1833 continue; 1834 } 1835 1836 if (sc->rl_head != NULL) { 1837 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1838 if (m->m_len == 0) 1839 m->m_len = RE_RX_DESC_BUFLEN; 1840 /* 1841 * Special case: if there's 4 bytes or less 1842 * in this buffer, the mbuf can be discarded: 1843 * the last 4 bytes is the CRC, which we don't 1844 * care about anyway. 1845 */ 1846 if (m->m_len <= ETHER_CRC_LEN) { 1847 sc->rl_tail->m_len -= 1848 (ETHER_CRC_LEN - m->m_len); 1849 m_freem(m); 1850 } else { 1851 m->m_len -= ETHER_CRC_LEN; 1852 m->m_flags &= ~M_PKTHDR; 1853 sc->rl_tail->m_next = m; 1854 } 1855 m = sc->rl_head; 1856 sc->rl_head = sc->rl_tail = NULL; 1857 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1858 } else 1859 m->m_pkthdr.len = m->m_len = 1860 (total_len - ETHER_CRC_LEN); 1861 1862#ifdef RE_FIXUP_RX 1863 re_fixup_rx(m); 1864#endif 1865 ifp->if_ipackets++; 1866 m->m_pkthdr.rcvif = ifp; 1867 1868 /* Do RX checksumming if enabled */ 1869 1870 if (ifp->if_capenable & IFCAP_RXCSUM) { 1871 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1872 /* Check IP header checksum */ 1873 if (rxstat & RL_RDESC_STAT_PROTOID) 1874 m->m_pkthdr.csum_flags |= 1875 CSUM_IP_CHECKED; 1876 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1877 m->m_pkthdr.csum_flags |= 1878 CSUM_IP_VALID; 1879 1880 /* Check TCP/UDP checksum */ 1881 if ((RL_TCPPKT(rxstat) && 1882 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1883 (RL_UDPPKT(rxstat) && 1884 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1885 m->m_pkthdr.csum_flags |= 1886 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1887 m->m_pkthdr.csum_data = 0xffff; 1888 } 1889 } else { 1890 /* 1891 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1892 */ 1893 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1894 (rxvlan & RL_RDESC_IPV4)) 1895 m->m_pkthdr.csum_flags |= 1896 CSUM_IP_CHECKED; 1897 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1898 (rxvlan & RL_RDESC_IPV4)) 1899 m->m_pkthdr.csum_flags |= 1900 CSUM_IP_VALID; 1901 if (((rxstat & RL_RDESC_STAT_TCP) && 1902 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1903 ((rxstat & RL_RDESC_STAT_UDP) && 1904 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1905 m->m_pkthdr.csum_flags |= 1906 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1907 m->m_pkthdr.csum_data = 0xffff; 1908 } 1909 } 1910 } 1911 maxpkt--; 1912 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1913 m->m_pkthdr.ether_vtag = 1914 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1915 m->m_flags |= M_VLANTAG; 1916 } 1917 RL_UNLOCK(sc); 1918 (*ifp->if_input)(ifp, m); 1919 RL_LOCK(sc); 1920 } 1921 1922 /* Flush the RX DMA ring */ 1923 1924 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1925 sc->rl_ldata.rl_rx_list_map, 1926 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1927 1928 sc->rl_ldata.rl_rx_prodidx = i; 1929 1930 if (maxpkt) 1931 return(EAGAIN); 1932 1933 return(0); 1934} 1935 1936static void 1937re_txeof(struct rl_softc *sc) 1938{ 1939 struct ifnet *ifp; 1940 struct rl_txdesc *txd; 1941 u_int32_t txstat; 1942 int cons; 1943 1944 cons = sc->rl_ldata.rl_tx_considx; 1945 if (cons == sc->rl_ldata.rl_tx_prodidx) 1946 return; 1947 1948 ifp = sc->rl_ifp; 1949 /* Invalidate the TX descriptor list */ 1950 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1951 sc->rl_ldata.rl_tx_list_map, 1952 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1953 1954 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1955 cons = RL_TX_DESC_NXT(sc, cons)) { 1956 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1957 if (txstat & RL_TDESC_STAT_OWN) 1958 break; 1959 /* 1960 * We only stash mbufs in the last descriptor 1961 * in a fragment chain, which also happens to 1962 * be the only place where the TX status bits 1963 * are valid. 1964 */ 1965 if (txstat & RL_TDESC_CMD_EOF) { 1966 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1967 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1968 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1969 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1970 txd->tx_dmamap); 1971 KASSERT(txd->tx_m != NULL, 1972 ("%s: freeing NULL mbufs!", __func__)); 1973 m_freem(txd->tx_m); 1974 txd->tx_m = NULL; 1975 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1976 RL_TDESC_STAT_COLCNT)) 1977 ifp->if_collisions++; 1978 if (txstat & RL_TDESC_STAT_TXERRSUM) 1979 ifp->if_oerrors++; 1980 else 1981 ifp->if_opackets++; 1982 } 1983 sc->rl_ldata.rl_tx_free++; 1984 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1985 } 1986 sc->rl_ldata.rl_tx_considx = cons; 1987 1988 /* No changes made to the TX ring, so no flush needed */ 1989 1990 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1991 /* 1992 * Some chips will ignore a second TX request issued 1993 * while an existing transmission is in progress. If 1994 * the transmitter goes idle but there are still 1995 * packets waiting to be sent, we need to restart the 1996 * channel here to flush them out. This only seems to 1997 * be required with the PCIe devices. 1998 */ 1999 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2000 2001#ifdef RE_TX_MODERATION 2002 /* 2003 * If not all descriptors have been reaped yet, reload 2004 * the timer so that we will eventually get another 2005 * interrupt that will cause us to re-enter this routine. 2006 * This is done in case the transmitter has gone idle. 2007 */ 2008 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2009#endif 2010 } else 2011 sc->rl_watchdog_timer = 0; 2012} 2013 2014static void 2015re_tick(void *xsc) 2016{ 2017 struct rl_softc *sc; 2018 struct mii_data *mii; 2019 struct ifnet *ifp; 2020 2021 sc = xsc; 2022 ifp = sc->rl_ifp; 2023 2024 RL_LOCK_ASSERT(sc); 2025 2026 re_watchdog(sc); 2027 2028 mii = device_get_softc(sc->rl_miibus); 2029 mii_tick(mii); 2030 if ((sc->rl_flags & RL_FLAG_LINK) != 0) { 2031 if (!(mii->mii_media_status & IFM_ACTIVE)) 2032 sc->rl_flags &= ~RL_FLAG_LINK; 2033 } else { 2034 if (mii->mii_media_status & IFM_ACTIVE && 2035 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2036 sc->rl_flags |= RL_FLAG_LINK; 2037 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2038 taskqueue_enqueue_fast(taskqueue_fast, 2039 &sc->rl_txtask); 2040 } 2041 } 2042 2043 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2044} 2045 2046#ifdef DEVICE_POLLING 2047static void 2048re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2049{ 2050 struct rl_softc *sc = ifp->if_softc; 2051 2052 RL_LOCK(sc); 2053 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2054 re_poll_locked(ifp, cmd, count); 2055 RL_UNLOCK(sc); 2056} 2057 2058static void 2059re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2060{ 2061 struct rl_softc *sc = ifp->if_softc; 2062 2063 RL_LOCK_ASSERT(sc); 2064 2065 sc->rxcycles = count; 2066 re_rxeof(sc); 2067 re_txeof(sc); 2068 2069 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2070 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2071 2072 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2073 u_int16_t status; 2074 2075 status = CSR_READ_2(sc, RL_ISR); 2076 if (status == 0xffff) 2077 return; 2078 if (status) 2079 CSR_WRITE_2(sc, RL_ISR, status); 2080 2081 /* 2082 * XXX check behaviour on receiver stalls. 2083 */ 2084 2085 if (status & RL_ISR_SYSTEM_ERR) { 2086 re_reset(sc); 2087 re_init_locked(sc); 2088 } 2089 } 2090} 2091#endif /* DEVICE_POLLING */ 2092 2093static int 2094re_intr(void *arg) 2095{ 2096 struct rl_softc *sc; 2097 uint16_t status; 2098 2099 sc = arg; 2100 2101 status = CSR_READ_2(sc, RL_ISR); 2102 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2103 return (FILTER_STRAY); 2104 CSR_WRITE_2(sc, RL_IMR, 0); 2105 2106 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2107 2108 return (FILTER_HANDLED); 2109} 2110 2111static void 2112re_int_task(void *arg, int npending) 2113{ 2114 struct rl_softc *sc; 2115 struct ifnet *ifp; 2116 u_int16_t status; 2117 int rval = 0; 2118 2119 sc = arg; 2120 ifp = sc->rl_ifp; 2121 2122 RL_LOCK(sc); 2123 2124 status = CSR_READ_2(sc, RL_ISR); 2125 CSR_WRITE_2(sc, RL_ISR, status); 2126 2127 if (sc->suspended || 2128 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2129 RL_UNLOCK(sc); 2130 return; 2131 } 2132 2133#ifdef DEVICE_POLLING 2134 if (ifp->if_capenable & IFCAP_POLLING) { 2135 RL_UNLOCK(sc); 2136 return; 2137 } 2138#endif 2139 2140 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2141 rval = re_rxeof(sc); 2142 2143#ifdef RE_TX_MODERATION 2144 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2145#else 2146 if (status & (RL_ISR_TX_OK| 2147#endif 2148 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2149 re_txeof(sc); 2150 2151 if (status & RL_ISR_SYSTEM_ERR) { 2152 re_reset(sc); 2153 re_init_locked(sc); 2154 } 2155 2156 if (status & RL_ISR_LINKCHG) { 2157 callout_stop(&sc->rl_stat_callout); 2158 re_tick(sc); 2159 } 2160 2161 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2162 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2163 2164 RL_UNLOCK(sc); 2165 2166 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2167 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2168 return; 2169 } 2170 2171 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2172 2173 return; 2174} 2175 2176static int 2177re_encap(struct rl_softc *sc, struct mbuf **m_head) 2178{ 2179 struct rl_txdesc *txd, *txd_last; 2180 bus_dma_segment_t segs[RL_NTXSEGS]; 2181 bus_dmamap_t map; 2182 struct mbuf *m_new; 2183 struct rl_desc *desc; 2184 int nsegs, prod; 2185 int i, error, ei, si; 2186 int padlen; 2187 uint32_t cmdstat, csum_flags, vlanctl; 2188 2189 RL_LOCK_ASSERT(sc); 2190 M_ASSERTPKTHDR((*m_head)); 2191 2192 /* 2193 * With some of the RealTek chips, using the checksum offload 2194 * support in conjunction with the autopadding feature results 2195 * in the transmission of corrupt frames. For example, if we 2196 * need to send a really small IP fragment that's less than 60 2197 * bytes in size, and IP header checksumming is enabled, the 2198 * resulting ethernet frame that appears on the wire will 2199 * have garbled payload. To work around this, if TX IP checksum 2200 * offload is enabled, we always manually pad short frames out 2201 * to the minimum ethernet frame size. 2202 */ 2203 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2204 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2205 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2206 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2207 if (M_WRITABLE(*m_head) == 0) { 2208 /* Get a writable copy. */ 2209 m_new = m_dup(*m_head, M_DONTWAIT); 2210 m_freem(*m_head); 2211 if (m_new == NULL) { 2212 *m_head = NULL; 2213 return (ENOBUFS); 2214 } 2215 *m_head = m_new; 2216 } 2217 if ((*m_head)->m_next != NULL || 2218 M_TRAILINGSPACE(*m_head) < padlen) { 2219 m_new = m_defrag(*m_head, M_DONTWAIT); 2220 if (m_new == NULL) { 2221 m_freem(*m_head); 2222 *m_head = NULL; 2223 return (ENOBUFS); 2224 } 2225 } else 2226 m_new = *m_head; 2227 2228 /* 2229 * Manually pad short frames, and zero the pad space 2230 * to avoid leaking data. 2231 */ 2232 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2233 m_new->m_pkthdr.len += padlen; 2234 m_new->m_len = m_new->m_pkthdr.len; 2235 *m_head = m_new; 2236 } 2237 2238 prod = sc->rl_ldata.rl_tx_prodidx; 2239 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2240 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2241 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2242 if (error == EFBIG) { 2243 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2244 if (m_new == NULL) { 2245 m_freem(*m_head); 2246 *m_head = NULL; 2247 return (ENOBUFS); 2248 } 2249 *m_head = m_new; 2250 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2251 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2252 if (error != 0) { 2253 m_freem(*m_head); 2254 *m_head = NULL; 2255 return (error); 2256 } 2257 } else if (error != 0) 2258 return (error); 2259 if (nsegs == 0) { 2260 m_freem(*m_head); 2261 *m_head = NULL; 2262 return (EIO); 2263 } 2264 2265 /* Check for number of available descriptors. */ 2266 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2267 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2268 return (ENOBUFS); 2269 } 2270 2271 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2272 BUS_DMASYNC_PREWRITE); 2273 2274 /* 2275 * Set up checksum offload. Note: checksum offload bits must 2276 * appear in all descriptors of a multi-descriptor transmit 2277 * attempt. This is according to testing done with an 8169 2278 * chip. This is a requirement. 2279 */ 2280 vlanctl = 0; 2281 csum_flags = 0; 2282 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2283 csum_flags = RL_TDESC_CMD_LGSEND | 2284 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2285 RL_TDESC_CMD_MSSVAL_SHIFT); 2286 else { 2287 /* 2288 * Unconditionally enable IP checksum if TCP or UDP 2289 * checksum is required. Otherwise, TCP/UDP checksum 2290 * does't make effects. 2291 */ 2292 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2293 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2294 csum_flags |= RL_TDESC_CMD_IPCSUM; 2295 if (((*m_head)->m_pkthdr.csum_flags & 2296 CSUM_TCP) != 0) 2297 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2298 if (((*m_head)->m_pkthdr.csum_flags & 2299 CSUM_UDP) != 0) 2300 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2301 } else { 2302 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2303 if (((*m_head)->m_pkthdr.csum_flags & 2304 CSUM_TCP) != 0) 2305 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2306 if (((*m_head)->m_pkthdr.csum_flags & 2307 CSUM_UDP) != 0) 2308 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2309 } 2310 } 2311 } 2312 2313 /* 2314 * Set up hardware VLAN tagging. Note: vlan tag info must 2315 * appear in all descriptors of a multi-descriptor 2316 * transmission attempt. 2317 */ 2318 if ((*m_head)->m_flags & M_VLANTAG) 2319 vlanctl |= htons((*m_head)->m_pkthdr.ether_vtag) | 2320 RL_TDESC_VLANCTL_TAG; 2321 2322 si = prod; 2323 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2324 desc = &sc->rl_ldata.rl_tx_list[prod]; 2325 desc->rl_vlanctl = htole32(vlanctl); 2326 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2327 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2328 cmdstat = segs[i].ds_len; 2329 if (i != 0) 2330 cmdstat |= RL_TDESC_CMD_OWN; 2331 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2332 cmdstat |= RL_TDESC_CMD_EOR; 2333 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2334 sc->rl_ldata.rl_tx_free--; 2335 } 2336 /* Update producer index. */ 2337 sc->rl_ldata.rl_tx_prodidx = prod; 2338 2339 /* Set EOF on the last descriptor. */ 2340 ei = RL_TX_DESC_PRV(sc, prod); 2341 desc = &sc->rl_ldata.rl_tx_list[ei]; 2342 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2343 2344 desc = &sc->rl_ldata.rl_tx_list[si]; 2345 /* Set SOF and transfer ownership of packet to the chip. */ 2346 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2347 2348 /* 2349 * Insure that the map for this transmission 2350 * is placed at the array index of the last descriptor 2351 * in this chain. (Swap last and first dmamaps.) 2352 */ 2353 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2354 map = txd->tx_dmamap; 2355 txd->tx_dmamap = txd_last->tx_dmamap; 2356 txd_last->tx_dmamap = map; 2357 txd_last->tx_m = *m_head; 2358 2359 return (0); 2360} 2361 2362static void 2363re_tx_task(void *arg, int npending) 2364{ 2365 struct ifnet *ifp; 2366 2367 ifp = arg; 2368 re_start(ifp); 2369 2370 return; 2371} 2372 2373/* 2374 * Main transmit routine for C+ and gigE NICs. 2375 */ 2376static void 2377re_start(struct ifnet *ifp) 2378{ 2379 struct rl_softc *sc; 2380 struct mbuf *m_head; 2381 int queued; 2382 2383 sc = ifp->if_softc; 2384 2385 RL_LOCK(sc); 2386 2387 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2388 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2389 RL_UNLOCK(sc); 2390 return; 2391 } 2392 2393 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2394 sc->rl_ldata.rl_tx_free > 1;) { 2395 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2396 if (m_head == NULL) 2397 break; 2398 2399 if (re_encap(sc, &m_head) != 0) { 2400 if (m_head == NULL) 2401 break; 2402 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2403 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2404 break; 2405 } 2406 2407 /* 2408 * If there's a BPF listener, bounce a copy of this frame 2409 * to him. 2410 */ 2411 ETHER_BPF_MTAP(ifp, m_head); 2412 2413 queued++; 2414 } 2415 2416 if (queued == 0) { 2417#ifdef RE_TX_MODERATION 2418 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2419 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2420#endif 2421 RL_UNLOCK(sc); 2422 return; 2423 } 2424 2425 /* Flush the TX descriptors */ 2426 2427 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2428 sc->rl_ldata.rl_tx_list_map, 2429 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2430 2431 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2432 2433#ifdef RE_TX_MODERATION 2434 /* 2435 * Use the countdown timer for interrupt moderation. 2436 * 'TX done' interrupts are disabled. Instead, we reset the 2437 * countdown timer, which will begin counting until it hits 2438 * the value in the TIMERINT register, and then trigger an 2439 * interrupt. Each time we write to the TIMERCNT register, 2440 * the timer count is reset to 0. 2441 */ 2442 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2443#endif 2444 2445 /* 2446 * Set a timeout in case the chip goes out to lunch. 2447 */ 2448 sc->rl_watchdog_timer = 5; 2449 2450 RL_UNLOCK(sc); 2451 2452 return; 2453} 2454 2455static void 2456re_init(void *xsc) 2457{ 2458 struct rl_softc *sc = xsc; 2459 2460 RL_LOCK(sc); 2461 re_init_locked(sc); 2462 RL_UNLOCK(sc); 2463} 2464 2465static void 2466re_init_locked(struct rl_softc *sc) 2467{ 2468 struct ifnet *ifp = sc->rl_ifp; 2469 struct mii_data *mii; 2470 u_int32_t rxcfg = 0; 2471 uint16_t cfg; 2472 union { 2473 uint32_t align_dummy; 2474 u_char eaddr[ETHER_ADDR_LEN]; 2475 } eaddr; 2476 2477 RL_LOCK_ASSERT(sc); 2478 2479 mii = device_get_softc(sc->rl_miibus); 2480 2481 /* 2482 * Cancel pending I/O and free all RX/TX buffers. 2483 */ 2484 re_stop(sc); 2485 2486 /* 2487 * Enable C+ RX and TX mode, as well as VLAN stripping and 2488 * RX checksum offload. We must configure the C+ register 2489 * before all others. 2490 */ 2491 cfg = RL_CPLUSCMD_PCI_MRW; 2492 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2493 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2494 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2495 cfg |= RL_CPLUSCMD_VLANSTRIP; 2496 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2497 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2498 /* XXX magic. */ 2499 cfg |= 0x0001; 2500 } else 2501 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2502 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2503 /* 2504 * Disable TSO if interface MTU size is greater than MSS 2505 * allowed in controller. 2506 */ 2507 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2508 ifp->if_capenable &= ~IFCAP_TSO4; 2509 ifp->if_hwassist &= ~CSUM_TSO; 2510 } 2511 2512 /* 2513 * Init our MAC address. Even though the chipset 2514 * documentation doesn't mention it, we need to enter "Config 2515 * register write enable" mode to modify the ID registers. 2516 */ 2517 /* Copy MAC address on stack to align. */ 2518 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2519 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2520 CSR_WRITE_4(sc, RL_IDR0, 2521 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2522 CSR_WRITE_4(sc, RL_IDR4, 2523 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2524 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2525 2526 /* 2527 * For C+ mode, initialize the RX descriptors and mbufs. 2528 */ 2529 re_rx_list_init(sc); 2530 re_tx_list_init(sc); 2531 2532 /* 2533 * Load the addresses of the RX and TX lists into the chip. 2534 */ 2535 2536 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2537 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2538 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2539 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2540 2541 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2542 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2543 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2544 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2545 2546 /* 2547 * Enable transmit and receive. 2548 */ 2549 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2550 2551 /* 2552 * Set the initial TX and RX configuration. 2553 */ 2554 if (sc->rl_testmode) { 2555 if (sc->rl_type == RL_8169) 2556 CSR_WRITE_4(sc, RL_TXCFG, 2557 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2558 else 2559 CSR_WRITE_4(sc, RL_TXCFG, 2560 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2561 } else 2562 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2563 2564 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2565 2566 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2567 2568 /* Set the individual bit to receive frames for this host only. */ 2569 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2570 rxcfg |= RL_RXCFG_RX_INDIV; 2571 2572 /* If we want promiscuous mode, set the allframes bit. */ 2573 if (ifp->if_flags & IFF_PROMISC) 2574 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2575 else 2576 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2577 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2578 2579 /* 2580 * Set capture broadcast bit to capture broadcast frames. 2581 */ 2582 if (ifp->if_flags & IFF_BROADCAST) 2583 rxcfg |= RL_RXCFG_RX_BROAD; 2584 else 2585 rxcfg &= ~RL_RXCFG_RX_BROAD; 2586 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2587 2588 /* 2589 * Program the multicast filter, if necessary. 2590 */ 2591 re_setmulti(sc); 2592 2593#ifdef DEVICE_POLLING 2594 /* 2595 * Disable interrupts if we are polling. 2596 */ 2597 if (ifp->if_capenable & IFCAP_POLLING) 2598 CSR_WRITE_2(sc, RL_IMR, 0); 2599 else /* otherwise ... */ 2600#endif 2601 2602 /* 2603 * Enable interrupts. 2604 */ 2605 if (sc->rl_testmode) 2606 CSR_WRITE_2(sc, RL_IMR, 0); 2607 else 2608 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2609 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2610 2611 /* Set initial TX threshold */ 2612 sc->rl_txthresh = RL_TX_THRESH_INIT; 2613 2614 /* Start RX/TX process. */ 2615 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2616#ifdef notdef 2617 /* Enable receiver and transmitter. */ 2618 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2619#endif 2620 2621#ifdef RE_TX_MODERATION 2622 /* 2623 * Initialize the timer interrupt register so that 2624 * a timer interrupt will be generated once the timer 2625 * reaches a certain number of ticks. The timer is 2626 * reloaded on each transmit. This gives us TX interrupt 2627 * moderation, which dramatically improves TX frame rate. 2628 */ 2629 if (sc->rl_type == RL_8169) 2630 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2631 else 2632 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2633#endif 2634 2635 /* 2636 * For 8169 gigE NICs, set the max allowed RX packet 2637 * size so we can receive jumbo frames. 2638 */ 2639 if (sc->rl_type == RL_8169) 2640 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2641 2642 if (sc->rl_testmode) 2643 return; 2644 2645 mii_mediachg(mii); 2646 2647 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2648 2649 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2650 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2651 2652 sc->rl_flags &= ~RL_FLAG_LINK; 2653 sc->rl_watchdog_timer = 0; 2654 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2655} 2656 2657/* 2658 * Set media options. 2659 */ 2660static int 2661re_ifmedia_upd(struct ifnet *ifp) 2662{ 2663 struct rl_softc *sc; 2664 struct mii_data *mii; 2665 2666 sc = ifp->if_softc; 2667 mii = device_get_softc(sc->rl_miibus); 2668 RL_LOCK(sc); 2669 mii_mediachg(mii); 2670 RL_UNLOCK(sc); 2671 2672 return (0); 2673} 2674 2675/* 2676 * Report current media status. 2677 */ 2678static void 2679re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2680{ 2681 struct rl_softc *sc; 2682 struct mii_data *mii; 2683 2684 sc = ifp->if_softc; 2685 mii = device_get_softc(sc->rl_miibus); 2686 2687 RL_LOCK(sc); 2688 mii_pollstat(mii); 2689 RL_UNLOCK(sc); 2690 ifmr->ifm_active = mii->mii_media_active; 2691 ifmr->ifm_status = mii->mii_media_status; 2692} 2693 2694static int 2695re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2696{ 2697 struct rl_softc *sc = ifp->if_softc; 2698 struct ifreq *ifr = (struct ifreq *) data; 2699 struct mii_data *mii; 2700 int error = 0; 2701 2702 switch (command) { 2703 case SIOCSIFMTU: 2704 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2705 error = EINVAL; 2706 break; 2707 } 2708 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2709 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2710 error = EINVAL; 2711 break; 2712 } 2713 RL_LOCK(sc); 2714 if (ifp->if_mtu != ifr->ifr_mtu) 2715 ifp->if_mtu = ifr->ifr_mtu; 2716 if (ifp->if_mtu > RL_TSO_MTU && 2717 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2718 ifp->if_capenable &= ~IFCAP_TSO4; 2719 ifp->if_hwassist &= ~CSUM_TSO; 2720 } 2721 RL_UNLOCK(sc); 2722 break; 2723 case SIOCSIFFLAGS: 2724 RL_LOCK(sc); 2725 if ((ifp->if_flags & IFF_UP) != 0) { 2726 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2727 if (((ifp->if_flags ^ sc->rl_if_flags) 2728 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2729 re_setmulti(sc); 2730 } else 2731 re_init_locked(sc); 2732 } else { 2733 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2734 re_stop(sc); 2735 } 2736 sc->rl_if_flags = ifp->if_flags; 2737 RL_UNLOCK(sc); 2738 break; 2739 case SIOCADDMULTI: 2740 case SIOCDELMULTI: 2741 RL_LOCK(sc); 2742 re_setmulti(sc); 2743 RL_UNLOCK(sc); 2744 break; 2745 case SIOCGIFMEDIA: 2746 case SIOCSIFMEDIA: 2747 mii = device_get_softc(sc->rl_miibus); 2748 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2749 break; 2750 case SIOCSIFCAP: 2751 { 2752 int mask, reinit; 2753 2754 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2755 reinit = 0; 2756#ifdef DEVICE_POLLING 2757 if (mask & IFCAP_POLLING) { 2758 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2759 error = ether_poll_register(re_poll, ifp); 2760 if (error) 2761 return(error); 2762 RL_LOCK(sc); 2763 /* Disable interrupts */ 2764 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2765 ifp->if_capenable |= IFCAP_POLLING; 2766 RL_UNLOCK(sc); 2767 } else { 2768 error = ether_poll_deregister(ifp); 2769 /* Enable interrupts. */ 2770 RL_LOCK(sc); 2771 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2772 ifp->if_capenable &= ~IFCAP_POLLING; 2773 RL_UNLOCK(sc); 2774 } 2775 } 2776#endif /* DEVICE_POLLING */ 2777 if (mask & IFCAP_HWCSUM) { 2778 ifp->if_capenable ^= IFCAP_HWCSUM; 2779 if (ifp->if_capenable & IFCAP_TXCSUM) 2780 ifp->if_hwassist |= RE_CSUM_FEATURES; 2781 else 2782 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2783 reinit = 1; 2784 } 2785 if (mask & IFCAP_VLAN_HWTAGGING) { 2786 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2787 reinit = 1; 2788 } 2789 if (mask & IFCAP_TSO4) { 2790 ifp->if_capenable ^= IFCAP_TSO4; 2791 if ((IFCAP_TSO4 & ifp->if_capenable) && 2792 (IFCAP_TSO4 & ifp->if_capabilities)) 2793 ifp->if_hwassist |= CSUM_TSO; 2794 else 2795 ifp->if_hwassist &= ~CSUM_TSO; 2796 if (ifp->if_mtu > RL_TSO_MTU && 2797 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2798 ifp->if_capenable &= ~IFCAP_TSO4; 2799 ifp->if_hwassist &= ~CSUM_TSO; 2800 } 2801 } 2802 if ((mask & IFCAP_WOL) != 0 && 2803 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2804 if ((mask & IFCAP_WOL_UCAST) != 0) 2805 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2806 if ((mask & IFCAP_WOL_MCAST) != 0) 2807 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2808 if ((mask & IFCAP_WOL_MAGIC) != 0) 2809 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2810 } 2811 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2812 re_init(sc); 2813 VLAN_CAPABILITIES(ifp); 2814 } 2815 break; 2816 default: 2817 error = ether_ioctl(ifp, command, data); 2818 break; 2819 } 2820 2821 return (error); 2822} 2823 2824static void 2825re_watchdog(struct rl_softc *sc) 2826{ 2827 2828 RL_LOCK_ASSERT(sc); 2829 2830 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2831 return; 2832 2833 device_printf(sc->rl_dev, "watchdog timeout\n"); 2834 sc->rl_ifp->if_oerrors++; 2835 2836 re_txeof(sc); 2837 re_rxeof(sc); 2838 re_init_locked(sc); 2839} 2840 2841/* 2842 * Stop the adapter and free any mbufs allocated to the 2843 * RX and TX lists. 2844 */ 2845static void 2846re_stop(struct rl_softc *sc) 2847{ 2848 register int i; 2849 struct ifnet *ifp; 2850 struct rl_txdesc *txd; 2851 struct rl_rxdesc *rxd; 2852 2853 RL_LOCK_ASSERT(sc); 2854 2855 ifp = sc->rl_ifp; 2856 2857 sc->rl_watchdog_timer = 0; 2858 callout_stop(&sc->rl_stat_callout); 2859 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2860 2861 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2862 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2863 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2864 2865 if (sc->rl_head != NULL) { 2866 m_freem(sc->rl_head); 2867 sc->rl_head = sc->rl_tail = NULL; 2868 } 2869 2870 /* Free the TX list buffers. */ 2871 2872 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2873 txd = &sc->rl_ldata.rl_tx_desc[i]; 2874 if (txd->tx_m != NULL) { 2875 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2876 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2877 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2878 txd->tx_dmamap); 2879 m_freem(txd->tx_m); 2880 txd->tx_m = NULL; 2881 } 2882 } 2883 2884 /* Free the RX list buffers. */ 2885 2886 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2887 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2888 if (rxd->rx_m != NULL) { 2889 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2890 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2891 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2892 rxd->rx_dmamap); 2893 m_freem(rxd->rx_m); 2894 rxd->rx_m = NULL; 2895 } 2896 } 2897} 2898 2899/* 2900 * Device suspend routine. Stop the interface and save some PCI 2901 * settings in case the BIOS doesn't restore them properly on 2902 * resume. 2903 */ 2904static int 2905re_suspend(device_t dev) 2906{ 2907 struct rl_softc *sc; 2908 2909 sc = device_get_softc(dev); 2910 2911 RL_LOCK(sc); 2912 re_stop(sc); 2913 re_setwol(sc); 2914 sc->suspended = 1; 2915 RL_UNLOCK(sc); 2916 2917 return (0); 2918} 2919 2920/* 2921 * Device resume routine. Restore some PCI settings in case the BIOS 2922 * doesn't, re-enable busmastering, and restart the interface if 2923 * appropriate. 2924 */ 2925static int 2926re_resume(device_t dev) 2927{ 2928 struct rl_softc *sc; 2929 struct ifnet *ifp; 2930 2931 sc = device_get_softc(dev); 2932 2933 RL_LOCK(sc); 2934 2935 ifp = sc->rl_ifp; 2936 2937 /* reinitialize interface if necessary */ 2938 if (ifp->if_flags & IFF_UP) 2939 re_init_locked(sc); 2940 2941 /* 2942 * Clear WOL matching such that normal Rx filtering 2943 * wouldn't interfere with WOL patterns. 2944 */ 2945 re_clrwol(sc); 2946 sc->suspended = 0; 2947 RL_UNLOCK(sc); 2948 2949 return (0); 2950} 2951 2952/* 2953 * Stop all chip I/O so that the kernel's probe routines don't 2954 * get confused by errant DMAs when rebooting. 2955 */ 2956static int 2957re_shutdown(device_t dev) 2958{ 2959 struct rl_softc *sc; 2960 2961 sc = device_get_softc(dev); 2962 2963 RL_LOCK(sc); 2964 re_stop(sc); 2965 /* 2966 * Mark interface as down since otherwise we will panic if 2967 * interrupt comes in later on, which can happen in some 2968 * cases. 2969 */ 2970 sc->rl_ifp->if_flags &= ~IFF_UP; 2971 re_setwol(sc); 2972 RL_UNLOCK(sc); 2973 2974 return (0); 2975} 2976 2977static void 2978re_setwol(struct rl_softc *sc) 2979{ 2980 struct ifnet *ifp; 2981 int pmc; 2982 uint16_t pmstat; 2983 uint8_t v; 2984 2985 RL_LOCK_ASSERT(sc); 2986 2987 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2988 return; 2989 2990 ifp = sc->rl_ifp; 2991 /* Enable config register write. */ 2992 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2993 2994 /* Enable PME. */ 2995 v = CSR_READ_1(sc, RL_CFG1); 2996 v &= ~RL_CFG1_PME; 2997 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2998 v |= RL_CFG1_PME; 2999 CSR_WRITE_1(sc, RL_CFG1, v); 3000 3001 v = CSR_READ_1(sc, RL_CFG3); 3002 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3003 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3004 v |= RL_CFG3_WOL_MAGIC; 3005 CSR_WRITE_1(sc, RL_CFG3, v); 3006 3007 /* Config register write done. */ 3008 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3009 3010 v = CSR_READ_1(sc, RL_CFG5); 3011 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3012 v &= ~RL_CFG5_WOL_LANWAKE; 3013 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3014 v |= RL_CFG5_WOL_UCAST; 3015 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3016 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3017 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3018 v |= RL_CFG5_WOL_LANWAKE; 3019 CSR_WRITE_1(sc, RL_CFG5, v); 3020 3021 /* 3022 * It seems that hardware resets its link speed to 100Mbps in 3023 * power down mode so switching to 100Mbps in driver is not 3024 * needed. 3025 */ 3026 3027 /* Request PME if WOL is requested. */ 3028 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3029 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3030 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3031 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3032 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3033} 3034 3035static void 3036re_clrwol(struct rl_softc *sc) 3037{ 3038 int pmc; 3039 uint8_t v; 3040 3041 RL_LOCK_ASSERT(sc); 3042 3043 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3044 return; 3045 3046 /* Enable config register write. */ 3047 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3048 3049 v = CSR_READ_1(sc, RL_CFG3); 3050 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3051 CSR_WRITE_1(sc, RL_CFG3, v); 3052 3053 /* Config register write done. */ 3054 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3055 3056 v = CSR_READ_1(sc, RL_CFG5); 3057 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3058 v &= ~RL_CFG5_WOL_LANWAKE; 3059 CSR_WRITE_1(sc, RL_CFG5, v); 3060} 3061