if_re.c revision 181270
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 181270 2008-08-04 02:05:09Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* Tunables. */ 159static int msi_disable = 1; 160TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164/* 165 * Various supported device vendors/types and their names. 166 */ 167static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8168C/8168CP/8111B/8111C/8111CP PCIe " 176 "Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8169, 0, 178 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 182 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 183 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 184 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 185 { USR_VENDORID, USR_DEVICEID_997902, 0, 186 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 187}; 188 189static struct rl_hwrev re_hwrevs[] = { 190 { RL_HWREV_8139, RL_8139, "" }, 191 { RL_HWREV_8139A, RL_8139, "A" }, 192 { RL_HWREV_8139AG, RL_8139, "A-G" }, 193 { RL_HWREV_8139B, RL_8139, "B" }, 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 204 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL"}, 205 { RL_HWREV_8100, RL_8139, "8100"}, 206 { RL_HWREV_8101, RL_8139, "8101"}, 207 { RL_HWREV_8100E, RL_8169, "8100E"}, 208 { RL_HWREV_8101E, RL_8169, "8101E"}, 209 { RL_HWREV_8102E, RL_8169, "8102E"}, 210 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 211 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 212 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 213 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 214 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 215 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 216 { 0, 0, NULL } 217}; 218 219static int re_probe (device_t); 220static int re_attach (device_t); 221static int re_detach (device_t); 222 223static int re_encap (struct rl_softc *, struct mbuf **); 224 225static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 226static int re_allocmem (device_t, struct rl_softc *); 227static __inline void re_discard_rxbuf 228 (struct rl_softc *, int); 229static int re_newbuf (struct rl_softc *, int); 230static int re_rx_list_init (struct rl_softc *); 231static int re_tx_list_init (struct rl_softc *); 232#ifdef RE_FIXUP_RX 233static __inline void re_fixup_rx 234 (struct mbuf *); 235#endif 236static int re_rxeof (struct rl_softc *); 237static void re_txeof (struct rl_softc *); 238#ifdef DEVICE_POLLING 239static void re_poll (struct ifnet *, enum poll_cmd, int); 240static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 241#endif 242static int re_intr (void *); 243static void re_tick (void *); 244static void re_tx_task (void *, int); 245static void re_int_task (void *, int); 246static void re_start (struct ifnet *); 247static int re_ioctl (struct ifnet *, u_long, caddr_t); 248static void re_init (void *); 249static void re_init_locked (struct rl_softc *); 250static void re_stop (struct rl_softc *); 251static void re_watchdog (struct rl_softc *); 252static int re_suspend (device_t); 253static int re_resume (device_t); 254static int re_shutdown (device_t); 255static int re_ifmedia_upd (struct ifnet *); 256static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 257 258static void re_eeprom_putbyte (struct rl_softc *, int); 259static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 260static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 261static int re_gmii_readreg (device_t, int, int); 262static int re_gmii_writereg (device_t, int, int, int); 263 264static int re_miibus_readreg (device_t, int, int); 265static int re_miibus_writereg (device_t, int, int, int); 266static void re_miibus_statchg (device_t); 267 268static void re_setmulti (struct rl_softc *); 269static void re_reset (struct rl_softc *); 270static void re_setwol (struct rl_softc *); 271static void re_clrwol (struct rl_softc *); 272 273#ifdef RE_DIAG 274static int re_diag (struct rl_softc *); 275#endif 276 277static device_method_t re_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, re_probe), 280 DEVMETHOD(device_attach, re_attach), 281 DEVMETHOD(device_detach, re_detach), 282 DEVMETHOD(device_suspend, re_suspend), 283 DEVMETHOD(device_resume, re_resume), 284 DEVMETHOD(device_shutdown, re_shutdown), 285 286 /* bus interface */ 287 DEVMETHOD(bus_print_child, bus_generic_print_child), 288 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 289 290 /* MII interface */ 291 DEVMETHOD(miibus_readreg, re_miibus_readreg), 292 DEVMETHOD(miibus_writereg, re_miibus_writereg), 293 DEVMETHOD(miibus_statchg, re_miibus_statchg), 294 295 { 0, 0 } 296}; 297 298static driver_t re_driver = { 299 "re", 300 re_methods, 301 sizeof(struct rl_softc) 302}; 303 304static devclass_t re_devclass; 305 306DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 307DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 308DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 309 310#define EE_SET(x) \ 311 CSR_WRITE_1(sc, RL_EECMD, \ 312 CSR_READ_1(sc, RL_EECMD) | x) 313 314#define EE_CLR(x) \ 315 CSR_WRITE_1(sc, RL_EECMD, \ 316 CSR_READ_1(sc, RL_EECMD) & ~x) 317 318/* 319 * Send a read command and address to the EEPROM, check for ACK. 320 */ 321static void 322re_eeprom_putbyte(sc, addr) 323 struct rl_softc *sc; 324 int addr; 325{ 326 register int d, i; 327 328 d = addr | (RL_9346_READ << sc->rl_eewidth); 329 330 /* 331 * Feed in each bit and strobe the clock. 332 */ 333 334 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 335 if (d & i) { 336 EE_SET(RL_EE_DATAIN); 337 } else { 338 EE_CLR(RL_EE_DATAIN); 339 } 340 DELAY(100); 341 EE_SET(RL_EE_CLK); 342 DELAY(150); 343 EE_CLR(RL_EE_CLK); 344 DELAY(100); 345 } 346 347 return; 348} 349 350/* 351 * Read a word of data stored in the EEPROM at address 'addr.' 352 */ 353static void 354re_eeprom_getword(sc, addr, dest) 355 struct rl_softc *sc; 356 int addr; 357 u_int16_t *dest; 358{ 359 register int i; 360 u_int16_t word = 0; 361 362 /* 363 * Send address of word we want to read. 364 */ 365 re_eeprom_putbyte(sc, addr); 366 367 /* 368 * Start reading bits from EEPROM. 369 */ 370 for (i = 0x8000; i; i >>= 1) { 371 EE_SET(RL_EE_CLK); 372 DELAY(100); 373 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 374 word |= i; 375 EE_CLR(RL_EE_CLK); 376 DELAY(100); 377 } 378 379 *dest = word; 380 381 return; 382} 383 384/* 385 * Read a sequence of words from the EEPROM. 386 */ 387static void 388re_read_eeprom(sc, dest, off, cnt) 389 struct rl_softc *sc; 390 caddr_t dest; 391 int off; 392 int cnt; 393{ 394 int i; 395 u_int16_t word = 0, *ptr; 396 397 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 398 399 DELAY(100); 400 401 for (i = 0; i < cnt; i++) { 402 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 403 re_eeprom_getword(sc, off + i, &word); 404 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 405 ptr = (u_int16_t *)(dest + (i * 2)); 406 *ptr = word; 407 } 408 409 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 410 411 return; 412} 413 414static int 415re_gmii_readreg(dev, phy, reg) 416 device_t dev; 417 int phy, reg; 418{ 419 struct rl_softc *sc; 420 u_int32_t rval; 421 int i; 422 423 if (phy != 1) 424 return (0); 425 426 sc = device_get_softc(dev); 427 428 /* Let the rgephy driver read the GMEDIASTAT register */ 429 430 if (reg == RL_GMEDIASTAT) { 431 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 432 return (rval); 433 } 434 435 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 436 DELAY(1000); 437 438 for (i = 0; i < RL_TIMEOUT; i++) { 439 rval = CSR_READ_4(sc, RL_PHYAR); 440 if (rval & RL_PHYAR_BUSY) 441 break; 442 DELAY(100); 443 } 444 445 if (i == RL_TIMEOUT) { 446 device_printf(sc->rl_dev, "PHY read failed\n"); 447 return (0); 448 } 449 450 return (rval & RL_PHYAR_PHYDATA); 451} 452 453static int 454re_gmii_writereg(dev, phy, reg, data) 455 device_t dev; 456 int phy, reg, data; 457{ 458 struct rl_softc *sc; 459 u_int32_t rval; 460 int i; 461 462 sc = device_get_softc(dev); 463 464 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 465 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 466 DELAY(1000); 467 468 for (i = 0; i < RL_TIMEOUT; i++) { 469 rval = CSR_READ_4(sc, RL_PHYAR); 470 if (!(rval & RL_PHYAR_BUSY)) 471 break; 472 DELAY(100); 473 } 474 475 if (i == RL_TIMEOUT) { 476 device_printf(sc->rl_dev, "PHY write failed\n"); 477 return (0); 478 } 479 480 return (0); 481} 482 483static int 484re_miibus_readreg(dev, phy, reg) 485 device_t dev; 486 int phy, reg; 487{ 488 struct rl_softc *sc; 489 u_int16_t rval = 0; 490 u_int16_t re8139_reg = 0; 491 492 sc = device_get_softc(dev); 493 494 if (sc->rl_type == RL_8169) { 495 rval = re_gmii_readreg(dev, phy, reg); 496 return (rval); 497 } 498 499 /* Pretend the internal PHY is only at address 0 */ 500 if (phy) { 501 return (0); 502 } 503 switch (reg) { 504 case MII_BMCR: 505 re8139_reg = RL_BMCR; 506 break; 507 case MII_BMSR: 508 re8139_reg = RL_BMSR; 509 break; 510 case MII_ANAR: 511 re8139_reg = RL_ANAR; 512 break; 513 case MII_ANER: 514 re8139_reg = RL_ANER; 515 break; 516 case MII_ANLPAR: 517 re8139_reg = RL_LPAR; 518 break; 519 case MII_PHYIDR1: 520 case MII_PHYIDR2: 521 return (0); 522 /* 523 * Allow the rlphy driver to read the media status 524 * register. If we have a link partner which does not 525 * support NWAY, this is the register which will tell 526 * us the results of parallel detection. 527 */ 528 case RL_MEDIASTAT: 529 rval = CSR_READ_1(sc, RL_MEDIASTAT); 530 return (rval); 531 default: 532 device_printf(sc->rl_dev, "bad phy register\n"); 533 return (0); 534 } 535 rval = CSR_READ_2(sc, re8139_reg); 536 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 537 /* 8139C+ has different bit layout. */ 538 rval &= ~(BMCR_LOOP | BMCR_ISO); 539 } 540 return (rval); 541} 542 543static int 544re_miibus_writereg(dev, phy, reg, data) 545 device_t dev; 546 int phy, reg, data; 547{ 548 struct rl_softc *sc; 549 u_int16_t re8139_reg = 0; 550 int rval = 0; 551 552 sc = device_get_softc(dev); 553 554 if (sc->rl_type == RL_8169) { 555 rval = re_gmii_writereg(dev, phy, reg, data); 556 return (rval); 557 } 558 559 /* Pretend the internal PHY is only at address 0 */ 560 if (phy) 561 return (0); 562 563 switch (reg) { 564 case MII_BMCR: 565 re8139_reg = RL_BMCR; 566 if (sc->rl_type == RL_8139CPLUS) { 567 /* 8139C+ has different bit layout. */ 568 data &= ~(BMCR_LOOP | BMCR_ISO); 569 } 570 break; 571 case MII_BMSR: 572 re8139_reg = RL_BMSR; 573 break; 574 case MII_ANAR: 575 re8139_reg = RL_ANAR; 576 break; 577 case MII_ANER: 578 re8139_reg = RL_ANER; 579 break; 580 case MII_ANLPAR: 581 re8139_reg = RL_LPAR; 582 break; 583 case MII_PHYIDR1: 584 case MII_PHYIDR2: 585 return (0); 586 break; 587 default: 588 device_printf(sc->rl_dev, "bad phy register\n"); 589 return (0); 590 } 591 CSR_WRITE_2(sc, re8139_reg, data); 592 return (0); 593} 594 595static void 596re_miibus_statchg(dev) 597 device_t dev; 598{ 599 600} 601 602/* 603 * Program the 64-bit multicast hash filter. 604 */ 605static void 606re_setmulti(sc) 607 struct rl_softc *sc; 608{ 609 struct ifnet *ifp; 610 int h = 0; 611 u_int32_t hashes[2] = { 0, 0 }; 612 struct ifmultiaddr *ifma; 613 u_int32_t rxfilt; 614 int mcnt = 0; 615 616 RL_LOCK_ASSERT(sc); 617 618 ifp = sc->rl_ifp; 619 620 621 rxfilt = CSR_READ_4(sc, RL_RXCFG); 622 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 623 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 624 if (ifp->if_flags & IFF_PROMISC) 625 rxfilt |= RL_RXCFG_RX_ALLPHYS; 626 /* 627 * Unlike other hardwares, we have to explicitly set 628 * RL_RXCFG_RX_MULTI to receive multicast frames in 629 * promiscuous mode. 630 */ 631 rxfilt |= RL_RXCFG_RX_MULTI; 632 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 633 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 634 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 635 return; 636 } 637 638 /* first, zot all the existing hash bits */ 639 CSR_WRITE_4(sc, RL_MAR0, 0); 640 CSR_WRITE_4(sc, RL_MAR4, 0); 641 642 /* now program new ones */ 643 IF_ADDR_LOCK(ifp); 644 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 645 if (ifma->ifma_addr->sa_family != AF_LINK) 646 continue; 647 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 648 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 649 if (h < 32) 650 hashes[0] |= (1 << h); 651 else 652 hashes[1] |= (1 << (h - 32)); 653 mcnt++; 654 } 655 IF_ADDR_UNLOCK(ifp); 656 657 if (mcnt) 658 rxfilt |= RL_RXCFG_RX_MULTI; 659 else 660 rxfilt &= ~RL_RXCFG_RX_MULTI; 661 662 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 663 664 /* 665 * For some unfathomable reason, RealTek decided to reverse 666 * the order of the multicast hash registers in the PCI Express 667 * parts. This means we have to write the hash pattern in reverse 668 * order for those devices. 669 */ 670 671 if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) { 672 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 673 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 674 } else { 675 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 676 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 677 } 678} 679 680static void 681re_reset(sc) 682 struct rl_softc *sc; 683{ 684 register int i; 685 686 RL_LOCK_ASSERT(sc); 687 688 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 689 690 for (i = 0; i < RL_TIMEOUT; i++) { 691 DELAY(10); 692 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 693 break; 694 } 695 if (i == RL_TIMEOUT) 696 device_printf(sc->rl_dev, "reset never completed!\n"); 697 698 CSR_WRITE_1(sc, 0x82, 1); 699} 700 701#ifdef RE_DIAG 702 703/* 704 * The following routine is designed to test for a defect on some 705 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 706 * lines connected to the bus, however for a 32-bit only card, they 707 * should be pulled high. The result of this defect is that the 708 * NIC will not work right if you plug it into a 64-bit slot: DMA 709 * operations will be done with 64-bit transfers, which will fail 710 * because the 64-bit data lines aren't connected. 711 * 712 * There's no way to work around this (short of talking a soldering 713 * iron to the board), however we can detect it. The method we use 714 * here is to put the NIC into digital loopback mode, set the receiver 715 * to promiscuous mode, and then try to send a frame. We then compare 716 * the frame data we sent to what was received. If the data matches, 717 * then the NIC is working correctly, otherwise we know the user has 718 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 719 * slot. In the latter case, there's no way the NIC can work correctly, 720 * so we print out a message on the console and abort the device attach. 721 */ 722 723static int 724re_diag(sc) 725 struct rl_softc *sc; 726{ 727 struct ifnet *ifp = sc->rl_ifp; 728 struct mbuf *m0; 729 struct ether_header *eh; 730 struct rl_desc *cur_rx; 731 u_int16_t status; 732 u_int32_t rxstat; 733 int total_len, i, error = 0, phyaddr; 734 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 735 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 736 737 /* Allocate a single mbuf */ 738 MGETHDR(m0, M_DONTWAIT, MT_DATA); 739 if (m0 == NULL) 740 return (ENOBUFS); 741 742 RL_LOCK(sc); 743 744 /* 745 * Initialize the NIC in test mode. This sets the chip up 746 * so that it can send and receive frames, but performs the 747 * following special functions: 748 * - Puts receiver in promiscuous mode 749 * - Enables digital loopback mode 750 * - Leaves interrupts turned off 751 */ 752 753 ifp->if_flags |= IFF_PROMISC; 754 sc->rl_testmode = 1; 755 re_reset(sc); 756 re_init_locked(sc); 757 sc->rl_flags |= RL_FLAG_LINK; 758 if (sc->rl_type == RL_8169) 759 phyaddr = 1; 760 else 761 phyaddr = 0; 762 763 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 764 for (i = 0; i < RL_TIMEOUT; i++) { 765 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 766 if (!(status & BMCR_RESET)) 767 break; 768 } 769 770 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 771 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 772 773 DELAY(100000); 774 775 /* Put some data in the mbuf */ 776 777 eh = mtod(m0, struct ether_header *); 778 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 779 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 780 eh->ether_type = htons(ETHERTYPE_IP); 781 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 782 783 /* 784 * Queue the packet, start transmission. 785 * Note: IF_HANDOFF() ultimately calls re_start() for us. 786 */ 787 788 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 789 RL_UNLOCK(sc); 790 /* XXX: re_diag must not be called when in ALTQ mode */ 791 IF_HANDOFF(&ifp->if_snd, m0, ifp); 792 RL_LOCK(sc); 793 m0 = NULL; 794 795 /* Wait for it to propagate through the chip */ 796 797 DELAY(100000); 798 for (i = 0; i < RL_TIMEOUT; i++) { 799 status = CSR_READ_2(sc, RL_ISR); 800 CSR_WRITE_2(sc, RL_ISR, status); 801 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 802 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 803 break; 804 DELAY(10); 805 } 806 807 if (i == RL_TIMEOUT) { 808 device_printf(sc->rl_dev, 809 "diagnostic failed, failed to receive packet in" 810 " loopback mode\n"); 811 error = EIO; 812 goto done; 813 } 814 815 /* 816 * The packet should have been dumped into the first 817 * entry in the RX DMA ring. Grab it from there. 818 */ 819 820 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 821 sc->rl_ldata.rl_rx_list_map, 822 BUS_DMASYNC_POSTREAD); 823 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 824 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 825 BUS_DMASYNC_POSTREAD); 826 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 827 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 828 829 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 830 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 831 eh = mtod(m0, struct ether_header *); 832 833 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 834 total_len = RL_RXBYTES(cur_rx); 835 rxstat = le32toh(cur_rx->rl_cmdstat); 836 837 if (total_len != ETHER_MIN_LEN) { 838 device_printf(sc->rl_dev, 839 "diagnostic failed, received short packet\n"); 840 error = EIO; 841 goto done; 842 } 843 844 /* Test that the received packet data matches what we sent. */ 845 846 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 847 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 848 ntohs(eh->ether_type) != ETHERTYPE_IP) { 849 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 850 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 851 dst, ":", src, ":", ETHERTYPE_IP); 852 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 853 eh->ether_dhost, ":", eh->ether_shost, ":", 854 ntohs(eh->ether_type)); 855 device_printf(sc->rl_dev, "You may have a defective 32-bit " 856 "NIC plugged into a 64-bit PCI slot.\n"); 857 device_printf(sc->rl_dev, "Please re-install the NIC in a " 858 "32-bit slot for proper operation.\n"); 859 device_printf(sc->rl_dev, "Read the re(4) man page for more " 860 "details.\n"); 861 error = EIO; 862 } 863 864done: 865 /* Turn interface off, release resources */ 866 867 sc->rl_testmode = 0; 868 sc->rl_flags &= ~RL_FLAG_LINK; 869 ifp->if_flags &= ~IFF_PROMISC; 870 re_stop(sc); 871 if (m0 != NULL) 872 m_freem(m0); 873 874 RL_UNLOCK(sc); 875 876 return (error); 877} 878 879#endif 880 881/* 882 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 883 * IDs against our list and return a device name if we find a match. 884 */ 885static int 886re_probe(dev) 887 device_t dev; 888{ 889 struct rl_type *t; 890 uint16_t devid, vendor; 891 uint16_t revid, sdevid; 892 int i; 893 894 vendor = pci_get_vendor(dev); 895 devid = pci_get_device(dev); 896 revid = pci_get_revid(dev); 897 sdevid = pci_get_subdevice(dev); 898 899 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 900 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 901 /* 902 * Only attach to rev. 3 of the Linksys EG1032 adapter. 903 * Rev. 2 is supported by sk(4). 904 */ 905 return (ENXIO); 906 } 907 } 908 909 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 910 if (revid != 0x20) { 911 /* 8139, let rl(4) take care of this device. */ 912 return (ENXIO); 913 } 914 } 915 916 t = re_devs; 917 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 918 if (vendor == t->rl_vid && devid == t->rl_did) { 919 device_set_desc(dev, t->rl_name); 920 return (BUS_PROBE_DEFAULT); 921 } 922 } 923 924 return (ENXIO); 925} 926 927/* 928 * Map a single buffer address. 929 */ 930 931static void 932re_dma_map_addr(arg, segs, nseg, error) 933 void *arg; 934 bus_dma_segment_t *segs; 935 int nseg; 936 int error; 937{ 938 bus_addr_t *addr; 939 940 if (error) 941 return; 942 943 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 944 addr = arg; 945 *addr = segs->ds_addr; 946} 947 948static int 949re_allocmem(dev, sc) 950 device_t dev; 951 struct rl_softc *sc; 952{ 953 bus_size_t rx_list_size, tx_list_size; 954 int error; 955 int i; 956 957 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 958 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 959 960 /* 961 * Allocate the parent bus DMA tag appropriate for PCI. 962 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 963 * register should be set. However some RealTek chips are known 964 * to be buggy on DAC handling, therefore disable DAC by limiting 965 * DMA address space to 32bit. PCIe variants of RealTek chips 966 * may not have the limitation but I took safer path. 967 */ 968 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 969 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 970 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 971 NULL, NULL, &sc->rl_parent_tag); 972 if (error) { 973 device_printf(dev, "could not allocate parent DMA tag\n"); 974 return (error); 975 } 976 977 /* 978 * Allocate map for TX mbufs. 979 */ 980 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 981 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 982 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 983 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 984 if (error) { 985 device_printf(dev, "could not allocate TX DMA tag\n"); 986 return (error); 987 } 988 989 /* 990 * Allocate map for RX mbufs. 991 */ 992 993 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 994 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 995 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 996 if (error) { 997 device_printf(dev, "could not allocate RX DMA tag\n"); 998 return (error); 999 } 1000 1001 /* 1002 * Allocate map for TX descriptor list. 1003 */ 1004 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1005 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1006 NULL, tx_list_size, 1, tx_list_size, 0, 1007 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1008 if (error) { 1009 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1010 return (error); 1011 } 1012 1013 /* Allocate DMA'able memory for the TX ring */ 1014 1015 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1016 (void **)&sc->rl_ldata.rl_tx_list, 1017 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1018 &sc->rl_ldata.rl_tx_list_map); 1019 if (error) { 1020 device_printf(dev, "could not allocate TX DMA ring\n"); 1021 return (error); 1022 } 1023 1024 /* Load the map for the TX ring. */ 1025 1026 sc->rl_ldata.rl_tx_list_addr = 0; 1027 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1028 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1029 tx_list_size, re_dma_map_addr, 1030 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1031 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1032 device_printf(dev, "could not load TX DMA ring\n"); 1033 return (ENOMEM); 1034 } 1035 1036 /* Create DMA maps for TX buffers */ 1037 1038 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1039 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1040 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1041 if (error) { 1042 device_printf(dev, "could not create DMA map for TX\n"); 1043 return (error); 1044 } 1045 } 1046 1047 /* 1048 * Allocate map for RX descriptor list. 1049 */ 1050 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1051 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1052 NULL, rx_list_size, 1, rx_list_size, 0, 1053 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1054 if (error) { 1055 device_printf(dev, "could not create RX DMA ring tag\n"); 1056 return (error); 1057 } 1058 1059 /* Allocate DMA'able memory for the RX ring */ 1060 1061 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1062 (void **)&sc->rl_ldata.rl_rx_list, 1063 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1064 &sc->rl_ldata.rl_rx_list_map); 1065 if (error) { 1066 device_printf(dev, "could not allocate RX DMA ring\n"); 1067 return (error); 1068 } 1069 1070 /* Load the map for the RX ring. */ 1071 1072 sc->rl_ldata.rl_rx_list_addr = 0; 1073 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1074 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1075 rx_list_size, re_dma_map_addr, 1076 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1077 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1078 device_printf(dev, "could not load RX DMA ring\n"); 1079 return (ENOMEM); 1080 } 1081 1082 /* Create DMA maps for RX buffers */ 1083 1084 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1085 &sc->rl_ldata.rl_rx_sparemap); 1086 if (error) { 1087 device_printf(dev, "could not create spare DMA map for RX\n"); 1088 return (error); 1089 } 1090 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1091 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1092 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1093 if (error) { 1094 device_printf(dev, "could not create DMA map for RX\n"); 1095 return (error); 1096 } 1097 } 1098 1099 return (0); 1100} 1101 1102/* 1103 * Attach the interface. Allocate softc structures, do ifmedia 1104 * setup and ethernet/BPF attach. 1105 */ 1106static int 1107re_attach(dev) 1108 device_t dev; 1109{ 1110 u_char eaddr[ETHER_ADDR_LEN]; 1111 u_int16_t as[ETHER_ADDR_LEN / 2]; 1112 struct rl_softc *sc; 1113 struct ifnet *ifp; 1114 struct rl_hwrev *hw_rev; 1115 int hwrev; 1116 u_int16_t devid, re_did = 0; 1117 int error = 0, rid, i; 1118 int msic, reg; 1119 uint8_t cfg; 1120 1121 sc = device_get_softc(dev); 1122 sc->rl_dev = dev; 1123 1124 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1125 MTX_DEF); 1126 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1127 1128 /* 1129 * Map control/status registers. 1130 */ 1131 pci_enable_busmaster(dev); 1132 1133 devid = pci_get_device(dev); 1134 /* Prefer memory space register mapping over IO space. */ 1135 sc->rl_res_id = PCIR_BAR(1); 1136 sc->rl_res_type = SYS_RES_MEMORY; 1137 /* RTL8168/8101E seems to use different BARs. */ 1138 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1139 sc->rl_res_id = PCIR_BAR(2); 1140 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1141 &sc->rl_res_id, RF_ACTIVE); 1142 1143 if (sc->rl_res == NULL) { 1144 sc->rl_res_id = PCIR_BAR(0); 1145 sc->rl_res_type = SYS_RES_IOPORT; 1146 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1147 &sc->rl_res_id, RF_ACTIVE); 1148 if (sc->rl_res == NULL) { 1149 device_printf(dev, "couldn't map ports/memory\n"); 1150 error = ENXIO; 1151 goto fail; 1152 } 1153 } 1154 1155 sc->rl_btag = rman_get_bustag(sc->rl_res); 1156 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1157 1158 msic = 0; 1159 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1160 msic = pci_msi_count(dev); 1161 if (bootverbose) 1162 device_printf(dev, "MSI count : %d\n", msic); 1163 } 1164 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1165 if (pci_alloc_msi(dev, &msic) == 0) { 1166 if (msic == RL_MSI_MESSAGES) { 1167 device_printf(dev, "Using %d MSI messages\n", 1168 msic); 1169 sc->rl_flags |= RL_FLAG_MSI; 1170 /* Explicitly set MSI enable bit. */ 1171 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1172 cfg = CSR_READ_1(sc, RL_CFG2); 1173 cfg |= RL_CFG2_MSI; 1174 CSR_WRITE_1(sc, RL_CFG2, cfg); 1175 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1176 } else 1177 pci_release_msi(dev); 1178 } 1179 } 1180 1181 /* Allocate interrupt */ 1182 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1183 rid = 0; 1184 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1185 RF_SHAREABLE | RF_ACTIVE); 1186 if (sc->rl_irq[0] == NULL) { 1187 device_printf(dev, "couldn't allocate IRQ resources\n"); 1188 error = ENXIO; 1189 goto fail; 1190 } 1191 } else { 1192 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1193 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1194 SYS_RES_IRQ, &rid, RF_ACTIVE); 1195 if (sc->rl_irq[i] == NULL) { 1196 device_printf(dev, 1197 "couldn't llocate IRQ resources for " 1198 "message %d\n", rid); 1199 error = ENXIO; 1200 goto fail; 1201 } 1202 } 1203 } 1204 1205 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1206 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1207 cfg = CSR_READ_1(sc, RL_CFG2); 1208 if ((cfg & RL_CFG2_MSI) != 0) { 1209 device_printf(dev, "turning off MSI enable bit.\n"); 1210 cfg &= ~RL_CFG2_MSI; 1211 CSR_WRITE_1(sc, RL_CFG2, cfg); 1212 } 1213 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1214 } 1215 1216 /* Reset the adapter. */ 1217 RL_LOCK(sc); 1218 re_reset(sc); 1219 RL_UNLOCK(sc); 1220 1221 hw_rev = re_hwrevs; 1222 hwrev = CSR_READ_4(sc, RL_TXCFG); 1223 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1224 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1225 hwrev &= RL_TXCFG_HWREV; 1226 while (hw_rev->rl_desc != NULL) { 1227 if (hw_rev->rl_rev == hwrev) { 1228 sc->rl_type = hw_rev->rl_type; 1229 break; 1230 } 1231 hw_rev++; 1232 } 1233 if (hw_rev->rl_desc == NULL) { 1234 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1235 error = ENXIO; 1236 goto fail; 1237 } 1238 1239 switch (hw_rev->rl_rev) { 1240 case RL_HWREV_8139CPLUS: 1241 sc->rl_flags |= RL_FLAG_NOJUMBO; 1242 break; 1243 case RL_HWREV_8100E: 1244 case RL_HWREV_8101E: 1245 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1246 RL_FLAG_PHYWAKE; 1247 break; 1248 case RL_HWREV_8102E: 1249 case RL_HWREV_8102EL: 1250 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1251 RL_FLAG_PHYWAKE | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; 1252 break; 1253 case RL_HWREV_8168_SPIN1: 1254 case RL_HWREV_8168_SPIN2: 1255 case RL_HWREV_8168_SPIN3: 1256 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1257 RL_FLAG_MACSTAT; 1258 break; 1259 case RL_HWREV_8168C: 1260 case RL_HWREV_8168C_SPIN2: 1261 case RL_HWREV_8168CP: 1262 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1263 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; 1264 /* 1265 * These controllers support jumbo frame but it seems 1266 * that enabling it requires touching additional magic 1267 * registers. Depending on MAC revisions some 1268 * controllers need to disable checksum offload. So 1269 * disable jumbo frame until I have better idea what 1270 * it really requires to make it support. 1271 * RTL8168C/CP : supports up to 6KB jumbo frame. 1272 * RTL8111C/CP : supports up to 9KB jumbo frame. 1273 */ 1274 sc->rl_flags |= RL_FLAG_NOJUMBO; 1275 break; 1276 case RL_HWREV_8169_8110SB: 1277 case RL_HWREV_8169_8110SC: 1278 case RL_HWREV_8169_8110SBL: 1279 sc->rl_flags |= RL_FLAG_PHYWAKE; 1280 break; 1281 default: 1282 break; 1283 } 1284 1285 /* Enable PME. */ 1286 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1287 cfg = CSR_READ_1(sc, RL_CFG1); 1288 cfg |= RL_CFG1_PME; 1289 CSR_WRITE_1(sc, RL_CFG1, cfg); 1290 cfg = CSR_READ_1(sc, RL_CFG5); 1291 cfg &= RL_CFG5_PME_STS; 1292 CSR_WRITE_1(sc, RL_CFG5, cfg); 1293 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1294 1295 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1296 /* 1297 * XXX Should have a better way to extract station 1298 * address from EEPROM. 1299 */ 1300 for (i = 0; i < ETHER_ADDR_LEN; i++) 1301 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1302 } else { 1303 sc->rl_eewidth = RL_9356_ADDR_LEN; 1304 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1305 if (re_did != 0x8129) 1306 sc->rl_eewidth = RL_9346_ADDR_LEN; 1307 1308 /* 1309 * Get station address from the EEPROM. 1310 */ 1311 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1312 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1313 as[i] = le16toh(as[i]); 1314 bcopy(as, eaddr, sizeof(eaddr)); 1315 } 1316 1317 if (sc->rl_type == RL_8169) { 1318 /* Set RX length mask and number of descriptors. */ 1319 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1320 sc->rl_txstart = RL_GTXSTART; 1321 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1322 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1323 } else { 1324 /* Set RX length mask and number of descriptors. */ 1325 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1326 sc->rl_txstart = RL_TXSTART; 1327 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1328 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1329 } 1330 1331 error = re_allocmem(dev, sc); 1332 if (error) 1333 goto fail; 1334 1335 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1336 if (ifp == NULL) { 1337 device_printf(dev, "can not if_alloc()\n"); 1338 error = ENOSPC; 1339 goto fail; 1340 } 1341 1342 /* Take PHY out of power down mode. */ 1343 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1344 re_gmii_writereg(dev, 1, 0x1f, 0); 1345 re_gmii_writereg(dev, 1, 0x0e, 0); 1346 } 1347 1348 /* Do MII setup */ 1349 if (mii_phy_probe(dev, &sc->rl_miibus, 1350 re_ifmedia_upd, re_ifmedia_sts)) { 1351 device_printf(dev, "MII without any phy!\n"); 1352 error = ENXIO; 1353 goto fail; 1354 } 1355 1356 ifp->if_softc = sc; 1357 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1358 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1359 ifp->if_ioctl = re_ioctl; 1360 ifp->if_start = re_start; 1361 ifp->if_hwassist = RE_CSUM_FEATURES; 1362 ifp->if_capabilities = IFCAP_HWCSUM; 1363 ifp->if_capenable = ifp->if_capabilities; 1364 ifp->if_init = re_init; 1365 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1366 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1367 IFQ_SET_READY(&ifp->if_snd); 1368 1369 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1370 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1371 1372 /* 1373 * XXX 1374 * Still have no idea how to make TSO work on 8168C, 8168CP, 1375 * 8111C and 8111CP. 1376 */ 1377 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1378 ifp->if_hwassist |= CSUM_TSO; 1379 ifp->if_capabilities |= IFCAP_TSO4; 1380 } 1381 1382 /* 1383 * Call MI attach routine. 1384 */ 1385 ether_ifattach(ifp, eaddr); 1386 1387 /* VLAN capability setup */ 1388 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1389 if (ifp->if_capabilities & IFCAP_HWCSUM) 1390 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1391 /* Enable WOL if PM is supported. */ 1392 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1393 ifp->if_capabilities |= IFCAP_WOL; 1394 ifp->if_capenable = ifp->if_capabilities; 1395#ifdef DEVICE_POLLING 1396 ifp->if_capabilities |= IFCAP_POLLING; 1397#endif 1398 /* 1399 * Tell the upper layer(s) we support long frames. 1400 * Must appear after the call to ether_ifattach() because 1401 * ether_ifattach() sets ifi_hdrlen to the default value. 1402 */ 1403 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1404 1405#ifdef RE_DIAG 1406 /* 1407 * Perform hardware diagnostic on the original RTL8169. 1408 * Some 32-bit cards were incorrectly wired and would 1409 * malfunction if plugged into a 64-bit slot. 1410 */ 1411 1412 if (hwrev == RL_HWREV_8169) { 1413 error = re_diag(sc); 1414 if (error) { 1415 device_printf(dev, 1416 "attach aborted due to hardware diag failure\n"); 1417 ether_ifdetach(ifp); 1418 goto fail; 1419 } 1420 } 1421#endif 1422 1423 /* Hook interrupt last to avoid having to lock softc */ 1424 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1425 error = bus_setup_intr(dev, sc->rl_irq[0], 1426 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1427 &sc->rl_intrhand[0]); 1428 else { 1429 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1430 error = bus_setup_intr(dev, sc->rl_irq[i], 1431 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1432 &sc->rl_intrhand[i]); 1433 if (error != 0) 1434 break; 1435 } 1436 } 1437 if (error) { 1438 device_printf(dev, "couldn't set up irq\n"); 1439 ether_ifdetach(ifp); 1440 } 1441 1442fail: 1443 1444 if (error) 1445 re_detach(dev); 1446 1447 return (error); 1448} 1449 1450/* 1451 * Shutdown hardware and free up resources. This can be called any 1452 * time after the mutex has been initialized. It is called in both 1453 * the error case in attach and the normal detach case so it needs 1454 * to be careful about only freeing resources that have actually been 1455 * allocated. 1456 */ 1457static int 1458re_detach(dev) 1459 device_t dev; 1460{ 1461 struct rl_softc *sc; 1462 struct ifnet *ifp; 1463 int i, rid; 1464 1465 sc = device_get_softc(dev); 1466 ifp = sc->rl_ifp; 1467 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1468 1469 /* These should only be active if attach succeeded */ 1470 if (device_is_attached(dev)) { 1471#ifdef DEVICE_POLLING 1472 if (ifp->if_capenable & IFCAP_POLLING) 1473 ether_poll_deregister(ifp); 1474#endif 1475 RL_LOCK(sc); 1476#if 0 1477 sc->suspended = 1; 1478#endif 1479 re_stop(sc); 1480 RL_UNLOCK(sc); 1481 callout_drain(&sc->rl_stat_callout); 1482 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1483 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1484 /* 1485 * Force off the IFF_UP flag here, in case someone 1486 * still had a BPF descriptor attached to this 1487 * interface. If they do, ether_ifdetach() will cause 1488 * the BPF code to try and clear the promisc mode 1489 * flag, which will bubble down to re_ioctl(), 1490 * which will try to call re_init() again. This will 1491 * turn the NIC back on and restart the MII ticker, 1492 * which will panic the system when the kernel tries 1493 * to invoke the re_tick() function that isn't there 1494 * anymore. 1495 */ 1496 ifp->if_flags &= ~IFF_UP; 1497 ether_ifdetach(ifp); 1498 } 1499 if (sc->rl_miibus) 1500 device_delete_child(dev, sc->rl_miibus); 1501 bus_generic_detach(dev); 1502 1503 /* 1504 * The rest is resource deallocation, so we should already be 1505 * stopped here. 1506 */ 1507 1508 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1509 if (sc->rl_intrhand[i] != NULL) { 1510 bus_teardown_intr(dev, sc->rl_irq[i], 1511 sc->rl_intrhand[i]); 1512 sc->rl_intrhand[i] = NULL; 1513 } 1514 } 1515 if (ifp != NULL) 1516 if_free(ifp); 1517 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1518 if (sc->rl_irq[0] != NULL) { 1519 bus_release_resource(dev, SYS_RES_IRQ, 0, 1520 sc->rl_irq[0]); 1521 sc->rl_irq[0] = NULL; 1522 } 1523 } else { 1524 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1525 if (sc->rl_irq[i] != NULL) { 1526 bus_release_resource(dev, SYS_RES_IRQ, rid, 1527 sc->rl_irq[i]); 1528 sc->rl_irq[i] = NULL; 1529 } 1530 } 1531 pci_release_msi(dev); 1532 } 1533 if (sc->rl_res) 1534 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1535 sc->rl_res); 1536 1537 /* Unload and free the RX DMA ring memory and map */ 1538 1539 if (sc->rl_ldata.rl_rx_list_tag) { 1540 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1541 sc->rl_ldata.rl_rx_list_map); 1542 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1543 sc->rl_ldata.rl_rx_list, 1544 sc->rl_ldata.rl_rx_list_map); 1545 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1546 } 1547 1548 /* Unload and free the TX DMA ring memory and map */ 1549 1550 if (sc->rl_ldata.rl_tx_list_tag) { 1551 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1552 sc->rl_ldata.rl_tx_list_map); 1553 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1554 sc->rl_ldata.rl_tx_list, 1555 sc->rl_ldata.rl_tx_list_map); 1556 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1557 } 1558 1559 /* Destroy all the RX and TX buffer maps */ 1560 1561 if (sc->rl_ldata.rl_tx_mtag) { 1562 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1563 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1564 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1565 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1566 } 1567 if (sc->rl_ldata.rl_rx_mtag) { 1568 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1569 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1570 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1571 if (sc->rl_ldata.rl_rx_sparemap) 1572 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1573 sc->rl_ldata.rl_rx_sparemap); 1574 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1575 } 1576 1577 /* Unload and free the stats buffer and map */ 1578 1579 if (sc->rl_ldata.rl_stag) { 1580 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1581 sc->rl_ldata.rl_rx_list_map); 1582 bus_dmamem_free(sc->rl_ldata.rl_stag, 1583 sc->rl_ldata.rl_stats, 1584 sc->rl_ldata.rl_smap); 1585 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1586 } 1587 1588 if (sc->rl_parent_tag) 1589 bus_dma_tag_destroy(sc->rl_parent_tag); 1590 1591 mtx_destroy(&sc->rl_mtx); 1592 1593 return (0); 1594} 1595 1596static __inline void 1597re_discard_rxbuf(sc, idx) 1598 struct rl_softc *sc; 1599 int idx; 1600{ 1601 struct rl_desc *desc; 1602 struct rl_rxdesc *rxd; 1603 uint32_t cmdstat; 1604 1605 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1606 desc = &sc->rl_ldata.rl_rx_list[idx]; 1607 desc->rl_vlanctl = 0; 1608 cmdstat = rxd->rx_size; 1609 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1610 cmdstat |= RL_RDESC_CMD_EOR; 1611 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1612} 1613 1614static int 1615re_newbuf(sc, idx) 1616 struct rl_softc *sc; 1617 int idx; 1618{ 1619 struct mbuf *m; 1620 struct rl_rxdesc *rxd; 1621 bus_dma_segment_t segs[1]; 1622 bus_dmamap_t map; 1623 struct rl_desc *desc; 1624 uint32_t cmdstat; 1625 int error, nsegs; 1626 1627 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1628 if (m == NULL) 1629 return (ENOBUFS); 1630 1631 m->m_len = m->m_pkthdr.len = MCLBYTES; 1632#ifdef RE_FIXUP_RX 1633 /* 1634 * This is part of an evil trick to deal with non-x86 platforms. 1635 * The RealTek chip requires RX buffers to be aligned on 64-bit 1636 * boundaries, but that will hose non-x86 machines. To get around 1637 * this, we leave some empty space at the start of each buffer 1638 * and for non-x86 hosts, we copy the buffer back six bytes 1639 * to achieve word alignment. This is slightly more efficient 1640 * than allocating a new buffer, copying the contents, and 1641 * discarding the old buffer. 1642 */ 1643 m_adj(m, RE_ETHER_ALIGN); 1644#endif 1645 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1646 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1647 if (error != 0) { 1648 m_freem(m); 1649 return (ENOBUFS); 1650 } 1651 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1652 1653 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1654 if (rxd->rx_m != NULL) { 1655 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1656 BUS_DMASYNC_POSTREAD); 1657 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1658 } 1659 1660 rxd->rx_m = m; 1661 map = rxd->rx_dmamap; 1662 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1663 rxd->rx_size = segs[0].ds_len; 1664 sc->rl_ldata.rl_rx_sparemap = map; 1665 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1666 BUS_DMASYNC_PREREAD); 1667 1668 desc = &sc->rl_ldata.rl_rx_list[idx]; 1669 desc->rl_vlanctl = 0; 1670 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1671 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1672 cmdstat = segs[0].ds_len; 1673 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1674 cmdstat |= RL_RDESC_CMD_EOR; 1675 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1676 1677 return (0); 1678} 1679 1680#ifdef RE_FIXUP_RX 1681static __inline void 1682re_fixup_rx(m) 1683 struct mbuf *m; 1684{ 1685 int i; 1686 uint16_t *src, *dst; 1687 1688 src = mtod(m, uint16_t *); 1689 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1690 1691 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1692 *dst++ = *src++; 1693 1694 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1695 1696 return; 1697} 1698#endif 1699 1700static int 1701re_tx_list_init(sc) 1702 struct rl_softc *sc; 1703{ 1704 struct rl_desc *desc; 1705 int i; 1706 1707 RL_LOCK_ASSERT(sc); 1708 1709 bzero(sc->rl_ldata.rl_tx_list, 1710 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1711 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1712 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1713 /* Set EOR. */ 1714 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1715 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1716 1717 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1718 sc->rl_ldata.rl_tx_list_map, 1719 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1720 1721 sc->rl_ldata.rl_tx_prodidx = 0; 1722 sc->rl_ldata.rl_tx_considx = 0; 1723 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1724 1725 return (0); 1726} 1727 1728static int 1729re_rx_list_init(sc) 1730 struct rl_softc *sc; 1731{ 1732 int error, i; 1733 1734 bzero(sc->rl_ldata.rl_rx_list, 1735 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1736 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1737 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1738 if ((error = re_newbuf(sc, i)) != 0) 1739 return (error); 1740 } 1741 1742 /* Flush the RX descriptors */ 1743 1744 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1745 sc->rl_ldata.rl_rx_list_map, 1746 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1747 1748 sc->rl_ldata.rl_rx_prodidx = 0; 1749 sc->rl_head = sc->rl_tail = NULL; 1750 1751 return (0); 1752} 1753 1754/* 1755 * RX handler for C+ and 8169. For the gigE chips, we support 1756 * the reception of jumbo frames that have been fragmented 1757 * across multiple 2K mbuf cluster buffers. 1758 */ 1759static int 1760re_rxeof(sc) 1761 struct rl_softc *sc; 1762{ 1763 struct mbuf *m; 1764 struct ifnet *ifp; 1765 int i, total_len; 1766 struct rl_desc *cur_rx; 1767 u_int32_t rxstat, rxvlan; 1768 int maxpkt = 16; 1769 1770 RL_LOCK_ASSERT(sc); 1771 1772 ifp = sc->rl_ifp; 1773 1774 /* Invalidate the descriptor memory */ 1775 1776 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1777 sc->rl_ldata.rl_rx_list_map, 1778 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1779 1780 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1781 i = RL_RX_DESC_NXT(sc, i)) { 1782 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1783 rxstat = le32toh(cur_rx->rl_cmdstat); 1784 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1785 break; 1786 total_len = rxstat & sc->rl_rxlenmask; 1787 rxvlan = le32toh(cur_rx->rl_vlanctl); 1788 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1789 1790 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1791 if (re_newbuf(sc, i) != 0) { 1792 /* 1793 * If this is part of a multi-fragment packet, 1794 * discard all the pieces. 1795 */ 1796 if (sc->rl_head != NULL) { 1797 m_freem(sc->rl_head); 1798 sc->rl_head = sc->rl_tail = NULL; 1799 } 1800 re_discard_rxbuf(sc, i); 1801 continue; 1802 } 1803 m->m_len = RE_RX_DESC_BUFLEN; 1804 if (sc->rl_head == NULL) 1805 sc->rl_head = sc->rl_tail = m; 1806 else { 1807 m->m_flags &= ~M_PKTHDR; 1808 sc->rl_tail->m_next = m; 1809 sc->rl_tail = m; 1810 } 1811 continue; 1812 } 1813 1814 /* 1815 * NOTE: for the 8139C+, the frame length field 1816 * is always 12 bits in size, but for the gigE chips, 1817 * it is 13 bits (since the max RX frame length is 16K). 1818 * Unfortunately, all 32 bits in the status word 1819 * were already used, so to make room for the extra 1820 * length bit, RealTek took out the 'frame alignment 1821 * error' bit and shifted the other status bits 1822 * over one slot. The OWN, EOR, FS and LS bits are 1823 * still in the same places. We have already extracted 1824 * the frame length and checked the OWN bit, so rather 1825 * than using an alternate bit mapping, we shift the 1826 * status bits one space to the right so we can evaluate 1827 * them using the 8169 status as though it was in the 1828 * same format as that of the 8139C+. 1829 */ 1830 if (sc->rl_type == RL_8169) 1831 rxstat >>= 1; 1832 1833 /* 1834 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1835 * set, but if CRC is clear, it will still be a valid frame. 1836 */ 1837 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1838 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1839 ifp->if_ierrors++; 1840 /* 1841 * If this is part of a multi-fragment packet, 1842 * discard all the pieces. 1843 */ 1844 if (sc->rl_head != NULL) { 1845 m_freem(sc->rl_head); 1846 sc->rl_head = sc->rl_tail = NULL; 1847 } 1848 re_discard_rxbuf(sc, i); 1849 continue; 1850 } 1851 1852 /* 1853 * If allocating a replacement mbuf fails, 1854 * reload the current one. 1855 */ 1856 1857 if (re_newbuf(sc, i) != 0) { 1858 ifp->if_iqdrops++; 1859 if (sc->rl_head != NULL) { 1860 m_freem(sc->rl_head); 1861 sc->rl_head = sc->rl_tail = NULL; 1862 } 1863 re_discard_rxbuf(sc, i); 1864 continue; 1865 } 1866 1867 if (sc->rl_head != NULL) { 1868 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1869 if (m->m_len == 0) 1870 m->m_len = RE_RX_DESC_BUFLEN; 1871 /* 1872 * Special case: if there's 4 bytes or less 1873 * in this buffer, the mbuf can be discarded: 1874 * the last 4 bytes is the CRC, which we don't 1875 * care about anyway. 1876 */ 1877 if (m->m_len <= ETHER_CRC_LEN) { 1878 sc->rl_tail->m_len -= 1879 (ETHER_CRC_LEN - m->m_len); 1880 m_freem(m); 1881 } else { 1882 m->m_len -= ETHER_CRC_LEN; 1883 m->m_flags &= ~M_PKTHDR; 1884 sc->rl_tail->m_next = m; 1885 } 1886 m = sc->rl_head; 1887 sc->rl_head = sc->rl_tail = NULL; 1888 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1889 } else 1890 m->m_pkthdr.len = m->m_len = 1891 (total_len - ETHER_CRC_LEN); 1892 1893#ifdef RE_FIXUP_RX 1894 re_fixup_rx(m); 1895#endif 1896 ifp->if_ipackets++; 1897 m->m_pkthdr.rcvif = ifp; 1898 1899 /* Do RX checksumming if enabled */ 1900 1901 if (ifp->if_capenable & IFCAP_RXCSUM) { 1902 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1903 /* Check IP header checksum */ 1904 if (rxstat & RL_RDESC_STAT_PROTOID) 1905 m->m_pkthdr.csum_flags |= 1906 CSUM_IP_CHECKED; 1907 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1908 m->m_pkthdr.csum_flags |= 1909 CSUM_IP_VALID; 1910 1911 /* Check TCP/UDP checksum */ 1912 if ((RL_TCPPKT(rxstat) && 1913 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1914 (RL_UDPPKT(rxstat) && 1915 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1916 m->m_pkthdr.csum_flags |= 1917 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1918 m->m_pkthdr.csum_data = 0xffff; 1919 } 1920 } else { 1921 /* 1922 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1923 */ 1924 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1925 (rxvlan & RL_RDESC_IPV4)) 1926 m->m_pkthdr.csum_flags |= 1927 CSUM_IP_CHECKED; 1928 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1929 (rxvlan & RL_RDESC_IPV4)) 1930 m->m_pkthdr.csum_flags |= 1931 CSUM_IP_VALID; 1932 if (((rxstat & RL_RDESC_STAT_TCP) && 1933 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1934 ((rxstat & RL_RDESC_STAT_UDP) && 1935 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1936 m->m_pkthdr.csum_flags |= 1937 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1938 m->m_pkthdr.csum_data = 0xffff; 1939 } 1940 } 1941 } 1942 maxpkt--; 1943 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1944 m->m_pkthdr.ether_vtag = 1945 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1946 m->m_flags |= M_VLANTAG; 1947 } 1948 RL_UNLOCK(sc); 1949 (*ifp->if_input)(ifp, m); 1950 RL_LOCK(sc); 1951 } 1952 1953 /* Flush the RX DMA ring */ 1954 1955 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1956 sc->rl_ldata.rl_rx_list_map, 1957 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1958 1959 sc->rl_ldata.rl_rx_prodidx = i; 1960 1961 if (maxpkt) 1962 return(EAGAIN); 1963 1964 return(0); 1965} 1966 1967static void 1968re_txeof(sc) 1969 struct rl_softc *sc; 1970{ 1971 struct ifnet *ifp; 1972 struct rl_txdesc *txd; 1973 u_int32_t txstat; 1974 int cons; 1975 1976 cons = sc->rl_ldata.rl_tx_considx; 1977 if (cons == sc->rl_ldata.rl_tx_prodidx) 1978 return; 1979 1980 ifp = sc->rl_ifp; 1981 /* Invalidate the TX descriptor list */ 1982 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1983 sc->rl_ldata.rl_tx_list_map, 1984 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1985 1986 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1987 cons = RL_TX_DESC_NXT(sc, cons)) { 1988 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1989 if (txstat & RL_TDESC_STAT_OWN) 1990 break; 1991 /* 1992 * We only stash mbufs in the last descriptor 1993 * in a fragment chain, which also happens to 1994 * be the only place where the TX status bits 1995 * are valid. 1996 */ 1997 if (txstat & RL_TDESC_CMD_EOF) { 1998 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1999 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2000 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2001 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2002 txd->tx_dmamap); 2003 KASSERT(txd->tx_m != NULL, 2004 ("%s: freeing NULL mbufs!", __func__)); 2005 m_freem(txd->tx_m); 2006 txd->tx_m = NULL; 2007 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2008 RL_TDESC_STAT_COLCNT)) 2009 ifp->if_collisions++; 2010 if (txstat & RL_TDESC_STAT_TXERRSUM) 2011 ifp->if_oerrors++; 2012 else 2013 ifp->if_opackets++; 2014 } 2015 sc->rl_ldata.rl_tx_free++; 2016 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2017 } 2018 sc->rl_ldata.rl_tx_considx = cons; 2019 2020 /* No changes made to the TX ring, so no flush needed */ 2021 2022 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2023 /* 2024 * Some chips will ignore a second TX request issued 2025 * while an existing transmission is in progress. If 2026 * the transmitter goes idle but there are still 2027 * packets waiting to be sent, we need to restart the 2028 * channel here to flush them out. This only seems to 2029 * be required with the PCIe devices. 2030 */ 2031 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2032 2033#ifdef RE_TX_MODERATION 2034 /* 2035 * If not all descriptors have been reaped yet, reload 2036 * the timer so that we will eventually get another 2037 * interrupt that will cause us to re-enter this routine. 2038 * This is done in case the transmitter has gone idle. 2039 */ 2040 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2041#endif 2042 } else 2043 sc->rl_watchdog_timer = 0; 2044} 2045 2046static void 2047re_tick(xsc) 2048 void *xsc; 2049{ 2050 struct rl_softc *sc; 2051 struct mii_data *mii; 2052 struct ifnet *ifp; 2053 2054 sc = xsc; 2055 ifp = sc->rl_ifp; 2056 2057 RL_LOCK_ASSERT(sc); 2058 2059 re_watchdog(sc); 2060 2061 mii = device_get_softc(sc->rl_miibus); 2062 mii_tick(mii); 2063 if ((sc->rl_flags & RL_FLAG_LINK) != 0) { 2064 if (!(mii->mii_media_status & IFM_ACTIVE)) 2065 sc->rl_flags &= ~RL_FLAG_LINK; 2066 } else { 2067 if (mii->mii_media_status & IFM_ACTIVE && 2068 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2069 sc->rl_flags |= RL_FLAG_LINK; 2070 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2071 taskqueue_enqueue_fast(taskqueue_fast, 2072 &sc->rl_txtask); 2073 } 2074 } 2075 2076 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2077} 2078 2079#ifdef DEVICE_POLLING 2080static void 2081re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2082{ 2083 struct rl_softc *sc = ifp->if_softc; 2084 2085 RL_LOCK(sc); 2086 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2087 re_poll_locked(ifp, cmd, count); 2088 RL_UNLOCK(sc); 2089} 2090 2091static void 2092re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2093{ 2094 struct rl_softc *sc = ifp->if_softc; 2095 2096 RL_LOCK_ASSERT(sc); 2097 2098 sc->rxcycles = count; 2099 re_rxeof(sc); 2100 re_txeof(sc); 2101 2102 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2103 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2104 2105 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2106 u_int16_t status; 2107 2108 status = CSR_READ_2(sc, RL_ISR); 2109 if (status == 0xffff) 2110 return; 2111 if (status) 2112 CSR_WRITE_2(sc, RL_ISR, status); 2113 2114 /* 2115 * XXX check behaviour on receiver stalls. 2116 */ 2117 2118 if (status & RL_ISR_SYSTEM_ERR) { 2119 re_reset(sc); 2120 re_init_locked(sc); 2121 } 2122 } 2123} 2124#endif /* DEVICE_POLLING */ 2125 2126static int 2127re_intr(arg) 2128 void *arg; 2129{ 2130 struct rl_softc *sc; 2131 uint16_t status; 2132 2133 sc = arg; 2134 2135 status = CSR_READ_2(sc, RL_ISR); 2136 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2137 return (FILTER_STRAY); 2138 CSR_WRITE_2(sc, RL_IMR, 0); 2139 2140 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2141 2142 return (FILTER_HANDLED); 2143} 2144 2145static void 2146re_int_task(arg, npending) 2147 void *arg; 2148 int npending; 2149{ 2150 struct rl_softc *sc; 2151 struct ifnet *ifp; 2152 u_int16_t status; 2153 int rval = 0; 2154 2155 sc = arg; 2156 ifp = sc->rl_ifp; 2157 2158 RL_LOCK(sc); 2159 2160 status = CSR_READ_2(sc, RL_ISR); 2161 CSR_WRITE_2(sc, RL_ISR, status); 2162 2163 if (sc->suspended || 2164 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2165 RL_UNLOCK(sc); 2166 return; 2167 } 2168 2169#ifdef DEVICE_POLLING 2170 if (ifp->if_capenable & IFCAP_POLLING) { 2171 RL_UNLOCK(sc); 2172 return; 2173 } 2174#endif 2175 2176 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2177 rval = re_rxeof(sc); 2178 2179#ifdef RE_TX_MODERATION 2180 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2181#else 2182 if (status & (RL_ISR_TX_OK| 2183#endif 2184 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2185 re_txeof(sc); 2186 2187 if (status & RL_ISR_SYSTEM_ERR) { 2188 re_reset(sc); 2189 re_init_locked(sc); 2190 } 2191 2192 if (status & RL_ISR_LINKCHG) { 2193 callout_stop(&sc->rl_stat_callout); 2194 re_tick(sc); 2195 } 2196 2197 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2198 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2199 2200 RL_UNLOCK(sc); 2201 2202 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2203 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2204 return; 2205 } 2206 2207 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2208 2209 return; 2210} 2211 2212static int 2213re_encap(sc, m_head) 2214 struct rl_softc *sc; 2215 struct mbuf **m_head; 2216{ 2217 struct rl_txdesc *txd, *txd_last; 2218 bus_dma_segment_t segs[RL_NTXSEGS]; 2219 bus_dmamap_t map; 2220 struct mbuf *m_new; 2221 struct rl_desc *desc; 2222 int nsegs, prod; 2223 int i, error, ei, si; 2224 int padlen; 2225 uint32_t cmdstat, csum_flags, vlanctl; 2226 2227 RL_LOCK_ASSERT(sc); 2228 M_ASSERTPKTHDR((*m_head)); 2229 2230 /* 2231 * With some of the RealTek chips, using the checksum offload 2232 * support in conjunction with the autopadding feature results 2233 * in the transmission of corrupt frames. For example, if we 2234 * need to send a really small IP fragment that's less than 60 2235 * bytes in size, and IP header checksumming is enabled, the 2236 * resulting ethernet frame that appears on the wire will 2237 * have garbled payload. To work around this, if TX IP checksum 2238 * offload is enabled, we always manually pad short frames out 2239 * to the minimum ethernet frame size. 2240 */ 2241 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2242 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2243 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2244 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2245 if (M_WRITABLE(*m_head) == 0) { 2246 /* Get a writable copy. */ 2247 m_new = m_dup(*m_head, M_DONTWAIT); 2248 m_freem(*m_head); 2249 if (m_new == NULL) { 2250 *m_head = NULL; 2251 return (ENOBUFS); 2252 } 2253 *m_head = m_new; 2254 } 2255 if ((*m_head)->m_next != NULL || 2256 M_TRAILINGSPACE(*m_head) < padlen) { 2257 m_new = m_defrag(*m_head, M_DONTWAIT); 2258 if (m_new == NULL) { 2259 m_freem(*m_head); 2260 *m_head = NULL; 2261 return (ENOBUFS); 2262 } 2263 } else 2264 m_new = *m_head; 2265 2266 /* 2267 * Manually pad short frames, and zero the pad space 2268 * to avoid leaking data. 2269 */ 2270 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2271 m_new->m_pkthdr.len += padlen; 2272 m_new->m_len = m_new->m_pkthdr.len; 2273 *m_head = m_new; 2274 } 2275 2276 prod = sc->rl_ldata.rl_tx_prodidx; 2277 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2278 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2279 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2280 if (error == EFBIG) { 2281 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2282 if (m_new == NULL) { 2283 m_freem(*m_head); 2284 *m_head = NULL; 2285 return (ENOBUFS); 2286 } 2287 *m_head = m_new; 2288 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2289 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2290 if (error != 0) { 2291 m_freem(*m_head); 2292 *m_head = NULL; 2293 return (error); 2294 } 2295 } else if (error != 0) 2296 return (error); 2297 if (nsegs == 0) { 2298 m_freem(*m_head); 2299 *m_head = NULL; 2300 return (EIO); 2301 } 2302 2303 /* Check for number of available descriptors. */ 2304 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2305 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2306 return (ENOBUFS); 2307 } 2308 2309 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2310 BUS_DMASYNC_PREWRITE); 2311 2312 /* 2313 * Set up checksum offload. Note: checksum offload bits must 2314 * appear in all descriptors of a multi-descriptor transmit 2315 * attempt. This is according to testing done with an 8169 2316 * chip. This is a requirement. 2317 */ 2318 vlanctl = 0; 2319 csum_flags = 0; 2320 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2321 csum_flags = RL_TDESC_CMD_LGSEND | 2322 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2323 RL_TDESC_CMD_MSSVAL_SHIFT); 2324 else { 2325 /* 2326 * Unconditionally enable IP checksum if TCP or UDP 2327 * checksum is required. Otherwise, TCP/UDP checksum 2328 * does't make effects. 2329 */ 2330 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2331 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2332 csum_flags |= RL_TDESC_CMD_IPCSUM; 2333 if (((*m_head)->m_pkthdr.csum_flags & 2334 CSUM_TCP) != 0) 2335 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2336 if (((*m_head)->m_pkthdr.csum_flags & 2337 CSUM_UDP) != 0) 2338 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2339 } else { 2340 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2341 if (((*m_head)->m_pkthdr.csum_flags & 2342 CSUM_TCP) != 0) 2343 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2344 if (((*m_head)->m_pkthdr.csum_flags & 2345 CSUM_UDP) != 0) 2346 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2347 } 2348 } 2349 } 2350 2351 /* 2352 * Set up hardware VLAN tagging. Note: vlan tag info must 2353 * appear in all descriptors of a multi-descriptor 2354 * transmission attempt. 2355 */ 2356 if ((*m_head)->m_flags & M_VLANTAG) 2357 vlanctl |= htons((*m_head)->m_pkthdr.ether_vtag) | 2358 RL_TDESC_VLANCTL_TAG; 2359 2360 si = prod; 2361 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2362 desc = &sc->rl_ldata.rl_tx_list[prod]; 2363 desc->rl_vlanctl = htole32(vlanctl); 2364 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2365 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2366 cmdstat = segs[i].ds_len; 2367 if (i != 0) 2368 cmdstat |= RL_TDESC_CMD_OWN; 2369 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2370 cmdstat |= RL_TDESC_CMD_EOR; 2371 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2372 sc->rl_ldata.rl_tx_free--; 2373 } 2374 /* Update producer index. */ 2375 sc->rl_ldata.rl_tx_prodidx = prod; 2376 2377 /* Set EOF on the last descriptor. */ 2378 ei = RL_TX_DESC_PRV(sc, prod); 2379 desc = &sc->rl_ldata.rl_tx_list[ei]; 2380 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2381 2382 desc = &sc->rl_ldata.rl_tx_list[si]; 2383 /* Set SOF and transfer ownership of packet to the chip. */ 2384 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2385 2386 /* 2387 * Insure that the map for this transmission 2388 * is placed at the array index of the last descriptor 2389 * in this chain. (Swap last and first dmamaps.) 2390 */ 2391 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2392 map = txd->tx_dmamap; 2393 txd->tx_dmamap = txd_last->tx_dmamap; 2394 txd_last->tx_dmamap = map; 2395 txd_last->tx_m = *m_head; 2396 2397 return (0); 2398} 2399 2400static void 2401re_tx_task(arg, npending) 2402 void *arg; 2403 int npending; 2404{ 2405 struct ifnet *ifp; 2406 2407 ifp = arg; 2408 re_start(ifp); 2409 2410 return; 2411} 2412 2413/* 2414 * Main transmit routine for C+ and gigE NICs. 2415 */ 2416static void 2417re_start(ifp) 2418 struct ifnet *ifp; 2419{ 2420 struct rl_softc *sc; 2421 struct mbuf *m_head; 2422 int queued; 2423 2424 sc = ifp->if_softc; 2425 2426 RL_LOCK(sc); 2427 2428 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2429 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2430 RL_UNLOCK(sc); 2431 return; 2432 } 2433 2434 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2435 sc->rl_ldata.rl_tx_free > 1;) { 2436 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2437 if (m_head == NULL) 2438 break; 2439 2440 if (re_encap(sc, &m_head) != 0) { 2441 if (m_head == NULL) 2442 break; 2443 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2444 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2445 break; 2446 } 2447 2448 /* 2449 * If there's a BPF listener, bounce a copy of this frame 2450 * to him. 2451 */ 2452 ETHER_BPF_MTAP(ifp, m_head); 2453 2454 queued++; 2455 } 2456 2457 if (queued == 0) { 2458#ifdef RE_TX_MODERATION 2459 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2460 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2461#endif 2462 RL_UNLOCK(sc); 2463 return; 2464 } 2465 2466 /* Flush the TX descriptors */ 2467 2468 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2469 sc->rl_ldata.rl_tx_list_map, 2470 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2471 2472 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2473 2474#ifdef RE_TX_MODERATION 2475 /* 2476 * Use the countdown timer for interrupt moderation. 2477 * 'TX done' interrupts are disabled. Instead, we reset the 2478 * countdown timer, which will begin counting until it hits 2479 * the value in the TIMERINT register, and then trigger an 2480 * interrupt. Each time we write to the TIMERCNT register, 2481 * the timer count is reset to 0. 2482 */ 2483 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2484#endif 2485 2486 /* 2487 * Set a timeout in case the chip goes out to lunch. 2488 */ 2489 sc->rl_watchdog_timer = 5; 2490 2491 RL_UNLOCK(sc); 2492 2493 return; 2494} 2495 2496static void 2497re_init(xsc) 2498 void *xsc; 2499{ 2500 struct rl_softc *sc = xsc; 2501 2502 RL_LOCK(sc); 2503 re_init_locked(sc); 2504 RL_UNLOCK(sc); 2505} 2506 2507static void 2508re_init_locked(sc) 2509 struct rl_softc *sc; 2510{ 2511 struct ifnet *ifp = sc->rl_ifp; 2512 struct mii_data *mii; 2513 u_int32_t rxcfg = 0; 2514 uint16_t cfg; 2515 union { 2516 uint32_t align_dummy; 2517 u_char eaddr[ETHER_ADDR_LEN]; 2518 } eaddr; 2519 2520 RL_LOCK_ASSERT(sc); 2521 2522 mii = device_get_softc(sc->rl_miibus); 2523 2524 /* 2525 * Cancel pending I/O and free all RX/TX buffers. 2526 */ 2527 re_stop(sc); 2528 2529 /* 2530 * Enable C+ RX and TX mode, as well as VLAN stripping and 2531 * RX checksum offload. We must configure the C+ register 2532 * before all others. 2533 */ 2534 cfg = RL_CPLUSCMD_PCI_MRW; 2535 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2536 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2537 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2538 cfg |= RL_CPLUSCMD_VLANSTRIP; 2539 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2540 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2541 /* XXX magic. */ 2542 cfg |= 0x0001; 2543 } else 2544 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2545 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2546 /* 2547 * Disable TSO if interface MTU size is greater than MSS 2548 * allowed in controller. 2549 */ 2550 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2551 ifp->if_capenable &= ~IFCAP_TSO4; 2552 ifp->if_hwassist &= ~CSUM_TSO; 2553 } 2554 2555 /* 2556 * Init our MAC address. Even though the chipset 2557 * documentation doesn't mention it, we need to enter "Config 2558 * register write enable" mode to modify the ID registers. 2559 */ 2560 /* Copy MAC address on stack to align. */ 2561 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2562 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2563 CSR_WRITE_4(sc, RL_IDR0, 2564 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2565 CSR_WRITE_4(sc, RL_IDR4, 2566 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2567 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2568 2569 /* 2570 * For C+ mode, initialize the RX descriptors and mbufs. 2571 */ 2572 re_rx_list_init(sc); 2573 re_tx_list_init(sc); 2574 2575 /* 2576 * Load the addresses of the RX and TX lists into the chip. 2577 */ 2578 2579 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2580 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2581 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2582 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2583 2584 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2585 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2586 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2587 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2588 2589 /* 2590 * Enable transmit and receive. 2591 */ 2592 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2593 2594 /* 2595 * Set the initial TX and RX configuration. 2596 */ 2597 if (sc->rl_testmode) { 2598 if (sc->rl_type == RL_8169) 2599 CSR_WRITE_4(sc, RL_TXCFG, 2600 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2601 else 2602 CSR_WRITE_4(sc, RL_TXCFG, 2603 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2604 } else 2605 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2606 2607 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2608 2609 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2610 2611 /* Set the individual bit to receive frames for this host only. */ 2612 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2613 rxcfg |= RL_RXCFG_RX_INDIV; 2614 2615 /* If we want promiscuous mode, set the allframes bit. */ 2616 if (ifp->if_flags & IFF_PROMISC) 2617 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2618 else 2619 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2620 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2621 2622 /* 2623 * Set capture broadcast bit to capture broadcast frames. 2624 */ 2625 if (ifp->if_flags & IFF_BROADCAST) 2626 rxcfg |= RL_RXCFG_RX_BROAD; 2627 else 2628 rxcfg &= ~RL_RXCFG_RX_BROAD; 2629 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2630 2631 /* 2632 * Program the multicast filter, if necessary. 2633 */ 2634 re_setmulti(sc); 2635 2636#ifdef DEVICE_POLLING 2637 /* 2638 * Disable interrupts if we are polling. 2639 */ 2640 if (ifp->if_capenable & IFCAP_POLLING) 2641 CSR_WRITE_2(sc, RL_IMR, 0); 2642 else /* otherwise ... */ 2643#endif 2644 2645 /* 2646 * Enable interrupts. 2647 */ 2648 if (sc->rl_testmode) 2649 CSR_WRITE_2(sc, RL_IMR, 0); 2650 else 2651 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2652 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2653 2654 /* Set initial TX threshold */ 2655 sc->rl_txthresh = RL_TX_THRESH_INIT; 2656 2657 /* Start RX/TX process. */ 2658 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2659#ifdef notdef 2660 /* Enable receiver and transmitter. */ 2661 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2662#endif 2663 2664#ifdef RE_TX_MODERATION 2665 /* 2666 * Initialize the timer interrupt register so that 2667 * a timer interrupt will be generated once the timer 2668 * reaches a certain number of ticks. The timer is 2669 * reloaded on each transmit. This gives us TX interrupt 2670 * moderation, which dramatically improves TX frame rate. 2671 */ 2672 if (sc->rl_type == RL_8169) 2673 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2674 else 2675 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2676#endif 2677 2678 /* 2679 * For 8169 gigE NICs, set the max allowed RX packet 2680 * size so we can receive jumbo frames. 2681 */ 2682 if (sc->rl_type == RL_8169) 2683 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2684 2685 if (sc->rl_testmode) 2686 return; 2687 2688 mii_mediachg(mii); 2689 2690 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2691 2692 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2693 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2694 2695 sc->rl_flags &= ~RL_FLAG_LINK; 2696 sc->rl_watchdog_timer = 0; 2697 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2698} 2699 2700/* 2701 * Set media options. 2702 */ 2703static int 2704re_ifmedia_upd(ifp) 2705 struct ifnet *ifp; 2706{ 2707 struct rl_softc *sc; 2708 struct mii_data *mii; 2709 2710 sc = ifp->if_softc; 2711 mii = device_get_softc(sc->rl_miibus); 2712 RL_LOCK(sc); 2713 mii_mediachg(mii); 2714 RL_UNLOCK(sc); 2715 2716 return (0); 2717} 2718 2719/* 2720 * Report current media status. 2721 */ 2722static void 2723re_ifmedia_sts(ifp, ifmr) 2724 struct ifnet *ifp; 2725 struct ifmediareq *ifmr; 2726{ 2727 struct rl_softc *sc; 2728 struct mii_data *mii; 2729 2730 sc = ifp->if_softc; 2731 mii = device_get_softc(sc->rl_miibus); 2732 2733 RL_LOCK(sc); 2734 mii_pollstat(mii); 2735 RL_UNLOCK(sc); 2736 ifmr->ifm_active = mii->mii_media_active; 2737 ifmr->ifm_status = mii->mii_media_status; 2738} 2739 2740static int 2741re_ioctl(ifp, command, data) 2742 struct ifnet *ifp; 2743 u_long command; 2744 caddr_t data; 2745{ 2746 struct rl_softc *sc = ifp->if_softc; 2747 struct ifreq *ifr = (struct ifreq *) data; 2748 struct mii_data *mii; 2749 int error = 0; 2750 2751 switch (command) { 2752 case SIOCSIFMTU: 2753 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2754 error = EINVAL; 2755 break; 2756 } 2757 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2758 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2759 error = EINVAL; 2760 break; 2761 } 2762 RL_LOCK(sc); 2763 if (ifp->if_mtu != ifr->ifr_mtu) 2764 ifp->if_mtu = ifr->ifr_mtu; 2765 if (ifp->if_mtu > RL_TSO_MTU && 2766 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2767 ifp->if_capenable &= ~IFCAP_TSO4; 2768 ifp->if_hwassist &= ~CSUM_TSO; 2769 } 2770 RL_UNLOCK(sc); 2771 break; 2772 case SIOCSIFFLAGS: 2773 RL_LOCK(sc); 2774 if ((ifp->if_flags & IFF_UP) != 0) { 2775 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2776 if (((ifp->if_flags ^ sc->rl_if_flags) 2777 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2778 re_setmulti(sc); 2779 } else 2780 re_init_locked(sc); 2781 } else { 2782 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2783 re_stop(sc); 2784 } 2785 sc->rl_if_flags = ifp->if_flags; 2786 RL_UNLOCK(sc); 2787 break; 2788 case SIOCADDMULTI: 2789 case SIOCDELMULTI: 2790 RL_LOCK(sc); 2791 re_setmulti(sc); 2792 RL_UNLOCK(sc); 2793 break; 2794 case SIOCGIFMEDIA: 2795 case SIOCSIFMEDIA: 2796 mii = device_get_softc(sc->rl_miibus); 2797 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2798 break; 2799 case SIOCSIFCAP: 2800 { 2801 int mask, reinit; 2802 2803 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2804 reinit = 0; 2805#ifdef DEVICE_POLLING 2806 if (mask & IFCAP_POLLING) { 2807 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2808 error = ether_poll_register(re_poll, ifp); 2809 if (error) 2810 return(error); 2811 RL_LOCK(sc); 2812 /* Disable interrupts */ 2813 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2814 ifp->if_capenable |= IFCAP_POLLING; 2815 RL_UNLOCK(sc); 2816 } else { 2817 error = ether_poll_deregister(ifp); 2818 /* Enable interrupts. */ 2819 RL_LOCK(sc); 2820 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2821 ifp->if_capenable &= ~IFCAP_POLLING; 2822 RL_UNLOCK(sc); 2823 } 2824 } 2825#endif /* DEVICE_POLLING */ 2826 if (mask & IFCAP_HWCSUM) { 2827 ifp->if_capenable ^= IFCAP_HWCSUM; 2828 if (ifp->if_capenable & IFCAP_TXCSUM) 2829 ifp->if_hwassist |= RE_CSUM_FEATURES; 2830 else 2831 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2832 reinit = 1; 2833 } 2834 if (mask & IFCAP_VLAN_HWTAGGING) { 2835 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2836 reinit = 1; 2837 } 2838 if (mask & IFCAP_TSO4) { 2839 ifp->if_capenable ^= IFCAP_TSO4; 2840 if ((IFCAP_TSO4 & ifp->if_capenable) && 2841 (IFCAP_TSO4 & ifp->if_capabilities)) 2842 ifp->if_hwassist |= CSUM_TSO; 2843 else 2844 ifp->if_hwassist &= ~CSUM_TSO; 2845 if (ifp->if_mtu > RL_TSO_MTU && 2846 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2847 ifp->if_capenable &= ~IFCAP_TSO4; 2848 ifp->if_hwassist &= ~CSUM_TSO; 2849 } 2850 } 2851 if ((mask & IFCAP_WOL) != 0 && 2852 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2853 if ((mask & IFCAP_WOL_UCAST) != 0) 2854 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2855 if ((mask & IFCAP_WOL_MCAST) != 0) 2856 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2857 if ((mask & IFCAP_WOL_MAGIC) != 0) 2858 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2859 } 2860 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2861 re_init(sc); 2862 VLAN_CAPABILITIES(ifp); 2863 } 2864 break; 2865 default: 2866 error = ether_ioctl(ifp, command, data); 2867 break; 2868 } 2869 2870 return (error); 2871} 2872 2873static void 2874re_watchdog(sc) 2875 struct rl_softc *sc; 2876{ 2877 2878 RL_LOCK_ASSERT(sc); 2879 2880 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2881 return; 2882 2883 device_printf(sc->rl_dev, "watchdog timeout\n"); 2884 sc->rl_ifp->if_oerrors++; 2885 2886 re_txeof(sc); 2887 re_rxeof(sc); 2888 re_init_locked(sc); 2889} 2890 2891/* 2892 * Stop the adapter and free any mbufs allocated to the 2893 * RX and TX lists. 2894 */ 2895static void 2896re_stop(sc) 2897 struct rl_softc *sc; 2898{ 2899 register int i; 2900 struct ifnet *ifp; 2901 struct rl_txdesc *txd; 2902 struct rl_rxdesc *rxd; 2903 2904 RL_LOCK_ASSERT(sc); 2905 2906 ifp = sc->rl_ifp; 2907 2908 sc->rl_watchdog_timer = 0; 2909 callout_stop(&sc->rl_stat_callout); 2910 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2911 2912 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2913 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2914 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2915 2916 if (sc->rl_head != NULL) { 2917 m_freem(sc->rl_head); 2918 sc->rl_head = sc->rl_tail = NULL; 2919 } 2920 2921 /* Free the TX list buffers. */ 2922 2923 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2924 txd = &sc->rl_ldata.rl_tx_desc[i]; 2925 if (txd->tx_m != NULL) { 2926 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2927 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2928 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2929 txd->tx_dmamap); 2930 m_freem(txd->tx_m); 2931 txd->tx_m = NULL; 2932 } 2933 } 2934 2935 /* Free the RX list buffers. */ 2936 2937 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2938 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2939 if (rxd->rx_m != NULL) { 2940 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2941 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2942 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2943 rxd->rx_dmamap); 2944 m_freem(rxd->rx_m); 2945 rxd->rx_m = NULL; 2946 } 2947 } 2948} 2949 2950/* 2951 * Device suspend routine. Stop the interface and save some PCI 2952 * settings in case the BIOS doesn't restore them properly on 2953 * resume. 2954 */ 2955static int 2956re_suspend(dev) 2957 device_t dev; 2958{ 2959 struct rl_softc *sc; 2960 2961 sc = device_get_softc(dev); 2962 2963 RL_LOCK(sc); 2964 re_stop(sc); 2965 re_setwol(sc); 2966 sc->suspended = 1; 2967 RL_UNLOCK(sc); 2968 2969 return (0); 2970} 2971 2972/* 2973 * Device resume routine. Restore some PCI settings in case the BIOS 2974 * doesn't, re-enable busmastering, and restart the interface if 2975 * appropriate. 2976 */ 2977static int 2978re_resume(dev) 2979 device_t dev; 2980{ 2981 struct rl_softc *sc; 2982 struct ifnet *ifp; 2983 2984 sc = device_get_softc(dev); 2985 2986 RL_LOCK(sc); 2987 2988 ifp = sc->rl_ifp; 2989 2990 /* reinitialize interface if necessary */ 2991 if (ifp->if_flags & IFF_UP) 2992 re_init_locked(sc); 2993 2994 /* 2995 * Clear WOL matching such that normal Rx filtering 2996 * wouldn't interfere with WOL patterns. 2997 */ 2998 re_clrwol(sc); 2999 sc->suspended = 0; 3000 RL_UNLOCK(sc); 3001 3002 return (0); 3003} 3004 3005/* 3006 * Stop all chip I/O so that the kernel's probe routines don't 3007 * get confused by errant DMAs when rebooting. 3008 */ 3009static int 3010re_shutdown(dev) 3011 device_t dev; 3012{ 3013 struct rl_softc *sc; 3014 3015 sc = device_get_softc(dev); 3016 3017 RL_LOCK(sc); 3018 re_stop(sc); 3019 /* 3020 * Mark interface as down since otherwise we will panic if 3021 * interrupt comes in later on, which can happen in some 3022 * cases. 3023 */ 3024 sc->rl_ifp->if_flags &= ~IFF_UP; 3025 re_setwol(sc); 3026 RL_UNLOCK(sc); 3027 3028 return (0); 3029} 3030 3031static void 3032re_setwol(sc) 3033 struct rl_softc *sc; 3034{ 3035 struct ifnet *ifp; 3036 int pmc; 3037 uint16_t pmstat; 3038 uint8_t v; 3039 3040 RL_LOCK_ASSERT(sc); 3041 3042 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3043 return; 3044 3045 ifp = sc->rl_ifp; 3046 /* Enable config register write. */ 3047 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3048 3049 /* Enable PME. */ 3050 v = CSR_READ_1(sc, RL_CFG1); 3051 v &= ~RL_CFG1_PME; 3052 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3053 v |= RL_CFG1_PME; 3054 CSR_WRITE_1(sc, RL_CFG1, v); 3055 3056 v = CSR_READ_1(sc, RL_CFG3); 3057 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3058 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3059 v |= RL_CFG3_WOL_MAGIC; 3060 CSR_WRITE_1(sc, RL_CFG3, v); 3061 3062 /* Config register write done. */ 3063 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3064 3065 v = CSR_READ_1(sc, RL_CFG5); 3066 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3067 v &= ~RL_CFG5_WOL_LANWAKE; 3068 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3069 v |= RL_CFG5_WOL_UCAST; 3070 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3071 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3072 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3073 v |= RL_CFG5_WOL_LANWAKE; 3074 CSR_WRITE_1(sc, RL_CFG5, v); 3075 3076 /* 3077 * It seems that hardware resets its link speed to 100Mbps in 3078 * power down mode so switching to 100Mbps in driver is not 3079 * needed. 3080 */ 3081 3082 /* Request PME if WOL is requested. */ 3083 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3084 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3085 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3086 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3087 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3088} 3089 3090static void 3091re_clrwol(sc) 3092 struct rl_softc *sc; 3093{ 3094 int pmc; 3095 uint8_t v; 3096 3097 RL_LOCK_ASSERT(sc); 3098 3099 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3100 return; 3101 3102 /* Enable config register write. */ 3103 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3104 3105 v = CSR_READ_1(sc, RL_CFG3); 3106 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3107 CSR_WRITE_1(sc, RL_CFG3, v); 3108 3109 /* Config register write done. */ 3110 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3111 3112 v = CSR_READ_1(sc, RL_CFG5); 3113 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3114 v &= ~RL_CFG5_WOL_LANWAKE; 3115 CSR_WRITE_1(sc, RL_CFG5, v); 3116} 3117