if_re.c revision 180177
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 180177 2008-07-02 08:00:14Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* Tunables. */ 159static int msi_disable = 1; 160TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164/* 165 * Various supported device vendors/types and their names. 166 */ 167static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8168C/8168CP/8111B/8111C/8111CP PCIe " 176 "Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8169, 0, 178 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 182 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 183 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 184 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 185 { USR_VENDORID, USR_DEVICEID_997902, 0, 186 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 187}; 188 189static struct rl_hwrev re_hwrevs[] = { 190 { RL_HWREV_8139, RL_8139, "" }, 191 { RL_HWREV_8139A, RL_8139, "A" }, 192 { RL_HWREV_8139AG, RL_8139, "A-G" }, 193 { RL_HWREV_8139B, RL_8139, "B" }, 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 204 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL"}, 205 { RL_HWREV_8100, RL_8139, "8100"}, 206 { RL_HWREV_8101, RL_8139, "8101"}, 207 { RL_HWREV_8100E, RL_8169, "8100E"}, 208 { RL_HWREV_8101E, RL_8169, "8101E"}, 209 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 210 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 211 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 212 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 213 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 214 { 0, 0, NULL } 215}; 216 217static int re_probe (device_t); 218static int re_attach (device_t); 219static int re_detach (device_t); 220 221static int re_encap (struct rl_softc *, struct mbuf **); 222 223static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 224static int re_allocmem (device_t, struct rl_softc *); 225static __inline void re_discard_rxbuf 226 (struct rl_softc *, int); 227static int re_newbuf (struct rl_softc *, int); 228static int re_rx_list_init (struct rl_softc *); 229static int re_tx_list_init (struct rl_softc *); 230#ifdef RE_FIXUP_RX 231static __inline void re_fixup_rx 232 (struct mbuf *); 233#endif 234static int re_rxeof (struct rl_softc *); 235static void re_txeof (struct rl_softc *); 236#ifdef DEVICE_POLLING 237static void re_poll (struct ifnet *, enum poll_cmd, int); 238static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 239#endif 240static int re_intr (void *); 241static void re_tick (void *); 242static void re_tx_task (void *, int); 243static void re_int_task (void *, int); 244static void re_start (struct ifnet *); 245static int re_ioctl (struct ifnet *, u_long, caddr_t); 246static void re_init (void *); 247static void re_init_locked (struct rl_softc *); 248static void re_stop (struct rl_softc *); 249static void re_watchdog (struct rl_softc *); 250static int re_suspend (device_t); 251static int re_resume (device_t); 252static int re_shutdown (device_t); 253static int re_ifmedia_upd (struct ifnet *); 254static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 255 256static void re_eeprom_putbyte (struct rl_softc *, int); 257static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 258static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 259static int re_gmii_readreg (device_t, int, int); 260static int re_gmii_writereg (device_t, int, int, int); 261 262static int re_miibus_readreg (device_t, int, int); 263static int re_miibus_writereg (device_t, int, int, int); 264static void re_miibus_statchg (device_t); 265 266static void re_setmulti (struct rl_softc *); 267static void re_reset (struct rl_softc *); 268static void re_setwol (struct rl_softc *); 269static void re_clrwol (struct rl_softc *); 270 271#ifdef RE_DIAG 272static int re_diag (struct rl_softc *); 273#endif 274 275static device_method_t re_methods[] = { 276 /* Device interface */ 277 DEVMETHOD(device_probe, re_probe), 278 DEVMETHOD(device_attach, re_attach), 279 DEVMETHOD(device_detach, re_detach), 280 DEVMETHOD(device_suspend, re_suspend), 281 DEVMETHOD(device_resume, re_resume), 282 DEVMETHOD(device_shutdown, re_shutdown), 283 284 /* bus interface */ 285 DEVMETHOD(bus_print_child, bus_generic_print_child), 286 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 287 288 /* MII interface */ 289 DEVMETHOD(miibus_readreg, re_miibus_readreg), 290 DEVMETHOD(miibus_writereg, re_miibus_writereg), 291 DEVMETHOD(miibus_statchg, re_miibus_statchg), 292 293 { 0, 0 } 294}; 295 296static driver_t re_driver = { 297 "re", 298 re_methods, 299 sizeof(struct rl_softc) 300}; 301 302static devclass_t re_devclass; 303 304DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 305DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 306DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 307 308#define EE_SET(x) \ 309 CSR_WRITE_1(sc, RL_EECMD, \ 310 CSR_READ_1(sc, RL_EECMD) | x) 311 312#define EE_CLR(x) \ 313 CSR_WRITE_1(sc, RL_EECMD, \ 314 CSR_READ_1(sc, RL_EECMD) & ~x) 315 316/* 317 * Send a read command and address to the EEPROM, check for ACK. 318 */ 319static void 320re_eeprom_putbyte(sc, addr) 321 struct rl_softc *sc; 322 int addr; 323{ 324 register int d, i; 325 326 d = addr | (RL_9346_READ << sc->rl_eewidth); 327 328 /* 329 * Feed in each bit and strobe the clock. 330 */ 331 332 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 333 if (d & i) { 334 EE_SET(RL_EE_DATAIN); 335 } else { 336 EE_CLR(RL_EE_DATAIN); 337 } 338 DELAY(100); 339 EE_SET(RL_EE_CLK); 340 DELAY(150); 341 EE_CLR(RL_EE_CLK); 342 DELAY(100); 343 } 344 345 return; 346} 347 348/* 349 * Read a word of data stored in the EEPROM at address 'addr.' 350 */ 351static void 352re_eeprom_getword(sc, addr, dest) 353 struct rl_softc *sc; 354 int addr; 355 u_int16_t *dest; 356{ 357 register int i; 358 u_int16_t word = 0; 359 360 /* 361 * Send address of word we want to read. 362 */ 363 re_eeprom_putbyte(sc, addr); 364 365 /* 366 * Start reading bits from EEPROM. 367 */ 368 for (i = 0x8000; i; i >>= 1) { 369 EE_SET(RL_EE_CLK); 370 DELAY(100); 371 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 372 word |= i; 373 EE_CLR(RL_EE_CLK); 374 DELAY(100); 375 } 376 377 *dest = word; 378 379 return; 380} 381 382/* 383 * Read a sequence of words from the EEPROM. 384 */ 385static void 386re_read_eeprom(sc, dest, off, cnt) 387 struct rl_softc *sc; 388 caddr_t dest; 389 int off; 390 int cnt; 391{ 392 int i; 393 u_int16_t word = 0, *ptr; 394 395 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 396 397 DELAY(100); 398 399 for (i = 0; i < cnt; i++) { 400 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 401 re_eeprom_getword(sc, off + i, &word); 402 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 403 ptr = (u_int16_t *)(dest + (i * 2)); 404 *ptr = word; 405 } 406 407 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 408 409 return; 410} 411 412static int 413re_gmii_readreg(dev, phy, reg) 414 device_t dev; 415 int phy, reg; 416{ 417 struct rl_softc *sc; 418 u_int32_t rval; 419 int i; 420 421 if (phy != 1) 422 return (0); 423 424 sc = device_get_softc(dev); 425 426 /* Let the rgephy driver read the GMEDIASTAT register */ 427 428 if (reg == RL_GMEDIASTAT) { 429 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 430 return (rval); 431 } 432 433 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 434 DELAY(1000); 435 436 for (i = 0; i < RL_TIMEOUT; i++) { 437 rval = CSR_READ_4(sc, RL_PHYAR); 438 if (rval & RL_PHYAR_BUSY) 439 break; 440 DELAY(100); 441 } 442 443 if (i == RL_TIMEOUT) { 444 device_printf(sc->rl_dev, "PHY read failed\n"); 445 return (0); 446 } 447 448 return (rval & RL_PHYAR_PHYDATA); 449} 450 451static int 452re_gmii_writereg(dev, phy, reg, data) 453 device_t dev; 454 int phy, reg, data; 455{ 456 struct rl_softc *sc; 457 u_int32_t rval; 458 int i; 459 460 sc = device_get_softc(dev); 461 462 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 463 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 464 DELAY(1000); 465 466 for (i = 0; i < RL_TIMEOUT; i++) { 467 rval = CSR_READ_4(sc, RL_PHYAR); 468 if (!(rval & RL_PHYAR_BUSY)) 469 break; 470 DELAY(100); 471 } 472 473 if (i == RL_TIMEOUT) { 474 device_printf(sc->rl_dev, "PHY write failed\n"); 475 return (0); 476 } 477 478 return (0); 479} 480 481static int 482re_miibus_readreg(dev, phy, reg) 483 device_t dev; 484 int phy, reg; 485{ 486 struct rl_softc *sc; 487 u_int16_t rval = 0; 488 u_int16_t re8139_reg = 0; 489 490 sc = device_get_softc(dev); 491 492 if (sc->rl_type == RL_8169) { 493 rval = re_gmii_readreg(dev, phy, reg); 494 return (rval); 495 } 496 497 /* Pretend the internal PHY is only at address 0 */ 498 if (phy) { 499 return (0); 500 } 501 switch (reg) { 502 case MII_BMCR: 503 re8139_reg = RL_BMCR; 504 break; 505 case MII_BMSR: 506 re8139_reg = RL_BMSR; 507 break; 508 case MII_ANAR: 509 re8139_reg = RL_ANAR; 510 break; 511 case MII_ANER: 512 re8139_reg = RL_ANER; 513 break; 514 case MII_ANLPAR: 515 re8139_reg = RL_LPAR; 516 break; 517 case MII_PHYIDR1: 518 case MII_PHYIDR2: 519 return (0); 520 /* 521 * Allow the rlphy driver to read the media status 522 * register. If we have a link partner which does not 523 * support NWAY, this is the register which will tell 524 * us the results of parallel detection. 525 */ 526 case RL_MEDIASTAT: 527 rval = CSR_READ_1(sc, RL_MEDIASTAT); 528 return (rval); 529 default: 530 device_printf(sc->rl_dev, "bad phy register\n"); 531 return (0); 532 } 533 rval = CSR_READ_2(sc, re8139_reg); 534 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 535 /* 8139C+ has different bit layout. */ 536 rval &= ~(BMCR_LOOP | BMCR_ISO); 537 } 538 return (rval); 539} 540 541static int 542re_miibus_writereg(dev, phy, reg, data) 543 device_t dev; 544 int phy, reg, data; 545{ 546 struct rl_softc *sc; 547 u_int16_t re8139_reg = 0; 548 int rval = 0; 549 550 sc = device_get_softc(dev); 551 552 if (sc->rl_type == RL_8169) { 553 rval = re_gmii_writereg(dev, phy, reg, data); 554 return (rval); 555 } 556 557 /* Pretend the internal PHY is only at address 0 */ 558 if (phy) 559 return (0); 560 561 switch (reg) { 562 case MII_BMCR: 563 re8139_reg = RL_BMCR; 564 if (sc->rl_type == RL_8139CPLUS) { 565 /* 8139C+ has different bit layout. */ 566 data &= ~(BMCR_LOOP | BMCR_ISO); 567 } 568 break; 569 case MII_BMSR: 570 re8139_reg = RL_BMSR; 571 break; 572 case MII_ANAR: 573 re8139_reg = RL_ANAR; 574 break; 575 case MII_ANER: 576 re8139_reg = RL_ANER; 577 break; 578 case MII_ANLPAR: 579 re8139_reg = RL_LPAR; 580 break; 581 case MII_PHYIDR1: 582 case MII_PHYIDR2: 583 return (0); 584 break; 585 default: 586 device_printf(sc->rl_dev, "bad phy register\n"); 587 return (0); 588 } 589 CSR_WRITE_2(sc, re8139_reg, data); 590 return (0); 591} 592 593static void 594re_miibus_statchg(dev) 595 device_t dev; 596{ 597 598} 599 600/* 601 * Program the 64-bit multicast hash filter. 602 */ 603static void 604re_setmulti(sc) 605 struct rl_softc *sc; 606{ 607 struct ifnet *ifp; 608 int h = 0; 609 u_int32_t hashes[2] = { 0, 0 }; 610 struct ifmultiaddr *ifma; 611 u_int32_t rxfilt; 612 int mcnt = 0; 613 614 RL_LOCK_ASSERT(sc); 615 616 ifp = sc->rl_ifp; 617 618 619 rxfilt = CSR_READ_4(sc, RL_RXCFG); 620 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 621 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 622 if (ifp->if_flags & IFF_PROMISC) 623 rxfilt |= RL_RXCFG_RX_ALLPHYS; 624 /* 625 * Unlike other hardwares, we have to explicitly set 626 * RL_RXCFG_RX_MULTI to receive multicast frames in 627 * promiscuous mode. 628 */ 629 rxfilt |= RL_RXCFG_RX_MULTI; 630 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 631 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 632 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 633 return; 634 } 635 636 /* first, zot all the existing hash bits */ 637 CSR_WRITE_4(sc, RL_MAR0, 0); 638 CSR_WRITE_4(sc, RL_MAR4, 0); 639 640 /* now program new ones */ 641 IF_ADDR_LOCK(ifp); 642 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 643 if (ifma->ifma_addr->sa_family != AF_LINK) 644 continue; 645 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 646 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 647 if (h < 32) 648 hashes[0] |= (1 << h); 649 else 650 hashes[1] |= (1 << (h - 32)); 651 mcnt++; 652 } 653 IF_ADDR_UNLOCK(ifp); 654 655 if (mcnt) 656 rxfilt |= RL_RXCFG_RX_MULTI; 657 else 658 rxfilt &= ~RL_RXCFG_RX_MULTI; 659 660 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 661 662 /* 663 * For some unfathomable reason, RealTek decided to reverse 664 * the order of the multicast hash registers in the PCI Express 665 * parts. This means we have to write the hash pattern in reverse 666 * order for those devices. 667 */ 668 669 if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) { 670 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 671 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 672 } else { 673 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 674 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 675 } 676} 677 678static void 679re_reset(sc) 680 struct rl_softc *sc; 681{ 682 register int i; 683 684 RL_LOCK_ASSERT(sc); 685 686 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 687 688 for (i = 0; i < RL_TIMEOUT; i++) { 689 DELAY(10); 690 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 691 break; 692 } 693 if (i == RL_TIMEOUT) 694 device_printf(sc->rl_dev, "reset never completed!\n"); 695 696 CSR_WRITE_1(sc, 0x82, 1); 697} 698 699#ifdef RE_DIAG 700 701/* 702 * The following routine is designed to test for a defect on some 703 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 704 * lines connected to the bus, however for a 32-bit only card, they 705 * should be pulled high. The result of this defect is that the 706 * NIC will not work right if you plug it into a 64-bit slot: DMA 707 * operations will be done with 64-bit transfers, which will fail 708 * because the 64-bit data lines aren't connected. 709 * 710 * There's no way to work around this (short of talking a soldering 711 * iron to the board), however we can detect it. The method we use 712 * here is to put the NIC into digital loopback mode, set the receiver 713 * to promiscuous mode, and then try to send a frame. We then compare 714 * the frame data we sent to what was received. If the data matches, 715 * then the NIC is working correctly, otherwise we know the user has 716 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 717 * slot. In the latter case, there's no way the NIC can work correctly, 718 * so we print out a message on the console and abort the device attach. 719 */ 720 721static int 722re_diag(sc) 723 struct rl_softc *sc; 724{ 725 struct ifnet *ifp = sc->rl_ifp; 726 struct mbuf *m0; 727 struct ether_header *eh; 728 struct rl_desc *cur_rx; 729 u_int16_t status; 730 u_int32_t rxstat; 731 int total_len, i, error = 0, phyaddr; 732 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 733 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 734 735 /* Allocate a single mbuf */ 736 MGETHDR(m0, M_DONTWAIT, MT_DATA); 737 if (m0 == NULL) 738 return (ENOBUFS); 739 740 RL_LOCK(sc); 741 742 /* 743 * Initialize the NIC in test mode. This sets the chip up 744 * so that it can send and receive frames, but performs the 745 * following special functions: 746 * - Puts receiver in promiscuous mode 747 * - Enables digital loopback mode 748 * - Leaves interrupts turned off 749 */ 750 751 ifp->if_flags |= IFF_PROMISC; 752 sc->rl_testmode = 1; 753 re_reset(sc); 754 re_init_locked(sc); 755 sc->rl_flags |= RL_FLAG_LINK; 756 if (sc->rl_type == RL_8169) 757 phyaddr = 1; 758 else 759 phyaddr = 0; 760 761 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 762 for (i = 0; i < RL_TIMEOUT; i++) { 763 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 764 if (!(status & BMCR_RESET)) 765 break; 766 } 767 768 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 769 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 770 771 DELAY(100000); 772 773 /* Put some data in the mbuf */ 774 775 eh = mtod(m0, struct ether_header *); 776 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 777 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 778 eh->ether_type = htons(ETHERTYPE_IP); 779 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 780 781 /* 782 * Queue the packet, start transmission. 783 * Note: IF_HANDOFF() ultimately calls re_start() for us. 784 */ 785 786 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 787 RL_UNLOCK(sc); 788 /* XXX: re_diag must not be called when in ALTQ mode */ 789 IF_HANDOFF(&ifp->if_snd, m0, ifp); 790 RL_LOCK(sc); 791 m0 = NULL; 792 793 /* Wait for it to propagate through the chip */ 794 795 DELAY(100000); 796 for (i = 0; i < RL_TIMEOUT; i++) { 797 status = CSR_READ_2(sc, RL_ISR); 798 CSR_WRITE_2(sc, RL_ISR, status); 799 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 800 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 801 break; 802 DELAY(10); 803 } 804 805 if (i == RL_TIMEOUT) { 806 device_printf(sc->rl_dev, 807 "diagnostic failed, failed to receive packet in" 808 " loopback mode\n"); 809 error = EIO; 810 goto done; 811 } 812 813 /* 814 * The packet should have been dumped into the first 815 * entry in the RX DMA ring. Grab it from there. 816 */ 817 818 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 819 sc->rl_ldata.rl_rx_list_map, 820 BUS_DMASYNC_POSTREAD); 821 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 822 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 823 BUS_DMASYNC_POSTREAD); 824 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 825 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 826 827 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 828 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 829 eh = mtod(m0, struct ether_header *); 830 831 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 832 total_len = RL_RXBYTES(cur_rx); 833 rxstat = le32toh(cur_rx->rl_cmdstat); 834 835 if (total_len != ETHER_MIN_LEN) { 836 device_printf(sc->rl_dev, 837 "diagnostic failed, received short packet\n"); 838 error = EIO; 839 goto done; 840 } 841 842 /* Test that the received packet data matches what we sent. */ 843 844 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 845 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 846 ntohs(eh->ether_type) != ETHERTYPE_IP) { 847 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 848 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 849 dst, ":", src, ":", ETHERTYPE_IP); 850 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 851 eh->ether_dhost, ":", eh->ether_shost, ":", 852 ntohs(eh->ether_type)); 853 device_printf(sc->rl_dev, "You may have a defective 32-bit " 854 "NIC plugged into a 64-bit PCI slot.\n"); 855 device_printf(sc->rl_dev, "Please re-install the NIC in a " 856 "32-bit slot for proper operation.\n"); 857 device_printf(sc->rl_dev, "Read the re(4) man page for more " 858 "details.\n"); 859 error = EIO; 860 } 861 862done: 863 /* Turn interface off, release resources */ 864 865 sc->rl_testmode = 0; 866 sc->rl_flags &= ~RL_FLAG_LINK; 867 ifp->if_flags &= ~IFF_PROMISC; 868 re_stop(sc); 869 if (m0 != NULL) 870 m_freem(m0); 871 872 RL_UNLOCK(sc); 873 874 return (error); 875} 876 877#endif 878 879/* 880 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 881 * IDs against our list and return a device name if we find a match. 882 */ 883static int 884re_probe(dev) 885 device_t dev; 886{ 887 struct rl_type *t; 888 uint16_t devid, vendor; 889 uint16_t revid, sdevid; 890 int i; 891 892 vendor = pci_get_vendor(dev); 893 devid = pci_get_device(dev); 894 revid = pci_get_revid(dev); 895 sdevid = pci_get_subdevice(dev); 896 897 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 898 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 899 /* 900 * Only attach to rev. 3 of the Linksys EG1032 adapter. 901 * Rev. 2 is supported by sk(4). 902 */ 903 return (ENXIO); 904 } 905 } 906 907 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 908 if (revid != 0x20) { 909 /* 8139, let rl(4) take care of this device. */ 910 return (ENXIO); 911 } 912 } 913 914 t = re_devs; 915 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 916 if (vendor == t->rl_vid && devid == t->rl_did) { 917 device_set_desc(dev, t->rl_name); 918 return (BUS_PROBE_DEFAULT); 919 } 920 } 921 922 return (ENXIO); 923} 924 925/* 926 * Map a single buffer address. 927 */ 928 929static void 930re_dma_map_addr(arg, segs, nseg, error) 931 void *arg; 932 bus_dma_segment_t *segs; 933 int nseg; 934 int error; 935{ 936 bus_addr_t *addr; 937 938 if (error) 939 return; 940 941 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 942 addr = arg; 943 *addr = segs->ds_addr; 944} 945 946static int 947re_allocmem(dev, sc) 948 device_t dev; 949 struct rl_softc *sc; 950{ 951 bus_size_t rx_list_size, tx_list_size; 952 int error; 953 int i; 954 955 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 956 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 957 958 /* 959 * Allocate the parent bus DMA tag appropriate for PCI. 960 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 961 * register should be set. However some RealTek chips are known 962 * to be buggy on DAC handling, therefore disable DAC by limiting 963 * DMA address space to 32bit. PCIe variants of RealTek chips 964 * may not have the limitation but I took safer path. 965 */ 966 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 967 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 968 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 969 NULL, NULL, &sc->rl_parent_tag); 970 if (error) { 971 device_printf(dev, "could not allocate parent DMA tag\n"); 972 return (error); 973 } 974 975 /* 976 * Allocate map for TX mbufs. 977 */ 978 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 979 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 980 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 981 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 982 if (error) { 983 device_printf(dev, "could not allocate TX DMA tag\n"); 984 return (error); 985 } 986 987 /* 988 * Allocate map for RX mbufs. 989 */ 990 991 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 992 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 993 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 994 if (error) { 995 device_printf(dev, "could not allocate RX DMA tag\n"); 996 return (error); 997 } 998 999 /* 1000 * Allocate map for TX descriptor list. 1001 */ 1002 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1003 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1004 NULL, tx_list_size, 1, tx_list_size, 0, 1005 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1006 if (error) { 1007 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1008 return (error); 1009 } 1010 1011 /* Allocate DMA'able memory for the TX ring */ 1012 1013 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1014 (void **)&sc->rl_ldata.rl_tx_list, 1015 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1016 &sc->rl_ldata.rl_tx_list_map); 1017 if (error) { 1018 device_printf(dev, "could not allocate TX DMA ring\n"); 1019 return (error); 1020 } 1021 1022 /* Load the map for the TX ring. */ 1023 1024 sc->rl_ldata.rl_tx_list_addr = 0; 1025 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1026 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1027 tx_list_size, re_dma_map_addr, 1028 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1029 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1030 device_printf(dev, "could not load TX DMA ring\n"); 1031 return (ENOMEM); 1032 } 1033 1034 /* Create DMA maps for TX buffers */ 1035 1036 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1037 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1038 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1039 if (error) { 1040 device_printf(dev, "could not create DMA map for TX\n"); 1041 return (error); 1042 } 1043 } 1044 1045 /* 1046 * Allocate map for RX descriptor list. 1047 */ 1048 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1049 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1050 NULL, rx_list_size, 1, rx_list_size, 0, 1051 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1052 if (error) { 1053 device_printf(dev, "could not create RX DMA ring tag\n"); 1054 return (error); 1055 } 1056 1057 /* Allocate DMA'able memory for the RX ring */ 1058 1059 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1060 (void **)&sc->rl_ldata.rl_rx_list, 1061 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1062 &sc->rl_ldata.rl_rx_list_map); 1063 if (error) { 1064 device_printf(dev, "could not allocate RX DMA ring\n"); 1065 return (error); 1066 } 1067 1068 /* Load the map for the RX ring. */ 1069 1070 sc->rl_ldata.rl_rx_list_addr = 0; 1071 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1072 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1073 rx_list_size, re_dma_map_addr, 1074 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1075 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1076 device_printf(dev, "could not load RX DMA ring\n"); 1077 return (ENOMEM); 1078 } 1079 1080 /* Create DMA maps for RX buffers */ 1081 1082 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1083 &sc->rl_ldata.rl_rx_sparemap); 1084 if (error) { 1085 device_printf(dev, "could not create spare DMA map for RX\n"); 1086 return (error); 1087 } 1088 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1089 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1090 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1091 if (error) { 1092 device_printf(dev, "could not create DMA map for RX\n"); 1093 return (error); 1094 } 1095 } 1096 1097 return (0); 1098} 1099 1100/* 1101 * Attach the interface. Allocate softc structures, do ifmedia 1102 * setup and ethernet/BPF attach. 1103 */ 1104static int 1105re_attach(dev) 1106 device_t dev; 1107{ 1108 u_char eaddr[ETHER_ADDR_LEN]; 1109 u_int16_t as[ETHER_ADDR_LEN / 2]; 1110 struct rl_softc *sc; 1111 struct ifnet *ifp; 1112 struct rl_hwrev *hw_rev; 1113 int hwrev; 1114 u_int16_t devid, re_did = 0; 1115 int error = 0, rid, i; 1116 int msic, reg; 1117 uint8_t cfg; 1118 1119 sc = device_get_softc(dev); 1120 sc->rl_dev = dev; 1121 1122 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1123 MTX_DEF); 1124 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1125 1126 /* 1127 * Map control/status registers. 1128 */ 1129 pci_enable_busmaster(dev); 1130 1131 devid = pci_get_device(dev); 1132 /* Prefer memory space register mapping over IO space. */ 1133 sc->rl_res_id = PCIR_BAR(1); 1134 sc->rl_res_type = SYS_RES_MEMORY; 1135 /* RTL8168/8101E seems to use different BARs. */ 1136 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1137 sc->rl_res_id = PCIR_BAR(2); 1138 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1139 &sc->rl_res_id, RF_ACTIVE); 1140 1141 if (sc->rl_res == NULL) { 1142 sc->rl_res_id = PCIR_BAR(0); 1143 sc->rl_res_type = SYS_RES_IOPORT; 1144 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1145 &sc->rl_res_id, RF_ACTIVE); 1146 if (sc->rl_res == NULL) { 1147 device_printf(dev, "couldn't map ports/memory\n"); 1148 error = ENXIO; 1149 goto fail; 1150 } 1151 } 1152 1153 sc->rl_btag = rman_get_bustag(sc->rl_res); 1154 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1155 1156 msic = 0; 1157 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1158 msic = pci_msi_count(dev); 1159 if (bootverbose) 1160 device_printf(dev, "MSI count : %d\n", msic); 1161 } 1162 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1163 if (pci_alloc_msi(dev, &msic) == 0) { 1164 if (msic == RL_MSI_MESSAGES) { 1165 device_printf(dev, "Using %d MSI messages\n", 1166 msic); 1167 sc->rl_flags |= RL_FLAG_MSI; 1168 /* Explicitly set MSI enable bit. */ 1169 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1170 cfg = CSR_READ_1(sc, RL_CFG2); 1171 cfg |= RL_CFG2_MSI; 1172 CSR_WRITE_1(sc, RL_CFG2, cfg); 1173 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1174 } else 1175 pci_release_msi(dev); 1176 } 1177 } 1178 1179 /* Allocate interrupt */ 1180 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1181 rid = 0; 1182 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1183 RF_SHAREABLE | RF_ACTIVE); 1184 if (sc->rl_irq[0] == NULL) { 1185 device_printf(dev, "couldn't allocate IRQ resources\n"); 1186 error = ENXIO; 1187 goto fail; 1188 } 1189 } else { 1190 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1191 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1192 SYS_RES_IRQ, &rid, RF_ACTIVE); 1193 if (sc->rl_irq[i] == NULL) { 1194 device_printf(dev, 1195 "couldn't llocate IRQ resources for " 1196 "message %d\n", rid); 1197 error = ENXIO; 1198 goto fail; 1199 } 1200 } 1201 } 1202 1203 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1204 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1205 cfg = CSR_READ_1(sc, RL_CFG2); 1206 if ((cfg & RL_CFG2_MSI) != 0) { 1207 device_printf(dev, "turning off MSI enable bit.\n"); 1208 cfg &= ~RL_CFG2_MSI; 1209 CSR_WRITE_1(sc, RL_CFG2, cfg); 1210 } 1211 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1212 } 1213 1214 /* Reset the adapter. */ 1215 RL_LOCK(sc); 1216 re_reset(sc); 1217 RL_UNLOCK(sc); 1218 1219 hw_rev = re_hwrevs; 1220 hwrev = CSR_READ_4(sc, RL_TXCFG); 1221 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1222 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1223 hwrev &= RL_TXCFG_HWREV; 1224 while (hw_rev->rl_desc != NULL) { 1225 if (hw_rev->rl_rev == hwrev) { 1226 sc->rl_type = hw_rev->rl_type; 1227 break; 1228 } 1229 hw_rev++; 1230 } 1231 if (hw_rev->rl_desc == NULL) { 1232 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1233 error = ENXIO; 1234 goto fail; 1235 } 1236 1237 switch (hw_rev->rl_rev) { 1238 case RL_HWREV_8139CPLUS: 1239 sc->rl_flags |= RL_FLAG_NOJUMBO; 1240 break; 1241 case RL_HWREV_8100E: 1242 case RL_HWREV_8101E: 1243 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE; 1244 break; 1245 case RL_HWREV_8168_SPIN1: 1246 case RL_HWREV_8168_SPIN2: 1247 case RL_HWREV_8168_SPIN3: 1248 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1249 RL_FLAG_MACSTAT; 1250 break; 1251 case RL_HWREV_8168C: 1252 case RL_HWREV_8168C_SPIN2: 1253 case RL_HWREV_8168CP: 1254 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1255 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; 1256 /* 1257 * These controllers support jumbo frame but it seems 1258 * that enabling it requires touching additional magic 1259 * registers. Depending on MAC revisions some 1260 * controllers need to disable checksum offload. So 1261 * disable jumbo frame until I have better idea what 1262 * it really requires to make it support. 1263 * RTL8168C/CP : supports up to 6KB jumbo frame. 1264 * RTL8111C/CP : supports up to 9KB jumbo frame. 1265 */ 1266 sc->rl_flags |= RL_FLAG_NOJUMBO; 1267 break; 1268 case RL_HWREV_8169_8110SB: 1269 case RL_HWREV_8169_8110SC: 1270 case RL_HWREV_8169_8110SBL: 1271 sc->rl_flags |= RL_FLAG_PHYWAKE; 1272 break; 1273 default: 1274 break; 1275 } 1276 1277 /* Enable PME. */ 1278 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1279 cfg = CSR_READ_1(sc, RL_CFG1); 1280 cfg |= RL_CFG1_PME; 1281 CSR_WRITE_1(sc, RL_CFG1, cfg); 1282 cfg = CSR_READ_1(sc, RL_CFG5); 1283 cfg &= RL_CFG5_PME_STS; 1284 CSR_WRITE_1(sc, RL_CFG5, cfg); 1285 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1286 1287 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1288 /* 1289 * XXX Should have a better way to extract station 1290 * address from EEPROM. 1291 */ 1292 for (i = 0; i < ETHER_ADDR_LEN; i++) 1293 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1294 } else { 1295 sc->rl_eewidth = RL_9356_ADDR_LEN; 1296 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1297 if (re_did != 0x8129) 1298 sc->rl_eewidth = RL_9346_ADDR_LEN; 1299 1300 /* 1301 * Get station address from the EEPROM. 1302 */ 1303 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1304 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1305 as[i] = le16toh(as[i]); 1306 bcopy(as, eaddr, sizeof(eaddr)); 1307 } 1308 1309 if (sc->rl_type == RL_8169) { 1310 /* Set RX length mask and number of descriptors. */ 1311 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1312 sc->rl_txstart = RL_GTXSTART; 1313 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1314 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1315 } else { 1316 /* Set RX length mask and number of descriptors. */ 1317 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1318 sc->rl_txstart = RL_TXSTART; 1319 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1320 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1321 } 1322 1323 error = re_allocmem(dev, sc); 1324 if (error) 1325 goto fail; 1326 1327 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1328 if (ifp == NULL) { 1329 device_printf(dev, "can not if_alloc()\n"); 1330 error = ENOSPC; 1331 goto fail; 1332 } 1333 1334 /* Take PHY out of power down mode. */ 1335 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1336 re_gmii_writereg(dev, 1, 0x1f, 0); 1337 re_gmii_writereg(dev, 1, 0x0e, 0); 1338 } 1339 1340 /* Do MII setup */ 1341 if (mii_phy_probe(dev, &sc->rl_miibus, 1342 re_ifmedia_upd, re_ifmedia_sts)) { 1343 device_printf(dev, "MII without any phy!\n"); 1344 error = ENXIO; 1345 goto fail; 1346 } 1347 1348 ifp->if_softc = sc; 1349 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1350 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1351 ifp->if_ioctl = re_ioctl; 1352 ifp->if_start = re_start; 1353 ifp->if_hwassist = RE_CSUM_FEATURES; 1354 ifp->if_capabilities = IFCAP_HWCSUM; 1355 ifp->if_capenable = ifp->if_capabilities; 1356 ifp->if_init = re_init; 1357 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1358 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1359 IFQ_SET_READY(&ifp->if_snd); 1360 1361 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1362 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1363 1364 /* 1365 * XXX 1366 * Still have no idea how to make TSO work on 8168C, 8168CP, 1367 * 8111C and 8111CP. 1368 */ 1369 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1370 ifp->if_hwassist |= CSUM_TSO; 1371 ifp->if_capabilities |= IFCAP_TSO4; 1372 } 1373 1374 /* 1375 * Call MI attach routine. 1376 */ 1377 ether_ifattach(ifp, eaddr); 1378 1379 /* VLAN capability setup */ 1380 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1381 if (ifp->if_capabilities & IFCAP_HWCSUM) 1382 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1383 /* Enable WOL if PM is supported. */ 1384 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1385 ifp->if_capabilities |= IFCAP_WOL; 1386 ifp->if_capenable = ifp->if_capabilities; 1387#ifdef DEVICE_POLLING 1388 ifp->if_capabilities |= IFCAP_POLLING; 1389#endif 1390 /* 1391 * Tell the upper layer(s) we support long frames. 1392 * Must appear after the call to ether_ifattach() because 1393 * ether_ifattach() sets ifi_hdrlen to the default value. 1394 */ 1395 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1396 1397#ifdef RE_DIAG 1398 /* 1399 * Perform hardware diagnostic on the original RTL8169. 1400 * Some 32-bit cards were incorrectly wired and would 1401 * malfunction if plugged into a 64-bit slot. 1402 */ 1403 1404 if (hwrev == RL_HWREV_8169) { 1405 error = re_diag(sc); 1406 if (error) { 1407 device_printf(dev, 1408 "attach aborted due to hardware diag failure\n"); 1409 ether_ifdetach(ifp); 1410 goto fail; 1411 } 1412 } 1413#endif 1414 1415 /* Hook interrupt last to avoid having to lock softc */ 1416 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1417 error = bus_setup_intr(dev, sc->rl_irq[0], 1418 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1419 &sc->rl_intrhand[0]); 1420 else { 1421 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1422 error = bus_setup_intr(dev, sc->rl_irq[i], 1423 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1424 &sc->rl_intrhand[i]); 1425 if (error != 0) 1426 break; 1427 } 1428 } 1429 if (error) { 1430 device_printf(dev, "couldn't set up irq\n"); 1431 ether_ifdetach(ifp); 1432 } 1433 1434fail: 1435 1436 if (error) 1437 re_detach(dev); 1438 1439 return (error); 1440} 1441 1442/* 1443 * Shutdown hardware and free up resources. This can be called any 1444 * time after the mutex has been initialized. It is called in both 1445 * the error case in attach and the normal detach case so it needs 1446 * to be careful about only freeing resources that have actually been 1447 * allocated. 1448 */ 1449static int 1450re_detach(dev) 1451 device_t dev; 1452{ 1453 struct rl_softc *sc; 1454 struct ifnet *ifp; 1455 int i, rid; 1456 1457 sc = device_get_softc(dev); 1458 ifp = sc->rl_ifp; 1459 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1460 1461 /* These should only be active if attach succeeded */ 1462 if (device_is_attached(dev)) { 1463#ifdef DEVICE_POLLING 1464 if (ifp->if_capenable & IFCAP_POLLING) 1465 ether_poll_deregister(ifp); 1466#endif 1467 RL_LOCK(sc); 1468#if 0 1469 sc->suspended = 1; 1470#endif 1471 re_stop(sc); 1472 RL_UNLOCK(sc); 1473 callout_drain(&sc->rl_stat_callout); 1474 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1475 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1476 /* 1477 * Force off the IFF_UP flag here, in case someone 1478 * still had a BPF descriptor attached to this 1479 * interface. If they do, ether_ifdetach() will cause 1480 * the BPF code to try and clear the promisc mode 1481 * flag, which will bubble down to re_ioctl(), 1482 * which will try to call re_init() again. This will 1483 * turn the NIC back on and restart the MII ticker, 1484 * which will panic the system when the kernel tries 1485 * to invoke the re_tick() function that isn't there 1486 * anymore. 1487 */ 1488 ifp->if_flags &= ~IFF_UP; 1489 ether_ifdetach(ifp); 1490 } 1491 if (sc->rl_miibus) 1492 device_delete_child(dev, sc->rl_miibus); 1493 bus_generic_detach(dev); 1494 1495 /* 1496 * The rest is resource deallocation, so we should already be 1497 * stopped here. 1498 */ 1499 1500 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1501 if (sc->rl_intrhand[i] != NULL) { 1502 bus_teardown_intr(dev, sc->rl_irq[i], 1503 sc->rl_intrhand[i]); 1504 sc->rl_intrhand[i] = NULL; 1505 } 1506 } 1507 if (ifp != NULL) 1508 if_free(ifp); 1509 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1510 if (sc->rl_irq[0] != NULL) { 1511 bus_release_resource(dev, SYS_RES_IRQ, 0, 1512 sc->rl_irq[0]); 1513 sc->rl_irq[0] = NULL; 1514 } 1515 } else { 1516 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1517 if (sc->rl_irq[i] != NULL) { 1518 bus_release_resource(dev, SYS_RES_IRQ, rid, 1519 sc->rl_irq[i]); 1520 sc->rl_irq[i] = NULL; 1521 } 1522 } 1523 pci_release_msi(dev); 1524 } 1525 if (sc->rl_res) 1526 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1527 sc->rl_res); 1528 1529 /* Unload and free the RX DMA ring memory and map */ 1530 1531 if (sc->rl_ldata.rl_rx_list_tag) { 1532 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1533 sc->rl_ldata.rl_rx_list_map); 1534 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1535 sc->rl_ldata.rl_rx_list, 1536 sc->rl_ldata.rl_rx_list_map); 1537 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1538 } 1539 1540 /* Unload and free the TX DMA ring memory and map */ 1541 1542 if (sc->rl_ldata.rl_tx_list_tag) { 1543 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1544 sc->rl_ldata.rl_tx_list_map); 1545 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1546 sc->rl_ldata.rl_tx_list, 1547 sc->rl_ldata.rl_tx_list_map); 1548 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1549 } 1550 1551 /* Destroy all the RX and TX buffer maps */ 1552 1553 if (sc->rl_ldata.rl_tx_mtag) { 1554 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1555 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1556 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1557 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1558 } 1559 if (sc->rl_ldata.rl_rx_mtag) { 1560 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1561 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1562 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1563 if (sc->rl_ldata.rl_rx_sparemap) 1564 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1565 sc->rl_ldata.rl_rx_sparemap); 1566 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1567 } 1568 1569 /* Unload and free the stats buffer and map */ 1570 1571 if (sc->rl_ldata.rl_stag) { 1572 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1573 sc->rl_ldata.rl_rx_list_map); 1574 bus_dmamem_free(sc->rl_ldata.rl_stag, 1575 sc->rl_ldata.rl_stats, 1576 sc->rl_ldata.rl_smap); 1577 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1578 } 1579 1580 if (sc->rl_parent_tag) 1581 bus_dma_tag_destroy(sc->rl_parent_tag); 1582 1583 mtx_destroy(&sc->rl_mtx); 1584 1585 return (0); 1586} 1587 1588static __inline void 1589re_discard_rxbuf(sc, idx) 1590 struct rl_softc *sc; 1591 int idx; 1592{ 1593 struct rl_desc *desc; 1594 struct rl_rxdesc *rxd; 1595 uint32_t cmdstat; 1596 1597 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1598 desc = &sc->rl_ldata.rl_rx_list[idx]; 1599 desc->rl_vlanctl = 0; 1600 cmdstat = rxd->rx_size; 1601 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1602 cmdstat |= RL_RDESC_CMD_EOR; 1603 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1604} 1605 1606static int 1607re_newbuf(sc, idx) 1608 struct rl_softc *sc; 1609 int idx; 1610{ 1611 struct mbuf *m; 1612 struct rl_rxdesc *rxd; 1613 bus_dma_segment_t segs[1]; 1614 bus_dmamap_t map; 1615 struct rl_desc *desc; 1616 uint32_t cmdstat; 1617 int error, nsegs; 1618 1619 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1620 if (m == NULL) 1621 return (ENOBUFS); 1622 1623 m->m_len = m->m_pkthdr.len = MCLBYTES; 1624#ifdef RE_FIXUP_RX 1625 /* 1626 * This is part of an evil trick to deal with non-x86 platforms. 1627 * The RealTek chip requires RX buffers to be aligned on 64-bit 1628 * boundaries, but that will hose non-x86 machines. To get around 1629 * this, we leave some empty space at the start of each buffer 1630 * and for non-x86 hosts, we copy the buffer back six bytes 1631 * to achieve word alignment. This is slightly more efficient 1632 * than allocating a new buffer, copying the contents, and 1633 * discarding the old buffer. 1634 */ 1635 m_adj(m, RE_ETHER_ALIGN); 1636#endif 1637 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1638 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1639 if (error != 0) { 1640 m_freem(m); 1641 return (ENOBUFS); 1642 } 1643 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1644 1645 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1646 if (rxd->rx_m != NULL) { 1647 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1648 BUS_DMASYNC_POSTREAD); 1649 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1650 } 1651 1652 rxd->rx_m = m; 1653 map = rxd->rx_dmamap; 1654 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1655 rxd->rx_size = segs[0].ds_len; 1656 sc->rl_ldata.rl_rx_sparemap = map; 1657 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1658 BUS_DMASYNC_PREREAD); 1659 1660 desc = &sc->rl_ldata.rl_rx_list[idx]; 1661 desc->rl_vlanctl = 0; 1662 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1663 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1664 cmdstat = segs[0].ds_len; 1665 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1666 cmdstat |= RL_RDESC_CMD_EOR; 1667 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1668 1669 return (0); 1670} 1671 1672#ifdef RE_FIXUP_RX 1673static __inline void 1674re_fixup_rx(m) 1675 struct mbuf *m; 1676{ 1677 int i; 1678 uint16_t *src, *dst; 1679 1680 src = mtod(m, uint16_t *); 1681 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1682 1683 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1684 *dst++ = *src++; 1685 1686 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1687 1688 return; 1689} 1690#endif 1691 1692static int 1693re_tx_list_init(sc) 1694 struct rl_softc *sc; 1695{ 1696 struct rl_desc *desc; 1697 int i; 1698 1699 RL_LOCK_ASSERT(sc); 1700 1701 bzero(sc->rl_ldata.rl_tx_list, 1702 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1703 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1704 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1705 /* Set EOR. */ 1706 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1707 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1708 1709 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1710 sc->rl_ldata.rl_tx_list_map, 1711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1712 1713 sc->rl_ldata.rl_tx_prodidx = 0; 1714 sc->rl_ldata.rl_tx_considx = 0; 1715 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1716 1717 return (0); 1718} 1719 1720static int 1721re_rx_list_init(sc) 1722 struct rl_softc *sc; 1723{ 1724 int error, i; 1725 1726 bzero(sc->rl_ldata.rl_rx_list, 1727 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1728 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1729 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1730 if ((error = re_newbuf(sc, i)) != 0) 1731 return (error); 1732 } 1733 1734 /* Flush the RX descriptors */ 1735 1736 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1737 sc->rl_ldata.rl_rx_list_map, 1738 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1739 1740 sc->rl_ldata.rl_rx_prodidx = 0; 1741 sc->rl_head = sc->rl_tail = NULL; 1742 1743 return (0); 1744} 1745 1746/* 1747 * RX handler for C+ and 8169. For the gigE chips, we support 1748 * the reception of jumbo frames that have been fragmented 1749 * across multiple 2K mbuf cluster buffers. 1750 */ 1751static int 1752re_rxeof(sc) 1753 struct rl_softc *sc; 1754{ 1755 struct mbuf *m; 1756 struct ifnet *ifp; 1757 int i, total_len; 1758 struct rl_desc *cur_rx; 1759 u_int32_t rxstat, rxvlan; 1760 int maxpkt = 16; 1761 1762 RL_LOCK_ASSERT(sc); 1763 1764 ifp = sc->rl_ifp; 1765 1766 /* Invalidate the descriptor memory */ 1767 1768 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1769 sc->rl_ldata.rl_rx_list_map, 1770 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1771 1772 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1773 i = RL_RX_DESC_NXT(sc, i)) { 1774 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1775 rxstat = le32toh(cur_rx->rl_cmdstat); 1776 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1777 break; 1778 total_len = rxstat & sc->rl_rxlenmask; 1779 rxvlan = le32toh(cur_rx->rl_vlanctl); 1780 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1781 1782 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1783 if (re_newbuf(sc, i) != 0) { 1784 /* 1785 * If this is part of a multi-fragment packet, 1786 * discard all the pieces. 1787 */ 1788 if (sc->rl_head != NULL) { 1789 m_freem(sc->rl_head); 1790 sc->rl_head = sc->rl_tail = NULL; 1791 } 1792 re_discard_rxbuf(sc, i); 1793 continue; 1794 } 1795 m->m_len = RE_RX_DESC_BUFLEN; 1796 if (sc->rl_head == NULL) 1797 sc->rl_head = sc->rl_tail = m; 1798 else { 1799 m->m_flags &= ~M_PKTHDR; 1800 sc->rl_tail->m_next = m; 1801 sc->rl_tail = m; 1802 } 1803 continue; 1804 } 1805 1806 /* 1807 * NOTE: for the 8139C+, the frame length field 1808 * is always 12 bits in size, but for the gigE chips, 1809 * it is 13 bits (since the max RX frame length is 16K). 1810 * Unfortunately, all 32 bits in the status word 1811 * were already used, so to make room for the extra 1812 * length bit, RealTek took out the 'frame alignment 1813 * error' bit and shifted the other status bits 1814 * over one slot. The OWN, EOR, FS and LS bits are 1815 * still in the same places. We have already extracted 1816 * the frame length and checked the OWN bit, so rather 1817 * than using an alternate bit mapping, we shift the 1818 * status bits one space to the right so we can evaluate 1819 * them using the 8169 status as though it was in the 1820 * same format as that of the 8139C+. 1821 */ 1822 if (sc->rl_type == RL_8169) 1823 rxstat >>= 1; 1824 1825 /* 1826 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1827 * set, but if CRC is clear, it will still be a valid frame. 1828 */ 1829 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1830 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1831 ifp->if_ierrors++; 1832 /* 1833 * If this is part of a multi-fragment packet, 1834 * discard all the pieces. 1835 */ 1836 if (sc->rl_head != NULL) { 1837 m_freem(sc->rl_head); 1838 sc->rl_head = sc->rl_tail = NULL; 1839 } 1840 re_discard_rxbuf(sc, i); 1841 continue; 1842 } 1843 1844 /* 1845 * If allocating a replacement mbuf fails, 1846 * reload the current one. 1847 */ 1848 1849 if (re_newbuf(sc, i) != 0) { 1850 ifp->if_iqdrops++; 1851 if (sc->rl_head != NULL) { 1852 m_freem(sc->rl_head); 1853 sc->rl_head = sc->rl_tail = NULL; 1854 } 1855 re_discard_rxbuf(sc, i); 1856 continue; 1857 } 1858 1859 if (sc->rl_head != NULL) { 1860 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1861 if (m->m_len == 0) 1862 m->m_len = RE_RX_DESC_BUFLEN; 1863 /* 1864 * Special case: if there's 4 bytes or less 1865 * in this buffer, the mbuf can be discarded: 1866 * the last 4 bytes is the CRC, which we don't 1867 * care about anyway. 1868 */ 1869 if (m->m_len <= ETHER_CRC_LEN) { 1870 sc->rl_tail->m_len -= 1871 (ETHER_CRC_LEN - m->m_len); 1872 m_freem(m); 1873 } else { 1874 m->m_len -= ETHER_CRC_LEN; 1875 m->m_flags &= ~M_PKTHDR; 1876 sc->rl_tail->m_next = m; 1877 } 1878 m = sc->rl_head; 1879 sc->rl_head = sc->rl_tail = NULL; 1880 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1881 } else 1882 m->m_pkthdr.len = m->m_len = 1883 (total_len - ETHER_CRC_LEN); 1884 1885#ifdef RE_FIXUP_RX 1886 re_fixup_rx(m); 1887#endif 1888 ifp->if_ipackets++; 1889 m->m_pkthdr.rcvif = ifp; 1890 1891 /* Do RX checksumming if enabled */ 1892 1893 if (ifp->if_capenable & IFCAP_RXCSUM) { 1894 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1895 /* Check IP header checksum */ 1896 if (rxstat & RL_RDESC_STAT_PROTOID) 1897 m->m_pkthdr.csum_flags |= 1898 CSUM_IP_CHECKED; 1899 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1900 m->m_pkthdr.csum_flags |= 1901 CSUM_IP_VALID; 1902 1903 /* Check TCP/UDP checksum */ 1904 if ((RL_TCPPKT(rxstat) && 1905 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1906 (RL_UDPPKT(rxstat) && 1907 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1908 m->m_pkthdr.csum_flags |= 1909 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1910 m->m_pkthdr.csum_data = 0xffff; 1911 } 1912 } else { 1913 /* 1914 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1915 */ 1916 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1917 (rxvlan & RL_RDESC_IPV4)) 1918 m->m_pkthdr.csum_flags |= 1919 CSUM_IP_CHECKED; 1920 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1921 (rxvlan & RL_RDESC_IPV4)) 1922 m->m_pkthdr.csum_flags |= 1923 CSUM_IP_VALID; 1924 if (((rxstat & RL_RDESC_STAT_TCP) && 1925 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1926 ((rxstat & RL_RDESC_STAT_UDP) && 1927 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1928 m->m_pkthdr.csum_flags |= 1929 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1930 m->m_pkthdr.csum_data = 0xffff; 1931 } 1932 } 1933 } 1934 maxpkt--; 1935 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1936 m->m_pkthdr.ether_vtag = 1937 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1938 m->m_flags |= M_VLANTAG; 1939 } 1940 RL_UNLOCK(sc); 1941 (*ifp->if_input)(ifp, m); 1942 RL_LOCK(sc); 1943 } 1944 1945 /* Flush the RX DMA ring */ 1946 1947 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1948 sc->rl_ldata.rl_rx_list_map, 1949 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1950 1951 sc->rl_ldata.rl_rx_prodidx = i; 1952 1953 if (maxpkt) 1954 return(EAGAIN); 1955 1956 return(0); 1957} 1958 1959static void 1960re_txeof(sc) 1961 struct rl_softc *sc; 1962{ 1963 struct ifnet *ifp; 1964 struct rl_txdesc *txd; 1965 u_int32_t txstat; 1966 int cons; 1967 1968 cons = sc->rl_ldata.rl_tx_considx; 1969 if (cons == sc->rl_ldata.rl_tx_prodidx) 1970 return; 1971 1972 ifp = sc->rl_ifp; 1973 /* Invalidate the TX descriptor list */ 1974 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1975 sc->rl_ldata.rl_tx_list_map, 1976 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1977 1978 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1979 cons = RL_TX_DESC_NXT(sc, cons)) { 1980 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1981 if (txstat & RL_TDESC_STAT_OWN) 1982 break; 1983 /* 1984 * We only stash mbufs in the last descriptor 1985 * in a fragment chain, which also happens to 1986 * be the only place where the TX status bits 1987 * are valid. 1988 */ 1989 if (txstat & RL_TDESC_CMD_EOF) { 1990 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1991 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1992 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1993 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1994 txd->tx_dmamap); 1995 KASSERT(txd->tx_m != NULL, 1996 ("%s: freeing NULL mbufs!", __func__)); 1997 m_freem(txd->tx_m); 1998 txd->tx_m = NULL; 1999 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2000 RL_TDESC_STAT_COLCNT)) 2001 ifp->if_collisions++; 2002 if (txstat & RL_TDESC_STAT_TXERRSUM) 2003 ifp->if_oerrors++; 2004 else 2005 ifp->if_opackets++; 2006 } 2007 sc->rl_ldata.rl_tx_free++; 2008 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2009 } 2010 sc->rl_ldata.rl_tx_considx = cons; 2011 2012 /* No changes made to the TX ring, so no flush needed */ 2013 2014 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2015 /* 2016 * Some chips will ignore a second TX request issued 2017 * while an existing transmission is in progress. If 2018 * the transmitter goes idle but there are still 2019 * packets waiting to be sent, we need to restart the 2020 * channel here to flush them out. This only seems to 2021 * be required with the PCIe devices. 2022 */ 2023 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2024 2025#ifdef RE_TX_MODERATION 2026 /* 2027 * If not all descriptors have been reaped yet, reload 2028 * the timer so that we will eventually get another 2029 * interrupt that will cause us to re-enter this routine. 2030 * This is done in case the transmitter has gone idle. 2031 */ 2032 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2033#endif 2034 } else 2035 sc->rl_watchdog_timer = 0; 2036} 2037 2038static void 2039re_tick(xsc) 2040 void *xsc; 2041{ 2042 struct rl_softc *sc; 2043 struct mii_data *mii; 2044 struct ifnet *ifp; 2045 2046 sc = xsc; 2047 ifp = sc->rl_ifp; 2048 2049 RL_LOCK_ASSERT(sc); 2050 2051 re_watchdog(sc); 2052 2053 mii = device_get_softc(sc->rl_miibus); 2054 mii_tick(mii); 2055 if ((sc->rl_flags & RL_FLAG_LINK) != 0) { 2056 if (!(mii->mii_media_status & IFM_ACTIVE)) 2057 sc->rl_flags &= ~RL_FLAG_LINK; 2058 } else { 2059 if (mii->mii_media_status & IFM_ACTIVE && 2060 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2061 sc->rl_flags |= RL_FLAG_LINK; 2062 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2063 taskqueue_enqueue_fast(taskqueue_fast, 2064 &sc->rl_txtask); 2065 } 2066 } 2067 2068 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2069} 2070 2071#ifdef DEVICE_POLLING 2072static void 2073re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2074{ 2075 struct rl_softc *sc = ifp->if_softc; 2076 2077 RL_LOCK(sc); 2078 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2079 re_poll_locked(ifp, cmd, count); 2080 RL_UNLOCK(sc); 2081} 2082 2083static void 2084re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2085{ 2086 struct rl_softc *sc = ifp->if_softc; 2087 2088 RL_LOCK_ASSERT(sc); 2089 2090 sc->rxcycles = count; 2091 re_rxeof(sc); 2092 re_txeof(sc); 2093 2094 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2095 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2096 2097 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2098 u_int16_t status; 2099 2100 status = CSR_READ_2(sc, RL_ISR); 2101 if (status == 0xffff) 2102 return; 2103 if (status) 2104 CSR_WRITE_2(sc, RL_ISR, status); 2105 2106 /* 2107 * XXX check behaviour on receiver stalls. 2108 */ 2109 2110 if (status & RL_ISR_SYSTEM_ERR) { 2111 re_reset(sc); 2112 re_init_locked(sc); 2113 } 2114 } 2115} 2116#endif /* DEVICE_POLLING */ 2117 2118static int 2119re_intr(arg) 2120 void *arg; 2121{ 2122 struct rl_softc *sc; 2123 uint16_t status; 2124 2125 sc = arg; 2126 2127 status = CSR_READ_2(sc, RL_ISR); 2128 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2129 return (FILTER_STRAY); 2130 CSR_WRITE_2(sc, RL_IMR, 0); 2131 2132 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2133 2134 return (FILTER_HANDLED); 2135} 2136 2137static void 2138re_int_task(arg, npending) 2139 void *arg; 2140 int npending; 2141{ 2142 struct rl_softc *sc; 2143 struct ifnet *ifp; 2144 u_int16_t status; 2145 int rval = 0; 2146 2147 sc = arg; 2148 ifp = sc->rl_ifp; 2149 2150 RL_LOCK(sc); 2151 2152 status = CSR_READ_2(sc, RL_ISR); 2153 CSR_WRITE_2(sc, RL_ISR, status); 2154 2155 if (sc->suspended || 2156 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2157 RL_UNLOCK(sc); 2158 return; 2159 } 2160 2161#ifdef DEVICE_POLLING 2162 if (ifp->if_capenable & IFCAP_POLLING) { 2163 RL_UNLOCK(sc); 2164 return; 2165 } 2166#endif 2167 2168 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2169 rval = re_rxeof(sc); 2170 2171#ifdef RE_TX_MODERATION 2172 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2173#else 2174 if (status & (RL_ISR_TX_OK| 2175#endif 2176 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2177 re_txeof(sc); 2178 2179 if (status & RL_ISR_SYSTEM_ERR) { 2180 re_reset(sc); 2181 re_init_locked(sc); 2182 } 2183 2184 if (status & RL_ISR_LINKCHG) { 2185 callout_stop(&sc->rl_stat_callout); 2186 re_tick(sc); 2187 } 2188 2189 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2190 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2191 2192 RL_UNLOCK(sc); 2193 2194 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2195 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2196 return; 2197 } 2198 2199 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2200 2201 return; 2202} 2203 2204static int 2205re_encap(sc, m_head) 2206 struct rl_softc *sc; 2207 struct mbuf **m_head; 2208{ 2209 struct rl_txdesc *txd, *txd_last; 2210 bus_dma_segment_t segs[RL_NTXSEGS]; 2211 bus_dmamap_t map; 2212 struct mbuf *m_new; 2213 struct rl_desc *desc; 2214 int nsegs, prod; 2215 int i, error, ei, si; 2216 int padlen; 2217 uint32_t cmdstat, csum_flags, vlanctl; 2218 2219 RL_LOCK_ASSERT(sc); 2220 M_ASSERTPKTHDR((*m_head)); 2221 2222 /* 2223 * With some of the RealTek chips, using the checksum offload 2224 * support in conjunction with the autopadding feature results 2225 * in the transmission of corrupt frames. For example, if we 2226 * need to send a really small IP fragment that's less than 60 2227 * bytes in size, and IP header checksumming is enabled, the 2228 * resulting ethernet frame that appears on the wire will 2229 * have garbled payload. To work around this, if TX IP checksum 2230 * offload is enabled, we always manually pad short frames out 2231 * to the minimum ethernet frame size. 2232 */ 2233 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2234 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2235 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2236 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2237 if (M_WRITABLE(*m_head) == 0) { 2238 /* Get a writable copy. */ 2239 m_new = m_dup(*m_head, M_DONTWAIT); 2240 m_freem(*m_head); 2241 if (m_new == NULL) { 2242 *m_head = NULL; 2243 return (ENOBUFS); 2244 } 2245 *m_head = m_new; 2246 } 2247 if ((*m_head)->m_next != NULL || 2248 M_TRAILINGSPACE(*m_head) < padlen) { 2249 m_new = m_defrag(*m_head, M_DONTWAIT); 2250 if (m_new == NULL) { 2251 m_freem(*m_head); 2252 *m_head = NULL; 2253 return (ENOBUFS); 2254 } 2255 } else 2256 m_new = *m_head; 2257 2258 /* 2259 * Manually pad short frames, and zero the pad space 2260 * to avoid leaking data. 2261 */ 2262 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2263 m_new->m_pkthdr.len += padlen; 2264 m_new->m_len = m_new->m_pkthdr.len; 2265 *m_head = m_new; 2266 } 2267 2268 prod = sc->rl_ldata.rl_tx_prodidx; 2269 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2270 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2271 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2272 if (error == EFBIG) { 2273 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2274 if (m_new == NULL) { 2275 m_freem(*m_head); 2276 *m_head = NULL; 2277 return (ENOBUFS); 2278 } 2279 *m_head = m_new; 2280 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2281 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2282 if (error != 0) { 2283 m_freem(*m_head); 2284 *m_head = NULL; 2285 return (error); 2286 } 2287 } else if (error != 0) 2288 return (error); 2289 if (nsegs == 0) { 2290 m_freem(*m_head); 2291 *m_head = NULL; 2292 return (EIO); 2293 } 2294 2295 /* Check for number of available descriptors. */ 2296 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2297 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2298 return (ENOBUFS); 2299 } 2300 2301 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2302 BUS_DMASYNC_PREWRITE); 2303 2304 /* 2305 * Set up checksum offload. Note: checksum offload bits must 2306 * appear in all descriptors of a multi-descriptor transmit 2307 * attempt. This is according to testing done with an 8169 2308 * chip. This is a requirement. 2309 */ 2310 vlanctl = 0; 2311 csum_flags = 0; 2312 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2313 csum_flags = RL_TDESC_CMD_LGSEND | 2314 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2315 RL_TDESC_CMD_MSSVAL_SHIFT); 2316 else { 2317 /* 2318 * Unconditionally enable IP checksum if TCP or UDP 2319 * checksum is required. Otherwise, TCP/UDP checksum 2320 * does't make effects. 2321 */ 2322 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2323 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2324 csum_flags |= RL_TDESC_CMD_IPCSUM; 2325 if (((*m_head)->m_pkthdr.csum_flags & 2326 CSUM_TCP) != 0) 2327 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2328 if (((*m_head)->m_pkthdr.csum_flags & 2329 CSUM_UDP) != 0) 2330 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2331 } else { 2332 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2333 if (((*m_head)->m_pkthdr.csum_flags & 2334 CSUM_TCP) != 0) 2335 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2336 if (((*m_head)->m_pkthdr.csum_flags & 2337 CSUM_UDP) != 0) 2338 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2339 } 2340 } 2341 } 2342 2343 /* 2344 * Set up hardware VLAN tagging. Note: vlan tag info must 2345 * appear in all descriptors of a multi-descriptor 2346 * transmission attempt. 2347 */ 2348 if ((*m_head)->m_flags & M_VLANTAG) 2349 vlanctl |= htons((*m_head)->m_pkthdr.ether_vtag) | 2350 RL_TDESC_VLANCTL_TAG; 2351 2352 si = prod; 2353 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2354 desc = &sc->rl_ldata.rl_tx_list[prod]; 2355 desc->rl_vlanctl = htole32(vlanctl); 2356 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2357 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2358 cmdstat = segs[i].ds_len; 2359 if (i != 0) 2360 cmdstat |= RL_TDESC_CMD_OWN; 2361 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2362 cmdstat |= RL_TDESC_CMD_EOR; 2363 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2364 sc->rl_ldata.rl_tx_free--; 2365 } 2366 /* Update producer index. */ 2367 sc->rl_ldata.rl_tx_prodidx = prod; 2368 2369 /* Set EOF on the last descriptor. */ 2370 ei = RL_TX_DESC_PRV(sc, prod); 2371 desc = &sc->rl_ldata.rl_tx_list[ei]; 2372 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2373 2374 desc = &sc->rl_ldata.rl_tx_list[si]; 2375 /* Set SOF and transfer ownership of packet to the chip. */ 2376 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2377 2378 /* 2379 * Insure that the map for this transmission 2380 * is placed at the array index of the last descriptor 2381 * in this chain. (Swap last and first dmamaps.) 2382 */ 2383 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2384 map = txd->tx_dmamap; 2385 txd->tx_dmamap = txd_last->tx_dmamap; 2386 txd_last->tx_dmamap = map; 2387 txd_last->tx_m = *m_head; 2388 2389 return (0); 2390} 2391 2392static void 2393re_tx_task(arg, npending) 2394 void *arg; 2395 int npending; 2396{ 2397 struct ifnet *ifp; 2398 2399 ifp = arg; 2400 re_start(ifp); 2401 2402 return; 2403} 2404 2405/* 2406 * Main transmit routine for C+ and gigE NICs. 2407 */ 2408static void 2409re_start(ifp) 2410 struct ifnet *ifp; 2411{ 2412 struct rl_softc *sc; 2413 struct mbuf *m_head; 2414 int queued; 2415 2416 sc = ifp->if_softc; 2417 2418 RL_LOCK(sc); 2419 2420 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2421 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2422 RL_UNLOCK(sc); 2423 return; 2424 } 2425 2426 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2427 sc->rl_ldata.rl_tx_free > 1;) { 2428 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2429 if (m_head == NULL) 2430 break; 2431 2432 if (re_encap(sc, &m_head) != 0) { 2433 if (m_head == NULL) 2434 break; 2435 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2436 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2437 break; 2438 } 2439 2440 /* 2441 * If there's a BPF listener, bounce a copy of this frame 2442 * to him. 2443 */ 2444 ETHER_BPF_MTAP(ifp, m_head); 2445 2446 queued++; 2447 } 2448 2449 if (queued == 0) { 2450#ifdef RE_TX_MODERATION 2451 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2452 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2453#endif 2454 RL_UNLOCK(sc); 2455 return; 2456 } 2457 2458 /* Flush the TX descriptors */ 2459 2460 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2461 sc->rl_ldata.rl_tx_list_map, 2462 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2463 2464 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2465 2466#ifdef RE_TX_MODERATION 2467 /* 2468 * Use the countdown timer for interrupt moderation. 2469 * 'TX done' interrupts are disabled. Instead, we reset the 2470 * countdown timer, which will begin counting until it hits 2471 * the value in the TIMERINT register, and then trigger an 2472 * interrupt. Each time we write to the TIMERCNT register, 2473 * the timer count is reset to 0. 2474 */ 2475 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2476#endif 2477 2478 /* 2479 * Set a timeout in case the chip goes out to lunch. 2480 */ 2481 sc->rl_watchdog_timer = 5; 2482 2483 RL_UNLOCK(sc); 2484 2485 return; 2486} 2487 2488static void 2489re_init(xsc) 2490 void *xsc; 2491{ 2492 struct rl_softc *sc = xsc; 2493 2494 RL_LOCK(sc); 2495 re_init_locked(sc); 2496 RL_UNLOCK(sc); 2497} 2498 2499static void 2500re_init_locked(sc) 2501 struct rl_softc *sc; 2502{ 2503 struct ifnet *ifp = sc->rl_ifp; 2504 struct mii_data *mii; 2505 u_int32_t rxcfg = 0; 2506 uint16_t cfg; 2507 union { 2508 uint32_t align_dummy; 2509 u_char eaddr[ETHER_ADDR_LEN]; 2510 } eaddr; 2511 2512 RL_LOCK_ASSERT(sc); 2513 2514 mii = device_get_softc(sc->rl_miibus); 2515 2516 /* 2517 * Cancel pending I/O and free all RX/TX buffers. 2518 */ 2519 re_stop(sc); 2520 2521 /* 2522 * Enable C+ RX and TX mode, as well as VLAN stripping and 2523 * RX checksum offload. We must configure the C+ register 2524 * before all others. 2525 */ 2526 cfg = RL_CPLUSCMD_PCI_MRW; 2527 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2528 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2529 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2530 cfg |= RL_CPLUSCMD_VLANSTRIP; 2531 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2532 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2533 /* XXX magic. */ 2534 cfg |= 0x0001; 2535 } else 2536 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2537 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2538 2539 /* 2540 * Init our MAC address. Even though the chipset 2541 * documentation doesn't mention it, we need to enter "Config 2542 * register write enable" mode to modify the ID registers. 2543 */ 2544 /* Copy MAC address on stack to align. */ 2545 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2546 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2547 CSR_WRITE_4(sc, RL_IDR0, 2548 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2549 CSR_WRITE_4(sc, RL_IDR4, 2550 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2551 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2552 2553 /* 2554 * For C+ mode, initialize the RX descriptors and mbufs. 2555 */ 2556 re_rx_list_init(sc); 2557 re_tx_list_init(sc); 2558 2559 /* 2560 * Load the addresses of the RX and TX lists into the chip. 2561 */ 2562 2563 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2564 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2565 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2566 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2567 2568 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2569 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2570 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2571 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2572 2573 /* 2574 * Enable transmit and receive. 2575 */ 2576 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2577 2578 /* 2579 * Set the initial TX and RX configuration. 2580 */ 2581 if (sc->rl_testmode) { 2582 if (sc->rl_type == RL_8169) 2583 CSR_WRITE_4(sc, RL_TXCFG, 2584 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2585 else 2586 CSR_WRITE_4(sc, RL_TXCFG, 2587 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2588 } else 2589 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2590 2591 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2592 2593 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2594 2595 /* Set the individual bit to receive frames for this host only. */ 2596 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2597 rxcfg |= RL_RXCFG_RX_INDIV; 2598 2599 /* If we want promiscuous mode, set the allframes bit. */ 2600 if (ifp->if_flags & IFF_PROMISC) 2601 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2602 else 2603 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2604 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2605 2606 /* 2607 * Set capture broadcast bit to capture broadcast frames. 2608 */ 2609 if (ifp->if_flags & IFF_BROADCAST) 2610 rxcfg |= RL_RXCFG_RX_BROAD; 2611 else 2612 rxcfg &= ~RL_RXCFG_RX_BROAD; 2613 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2614 2615 /* 2616 * Program the multicast filter, if necessary. 2617 */ 2618 re_setmulti(sc); 2619 2620#ifdef DEVICE_POLLING 2621 /* 2622 * Disable interrupts if we are polling. 2623 */ 2624 if (ifp->if_capenable & IFCAP_POLLING) 2625 CSR_WRITE_2(sc, RL_IMR, 0); 2626 else /* otherwise ... */ 2627#endif 2628 2629 /* 2630 * Enable interrupts. 2631 */ 2632 if (sc->rl_testmode) 2633 CSR_WRITE_2(sc, RL_IMR, 0); 2634 else 2635 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2636 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2637 2638 /* Set initial TX threshold */ 2639 sc->rl_txthresh = RL_TX_THRESH_INIT; 2640 2641 /* Start RX/TX process. */ 2642 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2643#ifdef notdef 2644 /* Enable receiver and transmitter. */ 2645 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2646#endif 2647 2648#ifdef RE_TX_MODERATION 2649 /* 2650 * Initialize the timer interrupt register so that 2651 * a timer interrupt will be generated once the timer 2652 * reaches a certain number of ticks. The timer is 2653 * reloaded on each transmit. This gives us TX interrupt 2654 * moderation, which dramatically improves TX frame rate. 2655 */ 2656 if (sc->rl_type == RL_8169) 2657 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2658 else 2659 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2660#endif 2661 2662 /* 2663 * For 8169 gigE NICs, set the max allowed RX packet 2664 * size so we can receive jumbo frames. 2665 */ 2666 if (sc->rl_type == RL_8169) 2667 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2668 2669 if (sc->rl_testmode) 2670 return; 2671 2672 mii_mediachg(mii); 2673 2674 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2675 2676 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2677 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2678 2679 sc->rl_flags &= ~RL_FLAG_LINK; 2680 sc->rl_watchdog_timer = 0; 2681 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2682} 2683 2684/* 2685 * Set media options. 2686 */ 2687static int 2688re_ifmedia_upd(ifp) 2689 struct ifnet *ifp; 2690{ 2691 struct rl_softc *sc; 2692 struct mii_data *mii; 2693 2694 sc = ifp->if_softc; 2695 mii = device_get_softc(sc->rl_miibus); 2696 RL_LOCK(sc); 2697 mii_mediachg(mii); 2698 RL_UNLOCK(sc); 2699 2700 return (0); 2701} 2702 2703/* 2704 * Report current media status. 2705 */ 2706static void 2707re_ifmedia_sts(ifp, ifmr) 2708 struct ifnet *ifp; 2709 struct ifmediareq *ifmr; 2710{ 2711 struct rl_softc *sc; 2712 struct mii_data *mii; 2713 2714 sc = ifp->if_softc; 2715 mii = device_get_softc(sc->rl_miibus); 2716 2717 RL_LOCK(sc); 2718 mii_pollstat(mii); 2719 RL_UNLOCK(sc); 2720 ifmr->ifm_active = mii->mii_media_active; 2721 ifmr->ifm_status = mii->mii_media_status; 2722} 2723 2724static int 2725re_ioctl(ifp, command, data) 2726 struct ifnet *ifp; 2727 u_long command; 2728 caddr_t data; 2729{ 2730 struct rl_softc *sc = ifp->if_softc; 2731 struct ifreq *ifr = (struct ifreq *) data; 2732 struct mii_data *mii; 2733 int error = 0; 2734 2735 switch (command) { 2736 case SIOCSIFMTU: 2737 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2738 error = EINVAL; 2739 break; 2740 } 2741 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2742 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2743 error = EINVAL; 2744 break; 2745 } 2746 RL_LOCK(sc); 2747 if (ifp->if_mtu != ifr->ifr_mtu) 2748 ifp->if_mtu = ifr->ifr_mtu; 2749 RL_UNLOCK(sc); 2750 break; 2751 case SIOCSIFFLAGS: 2752 RL_LOCK(sc); 2753 if ((ifp->if_flags & IFF_UP) != 0) { 2754 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2755 if (((ifp->if_flags ^ sc->rl_if_flags) 2756 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2757 re_setmulti(sc); 2758 } else 2759 re_init_locked(sc); 2760 } else { 2761 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2762 re_stop(sc); 2763 } 2764 sc->rl_if_flags = ifp->if_flags; 2765 RL_UNLOCK(sc); 2766 break; 2767 case SIOCADDMULTI: 2768 case SIOCDELMULTI: 2769 RL_LOCK(sc); 2770 re_setmulti(sc); 2771 RL_UNLOCK(sc); 2772 break; 2773 case SIOCGIFMEDIA: 2774 case SIOCSIFMEDIA: 2775 mii = device_get_softc(sc->rl_miibus); 2776 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2777 break; 2778 case SIOCSIFCAP: 2779 { 2780 int mask, reinit; 2781 2782 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2783 reinit = 0; 2784#ifdef DEVICE_POLLING 2785 if (mask & IFCAP_POLLING) { 2786 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2787 error = ether_poll_register(re_poll, ifp); 2788 if (error) 2789 return(error); 2790 RL_LOCK(sc); 2791 /* Disable interrupts */ 2792 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2793 ifp->if_capenable |= IFCAP_POLLING; 2794 RL_UNLOCK(sc); 2795 } else { 2796 error = ether_poll_deregister(ifp); 2797 /* Enable interrupts. */ 2798 RL_LOCK(sc); 2799 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2800 ifp->if_capenable &= ~IFCAP_POLLING; 2801 RL_UNLOCK(sc); 2802 } 2803 } 2804#endif /* DEVICE_POLLING */ 2805 if (mask & IFCAP_HWCSUM) { 2806 ifp->if_capenable ^= IFCAP_HWCSUM; 2807 if (ifp->if_capenable & IFCAP_TXCSUM) 2808 ifp->if_hwassist |= RE_CSUM_FEATURES; 2809 else 2810 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2811 reinit = 1; 2812 } 2813 if (mask & IFCAP_VLAN_HWTAGGING) { 2814 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2815 reinit = 1; 2816 } 2817 if (mask & IFCAP_TSO4) { 2818 ifp->if_capenable ^= IFCAP_TSO4; 2819 if ((IFCAP_TSO4 & ifp->if_capenable) && 2820 (IFCAP_TSO4 & ifp->if_capabilities)) 2821 ifp->if_hwassist |= CSUM_TSO; 2822 else 2823 ifp->if_hwassist &= ~CSUM_TSO; 2824 } 2825 if ((mask & IFCAP_WOL) != 0 && 2826 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2827 if ((mask & IFCAP_WOL_UCAST) != 0) 2828 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2829 if ((mask & IFCAP_WOL_MCAST) != 0) 2830 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2831 if ((mask & IFCAP_WOL_MAGIC) != 0) 2832 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2833 } 2834 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2835 re_init(sc); 2836 VLAN_CAPABILITIES(ifp); 2837 } 2838 break; 2839 default: 2840 error = ether_ioctl(ifp, command, data); 2841 break; 2842 } 2843 2844 return (error); 2845} 2846 2847static void 2848re_watchdog(sc) 2849 struct rl_softc *sc; 2850{ 2851 2852 RL_LOCK_ASSERT(sc); 2853 2854 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2855 return; 2856 2857 device_printf(sc->rl_dev, "watchdog timeout\n"); 2858 sc->rl_ifp->if_oerrors++; 2859 2860 re_txeof(sc); 2861 re_rxeof(sc); 2862 re_init_locked(sc); 2863} 2864 2865/* 2866 * Stop the adapter and free any mbufs allocated to the 2867 * RX and TX lists. 2868 */ 2869static void 2870re_stop(sc) 2871 struct rl_softc *sc; 2872{ 2873 register int i; 2874 struct ifnet *ifp; 2875 struct rl_txdesc *txd; 2876 struct rl_rxdesc *rxd; 2877 2878 RL_LOCK_ASSERT(sc); 2879 2880 ifp = sc->rl_ifp; 2881 2882 sc->rl_watchdog_timer = 0; 2883 callout_stop(&sc->rl_stat_callout); 2884 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2885 2886 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2887 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2888 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2889 2890 if (sc->rl_head != NULL) { 2891 m_freem(sc->rl_head); 2892 sc->rl_head = sc->rl_tail = NULL; 2893 } 2894 2895 /* Free the TX list buffers. */ 2896 2897 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2898 txd = &sc->rl_ldata.rl_tx_desc[i]; 2899 if (txd->tx_m != NULL) { 2900 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2901 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2902 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2903 txd->tx_dmamap); 2904 m_freem(txd->tx_m); 2905 txd->tx_m = NULL; 2906 } 2907 } 2908 2909 /* Free the RX list buffers. */ 2910 2911 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2912 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2913 if (rxd->rx_m != NULL) { 2914 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2915 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2916 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2917 rxd->rx_dmamap); 2918 m_freem(rxd->rx_m); 2919 rxd->rx_m = NULL; 2920 } 2921 } 2922} 2923 2924/* 2925 * Device suspend routine. Stop the interface and save some PCI 2926 * settings in case the BIOS doesn't restore them properly on 2927 * resume. 2928 */ 2929static int 2930re_suspend(dev) 2931 device_t dev; 2932{ 2933 struct rl_softc *sc; 2934 2935 sc = device_get_softc(dev); 2936 2937 RL_LOCK(sc); 2938 re_stop(sc); 2939 re_setwol(sc); 2940 sc->suspended = 1; 2941 RL_UNLOCK(sc); 2942 2943 return (0); 2944} 2945 2946/* 2947 * Device resume routine. Restore some PCI settings in case the BIOS 2948 * doesn't, re-enable busmastering, and restart the interface if 2949 * appropriate. 2950 */ 2951static int 2952re_resume(dev) 2953 device_t dev; 2954{ 2955 struct rl_softc *sc; 2956 struct ifnet *ifp; 2957 2958 sc = device_get_softc(dev); 2959 2960 RL_LOCK(sc); 2961 2962 ifp = sc->rl_ifp; 2963 2964 /* reinitialize interface if necessary */ 2965 if (ifp->if_flags & IFF_UP) 2966 re_init_locked(sc); 2967 2968 /* 2969 * Clear WOL matching such that normal Rx filtering 2970 * wouldn't interfere with WOL patterns. 2971 */ 2972 re_clrwol(sc); 2973 sc->suspended = 0; 2974 RL_UNLOCK(sc); 2975 2976 return (0); 2977} 2978 2979/* 2980 * Stop all chip I/O so that the kernel's probe routines don't 2981 * get confused by errant DMAs when rebooting. 2982 */ 2983static int 2984re_shutdown(dev) 2985 device_t dev; 2986{ 2987 struct rl_softc *sc; 2988 2989 sc = device_get_softc(dev); 2990 2991 RL_LOCK(sc); 2992 re_stop(sc); 2993 /* 2994 * Mark interface as down since otherwise we will panic if 2995 * interrupt comes in later on, which can happen in some 2996 * cases. 2997 */ 2998 sc->rl_ifp->if_flags &= ~IFF_UP; 2999 re_setwol(sc); 3000 RL_UNLOCK(sc); 3001 3002 return (0); 3003} 3004 3005static void 3006re_setwol(sc) 3007 struct rl_softc *sc; 3008{ 3009 struct ifnet *ifp; 3010 int pmc; 3011 uint16_t pmstat; 3012 uint8_t v; 3013 3014 RL_LOCK_ASSERT(sc); 3015 3016 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3017 return; 3018 3019 ifp = sc->rl_ifp; 3020 /* Enable config register write. */ 3021 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3022 3023 /* Enable PME. */ 3024 v = CSR_READ_1(sc, RL_CFG1); 3025 v &= ~RL_CFG1_PME; 3026 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3027 v |= RL_CFG1_PME; 3028 CSR_WRITE_1(sc, RL_CFG1, v); 3029 3030 v = CSR_READ_1(sc, RL_CFG3); 3031 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3032 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3033 v |= RL_CFG3_WOL_MAGIC; 3034 CSR_WRITE_1(sc, RL_CFG3, v); 3035 3036 /* Config register write done. */ 3037 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3038 3039 v = CSR_READ_1(sc, RL_CFG5); 3040 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3041 v &= ~RL_CFG5_WOL_LANWAKE; 3042 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3043 v |= RL_CFG5_WOL_UCAST; 3044 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3045 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3046 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3047 v |= RL_CFG5_WOL_LANWAKE; 3048 CSR_WRITE_1(sc, RL_CFG5, v); 3049 3050 /* 3051 * It seems that hardware resets its link speed to 100Mbps in 3052 * power down mode so switching to 100Mbps in driver is not 3053 * needed. 3054 */ 3055 3056 /* Request PME if WOL is requested. */ 3057 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3058 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3059 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3060 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3061 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3062} 3063 3064static void 3065re_clrwol(sc) 3066 struct rl_softc *sc; 3067{ 3068 int pmc; 3069 uint8_t v; 3070 3071 RL_LOCK_ASSERT(sc); 3072 3073 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3074 return; 3075 3076 /* Enable config register write. */ 3077 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3078 3079 v = CSR_READ_1(sc, RL_CFG3); 3080 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3081 CSR_WRITE_1(sc, RL_CFG3, v); 3082 3083 /* Config register write done. */ 3084 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3085 3086 v = CSR_READ_1(sc, RL_CFG5); 3087 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3088 v &= ~RL_CFG5_WOL_LANWAKE; 3089 CSR_WRITE_1(sc, RL_CFG5, v); 3090} 3091