if_re.c revision 180176
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 180176 2008-07-02 07:54:53Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* Tunables. */ 159static int msi_disable = 1; 160TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164/* 165 * Various supported device vendors/types and their names. 166 */ 167static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8168C/8168CP/8111B/8111C/8111CP PCIe " 176 "Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8169, 0, 178 "RealTek 8169/8169S/8169SB/8110S/8110SB Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 182 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 183 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 184 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 185 { USR_VENDORID, USR_DEVICEID_997902, 0, 186 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 187}; 188 189static struct rl_hwrev re_hwrevs[] = { 190 { RL_HWREV_8139, RL_8139, "" }, 191 { RL_HWREV_8139A, RL_8139, "A" }, 192 { RL_HWREV_8139AG, RL_8139, "A-G" }, 193 { RL_HWREV_8139B, RL_8139, "B" }, 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 204 { RL_HWREV_8100, RL_8139, "8100"}, 205 { RL_HWREV_8101, RL_8139, "8101"}, 206 { RL_HWREV_8100E, RL_8169, "8100E"}, 207 { RL_HWREV_8101E, RL_8169, "8101E"}, 208 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 209 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 210 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 211 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 212 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 213 { 0, 0, NULL } 214}; 215 216static int re_probe (device_t); 217static int re_attach (device_t); 218static int re_detach (device_t); 219 220static int re_encap (struct rl_softc *, struct mbuf **); 221 222static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 223static int re_allocmem (device_t, struct rl_softc *); 224static __inline void re_discard_rxbuf 225 (struct rl_softc *, int); 226static int re_newbuf (struct rl_softc *, int); 227static int re_rx_list_init (struct rl_softc *); 228static int re_tx_list_init (struct rl_softc *); 229#ifdef RE_FIXUP_RX 230static __inline void re_fixup_rx 231 (struct mbuf *); 232#endif 233static int re_rxeof (struct rl_softc *); 234static void re_txeof (struct rl_softc *); 235#ifdef DEVICE_POLLING 236static void re_poll (struct ifnet *, enum poll_cmd, int); 237static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 238#endif 239static int re_intr (void *); 240static void re_tick (void *); 241static void re_tx_task (void *, int); 242static void re_int_task (void *, int); 243static void re_start (struct ifnet *); 244static int re_ioctl (struct ifnet *, u_long, caddr_t); 245static void re_init (void *); 246static void re_init_locked (struct rl_softc *); 247static void re_stop (struct rl_softc *); 248static void re_watchdog (struct rl_softc *); 249static int re_suspend (device_t); 250static int re_resume (device_t); 251static int re_shutdown (device_t); 252static int re_ifmedia_upd (struct ifnet *); 253static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 254 255static void re_eeprom_putbyte (struct rl_softc *, int); 256static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 257static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 258static int re_gmii_readreg (device_t, int, int); 259static int re_gmii_writereg (device_t, int, int, int); 260 261static int re_miibus_readreg (device_t, int, int); 262static int re_miibus_writereg (device_t, int, int, int); 263static void re_miibus_statchg (device_t); 264 265static void re_setmulti (struct rl_softc *); 266static void re_reset (struct rl_softc *); 267static void re_setwol (struct rl_softc *); 268static void re_clrwol (struct rl_softc *); 269 270#ifdef RE_DIAG 271static int re_diag (struct rl_softc *); 272#endif 273 274static device_method_t re_methods[] = { 275 /* Device interface */ 276 DEVMETHOD(device_probe, re_probe), 277 DEVMETHOD(device_attach, re_attach), 278 DEVMETHOD(device_detach, re_detach), 279 DEVMETHOD(device_suspend, re_suspend), 280 DEVMETHOD(device_resume, re_resume), 281 DEVMETHOD(device_shutdown, re_shutdown), 282 283 /* bus interface */ 284 DEVMETHOD(bus_print_child, bus_generic_print_child), 285 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 286 287 /* MII interface */ 288 DEVMETHOD(miibus_readreg, re_miibus_readreg), 289 DEVMETHOD(miibus_writereg, re_miibus_writereg), 290 DEVMETHOD(miibus_statchg, re_miibus_statchg), 291 292 { 0, 0 } 293}; 294 295static driver_t re_driver = { 296 "re", 297 re_methods, 298 sizeof(struct rl_softc) 299}; 300 301static devclass_t re_devclass; 302 303DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 304DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 305DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 306 307#define EE_SET(x) \ 308 CSR_WRITE_1(sc, RL_EECMD, \ 309 CSR_READ_1(sc, RL_EECMD) | x) 310 311#define EE_CLR(x) \ 312 CSR_WRITE_1(sc, RL_EECMD, \ 313 CSR_READ_1(sc, RL_EECMD) & ~x) 314 315/* 316 * Send a read command and address to the EEPROM, check for ACK. 317 */ 318static void 319re_eeprom_putbyte(sc, addr) 320 struct rl_softc *sc; 321 int addr; 322{ 323 register int d, i; 324 325 d = addr | (RL_9346_READ << sc->rl_eewidth); 326 327 /* 328 * Feed in each bit and strobe the clock. 329 */ 330 331 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 332 if (d & i) { 333 EE_SET(RL_EE_DATAIN); 334 } else { 335 EE_CLR(RL_EE_DATAIN); 336 } 337 DELAY(100); 338 EE_SET(RL_EE_CLK); 339 DELAY(150); 340 EE_CLR(RL_EE_CLK); 341 DELAY(100); 342 } 343 344 return; 345} 346 347/* 348 * Read a word of data stored in the EEPROM at address 'addr.' 349 */ 350static void 351re_eeprom_getword(sc, addr, dest) 352 struct rl_softc *sc; 353 int addr; 354 u_int16_t *dest; 355{ 356 register int i; 357 u_int16_t word = 0; 358 359 /* 360 * Send address of word we want to read. 361 */ 362 re_eeprom_putbyte(sc, addr); 363 364 /* 365 * Start reading bits from EEPROM. 366 */ 367 for (i = 0x8000; i; i >>= 1) { 368 EE_SET(RL_EE_CLK); 369 DELAY(100); 370 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 371 word |= i; 372 EE_CLR(RL_EE_CLK); 373 DELAY(100); 374 } 375 376 *dest = word; 377 378 return; 379} 380 381/* 382 * Read a sequence of words from the EEPROM. 383 */ 384static void 385re_read_eeprom(sc, dest, off, cnt) 386 struct rl_softc *sc; 387 caddr_t dest; 388 int off; 389 int cnt; 390{ 391 int i; 392 u_int16_t word = 0, *ptr; 393 394 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 395 396 DELAY(100); 397 398 for (i = 0; i < cnt; i++) { 399 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 400 re_eeprom_getword(sc, off + i, &word); 401 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 402 ptr = (u_int16_t *)(dest + (i * 2)); 403 *ptr = word; 404 } 405 406 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 407 408 return; 409} 410 411static int 412re_gmii_readreg(dev, phy, reg) 413 device_t dev; 414 int phy, reg; 415{ 416 struct rl_softc *sc; 417 u_int32_t rval; 418 int i; 419 420 if (phy != 1) 421 return (0); 422 423 sc = device_get_softc(dev); 424 425 /* Let the rgephy driver read the GMEDIASTAT register */ 426 427 if (reg == RL_GMEDIASTAT) { 428 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 429 return (rval); 430 } 431 432 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 433 DELAY(1000); 434 435 for (i = 0; i < RL_TIMEOUT; i++) { 436 rval = CSR_READ_4(sc, RL_PHYAR); 437 if (rval & RL_PHYAR_BUSY) 438 break; 439 DELAY(100); 440 } 441 442 if (i == RL_TIMEOUT) { 443 device_printf(sc->rl_dev, "PHY read failed\n"); 444 return (0); 445 } 446 447 return (rval & RL_PHYAR_PHYDATA); 448} 449 450static int 451re_gmii_writereg(dev, phy, reg, data) 452 device_t dev; 453 int phy, reg, data; 454{ 455 struct rl_softc *sc; 456 u_int32_t rval; 457 int i; 458 459 sc = device_get_softc(dev); 460 461 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 462 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 463 DELAY(1000); 464 465 for (i = 0; i < RL_TIMEOUT; i++) { 466 rval = CSR_READ_4(sc, RL_PHYAR); 467 if (!(rval & RL_PHYAR_BUSY)) 468 break; 469 DELAY(100); 470 } 471 472 if (i == RL_TIMEOUT) { 473 device_printf(sc->rl_dev, "PHY write failed\n"); 474 return (0); 475 } 476 477 return (0); 478} 479 480static int 481re_miibus_readreg(dev, phy, reg) 482 device_t dev; 483 int phy, reg; 484{ 485 struct rl_softc *sc; 486 u_int16_t rval = 0; 487 u_int16_t re8139_reg = 0; 488 489 sc = device_get_softc(dev); 490 491 if (sc->rl_type == RL_8169) { 492 rval = re_gmii_readreg(dev, phy, reg); 493 return (rval); 494 } 495 496 /* Pretend the internal PHY is only at address 0 */ 497 if (phy) { 498 return (0); 499 } 500 switch (reg) { 501 case MII_BMCR: 502 re8139_reg = RL_BMCR; 503 break; 504 case MII_BMSR: 505 re8139_reg = RL_BMSR; 506 break; 507 case MII_ANAR: 508 re8139_reg = RL_ANAR; 509 break; 510 case MII_ANER: 511 re8139_reg = RL_ANER; 512 break; 513 case MII_ANLPAR: 514 re8139_reg = RL_LPAR; 515 break; 516 case MII_PHYIDR1: 517 case MII_PHYIDR2: 518 return (0); 519 /* 520 * Allow the rlphy driver to read the media status 521 * register. If we have a link partner which does not 522 * support NWAY, this is the register which will tell 523 * us the results of parallel detection. 524 */ 525 case RL_MEDIASTAT: 526 rval = CSR_READ_1(sc, RL_MEDIASTAT); 527 return (rval); 528 default: 529 device_printf(sc->rl_dev, "bad phy register\n"); 530 return (0); 531 } 532 rval = CSR_READ_2(sc, re8139_reg); 533 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 534 /* 8139C+ has different bit layout. */ 535 rval &= ~(BMCR_LOOP | BMCR_ISO); 536 } 537 return (rval); 538} 539 540static int 541re_miibus_writereg(dev, phy, reg, data) 542 device_t dev; 543 int phy, reg, data; 544{ 545 struct rl_softc *sc; 546 u_int16_t re8139_reg = 0; 547 int rval = 0; 548 549 sc = device_get_softc(dev); 550 551 if (sc->rl_type == RL_8169) { 552 rval = re_gmii_writereg(dev, phy, reg, data); 553 return (rval); 554 } 555 556 /* Pretend the internal PHY is only at address 0 */ 557 if (phy) 558 return (0); 559 560 switch (reg) { 561 case MII_BMCR: 562 re8139_reg = RL_BMCR; 563 if (sc->rl_type == RL_8139CPLUS) { 564 /* 8139C+ has different bit layout. */ 565 data &= ~(BMCR_LOOP | BMCR_ISO); 566 } 567 break; 568 case MII_BMSR: 569 re8139_reg = RL_BMSR; 570 break; 571 case MII_ANAR: 572 re8139_reg = RL_ANAR; 573 break; 574 case MII_ANER: 575 re8139_reg = RL_ANER; 576 break; 577 case MII_ANLPAR: 578 re8139_reg = RL_LPAR; 579 break; 580 case MII_PHYIDR1: 581 case MII_PHYIDR2: 582 return (0); 583 break; 584 default: 585 device_printf(sc->rl_dev, "bad phy register\n"); 586 return (0); 587 } 588 CSR_WRITE_2(sc, re8139_reg, data); 589 return (0); 590} 591 592static void 593re_miibus_statchg(dev) 594 device_t dev; 595{ 596 597} 598 599/* 600 * Program the 64-bit multicast hash filter. 601 */ 602static void 603re_setmulti(sc) 604 struct rl_softc *sc; 605{ 606 struct ifnet *ifp; 607 int h = 0; 608 u_int32_t hashes[2] = { 0, 0 }; 609 struct ifmultiaddr *ifma; 610 u_int32_t rxfilt; 611 int mcnt = 0; 612 613 RL_LOCK_ASSERT(sc); 614 615 ifp = sc->rl_ifp; 616 617 618 rxfilt = CSR_READ_4(sc, RL_RXCFG); 619 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 620 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 621 if (ifp->if_flags & IFF_PROMISC) 622 rxfilt |= RL_RXCFG_RX_ALLPHYS; 623 /* 624 * Unlike other hardwares, we have to explicitly set 625 * RL_RXCFG_RX_MULTI to receive multicast frames in 626 * promiscuous mode. 627 */ 628 rxfilt |= RL_RXCFG_RX_MULTI; 629 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 630 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 631 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 632 return; 633 } 634 635 /* first, zot all the existing hash bits */ 636 CSR_WRITE_4(sc, RL_MAR0, 0); 637 CSR_WRITE_4(sc, RL_MAR4, 0); 638 639 /* now program new ones */ 640 IF_ADDR_LOCK(ifp); 641 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 642 if (ifma->ifma_addr->sa_family != AF_LINK) 643 continue; 644 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 645 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 646 if (h < 32) 647 hashes[0] |= (1 << h); 648 else 649 hashes[1] |= (1 << (h - 32)); 650 mcnt++; 651 } 652 IF_ADDR_UNLOCK(ifp); 653 654 if (mcnt) 655 rxfilt |= RL_RXCFG_RX_MULTI; 656 else 657 rxfilt &= ~RL_RXCFG_RX_MULTI; 658 659 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 660 661 /* 662 * For some unfathomable reason, RealTek decided to reverse 663 * the order of the multicast hash registers in the PCI Express 664 * parts. This means we have to write the hash pattern in reverse 665 * order for those devices. 666 */ 667 668 if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) { 669 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 670 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 671 } else { 672 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 673 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 674 } 675} 676 677static void 678re_reset(sc) 679 struct rl_softc *sc; 680{ 681 register int i; 682 683 RL_LOCK_ASSERT(sc); 684 685 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 686 687 for (i = 0; i < RL_TIMEOUT; i++) { 688 DELAY(10); 689 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 690 break; 691 } 692 if (i == RL_TIMEOUT) 693 device_printf(sc->rl_dev, "reset never completed!\n"); 694 695 CSR_WRITE_1(sc, 0x82, 1); 696} 697 698#ifdef RE_DIAG 699 700/* 701 * The following routine is designed to test for a defect on some 702 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 703 * lines connected to the bus, however for a 32-bit only card, they 704 * should be pulled high. The result of this defect is that the 705 * NIC will not work right if you plug it into a 64-bit slot: DMA 706 * operations will be done with 64-bit transfers, which will fail 707 * because the 64-bit data lines aren't connected. 708 * 709 * There's no way to work around this (short of talking a soldering 710 * iron to the board), however we can detect it. The method we use 711 * here is to put the NIC into digital loopback mode, set the receiver 712 * to promiscuous mode, and then try to send a frame. We then compare 713 * the frame data we sent to what was received. If the data matches, 714 * then the NIC is working correctly, otherwise we know the user has 715 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 716 * slot. In the latter case, there's no way the NIC can work correctly, 717 * so we print out a message on the console and abort the device attach. 718 */ 719 720static int 721re_diag(sc) 722 struct rl_softc *sc; 723{ 724 struct ifnet *ifp = sc->rl_ifp; 725 struct mbuf *m0; 726 struct ether_header *eh; 727 struct rl_desc *cur_rx; 728 u_int16_t status; 729 u_int32_t rxstat; 730 int total_len, i, error = 0, phyaddr; 731 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 732 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 733 734 /* Allocate a single mbuf */ 735 MGETHDR(m0, M_DONTWAIT, MT_DATA); 736 if (m0 == NULL) 737 return (ENOBUFS); 738 739 RL_LOCK(sc); 740 741 /* 742 * Initialize the NIC in test mode. This sets the chip up 743 * so that it can send and receive frames, but performs the 744 * following special functions: 745 * - Puts receiver in promiscuous mode 746 * - Enables digital loopback mode 747 * - Leaves interrupts turned off 748 */ 749 750 ifp->if_flags |= IFF_PROMISC; 751 sc->rl_testmode = 1; 752 re_reset(sc); 753 re_init_locked(sc); 754 sc->rl_flags |= RL_FLAG_LINK; 755 if (sc->rl_type == RL_8169) 756 phyaddr = 1; 757 else 758 phyaddr = 0; 759 760 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 761 for (i = 0; i < RL_TIMEOUT; i++) { 762 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 763 if (!(status & BMCR_RESET)) 764 break; 765 } 766 767 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 768 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 769 770 DELAY(100000); 771 772 /* Put some data in the mbuf */ 773 774 eh = mtod(m0, struct ether_header *); 775 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 776 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 777 eh->ether_type = htons(ETHERTYPE_IP); 778 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 779 780 /* 781 * Queue the packet, start transmission. 782 * Note: IF_HANDOFF() ultimately calls re_start() for us. 783 */ 784 785 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 786 RL_UNLOCK(sc); 787 /* XXX: re_diag must not be called when in ALTQ mode */ 788 IF_HANDOFF(&ifp->if_snd, m0, ifp); 789 RL_LOCK(sc); 790 m0 = NULL; 791 792 /* Wait for it to propagate through the chip */ 793 794 DELAY(100000); 795 for (i = 0; i < RL_TIMEOUT; i++) { 796 status = CSR_READ_2(sc, RL_ISR); 797 CSR_WRITE_2(sc, RL_ISR, status); 798 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 799 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 800 break; 801 DELAY(10); 802 } 803 804 if (i == RL_TIMEOUT) { 805 device_printf(sc->rl_dev, 806 "diagnostic failed, failed to receive packet in" 807 " loopback mode\n"); 808 error = EIO; 809 goto done; 810 } 811 812 /* 813 * The packet should have been dumped into the first 814 * entry in the RX DMA ring. Grab it from there. 815 */ 816 817 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 818 sc->rl_ldata.rl_rx_list_map, 819 BUS_DMASYNC_POSTREAD); 820 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 821 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 822 BUS_DMASYNC_POSTREAD); 823 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 824 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 825 826 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 827 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 828 eh = mtod(m0, struct ether_header *); 829 830 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 831 total_len = RL_RXBYTES(cur_rx); 832 rxstat = le32toh(cur_rx->rl_cmdstat); 833 834 if (total_len != ETHER_MIN_LEN) { 835 device_printf(sc->rl_dev, 836 "diagnostic failed, received short packet\n"); 837 error = EIO; 838 goto done; 839 } 840 841 /* Test that the received packet data matches what we sent. */ 842 843 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 844 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 845 ntohs(eh->ether_type) != ETHERTYPE_IP) { 846 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 847 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 848 dst, ":", src, ":", ETHERTYPE_IP); 849 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 850 eh->ether_dhost, ":", eh->ether_shost, ":", 851 ntohs(eh->ether_type)); 852 device_printf(sc->rl_dev, "You may have a defective 32-bit " 853 "NIC plugged into a 64-bit PCI slot.\n"); 854 device_printf(sc->rl_dev, "Please re-install the NIC in a " 855 "32-bit slot for proper operation.\n"); 856 device_printf(sc->rl_dev, "Read the re(4) man page for more " 857 "details.\n"); 858 error = EIO; 859 } 860 861done: 862 /* Turn interface off, release resources */ 863 864 sc->rl_testmode = 0; 865 sc->rl_flags &= ~RL_FLAG_LINK; 866 ifp->if_flags &= ~IFF_PROMISC; 867 re_stop(sc); 868 if (m0 != NULL) 869 m_freem(m0); 870 871 RL_UNLOCK(sc); 872 873 return (error); 874} 875 876#endif 877 878/* 879 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 880 * IDs against our list and return a device name if we find a match. 881 */ 882static int 883re_probe(dev) 884 device_t dev; 885{ 886 struct rl_type *t; 887 uint16_t devid, vendor; 888 uint16_t revid, sdevid; 889 int i; 890 891 vendor = pci_get_vendor(dev); 892 devid = pci_get_device(dev); 893 revid = pci_get_revid(dev); 894 sdevid = pci_get_subdevice(dev); 895 896 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 897 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 898 /* 899 * Only attach to rev. 3 of the Linksys EG1032 adapter. 900 * Rev. 2 is supported by sk(4). 901 */ 902 return (ENXIO); 903 } 904 } 905 906 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 907 if (revid != 0x20) { 908 /* 8139, let rl(4) take care of this device. */ 909 return (ENXIO); 910 } 911 } 912 913 t = re_devs; 914 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 915 if (vendor == t->rl_vid && devid == t->rl_did) { 916 device_set_desc(dev, t->rl_name); 917 return (BUS_PROBE_DEFAULT); 918 } 919 } 920 921 return (ENXIO); 922} 923 924/* 925 * Map a single buffer address. 926 */ 927 928static void 929re_dma_map_addr(arg, segs, nseg, error) 930 void *arg; 931 bus_dma_segment_t *segs; 932 int nseg; 933 int error; 934{ 935 bus_addr_t *addr; 936 937 if (error) 938 return; 939 940 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 941 addr = arg; 942 *addr = segs->ds_addr; 943} 944 945static int 946re_allocmem(dev, sc) 947 device_t dev; 948 struct rl_softc *sc; 949{ 950 bus_size_t rx_list_size, tx_list_size; 951 int error; 952 int i; 953 954 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 955 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 956 957 /* 958 * Allocate the parent bus DMA tag appropriate for PCI. 959 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 960 * register should be set. However some RealTek chips are known 961 * to be buggy on DAC handling, therefore disable DAC by limiting 962 * DMA address space to 32bit. PCIe variants of RealTek chips 963 * may not have the limitation but I took safer path. 964 */ 965 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 966 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 967 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 968 NULL, NULL, &sc->rl_parent_tag); 969 if (error) { 970 device_printf(dev, "could not allocate parent DMA tag\n"); 971 return (error); 972 } 973 974 /* 975 * Allocate map for TX mbufs. 976 */ 977 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 978 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 979 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 980 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 981 if (error) { 982 device_printf(dev, "could not allocate TX DMA tag\n"); 983 return (error); 984 } 985 986 /* 987 * Allocate map for RX mbufs. 988 */ 989 990 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 991 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 992 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 993 if (error) { 994 device_printf(dev, "could not allocate RX DMA tag\n"); 995 return (error); 996 } 997 998 /* 999 * Allocate map for TX descriptor list. 1000 */ 1001 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1002 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1003 NULL, tx_list_size, 1, tx_list_size, 0, 1004 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1005 if (error) { 1006 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1007 return (error); 1008 } 1009 1010 /* Allocate DMA'able memory for the TX ring */ 1011 1012 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1013 (void **)&sc->rl_ldata.rl_tx_list, 1014 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1015 &sc->rl_ldata.rl_tx_list_map); 1016 if (error) { 1017 device_printf(dev, "could not allocate TX DMA ring\n"); 1018 return (error); 1019 } 1020 1021 /* Load the map for the TX ring. */ 1022 1023 sc->rl_ldata.rl_tx_list_addr = 0; 1024 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1025 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1026 tx_list_size, re_dma_map_addr, 1027 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1028 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1029 device_printf(dev, "could not load TX DMA ring\n"); 1030 return (ENOMEM); 1031 } 1032 1033 /* Create DMA maps for TX buffers */ 1034 1035 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1036 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1037 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1038 if (error) { 1039 device_printf(dev, "could not create DMA map for TX\n"); 1040 return (error); 1041 } 1042 } 1043 1044 /* 1045 * Allocate map for RX descriptor list. 1046 */ 1047 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1048 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1049 NULL, rx_list_size, 1, rx_list_size, 0, 1050 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1051 if (error) { 1052 device_printf(dev, "could not create RX DMA ring tag\n"); 1053 return (error); 1054 } 1055 1056 /* Allocate DMA'able memory for the RX ring */ 1057 1058 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1059 (void **)&sc->rl_ldata.rl_rx_list, 1060 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1061 &sc->rl_ldata.rl_rx_list_map); 1062 if (error) { 1063 device_printf(dev, "could not allocate RX DMA ring\n"); 1064 return (error); 1065 } 1066 1067 /* Load the map for the RX ring. */ 1068 1069 sc->rl_ldata.rl_rx_list_addr = 0; 1070 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1071 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1072 rx_list_size, re_dma_map_addr, 1073 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1074 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1075 device_printf(dev, "could not load RX DMA ring\n"); 1076 return (ENOMEM); 1077 } 1078 1079 /* Create DMA maps for RX buffers */ 1080 1081 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1082 &sc->rl_ldata.rl_rx_sparemap); 1083 if (error) { 1084 device_printf(dev, "could not create spare DMA map for RX\n"); 1085 return (error); 1086 } 1087 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1088 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1089 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1090 if (error) { 1091 device_printf(dev, "could not create DMA map for RX\n"); 1092 return (error); 1093 } 1094 } 1095 1096 return (0); 1097} 1098 1099/* 1100 * Attach the interface. Allocate softc structures, do ifmedia 1101 * setup and ethernet/BPF attach. 1102 */ 1103static int 1104re_attach(dev) 1105 device_t dev; 1106{ 1107 u_char eaddr[ETHER_ADDR_LEN]; 1108 u_int16_t as[ETHER_ADDR_LEN / 2]; 1109 struct rl_softc *sc; 1110 struct ifnet *ifp; 1111 struct rl_hwrev *hw_rev; 1112 int hwrev; 1113 u_int16_t devid, re_did = 0; 1114 int error = 0, rid, i; 1115 int msic, reg; 1116 uint8_t cfg; 1117 1118 sc = device_get_softc(dev); 1119 sc->rl_dev = dev; 1120 1121 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1122 MTX_DEF); 1123 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1124 1125 /* 1126 * Map control/status registers. 1127 */ 1128 pci_enable_busmaster(dev); 1129 1130 devid = pci_get_device(dev); 1131 /* Prefer memory space register mapping over IO space. */ 1132 sc->rl_res_id = PCIR_BAR(1); 1133 sc->rl_res_type = SYS_RES_MEMORY; 1134 /* RTL8168/8101E seems to use different BARs. */ 1135 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1136 sc->rl_res_id = PCIR_BAR(2); 1137 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1138 &sc->rl_res_id, RF_ACTIVE); 1139 1140 if (sc->rl_res == NULL) { 1141 sc->rl_res_id = PCIR_BAR(0); 1142 sc->rl_res_type = SYS_RES_IOPORT; 1143 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1144 &sc->rl_res_id, RF_ACTIVE); 1145 if (sc->rl_res == NULL) { 1146 device_printf(dev, "couldn't map ports/memory\n"); 1147 error = ENXIO; 1148 goto fail; 1149 } 1150 } 1151 1152 sc->rl_btag = rman_get_bustag(sc->rl_res); 1153 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1154 1155 msic = 0; 1156 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1157 msic = pci_msi_count(dev); 1158 if (bootverbose) 1159 device_printf(dev, "MSI count : %d\n", msic); 1160 } 1161 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1162 if (pci_alloc_msi(dev, &msic) == 0) { 1163 if (msic == RL_MSI_MESSAGES) { 1164 device_printf(dev, "Using %d MSI messages\n", 1165 msic); 1166 sc->rl_flags |= RL_FLAG_MSI; 1167 /* Explicitly set MSI enable bit. */ 1168 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1169 cfg = CSR_READ_1(sc, RL_CFG2); 1170 cfg |= RL_CFG2_MSI; 1171 CSR_WRITE_1(sc, RL_CFG2, cfg); 1172 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1173 } else 1174 pci_release_msi(dev); 1175 } 1176 } 1177 1178 /* Allocate interrupt */ 1179 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1180 rid = 0; 1181 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1182 RF_SHAREABLE | RF_ACTIVE); 1183 if (sc->rl_irq[0] == NULL) { 1184 device_printf(dev, "couldn't allocate IRQ resources\n"); 1185 error = ENXIO; 1186 goto fail; 1187 } 1188 } else { 1189 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1190 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1191 SYS_RES_IRQ, &rid, RF_ACTIVE); 1192 if (sc->rl_irq[i] == NULL) { 1193 device_printf(dev, 1194 "couldn't llocate IRQ resources for " 1195 "message %d\n", rid); 1196 error = ENXIO; 1197 goto fail; 1198 } 1199 } 1200 } 1201 1202 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1203 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1204 cfg = CSR_READ_1(sc, RL_CFG2); 1205 if ((cfg & RL_CFG2_MSI) != 0) { 1206 device_printf(dev, "turning off MSI enable bit.\n"); 1207 cfg &= ~RL_CFG2_MSI; 1208 CSR_WRITE_1(sc, RL_CFG2, cfg); 1209 } 1210 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1211 } 1212 1213 /* Reset the adapter. */ 1214 RL_LOCK(sc); 1215 re_reset(sc); 1216 RL_UNLOCK(sc); 1217 1218 hw_rev = re_hwrevs; 1219 hwrev = CSR_READ_4(sc, RL_TXCFG); 1220 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1221 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1222 hwrev &= RL_TXCFG_HWREV; 1223 while (hw_rev->rl_desc != NULL) { 1224 if (hw_rev->rl_rev == hwrev) { 1225 sc->rl_type = hw_rev->rl_type; 1226 break; 1227 } 1228 hw_rev++; 1229 } 1230 if (hw_rev->rl_desc == NULL) { 1231 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1232 error = ENXIO; 1233 goto fail; 1234 } 1235 1236 switch (hw_rev->rl_rev) { 1237 case RL_HWREV_8139CPLUS: 1238 sc->rl_flags |= RL_FLAG_NOJUMBO; 1239 break; 1240 case RL_HWREV_8100E: 1241 case RL_HWREV_8101E: 1242 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE; 1243 break; 1244 case RL_HWREV_8168_SPIN1: 1245 case RL_HWREV_8168_SPIN2: 1246 case RL_HWREV_8168_SPIN3: 1247 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1248 RL_FLAG_MACSTAT; 1249 break; 1250 case RL_HWREV_8168C: 1251 case RL_HWREV_8168C_SPIN2: 1252 case RL_HWREV_8168CP: 1253 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1254 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; 1255 /* 1256 * These controllers support jumbo frame but it seems 1257 * that enabling it requires touching additional magic 1258 * registers. Depending on MAC revisions some 1259 * controllers need to disable checksum offload. So 1260 * disable jumbo frame until I have better idea what 1261 * it really requires to make it support. 1262 * RTL8168C/CP : supports up to 6KB jumbo frame. 1263 * RTL8111C/CP : supports up to 9KB jumbo frame. 1264 */ 1265 sc->rl_flags |= RL_FLAG_NOJUMBO; 1266 break; 1267 case RL_HWREV_8169_8110SB: 1268 case RL_HWREV_8169_8110SC: 1269 sc->rl_flags |= RL_FLAG_PHYWAKE; 1270 break; 1271 default: 1272 break; 1273 } 1274 1275 /* Enable PME. */ 1276 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1277 cfg = CSR_READ_1(sc, RL_CFG1); 1278 cfg |= RL_CFG1_PME; 1279 CSR_WRITE_1(sc, RL_CFG1, cfg); 1280 cfg = CSR_READ_1(sc, RL_CFG5); 1281 cfg &= RL_CFG5_PME_STS; 1282 CSR_WRITE_1(sc, RL_CFG5, cfg); 1283 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1284 1285 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1286 /* 1287 * XXX Should have a better way to extract station 1288 * address from EEPROM. 1289 */ 1290 for (i = 0; i < ETHER_ADDR_LEN; i++) 1291 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1292 } else { 1293 sc->rl_eewidth = RL_9356_ADDR_LEN; 1294 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1295 if (re_did != 0x8129) 1296 sc->rl_eewidth = RL_9346_ADDR_LEN; 1297 1298 /* 1299 * Get station address from the EEPROM. 1300 */ 1301 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1302 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1303 as[i] = le16toh(as[i]); 1304 bcopy(as, eaddr, sizeof(eaddr)); 1305 } 1306 1307 if (sc->rl_type == RL_8169) { 1308 /* Set RX length mask and number of descriptors. */ 1309 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1310 sc->rl_txstart = RL_GTXSTART; 1311 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1312 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1313 } else { 1314 /* Set RX length mask and number of descriptors. */ 1315 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1316 sc->rl_txstart = RL_TXSTART; 1317 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1318 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1319 } 1320 1321 error = re_allocmem(dev, sc); 1322 if (error) 1323 goto fail; 1324 1325 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1326 if (ifp == NULL) { 1327 device_printf(dev, "can not if_alloc()\n"); 1328 error = ENOSPC; 1329 goto fail; 1330 } 1331 1332 /* Take PHY out of power down mode. */ 1333 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1334 re_gmii_writereg(dev, 1, 0x1f, 0); 1335 re_gmii_writereg(dev, 1, 0x0e, 0); 1336 } 1337 1338 /* Do MII setup */ 1339 if (mii_phy_probe(dev, &sc->rl_miibus, 1340 re_ifmedia_upd, re_ifmedia_sts)) { 1341 device_printf(dev, "MII without any phy!\n"); 1342 error = ENXIO; 1343 goto fail; 1344 } 1345 1346 ifp->if_softc = sc; 1347 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1348 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1349 ifp->if_ioctl = re_ioctl; 1350 ifp->if_start = re_start; 1351 ifp->if_hwassist = RE_CSUM_FEATURES; 1352 ifp->if_capabilities = IFCAP_HWCSUM; 1353 ifp->if_capenable = ifp->if_capabilities; 1354 ifp->if_init = re_init; 1355 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1356 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1357 IFQ_SET_READY(&ifp->if_snd); 1358 1359 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1360 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1361 1362 /* 1363 * XXX 1364 * Still have no idea how to make TSO work on 8168C, 8168CP, 1365 * 8111C and 8111CP. 1366 */ 1367 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1368 ifp->if_hwassist |= CSUM_TSO; 1369 ifp->if_capabilities |= IFCAP_TSO4; 1370 } 1371 1372 /* 1373 * Call MI attach routine. 1374 */ 1375 ether_ifattach(ifp, eaddr); 1376 1377 /* VLAN capability setup */ 1378 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1379 if (ifp->if_capabilities & IFCAP_HWCSUM) 1380 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1381 /* Enable WOL if PM is supported. */ 1382 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1383 ifp->if_capabilities |= IFCAP_WOL; 1384 ifp->if_capenable = ifp->if_capabilities; 1385#ifdef DEVICE_POLLING 1386 ifp->if_capabilities |= IFCAP_POLLING; 1387#endif 1388 /* 1389 * Tell the upper layer(s) we support long frames. 1390 * Must appear after the call to ether_ifattach() because 1391 * ether_ifattach() sets ifi_hdrlen to the default value. 1392 */ 1393 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1394 1395#ifdef RE_DIAG 1396 /* 1397 * Perform hardware diagnostic on the original RTL8169. 1398 * Some 32-bit cards were incorrectly wired and would 1399 * malfunction if plugged into a 64-bit slot. 1400 */ 1401 1402 if (hwrev == RL_HWREV_8169) { 1403 error = re_diag(sc); 1404 if (error) { 1405 device_printf(dev, 1406 "attach aborted due to hardware diag failure\n"); 1407 ether_ifdetach(ifp); 1408 goto fail; 1409 } 1410 } 1411#endif 1412 1413 /* Hook interrupt last to avoid having to lock softc */ 1414 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1415 error = bus_setup_intr(dev, sc->rl_irq[0], 1416 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1417 &sc->rl_intrhand[0]); 1418 else { 1419 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1420 error = bus_setup_intr(dev, sc->rl_irq[i], 1421 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1422 &sc->rl_intrhand[i]); 1423 if (error != 0) 1424 break; 1425 } 1426 } 1427 if (error) { 1428 device_printf(dev, "couldn't set up irq\n"); 1429 ether_ifdetach(ifp); 1430 } 1431 1432fail: 1433 1434 if (error) 1435 re_detach(dev); 1436 1437 return (error); 1438} 1439 1440/* 1441 * Shutdown hardware and free up resources. This can be called any 1442 * time after the mutex has been initialized. It is called in both 1443 * the error case in attach and the normal detach case so it needs 1444 * to be careful about only freeing resources that have actually been 1445 * allocated. 1446 */ 1447static int 1448re_detach(dev) 1449 device_t dev; 1450{ 1451 struct rl_softc *sc; 1452 struct ifnet *ifp; 1453 int i, rid; 1454 1455 sc = device_get_softc(dev); 1456 ifp = sc->rl_ifp; 1457 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1458 1459 /* These should only be active if attach succeeded */ 1460 if (device_is_attached(dev)) { 1461#ifdef DEVICE_POLLING 1462 if (ifp->if_capenable & IFCAP_POLLING) 1463 ether_poll_deregister(ifp); 1464#endif 1465 RL_LOCK(sc); 1466#if 0 1467 sc->suspended = 1; 1468#endif 1469 re_stop(sc); 1470 RL_UNLOCK(sc); 1471 callout_drain(&sc->rl_stat_callout); 1472 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1473 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1474 /* 1475 * Force off the IFF_UP flag here, in case someone 1476 * still had a BPF descriptor attached to this 1477 * interface. If they do, ether_ifdetach() will cause 1478 * the BPF code to try and clear the promisc mode 1479 * flag, which will bubble down to re_ioctl(), 1480 * which will try to call re_init() again. This will 1481 * turn the NIC back on and restart the MII ticker, 1482 * which will panic the system when the kernel tries 1483 * to invoke the re_tick() function that isn't there 1484 * anymore. 1485 */ 1486 ifp->if_flags &= ~IFF_UP; 1487 ether_ifdetach(ifp); 1488 } 1489 if (sc->rl_miibus) 1490 device_delete_child(dev, sc->rl_miibus); 1491 bus_generic_detach(dev); 1492 1493 /* 1494 * The rest is resource deallocation, so we should already be 1495 * stopped here. 1496 */ 1497 1498 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1499 if (sc->rl_intrhand[i] != NULL) { 1500 bus_teardown_intr(dev, sc->rl_irq[i], 1501 sc->rl_intrhand[i]); 1502 sc->rl_intrhand[i] = NULL; 1503 } 1504 } 1505 if (ifp != NULL) 1506 if_free(ifp); 1507 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1508 if (sc->rl_irq[0] != NULL) { 1509 bus_release_resource(dev, SYS_RES_IRQ, 0, 1510 sc->rl_irq[0]); 1511 sc->rl_irq[0] = NULL; 1512 } 1513 } else { 1514 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1515 if (sc->rl_irq[i] != NULL) { 1516 bus_release_resource(dev, SYS_RES_IRQ, rid, 1517 sc->rl_irq[i]); 1518 sc->rl_irq[i] = NULL; 1519 } 1520 } 1521 pci_release_msi(dev); 1522 } 1523 if (sc->rl_res) 1524 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1525 sc->rl_res); 1526 1527 /* Unload and free the RX DMA ring memory and map */ 1528 1529 if (sc->rl_ldata.rl_rx_list_tag) { 1530 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1531 sc->rl_ldata.rl_rx_list_map); 1532 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1533 sc->rl_ldata.rl_rx_list, 1534 sc->rl_ldata.rl_rx_list_map); 1535 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1536 } 1537 1538 /* Unload and free the TX DMA ring memory and map */ 1539 1540 if (sc->rl_ldata.rl_tx_list_tag) { 1541 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1542 sc->rl_ldata.rl_tx_list_map); 1543 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1544 sc->rl_ldata.rl_tx_list, 1545 sc->rl_ldata.rl_tx_list_map); 1546 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1547 } 1548 1549 /* Destroy all the RX and TX buffer maps */ 1550 1551 if (sc->rl_ldata.rl_tx_mtag) { 1552 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1553 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1554 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1555 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1556 } 1557 if (sc->rl_ldata.rl_rx_mtag) { 1558 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1559 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1560 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1561 if (sc->rl_ldata.rl_rx_sparemap) 1562 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1563 sc->rl_ldata.rl_rx_sparemap); 1564 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1565 } 1566 1567 /* Unload and free the stats buffer and map */ 1568 1569 if (sc->rl_ldata.rl_stag) { 1570 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1571 sc->rl_ldata.rl_rx_list_map); 1572 bus_dmamem_free(sc->rl_ldata.rl_stag, 1573 sc->rl_ldata.rl_stats, 1574 sc->rl_ldata.rl_smap); 1575 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1576 } 1577 1578 if (sc->rl_parent_tag) 1579 bus_dma_tag_destroy(sc->rl_parent_tag); 1580 1581 mtx_destroy(&sc->rl_mtx); 1582 1583 return (0); 1584} 1585 1586static __inline void 1587re_discard_rxbuf(sc, idx) 1588 struct rl_softc *sc; 1589 int idx; 1590{ 1591 struct rl_desc *desc; 1592 struct rl_rxdesc *rxd; 1593 uint32_t cmdstat; 1594 1595 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1596 desc = &sc->rl_ldata.rl_rx_list[idx]; 1597 desc->rl_vlanctl = 0; 1598 cmdstat = rxd->rx_size; 1599 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1600 cmdstat |= RL_RDESC_CMD_EOR; 1601 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1602} 1603 1604static int 1605re_newbuf(sc, idx) 1606 struct rl_softc *sc; 1607 int idx; 1608{ 1609 struct mbuf *m; 1610 struct rl_rxdesc *rxd; 1611 bus_dma_segment_t segs[1]; 1612 bus_dmamap_t map; 1613 struct rl_desc *desc; 1614 uint32_t cmdstat; 1615 int error, nsegs; 1616 1617 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1618 if (m == NULL) 1619 return (ENOBUFS); 1620 1621 m->m_len = m->m_pkthdr.len = MCLBYTES; 1622#ifdef RE_FIXUP_RX 1623 /* 1624 * This is part of an evil trick to deal with non-x86 platforms. 1625 * The RealTek chip requires RX buffers to be aligned on 64-bit 1626 * boundaries, but that will hose non-x86 machines. To get around 1627 * this, we leave some empty space at the start of each buffer 1628 * and for non-x86 hosts, we copy the buffer back six bytes 1629 * to achieve word alignment. This is slightly more efficient 1630 * than allocating a new buffer, copying the contents, and 1631 * discarding the old buffer. 1632 */ 1633 m_adj(m, RE_ETHER_ALIGN); 1634#endif 1635 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1636 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1637 if (error != 0) { 1638 m_freem(m); 1639 return (ENOBUFS); 1640 } 1641 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1642 1643 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1644 if (rxd->rx_m != NULL) { 1645 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1646 BUS_DMASYNC_POSTREAD); 1647 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1648 } 1649 1650 rxd->rx_m = m; 1651 map = rxd->rx_dmamap; 1652 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1653 rxd->rx_size = segs[0].ds_len; 1654 sc->rl_ldata.rl_rx_sparemap = map; 1655 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1656 BUS_DMASYNC_PREREAD); 1657 1658 desc = &sc->rl_ldata.rl_rx_list[idx]; 1659 desc->rl_vlanctl = 0; 1660 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1661 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1662 cmdstat = segs[0].ds_len; 1663 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1664 cmdstat |= RL_RDESC_CMD_EOR; 1665 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1666 1667 return (0); 1668} 1669 1670#ifdef RE_FIXUP_RX 1671static __inline void 1672re_fixup_rx(m) 1673 struct mbuf *m; 1674{ 1675 int i; 1676 uint16_t *src, *dst; 1677 1678 src = mtod(m, uint16_t *); 1679 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1680 1681 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1682 *dst++ = *src++; 1683 1684 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1685 1686 return; 1687} 1688#endif 1689 1690static int 1691re_tx_list_init(sc) 1692 struct rl_softc *sc; 1693{ 1694 struct rl_desc *desc; 1695 int i; 1696 1697 RL_LOCK_ASSERT(sc); 1698 1699 bzero(sc->rl_ldata.rl_tx_list, 1700 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1701 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1702 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1703 /* Set EOR. */ 1704 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1705 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1706 1707 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1708 sc->rl_ldata.rl_tx_list_map, 1709 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1710 1711 sc->rl_ldata.rl_tx_prodidx = 0; 1712 sc->rl_ldata.rl_tx_considx = 0; 1713 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1714 1715 return (0); 1716} 1717 1718static int 1719re_rx_list_init(sc) 1720 struct rl_softc *sc; 1721{ 1722 int error, i; 1723 1724 bzero(sc->rl_ldata.rl_rx_list, 1725 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1726 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1727 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1728 if ((error = re_newbuf(sc, i)) != 0) 1729 return (error); 1730 } 1731 1732 /* Flush the RX descriptors */ 1733 1734 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1735 sc->rl_ldata.rl_rx_list_map, 1736 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1737 1738 sc->rl_ldata.rl_rx_prodidx = 0; 1739 sc->rl_head = sc->rl_tail = NULL; 1740 1741 return (0); 1742} 1743 1744/* 1745 * RX handler for C+ and 8169. For the gigE chips, we support 1746 * the reception of jumbo frames that have been fragmented 1747 * across multiple 2K mbuf cluster buffers. 1748 */ 1749static int 1750re_rxeof(sc) 1751 struct rl_softc *sc; 1752{ 1753 struct mbuf *m; 1754 struct ifnet *ifp; 1755 int i, total_len; 1756 struct rl_desc *cur_rx; 1757 u_int32_t rxstat, rxvlan; 1758 int maxpkt = 16; 1759 1760 RL_LOCK_ASSERT(sc); 1761 1762 ifp = sc->rl_ifp; 1763 1764 /* Invalidate the descriptor memory */ 1765 1766 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1767 sc->rl_ldata.rl_rx_list_map, 1768 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1769 1770 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1771 i = RL_RX_DESC_NXT(sc, i)) { 1772 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1773 rxstat = le32toh(cur_rx->rl_cmdstat); 1774 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1775 break; 1776 total_len = rxstat & sc->rl_rxlenmask; 1777 rxvlan = le32toh(cur_rx->rl_vlanctl); 1778 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1779 1780 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1781 if (re_newbuf(sc, i) != 0) { 1782 /* 1783 * If this is part of a multi-fragment packet, 1784 * discard all the pieces. 1785 */ 1786 if (sc->rl_head != NULL) { 1787 m_freem(sc->rl_head); 1788 sc->rl_head = sc->rl_tail = NULL; 1789 } 1790 re_discard_rxbuf(sc, i); 1791 continue; 1792 } 1793 m->m_len = RE_RX_DESC_BUFLEN; 1794 if (sc->rl_head == NULL) 1795 sc->rl_head = sc->rl_tail = m; 1796 else { 1797 m->m_flags &= ~M_PKTHDR; 1798 sc->rl_tail->m_next = m; 1799 sc->rl_tail = m; 1800 } 1801 continue; 1802 } 1803 1804 /* 1805 * NOTE: for the 8139C+, the frame length field 1806 * is always 12 bits in size, but for the gigE chips, 1807 * it is 13 bits (since the max RX frame length is 16K). 1808 * Unfortunately, all 32 bits in the status word 1809 * were already used, so to make room for the extra 1810 * length bit, RealTek took out the 'frame alignment 1811 * error' bit and shifted the other status bits 1812 * over one slot. The OWN, EOR, FS and LS bits are 1813 * still in the same places. We have already extracted 1814 * the frame length and checked the OWN bit, so rather 1815 * than using an alternate bit mapping, we shift the 1816 * status bits one space to the right so we can evaluate 1817 * them using the 8169 status as though it was in the 1818 * same format as that of the 8139C+. 1819 */ 1820 if (sc->rl_type == RL_8169) 1821 rxstat >>= 1; 1822 1823 /* 1824 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1825 * set, but if CRC is clear, it will still be a valid frame. 1826 */ 1827 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1828 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1829 ifp->if_ierrors++; 1830 /* 1831 * If this is part of a multi-fragment packet, 1832 * discard all the pieces. 1833 */ 1834 if (sc->rl_head != NULL) { 1835 m_freem(sc->rl_head); 1836 sc->rl_head = sc->rl_tail = NULL; 1837 } 1838 re_discard_rxbuf(sc, i); 1839 continue; 1840 } 1841 1842 /* 1843 * If allocating a replacement mbuf fails, 1844 * reload the current one. 1845 */ 1846 1847 if (re_newbuf(sc, i) != 0) { 1848 ifp->if_iqdrops++; 1849 if (sc->rl_head != NULL) { 1850 m_freem(sc->rl_head); 1851 sc->rl_head = sc->rl_tail = NULL; 1852 } 1853 re_discard_rxbuf(sc, i); 1854 continue; 1855 } 1856 1857 if (sc->rl_head != NULL) { 1858 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1859 if (m->m_len == 0) 1860 m->m_len = RE_RX_DESC_BUFLEN; 1861 /* 1862 * Special case: if there's 4 bytes or less 1863 * in this buffer, the mbuf can be discarded: 1864 * the last 4 bytes is the CRC, which we don't 1865 * care about anyway. 1866 */ 1867 if (m->m_len <= ETHER_CRC_LEN) { 1868 sc->rl_tail->m_len -= 1869 (ETHER_CRC_LEN - m->m_len); 1870 m_freem(m); 1871 } else { 1872 m->m_len -= ETHER_CRC_LEN; 1873 m->m_flags &= ~M_PKTHDR; 1874 sc->rl_tail->m_next = m; 1875 } 1876 m = sc->rl_head; 1877 sc->rl_head = sc->rl_tail = NULL; 1878 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1879 } else 1880 m->m_pkthdr.len = m->m_len = 1881 (total_len - ETHER_CRC_LEN); 1882 1883#ifdef RE_FIXUP_RX 1884 re_fixup_rx(m); 1885#endif 1886 ifp->if_ipackets++; 1887 m->m_pkthdr.rcvif = ifp; 1888 1889 /* Do RX checksumming if enabled */ 1890 1891 if (ifp->if_capenable & IFCAP_RXCSUM) { 1892 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1893 /* Check IP header checksum */ 1894 if (rxstat & RL_RDESC_STAT_PROTOID) 1895 m->m_pkthdr.csum_flags |= 1896 CSUM_IP_CHECKED; 1897 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1898 m->m_pkthdr.csum_flags |= 1899 CSUM_IP_VALID; 1900 1901 /* Check TCP/UDP checksum */ 1902 if ((RL_TCPPKT(rxstat) && 1903 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1904 (RL_UDPPKT(rxstat) && 1905 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1906 m->m_pkthdr.csum_flags |= 1907 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1908 m->m_pkthdr.csum_data = 0xffff; 1909 } 1910 } else { 1911 /* 1912 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1913 */ 1914 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1915 (rxvlan & RL_RDESC_IPV4)) 1916 m->m_pkthdr.csum_flags |= 1917 CSUM_IP_CHECKED; 1918 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1919 (rxvlan & RL_RDESC_IPV4)) 1920 m->m_pkthdr.csum_flags |= 1921 CSUM_IP_VALID; 1922 if (((rxstat & RL_RDESC_STAT_TCP) && 1923 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1924 ((rxstat & RL_RDESC_STAT_UDP) && 1925 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1926 m->m_pkthdr.csum_flags |= 1927 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1928 m->m_pkthdr.csum_data = 0xffff; 1929 } 1930 } 1931 } 1932 maxpkt--; 1933 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1934 m->m_pkthdr.ether_vtag = 1935 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1936 m->m_flags |= M_VLANTAG; 1937 } 1938 RL_UNLOCK(sc); 1939 (*ifp->if_input)(ifp, m); 1940 RL_LOCK(sc); 1941 } 1942 1943 /* Flush the RX DMA ring */ 1944 1945 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1946 sc->rl_ldata.rl_rx_list_map, 1947 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1948 1949 sc->rl_ldata.rl_rx_prodidx = i; 1950 1951 if (maxpkt) 1952 return(EAGAIN); 1953 1954 return(0); 1955} 1956 1957static void 1958re_txeof(sc) 1959 struct rl_softc *sc; 1960{ 1961 struct ifnet *ifp; 1962 struct rl_txdesc *txd; 1963 u_int32_t txstat; 1964 int cons; 1965 1966 cons = sc->rl_ldata.rl_tx_considx; 1967 if (cons == sc->rl_ldata.rl_tx_prodidx) 1968 return; 1969 1970 ifp = sc->rl_ifp; 1971 /* Invalidate the TX descriptor list */ 1972 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1973 sc->rl_ldata.rl_tx_list_map, 1974 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1975 1976 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1977 cons = RL_TX_DESC_NXT(sc, cons)) { 1978 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1979 if (txstat & RL_TDESC_STAT_OWN) 1980 break; 1981 /* 1982 * We only stash mbufs in the last descriptor 1983 * in a fragment chain, which also happens to 1984 * be the only place where the TX status bits 1985 * are valid. 1986 */ 1987 if (txstat & RL_TDESC_CMD_EOF) { 1988 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1989 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1990 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1991 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1992 txd->tx_dmamap); 1993 KASSERT(txd->tx_m != NULL, 1994 ("%s: freeing NULL mbufs!", __func__)); 1995 m_freem(txd->tx_m); 1996 txd->tx_m = NULL; 1997 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1998 RL_TDESC_STAT_COLCNT)) 1999 ifp->if_collisions++; 2000 if (txstat & RL_TDESC_STAT_TXERRSUM) 2001 ifp->if_oerrors++; 2002 else 2003 ifp->if_opackets++; 2004 } 2005 sc->rl_ldata.rl_tx_free++; 2006 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2007 } 2008 sc->rl_ldata.rl_tx_considx = cons; 2009 2010 /* No changes made to the TX ring, so no flush needed */ 2011 2012 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2013 /* 2014 * Some chips will ignore a second TX request issued 2015 * while an existing transmission is in progress. If 2016 * the transmitter goes idle but there are still 2017 * packets waiting to be sent, we need to restart the 2018 * channel here to flush them out. This only seems to 2019 * be required with the PCIe devices. 2020 */ 2021 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2022 2023#ifdef RE_TX_MODERATION 2024 /* 2025 * If not all descriptors have been reaped yet, reload 2026 * the timer so that we will eventually get another 2027 * interrupt that will cause us to re-enter this routine. 2028 * This is done in case the transmitter has gone idle. 2029 */ 2030 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2031#endif 2032 } else 2033 sc->rl_watchdog_timer = 0; 2034} 2035 2036static void 2037re_tick(xsc) 2038 void *xsc; 2039{ 2040 struct rl_softc *sc; 2041 struct mii_data *mii; 2042 struct ifnet *ifp; 2043 2044 sc = xsc; 2045 ifp = sc->rl_ifp; 2046 2047 RL_LOCK_ASSERT(sc); 2048 2049 re_watchdog(sc); 2050 2051 mii = device_get_softc(sc->rl_miibus); 2052 mii_tick(mii); 2053 if ((sc->rl_flags & RL_FLAG_LINK) != 0) { 2054 if (!(mii->mii_media_status & IFM_ACTIVE)) 2055 sc->rl_flags &= ~RL_FLAG_LINK; 2056 } else { 2057 if (mii->mii_media_status & IFM_ACTIVE && 2058 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2059 sc->rl_flags |= RL_FLAG_LINK; 2060 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2061 taskqueue_enqueue_fast(taskqueue_fast, 2062 &sc->rl_txtask); 2063 } 2064 } 2065 2066 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2067} 2068 2069#ifdef DEVICE_POLLING 2070static void 2071re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2072{ 2073 struct rl_softc *sc = ifp->if_softc; 2074 2075 RL_LOCK(sc); 2076 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2077 re_poll_locked(ifp, cmd, count); 2078 RL_UNLOCK(sc); 2079} 2080 2081static void 2082re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2083{ 2084 struct rl_softc *sc = ifp->if_softc; 2085 2086 RL_LOCK_ASSERT(sc); 2087 2088 sc->rxcycles = count; 2089 re_rxeof(sc); 2090 re_txeof(sc); 2091 2092 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2093 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2094 2095 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2096 u_int16_t status; 2097 2098 status = CSR_READ_2(sc, RL_ISR); 2099 if (status == 0xffff) 2100 return; 2101 if (status) 2102 CSR_WRITE_2(sc, RL_ISR, status); 2103 2104 /* 2105 * XXX check behaviour on receiver stalls. 2106 */ 2107 2108 if (status & RL_ISR_SYSTEM_ERR) { 2109 re_reset(sc); 2110 re_init_locked(sc); 2111 } 2112 } 2113} 2114#endif /* DEVICE_POLLING */ 2115 2116static int 2117re_intr(arg) 2118 void *arg; 2119{ 2120 struct rl_softc *sc; 2121 uint16_t status; 2122 2123 sc = arg; 2124 2125 status = CSR_READ_2(sc, RL_ISR); 2126 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2127 return (FILTER_STRAY); 2128 CSR_WRITE_2(sc, RL_IMR, 0); 2129 2130 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2131 2132 return (FILTER_HANDLED); 2133} 2134 2135static void 2136re_int_task(arg, npending) 2137 void *arg; 2138 int npending; 2139{ 2140 struct rl_softc *sc; 2141 struct ifnet *ifp; 2142 u_int16_t status; 2143 int rval = 0; 2144 2145 sc = arg; 2146 ifp = sc->rl_ifp; 2147 2148 RL_LOCK(sc); 2149 2150 status = CSR_READ_2(sc, RL_ISR); 2151 CSR_WRITE_2(sc, RL_ISR, status); 2152 2153 if (sc->suspended || 2154 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2155 RL_UNLOCK(sc); 2156 return; 2157 } 2158 2159#ifdef DEVICE_POLLING 2160 if (ifp->if_capenable & IFCAP_POLLING) { 2161 RL_UNLOCK(sc); 2162 return; 2163 } 2164#endif 2165 2166 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2167 rval = re_rxeof(sc); 2168 2169#ifdef RE_TX_MODERATION 2170 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2171#else 2172 if (status & (RL_ISR_TX_OK| 2173#endif 2174 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2175 re_txeof(sc); 2176 2177 if (status & RL_ISR_SYSTEM_ERR) { 2178 re_reset(sc); 2179 re_init_locked(sc); 2180 } 2181 2182 if (status & RL_ISR_LINKCHG) { 2183 callout_stop(&sc->rl_stat_callout); 2184 re_tick(sc); 2185 } 2186 2187 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2188 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2189 2190 RL_UNLOCK(sc); 2191 2192 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2193 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2194 return; 2195 } 2196 2197 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2198 2199 return; 2200} 2201 2202static int 2203re_encap(sc, m_head) 2204 struct rl_softc *sc; 2205 struct mbuf **m_head; 2206{ 2207 struct rl_txdesc *txd, *txd_last; 2208 bus_dma_segment_t segs[RL_NTXSEGS]; 2209 bus_dmamap_t map; 2210 struct mbuf *m_new; 2211 struct rl_desc *desc; 2212 int nsegs, prod; 2213 int i, error, ei, si; 2214 int padlen; 2215 uint32_t cmdstat, csum_flags, vlanctl; 2216 2217 RL_LOCK_ASSERT(sc); 2218 M_ASSERTPKTHDR((*m_head)); 2219 2220 /* 2221 * With some of the RealTek chips, using the checksum offload 2222 * support in conjunction with the autopadding feature results 2223 * in the transmission of corrupt frames. For example, if we 2224 * need to send a really small IP fragment that's less than 60 2225 * bytes in size, and IP header checksumming is enabled, the 2226 * resulting ethernet frame that appears on the wire will 2227 * have garbled payload. To work around this, if TX IP checksum 2228 * offload is enabled, we always manually pad short frames out 2229 * to the minimum ethernet frame size. 2230 */ 2231 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2232 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2233 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2234 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2235 if (M_WRITABLE(*m_head) == 0) { 2236 /* Get a writable copy. */ 2237 m_new = m_dup(*m_head, M_DONTWAIT); 2238 m_freem(*m_head); 2239 if (m_new == NULL) { 2240 *m_head = NULL; 2241 return (ENOBUFS); 2242 } 2243 *m_head = m_new; 2244 } 2245 if ((*m_head)->m_next != NULL || 2246 M_TRAILINGSPACE(*m_head) < padlen) { 2247 m_new = m_defrag(*m_head, M_DONTWAIT); 2248 if (m_new == NULL) { 2249 m_freem(*m_head); 2250 *m_head = NULL; 2251 return (ENOBUFS); 2252 } 2253 } else 2254 m_new = *m_head; 2255 2256 /* 2257 * Manually pad short frames, and zero the pad space 2258 * to avoid leaking data. 2259 */ 2260 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2261 m_new->m_pkthdr.len += padlen; 2262 m_new->m_len = m_new->m_pkthdr.len; 2263 *m_head = m_new; 2264 } 2265 2266 prod = sc->rl_ldata.rl_tx_prodidx; 2267 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2268 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2269 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2270 if (error == EFBIG) { 2271 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2272 if (m_new == NULL) { 2273 m_freem(*m_head); 2274 *m_head = NULL; 2275 return (ENOBUFS); 2276 } 2277 *m_head = m_new; 2278 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2279 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2280 if (error != 0) { 2281 m_freem(*m_head); 2282 *m_head = NULL; 2283 return (error); 2284 } 2285 } else if (error != 0) 2286 return (error); 2287 if (nsegs == 0) { 2288 m_freem(*m_head); 2289 *m_head = NULL; 2290 return (EIO); 2291 } 2292 2293 /* Check for number of available descriptors. */ 2294 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2295 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2296 return (ENOBUFS); 2297 } 2298 2299 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2300 BUS_DMASYNC_PREWRITE); 2301 2302 /* 2303 * Set up checksum offload. Note: checksum offload bits must 2304 * appear in all descriptors of a multi-descriptor transmit 2305 * attempt. This is according to testing done with an 8169 2306 * chip. This is a requirement. 2307 */ 2308 vlanctl = 0; 2309 csum_flags = 0; 2310 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2311 csum_flags = RL_TDESC_CMD_LGSEND | 2312 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2313 RL_TDESC_CMD_MSSVAL_SHIFT); 2314 else { 2315 /* 2316 * Unconditionally enable IP checksum if TCP or UDP 2317 * checksum is required. Otherwise, TCP/UDP checksum 2318 * does't make effects. 2319 */ 2320 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2321 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2322 csum_flags |= RL_TDESC_CMD_IPCSUM; 2323 if (((*m_head)->m_pkthdr.csum_flags & 2324 CSUM_TCP) != 0) 2325 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2326 if (((*m_head)->m_pkthdr.csum_flags & 2327 CSUM_UDP) != 0) 2328 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2329 } else { 2330 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2331 if (((*m_head)->m_pkthdr.csum_flags & 2332 CSUM_TCP) != 0) 2333 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2334 if (((*m_head)->m_pkthdr.csum_flags & 2335 CSUM_UDP) != 0) 2336 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2337 } 2338 } 2339 } 2340 2341 /* 2342 * Set up hardware VLAN tagging. Note: vlan tag info must 2343 * appear in all descriptors of a multi-descriptor 2344 * transmission attempt. 2345 */ 2346 if ((*m_head)->m_flags & M_VLANTAG) 2347 vlanctl |= htons((*m_head)->m_pkthdr.ether_vtag) | 2348 RL_TDESC_VLANCTL_TAG; 2349 2350 si = prod; 2351 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2352 desc = &sc->rl_ldata.rl_tx_list[prod]; 2353 desc->rl_vlanctl = htole32(vlanctl); 2354 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2355 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2356 cmdstat = segs[i].ds_len; 2357 if (i != 0) 2358 cmdstat |= RL_TDESC_CMD_OWN; 2359 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2360 cmdstat |= RL_TDESC_CMD_EOR; 2361 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2362 sc->rl_ldata.rl_tx_free--; 2363 } 2364 /* Update producer index. */ 2365 sc->rl_ldata.rl_tx_prodidx = prod; 2366 2367 /* Set EOF on the last descriptor. */ 2368 ei = RL_TX_DESC_PRV(sc, prod); 2369 desc = &sc->rl_ldata.rl_tx_list[ei]; 2370 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2371 2372 desc = &sc->rl_ldata.rl_tx_list[si]; 2373 /* Set SOF and transfer ownership of packet to the chip. */ 2374 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2375 2376 /* 2377 * Insure that the map for this transmission 2378 * is placed at the array index of the last descriptor 2379 * in this chain. (Swap last and first dmamaps.) 2380 */ 2381 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2382 map = txd->tx_dmamap; 2383 txd->tx_dmamap = txd_last->tx_dmamap; 2384 txd_last->tx_dmamap = map; 2385 txd_last->tx_m = *m_head; 2386 2387 return (0); 2388} 2389 2390static void 2391re_tx_task(arg, npending) 2392 void *arg; 2393 int npending; 2394{ 2395 struct ifnet *ifp; 2396 2397 ifp = arg; 2398 re_start(ifp); 2399 2400 return; 2401} 2402 2403/* 2404 * Main transmit routine for C+ and gigE NICs. 2405 */ 2406static void 2407re_start(ifp) 2408 struct ifnet *ifp; 2409{ 2410 struct rl_softc *sc; 2411 struct mbuf *m_head; 2412 int queued; 2413 2414 sc = ifp->if_softc; 2415 2416 RL_LOCK(sc); 2417 2418 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2419 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2420 RL_UNLOCK(sc); 2421 return; 2422 } 2423 2424 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2425 sc->rl_ldata.rl_tx_free > 1;) { 2426 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2427 if (m_head == NULL) 2428 break; 2429 2430 if (re_encap(sc, &m_head) != 0) { 2431 if (m_head == NULL) 2432 break; 2433 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2434 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2435 break; 2436 } 2437 2438 /* 2439 * If there's a BPF listener, bounce a copy of this frame 2440 * to him. 2441 */ 2442 ETHER_BPF_MTAP(ifp, m_head); 2443 2444 queued++; 2445 } 2446 2447 if (queued == 0) { 2448#ifdef RE_TX_MODERATION 2449 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2450 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2451#endif 2452 RL_UNLOCK(sc); 2453 return; 2454 } 2455 2456 /* Flush the TX descriptors */ 2457 2458 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2459 sc->rl_ldata.rl_tx_list_map, 2460 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2461 2462 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2463 2464#ifdef RE_TX_MODERATION 2465 /* 2466 * Use the countdown timer for interrupt moderation. 2467 * 'TX done' interrupts are disabled. Instead, we reset the 2468 * countdown timer, which will begin counting until it hits 2469 * the value in the TIMERINT register, and then trigger an 2470 * interrupt. Each time we write to the TIMERCNT register, 2471 * the timer count is reset to 0. 2472 */ 2473 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2474#endif 2475 2476 /* 2477 * Set a timeout in case the chip goes out to lunch. 2478 */ 2479 sc->rl_watchdog_timer = 5; 2480 2481 RL_UNLOCK(sc); 2482 2483 return; 2484} 2485 2486static void 2487re_init(xsc) 2488 void *xsc; 2489{ 2490 struct rl_softc *sc = xsc; 2491 2492 RL_LOCK(sc); 2493 re_init_locked(sc); 2494 RL_UNLOCK(sc); 2495} 2496 2497static void 2498re_init_locked(sc) 2499 struct rl_softc *sc; 2500{ 2501 struct ifnet *ifp = sc->rl_ifp; 2502 struct mii_data *mii; 2503 u_int32_t rxcfg = 0; 2504 uint16_t cfg; 2505 union { 2506 uint32_t align_dummy; 2507 u_char eaddr[ETHER_ADDR_LEN]; 2508 } eaddr; 2509 2510 RL_LOCK_ASSERT(sc); 2511 2512 mii = device_get_softc(sc->rl_miibus); 2513 2514 /* 2515 * Cancel pending I/O and free all RX/TX buffers. 2516 */ 2517 re_stop(sc); 2518 2519 /* 2520 * Enable C+ RX and TX mode, as well as VLAN stripping and 2521 * RX checksum offload. We must configure the C+ register 2522 * before all others. 2523 */ 2524 cfg = RL_CPLUSCMD_PCI_MRW; 2525 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2526 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2527 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2528 cfg |= RL_CPLUSCMD_VLANSTRIP; 2529 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2530 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2531 /* XXX magic. */ 2532 cfg |= 0x0001; 2533 } else 2534 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2535 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2536 2537 /* 2538 * Init our MAC address. Even though the chipset 2539 * documentation doesn't mention it, we need to enter "Config 2540 * register write enable" mode to modify the ID registers. 2541 */ 2542 /* Copy MAC address on stack to align. */ 2543 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2544 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2545 CSR_WRITE_4(sc, RL_IDR0, 2546 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2547 CSR_WRITE_4(sc, RL_IDR4, 2548 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2549 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2550 2551 /* 2552 * For C+ mode, initialize the RX descriptors and mbufs. 2553 */ 2554 re_rx_list_init(sc); 2555 re_tx_list_init(sc); 2556 2557 /* 2558 * Load the addresses of the RX and TX lists into the chip. 2559 */ 2560 2561 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2562 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2563 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2564 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2565 2566 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2567 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2568 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2569 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2570 2571 /* 2572 * Enable transmit and receive. 2573 */ 2574 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2575 2576 /* 2577 * Set the initial TX and RX configuration. 2578 */ 2579 if (sc->rl_testmode) { 2580 if (sc->rl_type == RL_8169) 2581 CSR_WRITE_4(sc, RL_TXCFG, 2582 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2583 else 2584 CSR_WRITE_4(sc, RL_TXCFG, 2585 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2586 } else 2587 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2588 2589 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2590 2591 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2592 2593 /* Set the individual bit to receive frames for this host only. */ 2594 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2595 rxcfg |= RL_RXCFG_RX_INDIV; 2596 2597 /* If we want promiscuous mode, set the allframes bit. */ 2598 if (ifp->if_flags & IFF_PROMISC) 2599 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2600 else 2601 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2602 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2603 2604 /* 2605 * Set capture broadcast bit to capture broadcast frames. 2606 */ 2607 if (ifp->if_flags & IFF_BROADCAST) 2608 rxcfg |= RL_RXCFG_RX_BROAD; 2609 else 2610 rxcfg &= ~RL_RXCFG_RX_BROAD; 2611 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2612 2613 /* 2614 * Program the multicast filter, if necessary. 2615 */ 2616 re_setmulti(sc); 2617 2618#ifdef DEVICE_POLLING 2619 /* 2620 * Disable interrupts if we are polling. 2621 */ 2622 if (ifp->if_capenable & IFCAP_POLLING) 2623 CSR_WRITE_2(sc, RL_IMR, 0); 2624 else /* otherwise ... */ 2625#endif 2626 2627 /* 2628 * Enable interrupts. 2629 */ 2630 if (sc->rl_testmode) 2631 CSR_WRITE_2(sc, RL_IMR, 0); 2632 else 2633 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2634 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2635 2636 /* Set initial TX threshold */ 2637 sc->rl_txthresh = RL_TX_THRESH_INIT; 2638 2639 /* Start RX/TX process. */ 2640 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2641#ifdef notdef 2642 /* Enable receiver and transmitter. */ 2643 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2644#endif 2645 2646#ifdef RE_TX_MODERATION 2647 /* 2648 * Initialize the timer interrupt register so that 2649 * a timer interrupt will be generated once the timer 2650 * reaches a certain number of ticks. The timer is 2651 * reloaded on each transmit. This gives us TX interrupt 2652 * moderation, which dramatically improves TX frame rate. 2653 */ 2654 if (sc->rl_type == RL_8169) 2655 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2656 else 2657 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2658#endif 2659 2660 /* 2661 * For 8169 gigE NICs, set the max allowed RX packet 2662 * size so we can receive jumbo frames. 2663 */ 2664 if (sc->rl_type == RL_8169) 2665 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2666 2667 if (sc->rl_testmode) 2668 return; 2669 2670 mii_mediachg(mii); 2671 2672 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2673 2674 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2675 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2676 2677 sc->rl_flags &= ~RL_FLAG_LINK; 2678 sc->rl_watchdog_timer = 0; 2679 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2680} 2681 2682/* 2683 * Set media options. 2684 */ 2685static int 2686re_ifmedia_upd(ifp) 2687 struct ifnet *ifp; 2688{ 2689 struct rl_softc *sc; 2690 struct mii_data *mii; 2691 2692 sc = ifp->if_softc; 2693 mii = device_get_softc(sc->rl_miibus); 2694 RL_LOCK(sc); 2695 mii_mediachg(mii); 2696 RL_UNLOCK(sc); 2697 2698 return (0); 2699} 2700 2701/* 2702 * Report current media status. 2703 */ 2704static void 2705re_ifmedia_sts(ifp, ifmr) 2706 struct ifnet *ifp; 2707 struct ifmediareq *ifmr; 2708{ 2709 struct rl_softc *sc; 2710 struct mii_data *mii; 2711 2712 sc = ifp->if_softc; 2713 mii = device_get_softc(sc->rl_miibus); 2714 2715 RL_LOCK(sc); 2716 mii_pollstat(mii); 2717 RL_UNLOCK(sc); 2718 ifmr->ifm_active = mii->mii_media_active; 2719 ifmr->ifm_status = mii->mii_media_status; 2720} 2721 2722static int 2723re_ioctl(ifp, command, data) 2724 struct ifnet *ifp; 2725 u_long command; 2726 caddr_t data; 2727{ 2728 struct rl_softc *sc = ifp->if_softc; 2729 struct ifreq *ifr = (struct ifreq *) data; 2730 struct mii_data *mii; 2731 int error = 0; 2732 2733 switch (command) { 2734 case SIOCSIFMTU: 2735 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2736 error = EINVAL; 2737 break; 2738 } 2739 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2740 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2741 error = EINVAL; 2742 break; 2743 } 2744 RL_LOCK(sc); 2745 if (ifp->if_mtu != ifr->ifr_mtu) 2746 ifp->if_mtu = ifr->ifr_mtu; 2747 RL_UNLOCK(sc); 2748 break; 2749 case SIOCSIFFLAGS: 2750 RL_LOCK(sc); 2751 if ((ifp->if_flags & IFF_UP) != 0) { 2752 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2753 if (((ifp->if_flags ^ sc->rl_if_flags) 2754 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2755 re_setmulti(sc); 2756 } else 2757 re_init_locked(sc); 2758 } else { 2759 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2760 re_stop(sc); 2761 } 2762 sc->rl_if_flags = ifp->if_flags; 2763 RL_UNLOCK(sc); 2764 break; 2765 case SIOCADDMULTI: 2766 case SIOCDELMULTI: 2767 RL_LOCK(sc); 2768 re_setmulti(sc); 2769 RL_UNLOCK(sc); 2770 break; 2771 case SIOCGIFMEDIA: 2772 case SIOCSIFMEDIA: 2773 mii = device_get_softc(sc->rl_miibus); 2774 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2775 break; 2776 case SIOCSIFCAP: 2777 { 2778 int mask, reinit; 2779 2780 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2781 reinit = 0; 2782#ifdef DEVICE_POLLING 2783 if (mask & IFCAP_POLLING) { 2784 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2785 error = ether_poll_register(re_poll, ifp); 2786 if (error) 2787 return(error); 2788 RL_LOCK(sc); 2789 /* Disable interrupts */ 2790 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2791 ifp->if_capenable |= IFCAP_POLLING; 2792 RL_UNLOCK(sc); 2793 } else { 2794 error = ether_poll_deregister(ifp); 2795 /* Enable interrupts. */ 2796 RL_LOCK(sc); 2797 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2798 ifp->if_capenable &= ~IFCAP_POLLING; 2799 RL_UNLOCK(sc); 2800 } 2801 } 2802#endif /* DEVICE_POLLING */ 2803 if (mask & IFCAP_HWCSUM) { 2804 ifp->if_capenable ^= IFCAP_HWCSUM; 2805 if (ifp->if_capenable & IFCAP_TXCSUM) 2806 ifp->if_hwassist |= RE_CSUM_FEATURES; 2807 else 2808 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2809 reinit = 1; 2810 } 2811 if (mask & IFCAP_VLAN_HWTAGGING) { 2812 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2813 reinit = 1; 2814 } 2815 if (mask & IFCAP_TSO4) { 2816 ifp->if_capenable ^= IFCAP_TSO4; 2817 if ((IFCAP_TSO4 & ifp->if_capenable) && 2818 (IFCAP_TSO4 & ifp->if_capabilities)) 2819 ifp->if_hwassist |= CSUM_TSO; 2820 else 2821 ifp->if_hwassist &= ~CSUM_TSO; 2822 } 2823 if ((mask & IFCAP_WOL) != 0 && 2824 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2825 if ((mask & IFCAP_WOL_UCAST) != 0) 2826 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2827 if ((mask & IFCAP_WOL_MCAST) != 0) 2828 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2829 if ((mask & IFCAP_WOL_MAGIC) != 0) 2830 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2831 } 2832 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2833 re_init(sc); 2834 VLAN_CAPABILITIES(ifp); 2835 } 2836 break; 2837 default: 2838 error = ether_ioctl(ifp, command, data); 2839 break; 2840 } 2841 2842 return (error); 2843} 2844 2845static void 2846re_watchdog(sc) 2847 struct rl_softc *sc; 2848{ 2849 2850 RL_LOCK_ASSERT(sc); 2851 2852 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2853 return; 2854 2855 device_printf(sc->rl_dev, "watchdog timeout\n"); 2856 sc->rl_ifp->if_oerrors++; 2857 2858 re_txeof(sc); 2859 re_rxeof(sc); 2860 re_init_locked(sc); 2861} 2862 2863/* 2864 * Stop the adapter and free any mbufs allocated to the 2865 * RX and TX lists. 2866 */ 2867static void 2868re_stop(sc) 2869 struct rl_softc *sc; 2870{ 2871 register int i; 2872 struct ifnet *ifp; 2873 struct rl_txdesc *txd; 2874 struct rl_rxdesc *rxd; 2875 2876 RL_LOCK_ASSERT(sc); 2877 2878 ifp = sc->rl_ifp; 2879 2880 sc->rl_watchdog_timer = 0; 2881 callout_stop(&sc->rl_stat_callout); 2882 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2883 2884 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2885 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2886 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2887 2888 if (sc->rl_head != NULL) { 2889 m_freem(sc->rl_head); 2890 sc->rl_head = sc->rl_tail = NULL; 2891 } 2892 2893 /* Free the TX list buffers. */ 2894 2895 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2896 txd = &sc->rl_ldata.rl_tx_desc[i]; 2897 if (txd->tx_m != NULL) { 2898 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2899 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2900 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2901 txd->tx_dmamap); 2902 m_freem(txd->tx_m); 2903 txd->tx_m = NULL; 2904 } 2905 } 2906 2907 /* Free the RX list buffers. */ 2908 2909 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2910 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2911 if (rxd->rx_m != NULL) { 2912 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2913 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2914 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2915 rxd->rx_dmamap); 2916 m_freem(rxd->rx_m); 2917 rxd->rx_m = NULL; 2918 } 2919 } 2920} 2921 2922/* 2923 * Device suspend routine. Stop the interface and save some PCI 2924 * settings in case the BIOS doesn't restore them properly on 2925 * resume. 2926 */ 2927static int 2928re_suspend(dev) 2929 device_t dev; 2930{ 2931 struct rl_softc *sc; 2932 2933 sc = device_get_softc(dev); 2934 2935 RL_LOCK(sc); 2936 re_stop(sc); 2937 re_setwol(sc); 2938 sc->suspended = 1; 2939 RL_UNLOCK(sc); 2940 2941 return (0); 2942} 2943 2944/* 2945 * Device resume routine. Restore some PCI settings in case the BIOS 2946 * doesn't, re-enable busmastering, and restart the interface if 2947 * appropriate. 2948 */ 2949static int 2950re_resume(dev) 2951 device_t dev; 2952{ 2953 struct rl_softc *sc; 2954 struct ifnet *ifp; 2955 2956 sc = device_get_softc(dev); 2957 2958 RL_LOCK(sc); 2959 2960 ifp = sc->rl_ifp; 2961 2962 /* reinitialize interface if necessary */ 2963 if (ifp->if_flags & IFF_UP) 2964 re_init_locked(sc); 2965 2966 /* 2967 * Clear WOL matching such that normal Rx filtering 2968 * wouldn't interfere with WOL patterns. 2969 */ 2970 re_clrwol(sc); 2971 sc->suspended = 0; 2972 RL_UNLOCK(sc); 2973 2974 return (0); 2975} 2976 2977/* 2978 * Stop all chip I/O so that the kernel's probe routines don't 2979 * get confused by errant DMAs when rebooting. 2980 */ 2981static int 2982re_shutdown(dev) 2983 device_t dev; 2984{ 2985 struct rl_softc *sc; 2986 2987 sc = device_get_softc(dev); 2988 2989 RL_LOCK(sc); 2990 re_stop(sc); 2991 /* 2992 * Mark interface as down since otherwise we will panic if 2993 * interrupt comes in later on, which can happen in some 2994 * cases. 2995 */ 2996 sc->rl_ifp->if_flags &= ~IFF_UP; 2997 re_setwol(sc); 2998 RL_UNLOCK(sc); 2999 3000 return (0); 3001} 3002 3003static void 3004re_setwol(sc) 3005 struct rl_softc *sc; 3006{ 3007 struct ifnet *ifp; 3008 int pmc; 3009 uint16_t pmstat; 3010 uint8_t v; 3011 3012 RL_LOCK_ASSERT(sc); 3013 3014 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3015 return; 3016 3017 ifp = sc->rl_ifp; 3018 /* Enable config register write. */ 3019 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3020 3021 /* Enable PME. */ 3022 v = CSR_READ_1(sc, RL_CFG1); 3023 v &= ~RL_CFG1_PME; 3024 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3025 v |= RL_CFG1_PME; 3026 CSR_WRITE_1(sc, RL_CFG1, v); 3027 3028 v = CSR_READ_1(sc, RL_CFG3); 3029 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3030 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3031 v |= RL_CFG3_WOL_MAGIC; 3032 CSR_WRITE_1(sc, RL_CFG3, v); 3033 3034 /* Config register write done. */ 3035 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3036 3037 v = CSR_READ_1(sc, RL_CFG5); 3038 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3039 v &= ~RL_CFG5_WOL_LANWAKE; 3040 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3041 v |= RL_CFG5_WOL_UCAST; 3042 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3043 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3044 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3045 v |= RL_CFG5_WOL_LANWAKE; 3046 CSR_WRITE_1(sc, RL_CFG5, v); 3047 3048 /* 3049 * It seems that hardware resets its link speed to 100Mbps in 3050 * power down mode so switching to 100Mbps in driver is not 3051 * needed. 3052 */ 3053 3054 /* Request PME if WOL is requested. */ 3055 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3056 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3057 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3058 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3059 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3060} 3061 3062static void 3063re_clrwol(sc) 3064 struct rl_softc *sc; 3065{ 3066 int pmc; 3067 uint8_t v; 3068 3069 RL_LOCK_ASSERT(sc); 3070 3071 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3072 return; 3073 3074 /* Enable config register write. */ 3075 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3076 3077 v = CSR_READ_1(sc, RL_CFG3); 3078 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3079 CSR_WRITE_1(sc, RL_CFG3, v); 3080 3081 /* Config register write done. */ 3082 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3083 3084 v = CSR_READ_1(sc, RL_CFG5); 3085 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3086 v &= ~RL_CFG5_WOL_LANWAKE; 3087 CSR_WRITE_1(sc, RL_CFG5, v); 3088} 3089