if_re.c revision 180175
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 180175 2008-07-02 06:55:03Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* Tunables. */ 159static int msi_disable = 1; 160TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164/* 165 * Various supported device vendors/types and their names. 166 */ 167static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8111B PCIe Gigabit Ethernet" }, 176 { RT_VENDORID, RT_DEVICEID_8169, 0, 177 "RealTek 8169/8169S/8169SB/8110S/8110SB Gigabit Ethernet" }, 178 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 179 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 180 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 181 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 182 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 183 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 184 { USR_VENDORID, USR_DEVICEID_997902, 0, 185 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 186}; 187 188static struct rl_hwrev re_hwrevs[] = { 189 { RL_HWREV_8139, RL_8139, "" }, 190 { RL_HWREV_8139A, RL_8139, "A" }, 191 { RL_HWREV_8139AG, RL_8139, "A-G" }, 192 { RL_HWREV_8139B, RL_8139, "B" }, 193 { RL_HWREV_8130, RL_8139, "8130" }, 194 { RL_HWREV_8139C, RL_8139, "C" }, 195 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 196 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 197 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 198 { RL_HWREV_8169, RL_8169, "8169"}, 199 { RL_HWREV_8169S, RL_8169, "8169S"}, 200 { RL_HWREV_8110S, RL_8169, "8110S"}, 201 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 202 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 203 { RL_HWREV_8100, RL_8139, "8100"}, 204 { RL_HWREV_8101, RL_8139, "8101"}, 205 { RL_HWREV_8100E, RL_8169, "8100E"}, 206 { RL_HWREV_8101E, RL_8169, "8101E"}, 207 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 208 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 209 { 0, 0, NULL } 210}; 211 212static int re_probe (device_t); 213static int re_attach (device_t); 214static int re_detach (device_t); 215 216static int re_encap (struct rl_softc *, struct mbuf **); 217 218static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 219static int re_allocmem (device_t, struct rl_softc *); 220static __inline void re_discard_rxbuf 221 (struct rl_softc *, int); 222static int re_newbuf (struct rl_softc *, int); 223static int re_rx_list_init (struct rl_softc *); 224static int re_tx_list_init (struct rl_softc *); 225#ifdef RE_FIXUP_RX 226static __inline void re_fixup_rx 227 (struct mbuf *); 228#endif 229static int re_rxeof (struct rl_softc *); 230static void re_txeof (struct rl_softc *); 231#ifdef DEVICE_POLLING 232static void re_poll (struct ifnet *, enum poll_cmd, int); 233static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 234#endif 235static int re_intr (void *); 236static void re_tick (void *); 237static void re_tx_task (void *, int); 238static void re_int_task (void *, int); 239static void re_start (struct ifnet *); 240static int re_ioctl (struct ifnet *, u_long, caddr_t); 241static void re_init (void *); 242static void re_init_locked (struct rl_softc *); 243static void re_stop (struct rl_softc *); 244static void re_watchdog (struct rl_softc *); 245static int re_suspend (device_t); 246static int re_resume (device_t); 247static int re_shutdown (device_t); 248static int re_ifmedia_upd (struct ifnet *); 249static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 250 251static void re_eeprom_putbyte (struct rl_softc *, int); 252static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 253static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 254static int re_gmii_readreg (device_t, int, int); 255static int re_gmii_writereg (device_t, int, int, int); 256 257static int re_miibus_readreg (device_t, int, int); 258static int re_miibus_writereg (device_t, int, int, int); 259static void re_miibus_statchg (device_t); 260 261static void re_setmulti (struct rl_softc *); 262static void re_reset (struct rl_softc *); 263static void re_setwol (struct rl_softc *); 264static void re_clrwol (struct rl_softc *); 265 266#ifdef RE_DIAG 267static int re_diag (struct rl_softc *); 268#endif 269 270static device_method_t re_methods[] = { 271 /* Device interface */ 272 DEVMETHOD(device_probe, re_probe), 273 DEVMETHOD(device_attach, re_attach), 274 DEVMETHOD(device_detach, re_detach), 275 DEVMETHOD(device_suspend, re_suspend), 276 DEVMETHOD(device_resume, re_resume), 277 DEVMETHOD(device_shutdown, re_shutdown), 278 279 /* bus interface */ 280 DEVMETHOD(bus_print_child, bus_generic_print_child), 281 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 282 283 /* MII interface */ 284 DEVMETHOD(miibus_readreg, re_miibus_readreg), 285 DEVMETHOD(miibus_writereg, re_miibus_writereg), 286 DEVMETHOD(miibus_statchg, re_miibus_statchg), 287 288 { 0, 0 } 289}; 290 291static driver_t re_driver = { 292 "re", 293 re_methods, 294 sizeof(struct rl_softc) 295}; 296 297static devclass_t re_devclass; 298 299DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 300DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 301DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 302 303#define EE_SET(x) \ 304 CSR_WRITE_1(sc, RL_EECMD, \ 305 CSR_READ_1(sc, RL_EECMD) | x) 306 307#define EE_CLR(x) \ 308 CSR_WRITE_1(sc, RL_EECMD, \ 309 CSR_READ_1(sc, RL_EECMD) & ~x) 310 311/* 312 * Send a read command and address to the EEPROM, check for ACK. 313 */ 314static void 315re_eeprom_putbyte(sc, addr) 316 struct rl_softc *sc; 317 int addr; 318{ 319 register int d, i; 320 321 d = addr | (RL_9346_READ << sc->rl_eewidth); 322 323 /* 324 * Feed in each bit and strobe the clock. 325 */ 326 327 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 328 if (d & i) { 329 EE_SET(RL_EE_DATAIN); 330 } else { 331 EE_CLR(RL_EE_DATAIN); 332 } 333 DELAY(100); 334 EE_SET(RL_EE_CLK); 335 DELAY(150); 336 EE_CLR(RL_EE_CLK); 337 DELAY(100); 338 } 339 340 return; 341} 342 343/* 344 * Read a word of data stored in the EEPROM at address 'addr.' 345 */ 346static void 347re_eeprom_getword(sc, addr, dest) 348 struct rl_softc *sc; 349 int addr; 350 u_int16_t *dest; 351{ 352 register int i; 353 u_int16_t word = 0; 354 355 /* 356 * Send address of word we want to read. 357 */ 358 re_eeprom_putbyte(sc, addr); 359 360 /* 361 * Start reading bits from EEPROM. 362 */ 363 for (i = 0x8000; i; i >>= 1) { 364 EE_SET(RL_EE_CLK); 365 DELAY(100); 366 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 367 word |= i; 368 EE_CLR(RL_EE_CLK); 369 DELAY(100); 370 } 371 372 *dest = word; 373 374 return; 375} 376 377/* 378 * Read a sequence of words from the EEPROM. 379 */ 380static void 381re_read_eeprom(sc, dest, off, cnt) 382 struct rl_softc *sc; 383 caddr_t dest; 384 int off; 385 int cnt; 386{ 387 int i; 388 u_int16_t word = 0, *ptr; 389 390 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 391 392 DELAY(100); 393 394 for (i = 0; i < cnt; i++) { 395 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 396 re_eeprom_getword(sc, off + i, &word); 397 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 398 ptr = (u_int16_t *)(dest + (i * 2)); 399 *ptr = word; 400 } 401 402 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 403 404 return; 405} 406 407static int 408re_gmii_readreg(dev, phy, reg) 409 device_t dev; 410 int phy, reg; 411{ 412 struct rl_softc *sc; 413 u_int32_t rval; 414 int i; 415 416 if (phy != 1) 417 return (0); 418 419 sc = device_get_softc(dev); 420 421 /* Let the rgephy driver read the GMEDIASTAT register */ 422 423 if (reg == RL_GMEDIASTAT) { 424 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 425 return (rval); 426 } 427 428 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 429 DELAY(1000); 430 431 for (i = 0; i < RL_TIMEOUT; i++) { 432 rval = CSR_READ_4(sc, RL_PHYAR); 433 if (rval & RL_PHYAR_BUSY) 434 break; 435 DELAY(100); 436 } 437 438 if (i == RL_TIMEOUT) { 439 device_printf(sc->rl_dev, "PHY read failed\n"); 440 return (0); 441 } 442 443 return (rval & RL_PHYAR_PHYDATA); 444} 445 446static int 447re_gmii_writereg(dev, phy, reg, data) 448 device_t dev; 449 int phy, reg, data; 450{ 451 struct rl_softc *sc; 452 u_int32_t rval; 453 int i; 454 455 sc = device_get_softc(dev); 456 457 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 458 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 459 DELAY(1000); 460 461 for (i = 0; i < RL_TIMEOUT; i++) { 462 rval = CSR_READ_4(sc, RL_PHYAR); 463 if (!(rval & RL_PHYAR_BUSY)) 464 break; 465 DELAY(100); 466 } 467 468 if (i == RL_TIMEOUT) { 469 device_printf(sc->rl_dev, "PHY write failed\n"); 470 return (0); 471 } 472 473 return (0); 474} 475 476static int 477re_miibus_readreg(dev, phy, reg) 478 device_t dev; 479 int phy, reg; 480{ 481 struct rl_softc *sc; 482 u_int16_t rval = 0; 483 u_int16_t re8139_reg = 0; 484 485 sc = device_get_softc(dev); 486 487 if (sc->rl_type == RL_8169) { 488 rval = re_gmii_readreg(dev, phy, reg); 489 return (rval); 490 } 491 492 /* Pretend the internal PHY is only at address 0 */ 493 if (phy) { 494 return (0); 495 } 496 switch (reg) { 497 case MII_BMCR: 498 re8139_reg = RL_BMCR; 499 break; 500 case MII_BMSR: 501 re8139_reg = RL_BMSR; 502 break; 503 case MII_ANAR: 504 re8139_reg = RL_ANAR; 505 break; 506 case MII_ANER: 507 re8139_reg = RL_ANER; 508 break; 509 case MII_ANLPAR: 510 re8139_reg = RL_LPAR; 511 break; 512 case MII_PHYIDR1: 513 case MII_PHYIDR2: 514 return (0); 515 /* 516 * Allow the rlphy driver to read the media status 517 * register. If we have a link partner which does not 518 * support NWAY, this is the register which will tell 519 * us the results of parallel detection. 520 */ 521 case RL_MEDIASTAT: 522 rval = CSR_READ_1(sc, RL_MEDIASTAT); 523 return (rval); 524 default: 525 device_printf(sc->rl_dev, "bad phy register\n"); 526 return (0); 527 } 528 rval = CSR_READ_2(sc, re8139_reg); 529 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 530 /* 8139C+ has different bit layout. */ 531 rval &= ~(BMCR_LOOP | BMCR_ISO); 532 } 533 return (rval); 534} 535 536static int 537re_miibus_writereg(dev, phy, reg, data) 538 device_t dev; 539 int phy, reg, data; 540{ 541 struct rl_softc *sc; 542 u_int16_t re8139_reg = 0; 543 int rval = 0; 544 545 sc = device_get_softc(dev); 546 547 if (sc->rl_type == RL_8169) { 548 rval = re_gmii_writereg(dev, phy, reg, data); 549 return (rval); 550 } 551 552 /* Pretend the internal PHY is only at address 0 */ 553 if (phy) 554 return (0); 555 556 switch (reg) { 557 case MII_BMCR: 558 re8139_reg = RL_BMCR; 559 if (sc->rl_type == RL_8139CPLUS) { 560 /* 8139C+ has different bit layout. */ 561 data &= ~(BMCR_LOOP | BMCR_ISO); 562 } 563 break; 564 case MII_BMSR: 565 re8139_reg = RL_BMSR; 566 break; 567 case MII_ANAR: 568 re8139_reg = RL_ANAR; 569 break; 570 case MII_ANER: 571 re8139_reg = RL_ANER; 572 break; 573 case MII_ANLPAR: 574 re8139_reg = RL_LPAR; 575 break; 576 case MII_PHYIDR1: 577 case MII_PHYIDR2: 578 return (0); 579 break; 580 default: 581 device_printf(sc->rl_dev, "bad phy register\n"); 582 return (0); 583 } 584 CSR_WRITE_2(sc, re8139_reg, data); 585 return (0); 586} 587 588static void 589re_miibus_statchg(dev) 590 device_t dev; 591{ 592 593} 594 595/* 596 * Program the 64-bit multicast hash filter. 597 */ 598static void 599re_setmulti(sc) 600 struct rl_softc *sc; 601{ 602 struct ifnet *ifp; 603 int h = 0; 604 u_int32_t hashes[2] = { 0, 0 }; 605 struct ifmultiaddr *ifma; 606 u_int32_t rxfilt; 607 int mcnt = 0; 608 609 RL_LOCK_ASSERT(sc); 610 611 ifp = sc->rl_ifp; 612 613 614 rxfilt = CSR_READ_4(sc, RL_RXCFG); 615 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 616 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 617 if (ifp->if_flags & IFF_PROMISC) 618 rxfilt |= RL_RXCFG_RX_ALLPHYS; 619 /* 620 * Unlike other hardwares, we have to explicitly set 621 * RL_RXCFG_RX_MULTI to receive multicast frames in 622 * promiscuous mode. 623 */ 624 rxfilt |= RL_RXCFG_RX_MULTI; 625 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 626 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 627 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 628 return; 629 } 630 631 /* first, zot all the existing hash bits */ 632 CSR_WRITE_4(sc, RL_MAR0, 0); 633 CSR_WRITE_4(sc, RL_MAR4, 0); 634 635 /* now program new ones */ 636 IF_ADDR_LOCK(ifp); 637 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 638 if (ifma->ifma_addr->sa_family != AF_LINK) 639 continue; 640 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 641 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 642 if (h < 32) 643 hashes[0] |= (1 << h); 644 else 645 hashes[1] |= (1 << (h - 32)); 646 mcnt++; 647 } 648 IF_ADDR_UNLOCK(ifp); 649 650 if (mcnt) 651 rxfilt |= RL_RXCFG_RX_MULTI; 652 else 653 rxfilt &= ~RL_RXCFG_RX_MULTI; 654 655 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 656 657 /* 658 * For some unfathomable reason, RealTek decided to reverse 659 * the order of the multicast hash registers in the PCI Express 660 * parts. This means we have to write the hash pattern in reverse 661 * order for those devices. 662 */ 663 664 if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) { 665 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 666 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 667 } else { 668 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 669 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 670 } 671} 672 673static void 674re_reset(sc) 675 struct rl_softc *sc; 676{ 677 register int i; 678 679 RL_LOCK_ASSERT(sc); 680 681 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 682 683 for (i = 0; i < RL_TIMEOUT; i++) { 684 DELAY(10); 685 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 686 break; 687 } 688 if (i == RL_TIMEOUT) 689 device_printf(sc->rl_dev, "reset never completed!\n"); 690 691 CSR_WRITE_1(sc, 0x82, 1); 692} 693 694#ifdef RE_DIAG 695 696/* 697 * The following routine is designed to test for a defect on some 698 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 699 * lines connected to the bus, however for a 32-bit only card, they 700 * should be pulled high. The result of this defect is that the 701 * NIC will not work right if you plug it into a 64-bit slot: DMA 702 * operations will be done with 64-bit transfers, which will fail 703 * because the 64-bit data lines aren't connected. 704 * 705 * There's no way to work around this (short of talking a soldering 706 * iron to the board), however we can detect it. The method we use 707 * here is to put the NIC into digital loopback mode, set the receiver 708 * to promiscuous mode, and then try to send a frame. We then compare 709 * the frame data we sent to what was received. If the data matches, 710 * then the NIC is working correctly, otherwise we know the user has 711 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 712 * slot. In the latter case, there's no way the NIC can work correctly, 713 * so we print out a message on the console and abort the device attach. 714 */ 715 716static int 717re_diag(sc) 718 struct rl_softc *sc; 719{ 720 struct ifnet *ifp = sc->rl_ifp; 721 struct mbuf *m0; 722 struct ether_header *eh; 723 struct rl_desc *cur_rx; 724 u_int16_t status; 725 u_int32_t rxstat; 726 int total_len, i, error = 0, phyaddr; 727 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 728 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 729 730 /* Allocate a single mbuf */ 731 MGETHDR(m0, M_DONTWAIT, MT_DATA); 732 if (m0 == NULL) 733 return (ENOBUFS); 734 735 RL_LOCK(sc); 736 737 /* 738 * Initialize the NIC in test mode. This sets the chip up 739 * so that it can send and receive frames, but performs the 740 * following special functions: 741 * - Puts receiver in promiscuous mode 742 * - Enables digital loopback mode 743 * - Leaves interrupts turned off 744 */ 745 746 ifp->if_flags |= IFF_PROMISC; 747 sc->rl_testmode = 1; 748 re_reset(sc); 749 re_init_locked(sc); 750 sc->rl_flags |= RL_FLAG_LINK; 751 if (sc->rl_type == RL_8169) 752 phyaddr = 1; 753 else 754 phyaddr = 0; 755 756 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 757 for (i = 0; i < RL_TIMEOUT; i++) { 758 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 759 if (!(status & BMCR_RESET)) 760 break; 761 } 762 763 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 764 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 765 766 DELAY(100000); 767 768 /* Put some data in the mbuf */ 769 770 eh = mtod(m0, struct ether_header *); 771 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 772 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 773 eh->ether_type = htons(ETHERTYPE_IP); 774 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 775 776 /* 777 * Queue the packet, start transmission. 778 * Note: IF_HANDOFF() ultimately calls re_start() for us. 779 */ 780 781 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 782 RL_UNLOCK(sc); 783 /* XXX: re_diag must not be called when in ALTQ mode */ 784 IF_HANDOFF(&ifp->if_snd, m0, ifp); 785 RL_LOCK(sc); 786 m0 = NULL; 787 788 /* Wait for it to propagate through the chip */ 789 790 DELAY(100000); 791 for (i = 0; i < RL_TIMEOUT; i++) { 792 status = CSR_READ_2(sc, RL_ISR); 793 CSR_WRITE_2(sc, RL_ISR, status); 794 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 795 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 796 break; 797 DELAY(10); 798 } 799 800 if (i == RL_TIMEOUT) { 801 device_printf(sc->rl_dev, 802 "diagnostic failed, failed to receive packet in" 803 " loopback mode\n"); 804 error = EIO; 805 goto done; 806 } 807 808 /* 809 * The packet should have been dumped into the first 810 * entry in the RX DMA ring. Grab it from there. 811 */ 812 813 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 814 sc->rl_ldata.rl_rx_list_map, 815 BUS_DMASYNC_POSTREAD); 816 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 817 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 818 BUS_DMASYNC_POSTREAD); 819 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 820 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 821 822 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 823 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 824 eh = mtod(m0, struct ether_header *); 825 826 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 827 total_len = RL_RXBYTES(cur_rx); 828 rxstat = le32toh(cur_rx->rl_cmdstat); 829 830 if (total_len != ETHER_MIN_LEN) { 831 device_printf(sc->rl_dev, 832 "diagnostic failed, received short packet\n"); 833 error = EIO; 834 goto done; 835 } 836 837 /* Test that the received packet data matches what we sent. */ 838 839 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 840 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 841 ntohs(eh->ether_type) != ETHERTYPE_IP) { 842 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 843 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 844 dst, ":", src, ":", ETHERTYPE_IP); 845 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 846 eh->ether_dhost, ":", eh->ether_shost, ":", 847 ntohs(eh->ether_type)); 848 device_printf(sc->rl_dev, "You may have a defective 32-bit " 849 "NIC plugged into a 64-bit PCI slot.\n"); 850 device_printf(sc->rl_dev, "Please re-install the NIC in a " 851 "32-bit slot for proper operation.\n"); 852 device_printf(sc->rl_dev, "Read the re(4) man page for more " 853 "details.\n"); 854 error = EIO; 855 } 856 857done: 858 /* Turn interface off, release resources */ 859 860 sc->rl_testmode = 0; 861 sc->rl_flags &= ~RL_FLAG_LINK; 862 ifp->if_flags &= ~IFF_PROMISC; 863 re_stop(sc); 864 if (m0 != NULL) 865 m_freem(m0); 866 867 RL_UNLOCK(sc); 868 869 return (error); 870} 871 872#endif 873 874/* 875 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 876 * IDs against our list and return a device name if we find a match. 877 */ 878static int 879re_probe(dev) 880 device_t dev; 881{ 882 struct rl_type *t; 883 uint16_t devid, vendor; 884 uint16_t revid, sdevid; 885 int i; 886 887 vendor = pci_get_vendor(dev); 888 devid = pci_get_device(dev); 889 revid = pci_get_revid(dev); 890 sdevid = pci_get_subdevice(dev); 891 892 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 893 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 894 /* 895 * Only attach to rev. 3 of the Linksys EG1032 adapter. 896 * Rev. 2 is supported by sk(4). 897 */ 898 return (ENXIO); 899 } 900 } 901 902 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 903 if (revid != 0x20) { 904 /* 8139, let rl(4) take care of this device. */ 905 return (ENXIO); 906 } 907 } 908 909 t = re_devs; 910 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 911 if (vendor == t->rl_vid && devid == t->rl_did) { 912 device_set_desc(dev, t->rl_name); 913 return (BUS_PROBE_DEFAULT); 914 } 915 } 916 917 return (ENXIO); 918} 919 920/* 921 * Map a single buffer address. 922 */ 923 924static void 925re_dma_map_addr(arg, segs, nseg, error) 926 void *arg; 927 bus_dma_segment_t *segs; 928 int nseg; 929 int error; 930{ 931 bus_addr_t *addr; 932 933 if (error) 934 return; 935 936 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 937 addr = arg; 938 *addr = segs->ds_addr; 939} 940 941static int 942re_allocmem(dev, sc) 943 device_t dev; 944 struct rl_softc *sc; 945{ 946 bus_size_t rx_list_size, tx_list_size; 947 int error; 948 int i; 949 950 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 951 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 952 953 /* 954 * Allocate the parent bus DMA tag appropriate for PCI. 955 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 956 * register should be set. However some RealTek chips are known 957 * to be buggy on DAC handling, therefore disable DAC by limiting 958 * DMA address space to 32bit. PCIe variants of RealTek chips 959 * may not have the limitation but I took safer path. 960 */ 961 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 962 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 963 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 964 NULL, NULL, &sc->rl_parent_tag); 965 if (error) { 966 device_printf(dev, "could not allocate parent DMA tag\n"); 967 return (error); 968 } 969 970 /* 971 * Allocate map for TX mbufs. 972 */ 973 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 974 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 975 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 976 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 977 if (error) { 978 device_printf(dev, "could not allocate TX DMA tag\n"); 979 return (error); 980 } 981 982 /* 983 * Allocate map for RX mbufs. 984 */ 985 986 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 987 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 988 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 989 if (error) { 990 device_printf(dev, "could not allocate RX DMA tag\n"); 991 return (error); 992 } 993 994 /* 995 * Allocate map for TX descriptor list. 996 */ 997 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 998 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 999 NULL, tx_list_size, 1, tx_list_size, 0, 1000 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1001 if (error) { 1002 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1003 return (error); 1004 } 1005 1006 /* Allocate DMA'able memory for the TX ring */ 1007 1008 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1009 (void **)&sc->rl_ldata.rl_tx_list, 1010 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1011 &sc->rl_ldata.rl_tx_list_map); 1012 if (error) { 1013 device_printf(dev, "could not allocate TX DMA ring\n"); 1014 return (error); 1015 } 1016 1017 /* Load the map for the TX ring. */ 1018 1019 sc->rl_ldata.rl_tx_list_addr = 0; 1020 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1021 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1022 tx_list_size, re_dma_map_addr, 1023 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1024 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1025 device_printf(dev, "could not load TX DMA ring\n"); 1026 return (ENOMEM); 1027 } 1028 1029 /* Create DMA maps for TX buffers */ 1030 1031 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1032 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1033 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1034 if (error) { 1035 device_printf(dev, "could not create DMA map for TX\n"); 1036 return (error); 1037 } 1038 } 1039 1040 /* 1041 * Allocate map for RX descriptor list. 1042 */ 1043 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1044 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1045 NULL, rx_list_size, 1, rx_list_size, 0, 1046 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1047 if (error) { 1048 device_printf(dev, "could not create RX DMA ring tag\n"); 1049 return (error); 1050 } 1051 1052 /* Allocate DMA'able memory for the RX ring */ 1053 1054 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1055 (void **)&sc->rl_ldata.rl_rx_list, 1056 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1057 &sc->rl_ldata.rl_rx_list_map); 1058 if (error) { 1059 device_printf(dev, "could not allocate RX DMA ring\n"); 1060 return (error); 1061 } 1062 1063 /* Load the map for the RX ring. */ 1064 1065 sc->rl_ldata.rl_rx_list_addr = 0; 1066 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1067 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1068 rx_list_size, re_dma_map_addr, 1069 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1070 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1071 device_printf(dev, "could not load RX DMA ring\n"); 1072 return (ENOMEM); 1073 } 1074 1075 /* Create DMA maps for RX buffers */ 1076 1077 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1078 &sc->rl_ldata.rl_rx_sparemap); 1079 if (error) { 1080 device_printf(dev, "could not create spare DMA map for RX\n"); 1081 return (error); 1082 } 1083 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1084 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1085 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1086 if (error) { 1087 device_printf(dev, "could not create DMA map for RX\n"); 1088 return (error); 1089 } 1090 } 1091 1092 return (0); 1093} 1094 1095/* 1096 * Attach the interface. Allocate softc structures, do ifmedia 1097 * setup and ethernet/BPF attach. 1098 */ 1099static int 1100re_attach(dev) 1101 device_t dev; 1102{ 1103 u_char eaddr[ETHER_ADDR_LEN]; 1104 u_int16_t as[ETHER_ADDR_LEN / 2]; 1105 struct rl_softc *sc; 1106 struct ifnet *ifp; 1107 struct rl_hwrev *hw_rev; 1108 int hwrev; 1109 u_int16_t devid, re_did = 0; 1110 int error = 0, rid, i; 1111 int msic, reg; 1112 uint8_t cfg; 1113 1114 sc = device_get_softc(dev); 1115 sc->rl_dev = dev; 1116 1117 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1118 MTX_DEF); 1119 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1120 1121 /* 1122 * Map control/status registers. 1123 */ 1124 pci_enable_busmaster(dev); 1125 1126 devid = pci_get_device(dev); 1127 /* Prefer memory space register mapping over IO space. */ 1128 sc->rl_res_id = PCIR_BAR(1); 1129 sc->rl_res_type = SYS_RES_MEMORY; 1130 /* RTL8168/8101E seems to use different BARs. */ 1131 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1132 sc->rl_res_id = PCIR_BAR(2); 1133 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1134 &sc->rl_res_id, RF_ACTIVE); 1135 1136 if (sc->rl_res == NULL) { 1137 sc->rl_res_id = PCIR_BAR(0); 1138 sc->rl_res_type = SYS_RES_IOPORT; 1139 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1140 &sc->rl_res_id, RF_ACTIVE); 1141 if (sc->rl_res == NULL) { 1142 device_printf(dev, "couldn't map ports/memory\n"); 1143 error = ENXIO; 1144 goto fail; 1145 } 1146 } 1147 1148 sc->rl_btag = rman_get_bustag(sc->rl_res); 1149 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1150 1151 msic = 0; 1152 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1153 msic = pci_msi_count(dev); 1154 if (bootverbose) 1155 device_printf(dev, "MSI count : %d\n", msic); 1156 } 1157 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1158 if (pci_alloc_msi(dev, &msic) == 0) { 1159 if (msic == RL_MSI_MESSAGES) { 1160 device_printf(dev, "Using %d MSI messages\n", 1161 msic); 1162 sc->rl_flags |= RL_FLAG_MSI; 1163 /* Explicitly set MSI enable bit. */ 1164 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1165 cfg = CSR_READ_1(sc, RL_CFG2); 1166 cfg |= RL_CFG2_MSI; 1167 CSR_WRITE_1(sc, RL_CFG2, cfg); 1168 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1169 } else 1170 pci_release_msi(dev); 1171 } 1172 } 1173 1174 /* Allocate interrupt */ 1175 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1176 rid = 0; 1177 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1178 RF_SHAREABLE | RF_ACTIVE); 1179 if (sc->rl_irq[0] == NULL) { 1180 device_printf(dev, "couldn't allocate IRQ resources\n"); 1181 error = ENXIO; 1182 goto fail; 1183 } 1184 } else { 1185 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1186 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1187 SYS_RES_IRQ, &rid, RF_ACTIVE); 1188 if (sc->rl_irq[i] == NULL) { 1189 device_printf(dev, 1190 "couldn't llocate IRQ resources for " 1191 "message %d\n", rid); 1192 error = ENXIO; 1193 goto fail; 1194 } 1195 } 1196 } 1197 1198 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1199 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1200 cfg = CSR_READ_1(sc, RL_CFG2); 1201 if ((cfg & RL_CFG2_MSI) != 0) { 1202 device_printf(dev, "turning off MSI enable bit.\n"); 1203 cfg &= ~RL_CFG2_MSI; 1204 CSR_WRITE_1(sc, RL_CFG2, cfg); 1205 } 1206 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1207 } 1208 1209 /* Reset the adapter. */ 1210 RL_LOCK(sc); 1211 re_reset(sc); 1212 RL_UNLOCK(sc); 1213 1214 hw_rev = re_hwrevs; 1215 hwrev = CSR_READ_4(sc, RL_TXCFG); 1216 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1217 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1218 hwrev &= RL_TXCFG_HWREV; 1219 while (hw_rev->rl_desc != NULL) { 1220 if (hw_rev->rl_rev == hwrev) { 1221 sc->rl_type = hw_rev->rl_type; 1222 break; 1223 } 1224 hw_rev++; 1225 } 1226 if (hw_rev->rl_desc == NULL) { 1227 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1228 error = ENXIO; 1229 goto fail; 1230 } 1231 1232 switch (hw_rev->rl_rev) { 1233 case RL_HWREV_8139CPLUS: 1234 sc->rl_flags |= RL_FLAG_NOJUMBO; 1235 break; 1236 case RL_HWREV_8100E: 1237 case RL_HWREV_8101E: 1238 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE; 1239 break; 1240 case RL_HWREV_8168_SPIN1: 1241 case RL_HWREV_8168_SPIN2: 1242 case RL_HWREV_8168_SPIN3: 1243 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE; 1244 break; 1245 case RL_HWREV_8169_8110SB: 1246 case RL_HWREV_8169_8110SC: 1247 sc->rl_flags |= RL_FLAG_PHYWAKE; 1248 break; 1249 default: 1250 break; 1251 } 1252 1253 sc->rl_eewidth = RL_9356_ADDR_LEN; 1254 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1255 if (re_did != 0x8129) 1256 sc->rl_eewidth = RL_9346_ADDR_LEN; 1257 1258 /* 1259 * Get station address from the EEPROM. 1260 */ 1261 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1262 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1263 as[i] = le16toh(as[i]); 1264 bcopy(as, eaddr, sizeof(eaddr)); 1265 1266 if (sc->rl_type == RL_8169) { 1267 /* Set RX length mask and number of descriptors. */ 1268 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1269 sc->rl_txstart = RL_GTXSTART; 1270 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1271 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1272 } else { 1273 /* Set RX length mask and number of descriptors. */ 1274 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1275 sc->rl_txstart = RL_TXSTART; 1276 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1277 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1278 } 1279 1280 error = re_allocmem(dev, sc); 1281 if (error) 1282 goto fail; 1283 1284 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1285 if (ifp == NULL) { 1286 device_printf(dev, "can not if_alloc()\n"); 1287 error = ENOSPC; 1288 goto fail; 1289 } 1290 1291 /* Take PHY out of power down mode. */ 1292 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1293 re_gmii_writereg(dev, 1, 0x1f, 0); 1294 re_gmii_writereg(dev, 1, 0x0e, 0); 1295 } 1296 1297 /* Do MII setup */ 1298 if (mii_phy_probe(dev, &sc->rl_miibus, 1299 re_ifmedia_upd, re_ifmedia_sts)) { 1300 device_printf(dev, "MII without any phy!\n"); 1301 error = ENXIO; 1302 goto fail; 1303 } 1304 1305 ifp->if_softc = sc; 1306 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1307 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1308 ifp->if_ioctl = re_ioctl; 1309 ifp->if_start = re_start; 1310 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1311 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1312 ifp->if_capenable = ifp->if_capabilities; 1313 ifp->if_init = re_init; 1314 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1315 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1316 IFQ_SET_READY(&ifp->if_snd); 1317 1318 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1319 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1320 1321 /* 1322 * Call MI attach routine. 1323 */ 1324 ether_ifattach(ifp, eaddr); 1325 1326 /* VLAN capability setup */ 1327 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1328 if (ifp->if_capabilities & IFCAP_HWCSUM) 1329 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1330 /* Enable WOL if PM is supported. */ 1331 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1332 ifp->if_capabilities |= IFCAP_WOL; 1333 ifp->if_capenable = ifp->if_capabilities; 1334#ifdef DEVICE_POLLING 1335 ifp->if_capabilities |= IFCAP_POLLING; 1336#endif 1337 /* 1338 * Tell the upper layer(s) we support long frames. 1339 * Must appear after the call to ether_ifattach() because 1340 * ether_ifattach() sets ifi_hdrlen to the default value. 1341 */ 1342 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1343 1344#ifdef RE_DIAG 1345 /* 1346 * Perform hardware diagnostic on the original RTL8169. 1347 * Some 32-bit cards were incorrectly wired and would 1348 * malfunction if plugged into a 64-bit slot. 1349 */ 1350 1351 if (hwrev == RL_HWREV_8169) { 1352 error = re_diag(sc); 1353 if (error) { 1354 device_printf(dev, 1355 "attach aborted due to hardware diag failure\n"); 1356 ether_ifdetach(ifp); 1357 goto fail; 1358 } 1359 } 1360#endif 1361 1362 /* Hook interrupt last to avoid having to lock softc */ 1363 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1364 error = bus_setup_intr(dev, sc->rl_irq[0], 1365 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1366 &sc->rl_intrhand[0]); 1367 else { 1368 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1369 error = bus_setup_intr(dev, sc->rl_irq[i], 1370 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1371 &sc->rl_intrhand[i]); 1372 if (error != 0) 1373 break; 1374 } 1375 } 1376 if (error) { 1377 device_printf(dev, "couldn't set up irq\n"); 1378 ether_ifdetach(ifp); 1379 } 1380 1381fail: 1382 1383 if (error) 1384 re_detach(dev); 1385 1386 return (error); 1387} 1388 1389/* 1390 * Shutdown hardware and free up resources. This can be called any 1391 * time after the mutex has been initialized. It is called in both 1392 * the error case in attach and the normal detach case so it needs 1393 * to be careful about only freeing resources that have actually been 1394 * allocated. 1395 */ 1396static int 1397re_detach(dev) 1398 device_t dev; 1399{ 1400 struct rl_softc *sc; 1401 struct ifnet *ifp; 1402 int i, rid; 1403 1404 sc = device_get_softc(dev); 1405 ifp = sc->rl_ifp; 1406 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1407 1408 /* These should only be active if attach succeeded */ 1409 if (device_is_attached(dev)) { 1410#ifdef DEVICE_POLLING 1411 if (ifp->if_capenable & IFCAP_POLLING) 1412 ether_poll_deregister(ifp); 1413#endif 1414 RL_LOCK(sc); 1415#if 0 1416 sc->suspended = 1; 1417#endif 1418 re_stop(sc); 1419 RL_UNLOCK(sc); 1420 callout_drain(&sc->rl_stat_callout); 1421 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1422 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1423 /* 1424 * Force off the IFF_UP flag here, in case someone 1425 * still had a BPF descriptor attached to this 1426 * interface. If they do, ether_ifdetach() will cause 1427 * the BPF code to try and clear the promisc mode 1428 * flag, which will bubble down to re_ioctl(), 1429 * which will try to call re_init() again. This will 1430 * turn the NIC back on and restart the MII ticker, 1431 * which will panic the system when the kernel tries 1432 * to invoke the re_tick() function that isn't there 1433 * anymore. 1434 */ 1435 ifp->if_flags &= ~IFF_UP; 1436 ether_ifdetach(ifp); 1437 } 1438 if (sc->rl_miibus) 1439 device_delete_child(dev, sc->rl_miibus); 1440 bus_generic_detach(dev); 1441 1442 /* 1443 * The rest is resource deallocation, so we should already be 1444 * stopped here. 1445 */ 1446 1447 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1448 if (sc->rl_intrhand[i] != NULL) { 1449 bus_teardown_intr(dev, sc->rl_irq[i], 1450 sc->rl_intrhand[i]); 1451 sc->rl_intrhand[i] = NULL; 1452 } 1453 } 1454 if (ifp != NULL) 1455 if_free(ifp); 1456 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1457 if (sc->rl_irq[0] != NULL) { 1458 bus_release_resource(dev, SYS_RES_IRQ, 0, 1459 sc->rl_irq[0]); 1460 sc->rl_irq[0] = NULL; 1461 } 1462 } else { 1463 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1464 if (sc->rl_irq[i] != NULL) { 1465 bus_release_resource(dev, SYS_RES_IRQ, rid, 1466 sc->rl_irq[i]); 1467 sc->rl_irq[i] = NULL; 1468 } 1469 } 1470 pci_release_msi(dev); 1471 } 1472 if (sc->rl_res) 1473 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1474 sc->rl_res); 1475 1476 /* Unload and free the RX DMA ring memory and map */ 1477 1478 if (sc->rl_ldata.rl_rx_list_tag) { 1479 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1480 sc->rl_ldata.rl_rx_list_map); 1481 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1482 sc->rl_ldata.rl_rx_list, 1483 sc->rl_ldata.rl_rx_list_map); 1484 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1485 } 1486 1487 /* Unload and free the TX DMA ring memory and map */ 1488 1489 if (sc->rl_ldata.rl_tx_list_tag) { 1490 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1491 sc->rl_ldata.rl_tx_list_map); 1492 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1493 sc->rl_ldata.rl_tx_list, 1494 sc->rl_ldata.rl_tx_list_map); 1495 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1496 } 1497 1498 /* Destroy all the RX and TX buffer maps */ 1499 1500 if (sc->rl_ldata.rl_tx_mtag) { 1501 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1502 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1503 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1504 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1505 } 1506 if (sc->rl_ldata.rl_rx_mtag) { 1507 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1508 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1509 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1510 if (sc->rl_ldata.rl_rx_sparemap) 1511 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1512 sc->rl_ldata.rl_rx_sparemap); 1513 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1514 } 1515 1516 /* Unload and free the stats buffer and map */ 1517 1518 if (sc->rl_ldata.rl_stag) { 1519 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1520 sc->rl_ldata.rl_rx_list_map); 1521 bus_dmamem_free(sc->rl_ldata.rl_stag, 1522 sc->rl_ldata.rl_stats, 1523 sc->rl_ldata.rl_smap); 1524 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1525 } 1526 1527 if (sc->rl_parent_tag) 1528 bus_dma_tag_destroy(sc->rl_parent_tag); 1529 1530 mtx_destroy(&sc->rl_mtx); 1531 1532 return (0); 1533} 1534 1535static __inline void 1536re_discard_rxbuf(sc, idx) 1537 struct rl_softc *sc; 1538 int idx; 1539{ 1540 struct rl_desc *desc; 1541 struct rl_rxdesc *rxd; 1542 uint32_t cmdstat; 1543 1544 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1545 desc = &sc->rl_ldata.rl_rx_list[idx]; 1546 desc->rl_vlanctl = 0; 1547 cmdstat = rxd->rx_size; 1548 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1549 cmdstat |= RL_RDESC_CMD_EOR; 1550 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1551} 1552 1553static int 1554re_newbuf(sc, idx) 1555 struct rl_softc *sc; 1556 int idx; 1557{ 1558 struct mbuf *m; 1559 struct rl_rxdesc *rxd; 1560 bus_dma_segment_t segs[1]; 1561 bus_dmamap_t map; 1562 struct rl_desc *desc; 1563 uint32_t cmdstat; 1564 int error, nsegs; 1565 1566 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1567 if (m == NULL) 1568 return (ENOBUFS); 1569 1570 m->m_len = m->m_pkthdr.len = MCLBYTES; 1571#ifdef RE_FIXUP_RX 1572 /* 1573 * This is part of an evil trick to deal with non-x86 platforms. 1574 * The RealTek chip requires RX buffers to be aligned on 64-bit 1575 * boundaries, but that will hose non-x86 machines. To get around 1576 * this, we leave some empty space at the start of each buffer 1577 * and for non-x86 hosts, we copy the buffer back six bytes 1578 * to achieve word alignment. This is slightly more efficient 1579 * than allocating a new buffer, copying the contents, and 1580 * discarding the old buffer. 1581 */ 1582 m_adj(m, RE_ETHER_ALIGN); 1583#endif 1584 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1585 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1586 if (error != 0) { 1587 m_freem(m); 1588 return (ENOBUFS); 1589 } 1590 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1591 1592 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1593 if (rxd->rx_m != NULL) { 1594 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1595 BUS_DMASYNC_POSTREAD); 1596 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1597 } 1598 1599 rxd->rx_m = m; 1600 map = rxd->rx_dmamap; 1601 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1602 rxd->rx_size = segs[0].ds_len; 1603 sc->rl_ldata.rl_rx_sparemap = map; 1604 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1605 BUS_DMASYNC_PREREAD); 1606 1607 desc = &sc->rl_ldata.rl_rx_list[idx]; 1608 desc->rl_vlanctl = 0; 1609 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1610 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1611 cmdstat = segs[0].ds_len; 1612 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1613 cmdstat |= RL_RDESC_CMD_EOR; 1614 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1615 1616 return (0); 1617} 1618 1619#ifdef RE_FIXUP_RX 1620static __inline void 1621re_fixup_rx(m) 1622 struct mbuf *m; 1623{ 1624 int i; 1625 uint16_t *src, *dst; 1626 1627 src = mtod(m, uint16_t *); 1628 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1629 1630 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1631 *dst++ = *src++; 1632 1633 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1634 1635 return; 1636} 1637#endif 1638 1639static int 1640re_tx_list_init(sc) 1641 struct rl_softc *sc; 1642{ 1643 struct rl_desc *desc; 1644 int i; 1645 1646 RL_LOCK_ASSERT(sc); 1647 1648 bzero(sc->rl_ldata.rl_tx_list, 1649 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1650 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1651 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1652 /* Set EOR. */ 1653 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1654 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1655 1656 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1657 sc->rl_ldata.rl_tx_list_map, 1658 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1659 1660 sc->rl_ldata.rl_tx_prodidx = 0; 1661 sc->rl_ldata.rl_tx_considx = 0; 1662 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1663 1664 return (0); 1665} 1666 1667static int 1668re_rx_list_init(sc) 1669 struct rl_softc *sc; 1670{ 1671 int error, i; 1672 1673 bzero(sc->rl_ldata.rl_rx_list, 1674 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1675 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1676 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1677 if ((error = re_newbuf(sc, i)) != 0) 1678 return (error); 1679 } 1680 1681 /* Flush the RX descriptors */ 1682 1683 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1684 sc->rl_ldata.rl_rx_list_map, 1685 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1686 1687 sc->rl_ldata.rl_rx_prodidx = 0; 1688 sc->rl_head = sc->rl_tail = NULL; 1689 1690 return (0); 1691} 1692 1693/* 1694 * RX handler for C+ and 8169. For the gigE chips, we support 1695 * the reception of jumbo frames that have been fragmented 1696 * across multiple 2K mbuf cluster buffers. 1697 */ 1698static int 1699re_rxeof(sc) 1700 struct rl_softc *sc; 1701{ 1702 struct mbuf *m; 1703 struct ifnet *ifp; 1704 int i, total_len; 1705 struct rl_desc *cur_rx; 1706 u_int32_t rxstat, rxvlan; 1707 int maxpkt = 16; 1708 1709 RL_LOCK_ASSERT(sc); 1710 1711 ifp = sc->rl_ifp; 1712 1713 /* Invalidate the descriptor memory */ 1714 1715 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1716 sc->rl_ldata.rl_rx_list_map, 1717 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1718 1719 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1720 i = RL_RX_DESC_NXT(sc, i)) { 1721 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1722 rxstat = le32toh(cur_rx->rl_cmdstat); 1723 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1724 break; 1725 total_len = rxstat & sc->rl_rxlenmask; 1726 rxvlan = le32toh(cur_rx->rl_vlanctl); 1727 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1728 1729 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1730 if (re_newbuf(sc, i) != 0) { 1731 /* 1732 * If this is part of a multi-fragment packet, 1733 * discard all the pieces. 1734 */ 1735 if (sc->rl_head != NULL) { 1736 m_freem(sc->rl_head); 1737 sc->rl_head = sc->rl_tail = NULL; 1738 } 1739 re_discard_rxbuf(sc, i); 1740 continue; 1741 } 1742 m->m_len = RE_RX_DESC_BUFLEN; 1743 if (sc->rl_head == NULL) 1744 sc->rl_head = sc->rl_tail = m; 1745 else { 1746 m->m_flags &= ~M_PKTHDR; 1747 sc->rl_tail->m_next = m; 1748 sc->rl_tail = m; 1749 } 1750 continue; 1751 } 1752 1753 /* 1754 * NOTE: for the 8139C+, the frame length field 1755 * is always 12 bits in size, but for the gigE chips, 1756 * it is 13 bits (since the max RX frame length is 16K). 1757 * Unfortunately, all 32 bits in the status word 1758 * were already used, so to make room for the extra 1759 * length bit, RealTek took out the 'frame alignment 1760 * error' bit and shifted the other status bits 1761 * over one slot. The OWN, EOR, FS and LS bits are 1762 * still in the same places. We have already extracted 1763 * the frame length and checked the OWN bit, so rather 1764 * than using an alternate bit mapping, we shift the 1765 * status bits one space to the right so we can evaluate 1766 * them using the 8169 status as though it was in the 1767 * same format as that of the 8139C+. 1768 */ 1769 if (sc->rl_type == RL_8169) 1770 rxstat >>= 1; 1771 1772 /* 1773 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1774 * set, but if CRC is clear, it will still be a valid frame. 1775 */ 1776 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1777 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1778 ifp->if_ierrors++; 1779 /* 1780 * If this is part of a multi-fragment packet, 1781 * discard all the pieces. 1782 */ 1783 if (sc->rl_head != NULL) { 1784 m_freem(sc->rl_head); 1785 sc->rl_head = sc->rl_tail = NULL; 1786 } 1787 re_discard_rxbuf(sc, i); 1788 continue; 1789 } 1790 1791 /* 1792 * If allocating a replacement mbuf fails, 1793 * reload the current one. 1794 */ 1795 1796 if (re_newbuf(sc, i) != 0) { 1797 ifp->if_iqdrops++; 1798 if (sc->rl_head != NULL) { 1799 m_freem(sc->rl_head); 1800 sc->rl_head = sc->rl_tail = NULL; 1801 } 1802 re_discard_rxbuf(sc, i); 1803 continue; 1804 } 1805 1806 if (sc->rl_head != NULL) { 1807 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1808 if (m->m_len == 0) 1809 m->m_len = RE_RX_DESC_BUFLEN; 1810 /* 1811 * Special case: if there's 4 bytes or less 1812 * in this buffer, the mbuf can be discarded: 1813 * the last 4 bytes is the CRC, which we don't 1814 * care about anyway. 1815 */ 1816 if (m->m_len <= ETHER_CRC_LEN) { 1817 sc->rl_tail->m_len -= 1818 (ETHER_CRC_LEN - m->m_len); 1819 m_freem(m); 1820 } else { 1821 m->m_len -= ETHER_CRC_LEN; 1822 m->m_flags &= ~M_PKTHDR; 1823 sc->rl_tail->m_next = m; 1824 } 1825 m = sc->rl_head; 1826 sc->rl_head = sc->rl_tail = NULL; 1827 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1828 } else 1829 m->m_pkthdr.len = m->m_len = 1830 (total_len - ETHER_CRC_LEN); 1831 1832#ifdef RE_FIXUP_RX 1833 re_fixup_rx(m); 1834#endif 1835 ifp->if_ipackets++; 1836 m->m_pkthdr.rcvif = ifp; 1837 1838 /* Do RX checksumming if enabled */ 1839 1840 if (ifp->if_capenable & IFCAP_RXCSUM) { 1841 1842 /* Check IP header checksum */ 1843 if (rxstat & RL_RDESC_STAT_PROTOID) 1844 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1845 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1846 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1847 1848 /* Check TCP/UDP checksum */ 1849 if ((RL_TCPPKT(rxstat) && 1850 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1851 (RL_UDPPKT(rxstat) && 1852 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1853 m->m_pkthdr.csum_flags |= 1854 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1855 m->m_pkthdr.csum_data = 0xffff; 1856 } 1857 } 1858 maxpkt--; 1859 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1860 m->m_pkthdr.ether_vtag = 1861 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1862 m->m_flags |= M_VLANTAG; 1863 } 1864 RL_UNLOCK(sc); 1865 (*ifp->if_input)(ifp, m); 1866 RL_LOCK(sc); 1867 } 1868 1869 /* Flush the RX DMA ring */ 1870 1871 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1872 sc->rl_ldata.rl_rx_list_map, 1873 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1874 1875 sc->rl_ldata.rl_rx_prodidx = i; 1876 1877 if (maxpkt) 1878 return(EAGAIN); 1879 1880 return(0); 1881} 1882 1883static void 1884re_txeof(sc) 1885 struct rl_softc *sc; 1886{ 1887 struct ifnet *ifp; 1888 struct rl_txdesc *txd; 1889 u_int32_t txstat; 1890 int cons; 1891 1892 cons = sc->rl_ldata.rl_tx_considx; 1893 if (cons == sc->rl_ldata.rl_tx_prodidx) 1894 return; 1895 1896 ifp = sc->rl_ifp; 1897 /* Invalidate the TX descriptor list */ 1898 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1899 sc->rl_ldata.rl_tx_list_map, 1900 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1901 1902 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1903 cons = RL_TX_DESC_NXT(sc, cons)) { 1904 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1905 if (txstat & RL_TDESC_STAT_OWN) 1906 break; 1907 /* 1908 * We only stash mbufs in the last descriptor 1909 * in a fragment chain, which also happens to 1910 * be the only place where the TX status bits 1911 * are valid. 1912 */ 1913 if (txstat & RL_TDESC_CMD_EOF) { 1914 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1915 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1916 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1917 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1918 txd->tx_dmamap); 1919 KASSERT(txd->tx_m != NULL, 1920 ("%s: freeing NULL mbufs!", __func__)); 1921 m_freem(txd->tx_m); 1922 txd->tx_m = NULL; 1923 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1924 RL_TDESC_STAT_COLCNT)) 1925 ifp->if_collisions++; 1926 if (txstat & RL_TDESC_STAT_TXERRSUM) 1927 ifp->if_oerrors++; 1928 else 1929 ifp->if_opackets++; 1930 } 1931 sc->rl_ldata.rl_tx_free++; 1932 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1933 } 1934 sc->rl_ldata.rl_tx_considx = cons; 1935 1936 /* No changes made to the TX ring, so no flush needed */ 1937 1938 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1939 /* 1940 * Some chips will ignore a second TX request issued 1941 * while an existing transmission is in progress. If 1942 * the transmitter goes idle but there are still 1943 * packets waiting to be sent, we need to restart the 1944 * channel here to flush them out. This only seems to 1945 * be required with the PCIe devices. 1946 */ 1947 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1948 1949#ifdef RE_TX_MODERATION 1950 /* 1951 * If not all descriptors have been reaped yet, reload 1952 * the timer so that we will eventually get another 1953 * interrupt that will cause us to re-enter this routine. 1954 * This is done in case the transmitter has gone idle. 1955 */ 1956 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1957#endif 1958 } else 1959 sc->rl_watchdog_timer = 0; 1960} 1961 1962static void 1963re_tick(xsc) 1964 void *xsc; 1965{ 1966 struct rl_softc *sc; 1967 struct mii_data *mii; 1968 struct ifnet *ifp; 1969 1970 sc = xsc; 1971 ifp = sc->rl_ifp; 1972 1973 RL_LOCK_ASSERT(sc); 1974 1975 re_watchdog(sc); 1976 1977 mii = device_get_softc(sc->rl_miibus); 1978 mii_tick(mii); 1979 if ((sc->rl_flags & RL_FLAG_LINK) != 0) { 1980 if (!(mii->mii_media_status & IFM_ACTIVE)) 1981 sc->rl_flags &= ~RL_FLAG_LINK; 1982 } else { 1983 if (mii->mii_media_status & IFM_ACTIVE && 1984 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1985 sc->rl_flags |= RL_FLAG_LINK; 1986 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1987 taskqueue_enqueue_fast(taskqueue_fast, 1988 &sc->rl_txtask); 1989 } 1990 } 1991 1992 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1993} 1994 1995#ifdef DEVICE_POLLING 1996static void 1997re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1998{ 1999 struct rl_softc *sc = ifp->if_softc; 2000 2001 RL_LOCK(sc); 2002 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2003 re_poll_locked(ifp, cmd, count); 2004 RL_UNLOCK(sc); 2005} 2006 2007static void 2008re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2009{ 2010 struct rl_softc *sc = ifp->if_softc; 2011 2012 RL_LOCK_ASSERT(sc); 2013 2014 sc->rxcycles = count; 2015 re_rxeof(sc); 2016 re_txeof(sc); 2017 2018 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2019 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2020 2021 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2022 u_int16_t status; 2023 2024 status = CSR_READ_2(sc, RL_ISR); 2025 if (status == 0xffff) 2026 return; 2027 if (status) 2028 CSR_WRITE_2(sc, RL_ISR, status); 2029 2030 /* 2031 * XXX check behaviour on receiver stalls. 2032 */ 2033 2034 if (status & RL_ISR_SYSTEM_ERR) { 2035 re_reset(sc); 2036 re_init_locked(sc); 2037 } 2038 } 2039} 2040#endif /* DEVICE_POLLING */ 2041 2042static int 2043re_intr(arg) 2044 void *arg; 2045{ 2046 struct rl_softc *sc; 2047 uint16_t status; 2048 2049 sc = arg; 2050 2051 status = CSR_READ_2(sc, RL_ISR); 2052 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2053 return (FILTER_STRAY); 2054 CSR_WRITE_2(sc, RL_IMR, 0); 2055 2056 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2057 2058 return (FILTER_HANDLED); 2059} 2060 2061static void 2062re_int_task(arg, npending) 2063 void *arg; 2064 int npending; 2065{ 2066 struct rl_softc *sc; 2067 struct ifnet *ifp; 2068 u_int16_t status; 2069 int rval = 0; 2070 2071 sc = arg; 2072 ifp = sc->rl_ifp; 2073 2074 RL_LOCK(sc); 2075 2076 status = CSR_READ_2(sc, RL_ISR); 2077 CSR_WRITE_2(sc, RL_ISR, status); 2078 2079 if (sc->suspended || 2080 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2081 RL_UNLOCK(sc); 2082 return; 2083 } 2084 2085#ifdef DEVICE_POLLING 2086 if (ifp->if_capenable & IFCAP_POLLING) { 2087 RL_UNLOCK(sc); 2088 return; 2089 } 2090#endif 2091 2092 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2093 rval = re_rxeof(sc); 2094 2095#ifdef RE_TX_MODERATION 2096 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2097#else 2098 if (status & (RL_ISR_TX_OK| 2099#endif 2100 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2101 re_txeof(sc); 2102 2103 if (status & RL_ISR_SYSTEM_ERR) { 2104 re_reset(sc); 2105 re_init_locked(sc); 2106 } 2107 2108 if (status & RL_ISR_LINKCHG) { 2109 callout_stop(&sc->rl_stat_callout); 2110 re_tick(sc); 2111 } 2112 2113 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2114 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2115 2116 RL_UNLOCK(sc); 2117 2118 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2119 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2120 return; 2121 } 2122 2123 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2124 2125 return; 2126} 2127 2128static int 2129re_encap(sc, m_head) 2130 struct rl_softc *sc; 2131 struct mbuf **m_head; 2132{ 2133 struct rl_txdesc *txd, *txd_last; 2134 bus_dma_segment_t segs[RL_NTXSEGS]; 2135 bus_dmamap_t map; 2136 struct mbuf *m_new; 2137 struct rl_desc *desc; 2138 int nsegs, prod; 2139 int i, error, ei, si; 2140 int padlen; 2141 uint32_t cmdstat, csum_flags, vlanctl; 2142 2143 RL_LOCK_ASSERT(sc); 2144 M_ASSERTPKTHDR((*m_head)); 2145 2146 /* 2147 * With some of the RealTek chips, using the checksum offload 2148 * support in conjunction with the autopadding feature results 2149 * in the transmission of corrupt frames. For example, if we 2150 * need to send a really small IP fragment that's less than 60 2151 * bytes in size, and IP header checksumming is enabled, the 2152 * resulting ethernet frame that appears on the wire will 2153 * have garbled payload. To work around this, if TX IP checksum 2154 * offload is enabled, we always manually pad short frames out 2155 * to the minimum ethernet frame size. 2156 */ 2157 if ((*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2158 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2159 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2160 if (M_WRITABLE(*m_head) == 0) { 2161 /* Get a writable copy. */ 2162 m_new = m_dup(*m_head, M_DONTWAIT); 2163 m_freem(*m_head); 2164 if (m_new == NULL) { 2165 *m_head = NULL; 2166 return (ENOBUFS); 2167 } 2168 *m_head = m_new; 2169 } 2170 if ((*m_head)->m_next != NULL || 2171 M_TRAILINGSPACE(*m_head) < padlen) { 2172 m_new = m_defrag(*m_head, M_DONTWAIT); 2173 if (m_new == NULL) { 2174 m_freem(*m_head); 2175 *m_head = NULL; 2176 return (ENOBUFS); 2177 } 2178 } else 2179 m_new = *m_head; 2180 2181 /* 2182 * Manually pad short frames, and zero the pad space 2183 * to avoid leaking data. 2184 */ 2185 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2186 m_new->m_pkthdr.len += padlen; 2187 m_new->m_len = m_new->m_pkthdr.len; 2188 *m_head = m_new; 2189 } 2190 2191 prod = sc->rl_ldata.rl_tx_prodidx; 2192 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2193 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2194 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2195 if (error == EFBIG) { 2196 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2197 if (m_new == NULL) { 2198 m_freem(*m_head); 2199 *m_head = NULL; 2200 return (ENOBUFS); 2201 } 2202 *m_head = m_new; 2203 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2204 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2205 if (error != 0) { 2206 m_freem(*m_head); 2207 *m_head = NULL; 2208 return (error); 2209 } 2210 } else if (error != 0) 2211 return (error); 2212 if (nsegs == 0) { 2213 m_freem(*m_head); 2214 *m_head = NULL; 2215 return (EIO); 2216 } 2217 2218 /* Check for number of available descriptors. */ 2219 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2220 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2221 return (ENOBUFS); 2222 } 2223 2224 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2225 BUS_DMASYNC_PREWRITE); 2226 2227 /* 2228 * Set up checksum offload. Note: checksum offload bits must 2229 * appear in all descriptors of a multi-descriptor transmit 2230 * attempt. This is according to testing done with an 8169 2231 * chip. This is a requirement. 2232 */ 2233 csum_flags = 0; 2234 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2235 csum_flags = RL_TDESC_CMD_LGSEND | 2236 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2237 RL_TDESC_CMD_MSSVAL_SHIFT); 2238 else { 2239 /* 2240 * Unconditionally enable IP checksum if TCP or UDP 2241 * checksum is required. Otherwise, TCP/UDP checksum 2242 * does't make effects. 2243 */ 2244 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2245 csum_flags |= RL_TDESC_CMD_IPCSUM; 2246 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2247 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2248 if (((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2249 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2250 } 2251 } 2252 2253 /* 2254 * Set up hardware VLAN tagging. Note: vlan tag info must 2255 * appear in all descriptors of a multi-descriptor 2256 * transmission attempt. 2257 */ 2258 vlanctl = 0; 2259 if ((*m_head)->m_flags & M_VLANTAG) 2260 vlanctl = 2261 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2262 RL_TDESC_VLANCTL_TAG); 2263 2264 si = prod; 2265 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2266 desc = &sc->rl_ldata.rl_tx_list[prod]; 2267 desc->rl_vlanctl = vlanctl; 2268 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2269 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2270 cmdstat = segs[i].ds_len; 2271 if (i != 0) 2272 cmdstat |= RL_TDESC_CMD_OWN; 2273 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2274 cmdstat |= RL_TDESC_CMD_EOR; 2275 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2276 sc->rl_ldata.rl_tx_free--; 2277 } 2278 /* Update producer index. */ 2279 sc->rl_ldata.rl_tx_prodidx = prod; 2280 2281 /* Set EOF on the last descriptor. */ 2282 ei = RL_TX_DESC_PRV(sc, prod); 2283 desc = &sc->rl_ldata.rl_tx_list[ei]; 2284 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2285 2286 desc = &sc->rl_ldata.rl_tx_list[si]; 2287 /* Set SOF and transfer ownership of packet to the chip. */ 2288 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2289 2290 /* 2291 * Insure that the map for this transmission 2292 * is placed at the array index of the last descriptor 2293 * in this chain. (Swap last and first dmamaps.) 2294 */ 2295 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2296 map = txd->tx_dmamap; 2297 txd->tx_dmamap = txd_last->tx_dmamap; 2298 txd_last->tx_dmamap = map; 2299 txd_last->tx_m = *m_head; 2300 2301 return (0); 2302} 2303 2304static void 2305re_tx_task(arg, npending) 2306 void *arg; 2307 int npending; 2308{ 2309 struct ifnet *ifp; 2310 2311 ifp = arg; 2312 re_start(ifp); 2313 2314 return; 2315} 2316 2317/* 2318 * Main transmit routine for C+ and gigE NICs. 2319 */ 2320static void 2321re_start(ifp) 2322 struct ifnet *ifp; 2323{ 2324 struct rl_softc *sc; 2325 struct mbuf *m_head; 2326 int queued; 2327 2328 sc = ifp->if_softc; 2329 2330 RL_LOCK(sc); 2331 2332 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2333 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2334 RL_UNLOCK(sc); 2335 return; 2336 } 2337 2338 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2339 sc->rl_ldata.rl_tx_free > 1;) { 2340 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2341 if (m_head == NULL) 2342 break; 2343 2344 if (re_encap(sc, &m_head) != 0) { 2345 if (m_head == NULL) 2346 break; 2347 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2348 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2349 break; 2350 } 2351 2352 /* 2353 * If there's a BPF listener, bounce a copy of this frame 2354 * to him. 2355 */ 2356 ETHER_BPF_MTAP(ifp, m_head); 2357 2358 queued++; 2359 } 2360 2361 if (queued == 0) { 2362#ifdef RE_TX_MODERATION 2363 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2364 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2365#endif 2366 RL_UNLOCK(sc); 2367 return; 2368 } 2369 2370 /* Flush the TX descriptors */ 2371 2372 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2373 sc->rl_ldata.rl_tx_list_map, 2374 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2375 2376 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2377 2378#ifdef RE_TX_MODERATION 2379 /* 2380 * Use the countdown timer for interrupt moderation. 2381 * 'TX done' interrupts are disabled. Instead, we reset the 2382 * countdown timer, which will begin counting until it hits 2383 * the value in the TIMERINT register, and then trigger an 2384 * interrupt. Each time we write to the TIMERCNT register, 2385 * the timer count is reset to 0. 2386 */ 2387 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2388#endif 2389 2390 /* 2391 * Set a timeout in case the chip goes out to lunch. 2392 */ 2393 sc->rl_watchdog_timer = 5; 2394 2395 RL_UNLOCK(sc); 2396 2397 return; 2398} 2399 2400static void 2401re_init(xsc) 2402 void *xsc; 2403{ 2404 struct rl_softc *sc = xsc; 2405 2406 RL_LOCK(sc); 2407 re_init_locked(sc); 2408 RL_UNLOCK(sc); 2409} 2410 2411static void 2412re_init_locked(sc) 2413 struct rl_softc *sc; 2414{ 2415 struct ifnet *ifp = sc->rl_ifp; 2416 struct mii_data *mii; 2417 u_int32_t rxcfg = 0; 2418 uint16_t cfg; 2419 union { 2420 uint32_t align_dummy; 2421 u_char eaddr[ETHER_ADDR_LEN]; 2422 } eaddr; 2423 2424 RL_LOCK_ASSERT(sc); 2425 2426 mii = device_get_softc(sc->rl_miibus); 2427 2428 /* 2429 * Cancel pending I/O and free all RX/TX buffers. 2430 */ 2431 re_stop(sc); 2432 2433 /* 2434 * Enable C+ RX and TX mode, as well as VLAN stripping and 2435 * RX checksum offload. We must configure the C+ register 2436 * before all others. 2437 */ 2438 cfg = RL_CPLUSCMD_PCI_MRW; 2439 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2440 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2441 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2442 cfg |= RL_CPLUSCMD_VLANSTRIP; 2443 CSR_WRITE_2(sc, RL_CPLUS_CMD, 2444 cfg | RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB); 2445 2446 /* 2447 * Init our MAC address. Even though the chipset 2448 * documentation doesn't mention it, we need to enter "Config 2449 * register write enable" mode to modify the ID registers. 2450 */ 2451 /* Copy MAC address on stack to align. */ 2452 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2453 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2454 CSR_WRITE_4(sc, RL_IDR0, 2455 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2456 CSR_WRITE_4(sc, RL_IDR4, 2457 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2458 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2459 2460 /* 2461 * For C+ mode, initialize the RX descriptors and mbufs. 2462 */ 2463 re_rx_list_init(sc); 2464 re_tx_list_init(sc); 2465 2466 /* 2467 * Load the addresses of the RX and TX lists into the chip. 2468 */ 2469 2470 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2471 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2472 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2473 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2474 2475 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2476 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2477 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2478 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2479 2480 /* 2481 * Enable transmit and receive. 2482 */ 2483 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2484 2485 /* 2486 * Set the initial TX and RX configuration. 2487 */ 2488 if (sc->rl_testmode) { 2489 if (sc->rl_type == RL_8169) 2490 CSR_WRITE_4(sc, RL_TXCFG, 2491 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2492 else 2493 CSR_WRITE_4(sc, RL_TXCFG, 2494 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2495 } else 2496 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2497 2498 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2499 2500 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2501 2502 /* Set the individual bit to receive frames for this host only. */ 2503 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2504 rxcfg |= RL_RXCFG_RX_INDIV; 2505 2506 /* If we want promiscuous mode, set the allframes bit. */ 2507 if (ifp->if_flags & IFF_PROMISC) 2508 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2509 else 2510 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2511 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2512 2513 /* 2514 * Set capture broadcast bit to capture broadcast frames. 2515 */ 2516 if (ifp->if_flags & IFF_BROADCAST) 2517 rxcfg |= RL_RXCFG_RX_BROAD; 2518 else 2519 rxcfg &= ~RL_RXCFG_RX_BROAD; 2520 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2521 2522 /* 2523 * Program the multicast filter, if necessary. 2524 */ 2525 re_setmulti(sc); 2526 2527#ifdef DEVICE_POLLING 2528 /* 2529 * Disable interrupts if we are polling. 2530 */ 2531 if (ifp->if_capenable & IFCAP_POLLING) 2532 CSR_WRITE_2(sc, RL_IMR, 0); 2533 else /* otherwise ... */ 2534#endif 2535 2536 /* 2537 * Enable interrupts. 2538 */ 2539 if (sc->rl_testmode) 2540 CSR_WRITE_2(sc, RL_IMR, 0); 2541 else 2542 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2543 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2544 2545 /* Set initial TX threshold */ 2546 sc->rl_txthresh = RL_TX_THRESH_INIT; 2547 2548 /* Start RX/TX process. */ 2549 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2550#ifdef notdef 2551 /* Enable receiver and transmitter. */ 2552 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2553#endif 2554 2555#ifdef RE_TX_MODERATION 2556 /* 2557 * Initialize the timer interrupt register so that 2558 * a timer interrupt will be generated once the timer 2559 * reaches a certain number of ticks. The timer is 2560 * reloaded on each transmit. This gives us TX interrupt 2561 * moderation, which dramatically improves TX frame rate. 2562 */ 2563 if (sc->rl_type == RL_8169) 2564 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2565 else 2566 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2567#endif 2568 2569 /* 2570 * For 8169 gigE NICs, set the max allowed RX packet 2571 * size so we can receive jumbo frames. 2572 */ 2573 if (sc->rl_type == RL_8169) 2574 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2575 2576 if (sc->rl_testmode) 2577 return; 2578 2579 mii_mediachg(mii); 2580 2581 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2582 2583 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2584 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2585 2586 sc->rl_flags &= ~RL_FLAG_LINK; 2587 sc->rl_watchdog_timer = 0; 2588 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2589} 2590 2591/* 2592 * Set media options. 2593 */ 2594static int 2595re_ifmedia_upd(ifp) 2596 struct ifnet *ifp; 2597{ 2598 struct rl_softc *sc; 2599 struct mii_data *mii; 2600 2601 sc = ifp->if_softc; 2602 mii = device_get_softc(sc->rl_miibus); 2603 RL_LOCK(sc); 2604 mii_mediachg(mii); 2605 RL_UNLOCK(sc); 2606 2607 return (0); 2608} 2609 2610/* 2611 * Report current media status. 2612 */ 2613static void 2614re_ifmedia_sts(ifp, ifmr) 2615 struct ifnet *ifp; 2616 struct ifmediareq *ifmr; 2617{ 2618 struct rl_softc *sc; 2619 struct mii_data *mii; 2620 2621 sc = ifp->if_softc; 2622 mii = device_get_softc(sc->rl_miibus); 2623 2624 RL_LOCK(sc); 2625 mii_pollstat(mii); 2626 RL_UNLOCK(sc); 2627 ifmr->ifm_active = mii->mii_media_active; 2628 ifmr->ifm_status = mii->mii_media_status; 2629} 2630 2631static int 2632re_ioctl(ifp, command, data) 2633 struct ifnet *ifp; 2634 u_long command; 2635 caddr_t data; 2636{ 2637 struct rl_softc *sc = ifp->if_softc; 2638 struct ifreq *ifr = (struct ifreq *) data; 2639 struct mii_data *mii; 2640 int error = 0; 2641 2642 switch (command) { 2643 case SIOCSIFMTU: 2644 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2645 error = EINVAL; 2646 break; 2647 } 2648 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2649 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2650 error = EINVAL; 2651 break; 2652 } 2653 RL_LOCK(sc); 2654 if (ifp->if_mtu != ifr->ifr_mtu) 2655 ifp->if_mtu = ifr->ifr_mtu; 2656 RL_UNLOCK(sc); 2657 break; 2658 case SIOCSIFFLAGS: 2659 RL_LOCK(sc); 2660 if ((ifp->if_flags & IFF_UP) != 0) { 2661 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2662 if (((ifp->if_flags ^ sc->rl_if_flags) 2663 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2664 re_setmulti(sc); 2665 } else 2666 re_init_locked(sc); 2667 } else { 2668 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2669 re_stop(sc); 2670 } 2671 sc->rl_if_flags = ifp->if_flags; 2672 RL_UNLOCK(sc); 2673 break; 2674 case SIOCADDMULTI: 2675 case SIOCDELMULTI: 2676 RL_LOCK(sc); 2677 re_setmulti(sc); 2678 RL_UNLOCK(sc); 2679 break; 2680 case SIOCGIFMEDIA: 2681 case SIOCSIFMEDIA: 2682 mii = device_get_softc(sc->rl_miibus); 2683 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2684 break; 2685 case SIOCSIFCAP: 2686 { 2687 int mask, reinit; 2688 2689 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2690 reinit = 0; 2691#ifdef DEVICE_POLLING 2692 if (mask & IFCAP_POLLING) { 2693 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2694 error = ether_poll_register(re_poll, ifp); 2695 if (error) 2696 return(error); 2697 RL_LOCK(sc); 2698 /* Disable interrupts */ 2699 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2700 ifp->if_capenable |= IFCAP_POLLING; 2701 RL_UNLOCK(sc); 2702 } else { 2703 error = ether_poll_deregister(ifp); 2704 /* Enable interrupts. */ 2705 RL_LOCK(sc); 2706 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2707 ifp->if_capenable &= ~IFCAP_POLLING; 2708 RL_UNLOCK(sc); 2709 } 2710 } 2711#endif /* DEVICE_POLLING */ 2712 if (mask & IFCAP_HWCSUM) { 2713 ifp->if_capenable ^= IFCAP_HWCSUM; 2714 if (ifp->if_capenable & IFCAP_TXCSUM) 2715 ifp->if_hwassist |= RE_CSUM_FEATURES; 2716 else 2717 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2718 reinit = 1; 2719 } 2720 if (mask & IFCAP_VLAN_HWTAGGING) { 2721 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2722 reinit = 1; 2723 } 2724 if (mask & IFCAP_TSO4) { 2725 ifp->if_capenable ^= IFCAP_TSO4; 2726 if ((IFCAP_TSO4 & ifp->if_capenable) && 2727 (IFCAP_TSO4 & ifp->if_capabilities)) 2728 ifp->if_hwassist |= CSUM_TSO; 2729 else 2730 ifp->if_hwassist &= ~CSUM_TSO; 2731 } 2732 if ((mask & IFCAP_WOL) != 0 && 2733 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2734 if ((mask & IFCAP_WOL_UCAST) != 0) 2735 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2736 if ((mask & IFCAP_WOL_MCAST) != 0) 2737 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2738 if ((mask & IFCAP_WOL_MAGIC) != 0) 2739 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2740 } 2741 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2742 re_init(sc); 2743 VLAN_CAPABILITIES(ifp); 2744 } 2745 break; 2746 default: 2747 error = ether_ioctl(ifp, command, data); 2748 break; 2749 } 2750 2751 return (error); 2752} 2753 2754static void 2755re_watchdog(sc) 2756 struct rl_softc *sc; 2757{ 2758 2759 RL_LOCK_ASSERT(sc); 2760 2761 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2762 return; 2763 2764 device_printf(sc->rl_dev, "watchdog timeout\n"); 2765 sc->rl_ifp->if_oerrors++; 2766 2767 re_txeof(sc); 2768 re_rxeof(sc); 2769 re_init_locked(sc); 2770} 2771 2772/* 2773 * Stop the adapter and free any mbufs allocated to the 2774 * RX and TX lists. 2775 */ 2776static void 2777re_stop(sc) 2778 struct rl_softc *sc; 2779{ 2780 register int i; 2781 struct ifnet *ifp; 2782 struct rl_txdesc *txd; 2783 struct rl_rxdesc *rxd; 2784 2785 RL_LOCK_ASSERT(sc); 2786 2787 ifp = sc->rl_ifp; 2788 2789 sc->rl_watchdog_timer = 0; 2790 callout_stop(&sc->rl_stat_callout); 2791 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2792 2793 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2794 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2795 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2796 2797 if (sc->rl_head != NULL) { 2798 m_freem(sc->rl_head); 2799 sc->rl_head = sc->rl_tail = NULL; 2800 } 2801 2802 /* Free the TX list buffers. */ 2803 2804 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2805 txd = &sc->rl_ldata.rl_tx_desc[i]; 2806 if (txd->tx_m != NULL) { 2807 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2808 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2809 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2810 txd->tx_dmamap); 2811 m_freem(txd->tx_m); 2812 txd->tx_m = NULL; 2813 } 2814 } 2815 2816 /* Free the RX list buffers. */ 2817 2818 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2819 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2820 if (rxd->rx_m != NULL) { 2821 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2822 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2823 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2824 rxd->rx_dmamap); 2825 m_freem(rxd->rx_m); 2826 rxd->rx_m = NULL; 2827 } 2828 } 2829} 2830 2831/* 2832 * Device suspend routine. Stop the interface and save some PCI 2833 * settings in case the BIOS doesn't restore them properly on 2834 * resume. 2835 */ 2836static int 2837re_suspend(dev) 2838 device_t dev; 2839{ 2840 struct rl_softc *sc; 2841 2842 sc = device_get_softc(dev); 2843 2844 RL_LOCK(sc); 2845 re_stop(sc); 2846 re_setwol(sc); 2847 sc->suspended = 1; 2848 RL_UNLOCK(sc); 2849 2850 return (0); 2851} 2852 2853/* 2854 * Device resume routine. Restore some PCI settings in case the BIOS 2855 * doesn't, re-enable busmastering, and restart the interface if 2856 * appropriate. 2857 */ 2858static int 2859re_resume(dev) 2860 device_t dev; 2861{ 2862 struct rl_softc *sc; 2863 struct ifnet *ifp; 2864 2865 sc = device_get_softc(dev); 2866 2867 RL_LOCK(sc); 2868 2869 ifp = sc->rl_ifp; 2870 2871 /* reinitialize interface if necessary */ 2872 if (ifp->if_flags & IFF_UP) 2873 re_init_locked(sc); 2874 2875 /* 2876 * Clear WOL matching such that normal Rx filtering 2877 * wouldn't interfere with WOL patterns. 2878 */ 2879 re_clrwol(sc); 2880 sc->suspended = 0; 2881 RL_UNLOCK(sc); 2882 2883 return (0); 2884} 2885 2886/* 2887 * Stop all chip I/O so that the kernel's probe routines don't 2888 * get confused by errant DMAs when rebooting. 2889 */ 2890static int 2891re_shutdown(dev) 2892 device_t dev; 2893{ 2894 struct rl_softc *sc; 2895 2896 sc = device_get_softc(dev); 2897 2898 RL_LOCK(sc); 2899 re_stop(sc); 2900 /* 2901 * Mark interface as down since otherwise we will panic if 2902 * interrupt comes in later on, which can happen in some 2903 * cases. 2904 */ 2905 sc->rl_ifp->if_flags &= ~IFF_UP; 2906 re_setwol(sc); 2907 RL_UNLOCK(sc); 2908 2909 return (0); 2910} 2911 2912static void 2913re_setwol(sc) 2914 struct rl_softc *sc; 2915{ 2916 struct ifnet *ifp; 2917 int pmc; 2918 uint16_t pmstat; 2919 uint8_t v; 2920 2921 RL_LOCK_ASSERT(sc); 2922 2923 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2924 return; 2925 2926 ifp = sc->rl_ifp; 2927 /* Enable config register write. */ 2928 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2929 2930 /* Enable PME. */ 2931 v = CSR_READ_1(sc, RL_CFG1); 2932 v &= ~RL_CFG1_PME; 2933 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2934 v |= RL_CFG1_PME; 2935 CSR_WRITE_1(sc, RL_CFG1, v); 2936 2937 v = CSR_READ_1(sc, RL_CFG3); 2938 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2939 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2940 v |= RL_CFG3_WOL_MAGIC; 2941 CSR_WRITE_1(sc, RL_CFG3, v); 2942 2943 /* Config register write done. */ 2944 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2945 2946 v = CSR_READ_1(sc, RL_CFG5); 2947 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2948 v &= ~RL_CFG5_WOL_LANWAKE; 2949 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2950 v |= RL_CFG5_WOL_UCAST; 2951 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2952 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 2953 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2954 v |= RL_CFG5_WOL_LANWAKE; 2955 CSR_WRITE_1(sc, RL_CFG5, v); 2956 2957 /* 2958 * It seems that hardware resets its link speed to 100Mbps in 2959 * power down mode so switching to 100Mbps in driver is not 2960 * needed. 2961 */ 2962 2963 /* Request PME if WOL is requested. */ 2964 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 2965 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2966 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2967 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2968 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2969} 2970 2971static void 2972re_clrwol(sc) 2973 struct rl_softc *sc; 2974{ 2975 int pmc; 2976 uint8_t v; 2977 2978 RL_LOCK_ASSERT(sc); 2979 2980 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2981 return; 2982 2983 /* Enable config register write. */ 2984 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2985 2986 v = CSR_READ_1(sc, RL_CFG3); 2987 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2988 CSR_WRITE_1(sc, RL_CFG3, v); 2989 2990 /* Config register write done. */ 2991 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2992 2993 v = CSR_READ_1(sc, RL_CFG5); 2994 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2995 v &= ~RL_CFG5_WOL_LANWAKE; 2996 CSR_WRITE_1(sc, RL_CFG5, v); 2997} 2998