if_re.c revision 180173
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 180173 2008-07-02 06:41:46Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* Tunables. */ 159static int msi_disable = 1; 160TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164/* 165 * Various supported device vendors/types and their names. 166 */ 167static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8111B PCIe Gigabit Ethernet" }, 176 { RT_VENDORID, RT_DEVICEID_8169, 0, 177 "RealTek 8169/8169S/8169SB/8110S/8110SB Gigabit Ethernet" }, 178 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 179 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 180 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 181 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 182 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 183 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 184 { USR_VENDORID, USR_DEVICEID_997902, 0, 185 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 186}; 187 188static struct rl_hwrev re_hwrevs[] = { 189 { RL_HWREV_8139, RL_8139, "" }, 190 { RL_HWREV_8139A, RL_8139, "A" }, 191 { RL_HWREV_8139AG, RL_8139, "A-G" }, 192 { RL_HWREV_8139B, RL_8139, "B" }, 193 { RL_HWREV_8130, RL_8139, "8130" }, 194 { RL_HWREV_8139C, RL_8139, "C" }, 195 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 196 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 197 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 198 { RL_HWREV_8169, RL_8169, "8169"}, 199 { RL_HWREV_8169S, RL_8169, "8169S"}, 200 { RL_HWREV_8110S, RL_8169, "8110S"}, 201 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 202 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 203 { RL_HWREV_8100, RL_8139, "8100"}, 204 { RL_HWREV_8101, RL_8139, "8101"}, 205 { RL_HWREV_8100E, RL_8169, "8100E"}, 206 { RL_HWREV_8101E, RL_8169, "8101E"}, 207 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 208 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 209 { 0, 0, NULL } 210}; 211 212static int re_probe (device_t); 213static int re_attach (device_t); 214static int re_detach (device_t); 215 216static int re_encap (struct rl_softc *, struct mbuf **); 217 218static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 219static int re_allocmem (device_t, struct rl_softc *); 220static __inline void re_discard_rxbuf 221 (struct rl_softc *, int); 222static int re_newbuf (struct rl_softc *, int); 223static int re_rx_list_init (struct rl_softc *); 224static int re_tx_list_init (struct rl_softc *); 225#ifdef RE_FIXUP_RX 226static __inline void re_fixup_rx 227 (struct mbuf *); 228#endif 229static int re_rxeof (struct rl_softc *); 230static void re_txeof (struct rl_softc *); 231#ifdef DEVICE_POLLING 232static void re_poll (struct ifnet *, enum poll_cmd, int); 233static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 234#endif 235static int re_intr (void *); 236static void re_tick (void *); 237static void re_tx_task (void *, int); 238static void re_int_task (void *, int); 239static void re_start (struct ifnet *); 240static int re_ioctl (struct ifnet *, u_long, caddr_t); 241static void re_init (void *); 242static void re_init_locked (struct rl_softc *); 243static void re_stop (struct rl_softc *); 244static void re_watchdog (struct rl_softc *); 245static int re_suspend (device_t); 246static int re_resume (device_t); 247static int re_shutdown (device_t); 248static int re_ifmedia_upd (struct ifnet *); 249static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 250 251static void re_eeprom_putbyte (struct rl_softc *, int); 252static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 253static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 254static int re_gmii_readreg (device_t, int, int); 255static int re_gmii_writereg (device_t, int, int, int); 256 257static int re_miibus_readreg (device_t, int, int); 258static int re_miibus_writereg (device_t, int, int, int); 259static void re_miibus_statchg (device_t); 260 261static void re_setmulti (struct rl_softc *); 262static void re_reset (struct rl_softc *); 263static void re_setwol (struct rl_softc *); 264static void re_clrwol (struct rl_softc *); 265 266#ifdef RE_DIAG 267static int re_diag (struct rl_softc *); 268#endif 269 270static device_method_t re_methods[] = { 271 /* Device interface */ 272 DEVMETHOD(device_probe, re_probe), 273 DEVMETHOD(device_attach, re_attach), 274 DEVMETHOD(device_detach, re_detach), 275 DEVMETHOD(device_suspend, re_suspend), 276 DEVMETHOD(device_resume, re_resume), 277 DEVMETHOD(device_shutdown, re_shutdown), 278 279 /* bus interface */ 280 DEVMETHOD(bus_print_child, bus_generic_print_child), 281 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 282 283 /* MII interface */ 284 DEVMETHOD(miibus_readreg, re_miibus_readreg), 285 DEVMETHOD(miibus_writereg, re_miibus_writereg), 286 DEVMETHOD(miibus_statchg, re_miibus_statchg), 287 288 { 0, 0 } 289}; 290 291static driver_t re_driver = { 292 "re", 293 re_methods, 294 sizeof(struct rl_softc) 295}; 296 297static devclass_t re_devclass; 298 299DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 300DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 301DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 302 303#define EE_SET(x) \ 304 CSR_WRITE_1(sc, RL_EECMD, \ 305 CSR_READ_1(sc, RL_EECMD) | x) 306 307#define EE_CLR(x) \ 308 CSR_WRITE_1(sc, RL_EECMD, \ 309 CSR_READ_1(sc, RL_EECMD) & ~x) 310 311/* 312 * Send a read command and address to the EEPROM, check for ACK. 313 */ 314static void 315re_eeprom_putbyte(sc, addr) 316 struct rl_softc *sc; 317 int addr; 318{ 319 register int d, i; 320 321 d = addr | (RL_9346_READ << sc->rl_eewidth); 322 323 /* 324 * Feed in each bit and strobe the clock. 325 */ 326 327 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 328 if (d & i) { 329 EE_SET(RL_EE_DATAIN); 330 } else { 331 EE_CLR(RL_EE_DATAIN); 332 } 333 DELAY(100); 334 EE_SET(RL_EE_CLK); 335 DELAY(150); 336 EE_CLR(RL_EE_CLK); 337 DELAY(100); 338 } 339 340 return; 341} 342 343/* 344 * Read a word of data stored in the EEPROM at address 'addr.' 345 */ 346static void 347re_eeprom_getword(sc, addr, dest) 348 struct rl_softc *sc; 349 int addr; 350 u_int16_t *dest; 351{ 352 register int i; 353 u_int16_t word = 0; 354 355 /* 356 * Send address of word we want to read. 357 */ 358 re_eeprom_putbyte(sc, addr); 359 360 /* 361 * Start reading bits from EEPROM. 362 */ 363 for (i = 0x8000; i; i >>= 1) { 364 EE_SET(RL_EE_CLK); 365 DELAY(100); 366 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 367 word |= i; 368 EE_CLR(RL_EE_CLK); 369 DELAY(100); 370 } 371 372 *dest = word; 373 374 return; 375} 376 377/* 378 * Read a sequence of words from the EEPROM. 379 */ 380static void 381re_read_eeprom(sc, dest, off, cnt) 382 struct rl_softc *sc; 383 caddr_t dest; 384 int off; 385 int cnt; 386{ 387 int i; 388 u_int16_t word = 0, *ptr; 389 390 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 391 392 DELAY(100); 393 394 for (i = 0; i < cnt; i++) { 395 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 396 re_eeprom_getword(sc, off + i, &word); 397 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 398 ptr = (u_int16_t *)(dest + (i * 2)); 399 *ptr = word; 400 } 401 402 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 403 404 return; 405} 406 407static int 408re_gmii_readreg(dev, phy, reg) 409 device_t dev; 410 int phy, reg; 411{ 412 struct rl_softc *sc; 413 u_int32_t rval; 414 int i; 415 416 if (phy != 1) 417 return (0); 418 419 sc = device_get_softc(dev); 420 421 /* Let the rgephy driver read the GMEDIASTAT register */ 422 423 if (reg == RL_GMEDIASTAT) { 424 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 425 return (rval); 426 } 427 428 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 429 DELAY(1000); 430 431 for (i = 0; i < RL_TIMEOUT; i++) { 432 rval = CSR_READ_4(sc, RL_PHYAR); 433 if (rval & RL_PHYAR_BUSY) 434 break; 435 DELAY(100); 436 } 437 438 if (i == RL_TIMEOUT) { 439 device_printf(sc->rl_dev, "PHY read failed\n"); 440 return (0); 441 } 442 443 return (rval & RL_PHYAR_PHYDATA); 444} 445 446static int 447re_gmii_writereg(dev, phy, reg, data) 448 device_t dev; 449 int phy, reg, data; 450{ 451 struct rl_softc *sc; 452 u_int32_t rval; 453 int i; 454 455 sc = device_get_softc(dev); 456 457 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 458 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 459 DELAY(1000); 460 461 for (i = 0; i < RL_TIMEOUT; i++) { 462 rval = CSR_READ_4(sc, RL_PHYAR); 463 if (!(rval & RL_PHYAR_BUSY)) 464 break; 465 DELAY(100); 466 } 467 468 if (i == RL_TIMEOUT) { 469 device_printf(sc->rl_dev, "PHY write failed\n"); 470 return (0); 471 } 472 473 return (0); 474} 475 476static int 477re_miibus_readreg(dev, phy, reg) 478 device_t dev; 479 int phy, reg; 480{ 481 struct rl_softc *sc; 482 u_int16_t rval = 0; 483 u_int16_t re8139_reg = 0; 484 485 sc = device_get_softc(dev); 486 487 if (sc->rl_type == RL_8169) { 488 rval = re_gmii_readreg(dev, phy, reg); 489 return (rval); 490 } 491 492 /* Pretend the internal PHY is only at address 0 */ 493 if (phy) { 494 return (0); 495 } 496 switch (reg) { 497 case MII_BMCR: 498 re8139_reg = RL_BMCR; 499 break; 500 case MII_BMSR: 501 re8139_reg = RL_BMSR; 502 break; 503 case MII_ANAR: 504 re8139_reg = RL_ANAR; 505 break; 506 case MII_ANER: 507 re8139_reg = RL_ANER; 508 break; 509 case MII_ANLPAR: 510 re8139_reg = RL_LPAR; 511 break; 512 case MII_PHYIDR1: 513 case MII_PHYIDR2: 514 return (0); 515 /* 516 * Allow the rlphy driver to read the media status 517 * register. If we have a link partner which does not 518 * support NWAY, this is the register which will tell 519 * us the results of parallel detection. 520 */ 521 case RL_MEDIASTAT: 522 rval = CSR_READ_1(sc, RL_MEDIASTAT); 523 return (rval); 524 default: 525 device_printf(sc->rl_dev, "bad phy register\n"); 526 return (0); 527 } 528 rval = CSR_READ_2(sc, re8139_reg); 529 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 530 /* 8139C+ has different bit layout. */ 531 rval &= ~(BMCR_LOOP | BMCR_ISO); 532 } 533 return (rval); 534} 535 536static int 537re_miibus_writereg(dev, phy, reg, data) 538 device_t dev; 539 int phy, reg, data; 540{ 541 struct rl_softc *sc; 542 u_int16_t re8139_reg = 0; 543 int rval = 0; 544 545 sc = device_get_softc(dev); 546 547 if (sc->rl_type == RL_8169) { 548 rval = re_gmii_writereg(dev, phy, reg, data); 549 return (rval); 550 } 551 552 /* Pretend the internal PHY is only at address 0 */ 553 if (phy) 554 return (0); 555 556 switch (reg) { 557 case MII_BMCR: 558 re8139_reg = RL_BMCR; 559 if (sc->rl_type == RL_8139CPLUS) { 560 /* 8139C+ has different bit layout. */ 561 data &= ~(BMCR_LOOP | BMCR_ISO); 562 } 563 break; 564 case MII_BMSR: 565 re8139_reg = RL_BMSR; 566 break; 567 case MII_ANAR: 568 re8139_reg = RL_ANAR; 569 break; 570 case MII_ANER: 571 re8139_reg = RL_ANER; 572 break; 573 case MII_ANLPAR: 574 re8139_reg = RL_LPAR; 575 break; 576 case MII_PHYIDR1: 577 case MII_PHYIDR2: 578 return (0); 579 break; 580 default: 581 device_printf(sc->rl_dev, "bad phy register\n"); 582 return (0); 583 } 584 CSR_WRITE_2(sc, re8139_reg, data); 585 return (0); 586} 587 588static void 589re_miibus_statchg(dev) 590 device_t dev; 591{ 592 593} 594 595/* 596 * Program the 64-bit multicast hash filter. 597 */ 598static void 599re_setmulti(sc) 600 struct rl_softc *sc; 601{ 602 struct ifnet *ifp; 603 int h = 0; 604 u_int32_t hashes[2] = { 0, 0 }; 605 struct ifmultiaddr *ifma; 606 u_int32_t rxfilt; 607 int mcnt = 0; 608 609 RL_LOCK_ASSERT(sc); 610 611 ifp = sc->rl_ifp; 612 613 614 rxfilt = CSR_READ_4(sc, RL_RXCFG); 615 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 616 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 617 if (ifp->if_flags & IFF_PROMISC) 618 rxfilt |= RL_RXCFG_RX_ALLPHYS; 619 /* 620 * Unlike other hardwares, we have to explicitly set 621 * RL_RXCFG_RX_MULTI to receive multicast frames in 622 * promiscuous mode. 623 */ 624 rxfilt |= RL_RXCFG_RX_MULTI; 625 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 626 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 627 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 628 return; 629 } 630 631 /* first, zot all the existing hash bits */ 632 CSR_WRITE_4(sc, RL_MAR0, 0); 633 CSR_WRITE_4(sc, RL_MAR4, 0); 634 635 /* now program new ones */ 636 IF_ADDR_LOCK(ifp); 637 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 638 if (ifma->ifma_addr->sa_family != AF_LINK) 639 continue; 640 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 641 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 642 if (h < 32) 643 hashes[0] |= (1 << h); 644 else 645 hashes[1] |= (1 << (h - 32)); 646 mcnt++; 647 } 648 IF_ADDR_UNLOCK(ifp); 649 650 if (mcnt) 651 rxfilt |= RL_RXCFG_RX_MULTI; 652 else 653 rxfilt &= ~RL_RXCFG_RX_MULTI; 654 655 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 656 657 /* 658 * For some unfathomable reason, RealTek decided to reverse 659 * the order of the multicast hash registers in the PCI Express 660 * parts. This means we have to write the hash pattern in reverse 661 * order for those devices. 662 */ 663 664 if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) { 665 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 666 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 667 } else { 668 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 669 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 670 } 671} 672 673static void 674re_reset(sc) 675 struct rl_softc *sc; 676{ 677 register int i; 678 679 RL_LOCK_ASSERT(sc); 680 681 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 682 683 for (i = 0; i < RL_TIMEOUT; i++) { 684 DELAY(10); 685 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 686 break; 687 } 688 if (i == RL_TIMEOUT) 689 device_printf(sc->rl_dev, "reset never completed!\n"); 690 691 CSR_WRITE_1(sc, 0x82, 1); 692} 693 694#ifdef RE_DIAG 695 696/* 697 * The following routine is designed to test for a defect on some 698 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 699 * lines connected to the bus, however for a 32-bit only card, they 700 * should be pulled high. The result of this defect is that the 701 * NIC will not work right if you plug it into a 64-bit slot: DMA 702 * operations will be done with 64-bit transfers, which will fail 703 * because the 64-bit data lines aren't connected. 704 * 705 * There's no way to work around this (short of talking a soldering 706 * iron to the board), however we can detect it. The method we use 707 * here is to put the NIC into digital loopback mode, set the receiver 708 * to promiscuous mode, and then try to send a frame. We then compare 709 * the frame data we sent to what was received. If the data matches, 710 * then the NIC is working correctly, otherwise we know the user has 711 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 712 * slot. In the latter case, there's no way the NIC can work correctly, 713 * so we print out a message on the console and abort the device attach. 714 */ 715 716static int 717re_diag(sc) 718 struct rl_softc *sc; 719{ 720 struct ifnet *ifp = sc->rl_ifp; 721 struct mbuf *m0; 722 struct ether_header *eh; 723 struct rl_desc *cur_rx; 724 u_int16_t status; 725 u_int32_t rxstat; 726 int total_len, i, error = 0, phyaddr; 727 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 728 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 729 730 /* Allocate a single mbuf */ 731 MGETHDR(m0, M_DONTWAIT, MT_DATA); 732 if (m0 == NULL) 733 return (ENOBUFS); 734 735 RL_LOCK(sc); 736 737 /* 738 * Initialize the NIC in test mode. This sets the chip up 739 * so that it can send and receive frames, but performs the 740 * following special functions: 741 * - Puts receiver in promiscuous mode 742 * - Enables digital loopback mode 743 * - Leaves interrupts turned off 744 */ 745 746 ifp->if_flags |= IFF_PROMISC; 747 sc->rl_testmode = 1; 748 re_reset(sc); 749 re_init_locked(sc); 750 sc->rl_flags |= RL_FLAG_LINK; 751 if (sc->rl_type == RL_8169) 752 phyaddr = 1; 753 else 754 phyaddr = 0; 755 756 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 757 for (i = 0; i < RL_TIMEOUT; i++) { 758 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 759 if (!(status & BMCR_RESET)) 760 break; 761 } 762 763 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 764 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 765 766 DELAY(100000); 767 768 /* Put some data in the mbuf */ 769 770 eh = mtod(m0, struct ether_header *); 771 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 772 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 773 eh->ether_type = htons(ETHERTYPE_IP); 774 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 775 776 /* 777 * Queue the packet, start transmission. 778 * Note: IF_HANDOFF() ultimately calls re_start() for us. 779 */ 780 781 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 782 RL_UNLOCK(sc); 783 /* XXX: re_diag must not be called when in ALTQ mode */ 784 IF_HANDOFF(&ifp->if_snd, m0, ifp); 785 RL_LOCK(sc); 786 m0 = NULL; 787 788 /* Wait for it to propagate through the chip */ 789 790 DELAY(100000); 791 for (i = 0; i < RL_TIMEOUT; i++) { 792 status = CSR_READ_2(sc, RL_ISR); 793 CSR_WRITE_2(sc, RL_ISR, status); 794 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 795 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 796 break; 797 DELAY(10); 798 } 799 800 if (i == RL_TIMEOUT) { 801 device_printf(sc->rl_dev, 802 "diagnostic failed, failed to receive packet in" 803 " loopback mode\n"); 804 error = EIO; 805 goto done; 806 } 807 808 /* 809 * The packet should have been dumped into the first 810 * entry in the RX DMA ring. Grab it from there. 811 */ 812 813 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 814 sc->rl_ldata.rl_rx_list_map, 815 BUS_DMASYNC_POSTREAD); 816 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 817 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 818 BUS_DMASYNC_POSTREAD); 819 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 820 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 821 822 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 823 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 824 eh = mtod(m0, struct ether_header *); 825 826 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 827 total_len = RL_RXBYTES(cur_rx); 828 rxstat = le32toh(cur_rx->rl_cmdstat); 829 830 if (total_len != ETHER_MIN_LEN) { 831 device_printf(sc->rl_dev, 832 "diagnostic failed, received short packet\n"); 833 error = EIO; 834 goto done; 835 } 836 837 /* Test that the received packet data matches what we sent. */ 838 839 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 840 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 841 ntohs(eh->ether_type) != ETHERTYPE_IP) { 842 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 843 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 844 dst, ":", src, ":", ETHERTYPE_IP); 845 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 846 eh->ether_dhost, ":", eh->ether_shost, ":", 847 ntohs(eh->ether_type)); 848 device_printf(sc->rl_dev, "You may have a defective 32-bit " 849 "NIC plugged into a 64-bit PCI slot.\n"); 850 device_printf(sc->rl_dev, "Please re-install the NIC in a " 851 "32-bit slot for proper operation.\n"); 852 device_printf(sc->rl_dev, "Read the re(4) man page for more " 853 "details.\n"); 854 error = EIO; 855 } 856 857done: 858 /* Turn interface off, release resources */ 859 860 sc->rl_testmode = 0; 861 sc->rl_flags &= ~RL_FLAG_LINK; 862 ifp->if_flags &= ~IFF_PROMISC; 863 re_stop(sc); 864 if (m0 != NULL) 865 m_freem(m0); 866 867 RL_UNLOCK(sc); 868 869 return (error); 870} 871 872#endif 873 874/* 875 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 876 * IDs against our list and return a device name if we find a match. 877 */ 878static int 879re_probe(dev) 880 device_t dev; 881{ 882 struct rl_type *t; 883 uint16_t devid, vendor; 884 uint16_t revid, sdevid; 885 int i; 886 887 vendor = pci_get_vendor(dev); 888 devid = pci_get_device(dev); 889 revid = pci_get_revid(dev); 890 sdevid = pci_get_subdevice(dev); 891 892 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 893 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 894 /* 895 * Only attach to rev. 3 of the Linksys EG1032 adapter. 896 * Rev. 2 is supported by sk(4). 897 */ 898 return (ENXIO); 899 } 900 } 901 902 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 903 if (revid != 0x20) { 904 /* 8139, let rl(4) take care of this device. */ 905 return (ENXIO); 906 } 907 } 908 909 t = re_devs; 910 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 911 if (vendor == t->rl_vid && devid == t->rl_did) { 912 device_set_desc(dev, t->rl_name); 913 return (BUS_PROBE_DEFAULT); 914 } 915 } 916 917 return (ENXIO); 918} 919 920/* 921 * Map a single buffer address. 922 */ 923 924static void 925re_dma_map_addr(arg, segs, nseg, error) 926 void *arg; 927 bus_dma_segment_t *segs; 928 int nseg; 929 int error; 930{ 931 bus_addr_t *addr; 932 933 if (error) 934 return; 935 936 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 937 addr = arg; 938 *addr = segs->ds_addr; 939} 940 941static int 942re_allocmem(dev, sc) 943 device_t dev; 944 struct rl_softc *sc; 945{ 946 bus_size_t rx_list_size, tx_list_size; 947 int error; 948 int i; 949 950 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 951 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 952 953 /* 954 * Allocate the parent bus DMA tag appropriate for PCI. 955 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 956 * register should be set. However some RealTek chips are known 957 * to be buggy on DAC handling, therefore disable DAC by limiting 958 * DMA address space to 32bit. PCIe variants of RealTek chips 959 * may not have the limitation but I took safer path. 960 */ 961 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 962 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 963 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 964 NULL, NULL, &sc->rl_parent_tag); 965 if (error) { 966 device_printf(dev, "could not allocate parent DMA tag\n"); 967 return (error); 968 } 969 970 /* 971 * Allocate map for TX mbufs. 972 */ 973 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 974 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 975 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 976 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 977 if (error) { 978 device_printf(dev, "could not allocate TX DMA tag\n"); 979 return (error); 980 } 981 982 /* 983 * Allocate map for RX mbufs. 984 */ 985 986 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 987 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 988 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 989 if (error) { 990 device_printf(dev, "could not allocate RX DMA tag\n"); 991 return (error); 992 } 993 994 /* 995 * Allocate map for TX descriptor list. 996 */ 997 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 998 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 999 NULL, tx_list_size, 1, tx_list_size, 0, 1000 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1001 if (error) { 1002 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1003 return (error); 1004 } 1005 1006 /* Allocate DMA'able memory for the TX ring */ 1007 1008 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1009 (void **)&sc->rl_ldata.rl_tx_list, 1010 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1011 &sc->rl_ldata.rl_tx_list_map); 1012 if (error) { 1013 device_printf(dev, "could not allocate TX DMA ring\n"); 1014 return (error); 1015 } 1016 1017 /* Load the map for the TX ring. */ 1018 1019 sc->rl_ldata.rl_tx_list_addr = 0; 1020 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1021 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1022 tx_list_size, re_dma_map_addr, 1023 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1024 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1025 device_printf(dev, "could not load TX DMA ring\n"); 1026 return (ENOMEM); 1027 } 1028 1029 /* Create DMA maps for TX buffers */ 1030 1031 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1032 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1033 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1034 if (error) { 1035 device_printf(dev, "could not create DMA map for TX\n"); 1036 return (error); 1037 } 1038 } 1039 1040 /* 1041 * Allocate map for RX descriptor list. 1042 */ 1043 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1044 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1045 NULL, rx_list_size, 1, rx_list_size, 0, 1046 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1047 if (error) { 1048 device_printf(dev, "could not create RX DMA ring tag\n"); 1049 return (error); 1050 } 1051 1052 /* Allocate DMA'able memory for the RX ring */ 1053 1054 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1055 (void **)&sc->rl_ldata.rl_rx_list, 1056 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1057 &sc->rl_ldata.rl_rx_list_map); 1058 if (error) { 1059 device_printf(dev, "could not allocate RX DMA ring\n"); 1060 return (error); 1061 } 1062 1063 /* Load the map for the RX ring. */ 1064 1065 sc->rl_ldata.rl_rx_list_addr = 0; 1066 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1067 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1068 rx_list_size, re_dma_map_addr, 1069 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1070 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1071 device_printf(dev, "could not load RX DMA ring\n"); 1072 return (ENOMEM); 1073 } 1074 1075 /* Create DMA maps for RX buffers */ 1076 1077 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1078 &sc->rl_ldata.rl_rx_sparemap); 1079 if (error) { 1080 device_printf(dev, "could not create spare DMA map for RX\n"); 1081 return (error); 1082 } 1083 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1084 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1085 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1086 if (error) { 1087 device_printf(dev, "could not create DMA map for RX\n"); 1088 return (error); 1089 } 1090 } 1091 1092 return (0); 1093} 1094 1095/* 1096 * Attach the interface. Allocate softc structures, do ifmedia 1097 * setup and ethernet/BPF attach. 1098 */ 1099static int 1100re_attach(dev) 1101 device_t dev; 1102{ 1103 u_char eaddr[ETHER_ADDR_LEN]; 1104 u_int16_t as[ETHER_ADDR_LEN / 2]; 1105 struct rl_softc *sc; 1106 struct ifnet *ifp; 1107 struct rl_hwrev *hw_rev; 1108 int hwrev; 1109 u_int16_t devid, re_did = 0; 1110 int error = 0, rid, i; 1111 int msic, reg; 1112 uint8_t cfg; 1113 1114 sc = device_get_softc(dev); 1115 sc->rl_dev = dev; 1116 1117 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1118 MTX_DEF); 1119 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1120 1121 /* 1122 * Map control/status registers. 1123 */ 1124 pci_enable_busmaster(dev); 1125 1126 devid = pci_get_device(dev); 1127 /* Prefer memory space register mapping over IO space. */ 1128 sc->rl_res_id = PCIR_BAR(1); 1129 sc->rl_res_type = SYS_RES_MEMORY; 1130 /* RTL8168/8101E seems to use different BARs. */ 1131 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1132 sc->rl_res_id = PCIR_BAR(2); 1133 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1134 &sc->rl_res_id, RF_ACTIVE); 1135 1136 if (sc->rl_res == NULL) { 1137 sc->rl_res_id = PCIR_BAR(0); 1138 sc->rl_res_type = SYS_RES_IOPORT; 1139 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1140 &sc->rl_res_id, RF_ACTIVE); 1141 if (sc->rl_res == NULL) { 1142 device_printf(dev, "couldn't map ports/memory\n"); 1143 error = ENXIO; 1144 goto fail; 1145 } 1146 } 1147 1148 sc->rl_btag = rman_get_bustag(sc->rl_res); 1149 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1150 1151 msic = 0; 1152 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1153 msic = pci_msi_count(dev); 1154 if (bootverbose) 1155 device_printf(dev, "MSI count : %d\n", msic); 1156 } 1157 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1158 if (pci_alloc_msi(dev, &msic) == 0) { 1159 if (msic == RL_MSI_MESSAGES) { 1160 device_printf(dev, "Using %d MSI messages\n", 1161 msic); 1162 sc->rl_flags |= RL_FLAG_MSI; 1163 /* Explicitly set MSI enable bit. */ 1164 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1165 cfg = CSR_READ_1(sc, RL_CFG2); 1166 cfg |= RL_CFG2_MSI; 1167 CSR_WRITE_1(sc, RL_CFG2, cfg); 1168 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1169 } else 1170 pci_release_msi(dev); 1171 } 1172 } 1173 1174 /* Allocate interrupt */ 1175 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1176 rid = 0; 1177 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1178 RF_SHAREABLE | RF_ACTIVE); 1179 if (sc->rl_irq[0] == NULL) { 1180 device_printf(dev, "couldn't allocate IRQ resources\n"); 1181 error = ENXIO; 1182 goto fail; 1183 } 1184 } else { 1185 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1186 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1187 SYS_RES_IRQ, &rid, RF_ACTIVE); 1188 if (sc->rl_irq[i] == NULL) { 1189 device_printf(dev, 1190 "couldn't llocate IRQ resources for " 1191 "message %d\n", rid); 1192 error = ENXIO; 1193 goto fail; 1194 } 1195 } 1196 } 1197 1198 /* Reset the adapter. */ 1199 RL_LOCK(sc); 1200 re_reset(sc); 1201 RL_UNLOCK(sc); 1202 1203 hw_rev = re_hwrevs; 1204 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1205 while (hw_rev->rl_desc != NULL) { 1206 if (hw_rev->rl_rev == hwrev) { 1207 sc->rl_type = hw_rev->rl_type; 1208 break; 1209 } 1210 hw_rev++; 1211 } 1212 if (hw_rev->rl_desc == NULL) { 1213 device_printf(dev, "Unknown H/W revision: %08x\n", hwrev); 1214 error = ENXIO; 1215 goto fail; 1216 } 1217 1218 switch (hw_rev->rl_rev) { 1219 case RL_HWREV_8139CPLUS: 1220 sc->rl_flags |= RL_FLAG_NOJUMBO; 1221 break; 1222 case RL_HWREV_8100E: 1223 case RL_HWREV_8101E: 1224 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE; 1225 break; 1226 case RL_HWREV_8168_SPIN1: 1227 case RL_HWREV_8168_SPIN2: 1228 case RL_HWREV_8168_SPIN3: 1229 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE; 1230 break; 1231 case RL_HWREV_8169_8110SB: 1232 case RL_HWREV_8169_8110SC: 1233 sc->rl_flags |= RL_FLAG_PHYWAKE; 1234 break; 1235 default: 1236 break; 1237 } 1238 1239 sc->rl_eewidth = RL_9356_ADDR_LEN; 1240 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1241 if (re_did != 0x8129) 1242 sc->rl_eewidth = RL_9346_ADDR_LEN; 1243 1244 /* 1245 * Get station address from the EEPROM. 1246 */ 1247 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1248 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1249 as[i] = le16toh(as[i]); 1250 bcopy(as, eaddr, sizeof(eaddr)); 1251 1252 if (sc->rl_type == RL_8169) { 1253 /* Set RX length mask and number of descriptors. */ 1254 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1255 sc->rl_txstart = RL_GTXSTART; 1256 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1257 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1258 } else { 1259 /* Set RX length mask and number of descriptors. */ 1260 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1261 sc->rl_txstart = RL_TXSTART; 1262 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1263 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1264 } 1265 1266 error = re_allocmem(dev, sc); 1267 if (error) 1268 goto fail; 1269 1270 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1271 if (ifp == NULL) { 1272 device_printf(dev, "can not if_alloc()\n"); 1273 error = ENOSPC; 1274 goto fail; 1275 } 1276 1277 /* Take PHY out of power down mode. */ 1278 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1279 re_gmii_writereg(dev, 1, 0x1f, 0); 1280 re_gmii_writereg(dev, 1, 0x0e, 0); 1281 } 1282 1283 /* Do MII setup */ 1284 if (mii_phy_probe(dev, &sc->rl_miibus, 1285 re_ifmedia_upd, re_ifmedia_sts)) { 1286 device_printf(dev, "MII without any phy!\n"); 1287 error = ENXIO; 1288 goto fail; 1289 } 1290 1291 ifp->if_softc = sc; 1292 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1293 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1294 ifp->if_ioctl = re_ioctl; 1295 ifp->if_start = re_start; 1296 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1297 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1298 ifp->if_capenable = ifp->if_capabilities; 1299 ifp->if_init = re_init; 1300 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1301 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1302 IFQ_SET_READY(&ifp->if_snd); 1303 1304 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1305 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1306 1307 /* 1308 * Call MI attach routine. 1309 */ 1310 ether_ifattach(ifp, eaddr); 1311 1312 /* VLAN capability setup */ 1313 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1314 if (ifp->if_capabilities & IFCAP_HWCSUM) 1315 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1316 /* Enable WOL if PM is supported. */ 1317 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1318 ifp->if_capabilities |= IFCAP_WOL; 1319 ifp->if_capenable = ifp->if_capabilities; 1320#ifdef DEVICE_POLLING 1321 ifp->if_capabilities |= IFCAP_POLLING; 1322#endif 1323 /* 1324 * Tell the upper layer(s) we support long frames. 1325 * Must appear after the call to ether_ifattach() because 1326 * ether_ifattach() sets ifi_hdrlen to the default value. 1327 */ 1328 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1329 1330#ifdef RE_DIAG 1331 /* 1332 * Perform hardware diagnostic on the original RTL8169. 1333 * Some 32-bit cards were incorrectly wired and would 1334 * malfunction if plugged into a 64-bit slot. 1335 */ 1336 1337 if (hwrev == RL_HWREV_8169) { 1338 error = re_diag(sc); 1339 if (error) { 1340 device_printf(dev, 1341 "attach aborted due to hardware diag failure\n"); 1342 ether_ifdetach(ifp); 1343 goto fail; 1344 } 1345 } 1346#endif 1347 1348 /* Hook interrupt last to avoid having to lock softc */ 1349 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1350 error = bus_setup_intr(dev, sc->rl_irq[0], 1351 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1352 &sc->rl_intrhand[0]); 1353 else { 1354 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1355 error = bus_setup_intr(dev, sc->rl_irq[i], 1356 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1357 &sc->rl_intrhand[i]); 1358 if (error != 0) 1359 break; 1360 } 1361 } 1362 if (error) { 1363 device_printf(dev, "couldn't set up irq\n"); 1364 ether_ifdetach(ifp); 1365 } 1366 1367fail: 1368 1369 if (error) 1370 re_detach(dev); 1371 1372 return (error); 1373} 1374 1375/* 1376 * Shutdown hardware and free up resources. This can be called any 1377 * time after the mutex has been initialized. It is called in both 1378 * the error case in attach and the normal detach case so it needs 1379 * to be careful about only freeing resources that have actually been 1380 * allocated. 1381 */ 1382static int 1383re_detach(dev) 1384 device_t dev; 1385{ 1386 struct rl_softc *sc; 1387 struct ifnet *ifp; 1388 int i, rid; 1389 1390 sc = device_get_softc(dev); 1391 ifp = sc->rl_ifp; 1392 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1393 1394 /* These should only be active if attach succeeded */ 1395 if (device_is_attached(dev)) { 1396#ifdef DEVICE_POLLING 1397 if (ifp->if_capenable & IFCAP_POLLING) 1398 ether_poll_deregister(ifp); 1399#endif 1400 RL_LOCK(sc); 1401#if 0 1402 sc->suspended = 1; 1403#endif 1404 re_stop(sc); 1405 RL_UNLOCK(sc); 1406 callout_drain(&sc->rl_stat_callout); 1407 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1408 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1409 /* 1410 * Force off the IFF_UP flag here, in case someone 1411 * still had a BPF descriptor attached to this 1412 * interface. If they do, ether_ifdetach() will cause 1413 * the BPF code to try and clear the promisc mode 1414 * flag, which will bubble down to re_ioctl(), 1415 * which will try to call re_init() again. This will 1416 * turn the NIC back on and restart the MII ticker, 1417 * which will panic the system when the kernel tries 1418 * to invoke the re_tick() function that isn't there 1419 * anymore. 1420 */ 1421 ifp->if_flags &= ~IFF_UP; 1422 ether_ifdetach(ifp); 1423 } 1424 if (sc->rl_miibus) 1425 device_delete_child(dev, sc->rl_miibus); 1426 bus_generic_detach(dev); 1427 1428 /* 1429 * The rest is resource deallocation, so we should already be 1430 * stopped here. 1431 */ 1432 1433 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1434 if (sc->rl_intrhand[i] != NULL) { 1435 bus_teardown_intr(dev, sc->rl_irq[i], 1436 sc->rl_intrhand[i]); 1437 sc->rl_intrhand[i] = NULL; 1438 } 1439 } 1440 if (ifp != NULL) 1441 if_free(ifp); 1442 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1443 if (sc->rl_irq[0] != NULL) { 1444 bus_release_resource(dev, SYS_RES_IRQ, 0, 1445 sc->rl_irq[0]); 1446 sc->rl_irq[0] = NULL; 1447 } 1448 } else { 1449 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1450 if (sc->rl_irq[i] != NULL) { 1451 bus_release_resource(dev, SYS_RES_IRQ, rid, 1452 sc->rl_irq[i]); 1453 sc->rl_irq[i] = NULL; 1454 } 1455 } 1456 pci_release_msi(dev); 1457 } 1458 if (sc->rl_res) 1459 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1460 sc->rl_res); 1461 1462 /* Unload and free the RX DMA ring memory and map */ 1463 1464 if (sc->rl_ldata.rl_rx_list_tag) { 1465 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1466 sc->rl_ldata.rl_rx_list_map); 1467 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1468 sc->rl_ldata.rl_rx_list, 1469 sc->rl_ldata.rl_rx_list_map); 1470 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1471 } 1472 1473 /* Unload and free the TX DMA ring memory and map */ 1474 1475 if (sc->rl_ldata.rl_tx_list_tag) { 1476 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1477 sc->rl_ldata.rl_tx_list_map); 1478 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1479 sc->rl_ldata.rl_tx_list, 1480 sc->rl_ldata.rl_tx_list_map); 1481 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1482 } 1483 1484 /* Destroy all the RX and TX buffer maps */ 1485 1486 if (sc->rl_ldata.rl_tx_mtag) { 1487 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1488 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1489 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1490 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1491 } 1492 if (sc->rl_ldata.rl_rx_mtag) { 1493 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1494 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1495 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1496 if (sc->rl_ldata.rl_rx_sparemap) 1497 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1498 sc->rl_ldata.rl_rx_sparemap); 1499 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1500 } 1501 1502 /* Unload and free the stats buffer and map */ 1503 1504 if (sc->rl_ldata.rl_stag) { 1505 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1506 sc->rl_ldata.rl_rx_list_map); 1507 bus_dmamem_free(sc->rl_ldata.rl_stag, 1508 sc->rl_ldata.rl_stats, 1509 sc->rl_ldata.rl_smap); 1510 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1511 } 1512 1513 if (sc->rl_parent_tag) 1514 bus_dma_tag_destroy(sc->rl_parent_tag); 1515 1516 mtx_destroy(&sc->rl_mtx); 1517 1518 return (0); 1519} 1520 1521static __inline void 1522re_discard_rxbuf(sc, idx) 1523 struct rl_softc *sc; 1524 int idx; 1525{ 1526 struct rl_desc *desc; 1527 struct rl_rxdesc *rxd; 1528 uint32_t cmdstat; 1529 1530 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1531 desc = &sc->rl_ldata.rl_rx_list[idx]; 1532 desc->rl_vlanctl = 0; 1533 cmdstat = rxd->rx_size; 1534 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1535 cmdstat |= RL_RDESC_CMD_EOR; 1536 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1537} 1538 1539static int 1540re_newbuf(sc, idx) 1541 struct rl_softc *sc; 1542 int idx; 1543{ 1544 struct mbuf *m; 1545 struct rl_rxdesc *rxd; 1546 bus_dma_segment_t segs[1]; 1547 bus_dmamap_t map; 1548 struct rl_desc *desc; 1549 uint32_t cmdstat; 1550 int error, nsegs; 1551 1552 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1553 if (m == NULL) 1554 return (ENOBUFS); 1555 1556 m->m_len = m->m_pkthdr.len = MCLBYTES; 1557#ifdef RE_FIXUP_RX 1558 /* 1559 * This is part of an evil trick to deal with non-x86 platforms. 1560 * The RealTek chip requires RX buffers to be aligned on 64-bit 1561 * boundaries, but that will hose non-x86 machines. To get around 1562 * this, we leave some empty space at the start of each buffer 1563 * and for non-x86 hosts, we copy the buffer back six bytes 1564 * to achieve word alignment. This is slightly more efficient 1565 * than allocating a new buffer, copying the contents, and 1566 * discarding the old buffer. 1567 */ 1568 m_adj(m, RE_ETHER_ALIGN); 1569#endif 1570 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1571 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1572 if (error != 0) { 1573 m_freem(m); 1574 return (ENOBUFS); 1575 } 1576 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1577 1578 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1579 if (rxd->rx_m != NULL) { 1580 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1581 BUS_DMASYNC_POSTREAD); 1582 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1583 } 1584 1585 rxd->rx_m = m; 1586 map = rxd->rx_dmamap; 1587 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1588 rxd->rx_size = segs[0].ds_len; 1589 sc->rl_ldata.rl_rx_sparemap = map; 1590 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1591 BUS_DMASYNC_PREREAD); 1592 1593 desc = &sc->rl_ldata.rl_rx_list[idx]; 1594 desc->rl_vlanctl = 0; 1595 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1596 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1597 cmdstat = segs[0].ds_len; 1598 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1599 cmdstat |= RL_RDESC_CMD_EOR; 1600 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1601 1602 return (0); 1603} 1604 1605#ifdef RE_FIXUP_RX 1606static __inline void 1607re_fixup_rx(m) 1608 struct mbuf *m; 1609{ 1610 int i; 1611 uint16_t *src, *dst; 1612 1613 src = mtod(m, uint16_t *); 1614 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1615 1616 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1617 *dst++ = *src++; 1618 1619 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1620 1621 return; 1622} 1623#endif 1624 1625static int 1626re_tx_list_init(sc) 1627 struct rl_softc *sc; 1628{ 1629 struct rl_desc *desc; 1630 int i; 1631 1632 RL_LOCK_ASSERT(sc); 1633 1634 bzero(sc->rl_ldata.rl_tx_list, 1635 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1636 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1637 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1638 /* Set EOR. */ 1639 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1640 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1641 1642 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1643 sc->rl_ldata.rl_tx_list_map, 1644 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1645 1646 sc->rl_ldata.rl_tx_prodidx = 0; 1647 sc->rl_ldata.rl_tx_considx = 0; 1648 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1649 1650 return (0); 1651} 1652 1653static int 1654re_rx_list_init(sc) 1655 struct rl_softc *sc; 1656{ 1657 int error, i; 1658 1659 bzero(sc->rl_ldata.rl_rx_list, 1660 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1661 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1662 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1663 if ((error = re_newbuf(sc, i)) != 0) 1664 return (error); 1665 } 1666 1667 /* Flush the RX descriptors */ 1668 1669 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1670 sc->rl_ldata.rl_rx_list_map, 1671 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1672 1673 sc->rl_ldata.rl_rx_prodidx = 0; 1674 sc->rl_head = sc->rl_tail = NULL; 1675 1676 return (0); 1677} 1678 1679/* 1680 * RX handler for C+ and 8169. For the gigE chips, we support 1681 * the reception of jumbo frames that have been fragmented 1682 * across multiple 2K mbuf cluster buffers. 1683 */ 1684static int 1685re_rxeof(sc) 1686 struct rl_softc *sc; 1687{ 1688 struct mbuf *m; 1689 struct ifnet *ifp; 1690 int i, total_len; 1691 struct rl_desc *cur_rx; 1692 u_int32_t rxstat, rxvlan; 1693 int maxpkt = 16; 1694 1695 RL_LOCK_ASSERT(sc); 1696 1697 ifp = sc->rl_ifp; 1698 1699 /* Invalidate the descriptor memory */ 1700 1701 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1702 sc->rl_ldata.rl_rx_list_map, 1703 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1704 1705 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1706 i = RL_RX_DESC_NXT(sc, i)) { 1707 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1708 rxstat = le32toh(cur_rx->rl_cmdstat); 1709 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1710 break; 1711 total_len = rxstat & sc->rl_rxlenmask; 1712 rxvlan = le32toh(cur_rx->rl_vlanctl); 1713 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1714 1715 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1716 if (re_newbuf(sc, i) != 0) { 1717 /* 1718 * If this is part of a multi-fragment packet, 1719 * discard all the pieces. 1720 */ 1721 if (sc->rl_head != NULL) { 1722 m_freem(sc->rl_head); 1723 sc->rl_head = sc->rl_tail = NULL; 1724 } 1725 re_discard_rxbuf(sc, i); 1726 continue; 1727 } 1728 m->m_len = RE_RX_DESC_BUFLEN; 1729 if (sc->rl_head == NULL) 1730 sc->rl_head = sc->rl_tail = m; 1731 else { 1732 m->m_flags &= ~M_PKTHDR; 1733 sc->rl_tail->m_next = m; 1734 sc->rl_tail = m; 1735 } 1736 continue; 1737 } 1738 1739 /* 1740 * NOTE: for the 8139C+, the frame length field 1741 * is always 12 bits in size, but for the gigE chips, 1742 * it is 13 bits (since the max RX frame length is 16K). 1743 * Unfortunately, all 32 bits in the status word 1744 * were already used, so to make room for the extra 1745 * length bit, RealTek took out the 'frame alignment 1746 * error' bit and shifted the other status bits 1747 * over one slot. The OWN, EOR, FS and LS bits are 1748 * still in the same places. We have already extracted 1749 * the frame length and checked the OWN bit, so rather 1750 * than using an alternate bit mapping, we shift the 1751 * status bits one space to the right so we can evaluate 1752 * them using the 8169 status as though it was in the 1753 * same format as that of the 8139C+. 1754 */ 1755 if (sc->rl_type == RL_8169) 1756 rxstat >>= 1; 1757 1758 /* 1759 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1760 * set, but if CRC is clear, it will still be a valid frame. 1761 */ 1762 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1763 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1764 ifp->if_ierrors++; 1765 /* 1766 * If this is part of a multi-fragment packet, 1767 * discard all the pieces. 1768 */ 1769 if (sc->rl_head != NULL) { 1770 m_freem(sc->rl_head); 1771 sc->rl_head = sc->rl_tail = NULL; 1772 } 1773 re_discard_rxbuf(sc, i); 1774 continue; 1775 } 1776 1777 /* 1778 * If allocating a replacement mbuf fails, 1779 * reload the current one. 1780 */ 1781 1782 if (re_newbuf(sc, i) != 0) { 1783 ifp->if_iqdrops++; 1784 if (sc->rl_head != NULL) { 1785 m_freem(sc->rl_head); 1786 sc->rl_head = sc->rl_tail = NULL; 1787 } 1788 re_discard_rxbuf(sc, i); 1789 continue; 1790 } 1791 1792 if (sc->rl_head != NULL) { 1793 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1794 if (m->m_len == 0) 1795 m->m_len = RE_RX_DESC_BUFLEN; 1796 /* 1797 * Special case: if there's 4 bytes or less 1798 * in this buffer, the mbuf can be discarded: 1799 * the last 4 bytes is the CRC, which we don't 1800 * care about anyway. 1801 */ 1802 if (m->m_len <= ETHER_CRC_LEN) { 1803 sc->rl_tail->m_len -= 1804 (ETHER_CRC_LEN - m->m_len); 1805 m_freem(m); 1806 } else { 1807 m->m_len -= ETHER_CRC_LEN; 1808 m->m_flags &= ~M_PKTHDR; 1809 sc->rl_tail->m_next = m; 1810 } 1811 m = sc->rl_head; 1812 sc->rl_head = sc->rl_tail = NULL; 1813 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1814 } else 1815 m->m_pkthdr.len = m->m_len = 1816 (total_len - ETHER_CRC_LEN); 1817 1818#ifdef RE_FIXUP_RX 1819 re_fixup_rx(m); 1820#endif 1821 ifp->if_ipackets++; 1822 m->m_pkthdr.rcvif = ifp; 1823 1824 /* Do RX checksumming if enabled */ 1825 1826 if (ifp->if_capenable & IFCAP_RXCSUM) { 1827 1828 /* Check IP header checksum */ 1829 if (rxstat & RL_RDESC_STAT_PROTOID) 1830 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1831 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1832 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1833 1834 /* Check TCP/UDP checksum */ 1835 if ((RL_TCPPKT(rxstat) && 1836 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1837 (RL_UDPPKT(rxstat) && 1838 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1839 m->m_pkthdr.csum_flags |= 1840 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1841 m->m_pkthdr.csum_data = 0xffff; 1842 } 1843 } 1844 maxpkt--; 1845 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1846 m->m_pkthdr.ether_vtag = 1847 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1848 m->m_flags |= M_VLANTAG; 1849 } 1850 RL_UNLOCK(sc); 1851 (*ifp->if_input)(ifp, m); 1852 RL_LOCK(sc); 1853 } 1854 1855 /* Flush the RX DMA ring */ 1856 1857 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1858 sc->rl_ldata.rl_rx_list_map, 1859 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1860 1861 sc->rl_ldata.rl_rx_prodidx = i; 1862 1863 if (maxpkt) 1864 return(EAGAIN); 1865 1866 return(0); 1867} 1868 1869static void 1870re_txeof(sc) 1871 struct rl_softc *sc; 1872{ 1873 struct ifnet *ifp; 1874 struct rl_txdesc *txd; 1875 u_int32_t txstat; 1876 int cons; 1877 1878 cons = sc->rl_ldata.rl_tx_considx; 1879 if (cons == sc->rl_ldata.rl_tx_prodidx) 1880 return; 1881 1882 ifp = sc->rl_ifp; 1883 /* Invalidate the TX descriptor list */ 1884 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1885 sc->rl_ldata.rl_tx_list_map, 1886 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1887 1888 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1889 cons = RL_TX_DESC_NXT(sc, cons)) { 1890 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1891 if (txstat & RL_TDESC_STAT_OWN) 1892 break; 1893 /* 1894 * We only stash mbufs in the last descriptor 1895 * in a fragment chain, which also happens to 1896 * be the only place where the TX status bits 1897 * are valid. 1898 */ 1899 if (txstat & RL_TDESC_CMD_EOF) { 1900 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1901 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1902 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1903 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1904 txd->tx_dmamap); 1905 KASSERT(txd->tx_m != NULL, 1906 ("%s: freeing NULL mbufs!", __func__)); 1907 m_freem(txd->tx_m); 1908 txd->tx_m = NULL; 1909 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1910 RL_TDESC_STAT_COLCNT)) 1911 ifp->if_collisions++; 1912 if (txstat & RL_TDESC_STAT_TXERRSUM) 1913 ifp->if_oerrors++; 1914 else 1915 ifp->if_opackets++; 1916 } 1917 sc->rl_ldata.rl_tx_free++; 1918 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1919 } 1920 sc->rl_ldata.rl_tx_considx = cons; 1921 1922 /* No changes made to the TX ring, so no flush needed */ 1923 1924 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1925 /* 1926 * Some chips will ignore a second TX request issued 1927 * while an existing transmission is in progress. If 1928 * the transmitter goes idle but there are still 1929 * packets waiting to be sent, we need to restart the 1930 * channel here to flush them out. This only seems to 1931 * be required with the PCIe devices. 1932 */ 1933 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1934 1935#ifdef RE_TX_MODERATION 1936 /* 1937 * If not all descriptors have been reaped yet, reload 1938 * the timer so that we will eventually get another 1939 * interrupt that will cause us to re-enter this routine. 1940 * This is done in case the transmitter has gone idle. 1941 */ 1942 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1943#endif 1944 } else 1945 sc->rl_watchdog_timer = 0; 1946} 1947 1948static void 1949re_tick(xsc) 1950 void *xsc; 1951{ 1952 struct rl_softc *sc; 1953 struct mii_data *mii; 1954 struct ifnet *ifp; 1955 1956 sc = xsc; 1957 ifp = sc->rl_ifp; 1958 1959 RL_LOCK_ASSERT(sc); 1960 1961 re_watchdog(sc); 1962 1963 mii = device_get_softc(sc->rl_miibus); 1964 mii_tick(mii); 1965 if ((sc->rl_flags & RL_FLAG_LINK) != 0) { 1966 if (!(mii->mii_media_status & IFM_ACTIVE)) 1967 sc->rl_flags &= ~RL_FLAG_LINK; 1968 } else { 1969 if (mii->mii_media_status & IFM_ACTIVE && 1970 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1971 sc->rl_flags |= RL_FLAG_LINK; 1972 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1973 taskqueue_enqueue_fast(taskqueue_fast, 1974 &sc->rl_txtask); 1975 } 1976 } 1977 1978 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1979} 1980 1981#ifdef DEVICE_POLLING 1982static void 1983re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1984{ 1985 struct rl_softc *sc = ifp->if_softc; 1986 1987 RL_LOCK(sc); 1988 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1989 re_poll_locked(ifp, cmd, count); 1990 RL_UNLOCK(sc); 1991} 1992 1993static void 1994re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1995{ 1996 struct rl_softc *sc = ifp->if_softc; 1997 1998 RL_LOCK_ASSERT(sc); 1999 2000 sc->rxcycles = count; 2001 re_rxeof(sc); 2002 re_txeof(sc); 2003 2004 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2005 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2006 2007 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2008 u_int16_t status; 2009 2010 status = CSR_READ_2(sc, RL_ISR); 2011 if (status == 0xffff) 2012 return; 2013 if (status) 2014 CSR_WRITE_2(sc, RL_ISR, status); 2015 2016 /* 2017 * XXX check behaviour on receiver stalls. 2018 */ 2019 2020 if (status & RL_ISR_SYSTEM_ERR) { 2021 re_reset(sc); 2022 re_init_locked(sc); 2023 } 2024 } 2025} 2026#endif /* DEVICE_POLLING */ 2027 2028static int 2029re_intr(arg) 2030 void *arg; 2031{ 2032 struct rl_softc *sc; 2033 uint16_t status; 2034 2035 sc = arg; 2036 2037 status = CSR_READ_2(sc, RL_ISR); 2038 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2039 return (FILTER_STRAY); 2040 CSR_WRITE_2(sc, RL_IMR, 0); 2041 2042 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2043 2044 return (FILTER_HANDLED); 2045} 2046 2047static void 2048re_int_task(arg, npending) 2049 void *arg; 2050 int npending; 2051{ 2052 struct rl_softc *sc; 2053 struct ifnet *ifp; 2054 u_int16_t status; 2055 int rval = 0; 2056 2057 sc = arg; 2058 ifp = sc->rl_ifp; 2059 2060 RL_LOCK(sc); 2061 2062 status = CSR_READ_2(sc, RL_ISR); 2063 CSR_WRITE_2(sc, RL_ISR, status); 2064 2065 if (sc->suspended || 2066 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2067 RL_UNLOCK(sc); 2068 return; 2069 } 2070 2071#ifdef DEVICE_POLLING 2072 if (ifp->if_capenable & IFCAP_POLLING) { 2073 RL_UNLOCK(sc); 2074 return; 2075 } 2076#endif 2077 2078 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2079 rval = re_rxeof(sc); 2080 2081#ifdef RE_TX_MODERATION 2082 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2083#else 2084 if (status & (RL_ISR_TX_OK| 2085#endif 2086 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2087 re_txeof(sc); 2088 2089 if (status & RL_ISR_SYSTEM_ERR) { 2090 re_reset(sc); 2091 re_init_locked(sc); 2092 } 2093 2094 if (status & RL_ISR_LINKCHG) { 2095 callout_stop(&sc->rl_stat_callout); 2096 re_tick(sc); 2097 } 2098 2099 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2100 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2101 2102 RL_UNLOCK(sc); 2103 2104 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2105 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2106 return; 2107 } 2108 2109 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2110 2111 return; 2112} 2113 2114static int 2115re_encap(sc, m_head) 2116 struct rl_softc *sc; 2117 struct mbuf **m_head; 2118{ 2119 struct rl_txdesc *txd, *txd_last; 2120 bus_dma_segment_t segs[RL_NTXSEGS]; 2121 bus_dmamap_t map; 2122 struct mbuf *m_new; 2123 struct rl_desc *desc; 2124 int nsegs, prod; 2125 int i, error, ei, si; 2126 int padlen; 2127 uint32_t cmdstat, csum_flags, vlanctl; 2128 2129 RL_LOCK_ASSERT(sc); 2130 M_ASSERTPKTHDR((*m_head)); 2131 2132 /* 2133 * With some of the RealTek chips, using the checksum offload 2134 * support in conjunction with the autopadding feature results 2135 * in the transmission of corrupt frames. For example, if we 2136 * need to send a really small IP fragment that's less than 60 2137 * bytes in size, and IP header checksumming is enabled, the 2138 * resulting ethernet frame that appears on the wire will 2139 * have garbled payload. To work around this, if TX IP checksum 2140 * offload is enabled, we always manually pad short frames out 2141 * to the minimum ethernet frame size. 2142 */ 2143 if ((*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2144 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2145 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2146 if (M_WRITABLE(*m_head) == 0) { 2147 /* Get a writable copy. */ 2148 m_new = m_dup(*m_head, M_DONTWAIT); 2149 m_freem(*m_head); 2150 if (m_new == NULL) { 2151 *m_head = NULL; 2152 return (ENOBUFS); 2153 } 2154 *m_head = m_new; 2155 } 2156 if ((*m_head)->m_next != NULL || 2157 M_TRAILINGSPACE(*m_head) < padlen) { 2158 m_new = m_defrag(*m_head, M_DONTWAIT); 2159 if (m_new == NULL) { 2160 m_freem(*m_head); 2161 *m_head = NULL; 2162 return (ENOBUFS); 2163 } 2164 } else 2165 m_new = *m_head; 2166 2167 /* 2168 * Manually pad short frames, and zero the pad space 2169 * to avoid leaking data. 2170 */ 2171 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2172 m_new->m_pkthdr.len += padlen; 2173 m_new->m_len = m_new->m_pkthdr.len; 2174 *m_head = m_new; 2175 } 2176 2177 prod = sc->rl_ldata.rl_tx_prodidx; 2178 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2179 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2180 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2181 if (error == EFBIG) { 2182 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2183 if (m_new == NULL) { 2184 m_freem(*m_head); 2185 *m_head = NULL; 2186 return (ENOBUFS); 2187 } 2188 *m_head = m_new; 2189 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2190 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2191 if (error != 0) { 2192 m_freem(*m_head); 2193 *m_head = NULL; 2194 return (error); 2195 } 2196 } else if (error != 0) 2197 return (error); 2198 if (nsegs == 0) { 2199 m_freem(*m_head); 2200 *m_head = NULL; 2201 return (EIO); 2202 } 2203 2204 /* Check for number of available descriptors. */ 2205 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2206 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2207 return (ENOBUFS); 2208 } 2209 2210 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2211 BUS_DMASYNC_PREWRITE); 2212 2213 /* 2214 * Set up checksum offload. Note: checksum offload bits must 2215 * appear in all descriptors of a multi-descriptor transmit 2216 * attempt. This is according to testing done with an 8169 2217 * chip. This is a requirement. 2218 */ 2219 csum_flags = 0; 2220 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2221 csum_flags = RL_TDESC_CMD_LGSEND | 2222 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2223 RL_TDESC_CMD_MSSVAL_SHIFT); 2224 else { 2225 /* 2226 * Unconditionally enable IP checksum if TCP or UDP 2227 * checksum is required. Otherwise, TCP/UDP checksum 2228 * does't make effects. 2229 */ 2230 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2231 csum_flags |= RL_TDESC_CMD_IPCSUM; 2232 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2233 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2234 if (((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2235 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2236 } 2237 } 2238 2239 /* 2240 * Set up hardware VLAN tagging. Note: vlan tag info must 2241 * appear in all descriptors of a multi-descriptor 2242 * transmission attempt. 2243 */ 2244 vlanctl = 0; 2245 if ((*m_head)->m_flags & M_VLANTAG) 2246 vlanctl = 2247 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2248 RL_TDESC_VLANCTL_TAG); 2249 2250 si = prod; 2251 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2252 desc = &sc->rl_ldata.rl_tx_list[prod]; 2253 desc->rl_vlanctl = vlanctl; 2254 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2255 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2256 cmdstat = segs[i].ds_len; 2257 if (i != 0) 2258 cmdstat |= RL_TDESC_CMD_OWN; 2259 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2260 cmdstat |= RL_TDESC_CMD_EOR; 2261 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2262 sc->rl_ldata.rl_tx_free--; 2263 } 2264 /* Update producer index. */ 2265 sc->rl_ldata.rl_tx_prodidx = prod; 2266 2267 /* Set EOF on the last descriptor. */ 2268 ei = RL_TX_DESC_PRV(sc, prod); 2269 desc = &sc->rl_ldata.rl_tx_list[ei]; 2270 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2271 2272 desc = &sc->rl_ldata.rl_tx_list[si]; 2273 /* Set SOF and transfer ownership of packet to the chip. */ 2274 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2275 2276 /* 2277 * Insure that the map for this transmission 2278 * is placed at the array index of the last descriptor 2279 * in this chain. (Swap last and first dmamaps.) 2280 */ 2281 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2282 map = txd->tx_dmamap; 2283 txd->tx_dmamap = txd_last->tx_dmamap; 2284 txd_last->tx_dmamap = map; 2285 txd_last->tx_m = *m_head; 2286 2287 return (0); 2288} 2289 2290static void 2291re_tx_task(arg, npending) 2292 void *arg; 2293 int npending; 2294{ 2295 struct ifnet *ifp; 2296 2297 ifp = arg; 2298 re_start(ifp); 2299 2300 return; 2301} 2302 2303/* 2304 * Main transmit routine for C+ and gigE NICs. 2305 */ 2306static void 2307re_start(ifp) 2308 struct ifnet *ifp; 2309{ 2310 struct rl_softc *sc; 2311 struct mbuf *m_head; 2312 int queued; 2313 2314 sc = ifp->if_softc; 2315 2316 RL_LOCK(sc); 2317 2318 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2319 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2320 RL_UNLOCK(sc); 2321 return; 2322 } 2323 2324 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2325 sc->rl_ldata.rl_tx_free > 1;) { 2326 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2327 if (m_head == NULL) 2328 break; 2329 2330 if (re_encap(sc, &m_head) != 0) { 2331 if (m_head == NULL) 2332 break; 2333 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2334 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2335 break; 2336 } 2337 2338 /* 2339 * If there's a BPF listener, bounce a copy of this frame 2340 * to him. 2341 */ 2342 ETHER_BPF_MTAP(ifp, m_head); 2343 2344 queued++; 2345 } 2346 2347 if (queued == 0) { 2348#ifdef RE_TX_MODERATION 2349 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2350 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2351#endif 2352 RL_UNLOCK(sc); 2353 return; 2354 } 2355 2356 /* Flush the TX descriptors */ 2357 2358 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2359 sc->rl_ldata.rl_tx_list_map, 2360 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2361 2362 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2363 2364#ifdef RE_TX_MODERATION 2365 /* 2366 * Use the countdown timer for interrupt moderation. 2367 * 'TX done' interrupts are disabled. Instead, we reset the 2368 * countdown timer, which will begin counting until it hits 2369 * the value in the TIMERINT register, and then trigger an 2370 * interrupt. Each time we write to the TIMERCNT register, 2371 * the timer count is reset to 0. 2372 */ 2373 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2374#endif 2375 2376 /* 2377 * Set a timeout in case the chip goes out to lunch. 2378 */ 2379 sc->rl_watchdog_timer = 5; 2380 2381 RL_UNLOCK(sc); 2382 2383 return; 2384} 2385 2386static void 2387re_init(xsc) 2388 void *xsc; 2389{ 2390 struct rl_softc *sc = xsc; 2391 2392 RL_LOCK(sc); 2393 re_init_locked(sc); 2394 RL_UNLOCK(sc); 2395} 2396 2397static void 2398re_init_locked(sc) 2399 struct rl_softc *sc; 2400{ 2401 struct ifnet *ifp = sc->rl_ifp; 2402 struct mii_data *mii; 2403 u_int32_t rxcfg = 0; 2404 uint16_t cfg; 2405 union { 2406 uint32_t align_dummy; 2407 u_char eaddr[ETHER_ADDR_LEN]; 2408 } eaddr; 2409 2410 RL_LOCK_ASSERT(sc); 2411 2412 mii = device_get_softc(sc->rl_miibus); 2413 2414 /* 2415 * Cancel pending I/O and free all RX/TX buffers. 2416 */ 2417 re_stop(sc); 2418 2419 /* 2420 * Enable C+ RX and TX mode, as well as VLAN stripping and 2421 * RX checksum offload. We must configure the C+ register 2422 * before all others. 2423 */ 2424 cfg = RL_CPLUSCMD_PCI_MRW; 2425 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2426 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2427 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2428 cfg |= RL_CPLUSCMD_VLANSTRIP; 2429 CSR_WRITE_2(sc, RL_CPLUS_CMD, 2430 cfg | RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB); 2431 2432 /* 2433 * Init our MAC address. Even though the chipset 2434 * documentation doesn't mention it, we need to enter "Config 2435 * register write enable" mode to modify the ID registers. 2436 */ 2437 /* Copy MAC address on stack to align. */ 2438 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2439 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2440 CSR_WRITE_4(sc, RL_IDR0, 2441 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2442 CSR_WRITE_4(sc, RL_IDR4, 2443 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2444 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2445 2446 /* 2447 * For C+ mode, initialize the RX descriptors and mbufs. 2448 */ 2449 re_rx_list_init(sc); 2450 re_tx_list_init(sc); 2451 2452 /* 2453 * Load the addresses of the RX and TX lists into the chip. 2454 */ 2455 2456 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2457 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2458 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2459 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2460 2461 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2462 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2463 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2464 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2465 2466 /* 2467 * Enable transmit and receive. 2468 */ 2469 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2470 2471 /* 2472 * Set the initial TX and RX configuration. 2473 */ 2474 if (sc->rl_testmode) { 2475 if (sc->rl_type == RL_8169) 2476 CSR_WRITE_4(sc, RL_TXCFG, 2477 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2478 else 2479 CSR_WRITE_4(sc, RL_TXCFG, 2480 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2481 } else 2482 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2483 2484 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2485 2486 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2487 2488 /* Set the individual bit to receive frames for this host only. */ 2489 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2490 rxcfg |= RL_RXCFG_RX_INDIV; 2491 2492 /* If we want promiscuous mode, set the allframes bit. */ 2493 if (ifp->if_flags & IFF_PROMISC) 2494 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2495 else 2496 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2497 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2498 2499 /* 2500 * Set capture broadcast bit to capture broadcast frames. 2501 */ 2502 if (ifp->if_flags & IFF_BROADCAST) 2503 rxcfg |= RL_RXCFG_RX_BROAD; 2504 else 2505 rxcfg &= ~RL_RXCFG_RX_BROAD; 2506 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2507 2508 /* 2509 * Program the multicast filter, if necessary. 2510 */ 2511 re_setmulti(sc); 2512 2513#ifdef DEVICE_POLLING 2514 /* 2515 * Disable interrupts if we are polling. 2516 */ 2517 if (ifp->if_capenable & IFCAP_POLLING) 2518 CSR_WRITE_2(sc, RL_IMR, 0); 2519 else /* otherwise ... */ 2520#endif 2521 2522 /* 2523 * Enable interrupts. 2524 */ 2525 if (sc->rl_testmode) 2526 CSR_WRITE_2(sc, RL_IMR, 0); 2527 else 2528 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2529 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2530 2531 /* Set initial TX threshold */ 2532 sc->rl_txthresh = RL_TX_THRESH_INIT; 2533 2534 /* Start RX/TX process. */ 2535 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2536#ifdef notdef 2537 /* Enable receiver and transmitter. */ 2538 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2539#endif 2540 2541#ifdef RE_TX_MODERATION 2542 /* 2543 * Initialize the timer interrupt register so that 2544 * a timer interrupt will be generated once the timer 2545 * reaches a certain number of ticks. The timer is 2546 * reloaded on each transmit. This gives us TX interrupt 2547 * moderation, which dramatically improves TX frame rate. 2548 */ 2549 if (sc->rl_type == RL_8169) 2550 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2551 else 2552 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2553#endif 2554 2555 /* 2556 * For 8169 gigE NICs, set the max allowed RX packet 2557 * size so we can receive jumbo frames. 2558 */ 2559 if (sc->rl_type == RL_8169) 2560 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2561 2562 if (sc->rl_testmode) 2563 return; 2564 2565 mii_mediachg(mii); 2566 2567 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2568 2569 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2570 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2571 2572 sc->rl_flags &= ~RL_FLAG_LINK; 2573 sc->rl_watchdog_timer = 0; 2574 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2575} 2576 2577/* 2578 * Set media options. 2579 */ 2580static int 2581re_ifmedia_upd(ifp) 2582 struct ifnet *ifp; 2583{ 2584 struct rl_softc *sc; 2585 struct mii_data *mii; 2586 2587 sc = ifp->if_softc; 2588 mii = device_get_softc(sc->rl_miibus); 2589 RL_LOCK(sc); 2590 mii_mediachg(mii); 2591 RL_UNLOCK(sc); 2592 2593 return (0); 2594} 2595 2596/* 2597 * Report current media status. 2598 */ 2599static void 2600re_ifmedia_sts(ifp, ifmr) 2601 struct ifnet *ifp; 2602 struct ifmediareq *ifmr; 2603{ 2604 struct rl_softc *sc; 2605 struct mii_data *mii; 2606 2607 sc = ifp->if_softc; 2608 mii = device_get_softc(sc->rl_miibus); 2609 2610 RL_LOCK(sc); 2611 mii_pollstat(mii); 2612 RL_UNLOCK(sc); 2613 ifmr->ifm_active = mii->mii_media_active; 2614 ifmr->ifm_status = mii->mii_media_status; 2615} 2616 2617static int 2618re_ioctl(ifp, command, data) 2619 struct ifnet *ifp; 2620 u_long command; 2621 caddr_t data; 2622{ 2623 struct rl_softc *sc = ifp->if_softc; 2624 struct ifreq *ifr = (struct ifreq *) data; 2625 struct mii_data *mii; 2626 int error = 0; 2627 2628 switch (command) { 2629 case SIOCSIFMTU: 2630 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2631 error = EINVAL; 2632 break; 2633 } 2634 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2635 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2636 error = EINVAL; 2637 break; 2638 } 2639 RL_LOCK(sc); 2640 if (ifp->if_mtu != ifr->ifr_mtu) 2641 ifp->if_mtu = ifr->ifr_mtu; 2642 RL_UNLOCK(sc); 2643 break; 2644 case SIOCSIFFLAGS: 2645 RL_LOCK(sc); 2646 if ((ifp->if_flags & IFF_UP) != 0) { 2647 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2648 if (((ifp->if_flags ^ sc->rl_if_flags) 2649 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2650 re_setmulti(sc); 2651 } else 2652 re_init_locked(sc); 2653 } else { 2654 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2655 re_stop(sc); 2656 } 2657 sc->rl_if_flags = ifp->if_flags; 2658 RL_UNLOCK(sc); 2659 break; 2660 case SIOCADDMULTI: 2661 case SIOCDELMULTI: 2662 RL_LOCK(sc); 2663 re_setmulti(sc); 2664 RL_UNLOCK(sc); 2665 break; 2666 case SIOCGIFMEDIA: 2667 case SIOCSIFMEDIA: 2668 mii = device_get_softc(sc->rl_miibus); 2669 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2670 break; 2671 case SIOCSIFCAP: 2672 { 2673 int mask, reinit; 2674 2675 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2676 reinit = 0; 2677#ifdef DEVICE_POLLING 2678 if (mask & IFCAP_POLLING) { 2679 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2680 error = ether_poll_register(re_poll, ifp); 2681 if (error) 2682 return(error); 2683 RL_LOCK(sc); 2684 /* Disable interrupts */ 2685 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2686 ifp->if_capenable |= IFCAP_POLLING; 2687 RL_UNLOCK(sc); 2688 } else { 2689 error = ether_poll_deregister(ifp); 2690 /* Enable interrupts. */ 2691 RL_LOCK(sc); 2692 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2693 ifp->if_capenable &= ~IFCAP_POLLING; 2694 RL_UNLOCK(sc); 2695 } 2696 } 2697#endif /* DEVICE_POLLING */ 2698 if (mask & IFCAP_HWCSUM) { 2699 ifp->if_capenable ^= IFCAP_HWCSUM; 2700 if (ifp->if_capenable & IFCAP_TXCSUM) 2701 ifp->if_hwassist |= RE_CSUM_FEATURES; 2702 else 2703 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2704 reinit = 1; 2705 } 2706 if (mask & IFCAP_VLAN_HWTAGGING) { 2707 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2708 reinit = 1; 2709 } 2710 if (mask & IFCAP_TSO4) { 2711 ifp->if_capenable ^= IFCAP_TSO4; 2712 if ((IFCAP_TSO4 & ifp->if_capenable) && 2713 (IFCAP_TSO4 & ifp->if_capabilities)) 2714 ifp->if_hwassist |= CSUM_TSO; 2715 else 2716 ifp->if_hwassist &= ~CSUM_TSO; 2717 } 2718 if ((mask & IFCAP_WOL) != 0 && 2719 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2720 if ((mask & IFCAP_WOL_UCAST) != 0) 2721 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2722 if ((mask & IFCAP_WOL_MCAST) != 0) 2723 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2724 if ((mask & IFCAP_WOL_MAGIC) != 0) 2725 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2726 } 2727 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2728 re_init(sc); 2729 VLAN_CAPABILITIES(ifp); 2730 } 2731 break; 2732 default: 2733 error = ether_ioctl(ifp, command, data); 2734 break; 2735 } 2736 2737 return (error); 2738} 2739 2740static void 2741re_watchdog(sc) 2742 struct rl_softc *sc; 2743{ 2744 2745 RL_LOCK_ASSERT(sc); 2746 2747 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2748 return; 2749 2750 device_printf(sc->rl_dev, "watchdog timeout\n"); 2751 sc->rl_ifp->if_oerrors++; 2752 2753 re_txeof(sc); 2754 re_rxeof(sc); 2755 re_init_locked(sc); 2756} 2757 2758/* 2759 * Stop the adapter and free any mbufs allocated to the 2760 * RX and TX lists. 2761 */ 2762static void 2763re_stop(sc) 2764 struct rl_softc *sc; 2765{ 2766 register int i; 2767 struct ifnet *ifp; 2768 struct rl_txdesc *txd; 2769 struct rl_rxdesc *rxd; 2770 2771 RL_LOCK_ASSERT(sc); 2772 2773 ifp = sc->rl_ifp; 2774 2775 sc->rl_watchdog_timer = 0; 2776 callout_stop(&sc->rl_stat_callout); 2777 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2778 2779 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2780 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2781 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2782 2783 if (sc->rl_head != NULL) { 2784 m_freem(sc->rl_head); 2785 sc->rl_head = sc->rl_tail = NULL; 2786 } 2787 2788 /* Free the TX list buffers. */ 2789 2790 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2791 txd = &sc->rl_ldata.rl_tx_desc[i]; 2792 if (txd->tx_m != NULL) { 2793 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2794 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2795 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2796 txd->tx_dmamap); 2797 m_freem(txd->tx_m); 2798 txd->tx_m = NULL; 2799 } 2800 } 2801 2802 /* Free the RX list buffers. */ 2803 2804 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2805 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2806 if (rxd->rx_m != NULL) { 2807 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2808 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2809 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2810 rxd->rx_dmamap); 2811 m_freem(rxd->rx_m); 2812 rxd->rx_m = NULL; 2813 } 2814 } 2815} 2816 2817/* 2818 * Device suspend routine. Stop the interface and save some PCI 2819 * settings in case the BIOS doesn't restore them properly on 2820 * resume. 2821 */ 2822static int 2823re_suspend(dev) 2824 device_t dev; 2825{ 2826 struct rl_softc *sc; 2827 2828 sc = device_get_softc(dev); 2829 2830 RL_LOCK(sc); 2831 re_stop(sc); 2832 re_setwol(sc); 2833 sc->suspended = 1; 2834 RL_UNLOCK(sc); 2835 2836 return (0); 2837} 2838 2839/* 2840 * Device resume routine. Restore some PCI settings in case the BIOS 2841 * doesn't, re-enable busmastering, and restart the interface if 2842 * appropriate. 2843 */ 2844static int 2845re_resume(dev) 2846 device_t dev; 2847{ 2848 struct rl_softc *sc; 2849 struct ifnet *ifp; 2850 2851 sc = device_get_softc(dev); 2852 2853 RL_LOCK(sc); 2854 2855 ifp = sc->rl_ifp; 2856 2857 /* reinitialize interface if necessary */ 2858 if (ifp->if_flags & IFF_UP) 2859 re_init_locked(sc); 2860 2861 /* 2862 * Clear WOL matching such that normal Rx filtering 2863 * wouldn't interfere with WOL patterns. 2864 */ 2865 re_clrwol(sc); 2866 sc->suspended = 0; 2867 RL_UNLOCK(sc); 2868 2869 return (0); 2870} 2871 2872/* 2873 * Stop all chip I/O so that the kernel's probe routines don't 2874 * get confused by errant DMAs when rebooting. 2875 */ 2876static int 2877re_shutdown(dev) 2878 device_t dev; 2879{ 2880 struct rl_softc *sc; 2881 2882 sc = device_get_softc(dev); 2883 2884 RL_LOCK(sc); 2885 re_stop(sc); 2886 /* 2887 * Mark interface as down since otherwise we will panic if 2888 * interrupt comes in later on, which can happen in some 2889 * cases. 2890 */ 2891 sc->rl_ifp->if_flags &= ~IFF_UP; 2892 re_setwol(sc); 2893 RL_UNLOCK(sc); 2894 2895 return (0); 2896} 2897 2898static void 2899re_setwol(sc) 2900 struct rl_softc *sc; 2901{ 2902 struct ifnet *ifp; 2903 int pmc; 2904 uint16_t pmstat; 2905 uint8_t v; 2906 2907 RL_LOCK_ASSERT(sc); 2908 2909 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2910 return; 2911 2912 ifp = sc->rl_ifp; 2913 /* Enable config register write. */ 2914 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2915 2916 /* Enable PME. */ 2917 v = CSR_READ_1(sc, RL_CFG1); 2918 v &= ~RL_CFG1_PME; 2919 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2920 v |= RL_CFG1_PME; 2921 CSR_WRITE_1(sc, RL_CFG1, v); 2922 2923 v = CSR_READ_1(sc, RL_CFG3); 2924 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2925 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2926 v |= RL_CFG3_WOL_MAGIC; 2927 CSR_WRITE_1(sc, RL_CFG3, v); 2928 2929 /* Config register write done. */ 2930 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2931 2932 v = CSR_READ_1(sc, RL_CFG5); 2933 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2934 v &= ~RL_CFG5_WOL_LANWAKE; 2935 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2936 v |= RL_CFG5_WOL_UCAST; 2937 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2938 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 2939 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2940 v |= RL_CFG5_WOL_LANWAKE; 2941 CSR_WRITE_1(sc, RL_CFG5, v); 2942 2943 /* 2944 * It seems that hardware resets its link speed to 100Mbps in 2945 * power down mode so switching to 100Mbps in driver is not 2946 * needed. 2947 */ 2948 2949 /* Request PME if WOL is requested. */ 2950 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 2951 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2952 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2953 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2954 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2955} 2956 2957static void 2958re_clrwol(sc) 2959 struct rl_softc *sc; 2960{ 2961 int pmc; 2962 uint8_t v; 2963 2964 RL_LOCK_ASSERT(sc); 2965 2966 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2967 return; 2968 2969 /* Enable config register write. */ 2970 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2971 2972 v = CSR_READ_1(sc, RL_CFG3); 2973 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2974 CSR_WRITE_1(sc, RL_CFG3, v); 2975 2976 /* Config register write done. */ 2977 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2978 2979 v = CSR_READ_1(sc, RL_CFG5); 2980 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2981 v &= ~RL_CFG5_WOL_LANWAKE; 2982 CSR_WRITE_1(sc, RL_CFG5, v); 2983} 2984