if_re.c revision 180168
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 180168 2008-07-02 05:01:19Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* 159 * Default to using PIO access for this driver. 160 */ 161#define RE_USEIOSPACE 162 163/* Tunables. */ 164static int msi_disable = 1; 165TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166 167#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 168 169/* 170 * Various supported device vendors/types and their names. 171 */ 172static struct rl_type re_devs[] = { 173 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 174 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 175 { RT_VENDORID, RT_DEVICEID_8139, 0, 176 "RealTek 8139C+ 10/100BaseTX" }, 177 { RT_VENDORID, RT_DEVICEID_8101E, 0, 178 "RealTek 8101E PCIe 10/100baseTX" }, 179 { RT_VENDORID, RT_DEVICEID_8168, 0, 180 "RealTek 8168/8168B/8111B PCIe Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169, 0, 182 "RealTek 8169/8169S/8169SB/8110S/8110SB Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 184 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 185 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 186 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 187 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 188 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 189 { USR_VENDORID, USR_DEVICEID_997902, 0, 190 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 191}; 192 193static struct rl_hwrev re_hwrevs[] = { 194 { RL_HWREV_8139, RL_8139, "" }, 195 { RL_HWREV_8139A, RL_8139, "A" }, 196 { RL_HWREV_8139AG, RL_8139, "A-G" }, 197 { RL_HWREV_8139B, RL_8139, "B" }, 198 { RL_HWREV_8130, RL_8139, "8130" }, 199 { RL_HWREV_8139C, RL_8139, "C" }, 200 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 201 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 202 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 203 { RL_HWREV_8169, RL_8169, "8169"}, 204 { RL_HWREV_8169S, RL_8169, "8169S"}, 205 { RL_HWREV_8110S, RL_8169, "8110S"}, 206 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 207 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 208 { RL_HWREV_8100, RL_8139, "8100"}, 209 { RL_HWREV_8101, RL_8139, "8101"}, 210 { RL_HWREV_8100E, RL_8169, "8100E"}, 211 { RL_HWREV_8101E, RL_8169, "8101E"}, 212 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 213 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 214 { 0, 0, NULL } 215}; 216 217static int re_probe (device_t); 218static int re_attach (device_t); 219static int re_detach (device_t); 220 221static int re_encap (struct rl_softc *, struct mbuf **); 222 223static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 224static int re_allocmem (device_t, struct rl_softc *); 225static __inline void re_discard_rxbuf 226 (struct rl_softc *, int); 227static int re_newbuf (struct rl_softc *, int); 228static int re_rx_list_init (struct rl_softc *); 229static int re_tx_list_init (struct rl_softc *); 230#ifdef RE_FIXUP_RX 231static __inline void re_fixup_rx 232 (struct mbuf *); 233#endif 234static int re_rxeof (struct rl_softc *); 235static void re_txeof (struct rl_softc *); 236#ifdef DEVICE_POLLING 237static void re_poll (struct ifnet *, enum poll_cmd, int); 238static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 239#endif 240static int re_intr (void *); 241static void re_tick (void *); 242static void re_tx_task (void *, int); 243static void re_int_task (void *, int); 244static void re_start (struct ifnet *); 245static int re_ioctl (struct ifnet *, u_long, caddr_t); 246static void re_init (void *); 247static void re_init_locked (struct rl_softc *); 248static void re_stop (struct rl_softc *); 249static void re_watchdog (struct rl_softc *); 250static int re_suspend (device_t); 251static int re_resume (device_t); 252static int re_shutdown (device_t); 253static int re_ifmedia_upd (struct ifnet *); 254static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 255 256static void re_eeprom_putbyte (struct rl_softc *, int); 257static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 258static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 259static int re_gmii_readreg (device_t, int, int); 260static int re_gmii_writereg (device_t, int, int, int); 261 262static int re_miibus_readreg (device_t, int, int); 263static int re_miibus_writereg (device_t, int, int, int); 264static void re_miibus_statchg (device_t); 265 266static void re_setmulti (struct rl_softc *); 267static void re_reset (struct rl_softc *); 268static void re_setwol (struct rl_softc *); 269static void re_clrwol (struct rl_softc *); 270 271#ifdef RE_DIAG 272static int re_diag (struct rl_softc *); 273#endif 274 275#ifdef RE_USEIOSPACE 276#define RL_RES SYS_RES_IOPORT 277#define RL_RID RL_PCI_LOIO 278#else 279#define RL_RES SYS_RES_MEMORY 280#define RL_RID RL_PCI_LOMEM 281#endif 282 283static device_method_t re_methods[] = { 284 /* Device interface */ 285 DEVMETHOD(device_probe, re_probe), 286 DEVMETHOD(device_attach, re_attach), 287 DEVMETHOD(device_detach, re_detach), 288 DEVMETHOD(device_suspend, re_suspend), 289 DEVMETHOD(device_resume, re_resume), 290 DEVMETHOD(device_shutdown, re_shutdown), 291 292 /* bus interface */ 293 DEVMETHOD(bus_print_child, bus_generic_print_child), 294 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 295 296 /* MII interface */ 297 DEVMETHOD(miibus_readreg, re_miibus_readreg), 298 DEVMETHOD(miibus_writereg, re_miibus_writereg), 299 DEVMETHOD(miibus_statchg, re_miibus_statchg), 300 301 { 0, 0 } 302}; 303 304static driver_t re_driver = { 305 "re", 306 re_methods, 307 sizeof(struct rl_softc) 308}; 309 310static devclass_t re_devclass; 311 312DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 313DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 314DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 315 316#define EE_SET(x) \ 317 CSR_WRITE_1(sc, RL_EECMD, \ 318 CSR_READ_1(sc, RL_EECMD) | x) 319 320#define EE_CLR(x) \ 321 CSR_WRITE_1(sc, RL_EECMD, \ 322 CSR_READ_1(sc, RL_EECMD) & ~x) 323 324/* 325 * Send a read command and address to the EEPROM, check for ACK. 326 */ 327static void 328re_eeprom_putbyte(sc, addr) 329 struct rl_softc *sc; 330 int addr; 331{ 332 register int d, i; 333 334 d = addr | (RL_9346_READ << sc->rl_eewidth); 335 336 /* 337 * Feed in each bit and strobe the clock. 338 */ 339 340 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 341 if (d & i) { 342 EE_SET(RL_EE_DATAIN); 343 } else { 344 EE_CLR(RL_EE_DATAIN); 345 } 346 DELAY(100); 347 EE_SET(RL_EE_CLK); 348 DELAY(150); 349 EE_CLR(RL_EE_CLK); 350 DELAY(100); 351 } 352 353 return; 354} 355 356/* 357 * Read a word of data stored in the EEPROM at address 'addr.' 358 */ 359static void 360re_eeprom_getword(sc, addr, dest) 361 struct rl_softc *sc; 362 int addr; 363 u_int16_t *dest; 364{ 365 register int i; 366 u_int16_t word = 0; 367 368 /* 369 * Send address of word we want to read. 370 */ 371 re_eeprom_putbyte(sc, addr); 372 373 /* 374 * Start reading bits from EEPROM. 375 */ 376 for (i = 0x8000; i; i >>= 1) { 377 EE_SET(RL_EE_CLK); 378 DELAY(100); 379 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 380 word |= i; 381 EE_CLR(RL_EE_CLK); 382 DELAY(100); 383 } 384 385 *dest = word; 386 387 return; 388} 389 390/* 391 * Read a sequence of words from the EEPROM. 392 */ 393static void 394re_read_eeprom(sc, dest, off, cnt) 395 struct rl_softc *sc; 396 caddr_t dest; 397 int off; 398 int cnt; 399{ 400 int i; 401 u_int16_t word = 0, *ptr; 402 403 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 404 405 DELAY(100); 406 407 for (i = 0; i < cnt; i++) { 408 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 409 re_eeprom_getword(sc, off + i, &word); 410 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 411 ptr = (u_int16_t *)(dest + (i * 2)); 412 *ptr = word; 413 } 414 415 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 416 417 return; 418} 419 420static int 421re_gmii_readreg(dev, phy, reg) 422 device_t dev; 423 int phy, reg; 424{ 425 struct rl_softc *sc; 426 u_int32_t rval; 427 int i; 428 429 if (phy != 1) 430 return (0); 431 432 sc = device_get_softc(dev); 433 434 /* Let the rgephy driver read the GMEDIASTAT register */ 435 436 if (reg == RL_GMEDIASTAT) { 437 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 438 return (rval); 439 } 440 441 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 442 DELAY(1000); 443 444 for (i = 0; i < RL_TIMEOUT; i++) { 445 rval = CSR_READ_4(sc, RL_PHYAR); 446 if (rval & RL_PHYAR_BUSY) 447 break; 448 DELAY(100); 449 } 450 451 if (i == RL_TIMEOUT) { 452 device_printf(sc->rl_dev, "PHY read failed\n"); 453 return (0); 454 } 455 456 return (rval & RL_PHYAR_PHYDATA); 457} 458 459static int 460re_gmii_writereg(dev, phy, reg, data) 461 device_t dev; 462 int phy, reg, data; 463{ 464 struct rl_softc *sc; 465 u_int32_t rval; 466 int i; 467 468 sc = device_get_softc(dev); 469 470 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 471 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 472 DELAY(1000); 473 474 for (i = 0; i < RL_TIMEOUT; i++) { 475 rval = CSR_READ_4(sc, RL_PHYAR); 476 if (!(rval & RL_PHYAR_BUSY)) 477 break; 478 DELAY(100); 479 } 480 481 if (i == RL_TIMEOUT) { 482 device_printf(sc->rl_dev, "PHY write failed\n"); 483 return (0); 484 } 485 486 return (0); 487} 488 489static int 490re_miibus_readreg(dev, phy, reg) 491 device_t dev; 492 int phy, reg; 493{ 494 struct rl_softc *sc; 495 u_int16_t rval = 0; 496 u_int16_t re8139_reg = 0; 497 498 sc = device_get_softc(dev); 499 500 if (sc->rl_type == RL_8169) { 501 rval = re_gmii_readreg(dev, phy, reg); 502 return (rval); 503 } 504 505 /* Pretend the internal PHY is only at address 0 */ 506 if (phy) { 507 return (0); 508 } 509 switch (reg) { 510 case MII_BMCR: 511 re8139_reg = RL_BMCR; 512 break; 513 case MII_BMSR: 514 re8139_reg = RL_BMSR; 515 break; 516 case MII_ANAR: 517 re8139_reg = RL_ANAR; 518 break; 519 case MII_ANER: 520 re8139_reg = RL_ANER; 521 break; 522 case MII_ANLPAR: 523 re8139_reg = RL_LPAR; 524 break; 525 case MII_PHYIDR1: 526 case MII_PHYIDR2: 527 return (0); 528 /* 529 * Allow the rlphy driver to read the media status 530 * register. If we have a link partner which does not 531 * support NWAY, this is the register which will tell 532 * us the results of parallel detection. 533 */ 534 case RL_MEDIASTAT: 535 rval = CSR_READ_1(sc, RL_MEDIASTAT); 536 return (rval); 537 default: 538 device_printf(sc->rl_dev, "bad phy register\n"); 539 return (0); 540 } 541 rval = CSR_READ_2(sc, re8139_reg); 542 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 543 /* 8139C+ has different bit layout. */ 544 rval &= ~(BMCR_LOOP | BMCR_ISO); 545 } 546 return (rval); 547} 548 549static int 550re_miibus_writereg(dev, phy, reg, data) 551 device_t dev; 552 int phy, reg, data; 553{ 554 struct rl_softc *sc; 555 u_int16_t re8139_reg = 0; 556 int rval = 0; 557 558 sc = device_get_softc(dev); 559 560 if (sc->rl_type == RL_8169) { 561 rval = re_gmii_writereg(dev, phy, reg, data); 562 return (rval); 563 } 564 565 /* Pretend the internal PHY is only at address 0 */ 566 if (phy) 567 return (0); 568 569 switch (reg) { 570 case MII_BMCR: 571 re8139_reg = RL_BMCR; 572 if (sc->rl_type == RL_8139CPLUS) { 573 /* 8139C+ has different bit layout. */ 574 data &= ~(BMCR_LOOP | BMCR_ISO); 575 } 576 break; 577 case MII_BMSR: 578 re8139_reg = RL_BMSR; 579 break; 580 case MII_ANAR: 581 re8139_reg = RL_ANAR; 582 break; 583 case MII_ANER: 584 re8139_reg = RL_ANER; 585 break; 586 case MII_ANLPAR: 587 re8139_reg = RL_LPAR; 588 break; 589 case MII_PHYIDR1: 590 case MII_PHYIDR2: 591 return (0); 592 break; 593 default: 594 device_printf(sc->rl_dev, "bad phy register\n"); 595 return (0); 596 } 597 CSR_WRITE_2(sc, re8139_reg, data); 598 return (0); 599} 600 601static void 602re_miibus_statchg(dev) 603 device_t dev; 604{ 605 606} 607 608/* 609 * Program the 64-bit multicast hash filter. 610 */ 611static void 612re_setmulti(sc) 613 struct rl_softc *sc; 614{ 615 struct ifnet *ifp; 616 int h = 0; 617 u_int32_t hashes[2] = { 0, 0 }; 618 struct ifmultiaddr *ifma; 619 u_int32_t rxfilt; 620 int mcnt = 0; 621 u_int32_t hwrev; 622 623 RL_LOCK_ASSERT(sc); 624 625 ifp = sc->rl_ifp; 626 627 628 rxfilt = CSR_READ_4(sc, RL_RXCFG); 629 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 if (ifp->if_flags & IFF_PROMISC) 632 rxfilt |= RL_RXCFG_RX_ALLPHYS; 633 /* 634 * Unlike other hardwares, we have to explicitly set 635 * RL_RXCFG_RX_MULTI to receive multicast frames in 636 * promiscuous mode. 637 */ 638 rxfilt |= RL_RXCFG_RX_MULTI; 639 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 640 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 641 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 642 return; 643 } 644 645 /* first, zot all the existing hash bits */ 646 CSR_WRITE_4(sc, RL_MAR0, 0); 647 CSR_WRITE_4(sc, RL_MAR4, 0); 648 649 /* now program new ones */ 650 IF_ADDR_LOCK(ifp); 651 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 652 if (ifma->ifma_addr->sa_family != AF_LINK) 653 continue; 654 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 655 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 656 if (h < 32) 657 hashes[0] |= (1 << h); 658 else 659 hashes[1] |= (1 << (h - 32)); 660 mcnt++; 661 } 662 IF_ADDR_UNLOCK(ifp); 663 664 if (mcnt) 665 rxfilt |= RL_RXCFG_RX_MULTI; 666 else 667 rxfilt &= ~RL_RXCFG_RX_MULTI; 668 669 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 670 671 /* 672 * For some unfathomable reason, RealTek decided to reverse 673 * the order of the multicast hash registers in the PCI Express 674 * parts. This means we have to write the hash pattern in reverse 675 * order for those devices. 676 */ 677 678 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 679 680 switch (hwrev) { 681 case RL_HWREV_8100E: 682 case RL_HWREV_8101E: 683 case RL_HWREV_8168_SPIN1: 684 case RL_HWREV_8168_SPIN2: 685 case RL_HWREV_8168_SPIN3: 686 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 687 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 688 break; 689 default: 690 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 691 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 692 break; 693 } 694} 695 696static void 697re_reset(sc) 698 struct rl_softc *sc; 699{ 700 register int i; 701 702 RL_LOCK_ASSERT(sc); 703 704 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 705 706 for (i = 0; i < RL_TIMEOUT; i++) { 707 DELAY(10); 708 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 709 break; 710 } 711 if (i == RL_TIMEOUT) 712 device_printf(sc->rl_dev, "reset never completed!\n"); 713 714 CSR_WRITE_1(sc, 0x82, 1); 715} 716 717#ifdef RE_DIAG 718 719/* 720 * The following routine is designed to test for a defect on some 721 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 722 * lines connected to the bus, however for a 32-bit only card, they 723 * should be pulled high. The result of this defect is that the 724 * NIC will not work right if you plug it into a 64-bit slot: DMA 725 * operations will be done with 64-bit transfers, which will fail 726 * because the 64-bit data lines aren't connected. 727 * 728 * There's no way to work around this (short of talking a soldering 729 * iron to the board), however we can detect it. The method we use 730 * here is to put the NIC into digital loopback mode, set the receiver 731 * to promiscuous mode, and then try to send a frame. We then compare 732 * the frame data we sent to what was received. If the data matches, 733 * then the NIC is working correctly, otherwise we know the user has 734 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 735 * slot. In the latter case, there's no way the NIC can work correctly, 736 * so we print out a message on the console and abort the device attach. 737 */ 738 739static int 740re_diag(sc) 741 struct rl_softc *sc; 742{ 743 struct ifnet *ifp = sc->rl_ifp; 744 struct mbuf *m0; 745 struct ether_header *eh; 746 struct rl_desc *cur_rx; 747 u_int16_t status; 748 u_int32_t rxstat; 749 int total_len, i, error = 0, phyaddr; 750 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 751 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 752 753 /* Allocate a single mbuf */ 754 MGETHDR(m0, M_DONTWAIT, MT_DATA); 755 if (m0 == NULL) 756 return (ENOBUFS); 757 758 RL_LOCK(sc); 759 760 /* 761 * Initialize the NIC in test mode. This sets the chip up 762 * so that it can send and receive frames, but performs the 763 * following special functions: 764 * - Puts receiver in promiscuous mode 765 * - Enables digital loopback mode 766 * - Leaves interrupts turned off 767 */ 768 769 ifp->if_flags |= IFF_PROMISC; 770 sc->rl_testmode = 1; 771 re_reset(sc); 772 re_init_locked(sc); 773 sc->rl_link = 1; 774 if (sc->rl_type == RL_8169) 775 phyaddr = 1; 776 else 777 phyaddr = 0; 778 779 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 780 for (i = 0; i < RL_TIMEOUT; i++) { 781 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 782 if (!(status & BMCR_RESET)) 783 break; 784 } 785 786 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 787 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 788 789 DELAY(100000); 790 791 /* Put some data in the mbuf */ 792 793 eh = mtod(m0, struct ether_header *); 794 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 795 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 796 eh->ether_type = htons(ETHERTYPE_IP); 797 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 798 799 /* 800 * Queue the packet, start transmission. 801 * Note: IF_HANDOFF() ultimately calls re_start() for us. 802 */ 803 804 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 805 RL_UNLOCK(sc); 806 /* XXX: re_diag must not be called when in ALTQ mode */ 807 IF_HANDOFF(&ifp->if_snd, m0, ifp); 808 RL_LOCK(sc); 809 m0 = NULL; 810 811 /* Wait for it to propagate through the chip */ 812 813 DELAY(100000); 814 for (i = 0; i < RL_TIMEOUT; i++) { 815 status = CSR_READ_2(sc, RL_ISR); 816 CSR_WRITE_2(sc, RL_ISR, status); 817 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 818 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 819 break; 820 DELAY(10); 821 } 822 823 if (i == RL_TIMEOUT) { 824 device_printf(sc->rl_dev, 825 "diagnostic failed, failed to receive packet in" 826 " loopback mode\n"); 827 error = EIO; 828 goto done; 829 } 830 831 /* 832 * The packet should have been dumped into the first 833 * entry in the RX DMA ring. Grab it from there. 834 */ 835 836 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 837 sc->rl_ldata.rl_rx_list_map, 838 BUS_DMASYNC_POSTREAD); 839 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 840 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 841 BUS_DMASYNC_POSTREAD); 842 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 843 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 844 845 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 846 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 847 eh = mtod(m0, struct ether_header *); 848 849 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 850 total_len = RL_RXBYTES(cur_rx); 851 rxstat = le32toh(cur_rx->rl_cmdstat); 852 853 if (total_len != ETHER_MIN_LEN) { 854 device_printf(sc->rl_dev, 855 "diagnostic failed, received short packet\n"); 856 error = EIO; 857 goto done; 858 } 859 860 /* Test that the received packet data matches what we sent. */ 861 862 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 863 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 864 ntohs(eh->ether_type) != ETHERTYPE_IP) { 865 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 866 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 867 dst, ":", src, ":", ETHERTYPE_IP); 868 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 869 eh->ether_dhost, ":", eh->ether_shost, ":", 870 ntohs(eh->ether_type)); 871 device_printf(sc->rl_dev, "You may have a defective 32-bit " 872 "NIC plugged into a 64-bit PCI slot.\n"); 873 device_printf(sc->rl_dev, "Please re-install the NIC in a " 874 "32-bit slot for proper operation.\n"); 875 device_printf(sc->rl_dev, "Read the re(4) man page for more " 876 "details.\n"); 877 error = EIO; 878 } 879 880done: 881 /* Turn interface off, release resources */ 882 883 sc->rl_testmode = 0; 884 sc->rl_link = 0; 885 ifp->if_flags &= ~IFF_PROMISC; 886 re_stop(sc); 887 if (m0 != NULL) 888 m_freem(m0); 889 890 RL_UNLOCK(sc); 891 892 return (error); 893} 894 895#endif 896 897/* 898 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 899 * IDs against our list and return a device name if we find a match. 900 */ 901static int 902re_probe(dev) 903 device_t dev; 904{ 905 struct rl_type *t; 906 uint16_t devid, vendor; 907 uint16_t revid, sdevid; 908 int i; 909 910 vendor = pci_get_vendor(dev); 911 devid = pci_get_device(dev); 912 revid = pci_get_revid(dev); 913 sdevid = pci_get_subdevice(dev); 914 915 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 916 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 917 /* 918 * Only attach to rev. 3 of the Linksys EG1032 adapter. 919 * Rev. 2 is supported by sk(4). 920 */ 921 return (ENXIO); 922 } 923 } 924 925 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 926 if (revid != 0x20) { 927 /* 8139, let rl(4) take care of this device. */ 928 return (ENXIO); 929 } 930 } 931 932 t = re_devs; 933 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 934 if (vendor == t->rl_vid && devid == t->rl_did) { 935 device_set_desc(dev, t->rl_name); 936 return (BUS_PROBE_DEFAULT); 937 } 938 } 939 940 return (ENXIO); 941} 942 943/* 944 * Map a single buffer address. 945 */ 946 947static void 948re_dma_map_addr(arg, segs, nseg, error) 949 void *arg; 950 bus_dma_segment_t *segs; 951 int nseg; 952 int error; 953{ 954 bus_addr_t *addr; 955 956 if (error) 957 return; 958 959 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 960 addr = arg; 961 *addr = segs->ds_addr; 962} 963 964static int 965re_allocmem(dev, sc) 966 device_t dev; 967 struct rl_softc *sc; 968{ 969 bus_size_t rx_list_size, tx_list_size; 970 int error; 971 int i; 972 973 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 974 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 975 976 /* 977 * Allocate the parent bus DMA tag appropriate for PCI. 978 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 979 * register should be set. However some RealTek chips are known 980 * to be buggy on DAC handling, therefore disable DAC by limiting 981 * DMA address space to 32bit. PCIe variants of RealTek chips 982 * may not have the limitation but I took safer path. 983 */ 984 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 985 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 986 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 987 NULL, NULL, &sc->rl_parent_tag); 988 if (error) { 989 device_printf(dev, "could not allocate parent DMA tag\n"); 990 return (error); 991 } 992 993 /* 994 * Allocate map for TX mbufs. 995 */ 996 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 997 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 998 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 999 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1000 if (error) { 1001 device_printf(dev, "could not allocate TX DMA tag\n"); 1002 return (error); 1003 } 1004 1005 /* 1006 * Allocate map for RX mbufs. 1007 */ 1008 1009 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1010 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1011 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1012 if (error) { 1013 device_printf(dev, "could not allocate RX DMA tag\n"); 1014 return (error); 1015 } 1016 1017 /* 1018 * Allocate map for TX descriptor list. 1019 */ 1020 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1021 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1022 NULL, tx_list_size, 1, tx_list_size, 0, 1023 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1024 if (error) { 1025 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1026 return (error); 1027 } 1028 1029 /* Allocate DMA'able memory for the TX ring */ 1030 1031 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1032 (void **)&sc->rl_ldata.rl_tx_list, 1033 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1034 &sc->rl_ldata.rl_tx_list_map); 1035 if (error) { 1036 device_printf(dev, "could not allocate TX DMA ring\n"); 1037 return (error); 1038 } 1039 1040 /* Load the map for the TX ring. */ 1041 1042 sc->rl_ldata.rl_tx_list_addr = 0; 1043 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1044 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1045 tx_list_size, re_dma_map_addr, 1046 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1047 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1048 device_printf(dev, "could not load TX DMA ring\n"); 1049 return (ENOMEM); 1050 } 1051 1052 /* Create DMA maps for TX buffers */ 1053 1054 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1055 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1056 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1057 if (error) { 1058 device_printf(dev, "could not create DMA map for TX\n"); 1059 return (error); 1060 } 1061 } 1062 1063 /* 1064 * Allocate map for RX descriptor list. 1065 */ 1066 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1067 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1068 NULL, rx_list_size, 1, rx_list_size, 0, 1069 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1070 if (error) { 1071 device_printf(dev, "could not create RX DMA ring tag\n"); 1072 return (error); 1073 } 1074 1075 /* Allocate DMA'able memory for the RX ring */ 1076 1077 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1078 (void **)&sc->rl_ldata.rl_rx_list, 1079 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1080 &sc->rl_ldata.rl_rx_list_map); 1081 if (error) { 1082 device_printf(dev, "could not allocate RX DMA ring\n"); 1083 return (error); 1084 } 1085 1086 /* Load the map for the RX ring. */ 1087 1088 sc->rl_ldata.rl_rx_list_addr = 0; 1089 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1090 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1091 rx_list_size, re_dma_map_addr, 1092 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1093 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1094 device_printf(dev, "could not load RX DMA ring\n"); 1095 return (ENOMEM); 1096 } 1097 1098 /* Create DMA maps for RX buffers */ 1099 1100 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1101 &sc->rl_ldata.rl_rx_sparemap); 1102 if (error) { 1103 device_printf(dev, "could not create spare DMA map for RX\n"); 1104 return (error); 1105 } 1106 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1107 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1108 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1109 if (error) { 1110 device_printf(dev, "could not create DMA map for RX\n"); 1111 return (error); 1112 } 1113 } 1114 1115 return (0); 1116} 1117 1118/* 1119 * Attach the interface. Allocate softc structures, do ifmedia 1120 * setup and ethernet/BPF attach. 1121 */ 1122static int 1123re_attach(dev) 1124 device_t dev; 1125{ 1126 u_char eaddr[ETHER_ADDR_LEN]; 1127 u_int16_t as[ETHER_ADDR_LEN / 2]; 1128 struct rl_softc *sc; 1129 struct ifnet *ifp; 1130 struct rl_hwrev *hw_rev; 1131 int hwrev; 1132 u_int16_t re_did = 0; 1133 int error = 0, rid, i; 1134 int msic, reg; 1135 uint8_t cfg; 1136 1137 sc = device_get_softc(dev); 1138 sc->rl_dev = dev; 1139 1140 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1141 MTX_DEF); 1142 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1143 1144 /* 1145 * Map control/status registers. 1146 */ 1147 pci_enable_busmaster(dev); 1148 1149 rid = RL_RID; 1150 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1151 RF_ACTIVE); 1152 1153 if (sc->rl_res == NULL) { 1154 device_printf(dev, "couldn't map ports/memory\n"); 1155 error = ENXIO; 1156 goto fail; 1157 } 1158 1159 sc->rl_btag = rman_get_bustag(sc->rl_res); 1160 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1161 1162 msic = 0; 1163 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1164 msic = pci_msi_count(dev); 1165 if (bootverbose) 1166 device_printf(dev, "MSI count : %d\n", msic); 1167 } 1168 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1169 if (pci_alloc_msi(dev, &msic) == 0) { 1170 if (msic == RL_MSI_MESSAGES) { 1171 device_printf(dev, "Using %d MSI messages\n", 1172 msic); 1173 sc->rl_msi = 1; 1174 /* Explicitly set MSI enable bit. */ 1175 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1176 cfg = CSR_READ_1(sc, RL_CFG2); 1177 cfg |= RL_CFG2_MSI; 1178 CSR_WRITE_1(sc, RL_CFG2, cfg); 1179 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1180 } else 1181 pci_release_msi(dev); 1182 } 1183 } 1184 1185 /* Allocate interrupt */ 1186 if (sc->rl_msi == 0) { 1187 rid = 0; 1188 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1189 RF_SHAREABLE | RF_ACTIVE); 1190 if (sc->rl_irq[0] == NULL) { 1191 device_printf(dev, "couldn't allocate IRQ resources\n"); 1192 error = ENXIO; 1193 goto fail; 1194 } 1195 } else { 1196 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1197 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1198 SYS_RES_IRQ, &rid, RF_ACTIVE); 1199 if (sc->rl_irq[i] == NULL) { 1200 device_printf(dev, 1201 "couldn't llocate IRQ resources for " 1202 "message %d\n", rid); 1203 error = ENXIO; 1204 goto fail; 1205 } 1206 } 1207 } 1208 1209 /* Reset the adapter. */ 1210 RL_LOCK(sc); 1211 re_reset(sc); 1212 RL_UNLOCK(sc); 1213 1214 hw_rev = re_hwrevs; 1215 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1216 while (hw_rev->rl_desc != NULL) { 1217 if (hw_rev->rl_rev == hwrev) { 1218 sc->rl_type = hw_rev->rl_type; 1219 break; 1220 } 1221 hw_rev++; 1222 } 1223 if (hw_rev->rl_desc == NULL) { 1224 device_printf(dev, "Unknown H/W revision: %08x\n", hwrev); 1225 error = ENXIO; 1226 goto fail; 1227 } 1228 1229 sc->rl_eewidth = RL_9356_ADDR_LEN; 1230 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1231 if (re_did != 0x8129) 1232 sc->rl_eewidth = RL_9346_ADDR_LEN; 1233 1234 /* 1235 * Get station address from the EEPROM. 1236 */ 1237 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1238 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1239 as[i] = le16toh(as[i]); 1240 bcopy(as, eaddr, sizeof(eaddr)); 1241 1242 if (sc->rl_type == RL_8169) { 1243 /* Set RX length mask and number of descriptors. */ 1244 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1245 sc->rl_txstart = RL_GTXSTART; 1246 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1247 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1248 } else { 1249 /* Set RX length mask and number of descriptors. */ 1250 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1251 sc->rl_txstart = RL_TXSTART; 1252 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1253 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1254 } 1255 1256 error = re_allocmem(dev, sc); 1257 if (error) 1258 goto fail; 1259 1260 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1261 if (ifp == NULL) { 1262 device_printf(dev, "can not if_alloc()\n"); 1263 error = ENOSPC; 1264 goto fail; 1265 } 1266 1267 /* Do MII setup */ 1268 if (mii_phy_probe(dev, &sc->rl_miibus, 1269 re_ifmedia_upd, re_ifmedia_sts)) { 1270 device_printf(dev, "MII without any phy!\n"); 1271 error = ENXIO; 1272 goto fail; 1273 } 1274 1275 /* Take PHY out of power down mode. */ 1276 if (sc->rl_type == RL_8169) { 1277 uint32_t rev; 1278 1279 rev = CSR_READ_4(sc, RL_TXCFG); 1280 /* HWVERID 0, 1 and 2 : bit26-30, bit23 */ 1281 rev &= 0x7c800000; 1282 if (rev != 0) { 1283 /* RTL8169S single chip */ 1284 switch (rev) { 1285 case RL_HWREV_8169_8110SB: 1286 case RL_HWREV_8169_8110SC: 1287 case RL_HWREV_8168_SPIN2: 1288 case RL_HWREV_8168_SPIN3: 1289 re_gmii_writereg(dev, 1, 0x1f, 0); 1290 re_gmii_writereg(dev, 1, 0x0e, 0); 1291 break; 1292 default: 1293 break; 1294 } 1295 } 1296 } 1297 1298 ifp->if_softc = sc; 1299 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1300 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1301 ifp->if_ioctl = re_ioctl; 1302 ifp->if_start = re_start; 1303 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1304 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1305 ifp->if_capenable = ifp->if_capabilities; 1306 ifp->if_init = re_init; 1307 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1308 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1309 IFQ_SET_READY(&ifp->if_snd); 1310 1311 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1312 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1313 1314 /* 1315 * Call MI attach routine. 1316 */ 1317 ether_ifattach(ifp, eaddr); 1318 1319 /* VLAN capability setup */ 1320 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1321 if (ifp->if_capabilities & IFCAP_HWCSUM) 1322 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1323 /* Enable WOL if PM is supported. */ 1324 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1325 ifp->if_capabilities |= IFCAP_WOL; 1326 ifp->if_capenable = ifp->if_capabilities; 1327#ifdef DEVICE_POLLING 1328 ifp->if_capabilities |= IFCAP_POLLING; 1329#endif 1330 /* 1331 * Tell the upper layer(s) we support long frames. 1332 * Must appear after the call to ether_ifattach() because 1333 * ether_ifattach() sets ifi_hdrlen to the default value. 1334 */ 1335 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1336 1337#ifdef RE_DIAG 1338 /* 1339 * Perform hardware diagnostic on the original RTL8169. 1340 * Some 32-bit cards were incorrectly wired and would 1341 * malfunction if plugged into a 64-bit slot. 1342 */ 1343 1344 if (hwrev == RL_HWREV_8169) { 1345 error = re_diag(sc); 1346 if (error) { 1347 device_printf(dev, 1348 "attach aborted due to hardware diag failure\n"); 1349 ether_ifdetach(ifp); 1350 goto fail; 1351 } 1352 } 1353#endif 1354 1355 /* Hook interrupt last to avoid having to lock softc */ 1356 if (sc->rl_msi == 0) 1357 error = bus_setup_intr(dev, sc->rl_irq[0], 1358 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1359 &sc->rl_intrhand[0]); 1360 else { 1361 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1362 error = bus_setup_intr(dev, sc->rl_irq[i], 1363 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1364 &sc->rl_intrhand[i]); 1365 if (error != 0) 1366 break; 1367 } 1368 } 1369 if (error) { 1370 device_printf(dev, "couldn't set up irq\n"); 1371 ether_ifdetach(ifp); 1372 } 1373 1374fail: 1375 1376 if (error) 1377 re_detach(dev); 1378 1379 return (error); 1380} 1381 1382/* 1383 * Shutdown hardware and free up resources. This can be called any 1384 * time after the mutex has been initialized. It is called in both 1385 * the error case in attach and the normal detach case so it needs 1386 * to be careful about only freeing resources that have actually been 1387 * allocated. 1388 */ 1389static int 1390re_detach(dev) 1391 device_t dev; 1392{ 1393 struct rl_softc *sc; 1394 struct ifnet *ifp; 1395 int i, rid; 1396 1397 sc = device_get_softc(dev); 1398 ifp = sc->rl_ifp; 1399 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1400 1401#ifdef DEVICE_POLLING 1402 if (ifp->if_capenable & IFCAP_POLLING) 1403 ether_poll_deregister(ifp); 1404#endif 1405 /* These should only be active if attach succeeded */ 1406 if (device_is_attached(dev)) { 1407 RL_LOCK(sc); 1408#if 0 1409 sc->suspended = 1; 1410#endif 1411 re_stop(sc); 1412 RL_UNLOCK(sc); 1413 callout_drain(&sc->rl_stat_callout); 1414 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1415 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1416 /* 1417 * Force off the IFF_UP flag here, in case someone 1418 * still had a BPF descriptor attached to this 1419 * interface. If they do, ether_ifdetach() will cause 1420 * the BPF code to try and clear the promisc mode 1421 * flag, which will bubble down to re_ioctl(), 1422 * which will try to call re_init() again. This will 1423 * turn the NIC back on and restart the MII ticker, 1424 * which will panic the system when the kernel tries 1425 * to invoke the re_tick() function that isn't there 1426 * anymore. 1427 */ 1428 ifp->if_flags &= ~IFF_UP; 1429 ether_ifdetach(ifp); 1430 } 1431 if (sc->rl_miibus) 1432 device_delete_child(dev, sc->rl_miibus); 1433 bus_generic_detach(dev); 1434 1435 /* 1436 * The rest is resource deallocation, so we should already be 1437 * stopped here. 1438 */ 1439 1440 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1441 if (sc->rl_intrhand[i] != NULL) { 1442 bus_teardown_intr(dev, sc->rl_irq[i], 1443 sc->rl_intrhand[i]); 1444 sc->rl_intrhand[i] = NULL; 1445 } 1446 } 1447 if (ifp != NULL) 1448 if_free(ifp); 1449 if (sc->rl_msi == 0) { 1450 if (sc->rl_irq[0] != NULL) { 1451 bus_release_resource(dev, SYS_RES_IRQ, 0, 1452 sc->rl_irq[0]); 1453 sc->rl_irq[0] = NULL; 1454 } 1455 } else { 1456 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1457 if (sc->rl_irq[i] != NULL) { 1458 bus_release_resource(dev, SYS_RES_IRQ, rid, 1459 sc->rl_irq[i]); 1460 sc->rl_irq[i] = NULL; 1461 } 1462 } 1463 pci_release_msi(dev); 1464 } 1465 if (sc->rl_res) 1466 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1467 1468 /* Unload and free the RX DMA ring memory and map */ 1469 1470 if (sc->rl_ldata.rl_rx_list_tag) { 1471 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1472 sc->rl_ldata.rl_rx_list_map); 1473 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1474 sc->rl_ldata.rl_rx_list, 1475 sc->rl_ldata.rl_rx_list_map); 1476 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1477 } 1478 1479 /* Unload and free the TX DMA ring memory and map */ 1480 1481 if (sc->rl_ldata.rl_tx_list_tag) { 1482 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1483 sc->rl_ldata.rl_tx_list_map); 1484 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1485 sc->rl_ldata.rl_tx_list, 1486 sc->rl_ldata.rl_tx_list_map); 1487 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1488 } 1489 1490 /* Destroy all the RX and TX buffer maps */ 1491 1492 if (sc->rl_ldata.rl_tx_mtag) { 1493 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1494 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1495 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1496 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1497 } 1498 if (sc->rl_ldata.rl_rx_mtag) { 1499 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1500 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1501 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1502 if (sc->rl_ldata.rl_rx_sparemap) 1503 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1504 sc->rl_ldata.rl_rx_sparemap); 1505 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1506 } 1507 1508 /* Unload and free the stats buffer and map */ 1509 1510 if (sc->rl_ldata.rl_stag) { 1511 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1512 sc->rl_ldata.rl_rx_list_map); 1513 bus_dmamem_free(sc->rl_ldata.rl_stag, 1514 sc->rl_ldata.rl_stats, 1515 sc->rl_ldata.rl_smap); 1516 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1517 } 1518 1519 if (sc->rl_parent_tag) 1520 bus_dma_tag_destroy(sc->rl_parent_tag); 1521 1522 mtx_destroy(&sc->rl_mtx); 1523 1524 return (0); 1525} 1526 1527static __inline void 1528re_discard_rxbuf(sc, idx) 1529 struct rl_softc *sc; 1530 int idx; 1531{ 1532 struct rl_desc *desc; 1533 struct rl_rxdesc *rxd; 1534 uint32_t cmdstat; 1535 1536 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1537 desc = &sc->rl_ldata.rl_rx_list[idx]; 1538 desc->rl_vlanctl = 0; 1539 cmdstat = rxd->rx_size; 1540 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1541 cmdstat |= RL_RDESC_CMD_EOR; 1542 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1543} 1544 1545static int 1546re_newbuf(sc, idx) 1547 struct rl_softc *sc; 1548 int idx; 1549{ 1550 struct mbuf *m; 1551 struct rl_rxdesc *rxd; 1552 bus_dma_segment_t segs[1]; 1553 bus_dmamap_t map; 1554 struct rl_desc *desc; 1555 uint32_t cmdstat; 1556 int error, nsegs; 1557 1558 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1559 if (m == NULL) 1560 return (ENOBUFS); 1561 1562 m->m_len = m->m_pkthdr.len = MCLBYTES; 1563#ifdef RE_FIXUP_RX 1564 /* 1565 * This is part of an evil trick to deal with non-x86 platforms. 1566 * The RealTek chip requires RX buffers to be aligned on 64-bit 1567 * boundaries, but that will hose non-x86 machines. To get around 1568 * this, we leave some empty space at the start of each buffer 1569 * and for non-x86 hosts, we copy the buffer back six bytes 1570 * to achieve word alignment. This is slightly more efficient 1571 * than allocating a new buffer, copying the contents, and 1572 * discarding the old buffer. 1573 */ 1574 m_adj(m, RE_ETHER_ALIGN); 1575#endif 1576 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1577 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1578 if (error != 0) { 1579 m_freem(m); 1580 return (ENOBUFS); 1581 } 1582 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1583 1584 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1585 if (rxd->rx_m != NULL) { 1586 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1587 BUS_DMASYNC_POSTREAD); 1588 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1589 } 1590 1591 rxd->rx_m = m; 1592 map = rxd->rx_dmamap; 1593 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1594 rxd->rx_size = segs[0].ds_len; 1595 sc->rl_ldata.rl_rx_sparemap = map; 1596 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1597 BUS_DMASYNC_PREREAD); 1598 1599 desc = &sc->rl_ldata.rl_rx_list[idx]; 1600 desc->rl_vlanctl = 0; 1601 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1602 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1603 cmdstat = segs[0].ds_len; 1604 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1605 cmdstat |= RL_RDESC_CMD_EOR; 1606 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1607 1608 return (0); 1609} 1610 1611#ifdef RE_FIXUP_RX 1612static __inline void 1613re_fixup_rx(m) 1614 struct mbuf *m; 1615{ 1616 int i; 1617 uint16_t *src, *dst; 1618 1619 src = mtod(m, uint16_t *); 1620 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1621 1622 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1623 *dst++ = *src++; 1624 1625 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1626 1627 return; 1628} 1629#endif 1630 1631static int 1632re_tx_list_init(sc) 1633 struct rl_softc *sc; 1634{ 1635 struct rl_desc *desc; 1636 int i; 1637 1638 RL_LOCK_ASSERT(sc); 1639 1640 bzero(sc->rl_ldata.rl_tx_list, 1641 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1642 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1643 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1644 /* Set EOR. */ 1645 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1646 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1647 1648 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1649 sc->rl_ldata.rl_tx_list_map, 1650 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1651 1652 sc->rl_ldata.rl_tx_prodidx = 0; 1653 sc->rl_ldata.rl_tx_considx = 0; 1654 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1655 1656 return (0); 1657} 1658 1659static int 1660re_rx_list_init(sc) 1661 struct rl_softc *sc; 1662{ 1663 int error, i; 1664 1665 bzero(sc->rl_ldata.rl_rx_list, 1666 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1667 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1668 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1669 if ((error = re_newbuf(sc, i)) != 0) 1670 return (error); 1671 } 1672 1673 /* Flush the RX descriptors */ 1674 1675 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1676 sc->rl_ldata.rl_rx_list_map, 1677 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1678 1679 sc->rl_ldata.rl_rx_prodidx = 0; 1680 sc->rl_head = sc->rl_tail = NULL; 1681 1682 return (0); 1683} 1684 1685/* 1686 * RX handler for C+ and 8169. For the gigE chips, we support 1687 * the reception of jumbo frames that have been fragmented 1688 * across multiple 2K mbuf cluster buffers. 1689 */ 1690static int 1691re_rxeof(sc) 1692 struct rl_softc *sc; 1693{ 1694 struct mbuf *m; 1695 struct ifnet *ifp; 1696 int i, total_len; 1697 struct rl_desc *cur_rx; 1698 u_int32_t rxstat, rxvlan; 1699 int maxpkt = 16; 1700 1701 RL_LOCK_ASSERT(sc); 1702 1703 ifp = sc->rl_ifp; 1704 1705 /* Invalidate the descriptor memory */ 1706 1707 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1708 sc->rl_ldata.rl_rx_list_map, 1709 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1710 1711 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1712 i = RL_RX_DESC_NXT(sc, i)) { 1713 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1714 rxstat = le32toh(cur_rx->rl_cmdstat); 1715 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1716 break; 1717 total_len = rxstat & sc->rl_rxlenmask; 1718 rxvlan = le32toh(cur_rx->rl_vlanctl); 1719 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1720 1721 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1722 if (re_newbuf(sc, i) != 0) { 1723 /* 1724 * If this is part of a multi-fragment packet, 1725 * discard all the pieces. 1726 */ 1727 if (sc->rl_head != NULL) { 1728 m_freem(sc->rl_head); 1729 sc->rl_head = sc->rl_tail = NULL; 1730 } 1731 re_discard_rxbuf(sc, i); 1732 continue; 1733 } 1734 m->m_len = RE_RX_DESC_BUFLEN; 1735 if (sc->rl_head == NULL) 1736 sc->rl_head = sc->rl_tail = m; 1737 else { 1738 m->m_flags &= ~M_PKTHDR; 1739 sc->rl_tail->m_next = m; 1740 sc->rl_tail = m; 1741 } 1742 continue; 1743 } 1744 1745 /* 1746 * NOTE: for the 8139C+, the frame length field 1747 * is always 12 bits in size, but for the gigE chips, 1748 * it is 13 bits (since the max RX frame length is 16K). 1749 * Unfortunately, all 32 bits in the status word 1750 * were already used, so to make room for the extra 1751 * length bit, RealTek took out the 'frame alignment 1752 * error' bit and shifted the other status bits 1753 * over one slot. The OWN, EOR, FS and LS bits are 1754 * still in the same places. We have already extracted 1755 * the frame length and checked the OWN bit, so rather 1756 * than using an alternate bit mapping, we shift the 1757 * status bits one space to the right so we can evaluate 1758 * them using the 8169 status as though it was in the 1759 * same format as that of the 8139C+. 1760 */ 1761 if (sc->rl_type == RL_8169) 1762 rxstat >>= 1; 1763 1764 /* 1765 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1766 * set, but if CRC is clear, it will still be a valid frame. 1767 */ 1768 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1769 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1770 ifp->if_ierrors++; 1771 /* 1772 * If this is part of a multi-fragment packet, 1773 * discard all the pieces. 1774 */ 1775 if (sc->rl_head != NULL) { 1776 m_freem(sc->rl_head); 1777 sc->rl_head = sc->rl_tail = NULL; 1778 } 1779 re_discard_rxbuf(sc, i); 1780 continue; 1781 } 1782 1783 /* 1784 * If allocating a replacement mbuf fails, 1785 * reload the current one. 1786 */ 1787 1788 if (re_newbuf(sc, i) != 0) { 1789 ifp->if_iqdrops++; 1790 if (sc->rl_head != NULL) { 1791 m_freem(sc->rl_head); 1792 sc->rl_head = sc->rl_tail = NULL; 1793 } 1794 re_discard_rxbuf(sc, i); 1795 continue; 1796 } 1797 1798 if (sc->rl_head != NULL) { 1799 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1800 if (m->m_len == 0) 1801 m->m_len = RE_RX_DESC_BUFLEN; 1802 /* 1803 * Special case: if there's 4 bytes or less 1804 * in this buffer, the mbuf can be discarded: 1805 * the last 4 bytes is the CRC, which we don't 1806 * care about anyway. 1807 */ 1808 if (m->m_len <= ETHER_CRC_LEN) { 1809 sc->rl_tail->m_len -= 1810 (ETHER_CRC_LEN - m->m_len); 1811 m_freem(m); 1812 } else { 1813 m->m_len -= ETHER_CRC_LEN; 1814 m->m_flags &= ~M_PKTHDR; 1815 sc->rl_tail->m_next = m; 1816 } 1817 m = sc->rl_head; 1818 sc->rl_head = sc->rl_tail = NULL; 1819 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1820 } else 1821 m->m_pkthdr.len = m->m_len = 1822 (total_len - ETHER_CRC_LEN); 1823 1824#ifdef RE_FIXUP_RX 1825 re_fixup_rx(m); 1826#endif 1827 ifp->if_ipackets++; 1828 m->m_pkthdr.rcvif = ifp; 1829 1830 /* Do RX checksumming if enabled */ 1831 1832 if (ifp->if_capenable & IFCAP_RXCSUM) { 1833 1834 /* Check IP header checksum */ 1835 if (rxstat & RL_RDESC_STAT_PROTOID) 1836 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1837 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1838 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1839 1840 /* Check TCP/UDP checksum */ 1841 if ((RL_TCPPKT(rxstat) && 1842 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1843 (RL_UDPPKT(rxstat) && 1844 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1845 m->m_pkthdr.csum_flags |= 1846 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1847 m->m_pkthdr.csum_data = 0xffff; 1848 } 1849 } 1850 maxpkt--; 1851 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1852 m->m_pkthdr.ether_vtag = 1853 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1854 m->m_flags |= M_VLANTAG; 1855 } 1856 RL_UNLOCK(sc); 1857 (*ifp->if_input)(ifp, m); 1858 RL_LOCK(sc); 1859 } 1860 1861 /* Flush the RX DMA ring */ 1862 1863 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1864 sc->rl_ldata.rl_rx_list_map, 1865 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1866 1867 sc->rl_ldata.rl_rx_prodidx = i; 1868 1869 if (maxpkt) 1870 return(EAGAIN); 1871 1872 return(0); 1873} 1874 1875static void 1876re_txeof(sc) 1877 struct rl_softc *sc; 1878{ 1879 struct ifnet *ifp; 1880 struct rl_txdesc *txd; 1881 u_int32_t txstat; 1882 int cons; 1883 1884 cons = sc->rl_ldata.rl_tx_considx; 1885 if (cons == sc->rl_ldata.rl_tx_prodidx) 1886 return; 1887 1888 ifp = sc->rl_ifp; 1889 /* Invalidate the TX descriptor list */ 1890 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1891 sc->rl_ldata.rl_tx_list_map, 1892 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1893 1894 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1895 cons = RL_TX_DESC_NXT(sc, cons)) { 1896 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1897 if (txstat & RL_TDESC_STAT_OWN) 1898 break; 1899 /* 1900 * We only stash mbufs in the last descriptor 1901 * in a fragment chain, which also happens to 1902 * be the only place where the TX status bits 1903 * are valid. 1904 */ 1905 if (txstat & RL_TDESC_CMD_EOF) { 1906 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1907 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1908 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1909 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1910 txd->tx_dmamap); 1911 KASSERT(txd->tx_m != NULL, 1912 ("%s: freeing NULL mbufs!", __func__)); 1913 m_freem(txd->tx_m); 1914 txd->tx_m = NULL; 1915 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1916 RL_TDESC_STAT_COLCNT)) 1917 ifp->if_collisions++; 1918 if (txstat & RL_TDESC_STAT_TXERRSUM) 1919 ifp->if_oerrors++; 1920 else 1921 ifp->if_opackets++; 1922 } 1923 sc->rl_ldata.rl_tx_free++; 1924 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1925 } 1926 sc->rl_ldata.rl_tx_considx = cons; 1927 1928 /* No changes made to the TX ring, so no flush needed */ 1929 1930 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1931 /* 1932 * Some chips will ignore a second TX request issued 1933 * while an existing transmission is in progress. If 1934 * the transmitter goes idle but there are still 1935 * packets waiting to be sent, we need to restart the 1936 * channel here to flush them out. This only seems to 1937 * be required with the PCIe devices. 1938 */ 1939 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1940 1941#ifdef RE_TX_MODERATION 1942 /* 1943 * If not all descriptors have been reaped yet, reload 1944 * the timer so that we will eventually get another 1945 * interrupt that will cause us to re-enter this routine. 1946 * This is done in case the transmitter has gone idle. 1947 */ 1948 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1949#endif 1950 } else 1951 sc->rl_watchdog_timer = 0; 1952} 1953 1954static void 1955re_tick(xsc) 1956 void *xsc; 1957{ 1958 struct rl_softc *sc; 1959 struct mii_data *mii; 1960 struct ifnet *ifp; 1961 1962 sc = xsc; 1963 ifp = sc->rl_ifp; 1964 1965 RL_LOCK_ASSERT(sc); 1966 1967 re_watchdog(sc); 1968 1969 mii = device_get_softc(sc->rl_miibus); 1970 mii_tick(mii); 1971 if (sc->rl_link) { 1972 if (!(mii->mii_media_status & IFM_ACTIVE)) 1973 sc->rl_link = 0; 1974 } else { 1975 if (mii->mii_media_status & IFM_ACTIVE && 1976 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1977 sc->rl_link = 1; 1978 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1979 taskqueue_enqueue_fast(taskqueue_fast, 1980 &sc->rl_txtask); 1981 } 1982 } 1983 1984 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1985} 1986 1987#ifdef DEVICE_POLLING 1988static void 1989re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1990{ 1991 struct rl_softc *sc = ifp->if_softc; 1992 1993 RL_LOCK(sc); 1994 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1995 re_poll_locked(ifp, cmd, count); 1996 RL_UNLOCK(sc); 1997} 1998 1999static void 2000re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2001{ 2002 struct rl_softc *sc = ifp->if_softc; 2003 2004 RL_LOCK_ASSERT(sc); 2005 2006 sc->rxcycles = count; 2007 re_rxeof(sc); 2008 re_txeof(sc); 2009 2010 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2011 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2012 2013 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2014 u_int16_t status; 2015 2016 status = CSR_READ_2(sc, RL_ISR); 2017 if (status == 0xffff) 2018 return; 2019 if (status) 2020 CSR_WRITE_2(sc, RL_ISR, status); 2021 2022 /* 2023 * XXX check behaviour on receiver stalls. 2024 */ 2025 2026 if (status & RL_ISR_SYSTEM_ERR) { 2027 re_reset(sc); 2028 re_init_locked(sc); 2029 } 2030 } 2031} 2032#endif /* DEVICE_POLLING */ 2033 2034static int 2035re_intr(arg) 2036 void *arg; 2037{ 2038 struct rl_softc *sc; 2039 uint16_t status; 2040 2041 sc = arg; 2042 2043 status = CSR_READ_2(sc, RL_ISR); 2044 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2045 return (FILTER_STRAY); 2046 CSR_WRITE_2(sc, RL_IMR, 0); 2047 2048 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2049 2050 return (FILTER_HANDLED); 2051} 2052 2053static void 2054re_int_task(arg, npending) 2055 void *arg; 2056 int npending; 2057{ 2058 struct rl_softc *sc; 2059 struct ifnet *ifp; 2060 u_int16_t status; 2061 int rval = 0; 2062 2063 sc = arg; 2064 ifp = sc->rl_ifp; 2065 2066 RL_LOCK(sc); 2067 2068 status = CSR_READ_2(sc, RL_ISR); 2069 CSR_WRITE_2(sc, RL_ISR, status); 2070 2071 if (sc->suspended || 2072 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2073 RL_UNLOCK(sc); 2074 return; 2075 } 2076 2077#ifdef DEVICE_POLLING 2078 if (ifp->if_capenable & IFCAP_POLLING) { 2079 RL_UNLOCK(sc); 2080 return; 2081 } 2082#endif 2083 2084 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2085 rval = re_rxeof(sc); 2086 2087#ifdef RE_TX_MODERATION 2088 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2089#else 2090 if (status & (RL_ISR_TX_OK| 2091#endif 2092 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2093 re_txeof(sc); 2094 2095 if (status & RL_ISR_SYSTEM_ERR) { 2096 re_reset(sc); 2097 re_init_locked(sc); 2098 } 2099 2100 if (status & RL_ISR_LINKCHG) { 2101 callout_stop(&sc->rl_stat_callout); 2102 re_tick(sc); 2103 } 2104 2105 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2106 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2107 2108 RL_UNLOCK(sc); 2109 2110 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2111 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2112 return; 2113 } 2114 2115 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2116 2117 return; 2118} 2119 2120static int 2121re_encap(sc, m_head) 2122 struct rl_softc *sc; 2123 struct mbuf **m_head; 2124{ 2125 struct rl_txdesc *txd, *txd_last; 2126 bus_dma_segment_t segs[RL_NTXSEGS]; 2127 bus_dmamap_t map; 2128 struct mbuf *m_new; 2129 struct rl_desc *desc; 2130 int nsegs, prod; 2131 int i, error, ei, si; 2132 int padlen; 2133 uint32_t cmdstat, csum_flags, vlanctl; 2134 2135 RL_LOCK_ASSERT(sc); 2136 M_ASSERTPKTHDR((*m_head)); 2137 2138 /* 2139 * With some of the RealTek chips, using the checksum offload 2140 * support in conjunction with the autopadding feature results 2141 * in the transmission of corrupt frames. For example, if we 2142 * need to send a really small IP fragment that's less than 60 2143 * bytes in size, and IP header checksumming is enabled, the 2144 * resulting ethernet frame that appears on the wire will 2145 * have garbled payload. To work around this, if TX IP checksum 2146 * offload is enabled, we always manually pad short frames out 2147 * to the minimum ethernet frame size. 2148 */ 2149 if ((*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2150 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2151 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2152 if (M_WRITABLE(*m_head) == 0) { 2153 /* Get a writable copy. */ 2154 m_new = m_dup(*m_head, M_DONTWAIT); 2155 m_freem(*m_head); 2156 if (m_new == NULL) { 2157 *m_head = NULL; 2158 return (ENOBUFS); 2159 } 2160 *m_head = m_new; 2161 } 2162 if ((*m_head)->m_next != NULL || 2163 M_TRAILINGSPACE(*m_head) < padlen) { 2164 m_new = m_defrag(*m_head, M_DONTWAIT); 2165 if (m_new == NULL) { 2166 m_freem(*m_head); 2167 *m_head = NULL; 2168 return (ENOBUFS); 2169 } 2170 } else 2171 m_new = *m_head; 2172 2173 /* 2174 * Manually pad short frames, and zero the pad space 2175 * to avoid leaking data. 2176 */ 2177 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2178 m_new->m_pkthdr.len += padlen; 2179 m_new->m_len = m_new->m_pkthdr.len; 2180 *m_head = m_new; 2181 } 2182 2183 prod = sc->rl_ldata.rl_tx_prodidx; 2184 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2185 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2186 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2187 if (error == EFBIG) { 2188 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2189 if (m_new == NULL) { 2190 m_freem(*m_head); 2191 *m_head = NULL; 2192 return (ENOBUFS); 2193 } 2194 *m_head = m_new; 2195 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2196 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2197 if (error != 0) { 2198 m_freem(*m_head); 2199 *m_head = NULL; 2200 return (error); 2201 } 2202 } else if (error != 0) 2203 return (error); 2204 if (nsegs == 0) { 2205 m_freem(*m_head); 2206 *m_head = NULL; 2207 return (EIO); 2208 } 2209 2210 /* Check for number of available descriptors. */ 2211 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2212 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2213 return (ENOBUFS); 2214 } 2215 2216 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2217 BUS_DMASYNC_PREWRITE); 2218 2219 /* 2220 * Set up checksum offload. Note: checksum offload bits must 2221 * appear in all descriptors of a multi-descriptor transmit 2222 * attempt. This is according to testing done with an 8169 2223 * chip. This is a requirement. 2224 */ 2225 csum_flags = 0; 2226 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2227 csum_flags = RL_TDESC_CMD_LGSEND | 2228 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2229 RL_TDESC_CMD_MSSVAL_SHIFT); 2230 else { 2231 /* 2232 * Unconditionally enable IP checksum if TCP or UDP 2233 * checksum is required. Otherwise, TCP/UDP checksum 2234 * does't make effects. 2235 */ 2236 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2237 csum_flags |= RL_TDESC_CMD_IPCSUM; 2238 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2239 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2240 if (((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2241 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2242 } 2243 } 2244 2245 /* 2246 * Set up hardware VLAN tagging. Note: vlan tag info must 2247 * appear in all descriptors of a multi-descriptor 2248 * transmission attempt. 2249 */ 2250 vlanctl = 0; 2251 if ((*m_head)->m_flags & M_VLANTAG) 2252 vlanctl = 2253 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2254 RL_TDESC_VLANCTL_TAG); 2255 2256 si = prod; 2257 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2258 desc = &sc->rl_ldata.rl_tx_list[prod]; 2259 desc->rl_vlanctl = vlanctl; 2260 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2261 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2262 cmdstat = segs[i].ds_len; 2263 if (i != 0) 2264 cmdstat |= RL_TDESC_CMD_OWN; 2265 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2266 cmdstat |= RL_TDESC_CMD_EOR; 2267 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2268 sc->rl_ldata.rl_tx_free--; 2269 } 2270 /* Update producer index. */ 2271 sc->rl_ldata.rl_tx_prodidx = prod; 2272 2273 /* Set EOF on the last descriptor. */ 2274 ei = RL_TX_DESC_PRV(sc, prod); 2275 desc = &sc->rl_ldata.rl_tx_list[ei]; 2276 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2277 2278 desc = &sc->rl_ldata.rl_tx_list[si]; 2279 /* Set SOF and transfer ownership of packet to the chip. */ 2280 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2281 2282 /* 2283 * Insure that the map for this transmission 2284 * is placed at the array index of the last descriptor 2285 * in this chain. (Swap last and first dmamaps.) 2286 */ 2287 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2288 map = txd->tx_dmamap; 2289 txd->tx_dmamap = txd_last->tx_dmamap; 2290 txd_last->tx_dmamap = map; 2291 txd_last->tx_m = *m_head; 2292 2293 return (0); 2294} 2295 2296static void 2297re_tx_task(arg, npending) 2298 void *arg; 2299 int npending; 2300{ 2301 struct ifnet *ifp; 2302 2303 ifp = arg; 2304 re_start(ifp); 2305 2306 return; 2307} 2308 2309/* 2310 * Main transmit routine for C+ and gigE NICs. 2311 */ 2312static void 2313re_start(ifp) 2314 struct ifnet *ifp; 2315{ 2316 struct rl_softc *sc; 2317 struct mbuf *m_head; 2318 int queued; 2319 2320 sc = ifp->if_softc; 2321 2322 RL_LOCK(sc); 2323 2324 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2325 IFF_DRV_RUNNING || sc->rl_link == 0) { 2326 RL_UNLOCK(sc); 2327 return; 2328 } 2329 2330 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2331 sc->rl_ldata.rl_tx_free > 1;) { 2332 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2333 if (m_head == NULL) 2334 break; 2335 2336 if (re_encap(sc, &m_head) != 0) { 2337 if (m_head == NULL) 2338 break; 2339 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2340 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2341 break; 2342 } 2343 2344 /* 2345 * If there's a BPF listener, bounce a copy of this frame 2346 * to him. 2347 */ 2348 ETHER_BPF_MTAP(ifp, m_head); 2349 2350 queued++; 2351 } 2352 2353 if (queued == 0) { 2354#ifdef RE_TX_MODERATION 2355 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2356 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2357#endif 2358 RL_UNLOCK(sc); 2359 return; 2360 } 2361 2362 /* Flush the TX descriptors */ 2363 2364 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2365 sc->rl_ldata.rl_tx_list_map, 2366 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2367 2368 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2369 2370#ifdef RE_TX_MODERATION 2371 /* 2372 * Use the countdown timer for interrupt moderation. 2373 * 'TX done' interrupts are disabled. Instead, we reset the 2374 * countdown timer, which will begin counting until it hits 2375 * the value in the TIMERINT register, and then trigger an 2376 * interrupt. Each time we write to the TIMERCNT register, 2377 * the timer count is reset to 0. 2378 */ 2379 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2380#endif 2381 2382 /* 2383 * Set a timeout in case the chip goes out to lunch. 2384 */ 2385 sc->rl_watchdog_timer = 5; 2386 2387 RL_UNLOCK(sc); 2388 2389 return; 2390} 2391 2392static void 2393re_init(xsc) 2394 void *xsc; 2395{ 2396 struct rl_softc *sc = xsc; 2397 2398 RL_LOCK(sc); 2399 re_init_locked(sc); 2400 RL_UNLOCK(sc); 2401} 2402 2403static void 2404re_init_locked(sc) 2405 struct rl_softc *sc; 2406{ 2407 struct ifnet *ifp = sc->rl_ifp; 2408 struct mii_data *mii; 2409 u_int32_t rxcfg = 0; 2410 uint16_t cfg; 2411 union { 2412 uint32_t align_dummy; 2413 u_char eaddr[ETHER_ADDR_LEN]; 2414 } eaddr; 2415 2416 RL_LOCK_ASSERT(sc); 2417 2418 mii = device_get_softc(sc->rl_miibus); 2419 2420 /* 2421 * Cancel pending I/O and free all RX/TX buffers. 2422 */ 2423 re_stop(sc); 2424 2425 /* 2426 * Enable C+ RX and TX mode, as well as VLAN stripping and 2427 * RX checksum offload. We must configure the C+ register 2428 * before all others. 2429 */ 2430 cfg = RL_CPLUSCMD_PCI_MRW; 2431 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2432 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2433 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2434 cfg |= RL_CPLUSCMD_VLANSTRIP; 2435 CSR_WRITE_2(sc, RL_CPLUS_CMD, 2436 cfg | RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB); 2437 2438 /* 2439 * Init our MAC address. Even though the chipset 2440 * documentation doesn't mention it, we need to enter "Config 2441 * register write enable" mode to modify the ID registers. 2442 */ 2443 /* Copy MAC address on stack to align. */ 2444 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2445 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2446 CSR_WRITE_4(sc, RL_IDR0, 2447 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2448 CSR_WRITE_4(sc, RL_IDR4, 2449 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2450 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2451 2452 /* 2453 * For C+ mode, initialize the RX descriptors and mbufs. 2454 */ 2455 re_rx_list_init(sc); 2456 re_tx_list_init(sc); 2457 2458 /* 2459 * Load the addresses of the RX and TX lists into the chip. 2460 */ 2461 2462 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2463 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2464 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2465 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2466 2467 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2468 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2469 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2470 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2471 2472 /* 2473 * Enable transmit and receive. 2474 */ 2475 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2476 2477 /* 2478 * Set the initial TX and RX configuration. 2479 */ 2480 if (sc->rl_testmode) { 2481 if (sc->rl_type == RL_8169) 2482 CSR_WRITE_4(sc, RL_TXCFG, 2483 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2484 else 2485 CSR_WRITE_4(sc, RL_TXCFG, 2486 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2487 } else 2488 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2489 2490 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2491 2492 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2493 2494 /* Set the individual bit to receive frames for this host only. */ 2495 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2496 rxcfg |= RL_RXCFG_RX_INDIV; 2497 2498 /* If we want promiscuous mode, set the allframes bit. */ 2499 if (ifp->if_flags & IFF_PROMISC) 2500 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2501 else 2502 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2503 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2504 2505 /* 2506 * Set capture broadcast bit to capture broadcast frames. 2507 */ 2508 if (ifp->if_flags & IFF_BROADCAST) 2509 rxcfg |= RL_RXCFG_RX_BROAD; 2510 else 2511 rxcfg &= ~RL_RXCFG_RX_BROAD; 2512 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2513 2514 /* 2515 * Program the multicast filter, if necessary. 2516 */ 2517 re_setmulti(sc); 2518 2519#ifdef DEVICE_POLLING 2520 /* 2521 * Disable interrupts if we are polling. 2522 */ 2523 if (ifp->if_capenable & IFCAP_POLLING) 2524 CSR_WRITE_2(sc, RL_IMR, 0); 2525 else /* otherwise ... */ 2526#endif 2527 2528 /* 2529 * Enable interrupts. 2530 */ 2531 if (sc->rl_testmode) 2532 CSR_WRITE_2(sc, RL_IMR, 0); 2533 else 2534 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2535 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2536 2537 /* Set initial TX threshold */ 2538 sc->rl_txthresh = RL_TX_THRESH_INIT; 2539 2540 /* Start RX/TX process. */ 2541 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2542#ifdef notdef 2543 /* Enable receiver and transmitter. */ 2544 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2545#endif 2546 2547#ifdef RE_TX_MODERATION 2548 /* 2549 * Initialize the timer interrupt register so that 2550 * a timer interrupt will be generated once the timer 2551 * reaches a certain number of ticks. The timer is 2552 * reloaded on each transmit. This gives us TX interrupt 2553 * moderation, which dramatically improves TX frame rate. 2554 */ 2555 if (sc->rl_type == RL_8169) 2556 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2557 else 2558 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2559#endif 2560 2561 /* 2562 * For 8169 gigE NICs, set the max allowed RX packet 2563 * size so we can receive jumbo frames. 2564 */ 2565 if (sc->rl_type == RL_8169) 2566 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2567 2568 if (sc->rl_testmode) 2569 return; 2570 2571 mii_mediachg(mii); 2572 2573 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2574 2575 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2576 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2577 2578 sc->rl_link = 0; 2579 sc->rl_watchdog_timer = 0; 2580 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2581} 2582 2583/* 2584 * Set media options. 2585 */ 2586static int 2587re_ifmedia_upd(ifp) 2588 struct ifnet *ifp; 2589{ 2590 struct rl_softc *sc; 2591 struct mii_data *mii; 2592 2593 sc = ifp->if_softc; 2594 mii = device_get_softc(sc->rl_miibus); 2595 RL_LOCK(sc); 2596 mii_mediachg(mii); 2597 RL_UNLOCK(sc); 2598 2599 return (0); 2600} 2601 2602/* 2603 * Report current media status. 2604 */ 2605static void 2606re_ifmedia_sts(ifp, ifmr) 2607 struct ifnet *ifp; 2608 struct ifmediareq *ifmr; 2609{ 2610 struct rl_softc *sc; 2611 struct mii_data *mii; 2612 2613 sc = ifp->if_softc; 2614 mii = device_get_softc(sc->rl_miibus); 2615 2616 RL_LOCK(sc); 2617 mii_pollstat(mii); 2618 RL_UNLOCK(sc); 2619 ifmr->ifm_active = mii->mii_media_active; 2620 ifmr->ifm_status = mii->mii_media_status; 2621} 2622 2623static int 2624re_ioctl(ifp, command, data) 2625 struct ifnet *ifp; 2626 u_long command; 2627 caddr_t data; 2628{ 2629 struct rl_softc *sc = ifp->if_softc; 2630 struct ifreq *ifr = (struct ifreq *) data; 2631 struct mii_data *mii; 2632 int error = 0; 2633 2634 switch (command) { 2635 case SIOCSIFMTU: 2636 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2637 error = EINVAL; 2638 break; 2639 } 2640 if (sc->rl_type == RL_8139CPLUS && 2641 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2642 error = EINVAL; 2643 break; 2644 } 2645 RL_LOCK(sc); 2646 if (ifp->if_mtu != ifr->ifr_mtu) 2647 ifp->if_mtu = ifr->ifr_mtu; 2648 RL_UNLOCK(sc); 2649 break; 2650 case SIOCSIFFLAGS: 2651 RL_LOCK(sc); 2652 if ((ifp->if_flags & IFF_UP) != 0) { 2653 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2654 if (((ifp->if_flags ^ sc->rl_if_flags) 2655 & IFF_PROMISC) != 0) 2656 re_setmulti(sc); 2657 } else 2658 re_init_locked(sc); 2659 } else { 2660 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2661 re_stop(sc); 2662 } 2663 sc->rl_if_flags = ifp->if_flags; 2664 RL_UNLOCK(sc); 2665 break; 2666 case SIOCADDMULTI: 2667 case SIOCDELMULTI: 2668 RL_LOCK(sc); 2669 re_setmulti(sc); 2670 RL_UNLOCK(sc); 2671 break; 2672 case SIOCGIFMEDIA: 2673 case SIOCSIFMEDIA: 2674 mii = device_get_softc(sc->rl_miibus); 2675 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2676 break; 2677 case SIOCSIFCAP: 2678 { 2679 int mask, reinit; 2680 2681 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2682 reinit = 0; 2683#ifdef DEVICE_POLLING 2684 if (mask & IFCAP_POLLING) { 2685 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2686 error = ether_poll_register(re_poll, ifp); 2687 if (error) 2688 return(error); 2689 RL_LOCK(sc); 2690 /* Disable interrupts */ 2691 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2692 ifp->if_capenable |= IFCAP_POLLING; 2693 RL_UNLOCK(sc); 2694 } else { 2695 error = ether_poll_deregister(ifp); 2696 /* Enable interrupts. */ 2697 RL_LOCK(sc); 2698 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2699 ifp->if_capenable &= ~IFCAP_POLLING; 2700 RL_UNLOCK(sc); 2701 } 2702 } 2703#endif /* DEVICE_POLLING */ 2704 if (mask & IFCAP_HWCSUM) { 2705 ifp->if_capenable ^= IFCAP_HWCSUM; 2706 if (ifp->if_capenable & IFCAP_TXCSUM) 2707 ifp->if_hwassist |= RE_CSUM_FEATURES; 2708 else 2709 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2710 reinit = 1; 2711 } 2712 if (mask & IFCAP_VLAN_HWTAGGING) { 2713 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2714 reinit = 1; 2715 } 2716 if (mask & IFCAP_TSO4) { 2717 ifp->if_capenable ^= IFCAP_TSO4; 2718 if ((IFCAP_TSO4 & ifp->if_capenable) && 2719 (IFCAP_TSO4 & ifp->if_capabilities)) 2720 ifp->if_hwassist |= CSUM_TSO; 2721 else 2722 ifp->if_hwassist &= ~CSUM_TSO; 2723 } 2724 if ((mask & IFCAP_WOL) != 0 && 2725 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2726 if ((mask & IFCAP_WOL_UCAST) != 0) 2727 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2728 if ((mask & IFCAP_WOL_MCAST) != 0) 2729 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2730 if ((mask & IFCAP_WOL_MAGIC) != 0) 2731 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2732 } 2733 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2734 re_init(sc); 2735 VLAN_CAPABILITIES(ifp); 2736 } 2737 break; 2738 default: 2739 error = ether_ioctl(ifp, command, data); 2740 break; 2741 } 2742 2743 return (error); 2744} 2745 2746static void 2747re_watchdog(sc) 2748 struct rl_softc *sc; 2749{ 2750 2751 RL_LOCK_ASSERT(sc); 2752 2753 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2754 return; 2755 2756 device_printf(sc->rl_dev, "watchdog timeout\n"); 2757 sc->rl_ifp->if_oerrors++; 2758 2759 re_txeof(sc); 2760 re_rxeof(sc); 2761 re_init_locked(sc); 2762} 2763 2764/* 2765 * Stop the adapter and free any mbufs allocated to the 2766 * RX and TX lists. 2767 */ 2768static void 2769re_stop(sc) 2770 struct rl_softc *sc; 2771{ 2772 register int i; 2773 struct ifnet *ifp; 2774 struct rl_txdesc *txd; 2775 struct rl_rxdesc *rxd; 2776 2777 RL_LOCK_ASSERT(sc); 2778 2779 ifp = sc->rl_ifp; 2780 2781 sc->rl_watchdog_timer = 0; 2782 callout_stop(&sc->rl_stat_callout); 2783 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2784 2785 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2786 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2787 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2788 2789 if (sc->rl_head != NULL) { 2790 m_freem(sc->rl_head); 2791 sc->rl_head = sc->rl_tail = NULL; 2792 } 2793 2794 /* Free the TX list buffers. */ 2795 2796 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2797 txd = &sc->rl_ldata.rl_tx_desc[i]; 2798 if (txd->tx_m != NULL) { 2799 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2800 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2801 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2802 txd->tx_dmamap); 2803 m_freem(txd->tx_m); 2804 txd->tx_m = NULL; 2805 } 2806 } 2807 2808 /* Free the RX list buffers. */ 2809 2810 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2811 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2812 if (rxd->rx_m != NULL) { 2813 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2814 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2815 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2816 rxd->rx_dmamap); 2817 m_freem(rxd->rx_m); 2818 rxd->rx_m = NULL; 2819 } 2820 } 2821} 2822 2823/* 2824 * Device suspend routine. Stop the interface and save some PCI 2825 * settings in case the BIOS doesn't restore them properly on 2826 * resume. 2827 */ 2828static int 2829re_suspend(dev) 2830 device_t dev; 2831{ 2832 struct rl_softc *sc; 2833 2834 sc = device_get_softc(dev); 2835 2836 RL_LOCK(sc); 2837 re_stop(sc); 2838 re_setwol(sc); 2839 sc->suspended = 1; 2840 RL_UNLOCK(sc); 2841 2842 return (0); 2843} 2844 2845/* 2846 * Device resume routine. Restore some PCI settings in case the BIOS 2847 * doesn't, re-enable busmastering, and restart the interface if 2848 * appropriate. 2849 */ 2850static int 2851re_resume(dev) 2852 device_t dev; 2853{ 2854 struct rl_softc *sc; 2855 struct ifnet *ifp; 2856 2857 sc = device_get_softc(dev); 2858 2859 RL_LOCK(sc); 2860 2861 ifp = sc->rl_ifp; 2862 2863 /* reinitialize interface if necessary */ 2864 if (ifp->if_flags & IFF_UP) 2865 re_init_locked(sc); 2866 2867 /* 2868 * Clear WOL matching such that normal Rx filtering 2869 * wouldn't interfere with WOL patterns. 2870 */ 2871 re_clrwol(sc); 2872 sc->suspended = 0; 2873 RL_UNLOCK(sc); 2874 2875 return (0); 2876} 2877 2878/* 2879 * Stop all chip I/O so that the kernel's probe routines don't 2880 * get confused by errant DMAs when rebooting. 2881 */ 2882static int 2883re_shutdown(dev) 2884 device_t dev; 2885{ 2886 struct rl_softc *sc; 2887 2888 sc = device_get_softc(dev); 2889 2890 RL_LOCK(sc); 2891 re_stop(sc); 2892 /* 2893 * Mark interface as down since otherwise we will panic if 2894 * interrupt comes in later on, which can happen in some 2895 * cases. 2896 */ 2897 sc->rl_ifp->if_flags &= ~IFF_UP; 2898 re_setwol(sc); 2899 RL_UNLOCK(sc); 2900 2901 return (0); 2902} 2903 2904static void 2905re_setwol(sc) 2906 struct rl_softc *sc; 2907{ 2908 struct ifnet *ifp; 2909 int pmc; 2910 uint16_t pmstat; 2911 uint8_t v; 2912 2913 RL_LOCK_ASSERT(sc); 2914 2915 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2916 return; 2917 2918 ifp = sc->rl_ifp; 2919 /* Enable config register write. */ 2920 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2921 2922 /* Enable PME. */ 2923 v = CSR_READ_1(sc, RL_CFG1); 2924 v &= ~RL_CFG1_PME; 2925 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2926 v |= RL_CFG1_PME; 2927 CSR_WRITE_1(sc, RL_CFG1, v); 2928 2929 v = CSR_READ_1(sc, RL_CFG3); 2930 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2931 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2932 v |= RL_CFG3_WOL_MAGIC; 2933 CSR_WRITE_1(sc, RL_CFG3, v); 2934 2935 /* Config register write done. */ 2936 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2937 2938 v = CSR_READ_1(sc, RL_CFG5); 2939 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2940 v &= ~RL_CFG5_WOL_LANWAKE; 2941 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2942 v |= RL_CFG5_WOL_UCAST; 2943 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2944 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 2945 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2946 v |= RL_CFG5_WOL_LANWAKE; 2947 CSR_WRITE_1(sc, RL_CFG5, v); 2948 2949 /* 2950 * It seems that hardware resets its link speed to 100Mbps in 2951 * power down mode so switching to 100Mbps in driver is not 2952 * needed. 2953 */ 2954 2955 /* Request PME if WOL is requested. */ 2956 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 2957 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2958 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2959 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2960 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2961} 2962 2963static void 2964re_clrwol(sc) 2965 struct rl_softc *sc; 2966{ 2967 int pmc; 2968 uint8_t v; 2969 2970 RL_LOCK_ASSERT(sc); 2971 2972 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2973 return; 2974 2975 /* Enable config register write. */ 2976 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2977 2978 v = CSR_READ_1(sc, RL_CFG3); 2979 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2980 CSR_WRITE_1(sc, RL_CFG3, v); 2981 2982 /* Config register write done. */ 2983 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2984 2985 v = CSR_READ_1(sc, RL_CFG5); 2986 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2987 v &= ~RL_CFG5_WOL_LANWAKE; 2988 CSR_WRITE_1(sc, RL_CFG5, v); 2989} 2990