if_re.c revision 177521
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 177521 2008-03-23 05:13:45Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149#include <pci/if_rlreg.h> 150 151MODULE_DEPEND(re, pci, 1, 1, 1); 152MODULE_DEPEND(re, ether, 1, 1, 1); 153MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155/* "device miibus" required. See GENERIC if you get errors here. */ 156#include "miibus_if.h" 157 158/* 159 * Default to using PIO access for this driver. 160 */ 161#define RE_USEIOSPACE 162 163/* Tunables. */ 164static int msi_disable = 0; 165TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166 167#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 168 169/* 170 * Various supported device vendors/types and their names. 171 */ 172static struct rl_type re_devs[] = { 173 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 174 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169_8110SB, 176 "D-Link DGE-528(T) Rev.B1 Gigabit Ethernet Adapter" }, 177 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 178 "RealTek 8139C+ 10/100BaseTX" }, 179 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 180 "RealTek 8101E PCIe 10/100baseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 182 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 184 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN3, 186 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 188 "RealTek 8169 Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 190 "RealTek 8169S Single-chip Gigabit Ethernet" }, 191 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 192 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC, 194 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 195 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 196 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 197 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 198 "RealTek 8110S Single-chip Gigabit Ethernet" }, 199 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 200 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 201 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 202 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 203 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 204 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 205}; 206 207static struct rl_hwrev re_hwrevs[] = { 208 { RL_HWREV_8139, RL_8139, "" }, 209 { RL_HWREV_8139A, RL_8139, "A" }, 210 { RL_HWREV_8139AG, RL_8139, "A-G" }, 211 { RL_HWREV_8139B, RL_8139, "B" }, 212 { RL_HWREV_8130, RL_8139, "8130" }, 213 { RL_HWREV_8139C, RL_8139, "C" }, 214 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 215 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 216 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 217 { RL_HWREV_8169, RL_8169, "8169"}, 218 { RL_HWREV_8169S, RL_8169, "8169S"}, 219 { RL_HWREV_8110S, RL_8169, "8110S"}, 220 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 221 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 222 { RL_HWREV_8100, RL_8139, "8100"}, 223 { RL_HWREV_8101, RL_8139, "8101"}, 224 { RL_HWREV_8100E, RL_8169, "8100E"}, 225 { RL_HWREV_8101E, RL_8169, "8101E"}, 226 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 227 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 228 { 0, 0, NULL } 229}; 230 231static int re_probe (device_t); 232static int re_attach (device_t); 233static int re_detach (device_t); 234 235static int re_encap (struct rl_softc *, struct mbuf **); 236 237static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 238static int re_allocmem (device_t, struct rl_softc *); 239static __inline void re_discard_rxbuf 240 (struct rl_softc *, int); 241static int re_newbuf (struct rl_softc *, int); 242static int re_rx_list_init (struct rl_softc *); 243static int re_tx_list_init (struct rl_softc *); 244#ifdef RE_FIXUP_RX 245static __inline void re_fixup_rx 246 (struct mbuf *); 247#endif 248static int re_rxeof (struct rl_softc *); 249static void re_txeof (struct rl_softc *); 250#ifdef DEVICE_POLLING 251static void re_poll (struct ifnet *, enum poll_cmd, int); 252static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 253#endif 254static int re_intr (void *); 255static void re_tick (void *); 256static void re_tx_task (void *, int); 257static void re_int_task (void *, int); 258static void re_start (struct ifnet *); 259static int re_ioctl (struct ifnet *, u_long, caddr_t); 260static void re_init (void *); 261static void re_init_locked (struct rl_softc *); 262static void re_stop (struct rl_softc *); 263static void re_watchdog (struct rl_softc *); 264static int re_suspend (device_t); 265static int re_resume (device_t); 266static int re_shutdown (device_t); 267static int re_ifmedia_upd (struct ifnet *); 268static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 269 270static void re_eeprom_putbyte (struct rl_softc *, int); 271static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 272static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 273static int re_gmii_readreg (device_t, int, int); 274static int re_gmii_writereg (device_t, int, int, int); 275 276static int re_miibus_readreg (device_t, int, int); 277static int re_miibus_writereg (device_t, int, int, int); 278static void re_miibus_statchg (device_t); 279 280static void re_setmulti (struct rl_softc *); 281static void re_reset (struct rl_softc *); 282static void re_setwol (struct rl_softc *); 283static void re_clrwol (struct rl_softc *); 284 285#ifdef RE_DIAG 286static int re_diag (struct rl_softc *); 287#endif 288 289#ifdef RE_USEIOSPACE 290#define RL_RES SYS_RES_IOPORT 291#define RL_RID RL_PCI_LOIO 292#else 293#define RL_RES SYS_RES_MEMORY 294#define RL_RID RL_PCI_LOMEM 295#endif 296 297static device_method_t re_methods[] = { 298 /* Device interface */ 299 DEVMETHOD(device_probe, re_probe), 300 DEVMETHOD(device_attach, re_attach), 301 DEVMETHOD(device_detach, re_detach), 302 DEVMETHOD(device_suspend, re_suspend), 303 DEVMETHOD(device_resume, re_resume), 304 DEVMETHOD(device_shutdown, re_shutdown), 305 306 /* bus interface */ 307 DEVMETHOD(bus_print_child, bus_generic_print_child), 308 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 309 310 /* MII interface */ 311 DEVMETHOD(miibus_readreg, re_miibus_readreg), 312 DEVMETHOD(miibus_writereg, re_miibus_writereg), 313 DEVMETHOD(miibus_statchg, re_miibus_statchg), 314 315 { 0, 0 } 316}; 317 318static driver_t re_driver = { 319 "re", 320 re_methods, 321 sizeof(struct rl_softc) 322}; 323 324static devclass_t re_devclass; 325 326DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 327DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 328DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 329 330#define EE_SET(x) \ 331 CSR_WRITE_1(sc, RL_EECMD, \ 332 CSR_READ_1(sc, RL_EECMD) | x) 333 334#define EE_CLR(x) \ 335 CSR_WRITE_1(sc, RL_EECMD, \ 336 CSR_READ_1(sc, RL_EECMD) & ~x) 337 338/* 339 * Send a read command and address to the EEPROM, check for ACK. 340 */ 341static void 342re_eeprom_putbyte(sc, addr) 343 struct rl_softc *sc; 344 int addr; 345{ 346 register int d, i; 347 348 d = addr | (RL_9346_READ << sc->rl_eewidth); 349 350 /* 351 * Feed in each bit and strobe the clock. 352 */ 353 354 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 355 if (d & i) { 356 EE_SET(RL_EE_DATAIN); 357 } else { 358 EE_CLR(RL_EE_DATAIN); 359 } 360 DELAY(100); 361 EE_SET(RL_EE_CLK); 362 DELAY(150); 363 EE_CLR(RL_EE_CLK); 364 DELAY(100); 365 } 366 367 return; 368} 369 370/* 371 * Read a word of data stored in the EEPROM at address 'addr.' 372 */ 373static void 374re_eeprom_getword(sc, addr, dest) 375 struct rl_softc *sc; 376 int addr; 377 u_int16_t *dest; 378{ 379 register int i; 380 u_int16_t word = 0; 381 382 /* 383 * Send address of word we want to read. 384 */ 385 re_eeprom_putbyte(sc, addr); 386 387 /* 388 * Start reading bits from EEPROM. 389 */ 390 for (i = 0x8000; i; i >>= 1) { 391 EE_SET(RL_EE_CLK); 392 DELAY(100); 393 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 394 word |= i; 395 EE_CLR(RL_EE_CLK); 396 DELAY(100); 397 } 398 399 *dest = word; 400 401 return; 402} 403 404/* 405 * Read a sequence of words from the EEPROM. 406 */ 407static void 408re_read_eeprom(sc, dest, off, cnt) 409 struct rl_softc *sc; 410 caddr_t dest; 411 int off; 412 int cnt; 413{ 414 int i; 415 u_int16_t word = 0, *ptr; 416 417 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 418 419 DELAY(100); 420 421 for (i = 0; i < cnt; i++) { 422 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 423 re_eeprom_getword(sc, off + i, &word); 424 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 425 ptr = (u_int16_t *)(dest + (i * 2)); 426 *ptr = word; 427 } 428 429 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 430 431 return; 432} 433 434static int 435re_gmii_readreg(dev, phy, reg) 436 device_t dev; 437 int phy, reg; 438{ 439 struct rl_softc *sc; 440 u_int32_t rval; 441 int i; 442 443 if (phy != 1) 444 return (0); 445 446 sc = device_get_softc(dev); 447 448 /* Let the rgephy driver read the GMEDIASTAT register */ 449 450 if (reg == RL_GMEDIASTAT) { 451 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 452 return (rval); 453 } 454 455 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 456 DELAY(1000); 457 458 for (i = 0; i < RL_TIMEOUT; i++) { 459 rval = CSR_READ_4(sc, RL_PHYAR); 460 if (rval & RL_PHYAR_BUSY) 461 break; 462 DELAY(100); 463 } 464 465 if (i == RL_TIMEOUT) { 466 device_printf(sc->rl_dev, "PHY read failed\n"); 467 return (0); 468 } 469 470 return (rval & RL_PHYAR_PHYDATA); 471} 472 473static int 474re_gmii_writereg(dev, phy, reg, data) 475 device_t dev; 476 int phy, reg, data; 477{ 478 struct rl_softc *sc; 479 u_int32_t rval; 480 int i; 481 482 sc = device_get_softc(dev); 483 484 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 485 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 486 DELAY(1000); 487 488 for (i = 0; i < RL_TIMEOUT; i++) { 489 rval = CSR_READ_4(sc, RL_PHYAR); 490 if (!(rval & RL_PHYAR_BUSY)) 491 break; 492 DELAY(100); 493 } 494 495 if (i == RL_TIMEOUT) { 496 device_printf(sc->rl_dev, "PHY write failed\n"); 497 return (0); 498 } 499 500 return (0); 501} 502 503static int 504re_miibus_readreg(dev, phy, reg) 505 device_t dev; 506 int phy, reg; 507{ 508 struct rl_softc *sc; 509 u_int16_t rval = 0; 510 u_int16_t re8139_reg = 0; 511 512 sc = device_get_softc(dev); 513 514 if (sc->rl_type == RL_8169) { 515 rval = re_gmii_readreg(dev, phy, reg); 516 return (rval); 517 } 518 519 /* Pretend the internal PHY is only at address 0 */ 520 if (phy) { 521 return (0); 522 } 523 switch (reg) { 524 case MII_BMCR: 525 re8139_reg = RL_BMCR; 526 break; 527 case MII_BMSR: 528 re8139_reg = RL_BMSR; 529 break; 530 case MII_ANAR: 531 re8139_reg = RL_ANAR; 532 break; 533 case MII_ANER: 534 re8139_reg = RL_ANER; 535 break; 536 case MII_ANLPAR: 537 re8139_reg = RL_LPAR; 538 break; 539 case MII_PHYIDR1: 540 case MII_PHYIDR2: 541 return (0); 542 /* 543 * Allow the rlphy driver to read the media status 544 * register. If we have a link partner which does not 545 * support NWAY, this is the register which will tell 546 * us the results of parallel detection. 547 */ 548 case RL_MEDIASTAT: 549 rval = CSR_READ_1(sc, RL_MEDIASTAT); 550 return (rval); 551 default: 552 device_printf(sc->rl_dev, "bad phy register\n"); 553 return (0); 554 } 555 rval = CSR_READ_2(sc, re8139_reg); 556 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 557 /* 8139C+ has different bit layout. */ 558 rval &= ~(BMCR_LOOP | BMCR_ISO); 559 } 560 return (rval); 561} 562 563static int 564re_miibus_writereg(dev, phy, reg, data) 565 device_t dev; 566 int phy, reg, data; 567{ 568 struct rl_softc *sc; 569 u_int16_t re8139_reg = 0; 570 int rval = 0; 571 572 sc = device_get_softc(dev); 573 574 if (sc->rl_type == RL_8169) { 575 rval = re_gmii_writereg(dev, phy, reg, data); 576 return (rval); 577 } 578 579 /* Pretend the internal PHY is only at address 0 */ 580 if (phy) 581 return (0); 582 583 switch (reg) { 584 case MII_BMCR: 585 re8139_reg = RL_BMCR; 586 if (sc->rl_type == RL_8139CPLUS) { 587 /* 8139C+ has different bit layout. */ 588 data &= ~(BMCR_LOOP | BMCR_ISO); 589 } 590 break; 591 case MII_BMSR: 592 re8139_reg = RL_BMSR; 593 break; 594 case MII_ANAR: 595 re8139_reg = RL_ANAR; 596 break; 597 case MII_ANER: 598 re8139_reg = RL_ANER; 599 break; 600 case MII_ANLPAR: 601 re8139_reg = RL_LPAR; 602 break; 603 case MII_PHYIDR1: 604 case MII_PHYIDR2: 605 return (0); 606 break; 607 default: 608 device_printf(sc->rl_dev, "bad phy register\n"); 609 return (0); 610 } 611 CSR_WRITE_2(sc, re8139_reg, data); 612 return (0); 613} 614 615static void 616re_miibus_statchg(dev) 617 device_t dev; 618{ 619 620} 621 622/* 623 * Program the 64-bit multicast hash filter. 624 */ 625static void 626re_setmulti(sc) 627 struct rl_softc *sc; 628{ 629 struct ifnet *ifp; 630 int h = 0; 631 u_int32_t hashes[2] = { 0, 0 }; 632 struct ifmultiaddr *ifma; 633 u_int32_t rxfilt; 634 int mcnt = 0; 635 u_int32_t hwrev; 636 637 RL_LOCK_ASSERT(sc); 638 639 ifp = sc->rl_ifp; 640 641 642 rxfilt = CSR_READ_4(sc, RL_RXCFG); 643 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 644 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 645 if (ifp->if_flags & IFF_PROMISC) 646 rxfilt |= RL_RXCFG_RX_ALLPHYS; 647 /* 648 * Unlike other hardwares, we have to explicitly set 649 * RL_RXCFG_RX_MULTI to receive multicast frames in 650 * promiscuous mode. 651 */ 652 rxfilt |= RL_RXCFG_RX_MULTI; 653 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 654 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 655 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 656 return; 657 } 658 659 /* first, zot all the existing hash bits */ 660 CSR_WRITE_4(sc, RL_MAR0, 0); 661 CSR_WRITE_4(sc, RL_MAR4, 0); 662 663 /* now program new ones */ 664 IF_ADDR_LOCK(ifp); 665 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 666 if (ifma->ifma_addr->sa_family != AF_LINK) 667 continue; 668 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 669 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 670 if (h < 32) 671 hashes[0] |= (1 << h); 672 else 673 hashes[1] |= (1 << (h - 32)); 674 mcnt++; 675 } 676 IF_ADDR_UNLOCK(ifp); 677 678 if (mcnt) 679 rxfilt |= RL_RXCFG_RX_MULTI; 680 else 681 rxfilt &= ~RL_RXCFG_RX_MULTI; 682 683 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 684 685 /* 686 * For some unfathomable reason, RealTek decided to reverse 687 * the order of the multicast hash registers in the PCI Express 688 * parts. This means we have to write the hash pattern in reverse 689 * order for those devices. 690 */ 691 692 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 693 694 switch (hwrev) { 695 case RL_HWREV_8100E: 696 case RL_HWREV_8101E: 697 case RL_HWREV_8168_SPIN1: 698 case RL_HWREV_8168_SPIN2: 699 case RL_HWREV_8168_SPIN3: 700 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 701 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 702 break; 703 default: 704 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 705 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 706 break; 707 } 708} 709 710static void 711re_reset(sc) 712 struct rl_softc *sc; 713{ 714 register int i; 715 716 RL_LOCK_ASSERT(sc); 717 718 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 719 720 for (i = 0; i < RL_TIMEOUT; i++) { 721 DELAY(10); 722 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 723 break; 724 } 725 if (i == RL_TIMEOUT) 726 device_printf(sc->rl_dev, "reset never completed!\n"); 727 728 CSR_WRITE_1(sc, 0x82, 1); 729} 730 731#ifdef RE_DIAG 732 733/* 734 * The following routine is designed to test for a defect on some 735 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 736 * lines connected to the bus, however for a 32-bit only card, they 737 * should be pulled high. The result of this defect is that the 738 * NIC will not work right if you plug it into a 64-bit slot: DMA 739 * operations will be done with 64-bit transfers, which will fail 740 * because the 64-bit data lines aren't connected. 741 * 742 * There's no way to work around this (short of talking a soldering 743 * iron to the board), however we can detect it. The method we use 744 * here is to put the NIC into digital loopback mode, set the receiver 745 * to promiscuous mode, and then try to send a frame. We then compare 746 * the frame data we sent to what was received. If the data matches, 747 * then the NIC is working correctly, otherwise we know the user has 748 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 749 * slot. In the latter case, there's no way the NIC can work correctly, 750 * so we print out a message on the console and abort the device attach. 751 */ 752 753static int 754re_diag(sc) 755 struct rl_softc *sc; 756{ 757 struct ifnet *ifp = sc->rl_ifp; 758 struct mbuf *m0; 759 struct ether_header *eh; 760 struct rl_desc *cur_rx; 761 u_int16_t status; 762 u_int32_t rxstat; 763 int total_len, i, error = 0, phyaddr; 764 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 765 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 766 767 /* Allocate a single mbuf */ 768 MGETHDR(m0, M_DONTWAIT, MT_DATA); 769 if (m0 == NULL) 770 return (ENOBUFS); 771 772 RL_LOCK(sc); 773 774 /* 775 * Initialize the NIC in test mode. This sets the chip up 776 * so that it can send and receive frames, but performs the 777 * following special functions: 778 * - Puts receiver in promiscuous mode 779 * - Enables digital loopback mode 780 * - Leaves interrupts turned off 781 */ 782 783 ifp->if_flags |= IFF_PROMISC; 784 sc->rl_testmode = 1; 785 re_reset(sc); 786 re_init_locked(sc); 787 sc->rl_link = 1; 788 if (sc->rl_type == RL_8169) 789 phyaddr = 1; 790 else 791 phyaddr = 0; 792 793 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 794 for (i = 0; i < RL_TIMEOUT; i++) { 795 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 796 if (!(status & BMCR_RESET)) 797 break; 798 } 799 800 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 801 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 802 803 DELAY(100000); 804 805 /* Put some data in the mbuf */ 806 807 eh = mtod(m0, struct ether_header *); 808 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 809 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 810 eh->ether_type = htons(ETHERTYPE_IP); 811 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 812 813 /* 814 * Queue the packet, start transmission. 815 * Note: IF_HANDOFF() ultimately calls re_start() for us. 816 */ 817 818 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 819 RL_UNLOCK(sc); 820 /* XXX: re_diag must not be called when in ALTQ mode */ 821 IF_HANDOFF(&ifp->if_snd, m0, ifp); 822 RL_LOCK(sc); 823 m0 = NULL; 824 825 /* Wait for it to propagate through the chip */ 826 827 DELAY(100000); 828 for (i = 0; i < RL_TIMEOUT; i++) { 829 status = CSR_READ_2(sc, RL_ISR); 830 CSR_WRITE_2(sc, RL_ISR, status); 831 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 832 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 833 break; 834 DELAY(10); 835 } 836 837 if (i == RL_TIMEOUT) { 838 device_printf(sc->rl_dev, 839 "diagnostic failed, failed to receive packet in" 840 " loopback mode\n"); 841 error = EIO; 842 goto done; 843 } 844 845 /* 846 * The packet should have been dumped into the first 847 * entry in the RX DMA ring. Grab it from there. 848 */ 849 850 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 851 sc->rl_ldata.rl_rx_list_map, 852 BUS_DMASYNC_POSTREAD); 853 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 854 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 855 BUS_DMASYNC_POSTREAD); 856 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 857 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 858 859 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 860 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 861 eh = mtod(m0, struct ether_header *); 862 863 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 864 total_len = RL_RXBYTES(cur_rx); 865 rxstat = le32toh(cur_rx->rl_cmdstat); 866 867 if (total_len != ETHER_MIN_LEN) { 868 device_printf(sc->rl_dev, 869 "diagnostic failed, received short packet\n"); 870 error = EIO; 871 goto done; 872 } 873 874 /* Test that the received packet data matches what we sent. */ 875 876 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 877 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 878 ntohs(eh->ether_type) != ETHERTYPE_IP) { 879 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 880 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 881 dst, ":", src, ":", ETHERTYPE_IP); 882 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 883 eh->ether_dhost, ":", eh->ether_shost, ":", 884 ntohs(eh->ether_type)); 885 device_printf(sc->rl_dev, "You may have a defective 32-bit " 886 "NIC plugged into a 64-bit PCI slot.\n"); 887 device_printf(sc->rl_dev, "Please re-install the NIC in a " 888 "32-bit slot for proper operation.\n"); 889 device_printf(sc->rl_dev, "Read the re(4) man page for more " 890 "details.\n"); 891 error = EIO; 892 } 893 894done: 895 /* Turn interface off, release resources */ 896 897 sc->rl_testmode = 0; 898 sc->rl_link = 0; 899 ifp->if_flags &= ~IFF_PROMISC; 900 re_stop(sc); 901 if (m0 != NULL) 902 m_freem(m0); 903 904 RL_UNLOCK(sc); 905 906 return (error); 907} 908 909#endif 910 911/* 912 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 913 * IDs against our list and return a device name if we find a match. 914 */ 915static int 916re_probe(dev) 917 device_t dev; 918{ 919 struct rl_type *t; 920 uint16_t devid, vendor; 921 uint16_t revid, sdevid; 922 int i; 923 924 vendor = pci_get_vendor(dev); 925 devid = pci_get_device(dev); 926 revid = pci_get_revid(dev); 927 sdevid = pci_get_subdevice(dev); 928 929 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 930 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 931 /* 932 * Only attach to rev. 3 of the Linksys EG1032 adapter. 933 * Rev. 2 is supported by sk(4). 934 */ 935 return (ENXIO); 936 } 937 } 938 939 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 940 if (revid != 0x20) { 941 /* 8139, let rl(4) take care of this device. */ 942 return (ENXIO); 943 } 944 } 945 946 t = re_devs; 947 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 948 if (vendor == t->rl_vid && devid == t->rl_did) { 949 device_set_desc(dev, t->rl_name); 950 return (BUS_PROBE_DEFAULT); 951 } 952 } 953 954 return (ENXIO); 955} 956 957/* 958 * Map a single buffer address. 959 */ 960 961static void 962re_dma_map_addr(arg, segs, nseg, error) 963 void *arg; 964 bus_dma_segment_t *segs; 965 int nseg; 966 int error; 967{ 968 bus_addr_t *addr; 969 970 if (error) 971 return; 972 973 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 974 addr = arg; 975 *addr = segs->ds_addr; 976} 977 978static int 979re_allocmem(dev, sc) 980 device_t dev; 981 struct rl_softc *sc; 982{ 983 bus_size_t rx_list_size, tx_list_size; 984 int error; 985 int i; 986 987 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 988 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 989 990 /* 991 * Allocate the parent bus DMA tag appropriate for PCI. 992 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 993 * register should be set. However some RealTek chips are known 994 * to be buggy on DAC handling, therefore disable DAC by limiting 995 * DMA address space to 32bit. PCIe variants of RealTek chips 996 * may not have the limitation but I took safer path. 997 */ 998 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 999 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1000 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1001 NULL, NULL, &sc->rl_parent_tag); 1002 if (error) { 1003 device_printf(dev, "could not allocate parent DMA tag\n"); 1004 return (error); 1005 } 1006 1007 /* 1008 * Allocate map for TX mbufs. 1009 */ 1010 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1011 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1012 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1013 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1014 if (error) { 1015 device_printf(dev, "could not allocate TX DMA tag\n"); 1016 return (error); 1017 } 1018 1019 /* 1020 * Allocate map for RX mbufs. 1021 */ 1022 1023 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1024 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1025 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1026 if (error) { 1027 device_printf(dev, "could not allocate RX DMA tag\n"); 1028 return (error); 1029 } 1030 1031 /* 1032 * Allocate map for TX descriptor list. 1033 */ 1034 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1035 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1036 NULL, tx_list_size, 1, tx_list_size, 0, 1037 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1038 if (error) { 1039 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1040 return (error); 1041 } 1042 1043 /* Allocate DMA'able memory for the TX ring */ 1044 1045 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1046 (void **)&sc->rl_ldata.rl_tx_list, 1047 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1048 &sc->rl_ldata.rl_tx_list_map); 1049 if (error) { 1050 device_printf(dev, "could not allocate TX DMA ring\n"); 1051 return (error); 1052 } 1053 1054 /* Load the map for the TX ring. */ 1055 1056 sc->rl_ldata.rl_tx_list_addr = 0; 1057 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1058 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1059 tx_list_size, re_dma_map_addr, 1060 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1061 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1062 device_printf(dev, "could not load TX DMA ring\n"); 1063 return (ENOMEM); 1064 } 1065 1066 /* Create DMA maps for TX buffers */ 1067 1068 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1069 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1070 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1071 if (error) { 1072 device_printf(dev, "could not create DMA map for TX\n"); 1073 return (error); 1074 } 1075 } 1076 1077 /* 1078 * Allocate map for RX descriptor list. 1079 */ 1080 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1081 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1082 NULL, rx_list_size, 1, rx_list_size, 0, 1083 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1084 if (error) { 1085 device_printf(dev, "could not create RX DMA ring tag\n"); 1086 return (error); 1087 } 1088 1089 /* Allocate DMA'able memory for the RX ring */ 1090 1091 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1092 (void **)&sc->rl_ldata.rl_rx_list, 1093 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1094 &sc->rl_ldata.rl_rx_list_map); 1095 if (error) { 1096 device_printf(dev, "could not allocate RX DMA ring\n"); 1097 return (error); 1098 } 1099 1100 /* Load the map for the RX ring. */ 1101 1102 sc->rl_ldata.rl_rx_list_addr = 0; 1103 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1104 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1105 rx_list_size, re_dma_map_addr, 1106 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1107 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1108 device_printf(dev, "could not load RX DMA ring\n"); 1109 return (ENOMEM); 1110 } 1111 1112 /* Create DMA maps for RX buffers */ 1113 1114 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1115 &sc->rl_ldata.rl_rx_sparemap); 1116 if (error) { 1117 device_printf(dev, "could not create spare DMA map for RX\n"); 1118 return (error); 1119 } 1120 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1121 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1122 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1123 if (error) { 1124 device_printf(dev, "could not create DMA map for RX\n"); 1125 return (error); 1126 } 1127 } 1128 1129 return (0); 1130} 1131 1132/* 1133 * Attach the interface. Allocate softc structures, do ifmedia 1134 * setup and ethernet/BPF attach. 1135 */ 1136static int 1137re_attach(dev) 1138 device_t dev; 1139{ 1140 u_char eaddr[ETHER_ADDR_LEN]; 1141 u_int16_t as[ETHER_ADDR_LEN / 2]; 1142 struct rl_softc *sc; 1143 struct ifnet *ifp; 1144 struct rl_hwrev *hw_rev; 1145 int hwrev; 1146 u_int16_t re_did = 0; 1147 int error = 0, rid, i; 1148 int msic, reg; 1149 1150 sc = device_get_softc(dev); 1151 sc->rl_dev = dev; 1152 1153 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1154 MTX_DEF); 1155 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1156 1157 /* 1158 * Map control/status registers. 1159 */ 1160 pci_enable_busmaster(dev); 1161 1162 rid = RL_RID; 1163 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1164 RF_ACTIVE); 1165 1166 if (sc->rl_res == NULL) { 1167 device_printf(dev, "couldn't map ports/memory\n"); 1168 error = ENXIO; 1169 goto fail; 1170 } 1171 1172 sc->rl_btag = rman_get_bustag(sc->rl_res); 1173 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1174 1175 msic = 0; 1176 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1177 msic = pci_msi_count(dev); 1178 if (bootverbose) 1179 device_printf(dev, "MSI count : %d\n", msic); 1180 } 1181 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1182 if (pci_alloc_msi(dev, &msic) == 0) { 1183 if (msic == RL_MSI_MESSAGES) { 1184 device_printf(dev, "Using %d MSI messages\n", 1185 msic); 1186 sc->rl_msi = 1; 1187 } else 1188 pci_release_msi(dev); 1189 } 1190 } 1191 1192 /* Allocate interrupt */ 1193 if (sc->rl_msi == 0) { 1194 rid = 0; 1195 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1196 RF_SHAREABLE | RF_ACTIVE); 1197 if (sc->rl_irq[0] == NULL) { 1198 device_printf(dev, "couldn't allocate IRQ resources\n"); 1199 error = ENXIO; 1200 goto fail; 1201 } 1202 } else { 1203 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1204 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1205 SYS_RES_IRQ, &rid, RF_ACTIVE); 1206 if (sc->rl_irq[i] == NULL) { 1207 device_printf(dev, 1208 "couldn't llocate IRQ resources for " 1209 "message %d\n", rid); 1210 error = ENXIO; 1211 goto fail; 1212 } 1213 } 1214 } 1215 1216 /* Reset the adapter. */ 1217 RL_LOCK(sc); 1218 re_reset(sc); 1219 RL_UNLOCK(sc); 1220 1221 hw_rev = re_hwrevs; 1222 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1223 while (hw_rev->rl_desc != NULL) { 1224 if (hw_rev->rl_rev == hwrev) { 1225 sc->rl_type = hw_rev->rl_type; 1226 break; 1227 } 1228 hw_rev++; 1229 } 1230 if (hw_rev->rl_desc == NULL) { 1231 device_printf(dev, "Unknown H/W revision: %08x\n", hwrev); 1232 error = ENXIO; 1233 goto fail; 1234 } 1235 1236 sc->rl_eewidth = RL_9356_ADDR_LEN; 1237 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1238 if (re_did != 0x8129) 1239 sc->rl_eewidth = RL_9346_ADDR_LEN; 1240 1241 /* 1242 * Get station address from the EEPROM. 1243 */ 1244 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1245 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1246 as[i] = le16toh(as[i]); 1247 bcopy(as, eaddr, sizeof(eaddr)); 1248 1249 if (sc->rl_type == RL_8169) { 1250 /* Set RX length mask and number of descriptors. */ 1251 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1252 sc->rl_txstart = RL_GTXSTART; 1253 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1254 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1255 } else { 1256 /* Set RX length mask and number of descriptors. */ 1257 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1258 sc->rl_txstart = RL_TXSTART; 1259 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1260 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1261 } 1262 if (hw_rev->rl_desc == NULL) { 1263 device_printf(dev, "Unsupported revision : 0x%08x\n", hwrev); 1264 error = ENXIO; 1265 goto fail; 1266 } 1267 1268 error = re_allocmem(dev, sc); 1269 if (error) 1270 goto fail; 1271 1272 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1273 if (ifp == NULL) { 1274 device_printf(dev, "can not if_alloc()\n"); 1275 error = ENOSPC; 1276 goto fail; 1277 } 1278 1279 /* Do MII setup */ 1280 if (mii_phy_probe(dev, &sc->rl_miibus, 1281 re_ifmedia_upd, re_ifmedia_sts)) { 1282 device_printf(dev, "MII without any phy!\n"); 1283 error = ENXIO; 1284 goto fail; 1285 } 1286 1287 /* Take PHY out of power down mode. */ 1288 if (sc->rl_type == RL_8169) { 1289 uint32_t rev; 1290 1291 rev = CSR_READ_4(sc, RL_TXCFG); 1292 /* HWVERID 0, 1 and 2 : bit26-30, bit23 */ 1293 rev &= 0x7c800000; 1294 if (rev != 0) { 1295 /* RTL8169S single chip */ 1296 switch (rev) { 1297 case RL_HWREV_8169_8110SB: 1298 case RL_HWREV_8169_8110SC: 1299 case RL_HWREV_8168_SPIN2: 1300 case RL_HWREV_8168_SPIN3: 1301 re_gmii_writereg(dev, 1, 0x1f, 0); 1302 re_gmii_writereg(dev, 1, 0x0e, 0); 1303 break; 1304 default: 1305 break; 1306 } 1307 } 1308 } 1309 1310 ifp->if_softc = sc; 1311 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1312 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1313 ifp->if_ioctl = re_ioctl; 1314 ifp->if_start = re_start; 1315 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1316 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1317 ifp->if_capenable = ifp->if_capabilities; 1318 ifp->if_init = re_init; 1319 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1320 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1321 IFQ_SET_READY(&ifp->if_snd); 1322 1323 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1324 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1325 1326 /* 1327 * Call MI attach routine. 1328 */ 1329 ether_ifattach(ifp, eaddr); 1330 1331 /* VLAN capability setup */ 1332 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1333 if (ifp->if_capabilities & IFCAP_HWCSUM) 1334 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1335 /* Enable WOL if PM is supported. */ 1336 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1337 ifp->if_capabilities |= IFCAP_WOL; 1338 ifp->if_capenable = ifp->if_capabilities; 1339#ifdef DEVICE_POLLING 1340 ifp->if_capabilities |= IFCAP_POLLING; 1341#endif 1342 /* 1343 * Tell the upper layer(s) we support long frames. 1344 * Must appear after the call to ether_ifattach() because 1345 * ether_ifattach() sets ifi_hdrlen to the default value. 1346 */ 1347 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1348 1349#ifdef RE_DIAG 1350 /* 1351 * Perform hardware diagnostic on the original RTL8169. 1352 * Some 32-bit cards were incorrectly wired and would 1353 * malfunction if plugged into a 64-bit slot. 1354 */ 1355 1356 if (hwrev == RL_HWREV_8169) { 1357 error = re_diag(sc); 1358 if (error) { 1359 device_printf(dev, 1360 "attach aborted due to hardware diag failure\n"); 1361 ether_ifdetach(ifp); 1362 goto fail; 1363 } 1364 } 1365#endif 1366 1367 /* Hook interrupt last to avoid having to lock softc */ 1368 if (sc->rl_msi == 0) 1369 error = bus_setup_intr(dev, sc->rl_irq[0], 1370 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1371 &sc->rl_intrhand[0]); 1372 else { 1373 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1374 error = bus_setup_intr(dev, sc->rl_irq[i], 1375 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1376 &sc->rl_intrhand[i]); 1377 if (error != 0) 1378 break; 1379 } 1380 } 1381 if (error) { 1382 device_printf(dev, "couldn't set up irq\n"); 1383 ether_ifdetach(ifp); 1384 } 1385 1386fail: 1387 1388 if (error) 1389 re_detach(dev); 1390 1391 return (error); 1392} 1393 1394/* 1395 * Shutdown hardware and free up resources. This can be called any 1396 * time after the mutex has been initialized. It is called in both 1397 * the error case in attach and the normal detach case so it needs 1398 * to be careful about only freeing resources that have actually been 1399 * allocated. 1400 */ 1401static int 1402re_detach(dev) 1403 device_t dev; 1404{ 1405 struct rl_softc *sc; 1406 struct ifnet *ifp; 1407 int i, rid; 1408 1409 sc = device_get_softc(dev); 1410 ifp = sc->rl_ifp; 1411 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1412 1413#ifdef DEVICE_POLLING 1414 if (ifp->if_capenable & IFCAP_POLLING) 1415 ether_poll_deregister(ifp); 1416#endif 1417 /* These should only be active if attach succeeded */ 1418 if (device_is_attached(dev)) { 1419 RL_LOCK(sc); 1420#if 0 1421 sc->suspended = 1; 1422#endif 1423 re_stop(sc); 1424 RL_UNLOCK(sc); 1425 callout_drain(&sc->rl_stat_callout); 1426 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1427 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1428 /* 1429 * Force off the IFF_UP flag here, in case someone 1430 * still had a BPF descriptor attached to this 1431 * interface. If they do, ether_ifdetach() will cause 1432 * the BPF code to try and clear the promisc mode 1433 * flag, which will bubble down to re_ioctl(), 1434 * which will try to call re_init() again. This will 1435 * turn the NIC back on and restart the MII ticker, 1436 * which will panic the system when the kernel tries 1437 * to invoke the re_tick() function that isn't there 1438 * anymore. 1439 */ 1440 ifp->if_flags &= ~IFF_UP; 1441 ether_ifdetach(ifp); 1442 } 1443 if (sc->rl_miibus) 1444 device_delete_child(dev, sc->rl_miibus); 1445 bus_generic_detach(dev); 1446 1447 /* 1448 * The rest is resource deallocation, so we should already be 1449 * stopped here. 1450 */ 1451 1452 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1453 if (sc->rl_intrhand[i] != NULL) { 1454 bus_teardown_intr(dev, sc->rl_irq[i], 1455 sc->rl_intrhand[i]); 1456 sc->rl_intrhand[i] = NULL; 1457 } 1458 } 1459 if (ifp != NULL) 1460 if_free(ifp); 1461 if (sc->rl_msi == 0) { 1462 if (sc->rl_irq[0] != NULL) { 1463 bus_release_resource(dev, SYS_RES_IRQ, 0, 1464 sc->rl_irq[0]); 1465 sc->rl_irq[0] = NULL; 1466 } 1467 } else { 1468 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1469 if (sc->rl_irq[i] != NULL) { 1470 bus_release_resource(dev, SYS_RES_IRQ, rid, 1471 sc->rl_irq[i]); 1472 sc->rl_irq[i] = NULL; 1473 } 1474 } 1475 pci_release_msi(dev); 1476 } 1477 if (sc->rl_res) 1478 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1479 1480 /* Unload and free the RX DMA ring memory and map */ 1481 1482 if (sc->rl_ldata.rl_rx_list_tag) { 1483 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1484 sc->rl_ldata.rl_rx_list_map); 1485 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1486 sc->rl_ldata.rl_rx_list, 1487 sc->rl_ldata.rl_rx_list_map); 1488 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1489 } 1490 1491 /* Unload and free the TX DMA ring memory and map */ 1492 1493 if (sc->rl_ldata.rl_tx_list_tag) { 1494 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1495 sc->rl_ldata.rl_tx_list_map); 1496 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1497 sc->rl_ldata.rl_tx_list, 1498 sc->rl_ldata.rl_tx_list_map); 1499 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1500 } 1501 1502 /* Destroy all the RX and TX buffer maps */ 1503 1504 if (sc->rl_ldata.rl_tx_mtag) { 1505 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1506 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1507 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1508 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1509 } 1510 if (sc->rl_ldata.rl_rx_mtag) { 1511 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1512 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1513 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1514 if (sc->rl_ldata.rl_rx_sparemap) 1515 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1516 sc->rl_ldata.rl_rx_sparemap); 1517 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1518 } 1519 1520 /* Unload and free the stats buffer and map */ 1521 1522 if (sc->rl_ldata.rl_stag) { 1523 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1524 sc->rl_ldata.rl_rx_list_map); 1525 bus_dmamem_free(sc->rl_ldata.rl_stag, 1526 sc->rl_ldata.rl_stats, 1527 sc->rl_ldata.rl_smap); 1528 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1529 } 1530 1531 if (sc->rl_parent_tag) 1532 bus_dma_tag_destroy(sc->rl_parent_tag); 1533 1534 mtx_destroy(&sc->rl_mtx); 1535 1536 return (0); 1537} 1538 1539static __inline void 1540re_discard_rxbuf(sc, idx) 1541 struct rl_softc *sc; 1542 int idx; 1543{ 1544 struct rl_desc *desc; 1545 struct rl_rxdesc *rxd; 1546 uint32_t cmdstat; 1547 1548 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1549 desc = &sc->rl_ldata.rl_rx_list[idx]; 1550 desc->rl_vlanctl = 0; 1551 cmdstat = rxd->rx_size; 1552 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1553 cmdstat |= RL_RDESC_CMD_EOR; 1554 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1555} 1556 1557static int 1558re_newbuf(sc, idx) 1559 struct rl_softc *sc; 1560 int idx; 1561{ 1562 struct mbuf *m; 1563 struct rl_rxdesc *rxd; 1564 bus_dma_segment_t segs[1]; 1565 bus_dmamap_t map; 1566 struct rl_desc *desc; 1567 uint32_t cmdstat; 1568 int error, nsegs; 1569 1570 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1571 if (m == NULL) 1572 return (ENOBUFS); 1573 1574 m->m_len = m->m_pkthdr.len = MCLBYTES; 1575#ifdef RE_FIXUP_RX 1576 /* 1577 * This is part of an evil trick to deal with non-x86 platforms. 1578 * The RealTek chip requires RX buffers to be aligned on 64-bit 1579 * boundaries, but that will hose non-x86 machines. To get around 1580 * this, we leave some empty space at the start of each buffer 1581 * and for non-x86 hosts, we copy the buffer back six bytes 1582 * to achieve word alignment. This is slightly more efficient 1583 * than allocating a new buffer, copying the contents, and 1584 * discarding the old buffer. 1585 */ 1586 m_adj(m, RE_ETHER_ALIGN); 1587#endif 1588 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1589 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1590 if (error != 0) { 1591 m_freem(m); 1592 return (ENOBUFS); 1593 } 1594 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1595 1596 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1597 if (rxd->rx_m != NULL) { 1598 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1599 BUS_DMASYNC_POSTREAD); 1600 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1601 } 1602 1603 rxd->rx_m = m; 1604 map = rxd->rx_dmamap; 1605 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1606 rxd->rx_size = segs[0].ds_len; 1607 sc->rl_ldata.rl_rx_sparemap = map; 1608 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1609 BUS_DMASYNC_PREREAD); 1610 1611 desc = &sc->rl_ldata.rl_rx_list[idx]; 1612 desc->rl_vlanctl = 0; 1613 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1614 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1615 cmdstat = segs[0].ds_len; 1616 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1617 cmdstat |= RL_RDESC_CMD_EOR; 1618 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1619 1620 return (0); 1621} 1622 1623#ifdef RE_FIXUP_RX 1624static __inline void 1625re_fixup_rx(m) 1626 struct mbuf *m; 1627{ 1628 int i; 1629 uint16_t *src, *dst; 1630 1631 src = mtod(m, uint16_t *); 1632 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1633 1634 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1635 *dst++ = *src++; 1636 1637 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1638 1639 return; 1640} 1641#endif 1642 1643static int 1644re_tx_list_init(sc) 1645 struct rl_softc *sc; 1646{ 1647 struct rl_desc *desc; 1648 int i; 1649 1650 RL_LOCK_ASSERT(sc); 1651 1652 bzero(sc->rl_ldata.rl_tx_list, 1653 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1654 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1655 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1656 /* Set EOR. */ 1657 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1658 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1659 1660 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1661 sc->rl_ldata.rl_tx_list_map, 1662 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1663 1664 sc->rl_ldata.rl_tx_prodidx = 0; 1665 sc->rl_ldata.rl_tx_considx = 0; 1666 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1667 1668 return (0); 1669} 1670 1671static int 1672re_rx_list_init(sc) 1673 struct rl_softc *sc; 1674{ 1675 int error, i; 1676 1677 bzero(sc->rl_ldata.rl_rx_list, 1678 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1679 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1680 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1681 if ((error = re_newbuf(sc, i)) != 0) 1682 return (error); 1683 } 1684 1685 /* Flush the RX descriptors */ 1686 1687 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1688 sc->rl_ldata.rl_rx_list_map, 1689 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1690 1691 sc->rl_ldata.rl_rx_prodidx = 0; 1692 sc->rl_head = sc->rl_tail = NULL; 1693 1694 return (0); 1695} 1696 1697/* 1698 * RX handler for C+ and 8169. For the gigE chips, we support 1699 * the reception of jumbo frames that have been fragmented 1700 * across multiple 2K mbuf cluster buffers. 1701 */ 1702static int 1703re_rxeof(sc) 1704 struct rl_softc *sc; 1705{ 1706 struct mbuf *m; 1707 struct ifnet *ifp; 1708 int i, total_len; 1709 struct rl_desc *cur_rx; 1710 u_int32_t rxstat, rxvlan; 1711 int maxpkt = 16; 1712 1713 RL_LOCK_ASSERT(sc); 1714 1715 ifp = sc->rl_ifp; 1716 1717 /* Invalidate the descriptor memory */ 1718 1719 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1720 sc->rl_ldata.rl_rx_list_map, 1721 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1722 1723 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1724 i = RL_RX_DESC_NXT(sc, i)) { 1725 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1726 rxstat = le32toh(cur_rx->rl_cmdstat); 1727 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1728 break; 1729 total_len = rxstat & sc->rl_rxlenmask; 1730 rxvlan = le32toh(cur_rx->rl_vlanctl); 1731 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1732 1733 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1734 if (re_newbuf(sc, i) != 0) { 1735 /* 1736 * If this is part of a multi-fragment packet, 1737 * discard all the pieces. 1738 */ 1739 if (sc->rl_head != NULL) { 1740 m_freem(sc->rl_head); 1741 sc->rl_head = sc->rl_tail = NULL; 1742 } 1743 re_discard_rxbuf(sc, i); 1744 continue; 1745 } 1746 m->m_len = RE_RX_DESC_BUFLEN; 1747 if (sc->rl_head == NULL) 1748 sc->rl_head = sc->rl_tail = m; 1749 else { 1750 m->m_flags &= ~M_PKTHDR; 1751 sc->rl_tail->m_next = m; 1752 sc->rl_tail = m; 1753 } 1754 continue; 1755 } 1756 1757 /* 1758 * NOTE: for the 8139C+, the frame length field 1759 * is always 12 bits in size, but for the gigE chips, 1760 * it is 13 bits (since the max RX frame length is 16K). 1761 * Unfortunately, all 32 bits in the status word 1762 * were already used, so to make room for the extra 1763 * length bit, RealTek took out the 'frame alignment 1764 * error' bit and shifted the other status bits 1765 * over one slot. The OWN, EOR, FS and LS bits are 1766 * still in the same places. We have already extracted 1767 * the frame length and checked the OWN bit, so rather 1768 * than using an alternate bit mapping, we shift the 1769 * status bits one space to the right so we can evaluate 1770 * them using the 8169 status as though it was in the 1771 * same format as that of the 8139C+. 1772 */ 1773 if (sc->rl_type == RL_8169) 1774 rxstat >>= 1; 1775 1776 /* 1777 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1778 * set, but if CRC is clear, it will still be a valid frame. 1779 */ 1780 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1781 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1782 ifp->if_ierrors++; 1783 /* 1784 * If this is part of a multi-fragment packet, 1785 * discard all the pieces. 1786 */ 1787 if (sc->rl_head != NULL) { 1788 m_freem(sc->rl_head); 1789 sc->rl_head = sc->rl_tail = NULL; 1790 } 1791 re_discard_rxbuf(sc, i); 1792 continue; 1793 } 1794 1795 /* 1796 * If allocating a replacement mbuf fails, 1797 * reload the current one. 1798 */ 1799 1800 if (re_newbuf(sc, i) != 0) { 1801 ifp->if_iqdrops++; 1802 if (sc->rl_head != NULL) { 1803 m_freem(sc->rl_head); 1804 sc->rl_head = sc->rl_tail = NULL; 1805 } 1806 re_discard_rxbuf(sc, i); 1807 continue; 1808 } 1809 1810 if (sc->rl_head != NULL) { 1811 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1812 if (m->m_len == 0) 1813 m->m_len = RE_RX_DESC_BUFLEN; 1814 /* 1815 * Special case: if there's 4 bytes or less 1816 * in this buffer, the mbuf can be discarded: 1817 * the last 4 bytes is the CRC, which we don't 1818 * care about anyway. 1819 */ 1820 if (m->m_len <= ETHER_CRC_LEN) { 1821 sc->rl_tail->m_len -= 1822 (ETHER_CRC_LEN - m->m_len); 1823 m_freem(m); 1824 } else { 1825 m->m_len -= ETHER_CRC_LEN; 1826 m->m_flags &= ~M_PKTHDR; 1827 sc->rl_tail->m_next = m; 1828 } 1829 m = sc->rl_head; 1830 sc->rl_head = sc->rl_tail = NULL; 1831 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1832 } else 1833 m->m_pkthdr.len = m->m_len = 1834 (total_len - ETHER_CRC_LEN); 1835 1836#ifdef RE_FIXUP_RX 1837 re_fixup_rx(m); 1838#endif 1839 ifp->if_ipackets++; 1840 m->m_pkthdr.rcvif = ifp; 1841 1842 /* Do RX checksumming if enabled */ 1843 1844 if (ifp->if_capenable & IFCAP_RXCSUM) { 1845 1846 /* Check IP header checksum */ 1847 if (rxstat & RL_RDESC_STAT_PROTOID) 1848 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1849 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1850 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1851 1852 /* Check TCP/UDP checksum */ 1853 if ((RL_TCPPKT(rxstat) && 1854 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1855 (RL_UDPPKT(rxstat) && 1856 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1857 m->m_pkthdr.csum_flags |= 1858 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1859 m->m_pkthdr.csum_data = 0xffff; 1860 } 1861 } 1862 maxpkt--; 1863 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1864 m->m_pkthdr.ether_vtag = 1865 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1866 m->m_flags |= M_VLANTAG; 1867 } 1868 RL_UNLOCK(sc); 1869 (*ifp->if_input)(ifp, m); 1870 RL_LOCK(sc); 1871 } 1872 1873 /* Flush the RX DMA ring */ 1874 1875 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1876 sc->rl_ldata.rl_rx_list_map, 1877 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1878 1879 sc->rl_ldata.rl_rx_prodidx = i; 1880 1881 if (maxpkt) 1882 return(EAGAIN); 1883 1884 return(0); 1885} 1886 1887static void 1888re_txeof(sc) 1889 struct rl_softc *sc; 1890{ 1891 struct ifnet *ifp; 1892 struct rl_txdesc *txd; 1893 u_int32_t txstat; 1894 int cons; 1895 1896 cons = sc->rl_ldata.rl_tx_considx; 1897 if (cons == sc->rl_ldata.rl_tx_prodidx) 1898 return; 1899 1900 ifp = sc->rl_ifp; 1901 /* Invalidate the TX descriptor list */ 1902 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1903 sc->rl_ldata.rl_tx_list_map, 1904 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1905 1906 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1907 cons = RL_TX_DESC_NXT(sc, cons)) { 1908 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1909 if (txstat & RL_TDESC_STAT_OWN) 1910 break; 1911 /* 1912 * We only stash mbufs in the last descriptor 1913 * in a fragment chain, which also happens to 1914 * be the only place where the TX status bits 1915 * are valid. 1916 */ 1917 if (txstat & RL_TDESC_CMD_EOF) { 1918 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1919 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1920 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1921 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1922 txd->tx_dmamap); 1923 KASSERT(txd->tx_m != NULL, 1924 ("%s: freeing NULL mbufs!", __func__)); 1925 m_freem(txd->tx_m); 1926 txd->tx_m = NULL; 1927 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1928 RL_TDESC_STAT_COLCNT)) 1929 ifp->if_collisions++; 1930 if (txstat & RL_TDESC_STAT_TXERRSUM) 1931 ifp->if_oerrors++; 1932 else 1933 ifp->if_opackets++; 1934 } 1935 sc->rl_ldata.rl_tx_free++; 1936 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1937 } 1938 sc->rl_ldata.rl_tx_considx = cons; 1939 1940 /* No changes made to the TX ring, so no flush needed */ 1941 1942 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1943 /* 1944 * Some chips will ignore a second TX request issued 1945 * while an existing transmission is in progress. If 1946 * the transmitter goes idle but there are still 1947 * packets waiting to be sent, we need to restart the 1948 * channel here to flush them out. This only seems to 1949 * be required with the PCIe devices. 1950 */ 1951 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1952 1953#ifdef RE_TX_MODERATION 1954 /* 1955 * If not all descriptors have been reaped yet, reload 1956 * the timer so that we will eventually get another 1957 * interrupt that will cause us to re-enter this routine. 1958 * This is done in case the transmitter has gone idle. 1959 */ 1960 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1961#endif 1962 } else 1963 sc->rl_watchdog_timer = 0; 1964} 1965 1966static void 1967re_tick(xsc) 1968 void *xsc; 1969{ 1970 struct rl_softc *sc; 1971 struct mii_data *mii; 1972 struct ifnet *ifp; 1973 1974 sc = xsc; 1975 ifp = sc->rl_ifp; 1976 1977 RL_LOCK_ASSERT(sc); 1978 1979 re_watchdog(sc); 1980 1981 mii = device_get_softc(sc->rl_miibus); 1982 mii_tick(mii); 1983 if (sc->rl_link) { 1984 if (!(mii->mii_media_status & IFM_ACTIVE)) 1985 sc->rl_link = 0; 1986 } else { 1987 if (mii->mii_media_status & IFM_ACTIVE && 1988 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1989 sc->rl_link = 1; 1990 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1991 taskqueue_enqueue_fast(taskqueue_fast, 1992 &sc->rl_txtask); 1993 } 1994 } 1995 1996 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1997} 1998 1999#ifdef DEVICE_POLLING 2000static void 2001re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2002{ 2003 struct rl_softc *sc = ifp->if_softc; 2004 2005 RL_LOCK(sc); 2006 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2007 re_poll_locked(ifp, cmd, count); 2008 RL_UNLOCK(sc); 2009} 2010 2011static void 2012re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2013{ 2014 struct rl_softc *sc = ifp->if_softc; 2015 2016 RL_LOCK_ASSERT(sc); 2017 2018 sc->rxcycles = count; 2019 re_rxeof(sc); 2020 re_txeof(sc); 2021 2022 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2023 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2024 2025 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2026 u_int16_t status; 2027 2028 status = CSR_READ_2(sc, RL_ISR); 2029 if (status == 0xffff) 2030 return; 2031 if (status) 2032 CSR_WRITE_2(sc, RL_ISR, status); 2033 2034 /* 2035 * XXX check behaviour on receiver stalls. 2036 */ 2037 2038 if (status & RL_ISR_SYSTEM_ERR) { 2039 re_reset(sc); 2040 re_init_locked(sc); 2041 } 2042 } 2043} 2044#endif /* DEVICE_POLLING */ 2045 2046static int 2047re_intr(arg) 2048 void *arg; 2049{ 2050 struct rl_softc *sc; 2051 uint16_t status; 2052 2053 sc = arg; 2054 2055 status = CSR_READ_2(sc, RL_ISR); 2056 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2057 return (FILTER_STRAY); 2058 CSR_WRITE_2(sc, RL_IMR, 0); 2059 2060 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2061 2062 return (FILTER_HANDLED); 2063} 2064 2065static void 2066re_int_task(arg, npending) 2067 void *arg; 2068 int npending; 2069{ 2070 struct rl_softc *sc; 2071 struct ifnet *ifp; 2072 u_int16_t status; 2073 int rval = 0; 2074 2075 sc = arg; 2076 ifp = sc->rl_ifp; 2077 2078 RL_LOCK(sc); 2079 2080 status = CSR_READ_2(sc, RL_ISR); 2081 CSR_WRITE_2(sc, RL_ISR, status); 2082 2083 if (sc->suspended || 2084 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2085 RL_UNLOCK(sc); 2086 return; 2087 } 2088 2089#ifdef DEVICE_POLLING 2090 if (ifp->if_capenable & IFCAP_POLLING) { 2091 RL_UNLOCK(sc); 2092 return; 2093 } 2094#endif 2095 2096 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2097 rval = re_rxeof(sc); 2098 2099#ifdef RE_TX_MODERATION 2100 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2101#else 2102 if (status & (RL_ISR_TX_OK| 2103#endif 2104 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2105 re_txeof(sc); 2106 2107 if (status & RL_ISR_SYSTEM_ERR) { 2108 re_reset(sc); 2109 re_init_locked(sc); 2110 } 2111 2112 if (status & RL_ISR_LINKCHG) { 2113 callout_stop(&sc->rl_stat_callout); 2114 re_tick(sc); 2115 } 2116 2117 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2118 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2119 2120 RL_UNLOCK(sc); 2121 2122 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2123 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2124 return; 2125 } 2126 2127 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2128 2129 return; 2130} 2131 2132static int 2133re_encap(sc, m_head) 2134 struct rl_softc *sc; 2135 struct mbuf **m_head; 2136{ 2137 struct rl_txdesc *txd, *txd_last; 2138 bus_dma_segment_t segs[RL_NTXSEGS]; 2139 bus_dmamap_t map; 2140 struct mbuf *m_new; 2141 struct rl_desc *desc; 2142 int nsegs, prod; 2143 int i, error, ei, si; 2144 int padlen; 2145 uint32_t cmdstat, csum_flags, vlanctl; 2146 2147 RL_LOCK_ASSERT(sc); 2148 M_ASSERTPKTHDR((*m_head)); 2149 2150 /* 2151 * With some of the RealTek chips, using the checksum offload 2152 * support in conjunction with the autopadding feature results 2153 * in the transmission of corrupt frames. For example, if we 2154 * need to send a really small IP fragment that's less than 60 2155 * bytes in size, and IP header checksumming is enabled, the 2156 * resulting ethernet frame that appears on the wire will 2157 * have garbled payload. To work around this, if TX checksum 2158 * offload is enabled, we always manually pad short frames out 2159 * to the minimum ethernet frame size. 2160 * 2161 * Note: this appears unnecessary for TCP, and doing it for TCP 2162 * with PCIe adapters seems to result in bad checksums. 2163 */ 2164 if ((*m_head)->m_pkthdr.csum_flags & (CSUM_IP | CSUM_UDP) && 2165 ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2166 (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) { 2167 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2168 if (M_WRITABLE(*m_head) == 0) { 2169 /* Get a writable copy. */ 2170 m_new = m_dup(*m_head, M_DONTWAIT); 2171 m_freem(*m_head); 2172 if (m_new == NULL) { 2173 *m_head = NULL; 2174 return (ENOBUFS); 2175 } 2176 *m_head = m_new; 2177 } 2178 if ((*m_head)->m_next != NULL || 2179 M_TRAILINGSPACE(*m_head) < padlen) { 2180 m_new = m_defrag(*m_head, M_DONTWAIT); 2181 if (m_new == NULL) { 2182 m_freem(*m_head); 2183 *m_head = NULL; 2184 return (ENOBUFS); 2185 } 2186 } else 2187 m_new = *m_head; 2188 2189 /* 2190 * Manually pad short frames, and zero the pad space 2191 * to avoid leaking data. 2192 */ 2193 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2194 m_new->m_pkthdr.len += padlen; 2195 m_new->m_len = m_new->m_pkthdr.len; 2196 *m_head = m_new; 2197 } 2198 2199 prod = sc->rl_ldata.rl_tx_prodidx; 2200 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2201 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2202 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2203 if (error == EFBIG) { 2204 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2205 if (m_new == NULL) { 2206 m_freem(*m_head); 2207 *m_head = NULL; 2208 return (ENOBUFS); 2209 } 2210 *m_head = m_new; 2211 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2212 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2213 if (error != 0) { 2214 m_freem(*m_head); 2215 *m_head = NULL; 2216 return (error); 2217 } 2218 } else if (error != 0) 2219 return (error); 2220 if (nsegs == 0) { 2221 m_freem(*m_head); 2222 *m_head = NULL; 2223 return (EIO); 2224 } 2225 2226 /* Check for number of available descriptors. */ 2227 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2228 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2229 return (ENOBUFS); 2230 } 2231 2232 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2233 BUS_DMASYNC_PREWRITE); 2234 2235 /* 2236 * Set up checksum offload. Note: checksum offload bits must 2237 * appear in all descriptors of a multi-descriptor transmit 2238 * attempt. This is according to testing done with an 8169 2239 * chip. This is a requirement. 2240 */ 2241 csum_flags = 0; 2242 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2243 csum_flags = RL_TDESC_CMD_LGSEND | 2244 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2245 RL_TDESC_CMD_MSSVAL_SHIFT); 2246 else { 2247 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2248 csum_flags |= RL_TDESC_CMD_IPCSUM; 2249 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2250 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2251 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2252 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2253 } 2254 2255 /* 2256 * Set up hardware VLAN tagging. Note: vlan tag info must 2257 * appear in all descriptors of a multi-descriptor 2258 * transmission attempt. 2259 */ 2260 vlanctl = 0; 2261 if ((*m_head)->m_flags & M_VLANTAG) 2262 vlanctl = 2263 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2264 RL_TDESC_VLANCTL_TAG); 2265 2266 si = prod; 2267 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2268 desc = &sc->rl_ldata.rl_tx_list[prod]; 2269 desc->rl_vlanctl = vlanctl; 2270 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2271 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2272 cmdstat = segs[i].ds_len; 2273 if (i != 0) 2274 cmdstat |= RL_TDESC_CMD_OWN; 2275 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2276 cmdstat |= RL_TDESC_CMD_EOR; 2277 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2278 sc->rl_ldata.rl_tx_free--; 2279 } 2280 /* Update producer index. */ 2281 sc->rl_ldata.rl_tx_prodidx = prod; 2282 2283 /* Set EOF on the last descriptor. */ 2284 ei = RL_TX_DESC_PRV(sc, prod); 2285 desc = &sc->rl_ldata.rl_tx_list[ei]; 2286 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2287 2288 desc = &sc->rl_ldata.rl_tx_list[si]; 2289 /* Set SOF and transfer ownership of packet to the chip. */ 2290 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2291 2292 /* 2293 * Insure that the map for this transmission 2294 * is placed at the array index of the last descriptor 2295 * in this chain. (Swap last and first dmamaps.) 2296 */ 2297 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2298 map = txd->tx_dmamap; 2299 txd->tx_dmamap = txd_last->tx_dmamap; 2300 txd_last->tx_dmamap = map; 2301 txd_last->tx_m = *m_head; 2302 2303 return (0); 2304} 2305 2306static void 2307re_tx_task(arg, npending) 2308 void *arg; 2309 int npending; 2310{ 2311 struct ifnet *ifp; 2312 2313 ifp = arg; 2314 re_start(ifp); 2315 2316 return; 2317} 2318 2319/* 2320 * Main transmit routine for C+ and gigE NICs. 2321 */ 2322static void 2323re_start(ifp) 2324 struct ifnet *ifp; 2325{ 2326 struct rl_softc *sc; 2327 struct mbuf *m_head; 2328 int queued; 2329 2330 sc = ifp->if_softc; 2331 2332 RL_LOCK(sc); 2333 2334 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2335 IFF_DRV_RUNNING || sc->rl_link == 0) { 2336 RL_UNLOCK(sc); 2337 return; 2338 } 2339 2340 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2341 sc->rl_ldata.rl_tx_free > 1;) { 2342 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2343 if (m_head == NULL) 2344 break; 2345 2346 if (re_encap(sc, &m_head) != 0) { 2347 if (m_head == NULL) 2348 break; 2349 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2350 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2351 break; 2352 } 2353 2354 /* 2355 * If there's a BPF listener, bounce a copy of this frame 2356 * to him. 2357 */ 2358 ETHER_BPF_MTAP(ifp, m_head); 2359 2360 queued++; 2361 } 2362 2363 if (queued == 0) { 2364#ifdef RE_TX_MODERATION 2365 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2366 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2367#endif 2368 RL_UNLOCK(sc); 2369 return; 2370 } 2371 2372 /* Flush the TX descriptors */ 2373 2374 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2375 sc->rl_ldata.rl_tx_list_map, 2376 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2377 2378 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2379 2380#ifdef RE_TX_MODERATION 2381 /* 2382 * Use the countdown timer for interrupt moderation. 2383 * 'TX done' interrupts are disabled. Instead, we reset the 2384 * countdown timer, which will begin counting until it hits 2385 * the value in the TIMERINT register, and then trigger an 2386 * interrupt. Each time we write to the TIMERCNT register, 2387 * the timer count is reset to 0. 2388 */ 2389 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2390#endif 2391 2392 /* 2393 * Set a timeout in case the chip goes out to lunch. 2394 */ 2395 sc->rl_watchdog_timer = 5; 2396 2397 RL_UNLOCK(sc); 2398 2399 return; 2400} 2401 2402static void 2403re_init(xsc) 2404 void *xsc; 2405{ 2406 struct rl_softc *sc = xsc; 2407 2408 RL_LOCK(sc); 2409 re_init_locked(sc); 2410 RL_UNLOCK(sc); 2411} 2412 2413static void 2414re_init_locked(sc) 2415 struct rl_softc *sc; 2416{ 2417 struct ifnet *ifp = sc->rl_ifp; 2418 struct mii_data *mii; 2419 u_int32_t rxcfg = 0; 2420 uint16_t cfg; 2421 union { 2422 uint32_t align_dummy; 2423 u_char eaddr[ETHER_ADDR_LEN]; 2424 } eaddr; 2425 2426 RL_LOCK_ASSERT(sc); 2427 2428 mii = device_get_softc(sc->rl_miibus); 2429 2430 /* 2431 * Cancel pending I/O and free all RX/TX buffers. 2432 */ 2433 re_stop(sc); 2434 2435 /* 2436 * Enable C+ RX and TX mode, as well as VLAN stripping and 2437 * RX checksum offload. We must configure the C+ register 2438 * before all others. 2439 */ 2440 cfg = RL_CPLUSCMD_PCI_MRW; 2441 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2442 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2443 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2444 cfg |= RL_CPLUSCMD_VLANSTRIP; 2445 CSR_WRITE_2(sc, RL_CPLUS_CMD, 2446 cfg | RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB); 2447 2448 /* 2449 * Init our MAC address. Even though the chipset 2450 * documentation doesn't mention it, we need to enter "Config 2451 * register write enable" mode to modify the ID registers. 2452 */ 2453 /* Copy MAC address on stack to align. */ 2454 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2455 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2456 CSR_WRITE_4(sc, RL_IDR0, 2457 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2458 CSR_WRITE_4(sc, RL_IDR4, 2459 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2460 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2461 2462 /* 2463 * For C+ mode, initialize the RX descriptors and mbufs. 2464 */ 2465 re_rx_list_init(sc); 2466 re_tx_list_init(sc); 2467 2468 /* 2469 * Load the addresses of the RX and TX lists into the chip. 2470 */ 2471 2472 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2473 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2474 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2475 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2476 2477 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2478 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2479 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2480 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2481 2482 /* 2483 * Enable transmit and receive. 2484 */ 2485 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2486 2487 /* 2488 * Set the initial TX and RX configuration. 2489 */ 2490 if (sc->rl_testmode) { 2491 if (sc->rl_type == RL_8169) 2492 CSR_WRITE_4(sc, RL_TXCFG, 2493 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2494 else 2495 CSR_WRITE_4(sc, RL_TXCFG, 2496 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2497 } else 2498 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2499 2500 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2501 2502 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2503 2504 /* Set the individual bit to receive frames for this host only. */ 2505 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2506 rxcfg |= RL_RXCFG_RX_INDIV; 2507 2508 /* If we want promiscuous mode, set the allframes bit. */ 2509 if (ifp->if_flags & IFF_PROMISC) 2510 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2511 else 2512 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2513 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2514 2515 /* 2516 * Set capture broadcast bit to capture broadcast frames. 2517 */ 2518 if (ifp->if_flags & IFF_BROADCAST) 2519 rxcfg |= RL_RXCFG_RX_BROAD; 2520 else 2521 rxcfg &= ~RL_RXCFG_RX_BROAD; 2522 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2523 2524 /* 2525 * Program the multicast filter, if necessary. 2526 */ 2527 re_setmulti(sc); 2528 2529#ifdef DEVICE_POLLING 2530 /* 2531 * Disable interrupts if we are polling. 2532 */ 2533 if (ifp->if_capenable & IFCAP_POLLING) 2534 CSR_WRITE_2(sc, RL_IMR, 0); 2535 else /* otherwise ... */ 2536#endif 2537 2538 /* 2539 * Enable interrupts. 2540 */ 2541 if (sc->rl_testmode) 2542 CSR_WRITE_2(sc, RL_IMR, 0); 2543 else 2544 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2545 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2546 2547 /* Set initial TX threshold */ 2548 sc->rl_txthresh = RL_TX_THRESH_INIT; 2549 2550 /* Start RX/TX process. */ 2551 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2552#ifdef notdef 2553 /* Enable receiver and transmitter. */ 2554 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2555#endif 2556 2557#ifdef RE_TX_MODERATION 2558 /* 2559 * Initialize the timer interrupt register so that 2560 * a timer interrupt will be generated once the timer 2561 * reaches a certain number of ticks. The timer is 2562 * reloaded on each transmit. This gives us TX interrupt 2563 * moderation, which dramatically improves TX frame rate. 2564 */ 2565 if (sc->rl_type == RL_8169) 2566 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2567 else 2568 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2569#endif 2570 2571 /* 2572 * For 8169 gigE NICs, set the max allowed RX packet 2573 * size so we can receive jumbo frames. 2574 */ 2575 if (sc->rl_type == RL_8169) 2576 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2577 2578 if (sc->rl_testmode) 2579 return; 2580 2581 mii_mediachg(mii); 2582 2583 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2584 2585 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2586 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2587 2588 sc->rl_link = 0; 2589 sc->rl_watchdog_timer = 0; 2590 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2591} 2592 2593/* 2594 * Set media options. 2595 */ 2596static int 2597re_ifmedia_upd(ifp) 2598 struct ifnet *ifp; 2599{ 2600 struct rl_softc *sc; 2601 struct mii_data *mii; 2602 2603 sc = ifp->if_softc; 2604 mii = device_get_softc(sc->rl_miibus); 2605 RL_LOCK(sc); 2606 mii_mediachg(mii); 2607 RL_UNLOCK(sc); 2608 2609 return (0); 2610} 2611 2612/* 2613 * Report current media status. 2614 */ 2615static void 2616re_ifmedia_sts(ifp, ifmr) 2617 struct ifnet *ifp; 2618 struct ifmediareq *ifmr; 2619{ 2620 struct rl_softc *sc; 2621 struct mii_data *mii; 2622 2623 sc = ifp->if_softc; 2624 mii = device_get_softc(sc->rl_miibus); 2625 2626 RL_LOCK(sc); 2627 mii_pollstat(mii); 2628 RL_UNLOCK(sc); 2629 ifmr->ifm_active = mii->mii_media_active; 2630 ifmr->ifm_status = mii->mii_media_status; 2631} 2632 2633static int 2634re_ioctl(ifp, command, data) 2635 struct ifnet *ifp; 2636 u_long command; 2637 caddr_t data; 2638{ 2639 struct rl_softc *sc = ifp->if_softc; 2640 struct ifreq *ifr = (struct ifreq *) data; 2641 struct mii_data *mii; 2642 int error = 0; 2643 2644 switch (command) { 2645 case SIOCSIFMTU: 2646 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2647 error = EINVAL; 2648 break; 2649 } 2650 if (sc->rl_type == RL_8139CPLUS && 2651 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2652 error = EINVAL; 2653 break; 2654 } 2655 RL_LOCK(sc); 2656 if (ifp->if_mtu != ifr->ifr_mtu) 2657 ifp->if_mtu = ifr->ifr_mtu; 2658 RL_UNLOCK(sc); 2659 break; 2660 case SIOCSIFFLAGS: 2661 RL_LOCK(sc); 2662 if ((ifp->if_flags & IFF_UP) != 0) { 2663 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2664 if (((ifp->if_flags ^ sc->rl_if_flags) 2665 & IFF_PROMISC) != 0) 2666 re_setmulti(sc); 2667 } else 2668 re_init_locked(sc); 2669 } else { 2670 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2671 re_stop(sc); 2672 } 2673 sc->rl_if_flags = ifp->if_flags; 2674 RL_UNLOCK(sc); 2675 break; 2676 case SIOCADDMULTI: 2677 case SIOCDELMULTI: 2678 RL_LOCK(sc); 2679 re_setmulti(sc); 2680 RL_UNLOCK(sc); 2681 break; 2682 case SIOCGIFMEDIA: 2683 case SIOCSIFMEDIA: 2684 mii = device_get_softc(sc->rl_miibus); 2685 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2686 break; 2687 case SIOCSIFCAP: 2688 { 2689 int mask, reinit; 2690 2691 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2692 reinit = 0; 2693#ifdef DEVICE_POLLING 2694 if (mask & IFCAP_POLLING) { 2695 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2696 error = ether_poll_register(re_poll, ifp); 2697 if (error) 2698 return(error); 2699 RL_LOCK(sc); 2700 /* Disable interrupts */ 2701 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2702 ifp->if_capenable |= IFCAP_POLLING; 2703 RL_UNLOCK(sc); 2704 } else { 2705 error = ether_poll_deregister(ifp); 2706 /* Enable interrupts. */ 2707 RL_LOCK(sc); 2708 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2709 ifp->if_capenable &= ~IFCAP_POLLING; 2710 RL_UNLOCK(sc); 2711 } 2712 } 2713#endif /* DEVICE_POLLING */ 2714 if (mask & IFCAP_HWCSUM) { 2715 ifp->if_capenable ^= IFCAP_HWCSUM; 2716 if (ifp->if_capenable & IFCAP_TXCSUM) 2717 ifp->if_hwassist |= RE_CSUM_FEATURES; 2718 else 2719 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2720 reinit = 1; 2721 } 2722 if (mask & IFCAP_VLAN_HWTAGGING) { 2723 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2724 reinit = 1; 2725 } 2726 if (mask & IFCAP_TSO4) { 2727 ifp->if_capenable ^= IFCAP_TSO4; 2728 if ((IFCAP_TSO4 & ifp->if_capenable) && 2729 (IFCAP_TSO4 & ifp->if_capabilities)) 2730 ifp->if_hwassist |= CSUM_TSO; 2731 else 2732 ifp->if_hwassist &= ~CSUM_TSO; 2733 } 2734 if ((mask & IFCAP_WOL) != 0 && 2735 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2736 if ((mask & IFCAP_WOL_UCAST) != 0) 2737 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2738 if ((mask & IFCAP_WOL_MCAST) != 0) 2739 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2740 if ((mask & IFCAP_WOL_MAGIC) != 0) 2741 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2742 } 2743 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2744 re_init(sc); 2745 VLAN_CAPABILITIES(ifp); 2746 } 2747 break; 2748 default: 2749 error = ether_ioctl(ifp, command, data); 2750 break; 2751 } 2752 2753 return (error); 2754} 2755 2756static void 2757re_watchdog(sc) 2758 struct rl_softc *sc; 2759{ 2760 2761 RL_LOCK_ASSERT(sc); 2762 2763 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2764 return; 2765 2766 device_printf(sc->rl_dev, "watchdog timeout\n"); 2767 sc->rl_ifp->if_oerrors++; 2768 2769 re_txeof(sc); 2770 re_rxeof(sc); 2771 re_init_locked(sc); 2772} 2773 2774/* 2775 * Stop the adapter and free any mbufs allocated to the 2776 * RX and TX lists. 2777 */ 2778static void 2779re_stop(sc) 2780 struct rl_softc *sc; 2781{ 2782 register int i; 2783 struct ifnet *ifp; 2784 struct rl_txdesc *txd; 2785 struct rl_rxdesc *rxd; 2786 2787 RL_LOCK_ASSERT(sc); 2788 2789 ifp = sc->rl_ifp; 2790 2791 sc->rl_watchdog_timer = 0; 2792 callout_stop(&sc->rl_stat_callout); 2793 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2794 2795 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2796 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2797 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2798 2799 if (sc->rl_head != NULL) { 2800 m_freem(sc->rl_head); 2801 sc->rl_head = sc->rl_tail = NULL; 2802 } 2803 2804 /* Free the TX list buffers. */ 2805 2806 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2807 txd = &sc->rl_ldata.rl_tx_desc[i]; 2808 if (txd->tx_m != NULL) { 2809 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2810 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2811 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2812 txd->tx_dmamap); 2813 m_freem(txd->tx_m); 2814 txd->tx_m = NULL; 2815 } 2816 } 2817 2818 /* Free the RX list buffers. */ 2819 2820 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2821 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2822 if (rxd->rx_m != NULL) { 2823 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2824 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2825 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2826 rxd->rx_dmamap); 2827 m_freem(rxd->rx_m); 2828 rxd->rx_m = NULL; 2829 } 2830 } 2831} 2832 2833/* 2834 * Device suspend routine. Stop the interface and save some PCI 2835 * settings in case the BIOS doesn't restore them properly on 2836 * resume. 2837 */ 2838static int 2839re_suspend(dev) 2840 device_t dev; 2841{ 2842 struct rl_softc *sc; 2843 2844 sc = device_get_softc(dev); 2845 2846 RL_LOCK(sc); 2847 re_stop(sc); 2848 re_setwol(sc); 2849 sc->suspended = 1; 2850 RL_UNLOCK(sc); 2851 2852 return (0); 2853} 2854 2855/* 2856 * Device resume routine. Restore some PCI settings in case the BIOS 2857 * doesn't, re-enable busmastering, and restart the interface if 2858 * appropriate. 2859 */ 2860static int 2861re_resume(dev) 2862 device_t dev; 2863{ 2864 struct rl_softc *sc; 2865 struct ifnet *ifp; 2866 2867 sc = device_get_softc(dev); 2868 2869 RL_LOCK(sc); 2870 2871 ifp = sc->rl_ifp; 2872 2873 /* reinitialize interface if necessary */ 2874 if (ifp->if_flags & IFF_UP) 2875 re_init_locked(sc); 2876 2877 /* 2878 * Clear WOL matching such that normal Rx filtering 2879 * wouldn't interfere with WOL patterns. 2880 */ 2881 re_clrwol(sc); 2882 sc->suspended = 0; 2883 RL_UNLOCK(sc); 2884 2885 return (0); 2886} 2887 2888/* 2889 * Stop all chip I/O so that the kernel's probe routines don't 2890 * get confused by errant DMAs when rebooting. 2891 */ 2892static int 2893re_shutdown(dev) 2894 device_t dev; 2895{ 2896 struct rl_softc *sc; 2897 2898 sc = device_get_softc(dev); 2899 2900 RL_LOCK(sc); 2901 re_stop(sc); 2902 /* 2903 * Mark interface as down since otherwise we will panic if 2904 * interrupt comes in later on, which can happen in some 2905 * cases. 2906 */ 2907 sc->rl_ifp->if_flags &= ~IFF_UP; 2908 re_setwol(sc); 2909 RL_UNLOCK(sc); 2910 2911 return (0); 2912} 2913 2914static void 2915re_setwol(sc) 2916 struct rl_softc *sc; 2917{ 2918 struct ifnet *ifp; 2919 int pmc; 2920 uint16_t pmstat; 2921 uint8_t v; 2922 2923 RL_LOCK_ASSERT(sc); 2924 2925 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2926 return; 2927 2928 ifp = sc->rl_ifp; 2929 /* Enable config register write. */ 2930 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2931 2932 /* Enable PME. */ 2933 v = CSR_READ_1(sc, RL_CFG1); 2934 v &= ~RL_CFG1_PME; 2935 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2936 v |= RL_CFG1_PME; 2937 CSR_WRITE_1(sc, RL_CFG1, v); 2938 2939 v = CSR_READ_1(sc, RL_CFG3); 2940 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2941 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2942 v |= RL_CFG3_WOL_MAGIC; 2943 CSR_WRITE_1(sc, RL_CFG3, v); 2944 2945 /* Config register write done. */ 2946 CSR_WRITE_1(sc, RL_EECMD, 0); 2947 2948 v = CSR_READ_1(sc, RL_CFG5); 2949 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2950 v &= ~RL_CFG5_WOL_LANWAKE; 2951 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2952 v |= RL_CFG5_WOL_UCAST; 2953 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2954 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 2955 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2956 v |= RL_CFG5_WOL_LANWAKE; 2957 CSR_WRITE_1(sc, RL_CFG5, v); 2958 2959 /* 2960 * It seems that hardware resets its link speed to 100Mbps in 2961 * power down mode so switching to 100Mbps in driver is not 2962 * needed. 2963 */ 2964 2965 /* Request PME if WOL is requested. */ 2966 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 2967 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2968 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2969 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2970 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2971} 2972 2973static void 2974re_clrwol(sc) 2975 struct rl_softc *sc; 2976{ 2977 int pmc; 2978 uint8_t v; 2979 2980 RL_LOCK_ASSERT(sc); 2981 2982 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2983 return; 2984 2985 /* Enable config register write. */ 2986 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2987 2988 v = CSR_READ_1(sc, RL_CFG3); 2989 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2990 CSR_WRITE_1(sc, RL_CFG3, v); 2991 2992 /* Config register write done. */ 2993 CSR_WRITE_1(sc, RL_EECMD, 0); 2994 2995 v = CSR_READ_1(sc, RL_CFG5); 2996 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2997 v &= ~RL_CFG5_WOL_LANWAKE; 2998 CSR_WRITE_1(sc, RL_CFG5, v); 2999} 3000