if_re.c revision 174203
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 174203 2007-12-03 01:28:08Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149MODULE_DEPEND(re, pci, 1, 1, 1); 150MODULE_DEPEND(re, ether, 1, 1, 1); 151MODULE_DEPEND(re, miibus, 1, 1, 1); 152 153/* "device miibus" required. See GENERIC if you get errors here. */ 154#include "miibus_if.h" 155 156/* 157 * Default to using PIO access for this driver. 158 */ 159#define RE_USEIOSPACE 160 161#include <pci/if_rlreg.h> 162 163/* Tunables. */ 164static int msi_disable = 0; 165TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166 167#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 168 169/* 170 * Various supported device vendors/types and their names. 171 */ 172static struct rl_type re_devs[] = { 173 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 174 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169_8110SB, 176 "D-Link DGE-528(T) Rev.B1 Gigabit Ethernet Adapter" }, 177 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 178 "RealTek 8139C+ 10/100BaseTX" }, 179 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 180 "RealTek 8101E PCIe 10/100baseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 182 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 184 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 186 "RealTek 8169 Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 188 "RealTek 8169S Single-chip Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 190 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 191 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC, 192 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 194 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 195 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 196 "RealTek 8110S Single-chip Gigabit Ethernet" }, 197 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 198 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 199 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 200 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 201 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 202 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }, 203 { 0, 0, 0, NULL } 204}; 205 206static struct rl_hwrev re_hwrevs[] = { 207 { RL_HWREV_8139, RL_8139, "" }, 208 { RL_HWREV_8139A, RL_8139, "A" }, 209 { RL_HWREV_8139AG, RL_8139, "A-G" }, 210 { RL_HWREV_8139B, RL_8139, "B" }, 211 { RL_HWREV_8130, RL_8139, "8130" }, 212 { RL_HWREV_8139C, RL_8139, "C" }, 213 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 214 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 215 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 216 { RL_HWREV_8169, RL_8169, "8169"}, 217 { RL_HWREV_8169S, RL_8169, "8169S"}, 218 { RL_HWREV_8110S, RL_8169, "8110S"}, 219 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 220 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 221 { RL_HWREV_8100, RL_8139, "8100"}, 222 { RL_HWREV_8101, RL_8139, "8101"}, 223 { RL_HWREV_8100E, RL_8169, "8100E"}, 224 { RL_HWREV_8101E, RL_8169, "8101E"}, 225 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 226 { 0, 0, NULL } 227}; 228 229static int re_probe (device_t); 230static int re_attach (device_t); 231static int re_detach (device_t); 232 233static int re_encap (struct rl_softc *, struct mbuf **, int *); 234 235static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 236static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 237 bus_size_t, int); 238static int re_allocmem (device_t, struct rl_softc *); 239static int re_newbuf (struct rl_softc *, int, struct mbuf *); 240static int re_rx_list_init (struct rl_softc *); 241static int re_tx_list_init (struct rl_softc *); 242#ifdef RE_FIXUP_RX 243static __inline void re_fixup_rx 244 (struct mbuf *); 245#endif 246static int re_rxeof (struct rl_softc *); 247static void re_txeof (struct rl_softc *); 248#ifdef DEVICE_POLLING 249static void re_poll (struct ifnet *, enum poll_cmd, int); 250static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 251#endif 252static int re_intr (void *); 253static void re_tick (void *); 254static void re_tx_task (void *, int); 255static void re_int_task (void *, int); 256static void re_start (struct ifnet *); 257static int re_ioctl (struct ifnet *, u_long, caddr_t); 258static void re_init (void *); 259static void re_init_locked (struct rl_softc *); 260static void re_stop (struct rl_softc *); 261static void re_watchdog (struct rl_softc *); 262static int re_suspend (device_t); 263static int re_resume (device_t); 264static int re_shutdown (device_t); 265static int re_ifmedia_upd (struct ifnet *); 266static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 267 268static void re_eeprom_putbyte (struct rl_softc *, int); 269static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 270static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 271static int re_gmii_readreg (device_t, int, int); 272static int re_gmii_writereg (device_t, int, int, int); 273 274static int re_miibus_readreg (device_t, int, int); 275static int re_miibus_writereg (device_t, int, int, int); 276static void re_miibus_statchg (device_t); 277 278static void re_setmulti (struct rl_softc *); 279static void re_reset (struct rl_softc *); 280 281#ifdef RE_DIAG 282static int re_diag (struct rl_softc *); 283#endif 284 285#ifdef RE_USEIOSPACE 286#define RL_RES SYS_RES_IOPORT 287#define RL_RID RL_PCI_LOIO 288#else 289#define RL_RES SYS_RES_MEMORY 290#define RL_RID RL_PCI_LOMEM 291#endif 292 293static device_method_t re_methods[] = { 294 /* Device interface */ 295 DEVMETHOD(device_probe, re_probe), 296 DEVMETHOD(device_attach, re_attach), 297 DEVMETHOD(device_detach, re_detach), 298 DEVMETHOD(device_suspend, re_suspend), 299 DEVMETHOD(device_resume, re_resume), 300 DEVMETHOD(device_shutdown, re_shutdown), 301 302 /* bus interface */ 303 DEVMETHOD(bus_print_child, bus_generic_print_child), 304 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 305 306 /* MII interface */ 307 DEVMETHOD(miibus_readreg, re_miibus_readreg), 308 DEVMETHOD(miibus_writereg, re_miibus_writereg), 309 DEVMETHOD(miibus_statchg, re_miibus_statchg), 310 311 { 0, 0 } 312}; 313 314static driver_t re_driver = { 315 "re", 316 re_methods, 317 sizeof(struct rl_softc) 318}; 319 320static devclass_t re_devclass; 321 322DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 323DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 324DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 325 326#define EE_SET(x) \ 327 CSR_WRITE_1(sc, RL_EECMD, \ 328 CSR_READ_1(sc, RL_EECMD) | x) 329 330#define EE_CLR(x) \ 331 CSR_WRITE_1(sc, RL_EECMD, \ 332 CSR_READ_1(sc, RL_EECMD) & ~x) 333 334/* 335 * Send a read command and address to the EEPROM, check for ACK. 336 */ 337static void 338re_eeprom_putbyte(sc, addr) 339 struct rl_softc *sc; 340 int addr; 341{ 342 register int d, i; 343 344 d = addr | (RL_9346_READ << sc->rl_eewidth); 345 346 /* 347 * Feed in each bit and strobe the clock. 348 */ 349 350 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 351 if (d & i) { 352 EE_SET(RL_EE_DATAIN); 353 } else { 354 EE_CLR(RL_EE_DATAIN); 355 } 356 DELAY(100); 357 EE_SET(RL_EE_CLK); 358 DELAY(150); 359 EE_CLR(RL_EE_CLK); 360 DELAY(100); 361 } 362 363 return; 364} 365 366/* 367 * Read a word of data stored in the EEPROM at address 'addr.' 368 */ 369static void 370re_eeprom_getword(sc, addr, dest) 371 struct rl_softc *sc; 372 int addr; 373 u_int16_t *dest; 374{ 375 register int i; 376 u_int16_t word = 0; 377 378 /* 379 * Send address of word we want to read. 380 */ 381 re_eeprom_putbyte(sc, addr); 382 383 /* 384 * Start reading bits from EEPROM. 385 */ 386 for (i = 0x8000; i; i >>= 1) { 387 EE_SET(RL_EE_CLK); 388 DELAY(100); 389 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 390 word |= i; 391 EE_CLR(RL_EE_CLK); 392 DELAY(100); 393 } 394 395 *dest = word; 396 397 return; 398} 399 400/* 401 * Read a sequence of words from the EEPROM. 402 */ 403static void 404re_read_eeprom(sc, dest, off, cnt) 405 struct rl_softc *sc; 406 caddr_t dest; 407 int off; 408 int cnt; 409{ 410 int i; 411 u_int16_t word = 0, *ptr; 412 413 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 414 415 DELAY(100); 416 417 for (i = 0; i < cnt; i++) { 418 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 419 re_eeprom_getword(sc, off + i, &word); 420 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 421 ptr = (u_int16_t *)(dest + (i * 2)); 422 *ptr = word; 423 } 424 425 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 426 427 return; 428} 429 430static int 431re_gmii_readreg(dev, phy, reg) 432 device_t dev; 433 int phy, reg; 434{ 435 struct rl_softc *sc; 436 u_int32_t rval; 437 int i; 438 439 if (phy != 1) 440 return (0); 441 442 sc = device_get_softc(dev); 443 444 /* Let the rgephy driver read the GMEDIASTAT register */ 445 446 if (reg == RL_GMEDIASTAT) { 447 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 448 return (rval); 449 } 450 451 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 452 DELAY(1000); 453 454 for (i = 0; i < RL_TIMEOUT; i++) { 455 rval = CSR_READ_4(sc, RL_PHYAR); 456 if (rval & RL_PHYAR_BUSY) 457 break; 458 DELAY(100); 459 } 460 461 if (i == RL_TIMEOUT) { 462 device_printf(sc->rl_dev, "PHY read failed\n"); 463 return (0); 464 } 465 466 return (rval & RL_PHYAR_PHYDATA); 467} 468 469static int 470re_gmii_writereg(dev, phy, reg, data) 471 device_t dev; 472 int phy, reg, data; 473{ 474 struct rl_softc *sc; 475 u_int32_t rval; 476 int i; 477 478 sc = device_get_softc(dev); 479 480 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 481 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 482 DELAY(1000); 483 484 for (i = 0; i < RL_TIMEOUT; i++) { 485 rval = CSR_READ_4(sc, RL_PHYAR); 486 if (!(rval & RL_PHYAR_BUSY)) 487 break; 488 DELAY(100); 489 } 490 491 if (i == RL_TIMEOUT) { 492 device_printf(sc->rl_dev, "PHY write failed\n"); 493 return (0); 494 } 495 496 return (0); 497} 498 499static int 500re_miibus_readreg(dev, phy, reg) 501 device_t dev; 502 int phy, reg; 503{ 504 struct rl_softc *sc; 505 u_int16_t rval = 0; 506 u_int16_t re8139_reg = 0; 507 508 sc = device_get_softc(dev); 509 510 if (sc->rl_type == RL_8169) { 511 rval = re_gmii_readreg(dev, phy, reg); 512 return (rval); 513 } 514 515 /* Pretend the internal PHY is only at address 0 */ 516 if (phy) { 517 return (0); 518 } 519 switch (reg) { 520 case MII_BMCR: 521 re8139_reg = RL_BMCR; 522 break; 523 case MII_BMSR: 524 re8139_reg = RL_BMSR; 525 break; 526 case MII_ANAR: 527 re8139_reg = RL_ANAR; 528 break; 529 case MII_ANER: 530 re8139_reg = RL_ANER; 531 break; 532 case MII_ANLPAR: 533 re8139_reg = RL_LPAR; 534 break; 535 case MII_PHYIDR1: 536 case MII_PHYIDR2: 537 return (0); 538 /* 539 * Allow the rlphy driver to read the media status 540 * register. If we have a link partner which does not 541 * support NWAY, this is the register which will tell 542 * us the results of parallel detection. 543 */ 544 case RL_MEDIASTAT: 545 rval = CSR_READ_1(sc, RL_MEDIASTAT); 546 return (rval); 547 default: 548 device_printf(sc->rl_dev, "bad phy register\n"); 549 return (0); 550 } 551 rval = CSR_READ_2(sc, re8139_reg); 552 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 553 /* 8139C+ has different bit layout. */ 554 rval &= ~(BMCR_LOOP | BMCR_ISO); 555 } 556 return (rval); 557} 558 559static int 560re_miibus_writereg(dev, phy, reg, data) 561 device_t dev; 562 int phy, reg, data; 563{ 564 struct rl_softc *sc; 565 u_int16_t re8139_reg = 0; 566 int rval = 0; 567 568 sc = device_get_softc(dev); 569 570 if (sc->rl_type == RL_8169) { 571 rval = re_gmii_writereg(dev, phy, reg, data); 572 return (rval); 573 } 574 575 /* Pretend the internal PHY is only at address 0 */ 576 if (phy) 577 return (0); 578 579 switch (reg) { 580 case MII_BMCR: 581 re8139_reg = RL_BMCR; 582 if (sc->rl_type == RL_8139CPLUS) { 583 /* 8139C+ has different bit layout. */ 584 data &= ~(BMCR_LOOP | BMCR_ISO); 585 } 586 break; 587 case MII_BMSR: 588 re8139_reg = RL_BMSR; 589 break; 590 case MII_ANAR: 591 re8139_reg = RL_ANAR; 592 break; 593 case MII_ANER: 594 re8139_reg = RL_ANER; 595 break; 596 case MII_ANLPAR: 597 re8139_reg = RL_LPAR; 598 break; 599 case MII_PHYIDR1: 600 case MII_PHYIDR2: 601 return (0); 602 break; 603 default: 604 device_printf(sc->rl_dev, "bad phy register\n"); 605 return (0); 606 } 607 CSR_WRITE_2(sc, re8139_reg, data); 608 return (0); 609} 610 611static void 612re_miibus_statchg(dev) 613 device_t dev; 614{ 615 616} 617 618/* 619 * Program the 64-bit multicast hash filter. 620 */ 621static void 622re_setmulti(sc) 623 struct rl_softc *sc; 624{ 625 struct ifnet *ifp; 626 int h = 0; 627 u_int32_t hashes[2] = { 0, 0 }; 628 struct ifmultiaddr *ifma; 629 u_int32_t rxfilt; 630 int mcnt = 0; 631 u_int32_t hwrev; 632 633 RL_LOCK_ASSERT(sc); 634 635 ifp = sc->rl_ifp; 636 637 638 rxfilt = CSR_READ_4(sc, RL_RXCFG); 639 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 640 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 641 if (ifp->if_flags & IFF_PROMISC) 642 rxfilt |= RL_RXCFG_RX_ALLPHYS; 643 if (ifp->if_flags & IFF_ALLMULTI) 644 rxfilt |= RL_RXCFG_RX_MULTI; 645 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 646 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 647 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 648 return; 649 } 650 651 /* first, zot all the existing hash bits */ 652 CSR_WRITE_4(sc, RL_MAR0, 0); 653 CSR_WRITE_4(sc, RL_MAR4, 0); 654 655 /* now program new ones */ 656 IF_ADDR_LOCK(ifp); 657 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 658 if (ifma->ifma_addr->sa_family != AF_LINK) 659 continue; 660 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 661 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 662 if (h < 32) 663 hashes[0] |= (1 << h); 664 else 665 hashes[1] |= (1 << (h - 32)); 666 mcnt++; 667 } 668 IF_ADDR_UNLOCK(ifp); 669 670 if (mcnt) 671 rxfilt |= RL_RXCFG_RX_MULTI; 672 else 673 rxfilt &= ~RL_RXCFG_RX_MULTI; 674 675 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 676 677 /* 678 * For some unfathomable reason, RealTek decided to reverse 679 * the order of the multicast hash registers in the PCI Express 680 * parts. This means we have to write the hash pattern in reverse 681 * order for those devices. 682 */ 683 684 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 685 686 if (hwrev == RL_HWREV_8100E || hwrev == RL_HWREV_8101E || 687 hwrev == RL_HWREV_8168_SPIN1 || hwrev == RL_HWREV_8168_SPIN2) { 688 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 689 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 690 } else { 691 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 692 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 693 } 694} 695 696static void 697re_reset(sc) 698 struct rl_softc *sc; 699{ 700 register int i; 701 702 RL_LOCK_ASSERT(sc); 703 704 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 705 706 for (i = 0; i < RL_TIMEOUT; i++) { 707 DELAY(10); 708 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 709 break; 710 } 711 if (i == RL_TIMEOUT) 712 device_printf(sc->rl_dev, "reset never completed!\n"); 713 714 CSR_WRITE_1(sc, 0x82, 1); 715} 716 717#ifdef RE_DIAG 718 719/* 720 * The following routine is designed to test for a defect on some 721 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 722 * lines connected to the bus, however for a 32-bit only card, they 723 * should be pulled high. The result of this defect is that the 724 * NIC will not work right if you plug it into a 64-bit slot: DMA 725 * operations will be done with 64-bit transfers, which will fail 726 * because the 64-bit data lines aren't connected. 727 * 728 * There's no way to work around this (short of talking a soldering 729 * iron to the board), however we can detect it. The method we use 730 * here is to put the NIC into digital loopback mode, set the receiver 731 * to promiscuous mode, and then try to send a frame. We then compare 732 * the frame data we sent to what was received. If the data matches, 733 * then the NIC is working correctly, otherwise we know the user has 734 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 735 * slot. In the latter case, there's no way the NIC can work correctly, 736 * so we print out a message on the console and abort the device attach. 737 */ 738 739static int 740re_diag(sc) 741 struct rl_softc *sc; 742{ 743 struct ifnet *ifp = sc->rl_ifp; 744 struct mbuf *m0; 745 struct ether_header *eh; 746 struct rl_desc *cur_rx; 747 u_int16_t status; 748 u_int32_t rxstat; 749 int total_len, i, error = 0, phyaddr; 750 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 751 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 752 753 /* Allocate a single mbuf */ 754 MGETHDR(m0, M_DONTWAIT, MT_DATA); 755 if (m0 == NULL) 756 return (ENOBUFS); 757 758 RL_LOCK(sc); 759 760 /* 761 * Initialize the NIC in test mode. This sets the chip up 762 * so that it can send and receive frames, but performs the 763 * following special functions: 764 * - Puts receiver in promiscuous mode 765 * - Enables digital loopback mode 766 * - Leaves interrupts turned off 767 */ 768 769 ifp->if_flags |= IFF_PROMISC; 770 sc->rl_testmode = 1; 771 re_reset(sc); 772 re_init_locked(sc); 773 sc->rl_link = 1; 774 if (sc->rl_type == RL_8169) 775 phyaddr = 1; 776 else 777 phyaddr = 0; 778 779 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 780 for (i = 0; i < RL_TIMEOUT; i++) { 781 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 782 if (!(status & BMCR_RESET)) 783 break; 784 } 785 786 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 787 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 788 789 DELAY(100000); 790 791 /* Put some data in the mbuf */ 792 793 eh = mtod(m0, struct ether_header *); 794 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 795 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 796 eh->ether_type = htons(ETHERTYPE_IP); 797 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 798 799 /* 800 * Queue the packet, start transmission. 801 * Note: IF_HANDOFF() ultimately calls re_start() for us. 802 */ 803 804 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 805 RL_UNLOCK(sc); 806 /* XXX: re_diag must not be called when in ALTQ mode */ 807 IF_HANDOFF(&ifp->if_snd, m0, ifp); 808 RL_LOCK(sc); 809 m0 = NULL; 810 811 /* Wait for it to propagate through the chip */ 812 813 DELAY(100000); 814 for (i = 0; i < RL_TIMEOUT; i++) { 815 status = CSR_READ_2(sc, RL_ISR); 816 CSR_WRITE_2(sc, RL_ISR, status); 817 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 818 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 819 break; 820 DELAY(10); 821 } 822 823 if (i == RL_TIMEOUT) { 824 device_printf(sc->rl_dev, 825 "diagnostic failed, failed to receive packet in" 826 " loopback mode\n"); 827 error = EIO; 828 goto done; 829 } 830 831 /* 832 * The packet should have been dumped into the first 833 * entry in the RX DMA ring. Grab it from there. 834 */ 835 836 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 837 sc->rl_ldata.rl_rx_list_map, 838 BUS_DMASYNC_POSTREAD); 839 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 840 sc->rl_ldata.rl_rx_dmamap[0], 841 BUS_DMASYNC_POSTWRITE); 842 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 843 sc->rl_ldata.rl_rx_dmamap[0]); 844 845 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 846 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 847 eh = mtod(m0, struct ether_header *); 848 849 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 850 total_len = RL_RXBYTES(cur_rx); 851 rxstat = le32toh(cur_rx->rl_cmdstat); 852 853 if (total_len != ETHER_MIN_LEN) { 854 device_printf(sc->rl_dev, 855 "diagnostic failed, received short packet\n"); 856 error = EIO; 857 goto done; 858 } 859 860 /* Test that the received packet data matches what we sent. */ 861 862 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 863 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 864 ntohs(eh->ether_type) != ETHERTYPE_IP) { 865 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 866 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 867 dst, ":", src, ":", ETHERTYPE_IP); 868 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 869 eh->ether_dhost, ":", eh->ether_shost, ":", 870 ntohs(eh->ether_type)); 871 device_printf(sc->rl_dev, "You may have a defective 32-bit " 872 "NIC plugged into a 64-bit PCI slot.\n"); 873 device_printf(sc->rl_dev, "Please re-install the NIC in a " 874 "32-bit slot for proper operation.\n"); 875 device_printf(sc->rl_dev, "Read the re(4) man page for more " 876 "details.\n"); 877 error = EIO; 878 } 879 880done: 881 /* Turn interface off, release resources */ 882 883 sc->rl_testmode = 0; 884 sc->rl_link = 0; 885 ifp->if_flags &= ~IFF_PROMISC; 886 re_stop(sc); 887 if (m0 != NULL) 888 m_freem(m0); 889 890 RL_UNLOCK(sc); 891 892 return (error); 893} 894 895#endif 896 897/* 898 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 899 * IDs against our list and return a device name if we find a match. 900 */ 901static int 902re_probe(dev) 903 device_t dev; 904{ 905 struct rl_type *t; 906 struct rl_softc *sc; 907 int rid; 908 u_int32_t hwrev; 909 910 t = re_devs; 911 sc = device_get_softc(dev); 912 913 while (t->rl_name != NULL) { 914 if ((pci_get_vendor(dev) == t->rl_vid) && 915 (pci_get_device(dev) == t->rl_did)) { 916 /* 917 * Only attach to rev. 3 of the Linksys EG1032 adapter. 918 * Rev. 2 i supported by sk(4). 919 */ 920 if ((t->rl_vid == LINKSYS_VENDORID) && 921 (t->rl_did == LINKSYS_DEVICEID_EG1032) && 922 (pci_get_subdevice(dev) != 923 LINKSYS_SUBDEVICE_EG1032_REV3)) { 924 t++; 925 continue; 926 } 927 928 /* 929 * Temporarily map the I/O space 930 * so we can read the chip ID register. 931 */ 932 rid = RL_RID; 933 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 934 RF_ACTIVE); 935 if (sc->rl_res == NULL) { 936 device_printf(dev, 937 "couldn't map ports/memory\n"); 938 return (ENXIO); 939 } 940 sc->rl_btag = rman_get_bustag(sc->rl_res); 941 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 942 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 943 bus_release_resource(dev, RL_RES, 944 RL_RID, sc->rl_res); 945 if (t->rl_basetype == hwrev) { 946 device_set_desc(dev, t->rl_name); 947 return (BUS_PROBE_DEFAULT); 948 } 949 } 950 t++; 951 } 952 953 return (ENXIO); 954} 955 956/* 957 * This routine takes the segment list provided as the result of 958 * a bus_dma_map_load() operation and assigns the addresses/lengths 959 * to RealTek DMA descriptors. This can be called either by the RX 960 * code or the TX code. In the RX case, we'll probably wind up mapping 961 * at most one segment. For the TX case, there could be any number of 962 * segments since TX packets may span multiple mbufs. In either case, 963 * if the number of segments is larger than the rl_maxsegs limit 964 * specified by the caller, we abort the mapping operation. Sadly, 965 * whoever designed the buffer mapping API did not provide a way to 966 * return an error from here, so we have to fake it a bit. 967 */ 968 969static void 970re_dma_map_desc(arg, segs, nseg, mapsize, error) 971 void *arg; 972 bus_dma_segment_t *segs; 973 int nseg; 974 bus_size_t mapsize; 975 int error; 976{ 977 struct rl_dmaload_arg *ctx; 978 struct rl_desc *d = NULL; 979 int i = 0, idx; 980 u_int32_t cmdstat; 981 int totlen = 0; 982 983 if (error) 984 return; 985 986 ctx = arg; 987 988 /* Signal error to caller if there's too many segments */ 989 if (nseg > ctx->rl_maxsegs) { 990 ctx->rl_maxsegs = 0; 991 return; 992 } 993 994 /* 995 * Map the segment array into descriptors. Note that we set the 996 * start-of-frame and end-of-frame markers for either TX or RX, but 997 * they really only have meaning in the TX case. (In the RX case, 998 * it's the chip that tells us where packets begin and end.) 999 * We also keep track of the end of the ring and set the 1000 * end-of-ring bits as needed, and we set the ownership bits 1001 * in all except the very first descriptor. (The caller will 1002 * set this descriptor later when it start transmission or 1003 * reception.) 1004 */ 1005 idx = ctx->rl_idx; 1006 for (;;) { 1007 d = &ctx->rl_ring[idx]; 1008 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 1009 ctx->rl_maxsegs = 0; 1010 return; 1011 } 1012 cmdstat = segs[i].ds_len; 1013 totlen += segs[i].ds_len; 1014 d->rl_vlanctl = 0; 1015 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 1016 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 1017 if (i == 0) 1018 cmdstat |= RL_TDESC_CMD_SOF; 1019 else 1020 cmdstat |= RL_TDESC_CMD_OWN; 1021 if (idx == (RL_RX_DESC_CNT - 1)) 1022 cmdstat |= RL_TDESC_CMD_EOR; 1023 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 1024 i++; 1025 if (i == nseg) 1026 break; 1027 RL_DESC_INC(idx); 1028 } 1029 1030 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 1031 ctx->rl_maxsegs = nseg; 1032 ctx->rl_idx = idx; 1033} 1034 1035/* 1036 * Map a single buffer address. 1037 */ 1038 1039static void 1040re_dma_map_addr(arg, segs, nseg, error) 1041 void *arg; 1042 bus_dma_segment_t *segs; 1043 int nseg; 1044 int error; 1045{ 1046 bus_addr_t *addr; 1047 1048 if (error) 1049 return; 1050 1051 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1052 addr = arg; 1053 *addr = segs->ds_addr; 1054} 1055 1056static int 1057re_allocmem(dev, sc) 1058 device_t dev; 1059 struct rl_softc *sc; 1060{ 1061 int error; 1062 int nseg; 1063 int i; 1064 1065 /* 1066 * Allocate map for RX mbufs. 1067 */ 1068 nseg = 32; 1069 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 1070 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1071 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 1072 NULL, NULL, &sc->rl_ldata.rl_mtag); 1073 if (error) { 1074 device_printf(dev, "could not allocate dma tag\n"); 1075 return (ENOMEM); 1076 } 1077 1078 /* 1079 * Allocate map for TX descriptor list. 1080 */ 1081 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1082 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1083 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, 1084 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1085 if (error) { 1086 device_printf(dev, "could not allocate dma tag\n"); 1087 return (ENOMEM); 1088 } 1089 1090 /* Allocate DMA'able memory for the TX ring */ 1091 1092 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1093 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1094 &sc->rl_ldata.rl_tx_list_map); 1095 if (error) 1096 return (ENOMEM); 1097 1098 /* Load the map for the TX ring. */ 1099 1100 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1101 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1102 RL_TX_LIST_SZ, re_dma_map_addr, 1103 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1104 1105 /* Create DMA maps for TX buffers */ 1106 1107 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1108 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1109 &sc->rl_ldata.rl_tx_dmamap[i]); 1110 if (error) { 1111 device_printf(dev, "can't create DMA map for TX\n"); 1112 return (ENOMEM); 1113 } 1114 } 1115 1116 /* 1117 * Allocate map for RX descriptor list. 1118 */ 1119 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1120 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1121 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, 0, 1122 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1123 if (error) { 1124 device_printf(dev, "could not allocate dma tag\n"); 1125 return (ENOMEM); 1126 } 1127 1128 /* Allocate DMA'able memory for the RX ring */ 1129 1130 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1131 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1132 &sc->rl_ldata.rl_rx_list_map); 1133 if (error) 1134 return (ENOMEM); 1135 1136 /* Load the map for the RX ring. */ 1137 1138 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1139 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1140 RL_RX_LIST_SZ, re_dma_map_addr, 1141 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1142 1143 /* Create DMA maps for RX buffers */ 1144 1145 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1146 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1147 &sc->rl_ldata.rl_rx_dmamap[i]); 1148 if (error) { 1149 device_printf(dev, "can't create DMA map for RX\n"); 1150 return (ENOMEM); 1151 } 1152 } 1153 1154 return (0); 1155} 1156 1157/* 1158 * Attach the interface. Allocate softc structures, do ifmedia 1159 * setup and ethernet/BPF attach. 1160 */ 1161static int 1162re_attach(dev) 1163 device_t dev; 1164{ 1165 u_char eaddr[ETHER_ADDR_LEN]; 1166 u_int16_t as[ETHER_ADDR_LEN / 2]; 1167 struct rl_softc *sc; 1168 struct ifnet *ifp; 1169 struct rl_hwrev *hw_rev; 1170 int hwrev; 1171 u_int16_t re_did = 0; 1172 int error = 0, rid, i; 1173 int msic, reg; 1174 1175 sc = device_get_softc(dev); 1176 sc->rl_dev = dev; 1177 1178 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1179 MTX_DEF); 1180 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1181 1182 /* 1183 * Map control/status registers. 1184 */ 1185 pci_enable_busmaster(dev); 1186 1187 rid = RL_RID; 1188 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1189 RF_ACTIVE); 1190 1191 if (sc->rl_res == NULL) { 1192 device_printf(dev, "couldn't map ports/memory\n"); 1193 error = ENXIO; 1194 goto fail; 1195 } 1196 1197 sc->rl_btag = rman_get_bustag(sc->rl_res); 1198 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1199 1200 msic = 0; 1201 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1202 msic = pci_msi_count(dev); 1203 if (bootverbose) 1204 device_printf(dev, "MSI count : %d\n", msic); 1205 } 1206 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1207 if (pci_alloc_msi(dev, &msic) == 0) { 1208 if (msic == RL_MSI_MESSAGES) { 1209 device_printf(dev, "Using %d MSI messages\n", 1210 msic); 1211 sc->rl_msi = 1; 1212 } else 1213 pci_release_msi(dev); 1214 } 1215 } 1216 1217 /* Allocate interrupt */ 1218 if (sc->rl_msi == 0) { 1219 rid = 0; 1220 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1221 RF_SHAREABLE | RF_ACTIVE); 1222 if (sc->rl_irq[0] == NULL) { 1223 device_printf(dev, "couldn't allocate IRQ resources\n"); 1224 error = ENXIO; 1225 goto fail; 1226 } 1227 } else { 1228 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1229 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1230 SYS_RES_IRQ, &rid, RF_ACTIVE); 1231 if (sc->rl_irq[i] == NULL) { 1232 device_printf(dev, 1233 "couldn't llocate IRQ resources for " 1234 "message %d\n", rid); 1235 error = ENXIO; 1236 goto fail; 1237 } 1238 } 1239 } 1240 1241 /* Reset the adapter. */ 1242 RL_LOCK(sc); 1243 re_reset(sc); 1244 RL_UNLOCK(sc); 1245 1246 hw_rev = re_hwrevs; 1247 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1248 while (hw_rev->rl_desc != NULL) { 1249 if (hw_rev->rl_rev == hwrev) { 1250 sc->rl_type = hw_rev->rl_type; 1251 break; 1252 } 1253 hw_rev++; 1254 } 1255 1256 sc->rl_eewidth = RL_9356_ADDR_LEN; 1257 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1258 if (re_did != 0x8129) 1259 sc->rl_eewidth = RL_9346_ADDR_LEN; 1260 1261 /* 1262 * Get station address from the EEPROM. 1263 */ 1264 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1265 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1266 as[i] = le16toh(as[i]); 1267 bcopy(as, eaddr, sizeof(eaddr)); 1268 1269 if (sc->rl_type == RL_8169) { 1270 /* Set RX length mask */ 1271 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1272 sc->rl_txstart = RL_GTXSTART; 1273 } else { 1274 /* Set RX length mask */ 1275 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1276 sc->rl_txstart = RL_TXSTART; 1277 } 1278 1279 /* 1280 * Allocate the parent bus DMA tag appropriate for PCI. 1281 */ 1282#define RL_NSEG_NEW 32 1283 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1284 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1285 MAXBSIZE, RL_NSEG_NEW, BUS_SPACE_MAXSIZE_32BIT, 0, 1286 NULL, NULL, &sc->rl_parent_tag); 1287 if (error) 1288 goto fail; 1289 1290 error = re_allocmem(dev, sc); 1291 1292 if (error) 1293 goto fail; 1294 1295 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1296 if (ifp == NULL) { 1297 device_printf(dev, "can not if_alloc()\n"); 1298 error = ENOSPC; 1299 goto fail; 1300 } 1301 1302 /* Do MII setup */ 1303 if (mii_phy_probe(dev, &sc->rl_miibus, 1304 re_ifmedia_upd, re_ifmedia_sts)) { 1305 device_printf(dev, "MII without any phy!\n"); 1306 error = ENXIO; 1307 goto fail; 1308 } 1309 1310 /* Take PHY out of power down mode. */ 1311 if (sc->rl_type == RL_8169) { 1312 uint32_t rev; 1313 1314 rev = CSR_READ_4(sc, RL_TXCFG); 1315 /* HWVERID 0, 1 and 2 : bit26-30, bit23 */ 1316 rev &= 0x7c800000; 1317 if (rev != 0) { 1318 /* RTL8169S single chip */ 1319 switch (rev) { 1320 case RL_HWREV_8169_8110SB: 1321 case RL_HWREV_8169_8110SC: 1322 case RL_HWREV_8168_SPIN2: 1323 re_gmii_writereg(dev, 1, 0x1f, 0); 1324 re_gmii_writereg(dev, 1, 0x0e, 0); 1325 break; 1326 default: 1327 break; 1328 } 1329 } 1330 } 1331 1332 ifp->if_softc = sc; 1333 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1334 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1335 ifp->if_ioctl = re_ioctl; 1336 ifp->if_start = re_start; 1337 ifp->if_hwassist = RE_CSUM_FEATURES; 1338 ifp->if_capabilities = IFCAP_HWCSUM; 1339 ifp->if_capenable = ifp->if_capabilities; 1340 ifp->if_init = re_init; 1341 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1342 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1343 IFQ_SET_READY(&ifp->if_snd); 1344 1345 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1346 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1347 1348 /* 1349 * Call MI attach routine. 1350 */ 1351 ether_ifattach(ifp, eaddr); 1352 1353 /* VLAN capability setup */ 1354 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1355 if (ifp->if_capabilities & IFCAP_HWCSUM) 1356 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1357 ifp->if_capenable = ifp->if_capabilities; 1358#ifdef DEVICE_POLLING 1359 ifp->if_capabilities |= IFCAP_POLLING; 1360#endif 1361 /* 1362 * Tell the upper layer(s) we support long frames. 1363 * Must appear after the call to ether_ifattach() because 1364 * ether_ifattach() sets ifi_hdrlen to the default value. 1365 */ 1366 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1367 1368#ifdef RE_DIAG 1369 /* 1370 * Perform hardware diagnostic on the original RTL8169. 1371 * Some 32-bit cards were incorrectly wired and would 1372 * malfunction if plugged into a 64-bit slot. 1373 */ 1374 1375 if (hwrev == RL_HWREV_8169) { 1376 error = re_diag(sc); 1377 if (error) { 1378 device_printf(dev, 1379 "attach aborted due to hardware diag failure\n"); 1380 ether_ifdetach(ifp); 1381 goto fail; 1382 } 1383 } 1384#endif 1385 1386 /* Hook interrupt last to avoid having to lock softc */ 1387 if (sc->rl_msi == 0) 1388 error = bus_setup_intr(dev, sc->rl_irq[0], 1389 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1390 &sc->rl_intrhand[0]); 1391 else { 1392 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1393 error = bus_setup_intr(dev, sc->rl_irq[i], 1394 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1395 &sc->rl_intrhand[i]); 1396 if (error != 0) 1397 break; 1398 } 1399 } 1400 if (error) { 1401 device_printf(dev, "couldn't set up irq\n"); 1402 ether_ifdetach(ifp); 1403 } 1404 1405fail: 1406 1407 if (error) 1408 re_detach(dev); 1409 1410 return (error); 1411} 1412 1413/* 1414 * Shutdown hardware and free up resources. This can be called any 1415 * time after the mutex has been initialized. It is called in both 1416 * the error case in attach and the normal detach case so it needs 1417 * to be careful about only freeing resources that have actually been 1418 * allocated. 1419 */ 1420static int 1421re_detach(dev) 1422 device_t dev; 1423{ 1424 struct rl_softc *sc; 1425 struct ifnet *ifp; 1426 int i, rid; 1427 1428 sc = device_get_softc(dev); 1429 ifp = sc->rl_ifp; 1430 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1431 1432#ifdef DEVICE_POLLING 1433 if (ifp->if_capenable & IFCAP_POLLING) 1434 ether_poll_deregister(ifp); 1435#endif 1436 /* These should only be active if attach succeeded */ 1437 if (device_is_attached(dev)) { 1438 RL_LOCK(sc); 1439#if 0 1440 sc->suspended = 1; 1441#endif 1442 re_stop(sc); 1443 RL_UNLOCK(sc); 1444 callout_drain(&sc->rl_stat_callout); 1445 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1446 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1447 /* 1448 * Force off the IFF_UP flag here, in case someone 1449 * still had a BPF descriptor attached to this 1450 * interface. If they do, ether_ifdetach() will cause 1451 * the BPF code to try and clear the promisc mode 1452 * flag, which will bubble down to re_ioctl(), 1453 * which will try to call re_init() again. This will 1454 * turn the NIC back on and restart the MII ticker, 1455 * which will panic the system when the kernel tries 1456 * to invoke the re_tick() function that isn't there 1457 * anymore. 1458 */ 1459 ifp->if_flags &= ~IFF_UP; 1460 ether_ifdetach(ifp); 1461 } 1462 if (sc->rl_miibus) 1463 device_delete_child(dev, sc->rl_miibus); 1464 bus_generic_detach(dev); 1465 1466 /* 1467 * The rest is resource deallocation, so we should already be 1468 * stopped here. 1469 */ 1470 1471 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1472 if (sc->rl_intrhand[i] != NULL) { 1473 bus_teardown_intr(dev, sc->rl_irq[i], 1474 sc->rl_intrhand[i]); 1475 sc->rl_intrhand[i] = NULL; 1476 } 1477 } 1478 if (ifp != NULL) 1479 if_free(ifp); 1480 if (sc->rl_msi == 0) { 1481 if (sc->rl_irq[0] != NULL) { 1482 bus_release_resource(dev, SYS_RES_IRQ, 0, 1483 sc->rl_irq[0]); 1484 sc->rl_irq[0] = NULL; 1485 } 1486 } else { 1487 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1488 if (sc->rl_irq[i] != NULL) { 1489 bus_release_resource(dev, SYS_RES_IRQ, rid, 1490 sc->rl_irq[i]); 1491 sc->rl_irq[i] = NULL; 1492 } 1493 } 1494 pci_release_msi(dev); 1495 } 1496 if (sc->rl_res) 1497 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1498 1499 /* Unload and free the RX DMA ring memory and map */ 1500 1501 if (sc->rl_ldata.rl_rx_list_tag) { 1502 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1503 sc->rl_ldata.rl_rx_list_map); 1504 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1505 sc->rl_ldata.rl_rx_list, 1506 sc->rl_ldata.rl_rx_list_map); 1507 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1508 } 1509 1510 /* Unload and free the TX DMA ring memory and map */ 1511 1512 if (sc->rl_ldata.rl_tx_list_tag) { 1513 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1514 sc->rl_ldata.rl_tx_list_map); 1515 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1516 sc->rl_ldata.rl_tx_list, 1517 sc->rl_ldata.rl_tx_list_map); 1518 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1519 } 1520 1521 /* Destroy all the RX and TX buffer maps */ 1522 1523 if (sc->rl_ldata.rl_mtag) { 1524 for (i = 0; i < RL_TX_DESC_CNT; i++) 1525 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1526 sc->rl_ldata.rl_tx_dmamap[i]); 1527 for (i = 0; i < RL_RX_DESC_CNT; i++) 1528 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1529 sc->rl_ldata.rl_rx_dmamap[i]); 1530 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1531 } 1532 1533 /* Unload and free the stats buffer and map */ 1534 1535 if (sc->rl_ldata.rl_stag) { 1536 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1537 sc->rl_ldata.rl_rx_list_map); 1538 bus_dmamem_free(sc->rl_ldata.rl_stag, 1539 sc->rl_ldata.rl_stats, 1540 sc->rl_ldata.rl_smap); 1541 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1542 } 1543 1544 if (sc->rl_parent_tag) 1545 bus_dma_tag_destroy(sc->rl_parent_tag); 1546 1547 mtx_destroy(&sc->rl_mtx); 1548 1549 return (0); 1550} 1551 1552static int 1553re_newbuf(sc, idx, m) 1554 struct rl_softc *sc; 1555 int idx; 1556 struct mbuf *m; 1557{ 1558 struct rl_dmaload_arg arg; 1559 struct mbuf *n = NULL; 1560 int error; 1561 1562 if (m == NULL) { 1563 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1564 if (n == NULL) 1565 return (ENOBUFS); 1566 m = n; 1567 } else 1568 m->m_data = m->m_ext.ext_buf; 1569 1570 m->m_len = m->m_pkthdr.len = MCLBYTES; 1571#ifdef RE_FIXUP_RX 1572 /* 1573 * This is part of an evil trick to deal with non-x86 platforms. 1574 * The RealTek chip requires RX buffers to be aligned on 64-bit 1575 * boundaries, but that will hose non-x86 machines. To get around 1576 * this, we leave some empty space at the start of each buffer 1577 * and for non-x86 hosts, we copy the buffer back six bytes 1578 * to achieve word alignment. This is slightly more efficient 1579 * than allocating a new buffer, copying the contents, and 1580 * discarding the old buffer. 1581 */ 1582 m_adj(m, RE_ETHER_ALIGN); 1583#endif 1584 arg.rl_idx = idx; 1585 arg.rl_maxsegs = 1; 1586 arg.rl_flags = 0; 1587 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1588 1589 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1590 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1591 &arg, BUS_DMA_NOWAIT); 1592 if (error || arg.rl_maxsegs != 1) { 1593 if (n != NULL) 1594 m_freem(n); 1595 if (arg.rl_maxsegs == 0) 1596 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1597 sc->rl_ldata.rl_rx_dmamap[idx]); 1598 return (ENOMEM); 1599 } 1600 1601 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1602 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1603 1604 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1605 sc->rl_ldata.rl_rx_dmamap[idx], 1606 BUS_DMASYNC_PREREAD); 1607 1608 return (0); 1609} 1610 1611#ifdef RE_FIXUP_RX 1612static __inline void 1613re_fixup_rx(m) 1614 struct mbuf *m; 1615{ 1616 int i; 1617 uint16_t *src, *dst; 1618 1619 src = mtod(m, uint16_t *); 1620 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1621 1622 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1623 *dst++ = *src++; 1624 1625 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1626 1627 return; 1628} 1629#endif 1630 1631static int 1632re_tx_list_init(sc) 1633 struct rl_softc *sc; 1634{ 1635 1636 RL_LOCK_ASSERT(sc); 1637 1638 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1639 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1640 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1641 1642 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1643 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1644 sc->rl_ldata.rl_tx_prodidx = 0; 1645 sc->rl_ldata.rl_tx_considx = 0; 1646 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1647 1648 return (0); 1649} 1650 1651static int 1652re_rx_list_init(sc) 1653 struct rl_softc *sc; 1654{ 1655 int i; 1656 1657 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1658 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1659 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1660 1661 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1662 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1663 return (ENOBUFS); 1664 } 1665 1666 /* Flush the RX descriptors */ 1667 1668 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1669 sc->rl_ldata.rl_rx_list_map, 1670 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1671 1672 sc->rl_ldata.rl_rx_prodidx = 0; 1673 sc->rl_head = sc->rl_tail = NULL; 1674 1675 return (0); 1676} 1677 1678/* 1679 * RX handler for C+ and 8169. For the gigE chips, we support 1680 * the reception of jumbo frames that have been fragmented 1681 * across multiple 2K mbuf cluster buffers. 1682 */ 1683static int 1684re_rxeof(sc) 1685 struct rl_softc *sc; 1686{ 1687 struct mbuf *m; 1688 struct ifnet *ifp; 1689 int i, total_len; 1690 struct rl_desc *cur_rx; 1691 u_int32_t rxstat, rxvlan; 1692 int maxpkt = 16; 1693 1694 RL_LOCK_ASSERT(sc); 1695 1696 ifp = sc->rl_ifp; 1697 i = sc->rl_ldata.rl_rx_prodidx; 1698 1699 /* Invalidate the descriptor memory */ 1700 1701 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1702 sc->rl_ldata.rl_rx_list_map, 1703 BUS_DMASYNC_POSTREAD); 1704 1705 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) { 1706 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1707 m = sc->rl_ldata.rl_rx_mbuf[i]; 1708 total_len = RL_RXBYTES(cur_rx); 1709 rxstat = le32toh(cur_rx->rl_cmdstat); 1710 rxvlan = le32toh(cur_rx->rl_vlanctl); 1711 1712 /* Invalidate the RX mbuf and unload its map */ 1713 1714 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1715 sc->rl_ldata.rl_rx_dmamap[i], 1716 BUS_DMASYNC_POSTWRITE); 1717 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1718 sc->rl_ldata.rl_rx_dmamap[i]); 1719 1720 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1721 m->m_len = RE_RX_DESC_BUFLEN; 1722 if (sc->rl_head == NULL) 1723 sc->rl_head = sc->rl_tail = m; 1724 else { 1725 m->m_flags &= ~M_PKTHDR; 1726 sc->rl_tail->m_next = m; 1727 sc->rl_tail = m; 1728 } 1729 re_newbuf(sc, i, NULL); 1730 RL_DESC_INC(i); 1731 continue; 1732 } 1733 1734 /* 1735 * NOTE: for the 8139C+, the frame length field 1736 * is always 12 bits in size, but for the gigE chips, 1737 * it is 13 bits (since the max RX frame length is 16K). 1738 * Unfortunately, all 32 bits in the status word 1739 * were already used, so to make room for the extra 1740 * length bit, RealTek took out the 'frame alignment 1741 * error' bit and shifted the other status bits 1742 * over one slot. The OWN, EOR, FS and LS bits are 1743 * still in the same places. We have already extracted 1744 * the frame length and checked the OWN bit, so rather 1745 * than using an alternate bit mapping, we shift the 1746 * status bits one space to the right so we can evaluate 1747 * them using the 8169 status as though it was in the 1748 * same format as that of the 8139C+. 1749 */ 1750 if (sc->rl_type == RL_8169) 1751 rxstat >>= 1; 1752 1753 /* 1754 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1755 * set, but if CRC is clear, it will still be a valid frame. 1756 */ 1757 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1758 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1759 ifp->if_ierrors++; 1760 /* 1761 * If this is part of a multi-fragment packet, 1762 * discard all the pieces. 1763 */ 1764 if (sc->rl_head != NULL) { 1765 m_freem(sc->rl_head); 1766 sc->rl_head = sc->rl_tail = NULL; 1767 } 1768 re_newbuf(sc, i, m); 1769 RL_DESC_INC(i); 1770 continue; 1771 } 1772 1773 /* 1774 * If allocating a replacement mbuf fails, 1775 * reload the current one. 1776 */ 1777 1778 if (re_newbuf(sc, i, NULL)) { 1779 ifp->if_ierrors++; 1780 if (sc->rl_head != NULL) { 1781 m_freem(sc->rl_head); 1782 sc->rl_head = sc->rl_tail = NULL; 1783 } 1784 re_newbuf(sc, i, m); 1785 RL_DESC_INC(i); 1786 continue; 1787 } 1788 1789 RL_DESC_INC(i); 1790 1791 if (sc->rl_head != NULL) { 1792 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1793 if (m->m_len == 0) 1794 m->m_len = RE_RX_DESC_BUFLEN; 1795 /* 1796 * Special case: if there's 4 bytes or less 1797 * in this buffer, the mbuf can be discarded: 1798 * the last 4 bytes is the CRC, which we don't 1799 * care about anyway. 1800 */ 1801 if (m->m_len <= ETHER_CRC_LEN) { 1802 sc->rl_tail->m_len -= 1803 (ETHER_CRC_LEN - m->m_len); 1804 m_freem(m); 1805 } else { 1806 m->m_len -= ETHER_CRC_LEN; 1807 m->m_flags &= ~M_PKTHDR; 1808 sc->rl_tail->m_next = m; 1809 } 1810 m = sc->rl_head; 1811 sc->rl_head = sc->rl_tail = NULL; 1812 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1813 } else 1814 m->m_pkthdr.len = m->m_len = 1815 (total_len - ETHER_CRC_LEN); 1816 1817#ifdef RE_FIXUP_RX 1818 re_fixup_rx(m); 1819#endif 1820 ifp->if_ipackets++; 1821 m->m_pkthdr.rcvif = ifp; 1822 1823 /* Do RX checksumming if enabled */ 1824 1825 if (ifp->if_capenable & IFCAP_RXCSUM) { 1826 1827 /* Check IP header checksum */ 1828 if (rxstat & RL_RDESC_STAT_PROTOID) 1829 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1830 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1831 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1832 1833 /* Check TCP/UDP checksum */ 1834 if ((RL_TCPPKT(rxstat) && 1835 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1836 (RL_UDPPKT(rxstat) && 1837 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1838 m->m_pkthdr.csum_flags |= 1839 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1840 m->m_pkthdr.csum_data = 0xffff; 1841 } 1842 } 1843 maxpkt--; 1844 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1845 m->m_pkthdr.ether_vtag = 1846 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1847 m->m_flags |= M_VLANTAG; 1848 } 1849 RL_UNLOCK(sc); 1850 (*ifp->if_input)(ifp, m); 1851 RL_LOCK(sc); 1852 } 1853 1854 /* Flush the RX DMA ring */ 1855 1856 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1857 sc->rl_ldata.rl_rx_list_map, 1858 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1859 1860 sc->rl_ldata.rl_rx_prodidx = i; 1861 1862 if (maxpkt) 1863 return(EAGAIN); 1864 1865 return(0); 1866} 1867 1868static void 1869re_txeof(sc) 1870 struct rl_softc *sc; 1871{ 1872 struct ifnet *ifp; 1873 u_int32_t txstat; 1874 int idx; 1875 1876 ifp = sc->rl_ifp; 1877 idx = sc->rl_ldata.rl_tx_considx; 1878 1879 /* Invalidate the TX descriptor list */ 1880 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1881 sc->rl_ldata.rl_tx_list_map, 1882 BUS_DMASYNC_POSTREAD); 1883 1884 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1885 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1886 if (txstat & RL_TDESC_CMD_OWN) 1887 break; 1888 1889 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0; 1890 1891 /* 1892 * We only stash mbufs in the last descriptor 1893 * in a fragment chain, which also happens to 1894 * be the only place where the TX status bits 1895 * are valid. 1896 */ 1897 if (txstat & RL_TDESC_CMD_EOF) { 1898 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1899 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1900 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1901 sc->rl_ldata.rl_tx_dmamap[idx]); 1902 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1903 RL_TDESC_STAT_COLCNT)) 1904 ifp->if_collisions++; 1905 if (txstat & RL_TDESC_STAT_TXERRSUM) 1906 ifp->if_oerrors++; 1907 else 1908 ifp->if_opackets++; 1909 } 1910 sc->rl_ldata.rl_tx_free++; 1911 RL_DESC_INC(idx); 1912 } 1913 sc->rl_ldata.rl_tx_considx = idx; 1914 1915 /* No changes made to the TX ring, so no flush needed */ 1916 1917 if (sc->rl_ldata.rl_tx_free > RL_TX_DESC_THLD) 1918 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1919 1920 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1921 /* 1922 * Some chips will ignore a second TX request issued 1923 * while an existing transmission is in progress. If 1924 * the transmitter goes idle but there are still 1925 * packets waiting to be sent, we need to restart the 1926 * channel here to flush them out. This only seems to 1927 * be required with the PCIe devices. 1928 */ 1929 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1930 1931#ifdef RE_TX_MODERATION 1932 /* 1933 * If not all descriptors have been reaped yet, reload 1934 * the timer so that we will eventually get another 1935 * interrupt that will cause us to re-enter this routine. 1936 * This is done in case the transmitter has gone idle. 1937 */ 1938 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1939#endif 1940 } else 1941 sc->rl_watchdog_timer = 0; 1942} 1943 1944static void 1945re_tick(xsc) 1946 void *xsc; 1947{ 1948 struct rl_softc *sc; 1949 struct mii_data *mii; 1950 struct ifnet *ifp; 1951 1952 sc = xsc; 1953 ifp = sc->rl_ifp; 1954 1955 RL_LOCK_ASSERT(sc); 1956 1957 re_watchdog(sc); 1958 1959 mii = device_get_softc(sc->rl_miibus); 1960 mii_tick(mii); 1961 if (sc->rl_link) { 1962 if (!(mii->mii_media_status & IFM_ACTIVE)) 1963 sc->rl_link = 0; 1964 } else { 1965 if (mii->mii_media_status & IFM_ACTIVE && 1966 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1967 sc->rl_link = 1; 1968 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1969 taskqueue_enqueue_fast(taskqueue_fast, 1970 &sc->rl_txtask); 1971 } 1972 } 1973 1974 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1975} 1976 1977#ifdef DEVICE_POLLING 1978static void 1979re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1980{ 1981 struct rl_softc *sc = ifp->if_softc; 1982 1983 RL_LOCK(sc); 1984 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1985 re_poll_locked(ifp, cmd, count); 1986 RL_UNLOCK(sc); 1987} 1988 1989static void 1990re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1991{ 1992 struct rl_softc *sc = ifp->if_softc; 1993 1994 RL_LOCK_ASSERT(sc); 1995 1996 sc->rxcycles = count; 1997 re_rxeof(sc); 1998 re_txeof(sc); 1999 2000 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2001 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2002 2003 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2004 u_int16_t status; 2005 2006 status = CSR_READ_2(sc, RL_ISR); 2007 if (status == 0xffff) 2008 return; 2009 if (status) 2010 CSR_WRITE_2(sc, RL_ISR, status); 2011 2012 /* 2013 * XXX check behaviour on receiver stalls. 2014 */ 2015 2016 if (status & RL_ISR_SYSTEM_ERR) { 2017 re_reset(sc); 2018 re_init_locked(sc); 2019 } 2020 } 2021} 2022#endif /* DEVICE_POLLING */ 2023 2024static int 2025re_intr(arg) 2026 void *arg; 2027{ 2028 struct rl_softc *sc; 2029 uint16_t status; 2030 2031 sc = arg; 2032 2033 status = CSR_READ_2(sc, RL_ISR); 2034 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2035 return (FILTER_STRAY); 2036 CSR_WRITE_2(sc, RL_IMR, 0); 2037 2038 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2039 2040 return (FILTER_HANDLED); 2041} 2042 2043static void 2044re_int_task(arg, npending) 2045 void *arg; 2046 int npending; 2047{ 2048 struct rl_softc *sc; 2049 struct ifnet *ifp; 2050 u_int16_t status; 2051 int rval = 0; 2052 2053 sc = arg; 2054 ifp = sc->rl_ifp; 2055 2056 RL_LOCK(sc); 2057 2058 status = CSR_READ_2(sc, RL_ISR); 2059 CSR_WRITE_2(sc, RL_ISR, status); 2060 2061 if (sc->suspended || !(ifp->if_flags & IFF_UP)) { 2062 RL_UNLOCK(sc); 2063 return; 2064 } 2065 2066#ifdef DEVICE_POLLING 2067 if (ifp->if_capenable & IFCAP_POLLING) { 2068 RL_UNLOCK(sc); 2069 return; 2070 } 2071#endif 2072 2073 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2074 rval = re_rxeof(sc); 2075 2076#ifdef RE_TX_MODERATION 2077 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2078#else 2079 if (status & (RL_ISR_TX_OK| 2080#endif 2081 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2082 re_txeof(sc); 2083 2084 if (status & RL_ISR_SYSTEM_ERR) { 2085 re_reset(sc); 2086 re_init_locked(sc); 2087 } 2088 2089 if (status & RL_ISR_LINKCHG) { 2090 callout_stop(&sc->rl_stat_callout); 2091 re_tick(sc); 2092 } 2093 2094 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2095 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2096 2097 RL_UNLOCK(sc); 2098 2099 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2100 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2101 return; 2102 } 2103 2104 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2105 2106 return; 2107} 2108 2109static int 2110re_encap(sc, m_head, idx) 2111 struct rl_softc *sc; 2112 struct mbuf **m_head; 2113 int *idx; 2114{ 2115 struct mbuf *m_new = NULL; 2116 struct rl_dmaload_arg arg; 2117 bus_dmamap_t map; 2118 int error; 2119 2120 RL_LOCK_ASSERT(sc); 2121 2122 if (sc->rl_ldata.rl_tx_free <= RL_TX_DESC_THLD) 2123 return (EFBIG); 2124 2125 /* 2126 * Set up checksum offload. Note: checksum offload bits must 2127 * appear in all descriptors of a multi-descriptor transmit 2128 * attempt. This is according to testing done with an 8169 2129 * chip. This is a requirement. 2130 */ 2131 2132 arg.rl_flags = 0; 2133 2134 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2135 arg.rl_flags = RL_TDESC_CMD_LGSEND | 2136 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2137 RL_TDESC_CMD_MSSVAL_SHIFT); 2138 else { 2139 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2140 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 2141 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2142 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 2143 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2144 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 2145 } 2146 2147 arg.rl_idx = *idx; 2148 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2149 if (arg.rl_maxsegs > RL_TX_DESC_THLD) 2150 arg.rl_maxsegs -= RL_TX_DESC_THLD; 2151 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2152 2153 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 2154 2155 /* 2156 * With some of the RealTek chips, using the checksum offload 2157 * support in conjunction with the autopadding feature results 2158 * in the transmission of corrupt frames. For example, if we 2159 * need to send a really small IP fragment that's less than 60 2160 * bytes in size, and IP header checksumming is enabled, the 2161 * resulting ethernet frame that appears on the wire will 2162 * have garbled payload. To work around this, if TX checksum 2163 * offload is enabled, we always manually pad short frames out 2164 * to the minimum ethernet frame size. We do this by pretending 2165 * the mbuf chain has too many fragments so the coalescing code 2166 * below can assemble the packet into a single buffer that's 2167 * padded out to the mininum frame size. 2168 * 2169 * Note: this appears unnecessary for TCP, and doing it for TCP 2170 * with PCIe adapters seems to result in bad checksums. 2171 */ 2172 2173 if (arg.rl_flags && !(arg.rl_flags & RL_TDESC_CMD_TCPCSUM) && 2174 (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) 2175 error = EFBIG; 2176 else 2177 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2178 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2179 2180 if (error && error != EFBIG) { 2181 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", error); 2182 return (ENOBUFS); 2183 } 2184 2185 /* Too many segments to map, coalesce into a single mbuf */ 2186 2187 if (error || arg.rl_maxsegs == 0) { 2188 if (arg.rl_maxsegs == 0) 2189 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map); 2190 m_new = m_defrag(*m_head, M_DONTWAIT); 2191 if (m_new == NULL) { 2192 m_freem(*m_head); 2193 *m_head = NULL; 2194 return (ENOBUFS); 2195 } 2196 *m_head = m_new; 2197 2198 /* 2199 * Manually pad short frames, and zero the pad space 2200 * to avoid leaking data. 2201 */ 2202 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) { 2203 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 2204 RL_MIN_FRAMELEN - m_new->m_pkthdr.len); 2205 m_new->m_pkthdr.len += RL_MIN_FRAMELEN - 2206 m_new->m_pkthdr.len; 2207 m_new->m_len = m_new->m_pkthdr.len; 2208 } 2209 2210 /* Note that we'll run over RL_TX_DESC_THLD here. */ 2211 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2212 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2213 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2214 if (error || arg.rl_maxsegs == 0) { 2215 device_printf(sc->rl_dev, 2216 "can't map defragmented mbuf (error %d)\n", error); 2217 m_freem(m_new); 2218 *m_head = NULL; 2219 if (arg.rl_maxsegs == 0) 2220 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map); 2221 return (EFBIG); 2222 } 2223 } 2224 2225 /* 2226 * Insure that the map for this transmission 2227 * is placed at the array index of the last descriptor 2228 * in this chain. (Swap last and first dmamaps.) 2229 */ 2230 sc->rl_ldata.rl_tx_dmamap[*idx] = 2231 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 2232 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 2233 2234 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 2235 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 2236 2237 /* 2238 * Set up hardware VLAN tagging. Note: vlan tag info must 2239 * appear in the first descriptor of a multi-descriptor 2240 * transmission attempt. 2241 */ 2242 if ((*m_head)->m_flags & M_VLANTAG) 2243 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 2244 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2245 RL_TDESC_VLANCTL_TAG); 2246 2247 /* Transfer ownership of packet to the chip. */ 2248 2249 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 2250 htole32(RL_TDESC_CMD_OWN); 2251 if (*idx != arg.rl_idx) 2252 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 2253 htole32(RL_TDESC_CMD_OWN); 2254 2255 RL_DESC_INC(arg.rl_idx); 2256 *idx = arg.rl_idx; 2257 2258 return (0); 2259} 2260 2261static void 2262re_tx_task(arg, npending) 2263 void *arg; 2264 int npending; 2265{ 2266 struct ifnet *ifp; 2267 2268 ifp = arg; 2269 re_start(ifp); 2270 2271 return; 2272} 2273 2274/* 2275 * Main transmit routine for C+ and gigE NICs. 2276 */ 2277static void 2278re_start(ifp) 2279 struct ifnet *ifp; 2280{ 2281 struct rl_softc *sc; 2282 struct mbuf *m_head = NULL; 2283 int idx, queued = 0; 2284 2285 sc = ifp->if_softc; 2286 2287 RL_LOCK(sc); 2288 2289 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 2290 RL_UNLOCK(sc); 2291 return; 2292 } 2293 2294 idx = sc->rl_ldata.rl_tx_prodidx; 2295 2296 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2297 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2298 if (m_head == NULL) 2299 break; 2300 2301 if (re_encap(sc, &m_head, &idx)) { 2302 if (m_head == NULL) 2303 break; 2304 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2305 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2306 break; 2307 } 2308 2309 /* 2310 * If there's a BPF listener, bounce a copy of this frame 2311 * to him. 2312 */ 2313 ETHER_BPF_MTAP(ifp, m_head); 2314 2315 queued++; 2316 } 2317 2318 if (queued == 0) { 2319#ifdef RE_TX_MODERATION 2320 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 2321 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2322#endif 2323 RL_UNLOCK(sc); 2324 return; 2325 } 2326 2327 /* Flush the TX descriptors */ 2328 2329 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2330 sc->rl_ldata.rl_tx_list_map, 2331 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2332 2333 sc->rl_ldata.rl_tx_prodidx = idx; 2334 2335 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2336 2337#ifdef RE_TX_MODERATION 2338 /* 2339 * Use the countdown timer for interrupt moderation. 2340 * 'TX done' interrupts are disabled. Instead, we reset the 2341 * countdown timer, which will begin counting until it hits 2342 * the value in the TIMERINT register, and then trigger an 2343 * interrupt. Each time we write to the TIMERCNT register, 2344 * the timer count is reset to 0. 2345 */ 2346 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2347#endif 2348 2349 /* 2350 * Set a timeout in case the chip goes out to lunch. 2351 */ 2352 sc->rl_watchdog_timer = 5; 2353 2354 RL_UNLOCK(sc); 2355 2356 return; 2357} 2358 2359static void 2360re_init(xsc) 2361 void *xsc; 2362{ 2363 struct rl_softc *sc = xsc; 2364 2365 RL_LOCK(sc); 2366 re_init_locked(sc); 2367 RL_UNLOCK(sc); 2368} 2369 2370static void 2371re_init_locked(sc) 2372 struct rl_softc *sc; 2373{ 2374 struct ifnet *ifp = sc->rl_ifp; 2375 struct mii_data *mii; 2376 u_int32_t rxcfg = 0; 2377 union { 2378 uint32_t align_dummy; 2379 u_char eaddr[ETHER_ADDR_LEN]; 2380 } eaddr; 2381 2382 RL_LOCK_ASSERT(sc); 2383 2384 mii = device_get_softc(sc->rl_miibus); 2385 2386 /* 2387 * Cancel pending I/O and free all RX/TX buffers. 2388 */ 2389 re_stop(sc); 2390 2391 /* 2392 * Enable C+ RX and TX mode, as well as VLAN stripping and 2393 * RX checksum offload. We must configure the C+ register 2394 * before all others. 2395 */ 2396 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2397 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2398 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB); 2399 2400 /* 2401 * Init our MAC address. Even though the chipset 2402 * documentation doesn't mention it, we need to enter "Config 2403 * register write enable" mode to modify the ID registers. 2404 */ 2405 /* Copy MAC address on stack to align. */ 2406 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2407 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2408 CSR_WRITE_4(sc, RL_IDR0, 2409 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2410 CSR_WRITE_4(sc, RL_IDR4, 2411 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2412 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2413 2414 /* 2415 * For C+ mode, initialize the RX descriptors and mbufs. 2416 */ 2417 re_rx_list_init(sc); 2418 re_tx_list_init(sc); 2419 2420 /* 2421 * Load the addresses of the RX and TX lists into the chip. 2422 */ 2423 2424 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2425 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2426 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2427 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2428 2429 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2430 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2431 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2432 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2433 2434 /* 2435 * Enable transmit and receive. 2436 */ 2437 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2438 2439 /* 2440 * Set the initial TX and RX configuration. 2441 */ 2442 if (sc->rl_testmode) { 2443 if (sc->rl_type == RL_8169) 2444 CSR_WRITE_4(sc, RL_TXCFG, 2445 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2446 else 2447 CSR_WRITE_4(sc, RL_TXCFG, 2448 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2449 } else 2450 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2451 2452 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2453 2454 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2455 2456 /* Set the individual bit to receive frames for this host only. */ 2457 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2458 rxcfg |= RL_RXCFG_RX_INDIV; 2459 2460 /* If we want promiscuous mode, set the allframes bit. */ 2461 if (ifp->if_flags & IFF_PROMISC) 2462 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2463 else 2464 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2465 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2466 2467 /* 2468 * Set capture broadcast bit to capture broadcast frames. 2469 */ 2470 if (ifp->if_flags & IFF_BROADCAST) 2471 rxcfg |= RL_RXCFG_RX_BROAD; 2472 else 2473 rxcfg &= ~RL_RXCFG_RX_BROAD; 2474 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2475 2476 /* 2477 * Program the multicast filter, if necessary. 2478 */ 2479 re_setmulti(sc); 2480 2481#ifdef DEVICE_POLLING 2482 /* 2483 * Disable interrupts if we are polling. 2484 */ 2485 if (ifp->if_capenable & IFCAP_POLLING) 2486 CSR_WRITE_2(sc, RL_IMR, 0); 2487 else /* otherwise ... */ 2488#endif 2489 2490 /* 2491 * Enable interrupts. 2492 */ 2493 if (sc->rl_testmode) 2494 CSR_WRITE_2(sc, RL_IMR, 0); 2495 else 2496 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2497 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2498 2499 /* Set initial TX threshold */ 2500 sc->rl_txthresh = RL_TX_THRESH_INIT; 2501 2502 /* Start RX/TX process. */ 2503 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2504#ifdef notdef 2505 /* Enable receiver and transmitter. */ 2506 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2507#endif 2508 2509#ifdef RE_TX_MODERATION 2510 /* 2511 * Initialize the timer interrupt register so that 2512 * a timer interrupt will be generated once the timer 2513 * reaches a certain number of ticks. The timer is 2514 * reloaded on each transmit. This gives us TX interrupt 2515 * moderation, which dramatically improves TX frame rate. 2516 */ 2517 if (sc->rl_type == RL_8169) 2518 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2519 else 2520 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2521#endif 2522 2523 /* 2524 * For 8169 gigE NICs, set the max allowed RX packet 2525 * size so we can receive jumbo frames. 2526 */ 2527 if (sc->rl_type == RL_8169) 2528 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2529 2530 if (sc->rl_testmode) 2531 return; 2532 2533 mii_mediachg(mii); 2534 2535 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2536 2537 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2538 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2539 2540 sc->rl_link = 0; 2541 sc->rl_watchdog_timer = 0; 2542 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2543} 2544 2545/* 2546 * Set media options. 2547 */ 2548static int 2549re_ifmedia_upd(ifp) 2550 struct ifnet *ifp; 2551{ 2552 struct rl_softc *sc; 2553 struct mii_data *mii; 2554 2555 sc = ifp->if_softc; 2556 mii = device_get_softc(sc->rl_miibus); 2557 RL_LOCK(sc); 2558 mii_mediachg(mii); 2559 RL_UNLOCK(sc); 2560 2561 return (0); 2562} 2563 2564/* 2565 * Report current media status. 2566 */ 2567static void 2568re_ifmedia_sts(ifp, ifmr) 2569 struct ifnet *ifp; 2570 struct ifmediareq *ifmr; 2571{ 2572 struct rl_softc *sc; 2573 struct mii_data *mii; 2574 2575 sc = ifp->if_softc; 2576 mii = device_get_softc(sc->rl_miibus); 2577 2578 RL_LOCK(sc); 2579 mii_pollstat(mii); 2580 RL_UNLOCK(sc); 2581 ifmr->ifm_active = mii->mii_media_active; 2582 ifmr->ifm_status = mii->mii_media_status; 2583} 2584 2585static int 2586re_ioctl(ifp, command, data) 2587 struct ifnet *ifp; 2588 u_long command; 2589 caddr_t data; 2590{ 2591 struct rl_softc *sc = ifp->if_softc; 2592 struct ifreq *ifr = (struct ifreq *) data; 2593 struct mii_data *mii; 2594 int error = 0; 2595 2596 switch (command) { 2597 case SIOCSIFMTU: 2598 RL_LOCK(sc); 2599 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2600 error = EINVAL; 2601 ifp->if_mtu = ifr->ifr_mtu; 2602 RL_UNLOCK(sc); 2603 break; 2604 case SIOCSIFFLAGS: 2605 RL_LOCK(sc); 2606 if ((ifp->if_flags & IFF_UP) != 0) { 2607 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2608 if (((ifp->if_flags ^ sc->rl_if_flags) 2609 & IFF_PROMISC) != 0) 2610 re_setmulti(sc); 2611 } else 2612 re_init_locked(sc); 2613 } else { 2614 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2615 re_stop(sc); 2616 } 2617 sc->rl_if_flags = ifp->if_flags; 2618 RL_UNLOCK(sc); 2619 break; 2620 case SIOCADDMULTI: 2621 case SIOCDELMULTI: 2622 RL_LOCK(sc); 2623 re_setmulti(sc); 2624 RL_UNLOCK(sc); 2625 break; 2626 case SIOCGIFMEDIA: 2627 case SIOCSIFMEDIA: 2628 mii = device_get_softc(sc->rl_miibus); 2629 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2630 break; 2631 case SIOCSIFCAP: 2632 { 2633 int mask, reinit; 2634 2635 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2636 reinit = 0; 2637#ifdef DEVICE_POLLING 2638 if (mask & IFCAP_POLLING) { 2639 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2640 error = ether_poll_register(re_poll, ifp); 2641 if (error) 2642 return(error); 2643 RL_LOCK(sc); 2644 /* Disable interrupts */ 2645 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2646 ifp->if_capenable |= IFCAP_POLLING; 2647 RL_UNLOCK(sc); 2648 } else { 2649 error = ether_poll_deregister(ifp); 2650 /* Enable interrupts. */ 2651 RL_LOCK(sc); 2652 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2653 ifp->if_capenable &= ~IFCAP_POLLING; 2654 RL_UNLOCK(sc); 2655 } 2656 } 2657#endif /* DEVICE_POLLING */ 2658 if (mask & IFCAP_HWCSUM) { 2659 ifp->if_capenable ^= IFCAP_HWCSUM; 2660 if (ifp->if_capenable & IFCAP_TXCSUM) 2661 ifp->if_hwassist |= RE_CSUM_FEATURES; 2662 else 2663 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2664 reinit = 1; 2665 } 2666 if (mask & IFCAP_VLAN_HWTAGGING) { 2667 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2668 reinit = 1; 2669 } 2670 if (mask & IFCAP_TSO4) { 2671 ifp->if_capenable ^= IFCAP_TSO4; 2672 if ((IFCAP_TSO4 & ifp->if_capenable) && 2673 (IFCAP_TSO4 & ifp->if_capabilities)) 2674 ifp->if_hwassist |= CSUM_TSO; 2675 else 2676 ifp->if_hwassist &= ~CSUM_TSO; 2677 } 2678 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2679 re_init(sc); 2680 VLAN_CAPABILITIES(ifp); 2681 } 2682 break; 2683 default: 2684 error = ether_ioctl(ifp, command, data); 2685 break; 2686 } 2687 2688 return (error); 2689} 2690 2691static void 2692re_watchdog(sc) 2693 struct rl_softc *sc; 2694{ 2695 2696 RL_LOCK_ASSERT(sc); 2697 2698 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2699 return; 2700 2701 device_printf(sc->rl_dev, "watchdog timeout\n"); 2702 sc->rl_ifp->if_oerrors++; 2703 2704 re_txeof(sc); 2705 re_rxeof(sc); 2706 re_init_locked(sc); 2707} 2708 2709/* 2710 * Stop the adapter and free any mbufs allocated to the 2711 * RX and TX lists. 2712 */ 2713static void 2714re_stop(sc) 2715 struct rl_softc *sc; 2716{ 2717 register int i; 2718 struct ifnet *ifp; 2719 2720 RL_LOCK_ASSERT(sc); 2721 2722 ifp = sc->rl_ifp; 2723 2724 sc->rl_watchdog_timer = 0; 2725 callout_stop(&sc->rl_stat_callout); 2726 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2727 2728 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2729 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2730 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2731 2732 if (sc->rl_head != NULL) { 2733 m_freem(sc->rl_head); 2734 sc->rl_head = sc->rl_tail = NULL; 2735 } 2736 2737 /* Free the TX list buffers. */ 2738 2739 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2740 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2741 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2742 sc->rl_ldata.rl_tx_dmamap[i]); 2743 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2744 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2745 } 2746 } 2747 2748 /* Free the RX list buffers. */ 2749 2750 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2751 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2752 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2753 sc->rl_ldata.rl_rx_dmamap[i]); 2754 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2755 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2756 } 2757 } 2758} 2759 2760/* 2761 * Device suspend routine. Stop the interface and save some PCI 2762 * settings in case the BIOS doesn't restore them properly on 2763 * resume. 2764 */ 2765static int 2766re_suspend(dev) 2767 device_t dev; 2768{ 2769 struct rl_softc *sc; 2770 2771 sc = device_get_softc(dev); 2772 2773 RL_LOCK(sc); 2774 re_stop(sc); 2775 sc->suspended = 1; 2776 RL_UNLOCK(sc); 2777 2778 return (0); 2779} 2780 2781/* 2782 * Device resume routine. Restore some PCI settings in case the BIOS 2783 * doesn't, re-enable busmastering, and restart the interface if 2784 * appropriate. 2785 */ 2786static int 2787re_resume(dev) 2788 device_t dev; 2789{ 2790 struct rl_softc *sc; 2791 struct ifnet *ifp; 2792 2793 sc = device_get_softc(dev); 2794 2795 RL_LOCK(sc); 2796 2797 ifp = sc->rl_ifp; 2798 2799 /* reinitialize interface if necessary */ 2800 if (ifp->if_flags & IFF_UP) 2801 re_init_locked(sc); 2802 2803 sc->suspended = 0; 2804 RL_UNLOCK(sc); 2805 2806 return (0); 2807} 2808 2809/* 2810 * Stop all chip I/O so that the kernel's probe routines don't 2811 * get confused by errant DMAs when rebooting. 2812 */ 2813static int 2814re_shutdown(dev) 2815 device_t dev; 2816{ 2817 struct rl_softc *sc; 2818 2819 sc = device_get_softc(dev); 2820 2821 RL_LOCK(sc); 2822 re_stop(sc); 2823 /* 2824 * Mark interface as down since otherwise we will panic if 2825 * interrupt comes in later on, which can happen in some 2826 * cases. 2827 */ 2828 sc->rl_ifp->if_flags &= ~IFF_UP; 2829 RL_UNLOCK(sc); 2830 2831 return (0); 2832} 2833