if_re.c revision 171604
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 171604 2007-07-27 00:43:12Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149MODULE_DEPEND(re, pci, 1, 1, 1); 150MODULE_DEPEND(re, ether, 1, 1, 1); 151MODULE_DEPEND(re, miibus, 1, 1, 1); 152 153/* "device miibus" required. See GENERIC if you get errors here. */ 154#include "miibus_if.h" 155 156/* 157 * Default to using PIO access for this driver. 158 */ 159#define RE_USEIOSPACE 160 161#include <pci/if_rlreg.h> 162 163/* Tunables. */ 164static int msi_disable = 0; 165TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166 167#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 168 169/* 170 * Various supported device vendors/types and their names. 171 */ 172static struct rl_type re_devs[] = { 173 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 174 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 175 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 176 "RealTek 8139C+ 10/100BaseTX" }, 177 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 178 "RealTek 8101E PCIe 10/100baseTX" }, 179 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 180 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 182 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 184 "RealTek 8169 Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 186 "RealTek 8169S Single-chip Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 188 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC, 190 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 191 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 192 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 194 "RealTek 8110S Single-chip Gigabit Ethernet" }, 195 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 196 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 197 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 198 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 199 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 200 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }, 201 { 0, 0, 0, NULL } 202}; 203 204static struct rl_hwrev re_hwrevs[] = { 205 { RL_HWREV_8139, RL_8139, "" }, 206 { RL_HWREV_8139A, RL_8139, "A" }, 207 { RL_HWREV_8139AG, RL_8139, "A-G" }, 208 { RL_HWREV_8139B, RL_8139, "B" }, 209 { RL_HWREV_8130, RL_8139, "8130" }, 210 { RL_HWREV_8139C, RL_8139, "C" }, 211 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 212 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 213 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 214 { RL_HWREV_8169, RL_8169, "8169"}, 215 { RL_HWREV_8169S, RL_8169, "8169S"}, 216 { RL_HWREV_8110S, RL_8169, "8110S"}, 217 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 218 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 219 { RL_HWREV_8100, RL_8139, "8100"}, 220 { RL_HWREV_8101, RL_8139, "8101"}, 221 { RL_HWREV_8100E, RL_8169, "8100E"}, 222 { RL_HWREV_8101E, RL_8169, "8101E"}, 223 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 224 { 0, 0, NULL } 225}; 226 227static int re_probe (device_t); 228static int re_attach (device_t); 229static int re_detach (device_t); 230 231static int re_encap (struct rl_softc *, struct mbuf **, int *); 232 233static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 234static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 235 bus_size_t, int); 236static int re_allocmem (device_t, struct rl_softc *); 237static int re_newbuf (struct rl_softc *, int, struct mbuf *); 238static int re_rx_list_init (struct rl_softc *); 239static int re_tx_list_init (struct rl_softc *); 240#ifdef RE_FIXUP_RX 241static __inline void re_fixup_rx 242 (struct mbuf *); 243#endif 244static int re_rxeof (struct rl_softc *); 245static void re_txeof (struct rl_softc *); 246#ifdef DEVICE_POLLING 247static void re_poll (struct ifnet *, enum poll_cmd, int); 248static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 249#endif 250static int re_intr (void *); 251static void re_tick (void *); 252static void re_tx_task (void *, int); 253static void re_int_task (void *, int); 254static void re_start (struct ifnet *); 255static int re_ioctl (struct ifnet *, u_long, caddr_t); 256static void re_init (void *); 257static void re_init_locked (struct rl_softc *); 258static void re_stop (struct rl_softc *); 259static void re_watchdog (struct rl_softc *); 260static int re_suspend (device_t); 261static int re_resume (device_t); 262static void re_shutdown (device_t); 263static int re_ifmedia_upd (struct ifnet *); 264static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 265 266static void re_eeprom_putbyte (struct rl_softc *, int); 267static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 268static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 269static int re_gmii_readreg (device_t, int, int); 270static int re_gmii_writereg (device_t, int, int, int); 271 272static int re_miibus_readreg (device_t, int, int); 273static int re_miibus_writereg (device_t, int, int, int); 274static void re_miibus_statchg (device_t); 275 276static void re_setmulti (struct rl_softc *); 277static void re_reset (struct rl_softc *); 278 279#ifdef RE_DIAG 280static int re_diag (struct rl_softc *); 281#endif 282 283#ifdef RE_USEIOSPACE 284#define RL_RES SYS_RES_IOPORT 285#define RL_RID RL_PCI_LOIO 286#else 287#define RL_RES SYS_RES_MEMORY 288#define RL_RID RL_PCI_LOMEM 289#endif 290 291static device_method_t re_methods[] = { 292 /* Device interface */ 293 DEVMETHOD(device_probe, re_probe), 294 DEVMETHOD(device_attach, re_attach), 295 DEVMETHOD(device_detach, re_detach), 296 DEVMETHOD(device_suspend, re_suspend), 297 DEVMETHOD(device_resume, re_resume), 298 DEVMETHOD(device_shutdown, re_shutdown), 299 300 /* bus interface */ 301 DEVMETHOD(bus_print_child, bus_generic_print_child), 302 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 303 304 /* MII interface */ 305 DEVMETHOD(miibus_readreg, re_miibus_readreg), 306 DEVMETHOD(miibus_writereg, re_miibus_writereg), 307 DEVMETHOD(miibus_statchg, re_miibus_statchg), 308 309 { 0, 0 } 310}; 311 312static driver_t re_driver = { 313 "re", 314 re_methods, 315 sizeof(struct rl_softc) 316}; 317 318static devclass_t re_devclass; 319 320DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 321DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 322DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 323 324#define EE_SET(x) \ 325 CSR_WRITE_1(sc, RL_EECMD, \ 326 CSR_READ_1(sc, RL_EECMD) | x) 327 328#define EE_CLR(x) \ 329 CSR_WRITE_1(sc, RL_EECMD, \ 330 CSR_READ_1(sc, RL_EECMD) & ~x) 331 332/* 333 * Send a read command and address to the EEPROM, check for ACK. 334 */ 335static void 336re_eeprom_putbyte(sc, addr) 337 struct rl_softc *sc; 338 int addr; 339{ 340 register int d, i; 341 342 d = addr | (RL_9346_READ << sc->rl_eewidth); 343 344 /* 345 * Feed in each bit and strobe the clock. 346 */ 347 348 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 349 if (d & i) { 350 EE_SET(RL_EE_DATAIN); 351 } else { 352 EE_CLR(RL_EE_DATAIN); 353 } 354 DELAY(100); 355 EE_SET(RL_EE_CLK); 356 DELAY(150); 357 EE_CLR(RL_EE_CLK); 358 DELAY(100); 359 } 360 361 return; 362} 363 364/* 365 * Read a word of data stored in the EEPROM at address 'addr.' 366 */ 367static void 368re_eeprom_getword(sc, addr, dest) 369 struct rl_softc *sc; 370 int addr; 371 u_int16_t *dest; 372{ 373 register int i; 374 u_int16_t word = 0; 375 376 /* 377 * Send address of word we want to read. 378 */ 379 re_eeprom_putbyte(sc, addr); 380 381 /* 382 * Start reading bits from EEPROM. 383 */ 384 for (i = 0x8000; i; i >>= 1) { 385 EE_SET(RL_EE_CLK); 386 DELAY(100); 387 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 388 word |= i; 389 EE_CLR(RL_EE_CLK); 390 DELAY(100); 391 } 392 393 *dest = word; 394 395 return; 396} 397 398/* 399 * Read a sequence of words from the EEPROM. 400 */ 401static void 402re_read_eeprom(sc, dest, off, cnt) 403 struct rl_softc *sc; 404 caddr_t dest; 405 int off; 406 int cnt; 407{ 408 int i; 409 u_int16_t word = 0, *ptr; 410 411 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 412 413 DELAY(100); 414 415 for (i = 0; i < cnt; i++) { 416 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 417 re_eeprom_getword(sc, off + i, &word); 418 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 419 ptr = (u_int16_t *)(dest + (i * 2)); 420 *ptr = word; 421 } 422 423 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 424 425 return; 426} 427 428static int 429re_gmii_readreg(dev, phy, reg) 430 device_t dev; 431 int phy, reg; 432{ 433 struct rl_softc *sc; 434 u_int32_t rval; 435 int i; 436 437 if (phy != 1) 438 return (0); 439 440 sc = device_get_softc(dev); 441 442 /* Let the rgephy driver read the GMEDIASTAT register */ 443 444 if (reg == RL_GMEDIASTAT) { 445 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 446 return (rval); 447 } 448 449 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 450 DELAY(1000); 451 452 for (i = 0; i < RL_TIMEOUT; i++) { 453 rval = CSR_READ_4(sc, RL_PHYAR); 454 if (rval & RL_PHYAR_BUSY) 455 break; 456 DELAY(100); 457 } 458 459 if (i == RL_TIMEOUT) { 460 device_printf(sc->rl_dev, "PHY read failed\n"); 461 return (0); 462 } 463 464 return (rval & RL_PHYAR_PHYDATA); 465} 466 467static int 468re_gmii_writereg(dev, phy, reg, data) 469 device_t dev; 470 int phy, reg, data; 471{ 472 struct rl_softc *sc; 473 u_int32_t rval; 474 int i; 475 476 sc = device_get_softc(dev); 477 478 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 479 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 480 DELAY(1000); 481 482 for (i = 0; i < RL_TIMEOUT; i++) { 483 rval = CSR_READ_4(sc, RL_PHYAR); 484 if (!(rval & RL_PHYAR_BUSY)) 485 break; 486 DELAY(100); 487 } 488 489 if (i == RL_TIMEOUT) { 490 device_printf(sc->rl_dev, "PHY write failed\n"); 491 return (0); 492 } 493 494 return (0); 495} 496 497static int 498re_miibus_readreg(dev, phy, reg) 499 device_t dev; 500 int phy, reg; 501{ 502 struct rl_softc *sc; 503 u_int16_t rval = 0; 504 u_int16_t re8139_reg = 0; 505 506 sc = device_get_softc(dev); 507 508 if (sc->rl_type == RL_8169) { 509 rval = re_gmii_readreg(dev, phy, reg); 510 return (rval); 511 } 512 513 /* Pretend the internal PHY is only at address 0 */ 514 if (phy) { 515 return (0); 516 } 517 switch (reg) { 518 case MII_BMCR: 519 re8139_reg = RL_BMCR; 520 break; 521 case MII_BMSR: 522 re8139_reg = RL_BMSR; 523 break; 524 case MII_ANAR: 525 re8139_reg = RL_ANAR; 526 break; 527 case MII_ANER: 528 re8139_reg = RL_ANER; 529 break; 530 case MII_ANLPAR: 531 re8139_reg = RL_LPAR; 532 break; 533 case MII_PHYIDR1: 534 case MII_PHYIDR2: 535 return (0); 536 /* 537 * Allow the rlphy driver to read the media status 538 * register. If we have a link partner which does not 539 * support NWAY, this is the register which will tell 540 * us the results of parallel detection. 541 */ 542 case RL_MEDIASTAT: 543 rval = CSR_READ_1(sc, RL_MEDIASTAT); 544 return (rval); 545 default: 546 device_printf(sc->rl_dev, "bad phy register\n"); 547 return (0); 548 } 549 rval = CSR_READ_2(sc, re8139_reg); 550 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 551 /* 8139C+ has different bit layout. */ 552 rval &= ~(BMCR_LOOP | BMCR_ISO); 553 } 554 return (rval); 555} 556 557static int 558re_miibus_writereg(dev, phy, reg, data) 559 device_t dev; 560 int phy, reg, data; 561{ 562 struct rl_softc *sc; 563 u_int16_t re8139_reg = 0; 564 int rval = 0; 565 566 sc = device_get_softc(dev); 567 568 if (sc->rl_type == RL_8169) { 569 rval = re_gmii_writereg(dev, phy, reg, data); 570 return (rval); 571 } 572 573 /* Pretend the internal PHY is only at address 0 */ 574 if (phy) 575 return (0); 576 577 switch (reg) { 578 case MII_BMCR: 579 re8139_reg = RL_BMCR; 580 if (sc->rl_type == RL_8139CPLUS) { 581 /* 8139C+ has different bit layout. */ 582 data &= ~(BMCR_LOOP | BMCR_ISO); 583 } 584 break; 585 case MII_BMSR: 586 re8139_reg = RL_BMSR; 587 break; 588 case MII_ANAR: 589 re8139_reg = RL_ANAR; 590 break; 591 case MII_ANER: 592 re8139_reg = RL_ANER; 593 break; 594 case MII_ANLPAR: 595 re8139_reg = RL_LPAR; 596 break; 597 case MII_PHYIDR1: 598 case MII_PHYIDR2: 599 return (0); 600 break; 601 default: 602 device_printf(sc->rl_dev, "bad phy register\n"); 603 return (0); 604 } 605 CSR_WRITE_2(sc, re8139_reg, data); 606 return (0); 607} 608 609static void 610re_miibus_statchg(dev) 611 device_t dev; 612{ 613 614} 615 616/* 617 * Program the 64-bit multicast hash filter. 618 */ 619static void 620re_setmulti(sc) 621 struct rl_softc *sc; 622{ 623 struct ifnet *ifp; 624 int h = 0; 625 u_int32_t hashes[2] = { 0, 0 }; 626 struct ifmultiaddr *ifma; 627 u_int32_t rxfilt; 628 int mcnt = 0; 629 u_int32_t hwrev; 630 631 RL_LOCK_ASSERT(sc); 632 633 ifp = sc->rl_ifp; 634 635 rxfilt = CSR_READ_4(sc, RL_RXCFG); 636 637 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 638 rxfilt |= RL_RXCFG_RX_MULTI; 639 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 640 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 641 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 642 return; 643 } 644 645 /* first, zot all the existing hash bits */ 646 CSR_WRITE_4(sc, RL_MAR0, 0); 647 CSR_WRITE_4(sc, RL_MAR4, 0); 648 649 /* now program new ones */ 650 IF_ADDR_LOCK(ifp); 651 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 652 if (ifma->ifma_addr->sa_family != AF_LINK) 653 continue; 654 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 655 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 656 if (h < 32) 657 hashes[0] |= (1 << h); 658 else 659 hashes[1] |= (1 << (h - 32)); 660 mcnt++; 661 } 662 IF_ADDR_UNLOCK(ifp); 663 664 if (mcnt) 665 rxfilt |= RL_RXCFG_RX_MULTI; 666 else 667 rxfilt &= ~RL_RXCFG_RX_MULTI; 668 669 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 670 671 /* 672 * For some unfathomable reason, RealTek decided to reverse 673 * the order of the multicast hash registers in the PCI Express 674 * parts. This means we have to write the hash pattern in reverse 675 * order for those devices. 676 */ 677 678 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 679 680 if (hwrev == RL_HWREV_8100E || hwrev == RL_HWREV_8101E || 681 hwrev == RL_HWREV_8168_SPIN1 || hwrev == RL_HWREV_8168_SPIN2) { 682 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 683 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 684 } else { 685 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 686 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 687 } 688} 689 690static void 691re_reset(sc) 692 struct rl_softc *sc; 693{ 694 register int i; 695 696 RL_LOCK_ASSERT(sc); 697 698 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 699 700 for (i = 0; i < RL_TIMEOUT; i++) { 701 DELAY(10); 702 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 703 break; 704 } 705 if (i == RL_TIMEOUT) 706 device_printf(sc->rl_dev, "reset never completed!\n"); 707 708 CSR_WRITE_1(sc, 0x82, 1); 709} 710 711#ifdef RE_DIAG 712 713/* 714 * The following routine is designed to test for a defect on some 715 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 716 * lines connected to the bus, however for a 32-bit only card, they 717 * should be pulled high. The result of this defect is that the 718 * NIC will not work right if you plug it into a 64-bit slot: DMA 719 * operations will be done with 64-bit transfers, which will fail 720 * because the 64-bit data lines aren't connected. 721 * 722 * There's no way to work around this (short of talking a soldering 723 * iron to the board), however we can detect it. The method we use 724 * here is to put the NIC into digital loopback mode, set the receiver 725 * to promiscuous mode, and then try to send a frame. We then compare 726 * the frame data we sent to what was received. If the data matches, 727 * then the NIC is working correctly, otherwise we know the user has 728 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 729 * slot. In the latter case, there's no way the NIC can work correctly, 730 * so we print out a message on the console and abort the device attach. 731 */ 732 733static int 734re_diag(sc) 735 struct rl_softc *sc; 736{ 737 struct ifnet *ifp = sc->rl_ifp; 738 struct mbuf *m0; 739 struct ether_header *eh; 740 struct rl_desc *cur_rx; 741 u_int16_t status; 742 u_int32_t rxstat; 743 int total_len, i, error = 0, phyaddr; 744 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 745 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 746 747 /* Allocate a single mbuf */ 748 MGETHDR(m0, M_DONTWAIT, MT_DATA); 749 if (m0 == NULL) 750 return (ENOBUFS); 751 752 RL_LOCK(sc); 753 754 /* 755 * Initialize the NIC in test mode. This sets the chip up 756 * so that it can send and receive frames, but performs the 757 * following special functions: 758 * - Puts receiver in promiscuous mode 759 * - Enables digital loopback mode 760 * - Leaves interrupts turned off 761 */ 762 763 ifp->if_flags |= IFF_PROMISC; 764 sc->rl_testmode = 1; 765 re_reset(sc); 766 re_init_locked(sc); 767 sc->rl_link = 1; 768 if (sc->rl_type == RL_8169) 769 phyaddr = 1; 770 else 771 phyaddr = 0; 772 773 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 774 for (i = 0; i < RL_TIMEOUT; i++) { 775 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 776 if (!(status & BMCR_RESET)) 777 break; 778 } 779 780 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 781 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 782 783 DELAY(100000); 784 785 /* Put some data in the mbuf */ 786 787 eh = mtod(m0, struct ether_header *); 788 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 789 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 790 eh->ether_type = htons(ETHERTYPE_IP); 791 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 792 793 /* 794 * Queue the packet, start transmission. 795 * Note: IF_HANDOFF() ultimately calls re_start() for us. 796 */ 797 798 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 799 RL_UNLOCK(sc); 800 /* XXX: re_diag must not be called when in ALTQ mode */ 801 IF_HANDOFF(&ifp->if_snd, m0, ifp); 802 RL_LOCK(sc); 803 m0 = NULL; 804 805 /* Wait for it to propagate through the chip */ 806 807 DELAY(100000); 808 for (i = 0; i < RL_TIMEOUT; i++) { 809 status = CSR_READ_2(sc, RL_ISR); 810 CSR_WRITE_2(sc, RL_ISR, status); 811 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 812 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 813 break; 814 DELAY(10); 815 } 816 817 if (i == RL_TIMEOUT) { 818 device_printf(sc->rl_dev, 819 "diagnostic failed, failed to receive packet in" 820 " loopback mode\n"); 821 error = EIO; 822 goto done; 823 } 824 825 /* 826 * The packet should have been dumped into the first 827 * entry in the RX DMA ring. Grab it from there. 828 */ 829 830 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 831 sc->rl_ldata.rl_rx_list_map, 832 BUS_DMASYNC_POSTREAD); 833 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 834 sc->rl_ldata.rl_rx_dmamap[0], 835 BUS_DMASYNC_POSTWRITE); 836 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 837 sc->rl_ldata.rl_rx_dmamap[0]); 838 839 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 840 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 841 eh = mtod(m0, struct ether_header *); 842 843 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 844 total_len = RL_RXBYTES(cur_rx); 845 rxstat = le32toh(cur_rx->rl_cmdstat); 846 847 if (total_len != ETHER_MIN_LEN) { 848 device_printf(sc->rl_dev, 849 "diagnostic failed, received short packet\n"); 850 error = EIO; 851 goto done; 852 } 853 854 /* Test that the received packet data matches what we sent. */ 855 856 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 857 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 858 ntohs(eh->ether_type) != ETHERTYPE_IP) { 859 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 860 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 861 dst, ":", src, ":", ETHERTYPE_IP); 862 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 863 eh->ether_dhost, ":", eh->ether_shost, ":", 864 ntohs(eh->ether_type)); 865 device_printf(sc->rl_dev, "You may have a defective 32-bit " 866 "NIC plugged into a 64-bit PCI slot.\n"); 867 device_printf(sc->rl_dev, "Please re-install the NIC in a " 868 "32-bit slot for proper operation.\n"); 869 device_printf(sc->rl_dev, "Read the re(4) man page for more " 870 "details.\n"); 871 error = EIO; 872 } 873 874done: 875 /* Turn interface off, release resources */ 876 877 sc->rl_testmode = 0; 878 sc->rl_link = 0; 879 ifp->if_flags &= ~IFF_PROMISC; 880 re_stop(sc); 881 if (m0 != NULL) 882 m_freem(m0); 883 884 RL_UNLOCK(sc); 885 886 return (error); 887} 888 889#endif 890 891/* 892 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 893 * IDs against our list and return a device name if we find a match. 894 */ 895static int 896re_probe(dev) 897 device_t dev; 898{ 899 struct rl_type *t; 900 struct rl_softc *sc; 901 int rid; 902 u_int32_t hwrev; 903 904 t = re_devs; 905 sc = device_get_softc(dev); 906 907 while (t->rl_name != NULL) { 908 if ((pci_get_vendor(dev) == t->rl_vid) && 909 (pci_get_device(dev) == t->rl_did)) { 910 /* 911 * Only attach to rev. 3 of the Linksys EG1032 adapter. 912 * Rev. 2 i supported by sk(4). 913 */ 914 if ((t->rl_vid == LINKSYS_VENDORID) && 915 (t->rl_did == LINKSYS_DEVICEID_EG1032) && 916 (pci_get_subdevice(dev) != 917 LINKSYS_SUBDEVICE_EG1032_REV3)) { 918 t++; 919 continue; 920 } 921 922 /* 923 * Temporarily map the I/O space 924 * so we can read the chip ID register. 925 */ 926 rid = RL_RID; 927 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 928 RF_ACTIVE); 929 if (sc->rl_res == NULL) { 930 device_printf(dev, 931 "couldn't map ports/memory\n"); 932 return (ENXIO); 933 } 934 sc->rl_btag = rman_get_bustag(sc->rl_res); 935 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 936 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 937 bus_release_resource(dev, RL_RES, 938 RL_RID, sc->rl_res); 939 if (t->rl_basetype == hwrev) { 940 device_set_desc(dev, t->rl_name); 941 return (BUS_PROBE_DEFAULT); 942 } 943 } 944 t++; 945 } 946 947 return (ENXIO); 948} 949 950/* 951 * This routine takes the segment list provided as the result of 952 * a bus_dma_map_load() operation and assigns the addresses/lengths 953 * to RealTek DMA descriptors. This can be called either by the RX 954 * code or the TX code. In the RX case, we'll probably wind up mapping 955 * at most one segment. For the TX case, there could be any number of 956 * segments since TX packets may span multiple mbufs. In either case, 957 * if the number of segments is larger than the rl_maxsegs limit 958 * specified by the caller, we abort the mapping operation. Sadly, 959 * whoever designed the buffer mapping API did not provide a way to 960 * return an error from here, so we have to fake it a bit. 961 */ 962 963static void 964re_dma_map_desc(arg, segs, nseg, mapsize, error) 965 void *arg; 966 bus_dma_segment_t *segs; 967 int nseg; 968 bus_size_t mapsize; 969 int error; 970{ 971 struct rl_dmaload_arg *ctx; 972 struct rl_desc *d = NULL; 973 int i = 0, idx; 974 u_int32_t cmdstat; 975 int totlen = 0; 976 977 if (error) 978 return; 979 980 ctx = arg; 981 982 /* Signal error to caller if there's too many segments */ 983 if (nseg > ctx->rl_maxsegs) { 984 ctx->rl_maxsegs = 0; 985 return; 986 } 987 988 /* 989 * Map the segment array into descriptors. Note that we set the 990 * start-of-frame and end-of-frame markers for either TX or RX, but 991 * they really only have meaning in the TX case. (In the RX case, 992 * it's the chip that tells us where packets begin and end.) 993 * We also keep track of the end of the ring and set the 994 * end-of-ring bits as needed, and we set the ownership bits 995 * in all except the very first descriptor. (The caller will 996 * set this descriptor later when it start transmission or 997 * reception.) 998 */ 999 idx = ctx->rl_idx; 1000 for (;;) { 1001 d = &ctx->rl_ring[idx]; 1002 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 1003 ctx->rl_maxsegs = 0; 1004 return; 1005 } 1006 cmdstat = segs[i].ds_len; 1007 totlen += segs[i].ds_len; 1008 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 1009 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 1010 if (i == 0) 1011 cmdstat |= RL_TDESC_CMD_SOF; 1012 else 1013 cmdstat |= RL_TDESC_CMD_OWN; 1014 if (idx == (RL_RX_DESC_CNT - 1)) 1015 cmdstat |= RL_TDESC_CMD_EOR; 1016 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 1017 i++; 1018 if (i == nseg) 1019 break; 1020 RL_DESC_INC(idx); 1021 } 1022 1023 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 1024 ctx->rl_maxsegs = nseg; 1025 ctx->rl_idx = idx; 1026} 1027 1028/* 1029 * Map a single buffer address. 1030 */ 1031 1032static void 1033re_dma_map_addr(arg, segs, nseg, error) 1034 void *arg; 1035 bus_dma_segment_t *segs; 1036 int nseg; 1037 int error; 1038{ 1039 bus_addr_t *addr; 1040 1041 if (error) 1042 return; 1043 1044 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1045 addr = arg; 1046 *addr = segs->ds_addr; 1047} 1048 1049static int 1050re_allocmem(dev, sc) 1051 device_t dev; 1052 struct rl_softc *sc; 1053{ 1054 int error; 1055 int nseg; 1056 int i; 1057 1058 /* 1059 * Allocate map for RX mbufs. 1060 */ 1061 nseg = 32; 1062 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 1063 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1064 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 1065 NULL, NULL, &sc->rl_ldata.rl_mtag); 1066 if (error) { 1067 device_printf(dev, "could not allocate dma tag\n"); 1068 return (ENOMEM); 1069 } 1070 1071 /* 1072 * Allocate map for TX descriptor list. 1073 */ 1074 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1075 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1076 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, 1077 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1078 if (error) { 1079 device_printf(dev, "could not allocate dma tag\n"); 1080 return (ENOMEM); 1081 } 1082 1083 /* Allocate DMA'able memory for the TX ring */ 1084 1085 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1086 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1087 &sc->rl_ldata.rl_tx_list_map); 1088 if (error) 1089 return (ENOMEM); 1090 1091 /* Load the map for the TX ring. */ 1092 1093 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1094 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1095 RL_TX_LIST_SZ, re_dma_map_addr, 1096 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1097 1098 /* Create DMA maps for TX buffers */ 1099 1100 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1101 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1102 &sc->rl_ldata.rl_tx_dmamap[i]); 1103 if (error) { 1104 device_printf(dev, "can't create DMA map for TX\n"); 1105 return (ENOMEM); 1106 } 1107 } 1108 1109 /* 1110 * Allocate map for RX descriptor list. 1111 */ 1112 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1113 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1114 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, 0, 1115 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1116 if (error) { 1117 device_printf(dev, "could not allocate dma tag\n"); 1118 return (ENOMEM); 1119 } 1120 1121 /* Allocate DMA'able memory for the RX ring */ 1122 1123 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1124 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1125 &sc->rl_ldata.rl_rx_list_map); 1126 if (error) 1127 return (ENOMEM); 1128 1129 /* Load the map for the RX ring. */ 1130 1131 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1132 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1133 RL_RX_LIST_SZ, re_dma_map_addr, 1134 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1135 1136 /* Create DMA maps for RX buffers */ 1137 1138 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1139 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1140 &sc->rl_ldata.rl_rx_dmamap[i]); 1141 if (error) { 1142 device_printf(dev, "can't create DMA map for RX\n"); 1143 return (ENOMEM); 1144 } 1145 } 1146 1147 return (0); 1148} 1149 1150/* 1151 * Attach the interface. Allocate softc structures, do ifmedia 1152 * setup and ethernet/BPF attach. 1153 */ 1154static int 1155re_attach(dev) 1156 device_t dev; 1157{ 1158 u_char eaddr[ETHER_ADDR_LEN]; 1159 u_int16_t as[ETHER_ADDR_LEN / 2]; 1160 struct rl_softc *sc; 1161 struct ifnet *ifp; 1162 struct rl_hwrev *hw_rev; 1163 int hwrev; 1164 u_int16_t re_did = 0; 1165 int error = 0, rid, i; 1166 int msic, reg; 1167 1168 sc = device_get_softc(dev); 1169 sc->rl_dev = dev; 1170 1171 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1172 MTX_DEF); 1173 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1174 1175 /* 1176 * Map control/status registers. 1177 */ 1178 pci_enable_busmaster(dev); 1179 1180 rid = RL_RID; 1181 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1182 RF_ACTIVE); 1183 1184 if (sc->rl_res == NULL) { 1185 device_printf(dev, "couldn't map ports/memory\n"); 1186 error = ENXIO; 1187 goto fail; 1188 } 1189 1190 sc->rl_btag = rman_get_bustag(sc->rl_res); 1191 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1192 1193 msic = 0; 1194 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1195 msic = pci_msi_count(dev); 1196 if (bootverbose) 1197 device_printf(dev, "MSI count : %d\n", msic); 1198 } 1199 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1200 if (pci_alloc_msi(dev, &msic) == 0) { 1201 if (msic == RL_MSI_MESSAGES) { 1202 device_printf(dev, "Using %d MSI messages\n", 1203 msic); 1204 sc->rl_msi = 1; 1205 } else 1206 pci_release_msi(dev); 1207 } 1208 } 1209 1210 /* Allocate interrupt */ 1211 if (sc->rl_msi == 0) { 1212 rid = 0; 1213 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1214 RF_SHAREABLE | RF_ACTIVE); 1215 if (sc->rl_irq[0] == NULL) { 1216 device_printf(dev, "couldn't allocate IRQ resources\n"); 1217 error = ENXIO; 1218 goto fail; 1219 } 1220 } else { 1221 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1222 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1223 SYS_RES_IRQ, &rid, RF_ACTIVE); 1224 if (sc->rl_irq[i] == NULL) { 1225 device_printf(dev, 1226 "couldn't llocate IRQ resources for " 1227 "message %d\n", rid); 1228 error = ENXIO; 1229 goto fail; 1230 } 1231 } 1232 } 1233 1234 /* Reset the adapter. */ 1235 RL_LOCK(sc); 1236 re_reset(sc); 1237 RL_UNLOCK(sc); 1238 1239 hw_rev = re_hwrevs; 1240 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1241 while (hw_rev->rl_desc != NULL) { 1242 if (hw_rev->rl_rev == hwrev) { 1243 sc->rl_type = hw_rev->rl_type; 1244 break; 1245 } 1246 hw_rev++; 1247 } 1248 1249 sc->rl_eewidth = RL_9356_ADDR_LEN; 1250 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1251 if (re_did != 0x8129) 1252 sc->rl_eewidth = RL_9346_ADDR_LEN; 1253 1254 /* 1255 * Get station address from the EEPROM. 1256 */ 1257 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1258 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1259 as[i] = le16toh(as[i]); 1260 bcopy(as, eaddr, sizeof(eaddr)); 1261 1262 if (sc->rl_type == RL_8169) { 1263 /* Set RX length mask */ 1264 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1265 sc->rl_txstart = RL_GTXSTART; 1266 } else { 1267 /* Set RX length mask */ 1268 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1269 sc->rl_txstart = RL_TXSTART; 1270 } 1271 1272 /* 1273 * Allocate the parent bus DMA tag appropriate for PCI. 1274 */ 1275#define RL_NSEG_NEW 32 1276 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1277 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1278 MAXBSIZE, RL_NSEG_NEW, BUS_SPACE_MAXSIZE_32BIT, 0, 1279 NULL, NULL, &sc->rl_parent_tag); 1280 if (error) 1281 goto fail; 1282 1283 error = re_allocmem(dev, sc); 1284 1285 if (error) 1286 goto fail; 1287 1288 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1289 if (ifp == NULL) { 1290 device_printf(dev, "can not if_alloc()\n"); 1291 error = ENOSPC; 1292 goto fail; 1293 } 1294 1295 /* Do MII setup */ 1296 if (mii_phy_probe(dev, &sc->rl_miibus, 1297 re_ifmedia_upd, re_ifmedia_sts)) { 1298 device_printf(dev, "MII without any phy!\n"); 1299 error = ENXIO; 1300 goto fail; 1301 } 1302 1303 ifp->if_softc = sc; 1304 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1305 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1306 ifp->if_ioctl = re_ioctl; 1307 ifp->if_start = re_start; 1308 ifp->if_hwassist = RE_CSUM_FEATURES; 1309 ifp->if_capabilities = IFCAP_HWCSUM; 1310 ifp->if_capenable = ifp->if_capabilities; 1311 ifp->if_init = re_init; 1312 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1313 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1314 IFQ_SET_READY(&ifp->if_snd); 1315 1316 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1317 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1318 1319 /* 1320 * Call MI attach routine. 1321 */ 1322 ether_ifattach(ifp, eaddr); 1323 1324 /* VLAN capability setup */ 1325 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1326 if (ifp->if_capabilities & IFCAP_HWCSUM) 1327 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1328 ifp->if_capenable = ifp->if_capabilities; 1329#ifdef DEVICE_POLLING 1330 ifp->if_capabilities |= IFCAP_POLLING; 1331#endif 1332 /* 1333 * Tell the upper layer(s) we support long frames. 1334 * Must appear after the call to ether_ifattach() because 1335 * ether_ifattach() sets ifi_hdrlen to the default value. 1336 */ 1337 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1338 1339#ifdef RE_DIAG 1340 /* 1341 * Perform hardware diagnostic on the original RTL8169. 1342 * Some 32-bit cards were incorrectly wired and would 1343 * malfunction if plugged into a 64-bit slot. 1344 */ 1345 1346 if (hwrev == RL_HWREV_8169) { 1347 error = re_diag(sc); 1348 if (error) { 1349 device_printf(dev, 1350 "attach aborted due to hardware diag failure\n"); 1351 ether_ifdetach(ifp); 1352 goto fail; 1353 } 1354 } 1355#endif 1356 1357 /* Hook interrupt last to avoid having to lock softc */ 1358 if (sc->rl_msi == 0) 1359 error = bus_setup_intr(dev, sc->rl_irq[0], 1360 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1361 &sc->rl_intrhand[0]); 1362 else { 1363 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1364 error = bus_setup_intr(dev, sc->rl_irq[i], 1365 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1366 &sc->rl_intrhand[i]); 1367 if (error != 0) 1368 break; 1369 } 1370 } 1371 if (error) { 1372 device_printf(dev, "couldn't set up irq\n"); 1373 ether_ifdetach(ifp); 1374 } 1375 1376fail: 1377 1378 if (error) 1379 re_detach(dev); 1380 1381 return (error); 1382} 1383 1384/* 1385 * Shutdown hardware and free up resources. This can be called any 1386 * time after the mutex has been initialized. It is called in both 1387 * the error case in attach and the normal detach case so it needs 1388 * to be careful about only freeing resources that have actually been 1389 * allocated. 1390 */ 1391static int 1392re_detach(dev) 1393 device_t dev; 1394{ 1395 struct rl_softc *sc; 1396 struct ifnet *ifp; 1397 int i, rid; 1398 1399 sc = device_get_softc(dev); 1400 ifp = sc->rl_ifp; 1401 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1402 1403#ifdef DEVICE_POLLING 1404 if (ifp->if_capenable & IFCAP_POLLING) 1405 ether_poll_deregister(ifp); 1406#endif 1407 /* These should only be active if attach succeeded */ 1408 if (device_is_attached(dev)) { 1409 RL_LOCK(sc); 1410#if 0 1411 sc->suspended = 1; 1412#endif 1413 re_stop(sc); 1414 RL_UNLOCK(sc); 1415 callout_drain(&sc->rl_stat_callout); 1416 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1417 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1418 /* 1419 * Force off the IFF_UP flag here, in case someone 1420 * still had a BPF descriptor attached to this 1421 * interface. If they do, ether_ifdetach() will cause 1422 * the BPF code to try and clear the promisc mode 1423 * flag, which will bubble down to re_ioctl(), 1424 * which will try to call re_init() again. This will 1425 * turn the NIC back on and restart the MII ticker, 1426 * which will panic the system when the kernel tries 1427 * to invoke the re_tick() function that isn't there 1428 * anymore. 1429 */ 1430 ifp->if_flags &= ~IFF_UP; 1431 ether_ifdetach(ifp); 1432 } 1433 if (sc->rl_miibus) 1434 device_delete_child(dev, sc->rl_miibus); 1435 bus_generic_detach(dev); 1436 1437 /* 1438 * The rest is resource deallocation, so we should already be 1439 * stopped here. 1440 */ 1441 1442 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1443 if (sc->rl_intrhand[i] != NULL) { 1444 bus_teardown_intr(dev, sc->rl_irq[i], 1445 sc->rl_intrhand[i]); 1446 sc->rl_intrhand[i] = NULL; 1447 } 1448 } 1449 if (ifp != NULL) 1450 if_free(ifp); 1451 if (sc->rl_msi == 0) { 1452 if (sc->rl_irq[0] != NULL) { 1453 bus_release_resource(dev, SYS_RES_IRQ, 0, 1454 sc->rl_irq[0]); 1455 sc->rl_irq[0] = NULL; 1456 } 1457 } else { 1458 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1459 if (sc->rl_irq[i] != NULL) { 1460 bus_release_resource(dev, SYS_RES_IRQ, rid, 1461 sc->rl_irq[i]); 1462 sc->rl_irq[i] = NULL; 1463 } 1464 } 1465 pci_release_msi(dev); 1466 } 1467 if (sc->rl_res) 1468 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1469 1470 /* Unload and free the RX DMA ring memory and map */ 1471 1472 if (sc->rl_ldata.rl_rx_list_tag) { 1473 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1474 sc->rl_ldata.rl_rx_list_map); 1475 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1476 sc->rl_ldata.rl_rx_list, 1477 sc->rl_ldata.rl_rx_list_map); 1478 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1479 } 1480 1481 /* Unload and free the TX DMA ring memory and map */ 1482 1483 if (sc->rl_ldata.rl_tx_list_tag) { 1484 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1485 sc->rl_ldata.rl_tx_list_map); 1486 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1487 sc->rl_ldata.rl_tx_list, 1488 sc->rl_ldata.rl_tx_list_map); 1489 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1490 } 1491 1492 /* Destroy all the RX and TX buffer maps */ 1493 1494 if (sc->rl_ldata.rl_mtag) { 1495 for (i = 0; i < RL_TX_DESC_CNT; i++) 1496 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1497 sc->rl_ldata.rl_tx_dmamap[i]); 1498 for (i = 0; i < RL_RX_DESC_CNT; i++) 1499 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1500 sc->rl_ldata.rl_rx_dmamap[i]); 1501 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1502 } 1503 1504 /* Unload and free the stats buffer and map */ 1505 1506 if (sc->rl_ldata.rl_stag) { 1507 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1508 sc->rl_ldata.rl_rx_list_map); 1509 bus_dmamem_free(sc->rl_ldata.rl_stag, 1510 sc->rl_ldata.rl_stats, 1511 sc->rl_ldata.rl_smap); 1512 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1513 } 1514 1515 if (sc->rl_parent_tag) 1516 bus_dma_tag_destroy(sc->rl_parent_tag); 1517 1518 mtx_destroy(&sc->rl_mtx); 1519 1520 return (0); 1521} 1522 1523static int 1524re_newbuf(sc, idx, m) 1525 struct rl_softc *sc; 1526 int idx; 1527 struct mbuf *m; 1528{ 1529 struct rl_dmaload_arg arg; 1530 struct mbuf *n = NULL; 1531 int error; 1532 1533 if (m == NULL) { 1534 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1535 if (n == NULL) 1536 return (ENOBUFS); 1537 m = n; 1538 } else 1539 m->m_data = m->m_ext.ext_buf; 1540 1541 m->m_len = m->m_pkthdr.len = MCLBYTES; 1542#ifdef RE_FIXUP_RX 1543 /* 1544 * This is part of an evil trick to deal with non-x86 platforms. 1545 * The RealTek chip requires RX buffers to be aligned on 64-bit 1546 * boundaries, but that will hose non-x86 machines. To get around 1547 * this, we leave some empty space at the start of each buffer 1548 * and for non-x86 hosts, we copy the buffer back six bytes 1549 * to achieve word alignment. This is slightly more efficient 1550 * than allocating a new buffer, copying the contents, and 1551 * discarding the old buffer. 1552 */ 1553 m_adj(m, RE_ETHER_ALIGN); 1554#endif 1555 arg.rl_idx = idx; 1556 arg.rl_maxsegs = 1; 1557 arg.rl_flags = 0; 1558 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1559 1560 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1561 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1562 &arg, BUS_DMA_NOWAIT); 1563 if (error || arg.rl_maxsegs != 1) { 1564 if (n != NULL) 1565 m_freem(n); 1566 if (arg.rl_maxsegs == 0) 1567 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1568 sc->rl_ldata.rl_rx_dmamap[idx]); 1569 return (ENOMEM); 1570 } 1571 1572 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1573 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1574 1575 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1576 sc->rl_ldata.rl_rx_dmamap[idx], 1577 BUS_DMASYNC_PREREAD); 1578 1579 return (0); 1580} 1581 1582#ifdef RE_FIXUP_RX 1583static __inline void 1584re_fixup_rx(m) 1585 struct mbuf *m; 1586{ 1587 int i; 1588 uint16_t *src, *dst; 1589 1590 src = mtod(m, uint16_t *); 1591 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1592 1593 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1594 *dst++ = *src++; 1595 1596 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1597 1598 return; 1599} 1600#endif 1601 1602static int 1603re_tx_list_init(sc) 1604 struct rl_softc *sc; 1605{ 1606 1607 RL_LOCK_ASSERT(sc); 1608 1609 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1610 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1611 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1612 1613 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1614 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1615 sc->rl_ldata.rl_tx_prodidx = 0; 1616 sc->rl_ldata.rl_tx_considx = 0; 1617 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1618 1619 return (0); 1620} 1621 1622static int 1623re_rx_list_init(sc) 1624 struct rl_softc *sc; 1625{ 1626 int i; 1627 1628 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1629 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1630 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1631 1632 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1633 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1634 return (ENOBUFS); 1635 } 1636 1637 /* Flush the RX descriptors */ 1638 1639 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1640 sc->rl_ldata.rl_rx_list_map, 1641 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1642 1643 sc->rl_ldata.rl_rx_prodidx = 0; 1644 sc->rl_head = sc->rl_tail = NULL; 1645 1646 return (0); 1647} 1648 1649/* 1650 * RX handler for C+ and 8169. For the gigE chips, we support 1651 * the reception of jumbo frames that have been fragmented 1652 * across multiple 2K mbuf cluster buffers. 1653 */ 1654static int 1655re_rxeof(sc) 1656 struct rl_softc *sc; 1657{ 1658 struct mbuf *m; 1659 struct ifnet *ifp; 1660 int i, total_len; 1661 struct rl_desc *cur_rx; 1662 u_int32_t rxstat, rxvlan; 1663 int maxpkt = 16; 1664 1665 RL_LOCK_ASSERT(sc); 1666 1667 ifp = sc->rl_ifp; 1668 i = sc->rl_ldata.rl_rx_prodidx; 1669 1670 /* Invalidate the descriptor memory */ 1671 1672 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1673 sc->rl_ldata.rl_rx_list_map, 1674 BUS_DMASYNC_POSTREAD); 1675 1676 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) { 1677 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1678 m = sc->rl_ldata.rl_rx_mbuf[i]; 1679 total_len = RL_RXBYTES(cur_rx); 1680 rxstat = le32toh(cur_rx->rl_cmdstat); 1681 rxvlan = le32toh(cur_rx->rl_vlanctl); 1682 1683 /* Invalidate the RX mbuf and unload its map */ 1684 1685 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1686 sc->rl_ldata.rl_rx_dmamap[i], 1687 BUS_DMASYNC_POSTWRITE); 1688 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1689 sc->rl_ldata.rl_rx_dmamap[i]); 1690 1691 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1692 m->m_len = RE_RX_DESC_BUFLEN; 1693 if (sc->rl_head == NULL) 1694 sc->rl_head = sc->rl_tail = m; 1695 else { 1696 m->m_flags &= ~M_PKTHDR; 1697 sc->rl_tail->m_next = m; 1698 sc->rl_tail = m; 1699 } 1700 re_newbuf(sc, i, NULL); 1701 RL_DESC_INC(i); 1702 continue; 1703 } 1704 1705 /* 1706 * NOTE: for the 8139C+, the frame length field 1707 * is always 12 bits in size, but for the gigE chips, 1708 * it is 13 bits (since the max RX frame length is 16K). 1709 * Unfortunately, all 32 bits in the status word 1710 * were already used, so to make room for the extra 1711 * length bit, RealTek took out the 'frame alignment 1712 * error' bit and shifted the other status bits 1713 * over one slot. The OWN, EOR, FS and LS bits are 1714 * still in the same places. We have already extracted 1715 * the frame length and checked the OWN bit, so rather 1716 * than using an alternate bit mapping, we shift the 1717 * status bits one space to the right so we can evaluate 1718 * them using the 8169 status as though it was in the 1719 * same format as that of the 8139C+. 1720 */ 1721 if (sc->rl_type == RL_8169) 1722 rxstat >>= 1; 1723 1724 /* 1725 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1726 * set, but if CRC is clear, it will still be a valid frame. 1727 */ 1728 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1729 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1730 ifp->if_ierrors++; 1731 /* 1732 * If this is part of a multi-fragment packet, 1733 * discard all the pieces. 1734 */ 1735 if (sc->rl_head != NULL) { 1736 m_freem(sc->rl_head); 1737 sc->rl_head = sc->rl_tail = NULL; 1738 } 1739 re_newbuf(sc, i, m); 1740 RL_DESC_INC(i); 1741 continue; 1742 } 1743 1744 /* 1745 * If allocating a replacement mbuf fails, 1746 * reload the current one. 1747 */ 1748 1749 if (re_newbuf(sc, i, NULL)) { 1750 ifp->if_ierrors++; 1751 if (sc->rl_head != NULL) { 1752 m_freem(sc->rl_head); 1753 sc->rl_head = sc->rl_tail = NULL; 1754 } 1755 re_newbuf(sc, i, m); 1756 RL_DESC_INC(i); 1757 continue; 1758 } 1759 1760 RL_DESC_INC(i); 1761 1762 if (sc->rl_head != NULL) { 1763 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1764 if (m->m_len == 0) 1765 m->m_len = RE_RX_DESC_BUFLEN; 1766 /* 1767 * Special case: if there's 4 bytes or less 1768 * in this buffer, the mbuf can be discarded: 1769 * the last 4 bytes is the CRC, which we don't 1770 * care about anyway. 1771 */ 1772 if (m->m_len <= ETHER_CRC_LEN) { 1773 sc->rl_tail->m_len -= 1774 (ETHER_CRC_LEN - m->m_len); 1775 m_freem(m); 1776 } else { 1777 m->m_len -= ETHER_CRC_LEN; 1778 m->m_flags &= ~M_PKTHDR; 1779 sc->rl_tail->m_next = m; 1780 } 1781 m = sc->rl_head; 1782 sc->rl_head = sc->rl_tail = NULL; 1783 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1784 } else 1785 m->m_pkthdr.len = m->m_len = 1786 (total_len - ETHER_CRC_LEN); 1787 1788#ifdef RE_FIXUP_RX 1789 re_fixup_rx(m); 1790#endif 1791 ifp->if_ipackets++; 1792 m->m_pkthdr.rcvif = ifp; 1793 1794 /* Do RX checksumming if enabled */ 1795 1796 if (ifp->if_capenable & IFCAP_RXCSUM) { 1797 1798 /* Check IP header checksum */ 1799 if (rxstat & RL_RDESC_STAT_PROTOID) 1800 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1801 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1802 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1803 1804 /* Check TCP/UDP checksum */ 1805 if ((RL_TCPPKT(rxstat) && 1806 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1807 (RL_UDPPKT(rxstat) && 1808 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1809 m->m_pkthdr.csum_flags |= 1810 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1811 m->m_pkthdr.csum_data = 0xffff; 1812 } 1813 } 1814 maxpkt--; 1815 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1816 m->m_pkthdr.ether_vtag = 1817 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1818 m->m_flags |= M_VLANTAG; 1819 } 1820 RL_UNLOCK(sc); 1821 (*ifp->if_input)(ifp, m); 1822 RL_LOCK(sc); 1823 } 1824 1825 /* Flush the RX DMA ring */ 1826 1827 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1828 sc->rl_ldata.rl_rx_list_map, 1829 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1830 1831 sc->rl_ldata.rl_rx_prodidx = i; 1832 1833 if (maxpkt) 1834 return(EAGAIN); 1835 1836 return(0); 1837} 1838 1839static void 1840re_txeof(sc) 1841 struct rl_softc *sc; 1842{ 1843 struct ifnet *ifp; 1844 u_int32_t txstat; 1845 int idx; 1846 1847 ifp = sc->rl_ifp; 1848 idx = sc->rl_ldata.rl_tx_considx; 1849 1850 /* Invalidate the TX descriptor list */ 1851 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1852 sc->rl_ldata.rl_tx_list_map, 1853 BUS_DMASYNC_POSTREAD); 1854 1855 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1856 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1857 if (txstat & RL_TDESC_CMD_OWN) 1858 break; 1859 1860 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0; 1861 1862 /* 1863 * We only stash mbufs in the last descriptor 1864 * in a fragment chain, which also happens to 1865 * be the only place where the TX status bits 1866 * are valid. 1867 */ 1868 if (txstat & RL_TDESC_CMD_EOF) { 1869 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1870 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1871 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1872 sc->rl_ldata.rl_tx_dmamap[idx]); 1873 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1874 RL_TDESC_STAT_COLCNT)) 1875 ifp->if_collisions++; 1876 if (txstat & RL_TDESC_STAT_TXERRSUM) 1877 ifp->if_oerrors++; 1878 else 1879 ifp->if_opackets++; 1880 } 1881 sc->rl_ldata.rl_tx_free++; 1882 RL_DESC_INC(idx); 1883 } 1884 sc->rl_ldata.rl_tx_considx = idx; 1885 1886 /* No changes made to the TX ring, so no flush needed */ 1887 1888 if (sc->rl_ldata.rl_tx_free > RL_TX_DESC_THLD) 1889 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1890 1891 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1892 /* 1893 * Some chips will ignore a second TX request issued 1894 * while an existing transmission is in progress. If 1895 * the transmitter goes idle but there are still 1896 * packets waiting to be sent, we need to restart the 1897 * channel here to flush them out. This only seems to 1898 * be required with the PCIe devices. 1899 */ 1900 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1901 1902#ifdef RE_TX_MODERATION 1903 /* 1904 * If not all descriptors have been reaped yet, reload 1905 * the timer so that we will eventually get another 1906 * interrupt that will cause us to re-enter this routine. 1907 * This is done in case the transmitter has gone idle. 1908 */ 1909 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1910#endif 1911 } else 1912 sc->rl_watchdog_timer = 0; 1913} 1914 1915static void 1916re_tick(xsc) 1917 void *xsc; 1918{ 1919 struct rl_softc *sc; 1920 struct mii_data *mii; 1921 struct ifnet *ifp; 1922 1923 sc = xsc; 1924 ifp = sc->rl_ifp; 1925 1926 RL_LOCK_ASSERT(sc); 1927 1928 re_watchdog(sc); 1929 1930 mii = device_get_softc(sc->rl_miibus); 1931 mii_tick(mii); 1932 if (sc->rl_link) { 1933 if (!(mii->mii_media_status & IFM_ACTIVE)) 1934 sc->rl_link = 0; 1935 } else { 1936 if (mii->mii_media_status & IFM_ACTIVE && 1937 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1938 sc->rl_link = 1; 1939 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1940 taskqueue_enqueue_fast(taskqueue_fast, 1941 &sc->rl_txtask); 1942 } 1943 } 1944 1945 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1946} 1947 1948#ifdef DEVICE_POLLING 1949static void 1950re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1951{ 1952 struct rl_softc *sc = ifp->if_softc; 1953 1954 RL_LOCK(sc); 1955 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1956 re_poll_locked(ifp, cmd, count); 1957 RL_UNLOCK(sc); 1958} 1959 1960static void 1961re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1962{ 1963 struct rl_softc *sc = ifp->if_softc; 1964 1965 RL_LOCK_ASSERT(sc); 1966 1967 sc->rxcycles = count; 1968 re_rxeof(sc); 1969 re_txeof(sc); 1970 1971 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1972 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 1973 1974 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1975 u_int16_t status; 1976 1977 status = CSR_READ_2(sc, RL_ISR); 1978 if (status == 0xffff) 1979 return; 1980 if (status) 1981 CSR_WRITE_2(sc, RL_ISR, status); 1982 1983 /* 1984 * XXX check behaviour on receiver stalls. 1985 */ 1986 1987 if (status & RL_ISR_SYSTEM_ERR) { 1988 re_reset(sc); 1989 re_init_locked(sc); 1990 } 1991 } 1992} 1993#endif /* DEVICE_POLLING */ 1994 1995static int 1996re_intr(arg) 1997 void *arg; 1998{ 1999 struct rl_softc *sc; 2000 uint16_t status; 2001 2002 sc = arg; 2003 2004 status = CSR_READ_2(sc, RL_ISR); 2005 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2006 return (FILTER_STRAY); 2007 CSR_WRITE_2(sc, RL_IMR, 0); 2008 2009 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2010 2011 return (FILTER_HANDLED); 2012} 2013 2014static void 2015re_int_task(arg, npending) 2016 void *arg; 2017 int npending; 2018{ 2019 struct rl_softc *sc; 2020 struct ifnet *ifp; 2021 u_int16_t status; 2022 int rval = 0; 2023 2024 sc = arg; 2025 ifp = sc->rl_ifp; 2026 2027 RL_LOCK(sc); 2028 2029 status = CSR_READ_2(sc, RL_ISR); 2030 CSR_WRITE_2(sc, RL_ISR, status); 2031 2032 if (sc->suspended || !(ifp->if_flags & IFF_UP)) { 2033 RL_UNLOCK(sc); 2034 return; 2035 } 2036 2037#ifdef DEVICE_POLLING 2038 if (ifp->if_capenable & IFCAP_POLLING) { 2039 RL_UNLOCK(sc); 2040 return; 2041 } 2042#endif 2043 2044 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2045 rval = re_rxeof(sc); 2046 2047#ifdef RE_TX_MODERATION 2048 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2049#else 2050 if (status & (RL_ISR_TX_OK| 2051#endif 2052 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2053 re_txeof(sc); 2054 2055 if (status & RL_ISR_SYSTEM_ERR) { 2056 re_reset(sc); 2057 re_init_locked(sc); 2058 } 2059 2060 if (status & RL_ISR_LINKCHG) { 2061 callout_stop(&sc->rl_stat_callout); 2062 re_tick(sc); 2063 } 2064 2065 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2066 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2067 2068 RL_UNLOCK(sc); 2069 2070 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2071 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2072 return; 2073 } 2074 2075 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2076 2077 return; 2078} 2079 2080static int 2081re_encap(sc, m_head, idx) 2082 struct rl_softc *sc; 2083 struct mbuf **m_head; 2084 int *idx; 2085{ 2086 struct mbuf *m_new = NULL; 2087 struct rl_dmaload_arg arg; 2088 bus_dmamap_t map; 2089 int error; 2090 2091 RL_LOCK_ASSERT(sc); 2092 2093 if (sc->rl_ldata.rl_tx_free <= RL_TX_DESC_THLD) 2094 return (EFBIG); 2095 2096 /* 2097 * Set up checksum offload. Note: checksum offload bits must 2098 * appear in all descriptors of a multi-descriptor transmit 2099 * attempt. This is according to testing done with an 8169 2100 * chip. This is a requirement. 2101 */ 2102 2103 arg.rl_flags = 0; 2104 2105 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2106 arg.rl_flags = RL_TDESC_CMD_LGSEND | 2107 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2108 RL_TDESC_CMD_MSSVAL_SHIFT); 2109 else { 2110 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2111 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 2112 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2113 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 2114 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2115 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 2116 } 2117 2118 arg.rl_idx = *idx; 2119 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2120 if (arg.rl_maxsegs > RL_TX_DESC_THLD) 2121 arg.rl_maxsegs -= RL_TX_DESC_THLD; 2122 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2123 2124 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 2125 2126 /* 2127 * With some of the RealTek chips, using the checksum offload 2128 * support in conjunction with the autopadding feature results 2129 * in the transmission of corrupt frames. For example, if we 2130 * need to send a really small IP fragment that's less than 60 2131 * bytes in size, and IP header checksumming is enabled, the 2132 * resulting ethernet frame that appears on the wire will 2133 * have garbled payload. To work around this, if TX checksum 2134 * offload is enabled, we always manually pad short frames out 2135 * to the minimum ethernet frame size. We do this by pretending 2136 * the mbuf chain has too many fragments so the coalescing code 2137 * below can assemble the packet into a single buffer that's 2138 * padded out to the mininum frame size. 2139 * 2140 * Note: this appears unnecessary for TCP, and doing it for TCP 2141 * with PCIe adapters seems to result in bad checksums. 2142 */ 2143 2144 if (arg.rl_flags && !(arg.rl_flags & RL_TDESC_CMD_TCPCSUM) && 2145 (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) 2146 error = EFBIG; 2147 else 2148 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2149 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2150 2151 if (error && error != EFBIG) { 2152 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", error); 2153 return (ENOBUFS); 2154 } 2155 2156 /* Too many segments to map, coalesce into a single mbuf */ 2157 2158 if (error || arg.rl_maxsegs == 0) { 2159 if (arg.rl_maxsegs == 0) 2160 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map); 2161 m_new = m_defrag(*m_head, M_DONTWAIT); 2162 if (m_new == NULL) { 2163 m_freem(*m_head); 2164 *m_head = NULL; 2165 return (ENOBUFS); 2166 } 2167 *m_head = m_new; 2168 2169 /* 2170 * Manually pad short frames, and zero the pad space 2171 * to avoid leaking data. 2172 */ 2173 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) { 2174 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 2175 RL_MIN_FRAMELEN - m_new->m_pkthdr.len); 2176 m_new->m_pkthdr.len += RL_MIN_FRAMELEN - 2177 m_new->m_pkthdr.len; 2178 m_new->m_len = m_new->m_pkthdr.len; 2179 } 2180 2181 /* Note that we'll run over RL_TX_DESC_THLD here. */ 2182 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2183 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2184 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2185 if (error || arg.rl_maxsegs == 0) { 2186 device_printf(sc->rl_dev, 2187 "can't map defragmented mbuf (error %d)\n", error); 2188 m_freem(m_new); 2189 *m_head = NULL; 2190 if (arg.rl_maxsegs == 0) 2191 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map); 2192 return (EFBIG); 2193 } 2194 } 2195 2196 /* 2197 * Insure that the map for this transmission 2198 * is placed at the array index of the last descriptor 2199 * in this chain. (Swap last and first dmamaps.) 2200 */ 2201 sc->rl_ldata.rl_tx_dmamap[*idx] = 2202 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 2203 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 2204 2205 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 2206 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 2207 2208 /* 2209 * Set up hardware VLAN tagging. Note: vlan tag info must 2210 * appear in the first descriptor of a multi-descriptor 2211 * transmission attempt. 2212 */ 2213 if ((*m_head)->m_flags & M_VLANTAG) 2214 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 2215 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2216 RL_TDESC_VLANCTL_TAG); 2217 2218 /* Transfer ownership of packet to the chip. */ 2219 2220 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 2221 htole32(RL_TDESC_CMD_OWN); 2222 if (*idx != arg.rl_idx) 2223 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 2224 htole32(RL_TDESC_CMD_OWN); 2225 2226 RL_DESC_INC(arg.rl_idx); 2227 *idx = arg.rl_idx; 2228 2229 return (0); 2230} 2231 2232static void 2233re_tx_task(arg, npending) 2234 void *arg; 2235 int npending; 2236{ 2237 struct ifnet *ifp; 2238 2239 ifp = arg; 2240 re_start(ifp); 2241 2242 return; 2243} 2244 2245/* 2246 * Main transmit routine for C+ and gigE NICs. 2247 */ 2248static void 2249re_start(ifp) 2250 struct ifnet *ifp; 2251{ 2252 struct rl_softc *sc; 2253 struct mbuf *m_head = NULL; 2254 int idx, queued = 0; 2255 2256 sc = ifp->if_softc; 2257 2258 RL_LOCK(sc); 2259 2260 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 2261 RL_UNLOCK(sc); 2262 return; 2263 } 2264 2265 idx = sc->rl_ldata.rl_tx_prodidx; 2266 2267 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2268 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2269 if (m_head == NULL) 2270 break; 2271 2272 if (re_encap(sc, &m_head, &idx)) { 2273 if (m_head == NULL) 2274 break; 2275 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2276 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2277 break; 2278 } 2279 2280 /* 2281 * If there's a BPF listener, bounce a copy of this frame 2282 * to him. 2283 */ 2284 ETHER_BPF_MTAP(ifp, m_head); 2285 2286 queued++; 2287 } 2288 2289 if (queued == 0) { 2290#ifdef RE_TX_MODERATION 2291 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 2292 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2293#endif 2294 RL_UNLOCK(sc); 2295 return; 2296 } 2297 2298 /* Flush the TX descriptors */ 2299 2300 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2301 sc->rl_ldata.rl_tx_list_map, 2302 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2303 2304 sc->rl_ldata.rl_tx_prodidx = idx; 2305 2306 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2307 2308#ifdef RE_TX_MODERATION 2309 /* 2310 * Use the countdown timer for interrupt moderation. 2311 * 'TX done' interrupts are disabled. Instead, we reset the 2312 * countdown timer, which will begin counting until it hits 2313 * the value in the TIMERINT register, and then trigger an 2314 * interrupt. Each time we write to the TIMERCNT register, 2315 * the timer count is reset to 0. 2316 */ 2317 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2318#endif 2319 2320 /* 2321 * Set a timeout in case the chip goes out to lunch. 2322 */ 2323 sc->rl_watchdog_timer = 5; 2324 2325 RL_UNLOCK(sc); 2326 2327 return; 2328} 2329 2330static void 2331re_init(xsc) 2332 void *xsc; 2333{ 2334 struct rl_softc *sc = xsc; 2335 2336 RL_LOCK(sc); 2337 re_init_locked(sc); 2338 RL_UNLOCK(sc); 2339} 2340 2341static void 2342re_init_locked(sc) 2343 struct rl_softc *sc; 2344{ 2345 struct ifnet *ifp = sc->rl_ifp; 2346 struct mii_data *mii; 2347 u_int32_t rxcfg = 0; 2348 union { 2349 uint32_t align_dummy; 2350 u_char eaddr[ETHER_ADDR_LEN]; 2351 } eaddr; 2352 2353 RL_LOCK_ASSERT(sc); 2354 2355 mii = device_get_softc(sc->rl_miibus); 2356 2357 /* 2358 * Cancel pending I/O and free all RX/TX buffers. 2359 */ 2360 re_stop(sc); 2361 2362 /* 2363 * Enable C+ RX and TX mode, as well as VLAN stripping and 2364 * RX checksum offload. We must configure the C+ register 2365 * before all others. 2366 */ 2367 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2368 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2369 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB); 2370 2371 /* 2372 * Init our MAC address. Even though the chipset 2373 * documentation doesn't mention it, we need to enter "Config 2374 * register write enable" mode to modify the ID registers. 2375 */ 2376 /* Copy MAC address on stack to align. */ 2377 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2378 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2379 CSR_WRITE_4(sc, RL_IDR0, 2380 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2381 CSR_WRITE_4(sc, RL_IDR4, 2382 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2383 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2384 2385 /* 2386 * For C+ mode, initialize the RX descriptors and mbufs. 2387 */ 2388 re_rx_list_init(sc); 2389 re_tx_list_init(sc); 2390 2391 /* 2392 * Load the addresses of the RX and TX lists into the chip. 2393 */ 2394 2395 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2396 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2397 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2398 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2399 2400 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2401 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2402 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2403 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2404 2405 /* 2406 * Enable transmit and receive. 2407 */ 2408 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2409 2410 /* 2411 * Set the initial TX and RX configuration. 2412 */ 2413 if (sc->rl_testmode) { 2414 if (sc->rl_type == RL_8169) 2415 CSR_WRITE_4(sc, RL_TXCFG, 2416 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2417 else 2418 CSR_WRITE_4(sc, RL_TXCFG, 2419 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2420 } else 2421 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2422 2423 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2424 2425 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2426 2427 /* Set the individual bit to receive frames for this host only. */ 2428 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2429 rxcfg |= RL_RXCFG_RX_INDIV; 2430 2431 /* If we want promiscuous mode, set the allframes bit. */ 2432 if (ifp->if_flags & IFF_PROMISC) 2433 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2434 else 2435 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2436 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2437 2438 /* 2439 * Set capture broadcast bit to capture broadcast frames. 2440 */ 2441 if (ifp->if_flags & IFF_BROADCAST) 2442 rxcfg |= RL_RXCFG_RX_BROAD; 2443 else 2444 rxcfg &= ~RL_RXCFG_RX_BROAD; 2445 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2446 2447 /* 2448 * Program the multicast filter, if necessary. 2449 */ 2450 re_setmulti(sc); 2451 2452#ifdef DEVICE_POLLING 2453 /* 2454 * Disable interrupts if we are polling. 2455 */ 2456 if (ifp->if_capenable & IFCAP_POLLING) 2457 CSR_WRITE_2(sc, RL_IMR, 0); 2458 else /* otherwise ... */ 2459#endif 2460 2461 /* 2462 * Enable interrupts. 2463 */ 2464 if (sc->rl_testmode) 2465 CSR_WRITE_2(sc, RL_IMR, 0); 2466 else 2467 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2468 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2469 2470 /* Set initial TX threshold */ 2471 sc->rl_txthresh = RL_TX_THRESH_INIT; 2472 2473 /* Start RX/TX process. */ 2474 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2475#ifdef notdef 2476 /* Enable receiver and transmitter. */ 2477 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2478#endif 2479 2480#ifdef RE_TX_MODERATION 2481 /* 2482 * Initialize the timer interrupt register so that 2483 * a timer interrupt will be generated once the timer 2484 * reaches a certain number of ticks. The timer is 2485 * reloaded on each transmit. This gives us TX interrupt 2486 * moderation, which dramatically improves TX frame rate. 2487 */ 2488 if (sc->rl_type == RL_8169) 2489 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2490 else 2491 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2492#endif 2493 2494 /* 2495 * For 8169 gigE NICs, set the max allowed RX packet 2496 * size so we can receive jumbo frames. 2497 */ 2498 if (sc->rl_type == RL_8169) 2499 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2500 2501 if (sc->rl_testmode) 2502 return; 2503 2504 mii_mediachg(mii); 2505 2506 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2507 2508 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2509 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2510 2511 sc->rl_link = 0; 2512 sc->rl_watchdog_timer = 0; 2513 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2514} 2515 2516/* 2517 * Set media options. 2518 */ 2519static int 2520re_ifmedia_upd(ifp) 2521 struct ifnet *ifp; 2522{ 2523 struct rl_softc *sc; 2524 struct mii_data *mii; 2525 2526 sc = ifp->if_softc; 2527 mii = device_get_softc(sc->rl_miibus); 2528 RL_LOCK(sc); 2529 mii_mediachg(mii); 2530 RL_UNLOCK(sc); 2531 2532 return (0); 2533} 2534 2535/* 2536 * Report current media status. 2537 */ 2538static void 2539re_ifmedia_sts(ifp, ifmr) 2540 struct ifnet *ifp; 2541 struct ifmediareq *ifmr; 2542{ 2543 struct rl_softc *sc; 2544 struct mii_data *mii; 2545 2546 sc = ifp->if_softc; 2547 mii = device_get_softc(sc->rl_miibus); 2548 2549 RL_LOCK(sc); 2550 mii_pollstat(mii); 2551 RL_UNLOCK(sc); 2552 ifmr->ifm_active = mii->mii_media_active; 2553 ifmr->ifm_status = mii->mii_media_status; 2554} 2555 2556static int 2557re_ioctl(ifp, command, data) 2558 struct ifnet *ifp; 2559 u_long command; 2560 caddr_t data; 2561{ 2562 struct rl_softc *sc = ifp->if_softc; 2563 struct ifreq *ifr = (struct ifreq *) data; 2564 struct mii_data *mii; 2565 int error = 0; 2566 2567 switch (command) { 2568 case SIOCSIFMTU: 2569 RL_LOCK(sc); 2570 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2571 error = EINVAL; 2572 ifp->if_mtu = ifr->ifr_mtu; 2573 RL_UNLOCK(sc); 2574 break; 2575 case SIOCSIFFLAGS: 2576 RL_LOCK(sc); 2577 if ((ifp->if_flags & IFF_UP) != 0) { 2578 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2579 if (((ifp->if_flags ^ sc->rl_if_flags) 2580 & IFF_PROMISC) != 0) 2581 re_setmulti(sc); 2582 } else 2583 re_init_locked(sc); 2584 } else { 2585 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2586 re_stop(sc); 2587 } 2588 sc->rl_if_flags = ifp->if_flags; 2589 RL_UNLOCK(sc); 2590 break; 2591 case SIOCADDMULTI: 2592 case SIOCDELMULTI: 2593 RL_LOCK(sc); 2594 re_setmulti(sc); 2595 RL_UNLOCK(sc); 2596 break; 2597 case SIOCGIFMEDIA: 2598 case SIOCSIFMEDIA: 2599 mii = device_get_softc(sc->rl_miibus); 2600 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2601 break; 2602 case SIOCSIFCAP: 2603 { 2604 int mask, reinit; 2605 2606 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2607 reinit = 0; 2608#ifdef DEVICE_POLLING 2609 if (mask & IFCAP_POLLING) { 2610 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2611 error = ether_poll_register(re_poll, ifp); 2612 if (error) 2613 return(error); 2614 RL_LOCK(sc); 2615 /* Disable interrupts */ 2616 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2617 ifp->if_capenable |= IFCAP_POLLING; 2618 RL_UNLOCK(sc); 2619 } else { 2620 error = ether_poll_deregister(ifp); 2621 /* Enable interrupts. */ 2622 RL_LOCK(sc); 2623 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2624 ifp->if_capenable &= ~IFCAP_POLLING; 2625 RL_UNLOCK(sc); 2626 } 2627 } 2628#endif /* DEVICE_POLLING */ 2629 if (mask & IFCAP_HWCSUM) { 2630 ifp->if_capenable ^= IFCAP_HWCSUM; 2631 if (ifp->if_capenable & IFCAP_TXCSUM) 2632 ifp->if_hwassist |= RE_CSUM_FEATURES; 2633 else 2634 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2635 reinit = 1; 2636 } 2637 if (mask & IFCAP_VLAN_HWTAGGING) { 2638 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2639 reinit = 1; 2640 } 2641 if (mask & IFCAP_TSO4) { 2642 ifp->if_capenable ^= IFCAP_TSO4; 2643 if ((IFCAP_TSO4 & ifp->if_capenable) && 2644 (IFCAP_TSO4 & ifp->if_capabilities)) 2645 ifp->if_hwassist |= CSUM_TSO; 2646 else 2647 ifp->if_hwassist &= ~CSUM_TSO; 2648 } 2649 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2650 re_init(sc); 2651 VLAN_CAPABILITIES(ifp); 2652 } 2653 break; 2654 default: 2655 error = ether_ioctl(ifp, command, data); 2656 break; 2657 } 2658 2659 return (error); 2660} 2661 2662static void 2663re_watchdog(sc) 2664 struct rl_softc *sc; 2665{ 2666 2667 RL_LOCK_ASSERT(sc); 2668 2669 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2670 return; 2671 2672 device_printf(sc->rl_dev, "watchdog timeout\n"); 2673 sc->rl_ifp->if_oerrors++; 2674 2675 re_txeof(sc); 2676 re_rxeof(sc); 2677 re_init_locked(sc); 2678} 2679 2680/* 2681 * Stop the adapter and free any mbufs allocated to the 2682 * RX and TX lists. 2683 */ 2684static void 2685re_stop(sc) 2686 struct rl_softc *sc; 2687{ 2688 register int i; 2689 struct ifnet *ifp; 2690 2691 RL_LOCK_ASSERT(sc); 2692 2693 ifp = sc->rl_ifp; 2694 2695 sc->rl_watchdog_timer = 0; 2696 callout_stop(&sc->rl_stat_callout); 2697 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2698 2699 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2700 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2701 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2702 2703 if (sc->rl_head != NULL) { 2704 m_freem(sc->rl_head); 2705 sc->rl_head = sc->rl_tail = NULL; 2706 } 2707 2708 /* Free the TX list buffers. */ 2709 2710 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2711 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2712 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2713 sc->rl_ldata.rl_tx_dmamap[i]); 2714 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2715 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2716 } 2717 } 2718 2719 /* Free the RX list buffers. */ 2720 2721 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2722 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2723 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2724 sc->rl_ldata.rl_rx_dmamap[i]); 2725 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2726 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2727 } 2728 } 2729} 2730 2731/* 2732 * Device suspend routine. Stop the interface and save some PCI 2733 * settings in case the BIOS doesn't restore them properly on 2734 * resume. 2735 */ 2736static int 2737re_suspend(dev) 2738 device_t dev; 2739{ 2740 struct rl_softc *sc; 2741 2742 sc = device_get_softc(dev); 2743 2744 RL_LOCK(sc); 2745 re_stop(sc); 2746 sc->suspended = 1; 2747 RL_UNLOCK(sc); 2748 2749 return (0); 2750} 2751 2752/* 2753 * Device resume routine. Restore some PCI settings in case the BIOS 2754 * doesn't, re-enable busmastering, and restart the interface if 2755 * appropriate. 2756 */ 2757static int 2758re_resume(dev) 2759 device_t dev; 2760{ 2761 struct rl_softc *sc; 2762 struct ifnet *ifp; 2763 2764 sc = device_get_softc(dev); 2765 2766 RL_LOCK(sc); 2767 2768 ifp = sc->rl_ifp; 2769 2770 /* reinitialize interface if necessary */ 2771 if (ifp->if_flags & IFF_UP) 2772 re_init_locked(sc); 2773 2774 sc->suspended = 0; 2775 RL_UNLOCK(sc); 2776 2777 return (0); 2778} 2779 2780/* 2781 * Stop all chip I/O so that the kernel's probe routines don't 2782 * get confused by errant DMAs when rebooting. 2783 */ 2784static void 2785re_shutdown(dev) 2786 device_t dev; 2787{ 2788 struct rl_softc *sc; 2789 2790 sc = device_get_softc(dev); 2791 2792 RL_LOCK(sc); 2793 re_stop(sc); 2794 /* 2795 * Mark interface as down since otherwise we will panic if 2796 * interrupt comes in later on, which can happen in some 2797 * cases. 2798 */ 2799 sc->rl_ifp->if_flags &= ~IFF_UP; 2800 RL_UNLOCK(sc); 2801} 2802