if_re.c revision 167190
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 167190 2007-03-04 03:38:08Z csjp $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149MODULE_DEPEND(re, pci, 1, 1, 1); 150MODULE_DEPEND(re, ether, 1, 1, 1); 151MODULE_DEPEND(re, miibus, 1, 1, 1); 152 153/* "device miibus" required. See GENERIC if you get errors here. */ 154#include "miibus_if.h" 155 156/* 157 * Default to using PIO access for this driver. 158 */ 159#define RE_USEIOSPACE 160 161#include <pci/if_rlreg.h> 162 163#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 164 165/* 166 * Various supported device vendors/types and their names. 167 */ 168static struct rl_type re_devs[] = { 169 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 171 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 172 "RealTek 8139C+ 10/100BaseTX" }, 173 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 174 "RealTek 8101E PCIe 10/100baseTX" }, 175 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 176 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 178 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 180 "RealTek 8169 Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 182 "RealTek 8169S Single-chip Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 184 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 186 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 188 "RealTek 8110S Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }, 195 { 0, 0, 0, NULL } 196}; 197 198static struct rl_hwrev re_hwrevs[] = { 199 { RL_HWREV_8139, RL_8139, "" }, 200 { RL_HWREV_8139A, RL_8139, "A" }, 201 { RL_HWREV_8139AG, RL_8139, "A-G" }, 202 { RL_HWREV_8139B, RL_8139, "B" }, 203 { RL_HWREV_8130, RL_8139, "8130" }, 204 { RL_HWREV_8139C, RL_8139, "C" }, 205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 207 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 208 { RL_HWREV_8169, RL_8169, "8169"}, 209 { RL_HWREV_8169S, RL_8169, "8169S"}, 210 { RL_HWREV_8110S, RL_8169, "8110S"}, 211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 213 { RL_HWREV_8100, RL_8139, "8100"}, 214 { RL_HWREV_8101, RL_8139, "8101"}, 215 { RL_HWREV_8100E, RL_8169, "8100E"}, 216 { RL_HWREV_8101E, RL_8169, "8101E"}, 217 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 218 { 0, 0, NULL } 219}; 220 221static int re_probe (device_t); 222static int re_attach (device_t); 223static int re_detach (device_t); 224 225static int re_encap (struct rl_softc *, struct mbuf **, int *); 226 227static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 228static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 229 bus_size_t, int); 230static int re_allocmem (device_t, struct rl_softc *); 231static int re_newbuf (struct rl_softc *, int, struct mbuf *); 232static int re_rx_list_init (struct rl_softc *); 233static int re_tx_list_init (struct rl_softc *); 234#ifdef RE_FIXUP_RX 235static __inline void re_fixup_rx 236 (struct mbuf *); 237#endif 238static int re_rxeof (struct rl_softc *); 239static void re_txeof (struct rl_softc *); 240#ifdef DEVICE_POLLING 241static void re_poll (struct ifnet *, enum poll_cmd, int); 242static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 243#endif 244static int re_intr (void *); 245static void re_tick (void *); 246static void re_tx_task (void *, int); 247static void re_int_task (void *, int); 248static void re_start (struct ifnet *); 249static int re_ioctl (struct ifnet *, u_long, caddr_t); 250static void re_init (void *); 251static void re_init_locked (struct rl_softc *); 252static void re_stop (struct rl_softc *); 253static void re_watchdog (struct rl_softc *); 254static int re_suspend (device_t); 255static int re_resume (device_t); 256static void re_shutdown (device_t); 257static int re_ifmedia_upd (struct ifnet *); 258static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 259 260static void re_eeprom_putbyte (struct rl_softc *, int); 261static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 262static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 263static int re_gmii_readreg (device_t, int, int); 264static int re_gmii_writereg (device_t, int, int, int); 265 266static int re_miibus_readreg (device_t, int, int); 267static int re_miibus_writereg (device_t, int, int, int); 268static void re_miibus_statchg (device_t); 269 270static void re_setmulti (struct rl_softc *); 271static void re_reset (struct rl_softc *); 272 273#ifdef RE_DIAG 274static int re_diag (struct rl_softc *); 275#endif 276 277#ifdef RE_USEIOSPACE 278#define RL_RES SYS_RES_IOPORT 279#define RL_RID RL_PCI_LOIO 280#else 281#define RL_RES SYS_RES_MEMORY 282#define RL_RID RL_PCI_LOMEM 283#endif 284 285static device_method_t re_methods[] = { 286 /* Device interface */ 287 DEVMETHOD(device_probe, re_probe), 288 DEVMETHOD(device_attach, re_attach), 289 DEVMETHOD(device_detach, re_detach), 290 DEVMETHOD(device_suspend, re_suspend), 291 DEVMETHOD(device_resume, re_resume), 292 DEVMETHOD(device_shutdown, re_shutdown), 293 294 /* bus interface */ 295 DEVMETHOD(bus_print_child, bus_generic_print_child), 296 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 297 298 /* MII interface */ 299 DEVMETHOD(miibus_readreg, re_miibus_readreg), 300 DEVMETHOD(miibus_writereg, re_miibus_writereg), 301 DEVMETHOD(miibus_statchg, re_miibus_statchg), 302 303 { 0, 0 } 304}; 305 306static driver_t re_driver = { 307 "re", 308 re_methods, 309 sizeof(struct rl_softc) 310}; 311 312static devclass_t re_devclass; 313 314DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 315DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 316DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 317 318#define EE_SET(x) \ 319 CSR_WRITE_1(sc, RL_EECMD, \ 320 CSR_READ_1(sc, RL_EECMD) | x) 321 322#define EE_CLR(x) \ 323 CSR_WRITE_1(sc, RL_EECMD, \ 324 CSR_READ_1(sc, RL_EECMD) & ~x) 325 326/* 327 * Send a read command and address to the EEPROM, check for ACK. 328 */ 329static void 330re_eeprom_putbyte(sc, addr) 331 struct rl_softc *sc; 332 int addr; 333{ 334 register int d, i; 335 336 d = addr | (RL_9346_READ << sc->rl_eewidth); 337 338 /* 339 * Feed in each bit and strobe the clock. 340 */ 341 342 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 343 if (d & i) { 344 EE_SET(RL_EE_DATAIN); 345 } else { 346 EE_CLR(RL_EE_DATAIN); 347 } 348 DELAY(100); 349 EE_SET(RL_EE_CLK); 350 DELAY(150); 351 EE_CLR(RL_EE_CLK); 352 DELAY(100); 353 } 354 355 return; 356} 357 358/* 359 * Read a word of data stored in the EEPROM at address 'addr.' 360 */ 361static void 362re_eeprom_getword(sc, addr, dest) 363 struct rl_softc *sc; 364 int addr; 365 u_int16_t *dest; 366{ 367 register int i; 368 u_int16_t word = 0; 369 370 /* 371 * Send address of word we want to read. 372 */ 373 re_eeprom_putbyte(sc, addr); 374 375 /* 376 * Start reading bits from EEPROM. 377 */ 378 for (i = 0x8000; i; i >>= 1) { 379 EE_SET(RL_EE_CLK); 380 DELAY(100); 381 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 382 word |= i; 383 EE_CLR(RL_EE_CLK); 384 DELAY(100); 385 } 386 387 *dest = word; 388 389 return; 390} 391 392/* 393 * Read a sequence of words from the EEPROM. 394 */ 395static void 396re_read_eeprom(sc, dest, off, cnt) 397 struct rl_softc *sc; 398 caddr_t dest; 399 int off; 400 int cnt; 401{ 402 int i; 403 u_int16_t word = 0, *ptr; 404 405 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 406 407 DELAY(100); 408 409 for (i = 0; i < cnt; i++) { 410 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 411 re_eeprom_getword(sc, off + i, &word); 412 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 413 ptr = (u_int16_t *)(dest + (i * 2)); 414 *ptr = word; 415 } 416 417 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 418 419 return; 420} 421 422static int 423re_gmii_readreg(dev, phy, reg) 424 device_t dev; 425 int phy, reg; 426{ 427 struct rl_softc *sc; 428 u_int32_t rval; 429 int i; 430 431 if (phy != 1) 432 return (0); 433 434 sc = device_get_softc(dev); 435 436 /* Let the rgephy driver read the GMEDIASTAT register */ 437 438 if (reg == RL_GMEDIASTAT) { 439 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 440 return (rval); 441 } 442 443 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 444 DELAY(1000); 445 446 for (i = 0; i < RL_TIMEOUT; i++) { 447 rval = CSR_READ_4(sc, RL_PHYAR); 448 if (rval & RL_PHYAR_BUSY) 449 break; 450 DELAY(100); 451 } 452 453 if (i == RL_TIMEOUT) { 454 device_printf(sc->rl_dev, "PHY read failed\n"); 455 return (0); 456 } 457 458 return (rval & RL_PHYAR_PHYDATA); 459} 460 461static int 462re_gmii_writereg(dev, phy, reg, data) 463 device_t dev; 464 int phy, reg, data; 465{ 466 struct rl_softc *sc; 467 u_int32_t rval; 468 int i; 469 470 sc = device_get_softc(dev); 471 472 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 473 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 474 DELAY(1000); 475 476 for (i = 0; i < RL_TIMEOUT; i++) { 477 rval = CSR_READ_4(sc, RL_PHYAR); 478 if (!(rval & RL_PHYAR_BUSY)) 479 break; 480 DELAY(100); 481 } 482 483 if (i == RL_TIMEOUT) { 484 device_printf(sc->rl_dev, "PHY write failed\n"); 485 return (0); 486 } 487 488 return (0); 489} 490 491static int 492re_miibus_readreg(dev, phy, reg) 493 device_t dev; 494 int phy, reg; 495{ 496 struct rl_softc *sc; 497 u_int16_t rval = 0; 498 u_int16_t re8139_reg = 0; 499 500 sc = device_get_softc(dev); 501 502 if (sc->rl_type == RL_8169) { 503 rval = re_gmii_readreg(dev, phy, reg); 504 return (rval); 505 } 506 507 /* Pretend the internal PHY is only at address 0 */ 508 if (phy) { 509 return (0); 510 } 511 switch (reg) { 512 case MII_BMCR: 513 re8139_reg = RL_BMCR; 514 break; 515 case MII_BMSR: 516 re8139_reg = RL_BMSR; 517 break; 518 case MII_ANAR: 519 re8139_reg = RL_ANAR; 520 break; 521 case MII_ANER: 522 re8139_reg = RL_ANER; 523 break; 524 case MII_ANLPAR: 525 re8139_reg = RL_LPAR; 526 break; 527 case MII_PHYIDR1: 528 case MII_PHYIDR2: 529 return (0); 530 /* 531 * Allow the rlphy driver to read the media status 532 * register. If we have a link partner which does not 533 * support NWAY, this is the register which will tell 534 * us the results of parallel detection. 535 */ 536 case RL_MEDIASTAT: 537 rval = CSR_READ_1(sc, RL_MEDIASTAT); 538 return (rval); 539 default: 540 device_printf(sc->rl_dev, "bad phy register\n"); 541 return (0); 542 } 543 rval = CSR_READ_2(sc, re8139_reg); 544 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 545 /* 8139C+ has different bit layout. */ 546 rval &= ~(BMCR_LOOP | BMCR_ISO); 547 } 548 return (rval); 549} 550 551static int 552re_miibus_writereg(dev, phy, reg, data) 553 device_t dev; 554 int phy, reg, data; 555{ 556 struct rl_softc *sc; 557 u_int16_t re8139_reg = 0; 558 int rval = 0; 559 560 sc = device_get_softc(dev); 561 562 if (sc->rl_type == RL_8169) { 563 rval = re_gmii_writereg(dev, phy, reg, data); 564 return (rval); 565 } 566 567 /* Pretend the internal PHY is only at address 0 */ 568 if (phy) 569 return (0); 570 571 switch (reg) { 572 case MII_BMCR: 573 re8139_reg = RL_BMCR; 574 if (sc->rl_type == RL_8139CPLUS) { 575 /* 8139C+ has different bit layout. */ 576 data &= ~(BMCR_LOOP | BMCR_ISO); 577 } 578 break; 579 case MII_BMSR: 580 re8139_reg = RL_BMSR; 581 break; 582 case MII_ANAR: 583 re8139_reg = RL_ANAR; 584 break; 585 case MII_ANER: 586 re8139_reg = RL_ANER; 587 break; 588 case MII_ANLPAR: 589 re8139_reg = RL_LPAR; 590 break; 591 case MII_PHYIDR1: 592 case MII_PHYIDR2: 593 return (0); 594 break; 595 default: 596 device_printf(sc->rl_dev, "bad phy register\n"); 597 return (0); 598 } 599 CSR_WRITE_2(sc, re8139_reg, data); 600 return (0); 601} 602 603static void 604re_miibus_statchg(dev) 605 device_t dev; 606{ 607 608} 609 610/* 611 * Program the 64-bit multicast hash filter. 612 */ 613static void 614re_setmulti(sc) 615 struct rl_softc *sc; 616{ 617 struct ifnet *ifp; 618 int h = 0; 619 u_int32_t hashes[2] = { 0, 0 }; 620 struct ifmultiaddr *ifma; 621 u_int32_t rxfilt; 622 int mcnt = 0; 623 u_int32_t hwrev; 624 625 RL_LOCK_ASSERT(sc); 626 627 ifp = sc->rl_ifp; 628 629 rxfilt = CSR_READ_4(sc, RL_RXCFG); 630 631 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 632 rxfilt |= RL_RXCFG_RX_MULTI; 633 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 634 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 635 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 636 return; 637 } 638 639 /* first, zot all the existing hash bits */ 640 CSR_WRITE_4(sc, RL_MAR0, 0); 641 CSR_WRITE_4(sc, RL_MAR4, 0); 642 643 /* now program new ones */ 644 IF_ADDR_LOCK(ifp); 645 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 646 if (ifma->ifma_addr->sa_family != AF_LINK) 647 continue; 648 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 649 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 650 if (h < 32) 651 hashes[0] |= (1 << h); 652 else 653 hashes[1] |= (1 << (h - 32)); 654 mcnt++; 655 } 656 IF_ADDR_UNLOCK(ifp); 657 658 if (mcnt) 659 rxfilt |= RL_RXCFG_RX_MULTI; 660 else 661 rxfilt &= ~RL_RXCFG_RX_MULTI; 662 663 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 664 665 /* 666 * For some unfathomable reason, RealTek decided to reverse 667 * the order of the multicast hash registers in the PCI Express 668 * parts. This means we have to write the hash pattern in reverse 669 * order for those devices. 670 */ 671 672 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 673 674 if (hwrev == RL_HWREV_8100E || hwrev == RL_HWREV_8101E || 675 hwrev == RL_HWREV_8168_SPIN1 || hwrev == RL_HWREV_8168_SPIN2) { 676 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 677 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 678 } else { 679 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 680 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 681 } 682} 683 684static void 685re_reset(sc) 686 struct rl_softc *sc; 687{ 688 register int i; 689 690 RL_LOCK_ASSERT(sc); 691 692 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 693 694 for (i = 0; i < RL_TIMEOUT; i++) { 695 DELAY(10); 696 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 697 break; 698 } 699 if (i == RL_TIMEOUT) 700 device_printf(sc->rl_dev, "reset never completed!\n"); 701 702 CSR_WRITE_1(sc, 0x82, 1); 703} 704 705#ifdef RE_DIAG 706 707/* 708 * The following routine is designed to test for a defect on some 709 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 710 * lines connected to the bus, however for a 32-bit only card, they 711 * should be pulled high. The result of this defect is that the 712 * NIC will not work right if you plug it into a 64-bit slot: DMA 713 * operations will be done with 64-bit transfers, which will fail 714 * because the 64-bit data lines aren't connected. 715 * 716 * There's no way to work around this (short of talking a soldering 717 * iron to the board), however we can detect it. The method we use 718 * here is to put the NIC into digital loopback mode, set the receiver 719 * to promiscuous mode, and then try to send a frame. We then compare 720 * the frame data we sent to what was received. If the data matches, 721 * then the NIC is working correctly, otherwise we know the user has 722 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 723 * slot. In the latter case, there's no way the NIC can work correctly, 724 * so we print out a message on the console and abort the device attach. 725 */ 726 727static int 728re_diag(sc) 729 struct rl_softc *sc; 730{ 731 struct ifnet *ifp = sc->rl_ifp; 732 struct mbuf *m0; 733 struct ether_header *eh; 734 struct rl_desc *cur_rx; 735 u_int16_t status; 736 u_int32_t rxstat; 737 int total_len, i, error = 0, phyaddr; 738 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 739 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 740 741 /* Allocate a single mbuf */ 742 MGETHDR(m0, M_DONTWAIT, MT_DATA); 743 if (m0 == NULL) 744 return (ENOBUFS); 745 746 RL_LOCK(sc); 747 748 /* 749 * Initialize the NIC in test mode. This sets the chip up 750 * so that it can send and receive frames, but performs the 751 * following special functions: 752 * - Puts receiver in promiscuous mode 753 * - Enables digital loopback mode 754 * - Leaves interrupts turned off 755 */ 756 757 ifp->if_flags |= IFF_PROMISC; 758 sc->rl_testmode = 1; 759 re_reset(sc); 760 re_init_locked(sc); 761 sc->rl_link = 1; 762 if (sc->rl_type == RL_8169) 763 phyaddr = 1; 764 else 765 phyaddr = 0; 766 767 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 768 for (i = 0; i < RL_TIMEOUT; i++) { 769 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 770 if (!(status & BMCR_RESET)) 771 break; 772 } 773 774 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 775 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 776 777 DELAY(100000); 778 779 /* Put some data in the mbuf */ 780 781 eh = mtod(m0, struct ether_header *); 782 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 783 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 784 eh->ether_type = htons(ETHERTYPE_IP); 785 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 786 787 /* 788 * Queue the packet, start transmission. 789 * Note: IF_HANDOFF() ultimately calls re_start() for us. 790 */ 791 792 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 793 RL_UNLOCK(sc); 794 /* XXX: re_diag must not be called when in ALTQ mode */ 795 IF_HANDOFF(&ifp->if_snd, m0, ifp); 796 RL_LOCK(sc); 797 m0 = NULL; 798 799 /* Wait for it to propagate through the chip */ 800 801 DELAY(100000); 802 for (i = 0; i < RL_TIMEOUT; i++) { 803 status = CSR_READ_2(sc, RL_ISR); 804 CSR_WRITE_2(sc, RL_ISR, status); 805 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 806 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 807 break; 808 DELAY(10); 809 } 810 811 if (i == RL_TIMEOUT) { 812 device_printf(sc->rl_dev, 813 "diagnostic failed, failed to receive packet in" 814 " loopback mode\n"); 815 error = EIO; 816 goto done; 817 } 818 819 /* 820 * The packet should have been dumped into the first 821 * entry in the RX DMA ring. Grab it from there. 822 */ 823 824 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 825 sc->rl_ldata.rl_rx_list_map, 826 BUS_DMASYNC_POSTREAD); 827 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 828 sc->rl_ldata.rl_rx_dmamap[0], 829 BUS_DMASYNC_POSTWRITE); 830 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 831 sc->rl_ldata.rl_rx_dmamap[0]); 832 833 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 834 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 835 eh = mtod(m0, struct ether_header *); 836 837 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 838 total_len = RL_RXBYTES(cur_rx); 839 rxstat = le32toh(cur_rx->rl_cmdstat); 840 841 if (total_len != ETHER_MIN_LEN) { 842 device_printf(sc->rl_dev, 843 "diagnostic failed, received short packet\n"); 844 error = EIO; 845 goto done; 846 } 847 848 /* Test that the received packet data matches what we sent. */ 849 850 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 851 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 852 ntohs(eh->ether_type) != ETHERTYPE_IP) { 853 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 854 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 855 dst, ":", src, ":", ETHERTYPE_IP); 856 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 857 eh->ether_dhost, ":", eh->ether_shost, ":", 858 ntohs(eh->ether_type)); 859 device_printf(sc->rl_dev, "You may have a defective 32-bit " 860 "NIC plugged into a 64-bit PCI slot.\n"); 861 device_printf(sc->rl_dev, "Please re-install the NIC in a " 862 "32-bit slot for proper operation.\n"); 863 device_printf(sc->rl_dev, "Read the re(4) man page for more " 864 "details.\n"); 865 error = EIO; 866 } 867 868done: 869 /* Turn interface off, release resources */ 870 871 sc->rl_testmode = 0; 872 sc->rl_link = 0; 873 ifp->if_flags &= ~IFF_PROMISC; 874 re_stop(sc); 875 if (m0 != NULL) 876 m_freem(m0); 877 878 RL_UNLOCK(sc); 879 880 return (error); 881} 882 883#endif 884 885/* 886 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 887 * IDs against our list and return a device name if we find a match. 888 */ 889static int 890re_probe(dev) 891 device_t dev; 892{ 893 struct rl_type *t; 894 struct rl_softc *sc; 895 int rid; 896 u_int32_t hwrev; 897 898 t = re_devs; 899 sc = device_get_softc(dev); 900 901 while (t->rl_name != NULL) { 902 if ((pci_get_vendor(dev) == t->rl_vid) && 903 (pci_get_device(dev) == t->rl_did)) { 904 /* 905 * Only attach to rev. 3 of the Linksys EG1032 adapter. 906 * Rev. 2 i supported by sk(4). 907 */ 908 if ((t->rl_vid == LINKSYS_VENDORID) && 909 (t->rl_did == LINKSYS_DEVICEID_EG1032) && 910 (pci_get_subdevice(dev) != 911 LINKSYS_SUBDEVICE_EG1032_REV3)) { 912 t++; 913 continue; 914 } 915 916 /* 917 * Temporarily map the I/O space 918 * so we can read the chip ID register. 919 */ 920 rid = RL_RID; 921 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 922 RF_ACTIVE); 923 if (sc->rl_res == NULL) { 924 device_printf(dev, 925 "couldn't map ports/memory\n"); 926 return (ENXIO); 927 } 928 sc->rl_btag = rman_get_bustag(sc->rl_res); 929 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 930 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 931 bus_release_resource(dev, RL_RES, 932 RL_RID, sc->rl_res); 933 if (t->rl_basetype == hwrev) { 934 device_set_desc(dev, t->rl_name); 935 return (BUS_PROBE_DEFAULT); 936 } 937 } 938 t++; 939 } 940 941 return (ENXIO); 942} 943 944/* 945 * This routine takes the segment list provided as the result of 946 * a bus_dma_map_load() operation and assigns the addresses/lengths 947 * to RealTek DMA descriptors. This can be called either by the RX 948 * code or the TX code. In the RX case, we'll probably wind up mapping 949 * at most one segment. For the TX case, there could be any number of 950 * segments since TX packets may span multiple mbufs. In either case, 951 * if the number of segments is larger than the rl_maxsegs limit 952 * specified by the caller, we abort the mapping operation. Sadly, 953 * whoever designed the buffer mapping API did not provide a way to 954 * return an error from here, so we have to fake it a bit. 955 */ 956 957static void 958re_dma_map_desc(arg, segs, nseg, mapsize, error) 959 void *arg; 960 bus_dma_segment_t *segs; 961 int nseg; 962 bus_size_t mapsize; 963 int error; 964{ 965 struct rl_dmaload_arg *ctx; 966 struct rl_desc *d = NULL; 967 int i = 0, idx; 968 u_int32_t cmdstat; 969 int totlen = 0; 970 971 if (error) 972 return; 973 974 ctx = arg; 975 976 /* Signal error to caller if there's too many segments */ 977 if (nseg > ctx->rl_maxsegs) { 978 ctx->rl_maxsegs = 0; 979 return; 980 } 981 982 /* 983 * Map the segment array into descriptors. Note that we set the 984 * start-of-frame and end-of-frame markers for either TX or RX, but 985 * they really only have meaning in the TX case. (In the RX case, 986 * it's the chip that tells us where packets begin and end.) 987 * We also keep track of the end of the ring and set the 988 * end-of-ring bits as needed, and we set the ownership bits 989 * in all except the very first descriptor. (The caller will 990 * set this descriptor later when it start transmission or 991 * reception.) 992 */ 993 idx = ctx->rl_idx; 994 for (;;) { 995 d = &ctx->rl_ring[idx]; 996 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 997 ctx->rl_maxsegs = 0; 998 return; 999 } 1000 cmdstat = segs[i].ds_len; 1001 totlen += segs[i].ds_len; 1002 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 1003 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 1004 if (i == 0) 1005 cmdstat |= RL_TDESC_CMD_SOF; 1006 else 1007 cmdstat |= RL_TDESC_CMD_OWN; 1008 if (idx == (RL_RX_DESC_CNT - 1)) 1009 cmdstat |= RL_TDESC_CMD_EOR; 1010 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 1011 i++; 1012 if (i == nseg) 1013 break; 1014 RL_DESC_INC(idx); 1015 } 1016 1017 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 1018 ctx->rl_maxsegs = nseg; 1019 ctx->rl_idx = idx; 1020} 1021 1022/* 1023 * Map a single buffer address. 1024 */ 1025 1026static void 1027re_dma_map_addr(arg, segs, nseg, error) 1028 void *arg; 1029 bus_dma_segment_t *segs; 1030 int nseg; 1031 int error; 1032{ 1033 bus_addr_t *addr; 1034 1035 if (error) 1036 return; 1037 1038 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1039 addr = arg; 1040 *addr = segs->ds_addr; 1041} 1042 1043static int 1044re_allocmem(dev, sc) 1045 device_t dev; 1046 struct rl_softc *sc; 1047{ 1048 int error; 1049 int nseg; 1050 int i; 1051 1052 /* 1053 * Allocate map for RX mbufs. 1054 */ 1055 nseg = 32; 1056 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 1057 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1058 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 1059 NULL, NULL, &sc->rl_ldata.rl_mtag); 1060 if (error) { 1061 device_printf(dev, "could not allocate dma tag\n"); 1062 return (ENOMEM); 1063 } 1064 1065 /* 1066 * Allocate map for TX descriptor list. 1067 */ 1068 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1069 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1070 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, 1071 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1072 if (error) { 1073 device_printf(dev, "could not allocate dma tag\n"); 1074 return (ENOMEM); 1075 } 1076 1077 /* Allocate DMA'able memory for the TX ring */ 1078 1079 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1080 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1081 &sc->rl_ldata.rl_tx_list_map); 1082 if (error) 1083 return (ENOMEM); 1084 1085 /* Load the map for the TX ring. */ 1086 1087 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1088 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1089 RL_TX_LIST_SZ, re_dma_map_addr, 1090 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1091 1092 /* Create DMA maps for TX buffers */ 1093 1094 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1095 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1096 &sc->rl_ldata.rl_tx_dmamap[i]); 1097 if (error) { 1098 device_printf(dev, "can't create DMA map for TX\n"); 1099 return (ENOMEM); 1100 } 1101 } 1102 1103 /* 1104 * Allocate map for RX descriptor list. 1105 */ 1106 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1107 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1108 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, 0, 1109 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1110 if (error) { 1111 device_printf(dev, "could not allocate dma tag\n"); 1112 return (ENOMEM); 1113 } 1114 1115 /* Allocate DMA'able memory for the RX ring */ 1116 1117 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1118 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1119 &sc->rl_ldata.rl_rx_list_map); 1120 if (error) 1121 return (ENOMEM); 1122 1123 /* Load the map for the RX ring. */ 1124 1125 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1126 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1127 RL_RX_LIST_SZ, re_dma_map_addr, 1128 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1129 1130 /* Create DMA maps for RX buffers */ 1131 1132 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1133 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1134 &sc->rl_ldata.rl_rx_dmamap[i]); 1135 if (error) { 1136 device_printf(dev, "can't create DMA map for RX\n"); 1137 return (ENOMEM); 1138 } 1139 } 1140 1141 return (0); 1142} 1143 1144/* 1145 * Attach the interface. Allocate softc structures, do ifmedia 1146 * setup and ethernet/BPF attach. 1147 */ 1148static int 1149re_attach(dev) 1150 device_t dev; 1151{ 1152 u_char eaddr[ETHER_ADDR_LEN]; 1153 u_int16_t as[ETHER_ADDR_LEN / 2]; 1154 struct rl_softc *sc; 1155 struct ifnet *ifp; 1156 struct rl_hwrev *hw_rev; 1157 int hwrev; 1158 u_int16_t re_did = 0; 1159 int error = 0, rid, i; 1160 1161 sc = device_get_softc(dev); 1162 sc->rl_dev = dev; 1163 1164 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1165 MTX_DEF); 1166 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1167 1168 /* 1169 * Map control/status registers. 1170 */ 1171 pci_enable_busmaster(dev); 1172 1173 rid = RL_RID; 1174 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1175 RF_ACTIVE); 1176 1177 if (sc->rl_res == NULL) { 1178 device_printf(dev, "couldn't map ports/memory\n"); 1179 error = ENXIO; 1180 goto fail; 1181 } 1182 1183 sc->rl_btag = rman_get_bustag(sc->rl_res); 1184 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1185 1186 /* Allocate interrupt */ 1187 rid = 0; 1188 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1189 RF_SHAREABLE | RF_ACTIVE); 1190 1191 if (sc->rl_irq == NULL) { 1192 device_printf(dev, "couldn't map interrupt\n"); 1193 error = ENXIO; 1194 goto fail; 1195 } 1196 1197 /* Reset the adapter. */ 1198 RL_LOCK(sc); 1199 re_reset(sc); 1200 RL_UNLOCK(sc); 1201 1202 hw_rev = re_hwrevs; 1203 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1204 while (hw_rev->rl_desc != NULL) { 1205 if (hw_rev->rl_rev == hwrev) { 1206 sc->rl_type = hw_rev->rl_type; 1207 break; 1208 } 1209 hw_rev++; 1210 } 1211 1212 sc->rl_eewidth = 6; 1213 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1214 if (re_did != 0x8129) 1215 sc->rl_eewidth = 8; 1216 1217 /* 1218 * Get station address from the EEPROM. 1219 */ 1220 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1221 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1222 as[i] = le16toh(as[i]); 1223 bcopy(as, eaddr, sizeof(eaddr)); 1224 1225 if (sc->rl_type == RL_8169) { 1226 /* Set RX length mask */ 1227 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1228 sc->rl_txstart = RL_GTXSTART; 1229 } else { 1230 /* Set RX length mask */ 1231 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1232 sc->rl_txstart = RL_TXSTART; 1233 } 1234 1235 /* 1236 * Allocate the parent bus DMA tag appropriate for PCI. 1237 */ 1238#define RL_NSEG_NEW 32 1239 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1240 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1241 MAXBSIZE, RL_NSEG_NEW, BUS_SPACE_MAXSIZE_32BIT, 0, 1242 NULL, NULL, &sc->rl_parent_tag); 1243 if (error) 1244 goto fail; 1245 1246 error = re_allocmem(dev, sc); 1247 1248 if (error) 1249 goto fail; 1250 1251 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1252 if (ifp == NULL) { 1253 device_printf(dev, "can not if_alloc()\n"); 1254 error = ENOSPC; 1255 goto fail; 1256 } 1257 1258 /* Do MII setup */ 1259 if (mii_phy_probe(dev, &sc->rl_miibus, 1260 re_ifmedia_upd, re_ifmedia_sts)) { 1261 device_printf(dev, "MII without any phy!\n"); 1262 error = ENXIO; 1263 goto fail; 1264 } 1265 1266 ifp->if_softc = sc; 1267 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1268 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1269 ifp->if_ioctl = re_ioctl; 1270 ifp->if_start = re_start; 1271 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1272 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1273 ifp->if_capenable = ifp->if_capabilities; 1274 ifp->if_init = re_init; 1275 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1276 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1277 IFQ_SET_READY(&ifp->if_snd); 1278 1279 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1280 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1281 1282 /* 1283 * Call MI attach routine. 1284 */ 1285 ether_ifattach(ifp, eaddr); 1286 1287 /* VLAN capability setup */ 1288 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1289 if (ifp->if_capabilities & IFCAP_HWCSUM) 1290 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1291 ifp->if_capenable = ifp->if_capabilities; 1292#ifdef DEVICE_POLLING 1293 ifp->if_capabilities |= IFCAP_POLLING; 1294#endif 1295 /* 1296 * Tell the upper layer(s) we support long frames. 1297 * Must appear after the call to ether_ifattach() because 1298 * ether_ifattach() sets ifi_hdrlen to the default value. 1299 */ 1300 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1301 1302#ifdef RE_DIAG 1303 /* 1304 * Perform hardware diagnostic on the original RTL8169. 1305 * Some 32-bit cards were incorrectly wired and would 1306 * malfunction if plugged into a 64-bit slot. 1307 */ 1308 1309 if (hwrev == RL_HWREV_8169) { 1310 error = re_diag(sc); 1311 if (error) { 1312 device_printf(dev, 1313 "attach aborted due to hardware diag failure\n"); 1314 ether_ifdetach(ifp); 1315 goto fail; 1316 } 1317 } 1318#endif 1319 1320 /* Hook interrupt last to avoid having to lock softc */ 1321 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1322 re_intr, NULL, sc, &sc->rl_intrhand); 1323 if (error) { 1324 device_printf(dev, "couldn't set up irq\n"); 1325 ether_ifdetach(ifp); 1326 } 1327 1328fail: 1329 1330 if (error) 1331 re_detach(dev); 1332 1333 return (error); 1334} 1335 1336/* 1337 * Shutdown hardware and free up resources. This can be called any 1338 * time after the mutex has been initialized. It is called in both 1339 * the error case in attach and the normal detach case so it needs 1340 * to be careful about only freeing resources that have actually been 1341 * allocated. 1342 */ 1343static int 1344re_detach(dev) 1345 device_t dev; 1346{ 1347 struct rl_softc *sc; 1348 struct ifnet *ifp; 1349 int i; 1350 1351 sc = device_get_softc(dev); 1352 ifp = sc->rl_ifp; 1353 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1354 1355#ifdef DEVICE_POLLING 1356 if (ifp->if_capenable & IFCAP_POLLING) 1357 ether_poll_deregister(ifp); 1358#endif 1359 /* These should only be active if attach succeeded */ 1360 if (device_is_attached(dev)) { 1361 RL_LOCK(sc); 1362#if 0 1363 sc->suspended = 1; 1364#endif 1365 re_stop(sc); 1366 RL_UNLOCK(sc); 1367 callout_drain(&sc->rl_stat_callout); 1368 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1369 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1370 /* 1371 * Force off the IFF_UP flag here, in case someone 1372 * still had a BPF descriptor attached to this 1373 * interface. If they do, ether_ifdetach() will cause 1374 * the BPF code to try and clear the promisc mode 1375 * flag, which will bubble down to re_ioctl(), 1376 * which will try to call re_init() again. This will 1377 * turn the NIC back on and restart the MII ticker, 1378 * which will panic the system when the kernel tries 1379 * to invoke the re_tick() function that isn't there 1380 * anymore. 1381 */ 1382 ifp->if_flags &= ~IFF_UP; 1383 ether_ifdetach(ifp); 1384 } 1385 if (sc->rl_miibus) 1386 device_delete_child(dev, sc->rl_miibus); 1387 bus_generic_detach(dev); 1388 1389 /* 1390 * The rest is resource deallocation, so we should already be 1391 * stopped here. 1392 */ 1393 1394 if (sc->rl_intrhand) 1395 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1396 if (ifp != NULL) 1397 if_free(ifp); 1398 if (sc->rl_irq) 1399 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1400 if (sc->rl_res) 1401 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1402 1403 /* Unload and free the RX DMA ring memory and map */ 1404 1405 if (sc->rl_ldata.rl_rx_list_tag) { 1406 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1407 sc->rl_ldata.rl_rx_list_map); 1408 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1409 sc->rl_ldata.rl_rx_list, 1410 sc->rl_ldata.rl_rx_list_map); 1411 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1412 } 1413 1414 /* Unload and free the TX DMA ring memory and map */ 1415 1416 if (sc->rl_ldata.rl_tx_list_tag) { 1417 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1418 sc->rl_ldata.rl_tx_list_map); 1419 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1420 sc->rl_ldata.rl_tx_list, 1421 sc->rl_ldata.rl_tx_list_map); 1422 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1423 } 1424 1425 /* Destroy all the RX and TX buffer maps */ 1426 1427 if (sc->rl_ldata.rl_mtag) { 1428 for (i = 0; i < RL_TX_DESC_CNT; i++) 1429 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1430 sc->rl_ldata.rl_tx_dmamap[i]); 1431 for (i = 0; i < RL_RX_DESC_CNT; i++) 1432 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1433 sc->rl_ldata.rl_rx_dmamap[i]); 1434 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1435 } 1436 1437 /* Unload and free the stats buffer and map */ 1438 1439 if (sc->rl_ldata.rl_stag) { 1440 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1441 sc->rl_ldata.rl_rx_list_map); 1442 bus_dmamem_free(sc->rl_ldata.rl_stag, 1443 sc->rl_ldata.rl_stats, 1444 sc->rl_ldata.rl_smap); 1445 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1446 } 1447 1448 if (sc->rl_parent_tag) 1449 bus_dma_tag_destroy(sc->rl_parent_tag); 1450 1451 mtx_destroy(&sc->rl_mtx); 1452 1453 return (0); 1454} 1455 1456static int 1457re_newbuf(sc, idx, m) 1458 struct rl_softc *sc; 1459 int idx; 1460 struct mbuf *m; 1461{ 1462 struct rl_dmaload_arg arg; 1463 struct mbuf *n = NULL; 1464 int error; 1465 1466 if (m == NULL) { 1467 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1468 if (n == NULL) 1469 return (ENOBUFS); 1470 m = n; 1471 } else 1472 m->m_data = m->m_ext.ext_buf; 1473 1474 m->m_len = m->m_pkthdr.len = MCLBYTES; 1475#ifdef RE_FIXUP_RX 1476 /* 1477 * This is part of an evil trick to deal with non-x86 platforms. 1478 * The RealTek chip requires RX buffers to be aligned on 64-bit 1479 * boundaries, but that will hose non-x86 machines. To get around 1480 * this, we leave some empty space at the start of each buffer 1481 * and for non-x86 hosts, we copy the buffer back six bytes 1482 * to achieve word alignment. This is slightly more efficient 1483 * than allocating a new buffer, copying the contents, and 1484 * discarding the old buffer. 1485 */ 1486 m_adj(m, RE_ETHER_ALIGN); 1487#endif 1488 arg.rl_idx = idx; 1489 arg.rl_maxsegs = 1; 1490 arg.rl_flags = 0; 1491 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1492 1493 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1494 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1495 &arg, BUS_DMA_NOWAIT); 1496 if (error || arg.rl_maxsegs != 1) { 1497 if (n != NULL) 1498 m_freem(n); 1499 if (arg.rl_maxsegs == 0) 1500 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1501 sc->rl_ldata.rl_rx_dmamap[idx]); 1502 return (ENOMEM); 1503 } 1504 1505 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1506 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1507 1508 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1509 sc->rl_ldata.rl_rx_dmamap[idx], 1510 BUS_DMASYNC_PREREAD); 1511 1512 return (0); 1513} 1514 1515#ifdef RE_FIXUP_RX 1516static __inline void 1517re_fixup_rx(m) 1518 struct mbuf *m; 1519{ 1520 int i; 1521 uint16_t *src, *dst; 1522 1523 src = mtod(m, uint16_t *); 1524 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1525 1526 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1527 *dst++ = *src++; 1528 1529 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1530 1531 return; 1532} 1533#endif 1534 1535static int 1536re_tx_list_init(sc) 1537 struct rl_softc *sc; 1538{ 1539 1540 RL_LOCK_ASSERT(sc); 1541 1542 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1543 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1544 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1545 1546 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1547 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1548 sc->rl_ldata.rl_tx_prodidx = 0; 1549 sc->rl_ldata.rl_tx_considx = 0; 1550 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1551 1552 return (0); 1553} 1554 1555static int 1556re_rx_list_init(sc) 1557 struct rl_softc *sc; 1558{ 1559 int i; 1560 1561 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1562 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1563 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1564 1565 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1566 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1567 return (ENOBUFS); 1568 } 1569 1570 /* Flush the RX descriptors */ 1571 1572 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1573 sc->rl_ldata.rl_rx_list_map, 1574 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1575 1576 sc->rl_ldata.rl_rx_prodidx = 0; 1577 sc->rl_head = sc->rl_tail = NULL; 1578 1579 return (0); 1580} 1581 1582/* 1583 * RX handler for C+ and 8169. For the gigE chips, we support 1584 * the reception of jumbo frames that have been fragmented 1585 * across multiple 2K mbuf cluster buffers. 1586 */ 1587static int 1588re_rxeof(sc) 1589 struct rl_softc *sc; 1590{ 1591 struct mbuf *m; 1592 struct ifnet *ifp; 1593 int i, total_len; 1594 struct rl_desc *cur_rx; 1595 u_int32_t rxstat, rxvlan; 1596 int maxpkt = 16; 1597 1598 RL_LOCK_ASSERT(sc); 1599 1600 ifp = sc->rl_ifp; 1601 i = sc->rl_ldata.rl_rx_prodidx; 1602 1603 /* Invalidate the descriptor memory */ 1604 1605 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1606 sc->rl_ldata.rl_rx_list_map, 1607 BUS_DMASYNC_POSTREAD); 1608 1609 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) { 1610 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1611 m = sc->rl_ldata.rl_rx_mbuf[i]; 1612 total_len = RL_RXBYTES(cur_rx); 1613 rxstat = le32toh(cur_rx->rl_cmdstat); 1614 rxvlan = le32toh(cur_rx->rl_vlanctl); 1615 1616 /* Invalidate the RX mbuf and unload its map */ 1617 1618 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1619 sc->rl_ldata.rl_rx_dmamap[i], 1620 BUS_DMASYNC_POSTWRITE); 1621 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1622 sc->rl_ldata.rl_rx_dmamap[i]); 1623 1624 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1625 m->m_len = RE_RX_DESC_BUFLEN; 1626 if (sc->rl_head == NULL) 1627 sc->rl_head = sc->rl_tail = m; 1628 else { 1629 m->m_flags &= ~M_PKTHDR; 1630 sc->rl_tail->m_next = m; 1631 sc->rl_tail = m; 1632 } 1633 re_newbuf(sc, i, NULL); 1634 RL_DESC_INC(i); 1635 continue; 1636 } 1637 1638 /* 1639 * NOTE: for the 8139C+, the frame length field 1640 * is always 12 bits in size, but for the gigE chips, 1641 * it is 13 bits (since the max RX frame length is 16K). 1642 * Unfortunately, all 32 bits in the status word 1643 * were already used, so to make room for the extra 1644 * length bit, RealTek took out the 'frame alignment 1645 * error' bit and shifted the other status bits 1646 * over one slot. The OWN, EOR, FS and LS bits are 1647 * still in the same places. We have already extracted 1648 * the frame length and checked the OWN bit, so rather 1649 * than using an alternate bit mapping, we shift the 1650 * status bits one space to the right so we can evaluate 1651 * them using the 8169 status as though it was in the 1652 * same format as that of the 8139C+. 1653 */ 1654 if (sc->rl_type == RL_8169) 1655 rxstat >>= 1; 1656 1657 /* 1658 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1659 * set, but if CRC is clear, it will still be a valid frame. 1660 */ 1661 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1662 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1663 ifp->if_ierrors++; 1664 /* 1665 * If this is part of a multi-fragment packet, 1666 * discard all the pieces. 1667 */ 1668 if (sc->rl_head != NULL) { 1669 m_freem(sc->rl_head); 1670 sc->rl_head = sc->rl_tail = NULL; 1671 } 1672 re_newbuf(sc, i, m); 1673 RL_DESC_INC(i); 1674 continue; 1675 } 1676 1677 /* 1678 * If allocating a replacement mbuf fails, 1679 * reload the current one. 1680 */ 1681 1682 if (re_newbuf(sc, i, NULL)) { 1683 ifp->if_ierrors++; 1684 if (sc->rl_head != NULL) { 1685 m_freem(sc->rl_head); 1686 sc->rl_head = sc->rl_tail = NULL; 1687 } 1688 re_newbuf(sc, i, m); 1689 RL_DESC_INC(i); 1690 continue; 1691 } 1692 1693 RL_DESC_INC(i); 1694 1695 if (sc->rl_head != NULL) { 1696 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1697 if (m->m_len == 0) 1698 m->m_len = RE_RX_DESC_BUFLEN; 1699 /* 1700 * Special case: if there's 4 bytes or less 1701 * in this buffer, the mbuf can be discarded: 1702 * the last 4 bytes is the CRC, which we don't 1703 * care about anyway. 1704 */ 1705 if (m->m_len <= ETHER_CRC_LEN) { 1706 sc->rl_tail->m_len -= 1707 (ETHER_CRC_LEN - m->m_len); 1708 m_freem(m); 1709 } else { 1710 m->m_len -= ETHER_CRC_LEN; 1711 m->m_flags &= ~M_PKTHDR; 1712 sc->rl_tail->m_next = m; 1713 } 1714 m = sc->rl_head; 1715 sc->rl_head = sc->rl_tail = NULL; 1716 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1717 } else 1718 m->m_pkthdr.len = m->m_len = 1719 (total_len - ETHER_CRC_LEN); 1720 1721#ifdef RE_FIXUP_RX 1722 re_fixup_rx(m); 1723#endif 1724 ifp->if_ipackets++; 1725 m->m_pkthdr.rcvif = ifp; 1726 1727 /* Do RX checksumming if enabled */ 1728 1729 if (ifp->if_capenable & IFCAP_RXCSUM) { 1730 1731 /* Check IP header checksum */ 1732 if (rxstat & RL_RDESC_STAT_PROTOID) 1733 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1734 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1735 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1736 1737 /* Check TCP/UDP checksum */ 1738 if ((RL_TCPPKT(rxstat) && 1739 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1740 (RL_UDPPKT(rxstat) && 1741 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1742 m->m_pkthdr.csum_flags |= 1743 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1744 m->m_pkthdr.csum_data = 0xffff; 1745 } 1746 } 1747 maxpkt--; 1748 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1749 m->m_pkthdr.ether_vtag = 1750 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1751 m->m_flags |= M_VLANTAG; 1752 } 1753 RL_UNLOCK(sc); 1754 (*ifp->if_input)(ifp, m); 1755 RL_LOCK(sc); 1756 } 1757 1758 /* Flush the RX DMA ring */ 1759 1760 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1761 sc->rl_ldata.rl_rx_list_map, 1762 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1763 1764 sc->rl_ldata.rl_rx_prodidx = i; 1765 1766 if (maxpkt) 1767 return(EAGAIN); 1768 1769 return(0); 1770} 1771 1772static void 1773re_txeof(sc) 1774 struct rl_softc *sc; 1775{ 1776 struct ifnet *ifp; 1777 u_int32_t txstat; 1778 int idx; 1779 1780 ifp = sc->rl_ifp; 1781 idx = sc->rl_ldata.rl_tx_considx; 1782 1783 /* Invalidate the TX descriptor list */ 1784 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1785 sc->rl_ldata.rl_tx_list_map, 1786 BUS_DMASYNC_POSTREAD); 1787 1788 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1789 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1790 if (txstat & RL_TDESC_CMD_OWN) 1791 break; 1792 1793 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0; 1794 1795 /* 1796 * We only stash mbufs in the last descriptor 1797 * in a fragment chain, which also happens to 1798 * be the only place where the TX status bits 1799 * are valid. 1800 */ 1801 if (txstat & RL_TDESC_CMD_EOF) { 1802 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1803 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1804 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1805 sc->rl_ldata.rl_tx_dmamap[idx]); 1806 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1807 RL_TDESC_STAT_COLCNT)) 1808 ifp->if_collisions++; 1809 if (txstat & RL_TDESC_STAT_TXERRSUM) 1810 ifp->if_oerrors++; 1811 else 1812 ifp->if_opackets++; 1813 } 1814 sc->rl_ldata.rl_tx_free++; 1815 RL_DESC_INC(idx); 1816 } 1817 sc->rl_ldata.rl_tx_considx = idx; 1818 1819 /* No changes made to the TX ring, so no flush needed */ 1820 1821 if (sc->rl_ldata.rl_tx_free > RL_TX_DESC_THLD) 1822 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1823 1824 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1825 /* 1826 * Some chips will ignore a second TX request issued 1827 * while an existing transmission is in progress. If 1828 * the transmitter goes idle but there are still 1829 * packets waiting to be sent, we need to restart the 1830 * channel here to flush them out. This only seems to 1831 * be required with the PCIe devices. 1832 */ 1833 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1834 1835#ifdef RE_TX_MODERATION 1836 /* 1837 * If not all descriptors have been reaped yet, reload 1838 * the timer so that we will eventually get another 1839 * interrupt that will cause us to re-enter this routine. 1840 * This is done in case the transmitter has gone idle. 1841 */ 1842 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1843#endif 1844 } else 1845 sc->rl_watchdog_timer = 0; 1846} 1847 1848static void 1849re_tick(xsc) 1850 void *xsc; 1851{ 1852 struct rl_softc *sc; 1853 struct mii_data *mii; 1854 struct ifnet *ifp; 1855 1856 sc = xsc; 1857 ifp = sc->rl_ifp; 1858 1859 RL_LOCK_ASSERT(sc); 1860 1861 re_watchdog(sc); 1862 1863 mii = device_get_softc(sc->rl_miibus); 1864 mii_tick(mii); 1865 if (sc->rl_link) { 1866 if (!(mii->mii_media_status & IFM_ACTIVE)) 1867 sc->rl_link = 0; 1868 } else { 1869 if (mii->mii_media_status & IFM_ACTIVE && 1870 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1871 sc->rl_link = 1; 1872 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1873 taskqueue_enqueue_fast(taskqueue_fast, 1874 &sc->rl_txtask); 1875 } 1876 } 1877 1878 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1879} 1880 1881#ifdef DEVICE_POLLING 1882static void 1883re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1884{ 1885 struct rl_softc *sc = ifp->if_softc; 1886 1887 RL_LOCK(sc); 1888 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1889 re_poll_locked(ifp, cmd, count); 1890 RL_UNLOCK(sc); 1891} 1892 1893static void 1894re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1895{ 1896 struct rl_softc *sc = ifp->if_softc; 1897 1898 RL_LOCK_ASSERT(sc); 1899 1900 sc->rxcycles = count; 1901 re_rxeof(sc); 1902 re_txeof(sc); 1903 1904 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1905 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 1906 1907 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1908 u_int16_t status; 1909 1910 status = CSR_READ_2(sc, RL_ISR); 1911 if (status == 0xffff) 1912 return; 1913 if (status) 1914 CSR_WRITE_2(sc, RL_ISR, status); 1915 1916 /* 1917 * XXX check behaviour on receiver stalls. 1918 */ 1919 1920 if (status & RL_ISR_SYSTEM_ERR) { 1921 re_reset(sc); 1922 re_init_locked(sc); 1923 } 1924 } 1925} 1926#endif /* DEVICE_POLLING */ 1927 1928static int 1929re_intr(arg) 1930 void *arg; 1931{ 1932 struct rl_softc *sc; 1933 uint16_t status; 1934 1935 sc = arg; 1936 1937 status = CSR_READ_2(sc, RL_ISR); 1938 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 1939 return (FILTER_STRAY); 1940 CSR_WRITE_2(sc, RL_IMR, 0); 1941 1942 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 1943 1944 return (FILTER_HANDLED); 1945} 1946 1947static void 1948re_int_task(arg, npending) 1949 void *arg; 1950 int npending; 1951{ 1952 struct rl_softc *sc; 1953 struct ifnet *ifp; 1954 u_int16_t status; 1955 int rval = 0; 1956 1957 sc = arg; 1958 ifp = sc->rl_ifp; 1959 1960 RL_LOCK(sc); 1961 1962 status = CSR_READ_2(sc, RL_ISR); 1963 CSR_WRITE_2(sc, RL_ISR, status); 1964 1965 if (sc->suspended || !(ifp->if_flags & IFF_UP)) { 1966 RL_UNLOCK(sc); 1967 return; 1968 } 1969 1970#ifdef DEVICE_POLLING 1971 if (ifp->if_capenable & IFCAP_POLLING) { 1972 RL_UNLOCK(sc); 1973 return; 1974 } 1975#endif 1976 1977 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 1978 rval = re_rxeof(sc); 1979 1980#ifdef RE_TX_MODERATION 1981 if (status & (RL_ISR_TIMEOUT_EXPIRED| 1982#else 1983 if (status & (RL_ISR_TX_OK| 1984#endif 1985 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 1986 re_txeof(sc); 1987 1988 if (status & RL_ISR_SYSTEM_ERR) { 1989 re_reset(sc); 1990 re_init_locked(sc); 1991 } 1992 1993 if (status & RL_ISR_LINKCHG) { 1994 callout_stop(&sc->rl_stat_callout); 1995 re_tick(sc); 1996 } 1997 1998 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1999 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2000 2001 RL_UNLOCK(sc); 2002 2003 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2004 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2005 return; 2006 } 2007 2008 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2009 2010 return; 2011} 2012 2013static int 2014re_encap(sc, m_head, idx) 2015 struct rl_softc *sc; 2016 struct mbuf **m_head; 2017 int *idx; 2018{ 2019 struct mbuf *m_new = NULL; 2020 struct rl_dmaload_arg arg; 2021 bus_dmamap_t map; 2022 int error; 2023 2024 RL_LOCK_ASSERT(sc); 2025 2026 if (sc->rl_ldata.rl_tx_free <= RL_TX_DESC_THLD) 2027 return (EFBIG); 2028 2029 /* 2030 * Set up checksum offload. Note: checksum offload bits must 2031 * appear in all descriptors of a multi-descriptor transmit 2032 * attempt. This is according to testing done with an 8169 2033 * chip. This is a requirement. 2034 */ 2035 2036 arg.rl_flags = 0; 2037 2038 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2039 arg.rl_flags = RL_TDESC_CMD_LGSEND | 2040 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2041 RL_TDESC_CMD_MSSVAL_SHIFT); 2042 else { 2043 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2044 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 2045 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2046 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 2047 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2048 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 2049 } 2050 2051 arg.rl_idx = *idx; 2052 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2053 if (arg.rl_maxsegs > RL_TX_DESC_THLD) 2054 arg.rl_maxsegs -= RL_TX_DESC_THLD; 2055 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2056 2057 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 2058 2059 /* 2060 * With some of the RealTek chips, using the checksum offload 2061 * support in conjunction with the autopadding feature results 2062 * in the transmission of corrupt frames. For example, if we 2063 * need to send a really small IP fragment that's less than 60 2064 * bytes in size, and IP header checksumming is enabled, the 2065 * resulting ethernet frame that appears on the wire will 2066 * have garbled payload. To work around this, if TX checksum 2067 * offload is enabled, we always manually pad short frames out 2068 * to the minimum ethernet frame size. We do this by pretending 2069 * the mbuf chain has too many fragments so the coalescing code 2070 * below can assemble the packet into a single buffer that's 2071 * padded out to the mininum frame size. 2072 * 2073 * Note: this appears unnecessary for TCP, and doing it for TCP 2074 * with PCIe adapters seems to result in bad checksums. 2075 */ 2076 2077 if (arg.rl_flags && !(arg.rl_flags & RL_TDESC_CMD_TCPCSUM) && 2078 (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) 2079 error = EFBIG; 2080 else 2081 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2082 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2083 2084 if (error && error != EFBIG) { 2085 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", error); 2086 return (ENOBUFS); 2087 } 2088 2089 /* Too many segments to map, coalesce into a single mbuf */ 2090 2091 if (error || arg.rl_maxsegs == 0) { 2092 if (arg.rl_maxsegs == 0) 2093 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map); 2094 m_new = m_defrag(*m_head, M_DONTWAIT); 2095 if (m_new == NULL) { 2096 m_freem(*m_head); 2097 *m_head = NULL; 2098 return (ENOBUFS); 2099 } 2100 *m_head = m_new; 2101 2102 /* 2103 * Manually pad short frames, and zero the pad space 2104 * to avoid leaking data. 2105 */ 2106 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) { 2107 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 2108 RL_MIN_FRAMELEN - m_new->m_pkthdr.len); 2109 m_new->m_pkthdr.len += RL_MIN_FRAMELEN - 2110 m_new->m_pkthdr.len; 2111 m_new->m_len = m_new->m_pkthdr.len; 2112 } 2113 2114 /* Note that we'll run over RL_TX_DESC_THLD here. */ 2115 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2116 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2117 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2118 if (error || arg.rl_maxsegs == 0) { 2119 device_printf(sc->rl_dev, 2120 "can't map defragmented mbuf (error %d)\n", error); 2121 m_freem(m_new); 2122 *m_head = NULL; 2123 if (arg.rl_maxsegs == 0) 2124 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map); 2125 return (EFBIG); 2126 } 2127 } 2128 2129 /* 2130 * Insure that the map for this transmission 2131 * is placed at the array index of the last descriptor 2132 * in this chain. (Swap last and first dmamaps.) 2133 */ 2134 sc->rl_ldata.rl_tx_dmamap[*idx] = 2135 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 2136 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 2137 2138 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 2139 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 2140 2141 /* 2142 * Set up hardware VLAN tagging. Note: vlan tag info must 2143 * appear in the first descriptor of a multi-descriptor 2144 * transmission attempt. 2145 */ 2146 if ((*m_head)->m_flags & M_VLANTAG) 2147 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 2148 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2149 RL_TDESC_VLANCTL_TAG); 2150 2151 /* Transfer ownership of packet to the chip. */ 2152 2153 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 2154 htole32(RL_TDESC_CMD_OWN); 2155 if (*idx != arg.rl_idx) 2156 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 2157 htole32(RL_TDESC_CMD_OWN); 2158 2159 RL_DESC_INC(arg.rl_idx); 2160 *idx = arg.rl_idx; 2161 2162 return (0); 2163} 2164 2165static void 2166re_tx_task(arg, npending) 2167 void *arg; 2168 int npending; 2169{ 2170 struct ifnet *ifp; 2171 2172 ifp = arg; 2173 re_start(ifp); 2174 2175 return; 2176} 2177 2178/* 2179 * Main transmit routine for C+ and gigE NICs. 2180 */ 2181static void 2182re_start(ifp) 2183 struct ifnet *ifp; 2184{ 2185 struct rl_softc *sc; 2186 struct mbuf *m_head = NULL; 2187 int idx, queued = 0; 2188 2189 sc = ifp->if_softc; 2190 2191 RL_LOCK(sc); 2192 2193 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 2194 RL_UNLOCK(sc); 2195 return; 2196 } 2197 2198 idx = sc->rl_ldata.rl_tx_prodidx; 2199 2200 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2201 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2202 if (m_head == NULL) 2203 break; 2204 2205 if (re_encap(sc, &m_head, &idx)) { 2206 if (m_head == NULL) 2207 break; 2208 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2209 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2210 break; 2211 } 2212 2213 /* 2214 * If there's a BPF listener, bounce a copy of this frame 2215 * to him. 2216 */ 2217 ETHER_BPF_MTAP(ifp, m_head); 2218 2219 queued++; 2220 } 2221 2222 if (queued == 0) { 2223#ifdef RE_TX_MODERATION 2224 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 2225 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2226#endif 2227 RL_UNLOCK(sc); 2228 return; 2229 } 2230 2231 /* Flush the TX descriptors */ 2232 2233 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2234 sc->rl_ldata.rl_tx_list_map, 2235 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2236 2237 sc->rl_ldata.rl_tx_prodidx = idx; 2238 2239 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2240 2241#ifdef RE_TX_MODERATION 2242 /* 2243 * Use the countdown timer for interrupt moderation. 2244 * 'TX done' interrupts are disabled. Instead, we reset the 2245 * countdown timer, which will begin counting until it hits 2246 * the value in the TIMERINT register, and then trigger an 2247 * interrupt. Each time we write to the TIMERCNT register, 2248 * the timer count is reset to 0. 2249 */ 2250 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2251#endif 2252 2253 /* 2254 * Set a timeout in case the chip goes out to lunch. 2255 */ 2256 sc->rl_watchdog_timer = 5; 2257 2258 RL_UNLOCK(sc); 2259 2260 return; 2261} 2262 2263static void 2264re_init(xsc) 2265 void *xsc; 2266{ 2267 struct rl_softc *sc = xsc; 2268 2269 RL_LOCK(sc); 2270 re_init_locked(sc); 2271 RL_UNLOCK(sc); 2272} 2273 2274static void 2275re_init_locked(sc) 2276 struct rl_softc *sc; 2277{ 2278 struct ifnet *ifp = sc->rl_ifp; 2279 struct mii_data *mii; 2280 u_int32_t rxcfg = 0; 2281 union { 2282 uint32_t align_dummy; 2283 u_char eaddr[ETHER_ADDR_LEN]; 2284 } eaddr; 2285 2286 RL_LOCK_ASSERT(sc); 2287 2288 mii = device_get_softc(sc->rl_miibus); 2289 2290 /* 2291 * Cancel pending I/O and free all RX/TX buffers. 2292 */ 2293 re_stop(sc); 2294 2295 /* 2296 * Enable C+ RX and TX mode, as well as VLAN stripping and 2297 * RX checksum offload. We must configure the C+ register 2298 * before all others. 2299 */ 2300 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2301 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2302 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB); 2303 2304 /* 2305 * Init our MAC address. Even though the chipset 2306 * documentation doesn't mention it, we need to enter "Config 2307 * register write enable" mode to modify the ID registers. 2308 */ 2309 /* Copy MAC address on stack to align. */ 2310 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2311 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2312 CSR_WRITE_4(sc, RL_IDR0, 2313 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2314 CSR_WRITE_4(sc, RL_IDR4, 2315 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2316 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2317 2318 /* 2319 * For C+ mode, initialize the RX descriptors and mbufs. 2320 */ 2321 re_rx_list_init(sc); 2322 re_tx_list_init(sc); 2323 2324 /* 2325 * Load the addresses of the RX and TX lists into the chip. 2326 */ 2327 2328 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2329 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2330 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2331 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2332 2333 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2334 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2335 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2336 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2337 2338 /* 2339 * Enable transmit and receive. 2340 */ 2341 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2342 2343 /* 2344 * Set the initial TX and RX configuration. 2345 */ 2346 if (sc->rl_testmode) { 2347 if (sc->rl_type == RL_8169) 2348 CSR_WRITE_4(sc, RL_TXCFG, 2349 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2350 else 2351 CSR_WRITE_4(sc, RL_TXCFG, 2352 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2353 } else 2354 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2355 2356 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2357 2358 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2359 2360 /* Set the individual bit to receive frames for this host only. */ 2361 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2362 rxcfg |= RL_RXCFG_RX_INDIV; 2363 2364 /* If we want promiscuous mode, set the allframes bit. */ 2365 if (ifp->if_flags & IFF_PROMISC) 2366 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2367 else 2368 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2369 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2370 2371 /* 2372 * Set capture broadcast bit to capture broadcast frames. 2373 */ 2374 if (ifp->if_flags & IFF_BROADCAST) 2375 rxcfg |= RL_RXCFG_RX_BROAD; 2376 else 2377 rxcfg &= ~RL_RXCFG_RX_BROAD; 2378 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2379 2380 /* 2381 * Program the multicast filter, if necessary. 2382 */ 2383 re_setmulti(sc); 2384 2385#ifdef DEVICE_POLLING 2386 /* 2387 * Disable interrupts if we are polling. 2388 */ 2389 if (ifp->if_capenable & IFCAP_POLLING) 2390 CSR_WRITE_2(sc, RL_IMR, 0); 2391 else /* otherwise ... */ 2392#endif 2393 2394 /* 2395 * Enable interrupts. 2396 */ 2397 if (sc->rl_testmode) 2398 CSR_WRITE_2(sc, RL_IMR, 0); 2399 else 2400 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2401 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2402 2403 /* Set initial TX threshold */ 2404 sc->rl_txthresh = RL_TX_THRESH_INIT; 2405 2406 /* Start RX/TX process. */ 2407 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2408#ifdef notdef 2409 /* Enable receiver and transmitter. */ 2410 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2411#endif 2412 2413#ifdef RE_TX_MODERATION 2414 /* 2415 * Initialize the timer interrupt register so that 2416 * a timer interrupt will be generated once the timer 2417 * reaches a certain number of ticks. The timer is 2418 * reloaded on each transmit. This gives us TX interrupt 2419 * moderation, which dramatically improves TX frame rate. 2420 */ 2421 if (sc->rl_type == RL_8169) 2422 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2423 else 2424 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2425#endif 2426 2427 /* 2428 * For 8169 gigE NICs, set the max allowed RX packet 2429 * size so we can receive jumbo frames. 2430 */ 2431 if (sc->rl_type == RL_8169) 2432 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2433 2434 if (sc->rl_testmode) 2435 return; 2436 2437 mii_mediachg(mii); 2438 2439 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2440 2441 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2442 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2443 2444 sc->rl_link = 0; 2445 sc->rl_watchdog_timer = 0; 2446 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2447} 2448 2449/* 2450 * Set media options. 2451 */ 2452static int 2453re_ifmedia_upd(ifp) 2454 struct ifnet *ifp; 2455{ 2456 struct rl_softc *sc; 2457 struct mii_data *mii; 2458 2459 sc = ifp->if_softc; 2460 mii = device_get_softc(sc->rl_miibus); 2461 RL_LOCK(sc); 2462 mii_mediachg(mii); 2463 RL_UNLOCK(sc); 2464 2465 return (0); 2466} 2467 2468/* 2469 * Report current media status. 2470 */ 2471static void 2472re_ifmedia_sts(ifp, ifmr) 2473 struct ifnet *ifp; 2474 struct ifmediareq *ifmr; 2475{ 2476 struct rl_softc *sc; 2477 struct mii_data *mii; 2478 2479 sc = ifp->if_softc; 2480 mii = device_get_softc(sc->rl_miibus); 2481 2482 RL_LOCK(sc); 2483 mii_pollstat(mii); 2484 RL_UNLOCK(sc); 2485 ifmr->ifm_active = mii->mii_media_active; 2486 ifmr->ifm_status = mii->mii_media_status; 2487} 2488 2489static int 2490re_ioctl(ifp, command, data) 2491 struct ifnet *ifp; 2492 u_long command; 2493 caddr_t data; 2494{ 2495 struct rl_softc *sc = ifp->if_softc; 2496 struct ifreq *ifr = (struct ifreq *) data; 2497 struct mii_data *mii; 2498 int error = 0; 2499 2500 switch (command) { 2501 case SIOCSIFMTU: 2502 RL_LOCK(sc); 2503 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2504 error = EINVAL; 2505 ifp->if_mtu = ifr->ifr_mtu; 2506 RL_UNLOCK(sc); 2507 break; 2508 case SIOCSIFFLAGS: 2509 RL_LOCK(sc); 2510 if (ifp->if_flags & IFF_UP) 2511 re_init_locked(sc); 2512 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2513 re_stop(sc); 2514 RL_UNLOCK(sc); 2515 break; 2516 case SIOCADDMULTI: 2517 case SIOCDELMULTI: 2518 RL_LOCK(sc); 2519 re_setmulti(sc); 2520 RL_UNLOCK(sc); 2521 break; 2522 case SIOCGIFMEDIA: 2523 case SIOCSIFMEDIA: 2524 mii = device_get_softc(sc->rl_miibus); 2525 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2526 break; 2527 case SIOCSIFCAP: 2528 { 2529 int mask, reinit; 2530 2531 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2532 reinit = 0; 2533#ifdef DEVICE_POLLING 2534 if (mask & IFCAP_POLLING) { 2535 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2536 error = ether_poll_register(re_poll, ifp); 2537 if (error) 2538 return(error); 2539 RL_LOCK(sc); 2540 /* Disable interrupts */ 2541 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2542 ifp->if_capenable |= IFCAP_POLLING; 2543 RL_UNLOCK(sc); 2544 } else { 2545 error = ether_poll_deregister(ifp); 2546 /* Enable interrupts. */ 2547 RL_LOCK(sc); 2548 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2549 ifp->if_capenable &= ~IFCAP_POLLING; 2550 RL_UNLOCK(sc); 2551 } 2552 } 2553#endif /* DEVICE_POLLING */ 2554 if (mask & IFCAP_HWCSUM) { 2555 ifp->if_capenable ^= IFCAP_HWCSUM; 2556 if (ifp->if_capenable & IFCAP_TXCSUM) 2557 ifp->if_hwassist |= RE_CSUM_FEATURES; 2558 else 2559 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2560 reinit = 1; 2561 } 2562 if (mask & IFCAP_VLAN_HWTAGGING) { 2563 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2564 reinit = 1; 2565 } 2566 if (mask & IFCAP_TSO4) { 2567 ifp->if_capenable ^= IFCAP_TSO4; 2568 if ((IFCAP_TSO4 & ifp->if_capenable) && 2569 (IFCAP_TSO4 & ifp->if_capabilities)) 2570 ifp->if_hwassist |= CSUM_TSO; 2571 else 2572 ifp->if_hwassist &= ~CSUM_TSO; 2573 } 2574 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2575 re_init(sc); 2576 VLAN_CAPABILITIES(ifp); 2577 } 2578 break; 2579 default: 2580 error = ether_ioctl(ifp, command, data); 2581 break; 2582 } 2583 2584 return (error); 2585} 2586 2587static void 2588re_watchdog(sc) 2589 struct rl_softc *sc; 2590{ 2591 2592 RL_LOCK_ASSERT(sc); 2593 2594 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2595 return; 2596 2597 device_printf(sc->rl_dev, "watchdog timeout\n"); 2598 sc->rl_ifp->if_oerrors++; 2599 2600 re_txeof(sc); 2601 re_rxeof(sc); 2602 re_init_locked(sc); 2603} 2604 2605/* 2606 * Stop the adapter and free any mbufs allocated to the 2607 * RX and TX lists. 2608 */ 2609static void 2610re_stop(sc) 2611 struct rl_softc *sc; 2612{ 2613 register int i; 2614 struct ifnet *ifp; 2615 2616 RL_LOCK_ASSERT(sc); 2617 2618 ifp = sc->rl_ifp; 2619 2620 sc->rl_watchdog_timer = 0; 2621 callout_stop(&sc->rl_stat_callout); 2622 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2623 2624 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2625 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2626 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2627 2628 if (sc->rl_head != NULL) { 2629 m_freem(sc->rl_head); 2630 sc->rl_head = sc->rl_tail = NULL; 2631 } 2632 2633 /* Free the TX list buffers. */ 2634 2635 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2636 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2637 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2638 sc->rl_ldata.rl_tx_dmamap[i]); 2639 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2640 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2641 } 2642 } 2643 2644 /* Free the RX list buffers. */ 2645 2646 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2647 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2648 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2649 sc->rl_ldata.rl_rx_dmamap[i]); 2650 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2651 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2652 } 2653 } 2654} 2655 2656/* 2657 * Device suspend routine. Stop the interface and save some PCI 2658 * settings in case the BIOS doesn't restore them properly on 2659 * resume. 2660 */ 2661static int 2662re_suspend(dev) 2663 device_t dev; 2664{ 2665 struct rl_softc *sc; 2666 2667 sc = device_get_softc(dev); 2668 2669 RL_LOCK(sc); 2670 re_stop(sc); 2671 sc->suspended = 1; 2672 RL_UNLOCK(sc); 2673 2674 return (0); 2675} 2676 2677/* 2678 * Device resume routine. Restore some PCI settings in case the BIOS 2679 * doesn't, re-enable busmastering, and restart the interface if 2680 * appropriate. 2681 */ 2682static int 2683re_resume(dev) 2684 device_t dev; 2685{ 2686 struct rl_softc *sc; 2687 struct ifnet *ifp; 2688 2689 sc = device_get_softc(dev); 2690 2691 RL_LOCK(sc); 2692 2693 ifp = sc->rl_ifp; 2694 2695 /* reinitialize interface if necessary */ 2696 if (ifp->if_flags & IFF_UP) 2697 re_init_locked(sc); 2698 2699 sc->suspended = 0; 2700 RL_UNLOCK(sc); 2701 2702 return (0); 2703} 2704 2705/* 2706 * Stop all chip I/O so that the kernel's probe routines don't 2707 * get confused by errant DMAs when rebooting. 2708 */ 2709static void 2710re_shutdown(dev) 2711 device_t dev; 2712{ 2713 struct rl_softc *sc; 2714 2715 sc = device_get_softc(dev); 2716 2717 RL_LOCK(sc); 2718 re_stop(sc); 2719 /* 2720 * Mark interface as down since otherwise we will panic if 2721 * interrupt comes in later on, which can happen in some 2722 * cases. 2723 */ 2724 sc->rl_ifp->if_flags &= ~IFF_UP; 2725 RL_UNLOCK(sc); 2726} 2727