if_re.c revision 164465
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 164465 2006-11-21 05:41:11Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149MODULE_DEPEND(re, pci, 1, 1, 1); 150MODULE_DEPEND(re, ether, 1, 1, 1); 151MODULE_DEPEND(re, miibus, 1, 1, 1); 152 153/* "device miibus" required. See GENERIC if you get errors here. */ 154#include "miibus_if.h" 155 156/* 157 * Default to using PIO access for this driver. 158 */ 159#define RE_USEIOSPACE 160 161#include <pci/if_rlreg.h> 162 163#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 164 165/* 166 * Various supported device vendors/types and their names. 167 */ 168static struct rl_type re_devs[] = { 169 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 171 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 172 "RealTek 8139C+ 10/100BaseTX" }, 173 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 174 "RealTek 8101E PCIe 10/100baseTX" }, 175 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 176 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 178 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 180 "RealTek 8169 Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 182 "RealTek 8169S Single-chip Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 184 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 186 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 188 "RealTek 8110S Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }, 195 { 0, 0, 0, NULL } 196}; 197 198static struct rl_hwrev re_hwrevs[] = { 199 { RL_HWREV_8139, RL_8139, "" }, 200 { RL_HWREV_8139A, RL_8139, "A" }, 201 { RL_HWREV_8139AG, RL_8139, "A-G" }, 202 { RL_HWREV_8139B, RL_8139, "B" }, 203 { RL_HWREV_8130, RL_8139, "8130" }, 204 { RL_HWREV_8139C, RL_8139, "C" }, 205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 207 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 208 { RL_HWREV_8169, RL_8169, "8169"}, 209 { RL_HWREV_8169S, RL_8169, "8169S"}, 210 { RL_HWREV_8110S, RL_8169, "8110S"}, 211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 213 { RL_HWREV_8100, RL_8139, "8100"}, 214 { RL_HWREV_8101, RL_8139, "8101"}, 215 { RL_HWREV_8100E, RL_8169, "8100E"}, 216 { RL_HWREV_8101E, RL_8169, "8101E"}, 217 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 218 { 0, 0, NULL } 219}; 220 221static int re_probe (device_t); 222static int re_attach (device_t); 223static int re_detach (device_t); 224 225static int re_encap (struct rl_softc *, struct mbuf **, int *); 226 227static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 228static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 229 bus_size_t, int); 230static int re_allocmem (device_t, struct rl_softc *); 231static int re_newbuf (struct rl_softc *, int, struct mbuf *); 232static int re_rx_list_init (struct rl_softc *); 233static int re_tx_list_init (struct rl_softc *); 234#ifdef RE_FIXUP_RX 235static __inline void re_fixup_rx 236 (struct mbuf *); 237#endif 238static int re_rxeof (struct rl_softc *); 239static void re_txeof (struct rl_softc *); 240#ifdef DEVICE_POLLING 241static void re_poll (struct ifnet *, enum poll_cmd, int); 242static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 243#endif 244static void re_intr (void *); 245static void re_tick (void *); 246static void re_tx_task (void *, int); 247static void re_int_task (void *, int); 248static void re_start (struct ifnet *); 249static int re_ioctl (struct ifnet *, u_long, caddr_t); 250static void re_init (void *); 251static void re_init_locked (struct rl_softc *); 252static void re_stop (struct rl_softc *); 253static void re_watchdog (struct ifnet *); 254static int re_suspend (device_t); 255static int re_resume (device_t); 256static void re_shutdown (device_t); 257static int re_ifmedia_upd (struct ifnet *); 258static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 259 260static void re_eeprom_putbyte (struct rl_softc *, int); 261static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 262static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 263static int re_gmii_readreg (device_t, int, int); 264static int re_gmii_writereg (device_t, int, int, int); 265 266static int re_miibus_readreg (device_t, int, int); 267static int re_miibus_writereg (device_t, int, int, int); 268static void re_miibus_statchg (device_t); 269 270static void re_setmulti (struct rl_softc *); 271static void re_reset (struct rl_softc *); 272 273#ifdef RE_DIAG 274static int re_diag (struct rl_softc *); 275#endif 276 277#ifdef RE_USEIOSPACE 278#define RL_RES SYS_RES_IOPORT 279#define RL_RID RL_PCI_LOIO 280#else 281#define RL_RES SYS_RES_MEMORY 282#define RL_RID RL_PCI_LOMEM 283#endif 284 285static device_method_t re_methods[] = { 286 /* Device interface */ 287 DEVMETHOD(device_probe, re_probe), 288 DEVMETHOD(device_attach, re_attach), 289 DEVMETHOD(device_detach, re_detach), 290 DEVMETHOD(device_suspend, re_suspend), 291 DEVMETHOD(device_resume, re_resume), 292 DEVMETHOD(device_shutdown, re_shutdown), 293 294 /* bus interface */ 295 DEVMETHOD(bus_print_child, bus_generic_print_child), 296 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 297 298 /* MII interface */ 299 DEVMETHOD(miibus_readreg, re_miibus_readreg), 300 DEVMETHOD(miibus_writereg, re_miibus_writereg), 301 DEVMETHOD(miibus_statchg, re_miibus_statchg), 302 303 { 0, 0 } 304}; 305 306static driver_t re_driver = { 307 "re", 308 re_methods, 309 sizeof(struct rl_softc) 310}; 311 312static devclass_t re_devclass; 313 314DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 315DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 316DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 317 318#define EE_SET(x) \ 319 CSR_WRITE_1(sc, RL_EECMD, \ 320 CSR_READ_1(sc, RL_EECMD) | x) 321 322#define EE_CLR(x) \ 323 CSR_WRITE_1(sc, RL_EECMD, \ 324 CSR_READ_1(sc, RL_EECMD) & ~x) 325 326/* 327 * Send a read command and address to the EEPROM, check for ACK. 328 */ 329static void 330re_eeprom_putbyte(sc, addr) 331 struct rl_softc *sc; 332 int addr; 333{ 334 register int d, i; 335 336 d = addr | (RL_9346_READ << sc->rl_eewidth); 337 338 /* 339 * Feed in each bit and strobe the clock. 340 */ 341 342 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 343 if (d & i) { 344 EE_SET(RL_EE_DATAIN); 345 } else { 346 EE_CLR(RL_EE_DATAIN); 347 } 348 DELAY(100); 349 EE_SET(RL_EE_CLK); 350 DELAY(150); 351 EE_CLR(RL_EE_CLK); 352 DELAY(100); 353 } 354 355 return; 356} 357 358/* 359 * Read a word of data stored in the EEPROM at address 'addr.' 360 */ 361static void 362re_eeprom_getword(sc, addr, dest) 363 struct rl_softc *sc; 364 int addr; 365 u_int16_t *dest; 366{ 367 register int i; 368 u_int16_t word = 0; 369 370 /* 371 * Send address of word we want to read. 372 */ 373 re_eeprom_putbyte(sc, addr); 374 375 /* 376 * Start reading bits from EEPROM. 377 */ 378 for (i = 0x8000; i; i >>= 1) { 379 EE_SET(RL_EE_CLK); 380 DELAY(100); 381 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 382 word |= i; 383 EE_CLR(RL_EE_CLK); 384 DELAY(100); 385 } 386 387 *dest = word; 388 389 return; 390} 391 392/* 393 * Read a sequence of words from the EEPROM. 394 */ 395static void 396re_read_eeprom(sc, dest, off, cnt) 397 struct rl_softc *sc; 398 caddr_t dest; 399 int off; 400 int cnt; 401{ 402 int i; 403 u_int16_t word = 0, *ptr; 404 405 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 406 407 DELAY(100); 408 409 for (i = 0; i < cnt; i++) { 410 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 411 re_eeprom_getword(sc, off + i, &word); 412 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 413 ptr = (u_int16_t *)(dest + (i * 2)); 414 *ptr = word; 415 } 416 417 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 418 419 return; 420} 421 422static int 423re_gmii_readreg(dev, phy, reg) 424 device_t dev; 425 int phy, reg; 426{ 427 struct rl_softc *sc; 428 u_int32_t rval; 429 int i; 430 431 if (phy != 1) 432 return (0); 433 434 sc = device_get_softc(dev); 435 436 /* Let the rgephy driver read the GMEDIASTAT register */ 437 438 if (reg == RL_GMEDIASTAT) { 439 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 440 return (rval); 441 } 442 443 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 444 DELAY(1000); 445 446 for (i = 0; i < RL_TIMEOUT; i++) { 447 rval = CSR_READ_4(sc, RL_PHYAR); 448 if (rval & RL_PHYAR_BUSY) 449 break; 450 DELAY(100); 451 } 452 453 if (i == RL_TIMEOUT) { 454 device_printf(sc->rl_dev, "PHY read failed\n"); 455 return (0); 456 } 457 458 return (rval & RL_PHYAR_PHYDATA); 459} 460 461static int 462re_gmii_writereg(dev, phy, reg, data) 463 device_t dev; 464 int phy, reg, data; 465{ 466 struct rl_softc *sc; 467 u_int32_t rval; 468 int i; 469 470 sc = device_get_softc(dev); 471 472 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 473 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 474 DELAY(1000); 475 476 for (i = 0; i < RL_TIMEOUT; i++) { 477 rval = CSR_READ_4(sc, RL_PHYAR); 478 if (!(rval & RL_PHYAR_BUSY)) 479 break; 480 DELAY(100); 481 } 482 483 if (i == RL_TIMEOUT) { 484 device_printf(sc->rl_dev, "PHY write failed\n"); 485 return (0); 486 } 487 488 return (0); 489} 490 491static int 492re_miibus_readreg(dev, phy, reg) 493 device_t dev; 494 int phy, reg; 495{ 496 struct rl_softc *sc; 497 u_int16_t rval = 0; 498 u_int16_t re8139_reg = 0; 499 500 sc = device_get_softc(dev); 501 502 if (sc->rl_type == RL_8169) { 503 rval = re_gmii_readreg(dev, phy, reg); 504 return (rval); 505 } 506 507 /* Pretend the internal PHY is only at address 0 */ 508 if (phy) { 509 return (0); 510 } 511 switch (reg) { 512 case MII_BMCR: 513 re8139_reg = RL_BMCR; 514 break; 515 case MII_BMSR: 516 re8139_reg = RL_BMSR; 517 break; 518 case MII_ANAR: 519 re8139_reg = RL_ANAR; 520 break; 521 case MII_ANER: 522 re8139_reg = RL_ANER; 523 break; 524 case MII_ANLPAR: 525 re8139_reg = RL_LPAR; 526 break; 527 case MII_PHYIDR1: 528 case MII_PHYIDR2: 529 return (0); 530 /* 531 * Allow the rlphy driver to read the media status 532 * register. If we have a link partner which does not 533 * support NWAY, this is the register which will tell 534 * us the results of parallel detection. 535 */ 536 case RL_MEDIASTAT: 537 rval = CSR_READ_1(sc, RL_MEDIASTAT); 538 return (rval); 539 default: 540 device_printf(sc->rl_dev, "bad phy register\n"); 541 return (0); 542 } 543 rval = CSR_READ_2(sc, re8139_reg); 544 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 545 /* 8139C+ has different bit layout. */ 546 rval &= ~(BMCR_LOOP | BMCR_ISO); 547 } 548 return (rval); 549} 550 551static int 552re_miibus_writereg(dev, phy, reg, data) 553 device_t dev; 554 int phy, reg, data; 555{ 556 struct rl_softc *sc; 557 u_int16_t re8139_reg = 0; 558 int rval = 0; 559 560 sc = device_get_softc(dev); 561 562 if (sc->rl_type == RL_8169) { 563 rval = re_gmii_writereg(dev, phy, reg, data); 564 return (rval); 565 } 566 567 /* Pretend the internal PHY is only at address 0 */ 568 if (phy) 569 return (0); 570 571 switch (reg) { 572 case MII_BMCR: 573 re8139_reg = RL_BMCR; 574 if (sc->rl_type == RL_8139CPLUS) { 575 /* 8139C+ has different bit layout. */ 576 data &= ~(BMCR_LOOP | BMCR_ISO); 577 } 578 break; 579 case MII_BMSR: 580 re8139_reg = RL_BMSR; 581 break; 582 case MII_ANAR: 583 re8139_reg = RL_ANAR; 584 break; 585 case MII_ANER: 586 re8139_reg = RL_ANER; 587 break; 588 case MII_ANLPAR: 589 re8139_reg = RL_LPAR; 590 break; 591 case MII_PHYIDR1: 592 case MII_PHYIDR2: 593 return (0); 594 break; 595 default: 596 device_printf(sc->rl_dev, "bad phy register\n"); 597 return (0); 598 } 599 CSR_WRITE_2(sc, re8139_reg, data); 600 return (0); 601} 602 603static void 604re_miibus_statchg(dev) 605 device_t dev; 606{ 607 608} 609 610/* 611 * Program the 64-bit multicast hash filter. 612 */ 613static void 614re_setmulti(sc) 615 struct rl_softc *sc; 616{ 617 struct ifnet *ifp; 618 int h = 0; 619 u_int32_t hashes[2] = { 0, 0 }; 620 struct ifmultiaddr *ifma; 621 u_int32_t rxfilt; 622 int mcnt = 0; 623 624 RL_LOCK_ASSERT(sc); 625 626 ifp = sc->rl_ifp; 627 628 rxfilt = CSR_READ_4(sc, RL_RXCFG); 629 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 rxfilt |= RL_RXCFG_RX_MULTI; 632 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 633 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 634 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 635 return; 636 } 637 638 /* first, zot all the existing hash bits */ 639 CSR_WRITE_4(sc, RL_MAR0, 0); 640 CSR_WRITE_4(sc, RL_MAR4, 0); 641 642 /* now program new ones */ 643 IF_ADDR_LOCK(ifp); 644 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 645 if (ifma->ifma_addr->sa_family != AF_LINK) 646 continue; 647 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 648 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 649 if (h < 32) 650 hashes[0] |= (1 << h); 651 else 652 hashes[1] |= (1 << (h - 32)); 653 mcnt++; 654 } 655 IF_ADDR_UNLOCK(ifp); 656 657 if (mcnt) 658 rxfilt |= RL_RXCFG_RX_MULTI; 659 else 660 rxfilt &= ~RL_RXCFG_RX_MULTI; 661 662 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 663 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 664 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 665} 666 667static void 668re_reset(sc) 669 struct rl_softc *sc; 670{ 671 register int i; 672 673 RL_LOCK_ASSERT(sc); 674 675 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 676 677 for (i = 0; i < RL_TIMEOUT; i++) { 678 DELAY(10); 679 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 680 break; 681 } 682 if (i == RL_TIMEOUT) 683 device_printf(sc->rl_dev, "reset never completed!\n"); 684 685 CSR_WRITE_1(sc, 0x82, 1); 686} 687 688#ifdef RE_DIAG 689 690/* 691 * The following routine is designed to test for a defect on some 692 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 693 * lines connected to the bus, however for a 32-bit only card, they 694 * should be pulled high. The result of this defect is that the 695 * NIC will not work right if you plug it into a 64-bit slot: DMA 696 * operations will be done with 64-bit transfers, which will fail 697 * because the 64-bit data lines aren't connected. 698 * 699 * There's no way to work around this (short of talking a soldering 700 * iron to the board), however we can detect it. The method we use 701 * here is to put the NIC into digital loopback mode, set the receiver 702 * to promiscuous mode, and then try to send a frame. We then compare 703 * the frame data we sent to what was received. If the data matches, 704 * then the NIC is working correctly, otherwise we know the user has 705 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 706 * slot. In the latter case, there's no way the NIC can work correctly, 707 * so we print out a message on the console and abort the device attach. 708 */ 709 710static int 711re_diag(sc) 712 struct rl_softc *sc; 713{ 714 struct ifnet *ifp = sc->rl_ifp; 715 struct mbuf *m0; 716 struct ether_header *eh; 717 struct rl_desc *cur_rx; 718 u_int16_t status; 719 u_int32_t rxstat; 720 int total_len, i, error = 0, phyaddr; 721 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 722 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 723 724 /* Allocate a single mbuf */ 725 MGETHDR(m0, M_DONTWAIT, MT_DATA); 726 if (m0 == NULL) 727 return (ENOBUFS); 728 729 RL_LOCK(sc); 730 731 /* 732 * Initialize the NIC in test mode. This sets the chip up 733 * so that it can send and receive frames, but performs the 734 * following special functions: 735 * - Puts receiver in promiscuous mode 736 * - Enables digital loopback mode 737 * - Leaves interrupts turned off 738 */ 739 740 ifp->if_flags |= IFF_PROMISC; 741 sc->rl_testmode = 1; 742 re_reset(sc); 743 re_init_locked(sc); 744 sc->rl_link = 1; 745 if (sc->rl_type == RL_8169) 746 phyaddr = 1; 747 else 748 phyaddr = 0; 749 750 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 751 for (i = 0; i < RL_TIMEOUT; i++) { 752 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 753 if (!(status & BMCR_RESET)) 754 break; 755 } 756 757 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 758 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 759 760 DELAY(100000); 761 762 /* Put some data in the mbuf */ 763 764 eh = mtod(m0, struct ether_header *); 765 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 766 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 767 eh->ether_type = htons(ETHERTYPE_IP); 768 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 769 770 /* 771 * Queue the packet, start transmission. 772 * Note: IF_HANDOFF() ultimately calls re_start() for us. 773 */ 774 775 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 776 RL_UNLOCK(sc); 777 /* XXX: re_diag must not be called when in ALTQ mode */ 778 IF_HANDOFF(&ifp->if_snd, m0, ifp); 779 RL_LOCK(sc); 780 m0 = NULL; 781 782 /* Wait for it to propagate through the chip */ 783 784 DELAY(100000); 785 for (i = 0; i < RL_TIMEOUT; i++) { 786 status = CSR_READ_2(sc, RL_ISR); 787 CSR_WRITE_2(sc, RL_ISR, status); 788 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 789 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 790 break; 791 DELAY(10); 792 } 793 794 if (i == RL_TIMEOUT) { 795 device_printf(sc->rl_dev, 796 "diagnostic failed, failed to receive packet in" 797 " loopback mode\n"); 798 error = EIO; 799 goto done; 800 } 801 802 /* 803 * The packet should have been dumped into the first 804 * entry in the RX DMA ring. Grab it from there. 805 */ 806 807 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 808 sc->rl_ldata.rl_rx_list_map, 809 BUS_DMASYNC_POSTREAD); 810 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 811 sc->rl_ldata.rl_rx_dmamap[0], 812 BUS_DMASYNC_POSTWRITE); 813 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 814 sc->rl_ldata.rl_rx_dmamap[0]); 815 816 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 817 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 818 eh = mtod(m0, struct ether_header *); 819 820 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 821 total_len = RL_RXBYTES(cur_rx); 822 rxstat = le32toh(cur_rx->rl_cmdstat); 823 824 if (total_len != ETHER_MIN_LEN) { 825 device_printf(sc->rl_dev, 826 "diagnostic failed, received short packet\n"); 827 error = EIO; 828 goto done; 829 } 830 831 /* Test that the received packet data matches what we sent. */ 832 833 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 834 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 835 ntohs(eh->ether_type) != ETHERTYPE_IP) { 836 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 837 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 838 dst, ":", src, ":", ETHERTYPE_IP); 839 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 840 eh->ether_dhost, ":", eh->ether_shost, ":", 841 ntohs(eh->ether_type)); 842 device_printf(sc->rl_dev, "You may have a defective 32-bit " 843 "NIC plugged into a 64-bit PCI slot.\n"); 844 device_printf(sc->rl_dev, "Please re-install the NIC in a " 845 "32-bit slot for proper operation.\n"); 846 device_printf(sc->rl_dev, "Read the re(4) man page for more " 847 "details.\n"); 848 error = EIO; 849 } 850 851done: 852 /* Turn interface off, release resources */ 853 854 sc->rl_testmode = 0; 855 sc->rl_link = 0; 856 ifp->if_flags &= ~IFF_PROMISC; 857 re_stop(sc); 858 if (m0 != NULL) 859 m_freem(m0); 860 861 RL_UNLOCK(sc); 862 863 return (error); 864} 865 866#endif 867 868/* 869 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 870 * IDs against our list and return a device name if we find a match. 871 */ 872static int 873re_probe(dev) 874 device_t dev; 875{ 876 struct rl_type *t; 877 struct rl_softc *sc; 878 int rid; 879 u_int32_t hwrev; 880 881 t = re_devs; 882 sc = device_get_softc(dev); 883 884 while (t->rl_name != NULL) { 885 if ((pci_get_vendor(dev) == t->rl_vid) && 886 (pci_get_device(dev) == t->rl_did)) { 887 /* 888 * Only attach to rev. 3 of the Linksys EG1032 adapter. 889 * Rev. 2 i supported by sk(4). 890 */ 891 if ((t->rl_vid == LINKSYS_VENDORID) && 892 (t->rl_did == LINKSYS_DEVICEID_EG1032) && 893 (pci_get_subdevice(dev) != 894 LINKSYS_SUBDEVICE_EG1032_REV3)) { 895 t++; 896 continue; 897 } 898 899 /* 900 * Temporarily map the I/O space 901 * so we can read the chip ID register. 902 */ 903 rid = RL_RID; 904 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 905 RF_ACTIVE); 906 if (sc->rl_res == NULL) { 907 device_printf(dev, 908 "couldn't map ports/memory\n"); 909 return (ENXIO); 910 } 911 sc->rl_btag = rman_get_bustag(sc->rl_res); 912 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 913 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 914 bus_release_resource(dev, RL_RES, 915 RL_RID, sc->rl_res); 916 if (t->rl_basetype == hwrev) { 917 device_set_desc(dev, t->rl_name); 918 return (BUS_PROBE_DEFAULT); 919 } 920 } 921 t++; 922 } 923 924 return (ENXIO); 925} 926 927/* 928 * This routine takes the segment list provided as the result of 929 * a bus_dma_map_load() operation and assigns the addresses/lengths 930 * to RealTek DMA descriptors. This can be called either by the RX 931 * code or the TX code. In the RX case, we'll probably wind up mapping 932 * at most one segment. For the TX case, there could be any number of 933 * segments since TX packets may span multiple mbufs. In either case, 934 * if the number of segments is larger than the rl_maxsegs limit 935 * specified by the caller, we abort the mapping operation. Sadly, 936 * whoever designed the buffer mapping API did not provide a way to 937 * return an error from here, so we have to fake it a bit. 938 */ 939 940static void 941re_dma_map_desc(arg, segs, nseg, mapsize, error) 942 void *arg; 943 bus_dma_segment_t *segs; 944 int nseg; 945 bus_size_t mapsize; 946 int error; 947{ 948 struct rl_dmaload_arg *ctx; 949 struct rl_desc *d = NULL; 950 int i = 0, idx; 951 u_int32_t cmdstat; 952 int totlen = 0; 953 954 if (error) 955 return; 956 957 ctx = arg; 958 959 /* Signal error to caller if there's too many segments */ 960 if (nseg > ctx->rl_maxsegs) { 961 ctx->rl_maxsegs = 0; 962 return; 963 } 964 965 /* 966 * Map the segment array into descriptors. Note that we set the 967 * start-of-frame and end-of-frame markers for either TX or RX, but 968 * they really only have meaning in the TX case. (In the RX case, 969 * it's the chip that tells us where packets begin and end.) 970 * We also keep track of the end of the ring and set the 971 * end-of-ring bits as needed, and we set the ownership bits 972 * in all except the very first descriptor. (The caller will 973 * set this descriptor later when it start transmission or 974 * reception.) 975 */ 976 idx = ctx->rl_idx; 977 for (;;) { 978 d = &ctx->rl_ring[idx]; 979 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 980 ctx->rl_maxsegs = 0; 981 return; 982 } 983 cmdstat = segs[i].ds_len; 984 totlen += segs[i].ds_len; 985 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 986 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 987 if (i == 0) 988 cmdstat |= RL_TDESC_CMD_SOF; 989 else 990 cmdstat |= RL_TDESC_CMD_OWN; 991 if (idx == (RL_RX_DESC_CNT - 1)) 992 cmdstat |= RL_TDESC_CMD_EOR; 993 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 994 i++; 995 if (i == nseg) 996 break; 997 RL_DESC_INC(idx); 998 } 999 1000 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 1001 ctx->rl_maxsegs = nseg; 1002 ctx->rl_idx = idx; 1003} 1004 1005/* 1006 * Map a single buffer address. 1007 */ 1008 1009static void 1010re_dma_map_addr(arg, segs, nseg, error) 1011 void *arg; 1012 bus_dma_segment_t *segs; 1013 int nseg; 1014 int error; 1015{ 1016 bus_addr_t *addr; 1017 1018 if (error) 1019 return; 1020 1021 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1022 addr = arg; 1023 *addr = segs->ds_addr; 1024} 1025 1026static int 1027re_allocmem(dev, sc) 1028 device_t dev; 1029 struct rl_softc *sc; 1030{ 1031 int error; 1032 int nseg; 1033 int i; 1034 1035 /* 1036 * Allocate map for RX mbufs. 1037 */ 1038 nseg = 32; 1039 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 1040 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1041 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 1042 NULL, NULL, &sc->rl_ldata.rl_mtag); 1043 if (error) { 1044 device_printf(dev, "could not allocate dma tag\n"); 1045 return (ENOMEM); 1046 } 1047 1048 /* 1049 * Allocate map for TX descriptor list. 1050 */ 1051 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1052 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1053 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1054 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1055 if (error) { 1056 device_printf(dev, "could not allocate dma tag\n"); 1057 return (ENOMEM); 1058 } 1059 1060 /* Allocate DMA'able memory for the TX ring */ 1061 1062 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1063 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1064 &sc->rl_ldata.rl_tx_list_map); 1065 if (error) 1066 return (ENOMEM); 1067 1068 /* Load the map for the TX ring. */ 1069 1070 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1071 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1072 RL_TX_LIST_SZ, re_dma_map_addr, 1073 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1074 1075 /* Create DMA maps for TX buffers */ 1076 1077 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1078 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1079 &sc->rl_ldata.rl_tx_dmamap[i]); 1080 if (error) { 1081 device_printf(dev, "can't create DMA map for TX\n"); 1082 return (ENOMEM); 1083 } 1084 } 1085 1086 /* 1087 * Allocate map for RX descriptor list. 1088 */ 1089 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1090 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1091 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1092 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1093 if (error) { 1094 device_printf(dev, "could not allocate dma tag\n"); 1095 return (ENOMEM); 1096 } 1097 1098 /* Allocate DMA'able memory for the RX ring */ 1099 1100 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1101 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1102 &sc->rl_ldata.rl_rx_list_map); 1103 if (error) 1104 return (ENOMEM); 1105 1106 /* Load the map for the RX ring. */ 1107 1108 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1109 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1110 RL_RX_LIST_SZ, re_dma_map_addr, 1111 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1112 1113 /* Create DMA maps for RX buffers */ 1114 1115 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1116 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1117 &sc->rl_ldata.rl_rx_dmamap[i]); 1118 if (error) { 1119 device_printf(dev, "can't create DMA map for RX\n"); 1120 return (ENOMEM); 1121 } 1122 } 1123 1124 return (0); 1125} 1126 1127/* 1128 * Attach the interface. Allocate softc structures, do ifmedia 1129 * setup and ethernet/BPF attach. 1130 */ 1131static int 1132re_attach(dev) 1133 device_t dev; 1134{ 1135 u_char eaddr[ETHER_ADDR_LEN]; 1136 u_int16_t as[ETHER_ADDR_LEN / 2]; 1137 struct rl_softc *sc; 1138 struct ifnet *ifp; 1139 struct rl_hwrev *hw_rev; 1140 int hwrev; 1141 u_int16_t re_did = 0; 1142 int error = 0, rid, i; 1143 1144 sc = device_get_softc(dev); 1145 sc->rl_dev = dev; 1146 1147 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1148 MTX_DEF); 1149 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1150 1151 /* 1152 * Map control/status registers. 1153 */ 1154 pci_enable_busmaster(dev); 1155 1156 rid = RL_RID; 1157 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1158 RF_ACTIVE); 1159 1160 if (sc->rl_res == NULL) { 1161 device_printf(dev, "couldn't map ports/memory\n"); 1162 error = ENXIO; 1163 goto fail; 1164 } 1165 1166 sc->rl_btag = rman_get_bustag(sc->rl_res); 1167 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1168 1169 /* Allocate interrupt */ 1170 rid = 0; 1171 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1172 RF_SHAREABLE | RF_ACTIVE); 1173 1174 if (sc->rl_irq == NULL) { 1175 device_printf(dev, "couldn't map interrupt\n"); 1176 error = ENXIO; 1177 goto fail; 1178 } 1179 1180 /* Reset the adapter. */ 1181 RL_LOCK(sc); 1182 re_reset(sc); 1183 RL_UNLOCK(sc); 1184 1185 hw_rev = re_hwrevs; 1186 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1187 while (hw_rev->rl_desc != NULL) { 1188 if (hw_rev->rl_rev == hwrev) { 1189 sc->rl_type = hw_rev->rl_type; 1190 break; 1191 } 1192 hw_rev++; 1193 } 1194 1195 sc->rl_eewidth = 6; 1196 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1197 if (re_did != 0x8129) 1198 sc->rl_eewidth = 8; 1199 1200 /* 1201 * Get station address from the EEPROM. 1202 */ 1203 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1204 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1205 as[i] = le16toh(as[i]); 1206 bcopy(as, eaddr, sizeof(eaddr)); 1207 1208 if (sc->rl_type == RL_8169) { 1209 /* Set RX length mask */ 1210 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1211 sc->rl_txstart = RL_GTXSTART; 1212 } else { 1213 /* Set RX length mask */ 1214 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1215 sc->rl_txstart = RL_TXSTART; 1216 } 1217 1218 /* 1219 * Allocate the parent bus DMA tag appropriate for PCI. 1220 */ 1221#define RL_NSEG_NEW 32 1222 error = bus_dma_tag_create(NULL, /* parent */ 1223 1, 0, /* alignment, boundary */ 1224 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1225 BUS_SPACE_MAXADDR, /* highaddr */ 1226 NULL, NULL, /* filter, filterarg */ 1227 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1228 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1229 BUS_DMA_ALLOCNOW, /* flags */ 1230 NULL, NULL, /* lockfunc, lockarg */ 1231 &sc->rl_parent_tag); 1232 if (error) 1233 goto fail; 1234 1235 error = re_allocmem(dev, sc); 1236 1237 if (error) 1238 goto fail; 1239 1240 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1241 if (ifp == NULL) { 1242 device_printf(dev, "can not if_alloc()\n"); 1243 error = ENOSPC; 1244 goto fail; 1245 } 1246 1247 /* Do MII setup */ 1248 if (mii_phy_probe(dev, &sc->rl_miibus, 1249 re_ifmedia_upd, re_ifmedia_sts)) { 1250 device_printf(dev, "MII without any phy!\n"); 1251 error = ENXIO; 1252 goto fail; 1253 } 1254 1255 ifp->if_softc = sc; 1256 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1257 ifp->if_mtu = ETHERMTU; 1258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1259 ifp->if_ioctl = re_ioctl; 1260 ifp->if_start = re_start; 1261 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1262 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1263 ifp->if_capenable = ifp->if_capabilities; 1264 ifp->if_watchdog = re_watchdog; 1265 ifp->if_init = re_init; 1266 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1267 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1268 IFQ_SET_READY(&ifp->if_snd); 1269 1270 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1271 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1272 1273 /* 1274 * Call MI attach routine. 1275 */ 1276 ether_ifattach(ifp, eaddr); 1277 1278 /* VLAN capability setup */ 1279 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1280 if (ifp->if_capabilities & IFCAP_HWCSUM) 1281 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1282 ifp->if_capenable = ifp->if_capabilities; 1283#ifdef DEVICE_POLLING 1284 ifp->if_capabilities |= IFCAP_POLLING; 1285#endif 1286 /* 1287 * Tell the upper layer(s) we support long frames. 1288 * Must appear after the call to ether_ifattach() because 1289 * ether_ifattach() sets ifi_hdrlen to the default value. 1290 */ 1291 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1292 1293#ifdef RE_DIAG 1294 /* 1295 * Perform hardware diagnostic on the original RTL8169. 1296 * Some 32-bit cards were incorrectly wired and would 1297 * malfunction if plugged into a 64-bit slot. 1298 */ 1299 1300 if (hwrev == RL_HWREV_8169) { 1301 error = re_diag(sc); 1302 if (error) { 1303 device_printf(dev, 1304 "attach aborted due to hardware diag failure\n"); 1305 ether_ifdetach(ifp); 1306 goto fail; 1307 } 1308 } 1309#endif 1310 1311 /* Hook interrupt last to avoid having to lock softc */ 1312 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE | 1313 INTR_FAST, re_intr, sc, &sc->rl_intrhand); 1314 if (error) { 1315 device_printf(dev, "couldn't set up irq\n"); 1316 ether_ifdetach(ifp); 1317 } 1318 1319fail: 1320 1321 if (error) 1322 re_detach(dev); 1323 1324 return (error); 1325} 1326 1327/* 1328 * Shutdown hardware and free up resources. This can be called any 1329 * time after the mutex has been initialized. It is called in both 1330 * the error case in attach and the normal detach case so it needs 1331 * to be careful about only freeing resources that have actually been 1332 * allocated. 1333 */ 1334static int 1335re_detach(dev) 1336 device_t dev; 1337{ 1338 struct rl_softc *sc; 1339 struct ifnet *ifp; 1340 int i; 1341 1342 sc = device_get_softc(dev); 1343 ifp = sc->rl_ifp; 1344 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1345 1346#ifdef DEVICE_POLLING 1347 if (ifp->if_capenable & IFCAP_POLLING) 1348 ether_poll_deregister(ifp); 1349#endif 1350 /* These should only be active if attach succeeded */ 1351 if (device_is_attached(dev)) { 1352 RL_LOCK(sc); 1353#if 0 1354 sc->suspended = 1; 1355#endif 1356 re_stop(sc); 1357 RL_UNLOCK(sc); 1358 callout_drain(&sc->rl_stat_callout); 1359 /* 1360 * Force off the IFF_UP flag here, in case someone 1361 * still had a BPF descriptor attached to this 1362 * interface. If they do, ether_ifdetach() will cause 1363 * the BPF code to try and clear the promisc mode 1364 * flag, which will bubble down to re_ioctl(), 1365 * which will try to call re_init() again. This will 1366 * turn the NIC back on and restart the MII ticker, 1367 * which will panic the system when the kernel tries 1368 * to invoke the re_tick() function that isn't there 1369 * anymore. 1370 */ 1371 ifp->if_flags &= ~IFF_UP; 1372 ether_ifdetach(ifp); 1373 } 1374 if (sc->rl_miibus) 1375 device_delete_child(dev, sc->rl_miibus); 1376 bus_generic_detach(dev); 1377 1378 /* 1379 * The rest is resource deallocation, so we should already be 1380 * stopped here. 1381 */ 1382 1383 if (sc->rl_intrhand) 1384 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1385 if (ifp != NULL) 1386 if_free(ifp); 1387 if (sc->rl_irq) 1388 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1389 if (sc->rl_res) 1390 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1391 1392 /* Yield the CPU long enough for any tasks to drain */ 1393 1394 tsleep(sc, PPAUSE, "rewait", hz); 1395 1396 /* Unload and free the RX DMA ring memory and map */ 1397 1398 if (sc->rl_ldata.rl_rx_list_tag) { 1399 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1400 sc->rl_ldata.rl_rx_list_map); 1401 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1402 sc->rl_ldata.rl_rx_list, 1403 sc->rl_ldata.rl_rx_list_map); 1404 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1405 } 1406 1407 /* Unload and free the TX DMA ring memory and map */ 1408 1409 if (sc->rl_ldata.rl_tx_list_tag) { 1410 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1411 sc->rl_ldata.rl_tx_list_map); 1412 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1413 sc->rl_ldata.rl_tx_list, 1414 sc->rl_ldata.rl_tx_list_map); 1415 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1416 } 1417 1418 /* Destroy all the RX and TX buffer maps */ 1419 1420 if (sc->rl_ldata.rl_mtag) { 1421 for (i = 0; i < RL_TX_DESC_CNT; i++) 1422 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1423 sc->rl_ldata.rl_tx_dmamap[i]); 1424 for (i = 0; i < RL_RX_DESC_CNT; i++) 1425 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1426 sc->rl_ldata.rl_rx_dmamap[i]); 1427 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1428 } 1429 1430 /* Unload and free the stats buffer and map */ 1431 1432 if (sc->rl_ldata.rl_stag) { 1433 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1434 sc->rl_ldata.rl_rx_list_map); 1435 bus_dmamem_free(sc->rl_ldata.rl_stag, 1436 sc->rl_ldata.rl_stats, 1437 sc->rl_ldata.rl_smap); 1438 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1439 } 1440 1441 if (sc->rl_parent_tag) 1442 bus_dma_tag_destroy(sc->rl_parent_tag); 1443 1444 mtx_destroy(&sc->rl_mtx); 1445 1446 return (0); 1447} 1448 1449static int 1450re_newbuf(sc, idx, m) 1451 struct rl_softc *sc; 1452 int idx; 1453 struct mbuf *m; 1454{ 1455 struct rl_dmaload_arg arg; 1456 struct mbuf *n = NULL; 1457 int error; 1458 1459 if (m == NULL) { 1460 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1461 if (n == NULL) 1462 return (ENOBUFS); 1463 m = n; 1464 } else 1465 m->m_data = m->m_ext.ext_buf; 1466 1467 m->m_len = m->m_pkthdr.len = MCLBYTES; 1468#ifdef RE_FIXUP_RX 1469 /* 1470 * This is part of an evil trick to deal with non-x86 platforms. 1471 * The RealTek chip requires RX buffers to be aligned on 64-bit 1472 * boundaries, but that will hose non-x86 machines. To get around 1473 * this, we leave some empty space at the start of each buffer 1474 * and for non-x86 hosts, we copy the buffer back six bytes 1475 * to achieve word alignment. This is slightly more efficient 1476 * than allocating a new buffer, copying the contents, and 1477 * discarding the old buffer. 1478 */ 1479 m_adj(m, RE_ETHER_ALIGN); 1480#endif 1481 arg.sc = sc; 1482 arg.rl_idx = idx; 1483 arg.rl_maxsegs = 1; 1484 arg.rl_flags = 0; 1485 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1486 1487 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1488 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1489 &arg, BUS_DMA_NOWAIT); 1490 if (error || arg.rl_maxsegs != 1) { 1491 if (n != NULL) 1492 m_freem(n); 1493 return (ENOMEM); 1494 } 1495 1496 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1497 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1498 1499 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1500 sc->rl_ldata.rl_rx_dmamap[idx], 1501 BUS_DMASYNC_PREREAD); 1502 1503 return (0); 1504} 1505 1506#ifdef RE_FIXUP_RX 1507static __inline void 1508re_fixup_rx(m) 1509 struct mbuf *m; 1510{ 1511 int i; 1512 uint16_t *src, *dst; 1513 1514 src = mtod(m, uint16_t *); 1515 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1516 1517 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1518 *dst++ = *src++; 1519 1520 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1521 1522 return; 1523} 1524#endif 1525 1526static int 1527re_tx_list_init(sc) 1528 struct rl_softc *sc; 1529{ 1530 1531 RL_LOCK_ASSERT(sc); 1532 1533 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1534 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1535 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1536 1537 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1538 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1539 sc->rl_ldata.rl_tx_prodidx = 0; 1540 sc->rl_ldata.rl_tx_considx = 0; 1541 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1542 1543 return (0); 1544} 1545 1546static int 1547re_rx_list_init(sc) 1548 struct rl_softc *sc; 1549{ 1550 int i; 1551 1552 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1553 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1554 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1555 1556 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1557 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1558 return (ENOBUFS); 1559 } 1560 1561 /* Flush the RX descriptors */ 1562 1563 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1564 sc->rl_ldata.rl_rx_list_map, 1565 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1566 1567 sc->rl_ldata.rl_rx_prodidx = 0; 1568 sc->rl_head = sc->rl_tail = NULL; 1569 1570 return (0); 1571} 1572 1573/* 1574 * RX handler for C+ and 8169. For the gigE chips, we support 1575 * the reception of jumbo frames that have been fragmented 1576 * across multiple 2K mbuf cluster buffers. 1577 */ 1578static int 1579re_rxeof(sc) 1580 struct rl_softc *sc; 1581{ 1582 struct mbuf *m; 1583 struct ifnet *ifp; 1584 int i, total_len; 1585 struct rl_desc *cur_rx; 1586 u_int32_t rxstat, rxvlan; 1587 int maxpkt = 16; 1588 1589 RL_LOCK_ASSERT(sc); 1590 1591 ifp = sc->rl_ifp; 1592 i = sc->rl_ldata.rl_rx_prodidx; 1593 1594 /* Invalidate the descriptor memory */ 1595 1596 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1597 sc->rl_ldata.rl_rx_list_map, 1598 BUS_DMASYNC_POSTREAD); 1599 1600 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) { 1601 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1602 m = sc->rl_ldata.rl_rx_mbuf[i]; 1603 total_len = RL_RXBYTES(cur_rx); 1604 rxstat = le32toh(cur_rx->rl_cmdstat); 1605 rxvlan = le32toh(cur_rx->rl_vlanctl); 1606 1607 /* Invalidate the RX mbuf and unload its map */ 1608 1609 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1610 sc->rl_ldata.rl_rx_dmamap[i], 1611 BUS_DMASYNC_POSTWRITE); 1612 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1613 sc->rl_ldata.rl_rx_dmamap[i]); 1614 1615 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1616 m->m_len = RE_RX_DESC_BUFLEN; 1617 if (sc->rl_head == NULL) 1618 sc->rl_head = sc->rl_tail = m; 1619 else { 1620 m->m_flags &= ~M_PKTHDR; 1621 sc->rl_tail->m_next = m; 1622 sc->rl_tail = m; 1623 } 1624 re_newbuf(sc, i, NULL); 1625 RL_DESC_INC(i); 1626 continue; 1627 } 1628 1629 /* 1630 * NOTE: for the 8139C+, the frame length field 1631 * is always 12 bits in size, but for the gigE chips, 1632 * it is 13 bits (since the max RX frame length is 16K). 1633 * Unfortunately, all 32 bits in the status word 1634 * were already used, so to make room for the extra 1635 * length bit, RealTek took out the 'frame alignment 1636 * error' bit and shifted the other status bits 1637 * over one slot. The OWN, EOR, FS and LS bits are 1638 * still in the same places. We have already extracted 1639 * the frame length and checked the OWN bit, so rather 1640 * than using an alternate bit mapping, we shift the 1641 * status bits one space to the right so we can evaluate 1642 * them using the 8169 status as though it was in the 1643 * same format as that of the 8139C+. 1644 */ 1645 if (sc->rl_type == RL_8169) 1646 rxstat >>= 1; 1647 1648 /* 1649 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1650 * set, but if CRC is clear, it will still be a valid frame. 1651 */ 1652 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1653 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1654 ifp->if_ierrors++; 1655 /* 1656 * If this is part of a multi-fragment packet, 1657 * discard all the pieces. 1658 */ 1659 if (sc->rl_head != NULL) { 1660 m_freem(sc->rl_head); 1661 sc->rl_head = sc->rl_tail = NULL; 1662 } 1663 re_newbuf(sc, i, m); 1664 RL_DESC_INC(i); 1665 continue; 1666 } 1667 1668 /* 1669 * If allocating a replacement mbuf fails, 1670 * reload the current one. 1671 */ 1672 1673 if (re_newbuf(sc, i, NULL)) { 1674 ifp->if_ierrors++; 1675 if (sc->rl_head != NULL) { 1676 m_freem(sc->rl_head); 1677 sc->rl_head = sc->rl_tail = NULL; 1678 } 1679 re_newbuf(sc, i, m); 1680 RL_DESC_INC(i); 1681 continue; 1682 } 1683 1684 RL_DESC_INC(i); 1685 1686 if (sc->rl_head != NULL) { 1687 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1688 if (m->m_len == 0) 1689 m->m_len = RE_RX_DESC_BUFLEN; 1690 /* 1691 * Special case: if there's 4 bytes or less 1692 * in this buffer, the mbuf can be discarded: 1693 * the last 4 bytes is the CRC, which we don't 1694 * care about anyway. 1695 */ 1696 if (m->m_len <= ETHER_CRC_LEN) { 1697 sc->rl_tail->m_len -= 1698 (ETHER_CRC_LEN - m->m_len); 1699 m_freem(m); 1700 } else { 1701 m->m_len -= ETHER_CRC_LEN; 1702 m->m_flags &= ~M_PKTHDR; 1703 sc->rl_tail->m_next = m; 1704 } 1705 m = sc->rl_head; 1706 sc->rl_head = sc->rl_tail = NULL; 1707 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1708 } else 1709 m->m_pkthdr.len = m->m_len = 1710 (total_len - ETHER_CRC_LEN); 1711 1712#ifdef RE_FIXUP_RX 1713 re_fixup_rx(m); 1714#endif 1715 ifp->if_ipackets++; 1716 m->m_pkthdr.rcvif = ifp; 1717 1718 /* Do RX checksumming if enabled */ 1719 1720 if (ifp->if_capenable & IFCAP_RXCSUM) { 1721 1722 /* Check IP header checksum */ 1723 if (rxstat & RL_RDESC_STAT_PROTOID) 1724 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1725 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1726 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1727 1728 /* Check TCP/UDP checksum */ 1729 if ((RL_TCPPKT(rxstat) && 1730 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1731 (RL_UDPPKT(rxstat) && 1732 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1733 m->m_pkthdr.csum_flags |= 1734 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1735 m->m_pkthdr.csum_data = 0xffff; 1736 } 1737 } 1738 maxpkt--; 1739 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1740 m->m_pkthdr.ether_vtag = 1741 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1742 m->m_flags |= M_VLANTAG; 1743 } 1744 RL_UNLOCK(sc); 1745 (*ifp->if_input)(ifp, m); 1746 RL_LOCK(sc); 1747 } 1748 1749 /* Flush the RX DMA ring */ 1750 1751 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1752 sc->rl_ldata.rl_rx_list_map, 1753 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1754 1755 sc->rl_ldata.rl_rx_prodidx = i; 1756 1757 if (maxpkt) 1758 return(EAGAIN); 1759 1760 return(0); 1761} 1762 1763static void 1764re_txeof(sc) 1765 struct rl_softc *sc; 1766{ 1767 struct ifnet *ifp; 1768 u_int32_t txstat; 1769 int idx; 1770 1771 ifp = sc->rl_ifp; 1772 idx = sc->rl_ldata.rl_tx_considx; 1773 1774 /* Invalidate the TX descriptor list */ 1775 1776 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1777 sc->rl_ldata.rl_tx_list_map, 1778 BUS_DMASYNC_POSTREAD); 1779 1780 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1781 1782 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1783 if (txstat & RL_TDESC_CMD_OWN) 1784 break; 1785 1786 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0; 1787 1788 /* 1789 * We only stash mbufs in the last descriptor 1790 * in a fragment chain, which also happens to 1791 * be the only place where the TX status bits 1792 * are valid. 1793 */ 1794 1795 if (txstat & RL_TDESC_CMD_EOF) { 1796 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1797 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1798 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1799 sc->rl_ldata.rl_tx_dmamap[idx]); 1800 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1801 RL_TDESC_STAT_COLCNT)) 1802 ifp->if_collisions++; 1803 if (txstat & RL_TDESC_STAT_TXERRSUM) 1804 ifp->if_oerrors++; 1805 else 1806 ifp->if_opackets++; 1807 } 1808 sc->rl_ldata.rl_tx_free++; 1809 RL_DESC_INC(idx); 1810 } 1811 1812 /* No changes made to the TX ring, so no flush needed */ 1813 1814 if (sc->rl_ldata.rl_tx_free) { 1815 sc->rl_ldata.rl_tx_considx = idx; 1816 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1817 ifp->if_timer = 0; 1818 } 1819 1820 /* 1821 * Some chips will ignore a second TX request issued while an 1822 * existing transmission is in progress. If the transmitter goes 1823 * idle but there are still packets waiting to be sent, we need 1824 * to restart the channel here to flush them out. This only seems 1825 * to be required with the PCIe devices. 1826 */ 1827 1828 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) 1829 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1830 1831#ifdef RE_TX_MODERATION 1832 /* 1833 * If not all descriptors have been released reaped yet, 1834 * reload the timer so that we will eventually get another 1835 * interrupt that will cause us to re-enter this routine. 1836 * This is done in case the transmitter has gone idle. 1837 */ 1838 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1839 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1840#endif 1841 1842} 1843 1844static void 1845re_tick(xsc) 1846 void *xsc; 1847{ 1848 struct rl_softc *sc; 1849 struct mii_data *mii; 1850 struct ifnet *ifp; 1851 1852 sc = xsc; 1853 ifp = sc->rl_ifp; 1854 1855 RL_LOCK_ASSERT(sc); 1856 1857 mii = device_get_softc(sc->rl_miibus); 1858 1859 mii_tick(mii); 1860 if (sc->rl_link) { 1861 if (!(mii->mii_media_status & IFM_ACTIVE)) 1862 sc->rl_link = 0; 1863 } else { 1864 if (mii->mii_media_status & IFM_ACTIVE && 1865 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1866 sc->rl_link = 1; 1867 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1868 taskqueue_enqueue_fast(taskqueue_fast, 1869 &sc->rl_txtask); 1870 } 1871 } 1872 1873 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1874} 1875 1876#ifdef DEVICE_POLLING 1877static void 1878re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1879{ 1880 struct rl_softc *sc = ifp->if_softc; 1881 1882 RL_LOCK(sc); 1883 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1884 re_poll_locked(ifp, cmd, count); 1885 RL_UNLOCK(sc); 1886} 1887 1888static void 1889re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1890{ 1891 struct rl_softc *sc = ifp->if_softc; 1892 1893 RL_LOCK_ASSERT(sc); 1894 1895 sc->rxcycles = count; 1896 re_rxeof(sc); 1897 re_txeof(sc); 1898 1899 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1900 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 1901 1902 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1903 u_int16_t status; 1904 1905 status = CSR_READ_2(sc, RL_ISR); 1906 if (status == 0xffff) 1907 return; 1908 if (status) 1909 CSR_WRITE_2(sc, RL_ISR, status); 1910 1911 /* 1912 * XXX check behaviour on receiver stalls. 1913 */ 1914 1915 if (status & RL_ISR_SYSTEM_ERR) { 1916 re_reset(sc); 1917 re_init_locked(sc); 1918 } 1919 } 1920} 1921#endif /* DEVICE_POLLING */ 1922 1923static void 1924re_intr(arg) 1925 void *arg; 1926{ 1927 struct rl_softc *sc; 1928 struct ifnet *ifp; 1929 uint16_t status; 1930 1931 sc = arg; 1932 ifp = sc->rl_ifp; 1933 1934 status = CSR_READ_2(sc, RL_ISR); 1935 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 1936 return; 1937 CSR_WRITE_2(sc, RL_IMR, 0); 1938 1939 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 1940 1941 return; 1942} 1943 1944static void 1945re_int_task(arg, npending) 1946 void *arg; 1947 int npending; 1948{ 1949 struct rl_softc *sc; 1950 struct ifnet *ifp; 1951 u_int16_t status; 1952 int rval = 0; 1953 1954 sc = arg; 1955 ifp = sc->rl_ifp; 1956 1957 RL_LOCK(sc); 1958 1959 status = CSR_READ_2(sc, RL_ISR); 1960 CSR_WRITE_2(sc, RL_ISR, status); 1961 1962 if (sc->suspended || !(ifp->if_flags & IFF_UP)) { 1963 RL_UNLOCK(sc); 1964 return; 1965 } 1966 1967#ifdef DEVICE_POLLING 1968 if (ifp->if_capenable & IFCAP_POLLING) { 1969 RL_UNLOCK(sc); 1970 return; 1971 } 1972#endif 1973 1974 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 1975 rval = re_rxeof(sc); 1976 1977#ifdef RE_TX_MODERATION 1978 if (status & (RL_ISR_TIMEOUT_EXPIRED| 1979#else 1980 if (status & (RL_ISR_TX_OK| 1981#endif 1982 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 1983 re_txeof(sc); 1984 1985 if (status & RL_ISR_SYSTEM_ERR) { 1986 re_reset(sc); 1987 re_init_locked(sc); 1988 } 1989 1990 if (status & RL_ISR_LINKCHG) { 1991 callout_stop(&sc->rl_stat_callout); 1992 re_tick(sc); 1993 } 1994 1995 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1996 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 1997 1998 RL_UNLOCK(sc); 1999 2000 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2001 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2002 return; 2003 } 2004 2005 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2006 2007 return; 2008} 2009 2010static int 2011re_encap(sc, m_head, idx) 2012 struct rl_softc *sc; 2013 struct mbuf **m_head; 2014 int *idx; 2015{ 2016 struct mbuf *m_new = NULL; 2017 struct rl_dmaload_arg arg; 2018 bus_dmamap_t map; 2019 int error; 2020 2021 RL_LOCK_ASSERT(sc); 2022 2023 if (sc->rl_ldata.rl_tx_free <= 4) 2024 return (EFBIG); 2025 2026 /* 2027 * Set up checksum offload. Note: checksum offload bits must 2028 * appear in all descriptors of a multi-descriptor transmit 2029 * attempt. This is according to testing done with an 8169 2030 * chip. This is a requirement. 2031 */ 2032 2033 arg.rl_flags = 0; 2034 2035 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2036 arg.rl_flags = RL_TDESC_CMD_LGSEND | 2037 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2038 RL_TDESC_CMD_MSSVAL_SHIFT); 2039 else { 2040 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2041 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 2042 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2043 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 2044 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2045 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 2046 } 2047 2048 arg.sc = sc; 2049 arg.rl_idx = *idx; 2050 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2051 if (arg.rl_maxsegs > 4) 2052 arg.rl_maxsegs -= 4; 2053 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2054 2055 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 2056 2057 /* 2058 * With some of the RealTek chips, using the checksum offload 2059 * support in conjunction with the autopadding feature results 2060 * in the transmission of corrupt frames. For example, if we 2061 * need to send a really small IP fragment that's less than 60 2062 * bytes in size, and IP header checksumming is enabled, the 2063 * resulting ethernet frame that appears on the wire will 2064 * have garbled payload. To work around this, if TX checksum 2065 * offload is enabled, we always manually pad short frames out 2066 * to the minimum ethernet frame size. We do this by pretending 2067 * the mbuf chain has too many fragments so the coalescing code 2068 * below can assemble the packet into a single buffer that's 2069 * padded out to the mininum frame size. 2070 */ 2071 2072 if (arg.rl_flags && (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) 2073 error = EFBIG; 2074 else 2075 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2076 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2077 2078 if (error && error != EFBIG) { 2079 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", error); 2080 return (ENOBUFS); 2081 } 2082 2083 /* Too many segments to map, coalesce into a single mbuf */ 2084 2085 if (error || arg.rl_maxsegs == 0) { 2086 m_new = m_defrag(*m_head, M_DONTWAIT); 2087 if (m_new == NULL) 2088 return (ENOBUFS); 2089 else 2090 *m_head = m_new; 2091 2092 /* 2093 * Manually pad short frames, and zero the pad space 2094 * to avoid leaking data. 2095 */ 2096 2097 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) { 2098 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 2099 RL_MIN_FRAMELEN - m_new->m_pkthdr.len); 2100 m_new->m_pkthdr.len += RL_MIN_FRAMELEN - 2101 m_new->m_pkthdr.len; 2102 m_new->m_len = m_new->m_pkthdr.len; 2103 } 2104 2105 arg.sc = sc; 2106 arg.rl_idx = *idx; 2107 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2108 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2109 2110 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2111 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2112 if (error) { 2113 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", 2114 error); 2115 return (EFBIG); 2116 } 2117 } 2118 2119 /* 2120 * Insure that the map for this transmission 2121 * is placed at the array index of the last descriptor 2122 * in this chain. (Swap last and first dmamaps.) 2123 */ 2124 sc->rl_ldata.rl_tx_dmamap[*idx] = 2125 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 2126 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 2127 2128 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 2129 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 2130 2131 /* 2132 * Set up hardware VLAN tagging. Note: vlan tag info must 2133 * appear in the first descriptor of a multi-descriptor 2134 * transmission attempt. 2135 */ 2136 if ((*m_head)->m_flags & M_VLANTAG) 2137 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 2138 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2139 RL_TDESC_VLANCTL_TAG); 2140 2141 /* Transfer ownership of packet to the chip. */ 2142 2143 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 2144 htole32(RL_TDESC_CMD_OWN); 2145 if (*idx != arg.rl_idx) 2146 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 2147 htole32(RL_TDESC_CMD_OWN); 2148 2149 RL_DESC_INC(arg.rl_idx); 2150 *idx = arg.rl_idx; 2151 2152 return (0); 2153} 2154 2155static void 2156re_tx_task(arg, npending) 2157 void *arg; 2158 int npending; 2159{ 2160 struct ifnet *ifp; 2161 2162 ifp = arg; 2163 re_start(ifp); 2164 2165 return; 2166} 2167 2168/* 2169 * Main transmit routine for C+ and gigE NICs. 2170 */ 2171static void 2172re_start(ifp) 2173 struct ifnet *ifp; 2174{ 2175 struct rl_softc *sc; 2176 struct mbuf *m_head = NULL; 2177 int idx, queued = 0; 2178 2179 sc = ifp->if_softc; 2180 2181 RL_LOCK(sc); 2182 2183 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 2184 RL_UNLOCK(sc); 2185 return; 2186 } 2187 2188 idx = sc->rl_ldata.rl_tx_prodidx; 2189 2190 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2191 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2192 if (m_head == NULL) 2193 break; 2194 2195 if (re_encap(sc, &m_head, &idx)) { 2196 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2197 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2198 break; 2199 } 2200 2201 /* 2202 * If there's a BPF listener, bounce a copy of this frame 2203 * to him. 2204 */ 2205 BPF_MTAP(ifp, m_head); 2206 2207 queued++; 2208 } 2209 2210 if (queued == 0) { 2211#ifdef RE_TX_MODERATION 2212 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 2213 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2214#endif 2215 RL_UNLOCK(sc); 2216 return; 2217 } 2218 2219 /* Flush the TX descriptors */ 2220 2221 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2222 sc->rl_ldata.rl_tx_list_map, 2223 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2224 2225 sc->rl_ldata.rl_tx_prodidx = idx; 2226 2227 /* 2228 * RealTek put the TX poll request register in a different 2229 * location on the 8169 gigE chip. I don't know why. 2230 */ 2231 2232 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2233 2234#ifdef RE_TX_MODERATION 2235 /* 2236 * Use the countdown timer for interrupt moderation. 2237 * 'TX done' interrupts are disabled. Instead, we reset the 2238 * countdown timer, which will begin counting until it hits 2239 * the value in the TIMERINT register, and then trigger an 2240 * interrupt. Each time we write to the TIMERCNT register, 2241 * the timer count is reset to 0. 2242 */ 2243 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2244#endif 2245 2246 /* 2247 * Set a timeout in case the chip goes out to lunch. 2248 */ 2249 2250 ifp->if_timer = 5; 2251 2252 RL_UNLOCK(sc); 2253 2254 return; 2255} 2256 2257static void 2258re_init(xsc) 2259 void *xsc; 2260{ 2261 struct rl_softc *sc = xsc; 2262 2263 RL_LOCK(sc); 2264 re_init_locked(sc); 2265 RL_UNLOCK(sc); 2266} 2267 2268static void 2269re_init_locked(sc) 2270 struct rl_softc *sc; 2271{ 2272 struct ifnet *ifp = sc->rl_ifp; 2273 struct mii_data *mii; 2274 u_int32_t rxcfg = 0; 2275 union { 2276 uint32_t align_dummy; 2277 u_char eaddr[ETHER_ADDR_LEN]; 2278 } eaddr; 2279 2280 RL_LOCK_ASSERT(sc); 2281 2282 mii = device_get_softc(sc->rl_miibus); 2283 2284 /* 2285 * Cancel pending I/O and free all RX/TX buffers. 2286 */ 2287 re_stop(sc); 2288 2289 /* 2290 * Enable C+ RX and TX mode, as well as VLAN stripping and 2291 * RX checksum offload. We must configure the C+ register 2292 * before all others. 2293 */ 2294 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2295 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2296 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB); 2297 2298 /* 2299 * Init our MAC address. Even though the chipset 2300 * documentation doesn't mention it, we need to enter "Config 2301 * register write enable" mode to modify the ID registers. 2302 */ 2303 /* Copy MAC address on stack to align. */ 2304 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2305 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2306 CSR_WRITE_4(sc, RL_IDR0, 2307 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2308 CSR_WRITE_4(sc, RL_IDR4, 2309 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2310 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2311 2312 /* 2313 * For C+ mode, initialize the RX descriptors and mbufs. 2314 */ 2315 re_rx_list_init(sc); 2316 re_tx_list_init(sc); 2317 2318 /* 2319 * Enable transmit and receive. 2320 */ 2321 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2322 2323 /* 2324 * Set the initial TX and RX configuration. 2325 */ 2326 if (sc->rl_testmode) { 2327 if (sc->rl_type == RL_8169) 2328 CSR_WRITE_4(sc, RL_TXCFG, 2329 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2330 else 2331 CSR_WRITE_4(sc, RL_TXCFG, 2332 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2333 } else 2334 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2335 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2336 2337 /* Set the individual bit to receive frames for this host only. */ 2338 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2339 rxcfg |= RL_RXCFG_RX_INDIV; 2340 2341 /* If we want promiscuous mode, set the allframes bit. */ 2342 if (ifp->if_flags & IFF_PROMISC) 2343 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2344 else 2345 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2346 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2347 2348 /* 2349 * Set capture broadcast bit to capture broadcast frames. 2350 */ 2351 if (ifp->if_flags & IFF_BROADCAST) 2352 rxcfg |= RL_RXCFG_RX_BROAD; 2353 else 2354 rxcfg &= ~RL_RXCFG_RX_BROAD; 2355 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2356 2357 /* 2358 * Program the multicast filter, if necessary. 2359 */ 2360 re_setmulti(sc); 2361 2362#ifdef DEVICE_POLLING 2363 /* 2364 * Disable interrupts if we are polling. 2365 */ 2366 if (ifp->if_capenable & IFCAP_POLLING) 2367 CSR_WRITE_2(sc, RL_IMR, 0); 2368 else /* otherwise ... */ 2369#endif 2370 2371 /* 2372 * Enable interrupts. 2373 */ 2374 if (sc->rl_testmode) 2375 CSR_WRITE_2(sc, RL_IMR, 0); 2376 else 2377 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2378 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2379 2380 /* Set initial TX threshold */ 2381 sc->rl_txthresh = RL_TX_THRESH_INIT; 2382 2383 /* Start RX/TX process. */ 2384 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2385#ifdef notdef 2386 /* Enable receiver and transmitter. */ 2387 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2388#endif 2389 /* 2390 * Load the addresses of the RX and TX lists into the chip. 2391 */ 2392 2393 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2394 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2395 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2396 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2397 2398 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2399 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2400 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2401 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2402 2403 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2404 2405#ifdef RE_TX_MODERATION 2406 /* 2407 * Initialize the timer interrupt register so that 2408 * a timer interrupt will be generated once the timer 2409 * reaches a certain number of ticks. The timer is 2410 * reloaded on each transmit. This gives us TX interrupt 2411 * moderation, which dramatically improves TX frame rate. 2412 */ 2413 if (sc->rl_type == RL_8169) 2414 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2415 else 2416 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2417#endif 2418 2419 /* 2420 * For 8169 gigE NICs, set the max allowed RX packet 2421 * size so we can receive jumbo frames. 2422 */ 2423 if (sc->rl_type == RL_8169) 2424 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2425 2426 if (sc->rl_testmode) 2427 return; 2428 2429 mii_mediachg(mii); 2430 2431 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2432 2433 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2434 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2435 2436 2437 sc->rl_link = 0; 2438 2439 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2440} 2441 2442/* 2443 * Set media options. 2444 */ 2445static int 2446re_ifmedia_upd(ifp) 2447 struct ifnet *ifp; 2448{ 2449 struct rl_softc *sc; 2450 struct mii_data *mii; 2451 2452 sc = ifp->if_softc; 2453 mii = device_get_softc(sc->rl_miibus); 2454 RL_LOCK(sc); 2455 mii_mediachg(mii); 2456 RL_UNLOCK(sc); 2457 2458 return (0); 2459} 2460 2461/* 2462 * Report current media status. 2463 */ 2464static void 2465re_ifmedia_sts(ifp, ifmr) 2466 struct ifnet *ifp; 2467 struct ifmediareq *ifmr; 2468{ 2469 struct rl_softc *sc; 2470 struct mii_data *mii; 2471 2472 sc = ifp->if_softc; 2473 mii = device_get_softc(sc->rl_miibus); 2474 2475 RL_LOCK(sc); 2476 mii_pollstat(mii); 2477 RL_UNLOCK(sc); 2478 ifmr->ifm_active = mii->mii_media_active; 2479 ifmr->ifm_status = mii->mii_media_status; 2480} 2481 2482static int 2483re_ioctl(ifp, command, data) 2484 struct ifnet *ifp; 2485 u_long command; 2486 caddr_t data; 2487{ 2488 struct rl_softc *sc = ifp->if_softc; 2489 struct ifreq *ifr = (struct ifreq *) data; 2490 struct mii_data *mii; 2491 int error = 0; 2492 2493 switch (command) { 2494 case SIOCSIFMTU: 2495 RL_LOCK(sc); 2496 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2497 error = EINVAL; 2498 ifp->if_mtu = ifr->ifr_mtu; 2499 RL_UNLOCK(sc); 2500 break; 2501 case SIOCSIFFLAGS: 2502 RL_LOCK(sc); 2503 if (ifp->if_flags & IFF_UP) 2504 re_init_locked(sc); 2505 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2506 re_stop(sc); 2507 RL_UNLOCK(sc); 2508 break; 2509 case SIOCADDMULTI: 2510 case SIOCDELMULTI: 2511 RL_LOCK(sc); 2512 re_setmulti(sc); 2513 RL_UNLOCK(sc); 2514 break; 2515 case SIOCGIFMEDIA: 2516 case SIOCSIFMEDIA: 2517 mii = device_get_softc(sc->rl_miibus); 2518 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2519 break; 2520 case SIOCSIFCAP: 2521 { 2522 int mask, reinit; 2523 2524 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2525 reinit = 0; 2526#ifdef DEVICE_POLLING 2527 if (mask & IFCAP_POLLING) { 2528 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2529 error = ether_poll_register(re_poll, ifp); 2530 if (error) 2531 return(error); 2532 RL_LOCK(sc); 2533 /* Disable interrupts */ 2534 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2535 ifp->if_capenable |= IFCAP_POLLING; 2536 RL_UNLOCK(sc); 2537 2538 } else { 2539 error = ether_poll_deregister(ifp); 2540 /* Enable interrupts. */ 2541 RL_LOCK(sc); 2542 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2543 ifp->if_capenable &= ~IFCAP_POLLING; 2544 RL_UNLOCK(sc); 2545 } 2546 } 2547#endif /* DEVICE_POLLING */ 2548 if (mask & IFCAP_HWCSUM) { 2549 ifp->if_capenable ^= IFCAP_HWCSUM; 2550 if (ifp->if_capenable & IFCAP_TXCSUM) 2551 ifp->if_hwassist |= RE_CSUM_FEATURES; 2552 else 2553 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2554 reinit = 1; 2555 } 2556 if (mask & IFCAP_VLAN_HWTAGGING) { 2557 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2558 reinit = 1; 2559 } 2560 if (mask & IFCAP_TSO4) { 2561 ifp->if_capenable ^= IFCAP_TSO4; 2562 if ((IFCAP_TSO4 & ifp->if_capenable) && 2563 (IFCAP_TSO4 & ifp->if_capabilities)) 2564 ifp->if_hwassist |= CSUM_TSO; 2565 else 2566 ifp->if_hwassist &= ~CSUM_TSO; 2567 } 2568 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2569 re_init(sc); 2570 VLAN_CAPABILITIES(ifp); 2571 } 2572 break; 2573 default: 2574 error = ether_ioctl(ifp, command, data); 2575 break; 2576 } 2577 2578 return (error); 2579} 2580 2581static void 2582re_watchdog(ifp) 2583 struct ifnet *ifp; 2584{ 2585 struct rl_softc *sc; 2586 2587 sc = ifp->if_softc; 2588 RL_LOCK(sc); 2589 if_printf(ifp, "watchdog timeout\n"); 2590 ifp->if_oerrors++; 2591 2592 re_txeof(sc); 2593 re_rxeof(sc); 2594 re_init_locked(sc); 2595 2596 RL_UNLOCK(sc); 2597} 2598 2599/* 2600 * Stop the adapter and free any mbufs allocated to the 2601 * RX and TX lists. 2602 */ 2603static void 2604re_stop(sc) 2605 struct rl_softc *sc; 2606{ 2607 register int i; 2608 struct ifnet *ifp; 2609 2610 RL_LOCK_ASSERT(sc); 2611 2612 ifp = sc->rl_ifp; 2613 ifp->if_timer = 0; 2614 2615 callout_stop(&sc->rl_stat_callout); 2616 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2617 2618 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2619 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2620 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2621 2622 if (sc->rl_head != NULL) { 2623 m_freem(sc->rl_head); 2624 sc->rl_head = sc->rl_tail = NULL; 2625 } 2626 2627 /* Free the TX list buffers. */ 2628 2629 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2630 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2631 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2632 sc->rl_ldata.rl_tx_dmamap[i]); 2633 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2634 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2635 } 2636 } 2637 2638 /* Free the RX list buffers. */ 2639 2640 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2641 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2642 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2643 sc->rl_ldata.rl_rx_dmamap[i]); 2644 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2645 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2646 } 2647 } 2648} 2649 2650/* 2651 * Device suspend routine. Stop the interface and save some PCI 2652 * settings in case the BIOS doesn't restore them properly on 2653 * resume. 2654 */ 2655static int 2656re_suspend(dev) 2657 device_t dev; 2658{ 2659 struct rl_softc *sc; 2660 2661 sc = device_get_softc(dev); 2662 2663 RL_LOCK(sc); 2664 re_stop(sc); 2665 sc->suspended = 1; 2666 RL_UNLOCK(sc); 2667 2668 return (0); 2669} 2670 2671/* 2672 * Device resume routine. Restore some PCI settings in case the BIOS 2673 * doesn't, re-enable busmastering, and restart the interface if 2674 * appropriate. 2675 */ 2676static int 2677re_resume(dev) 2678 device_t dev; 2679{ 2680 struct rl_softc *sc; 2681 struct ifnet *ifp; 2682 2683 sc = device_get_softc(dev); 2684 2685 RL_LOCK(sc); 2686 2687 ifp = sc->rl_ifp; 2688 2689 /* reinitialize interface if necessary */ 2690 if (ifp->if_flags & IFF_UP) 2691 re_init_locked(sc); 2692 2693 sc->suspended = 0; 2694 RL_UNLOCK(sc); 2695 2696 return (0); 2697} 2698 2699/* 2700 * Stop all chip I/O so that the kernel's probe routines don't 2701 * get confused by errant DMAs when rebooting. 2702 */ 2703static void 2704re_shutdown(dev) 2705 device_t dev; 2706{ 2707 struct rl_softc *sc; 2708 2709 sc = device_get_softc(dev); 2710 2711 RL_LOCK(sc); 2712 re_stop(sc); 2713 /* 2714 * Mark interface as down since otherwise we will panic if 2715 * interrupt comes in later on, which can happen in some 2716 * cases. 2717 */ 2718 sc->rl_ifp->if_flags &= ~IFF_UP; 2719 RL_UNLOCK(sc); 2720} 2721