if_re.c revision 162321
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 162321 2006-09-15 15:16:12Z glebius $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149MODULE_DEPEND(re, pci, 1, 1, 1); 150MODULE_DEPEND(re, ether, 1, 1, 1); 151MODULE_DEPEND(re, miibus, 1, 1, 1); 152 153/* "device miibus" required. See GENERIC if you get errors here. */ 154#include "miibus_if.h" 155 156/* 157 * Default to using PIO access for this driver. 158 */ 159#define RE_USEIOSPACE 160 161#include <pci/if_rlreg.h> 162 163#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 164 165/* 166 * Various supported device vendors/types and their names. 167 */ 168static struct rl_type re_devs[] = { 169 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 171 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 172 "RealTek 8139C+ 10/100BaseTX" }, 173 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 174 "RealTek 8101E PCIe 10/100baseTX" }, 175 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 176 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 178 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 180 "RealTek 8169 Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 182 "RealTek 8169S Single-chip Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 184 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 186 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 188 "RealTek 8110S Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }, 195 { 0, 0, 0, NULL } 196}; 197 198static struct rl_hwrev re_hwrevs[] = { 199 { RL_HWREV_8139, RL_8139, "" }, 200 { RL_HWREV_8139A, RL_8139, "A" }, 201 { RL_HWREV_8139AG, RL_8139, "A-G" }, 202 { RL_HWREV_8139B, RL_8139, "B" }, 203 { RL_HWREV_8130, RL_8139, "8130" }, 204 { RL_HWREV_8139C, RL_8139, "C" }, 205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 207 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 208 { RL_HWREV_8169, RL_8169, "8169"}, 209 { RL_HWREV_8169S, RL_8169, "8169S"}, 210 { RL_HWREV_8110S, RL_8169, "8110S"}, 211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 213 { RL_HWREV_8100, RL_8139, "8100"}, 214 { RL_HWREV_8101, RL_8139, "8101"}, 215 { RL_HWREV_8100E, RL_8169, "8100E"}, 216 { RL_HWREV_8101E, RL_8169, "8101E"}, 217 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 218 { 0, 0, NULL } 219}; 220 221static int re_probe (device_t); 222static int re_attach (device_t); 223static int re_detach (device_t); 224 225static int re_encap (struct rl_softc *, struct mbuf **, int *); 226 227static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 228static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 229 bus_size_t, int); 230static int re_allocmem (device_t, struct rl_softc *); 231static int re_newbuf (struct rl_softc *, int, struct mbuf *); 232static int re_rx_list_init (struct rl_softc *); 233static int re_tx_list_init (struct rl_softc *); 234#ifdef RE_FIXUP_RX 235static __inline void re_fixup_rx 236 (struct mbuf *); 237#endif 238static int re_rxeof (struct rl_softc *); 239static void re_txeof (struct rl_softc *); 240#ifdef DEVICE_POLLING 241static void re_poll (struct ifnet *, enum poll_cmd, int); 242static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 243#endif 244static void re_intr (void *); 245static void re_tick (void *); 246static void re_tx_task (void *, int); 247static void re_int_task (void *, int); 248static void re_start (struct ifnet *); 249static int re_ioctl (struct ifnet *, u_long, caddr_t); 250static void re_init (void *); 251static void re_init_locked (struct rl_softc *); 252static void re_stop (struct rl_softc *); 253static void re_watchdog (struct ifnet *); 254static int re_suspend (device_t); 255static int re_resume (device_t); 256static void re_shutdown (device_t); 257static int re_ifmedia_upd (struct ifnet *); 258static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 259 260static void re_eeprom_putbyte (struct rl_softc *, int); 261static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 262static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 263static int re_gmii_readreg (device_t, int, int); 264static int re_gmii_writereg (device_t, int, int, int); 265 266static int re_miibus_readreg (device_t, int, int); 267static int re_miibus_writereg (device_t, int, int, int); 268static void re_miibus_statchg (device_t); 269 270static void re_setmulti (struct rl_softc *); 271static void re_reset (struct rl_softc *); 272 273#ifdef RE_DIAG 274static int re_diag (struct rl_softc *); 275#endif 276 277#ifdef RE_USEIOSPACE 278#define RL_RES SYS_RES_IOPORT 279#define RL_RID RL_PCI_LOIO 280#else 281#define RL_RES SYS_RES_MEMORY 282#define RL_RID RL_PCI_LOMEM 283#endif 284 285static device_method_t re_methods[] = { 286 /* Device interface */ 287 DEVMETHOD(device_probe, re_probe), 288 DEVMETHOD(device_attach, re_attach), 289 DEVMETHOD(device_detach, re_detach), 290 DEVMETHOD(device_suspend, re_suspend), 291 DEVMETHOD(device_resume, re_resume), 292 DEVMETHOD(device_shutdown, re_shutdown), 293 294 /* bus interface */ 295 DEVMETHOD(bus_print_child, bus_generic_print_child), 296 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 297 298 /* MII interface */ 299 DEVMETHOD(miibus_readreg, re_miibus_readreg), 300 DEVMETHOD(miibus_writereg, re_miibus_writereg), 301 DEVMETHOD(miibus_statchg, re_miibus_statchg), 302 303 { 0, 0 } 304}; 305 306static driver_t re_driver = { 307 "re", 308 re_methods, 309 sizeof(struct rl_softc) 310}; 311 312static devclass_t re_devclass; 313 314DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 315DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 316DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 317 318#define EE_SET(x) \ 319 CSR_WRITE_1(sc, RL_EECMD, \ 320 CSR_READ_1(sc, RL_EECMD) | x) 321 322#define EE_CLR(x) \ 323 CSR_WRITE_1(sc, RL_EECMD, \ 324 CSR_READ_1(sc, RL_EECMD) & ~x) 325 326/* 327 * Send a read command and address to the EEPROM, check for ACK. 328 */ 329static void 330re_eeprom_putbyte(sc, addr) 331 struct rl_softc *sc; 332 int addr; 333{ 334 register int d, i; 335 336 d = addr | (RL_9346_READ << sc->rl_eewidth); 337 338 /* 339 * Feed in each bit and strobe the clock. 340 */ 341 342 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 343 if (d & i) { 344 EE_SET(RL_EE_DATAIN); 345 } else { 346 EE_CLR(RL_EE_DATAIN); 347 } 348 DELAY(100); 349 EE_SET(RL_EE_CLK); 350 DELAY(150); 351 EE_CLR(RL_EE_CLK); 352 DELAY(100); 353 } 354 355 return; 356} 357 358/* 359 * Read a word of data stored in the EEPROM at address 'addr.' 360 */ 361static void 362re_eeprom_getword(sc, addr, dest) 363 struct rl_softc *sc; 364 int addr; 365 u_int16_t *dest; 366{ 367 register int i; 368 u_int16_t word = 0; 369 370 /* 371 * Send address of word we want to read. 372 */ 373 re_eeprom_putbyte(sc, addr); 374 375 /* 376 * Start reading bits from EEPROM. 377 */ 378 for (i = 0x8000; i; i >>= 1) { 379 EE_SET(RL_EE_CLK); 380 DELAY(100); 381 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 382 word |= i; 383 EE_CLR(RL_EE_CLK); 384 DELAY(100); 385 } 386 387 *dest = word; 388 389 return; 390} 391 392/* 393 * Read a sequence of words from the EEPROM. 394 */ 395static void 396re_read_eeprom(sc, dest, off, cnt) 397 struct rl_softc *sc; 398 caddr_t dest; 399 int off; 400 int cnt; 401{ 402 int i; 403 u_int16_t word = 0, *ptr; 404 405 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 406 407 DELAY(100); 408 409 for (i = 0; i < cnt; i++) { 410 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 411 re_eeprom_getword(sc, off + i, &word); 412 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 413 ptr = (u_int16_t *)(dest + (i * 2)); 414 *ptr = word; 415 } 416 417 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 418 419 return; 420} 421 422static int 423re_gmii_readreg(dev, phy, reg) 424 device_t dev; 425 int phy, reg; 426{ 427 struct rl_softc *sc; 428 u_int32_t rval; 429 int i; 430 431 if (phy != 1) 432 return (0); 433 434 sc = device_get_softc(dev); 435 436 /* Let the rgephy driver read the GMEDIASTAT register */ 437 438 if (reg == RL_GMEDIASTAT) { 439 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 440 return (rval); 441 } 442 443 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 444 DELAY(1000); 445 446 for (i = 0; i < RL_TIMEOUT; i++) { 447 rval = CSR_READ_4(sc, RL_PHYAR); 448 if (rval & RL_PHYAR_BUSY) 449 break; 450 DELAY(100); 451 } 452 453 if (i == RL_TIMEOUT) { 454 device_printf(sc->rl_dev, "PHY read failed\n"); 455 return (0); 456 } 457 458 return (rval & RL_PHYAR_PHYDATA); 459} 460 461static int 462re_gmii_writereg(dev, phy, reg, data) 463 device_t dev; 464 int phy, reg, data; 465{ 466 struct rl_softc *sc; 467 u_int32_t rval; 468 int i; 469 470 sc = device_get_softc(dev); 471 472 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 473 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 474 DELAY(1000); 475 476 for (i = 0; i < RL_TIMEOUT; i++) { 477 rval = CSR_READ_4(sc, RL_PHYAR); 478 if (!(rval & RL_PHYAR_BUSY)) 479 break; 480 DELAY(100); 481 } 482 483 if (i == RL_TIMEOUT) { 484 device_printf(sc->rl_dev, "PHY write failed\n"); 485 return (0); 486 } 487 488 return (0); 489} 490 491static int 492re_miibus_readreg(dev, phy, reg) 493 device_t dev; 494 int phy, reg; 495{ 496 struct rl_softc *sc; 497 u_int16_t rval = 0; 498 u_int16_t re8139_reg = 0; 499 500 sc = device_get_softc(dev); 501 502 if (sc->rl_type == RL_8169) { 503 rval = re_gmii_readreg(dev, phy, reg); 504 return (rval); 505 } 506 507 /* Pretend the internal PHY is only at address 0 */ 508 if (phy) { 509 return (0); 510 } 511 switch (reg) { 512 case MII_BMCR: 513 re8139_reg = RL_BMCR; 514 break; 515 case MII_BMSR: 516 re8139_reg = RL_BMSR; 517 break; 518 case MII_ANAR: 519 re8139_reg = RL_ANAR; 520 break; 521 case MII_ANER: 522 re8139_reg = RL_ANER; 523 break; 524 case MII_ANLPAR: 525 re8139_reg = RL_LPAR; 526 break; 527 case MII_PHYIDR1: 528 case MII_PHYIDR2: 529 return (0); 530 /* 531 * Allow the rlphy driver to read the media status 532 * register. If we have a link partner which does not 533 * support NWAY, this is the register which will tell 534 * us the results of parallel detection. 535 */ 536 case RL_MEDIASTAT: 537 rval = CSR_READ_1(sc, RL_MEDIASTAT); 538 return (rval); 539 default: 540 device_printf(sc->rl_dev, "bad phy register\n"); 541 return (0); 542 } 543 rval = CSR_READ_2(sc, re8139_reg); 544 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 545 /* 8139C+ has different bit layout. */ 546 rval &= ~(BMCR_LOOP | BMCR_ISO); 547 } 548 return (rval); 549} 550 551static int 552re_miibus_writereg(dev, phy, reg, data) 553 device_t dev; 554 int phy, reg, data; 555{ 556 struct rl_softc *sc; 557 u_int16_t re8139_reg = 0; 558 int rval = 0; 559 560 sc = device_get_softc(dev); 561 562 if (sc->rl_type == RL_8169) { 563 rval = re_gmii_writereg(dev, phy, reg, data); 564 return (rval); 565 } 566 567 /* Pretend the internal PHY is only at address 0 */ 568 if (phy) 569 return (0); 570 571 switch (reg) { 572 case MII_BMCR: 573 re8139_reg = RL_BMCR; 574 if (sc->rl_type == RL_8139CPLUS) { 575 /* 8139C+ has different bit layout. */ 576 data &= ~(BMCR_LOOP | BMCR_ISO); 577 } 578 break; 579 case MII_BMSR: 580 re8139_reg = RL_BMSR; 581 break; 582 case MII_ANAR: 583 re8139_reg = RL_ANAR; 584 break; 585 case MII_ANER: 586 re8139_reg = RL_ANER; 587 break; 588 case MII_ANLPAR: 589 re8139_reg = RL_LPAR; 590 break; 591 case MII_PHYIDR1: 592 case MII_PHYIDR2: 593 return (0); 594 break; 595 default: 596 device_printf(sc->rl_dev, "bad phy register\n"); 597 return (0); 598 } 599 CSR_WRITE_2(sc, re8139_reg, data); 600 return (0); 601} 602 603static void 604re_miibus_statchg(dev) 605 device_t dev; 606{ 607 608} 609 610/* 611 * Program the 64-bit multicast hash filter. 612 */ 613static void 614re_setmulti(sc) 615 struct rl_softc *sc; 616{ 617 struct ifnet *ifp; 618 int h = 0; 619 u_int32_t hashes[2] = { 0, 0 }; 620 struct ifmultiaddr *ifma; 621 u_int32_t rxfilt; 622 int mcnt = 0; 623 624 RL_LOCK_ASSERT(sc); 625 626 ifp = sc->rl_ifp; 627 628 rxfilt = CSR_READ_4(sc, RL_RXCFG); 629 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 rxfilt |= RL_RXCFG_RX_MULTI; 632 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 633 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 634 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 635 return; 636 } 637 638 /* first, zot all the existing hash bits */ 639 CSR_WRITE_4(sc, RL_MAR0, 0); 640 CSR_WRITE_4(sc, RL_MAR4, 0); 641 642 /* now program new ones */ 643 IF_ADDR_LOCK(ifp); 644 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 645 if (ifma->ifma_addr->sa_family != AF_LINK) 646 continue; 647 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 648 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 649 if (h < 32) 650 hashes[0] |= (1 << h); 651 else 652 hashes[1] |= (1 << (h - 32)); 653 mcnt++; 654 } 655 IF_ADDR_UNLOCK(ifp); 656 657 if (mcnt) 658 rxfilt |= RL_RXCFG_RX_MULTI; 659 else 660 rxfilt &= ~RL_RXCFG_RX_MULTI; 661 662 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 663 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 664 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 665} 666 667static void 668re_reset(sc) 669 struct rl_softc *sc; 670{ 671 register int i; 672 673 RL_LOCK_ASSERT(sc); 674 675 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 676 677 for (i = 0; i < RL_TIMEOUT; i++) { 678 DELAY(10); 679 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 680 break; 681 } 682 if (i == RL_TIMEOUT) 683 device_printf(sc->rl_dev, "reset never completed!\n"); 684 685 CSR_WRITE_1(sc, 0x82, 1); 686} 687 688#ifdef RE_DIAG 689 690/* 691 * The following routine is designed to test for a defect on some 692 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 693 * lines connected to the bus, however for a 32-bit only card, they 694 * should be pulled high. The result of this defect is that the 695 * NIC will not work right if you plug it into a 64-bit slot: DMA 696 * operations will be done with 64-bit transfers, which will fail 697 * because the 64-bit data lines aren't connected. 698 * 699 * There's no way to work around this (short of talking a soldering 700 * iron to the board), however we can detect it. The method we use 701 * here is to put the NIC into digital loopback mode, set the receiver 702 * to promiscuous mode, and then try to send a frame. We then compare 703 * the frame data we sent to what was received. If the data matches, 704 * then the NIC is working correctly, otherwise we know the user has 705 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 706 * slot. In the latter case, there's no way the NIC can work correctly, 707 * so we print out a message on the console and abort the device attach. 708 */ 709 710static int 711re_diag(sc) 712 struct rl_softc *sc; 713{ 714 struct ifnet *ifp = sc->rl_ifp; 715 struct mbuf *m0; 716 struct ether_header *eh; 717 struct rl_desc *cur_rx; 718 u_int16_t status; 719 u_int32_t rxstat; 720 int total_len, i, error = 0, phyaddr; 721 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 722 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 723 724 /* Allocate a single mbuf */ 725 MGETHDR(m0, M_DONTWAIT, MT_DATA); 726 if (m0 == NULL) 727 return (ENOBUFS); 728 729 RL_LOCK(sc); 730 731 /* 732 * Initialize the NIC in test mode. This sets the chip up 733 * so that it can send and receive frames, but performs the 734 * following special functions: 735 * - Puts receiver in promiscuous mode 736 * - Enables digital loopback mode 737 * - Leaves interrupts turned off 738 */ 739 740 ifp->if_flags |= IFF_PROMISC; 741 sc->rl_testmode = 1; 742 re_reset(sc); 743 re_init_locked(sc); 744 sc->rl_link = 1; 745 if (sc->rl_type == RL_8169) 746 phyaddr = 1; 747 else 748 phyaddr = 0; 749 750 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 751 for (i = 0; i < RL_TIMEOUT; i++) { 752 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 753 if (!(status & BMCR_RESET)) 754 break; 755 } 756 757 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 758 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 759 760 DELAY(100000); 761 762 /* Put some data in the mbuf */ 763 764 eh = mtod(m0, struct ether_header *); 765 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 766 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 767 eh->ether_type = htons(ETHERTYPE_IP); 768 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 769 770 /* 771 * Queue the packet, start transmission. 772 * Note: IF_HANDOFF() ultimately calls re_start() for us. 773 */ 774 775 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 776 RL_UNLOCK(sc); 777 /* XXX: re_diag must not be called when in ALTQ mode */ 778 IF_HANDOFF(&ifp->if_snd, m0, ifp); 779 RL_LOCK(sc); 780 m0 = NULL; 781 782 /* Wait for it to propagate through the chip */ 783 784 DELAY(100000); 785 for (i = 0; i < RL_TIMEOUT; i++) { 786 status = CSR_READ_2(sc, RL_ISR); 787 CSR_WRITE_2(sc, RL_ISR, status); 788 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 789 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 790 break; 791 DELAY(10); 792 } 793 794 if (i == RL_TIMEOUT) { 795 device_printf(sc->rl_dev, 796 "diagnostic failed, failed to receive packet in" 797 " loopback mode\n"); 798 error = EIO; 799 goto done; 800 } 801 802 /* 803 * The packet should have been dumped into the first 804 * entry in the RX DMA ring. Grab it from there. 805 */ 806 807 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 808 sc->rl_ldata.rl_rx_list_map, 809 BUS_DMASYNC_POSTREAD); 810 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 811 sc->rl_ldata.rl_rx_dmamap[0], 812 BUS_DMASYNC_POSTWRITE); 813 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 814 sc->rl_ldata.rl_rx_dmamap[0]); 815 816 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 817 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 818 eh = mtod(m0, struct ether_header *); 819 820 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 821 total_len = RL_RXBYTES(cur_rx); 822 rxstat = le32toh(cur_rx->rl_cmdstat); 823 824 if (total_len != ETHER_MIN_LEN) { 825 device_printf(sc->rl_dev, 826 "diagnostic failed, received short packet\n"); 827 error = EIO; 828 goto done; 829 } 830 831 /* Test that the received packet data matches what we sent. */ 832 833 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 834 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 835 ntohs(eh->ether_type) != ETHERTYPE_IP) { 836 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 837 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 838 dst, ":", src, ":", ETHERTYPE_IP); 839 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 840 eh->ether_dhost, ":", eh->ether_shost, ":", 841 ntohs(eh->ether_type)); 842 device_printf(sc->rl_dev, "You may have a defective 32-bit " 843 "NIC plugged into a 64-bit PCI slot.\n"); 844 device_printf(sc->rl_dev, "Please re-install the NIC in a " 845 "32-bit slot for proper operation.\n"); 846 device_printf(sc->rl_dev, "Read the re(4) man page for more " 847 "details.\n"); 848 error = EIO; 849 } 850 851done: 852 /* Turn interface off, release resources */ 853 854 sc->rl_testmode = 0; 855 sc->rl_link = 0; 856 ifp->if_flags &= ~IFF_PROMISC; 857 re_stop(sc); 858 if (m0 != NULL) 859 m_freem(m0); 860 861 RL_UNLOCK(sc); 862 863 return (error); 864} 865 866#endif 867 868/* 869 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 870 * IDs against our list and return a device name if we find a match. 871 */ 872static int 873re_probe(dev) 874 device_t dev; 875{ 876 struct rl_type *t; 877 struct rl_softc *sc; 878 int rid; 879 u_int32_t hwrev; 880 881 t = re_devs; 882 sc = device_get_softc(dev); 883 884 while (t->rl_name != NULL) { 885 if ((pci_get_vendor(dev) == t->rl_vid) && 886 (pci_get_device(dev) == t->rl_did)) { 887 /* 888 * Only attach to rev. 3 of the Linksys EG1032 adapter. 889 * Rev. 2 i supported by sk(4). 890 */ 891 if ((t->rl_vid == LINKSYS_VENDORID) && 892 (t->rl_did == LINKSYS_DEVICEID_EG1032) && 893 (pci_get_subdevice(dev) != 894 LINKSYS_SUBDEVICE_EG1032_REV3)) { 895 t++; 896 continue; 897 } 898 899 /* 900 * Temporarily map the I/O space 901 * so we can read the chip ID register. 902 */ 903 rid = RL_RID; 904 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 905 RF_ACTIVE); 906 if (sc->rl_res == NULL) { 907 device_printf(dev, 908 "couldn't map ports/memory\n"); 909 return (ENXIO); 910 } 911 sc->rl_btag = rman_get_bustag(sc->rl_res); 912 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 913 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 914 bus_release_resource(dev, RL_RES, 915 RL_RID, sc->rl_res); 916 if (t->rl_basetype == hwrev) { 917 device_set_desc(dev, t->rl_name); 918 return (BUS_PROBE_DEFAULT); 919 } 920 } 921 t++; 922 } 923 924 return (ENXIO); 925} 926 927/* 928 * This routine takes the segment list provided as the result of 929 * a bus_dma_map_load() operation and assigns the addresses/lengths 930 * to RealTek DMA descriptors. This can be called either by the RX 931 * code or the TX code. In the RX case, we'll probably wind up mapping 932 * at most one segment. For the TX case, there could be any number of 933 * segments since TX packets may span multiple mbufs. In either case, 934 * if the number of segments is larger than the rl_maxsegs limit 935 * specified by the caller, we abort the mapping operation. Sadly, 936 * whoever designed the buffer mapping API did not provide a way to 937 * return an error from here, so we have to fake it a bit. 938 */ 939 940static void 941re_dma_map_desc(arg, segs, nseg, mapsize, error) 942 void *arg; 943 bus_dma_segment_t *segs; 944 int nseg; 945 bus_size_t mapsize; 946 int error; 947{ 948 struct rl_dmaload_arg *ctx; 949 struct rl_desc *d = NULL; 950 int i = 0, idx; 951 u_int32_t cmdstat; 952 int totlen = 0; 953 954 if (error) 955 return; 956 957 ctx = arg; 958 959 /* Signal error to caller if there's too many segments */ 960 if (nseg > ctx->rl_maxsegs) { 961 ctx->rl_maxsegs = 0; 962 return; 963 } 964 965 /* 966 * Map the segment array into descriptors. Note that we set the 967 * start-of-frame and end-of-frame markers for either TX or RX, but 968 * they really only have meaning in the TX case. (In the RX case, 969 * it's the chip that tells us where packets begin and end.) 970 * We also keep track of the end of the ring and set the 971 * end-of-ring bits as needed, and we set the ownership bits 972 * in all except the very first descriptor. (The caller will 973 * set this descriptor later when it start transmission or 974 * reception.) 975 */ 976 idx = ctx->rl_idx; 977 for (;;) { 978 d = &ctx->rl_ring[idx]; 979 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 980 ctx->rl_maxsegs = 0; 981 return; 982 } 983 cmdstat = segs[i].ds_len; 984 totlen += segs[i].ds_len; 985 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 986 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 987 if (i == 0) 988 cmdstat |= RL_TDESC_CMD_SOF; 989 else 990 cmdstat |= RL_TDESC_CMD_OWN; 991 if (idx == (RL_RX_DESC_CNT - 1)) 992 cmdstat |= RL_TDESC_CMD_EOR; 993 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 994 i++; 995 if (i == nseg) 996 break; 997 RL_DESC_INC(idx); 998 } 999 1000 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 1001 ctx->rl_maxsegs = nseg; 1002 ctx->rl_idx = idx; 1003} 1004 1005/* 1006 * Map a single buffer address. 1007 */ 1008 1009static void 1010re_dma_map_addr(arg, segs, nseg, error) 1011 void *arg; 1012 bus_dma_segment_t *segs; 1013 int nseg; 1014 int error; 1015{ 1016 bus_addr_t *addr; 1017 1018 if (error) 1019 return; 1020 1021 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1022 addr = arg; 1023 *addr = segs->ds_addr; 1024} 1025 1026static int 1027re_allocmem(dev, sc) 1028 device_t dev; 1029 struct rl_softc *sc; 1030{ 1031 int error; 1032 int nseg; 1033 int i; 1034 1035 /* 1036 * Allocate map for RX mbufs. 1037 */ 1038 nseg = 32; 1039 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 1040 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1041 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 1042 NULL, NULL, &sc->rl_ldata.rl_mtag); 1043 if (error) { 1044 device_printf(dev, "could not allocate dma tag\n"); 1045 return (ENOMEM); 1046 } 1047 1048 /* 1049 * Allocate map for TX descriptor list. 1050 */ 1051 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1052 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1053 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1054 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1055 if (error) { 1056 device_printf(dev, "could not allocate dma tag\n"); 1057 return (ENOMEM); 1058 } 1059 1060 /* Allocate DMA'able memory for the TX ring */ 1061 1062 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1063 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1064 &sc->rl_ldata.rl_tx_list_map); 1065 if (error) 1066 return (ENOMEM); 1067 1068 /* Load the map for the TX ring. */ 1069 1070 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1071 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1072 RL_TX_LIST_SZ, re_dma_map_addr, 1073 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1074 1075 /* Create DMA maps for TX buffers */ 1076 1077 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1078 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1079 &sc->rl_ldata.rl_tx_dmamap[i]); 1080 if (error) { 1081 device_printf(dev, "can't create DMA map for TX\n"); 1082 return (ENOMEM); 1083 } 1084 } 1085 1086 /* 1087 * Allocate map for RX descriptor list. 1088 */ 1089 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1090 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1091 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1092 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1093 if (error) { 1094 device_printf(dev, "could not allocate dma tag\n"); 1095 return (ENOMEM); 1096 } 1097 1098 /* Allocate DMA'able memory for the RX ring */ 1099 1100 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1101 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1102 &sc->rl_ldata.rl_rx_list_map); 1103 if (error) 1104 return (ENOMEM); 1105 1106 /* Load the map for the RX ring. */ 1107 1108 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1109 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1110 RL_RX_LIST_SZ, re_dma_map_addr, 1111 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1112 1113 /* Create DMA maps for RX buffers */ 1114 1115 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1116 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1117 &sc->rl_ldata.rl_rx_dmamap[i]); 1118 if (error) { 1119 device_printf(dev, "can't create DMA map for RX\n"); 1120 return (ENOMEM); 1121 } 1122 } 1123 1124 return (0); 1125} 1126 1127/* 1128 * Attach the interface. Allocate softc structures, do ifmedia 1129 * setup and ethernet/BPF attach. 1130 */ 1131static int 1132re_attach(dev) 1133 device_t dev; 1134{ 1135 u_char eaddr[ETHER_ADDR_LEN]; 1136 u_int16_t as[ETHER_ADDR_LEN / 2]; 1137 struct rl_softc *sc; 1138 struct ifnet *ifp; 1139 struct rl_hwrev *hw_rev; 1140 int hwrev; 1141 u_int16_t re_did = 0; 1142 int error = 0, rid, i; 1143 1144 sc = device_get_softc(dev); 1145 sc->rl_dev = dev; 1146 1147 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1148 MTX_DEF); 1149 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1150 1151 /* 1152 * Map control/status registers. 1153 */ 1154 pci_enable_busmaster(dev); 1155 1156 rid = RL_RID; 1157 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1158 RF_ACTIVE); 1159 1160 if (sc->rl_res == NULL) { 1161 device_printf(dev, "couldn't map ports/memory\n"); 1162 error = ENXIO; 1163 goto fail; 1164 } 1165 1166 sc->rl_btag = rman_get_bustag(sc->rl_res); 1167 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1168 1169 /* Allocate interrupt */ 1170 rid = 0; 1171 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1172 RF_SHAREABLE | RF_ACTIVE); 1173 1174 if (sc->rl_irq == NULL) { 1175 device_printf(dev, "couldn't map interrupt\n"); 1176 error = ENXIO; 1177 goto fail; 1178 } 1179 1180 /* Reset the adapter. */ 1181 RL_LOCK(sc); 1182 re_reset(sc); 1183 RL_UNLOCK(sc); 1184 1185 hw_rev = re_hwrevs; 1186 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1187 while (hw_rev->rl_desc != NULL) { 1188 if (hw_rev->rl_rev == hwrev) { 1189 sc->rl_type = hw_rev->rl_type; 1190 break; 1191 } 1192 hw_rev++; 1193 } 1194 1195 sc->rl_eewidth = 6; 1196 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1197 if (re_did != 0x8129) 1198 sc->rl_eewidth = 8; 1199 1200 /* 1201 * Get station address from the EEPROM. 1202 */ 1203 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1204 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1205 as[i] = le16toh(as[i]); 1206 bcopy(as, eaddr, sizeof(eaddr)); 1207 1208 if (sc->rl_type == RL_8169) { 1209 /* Set RX length mask */ 1210 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1211 sc->rl_txstart = RL_GTXSTART; 1212 } else { 1213 /* Set RX length mask */ 1214 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1215 sc->rl_txstart = RL_TXSTART; 1216 } 1217 1218 /* 1219 * Allocate the parent bus DMA tag appropriate for PCI. 1220 */ 1221#define RL_NSEG_NEW 32 1222 error = bus_dma_tag_create(NULL, /* parent */ 1223 1, 0, /* alignment, boundary */ 1224 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1225 BUS_SPACE_MAXADDR, /* highaddr */ 1226 NULL, NULL, /* filter, filterarg */ 1227 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1228 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1229 BUS_DMA_ALLOCNOW, /* flags */ 1230 NULL, NULL, /* lockfunc, lockarg */ 1231 &sc->rl_parent_tag); 1232 if (error) 1233 goto fail; 1234 1235 error = re_allocmem(dev, sc); 1236 1237 if (error) 1238 goto fail; 1239 1240 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1241 if (ifp == NULL) { 1242 device_printf(dev, "can not if_alloc()\n"); 1243 error = ENOSPC; 1244 goto fail; 1245 } 1246 1247 /* Do MII setup */ 1248 if (mii_phy_probe(dev, &sc->rl_miibus, 1249 re_ifmedia_upd, re_ifmedia_sts)) { 1250 device_printf(dev, "MII without any phy!\n"); 1251 error = ENXIO; 1252 goto fail; 1253 } 1254 1255 ifp->if_softc = sc; 1256 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1257 ifp->if_mtu = ETHERMTU; 1258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1259 ifp->if_ioctl = re_ioctl; 1260 ifp->if_capabilities = IFCAP_VLAN_MTU; 1261 ifp->if_start = re_start; 1262 ifp->if_hwassist = RE_CSUM_FEATURES; 1263 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1264 ifp->if_capenable = ifp->if_capabilities; 1265#ifdef DEVICE_POLLING 1266 ifp->if_capabilities |= IFCAP_POLLING; 1267#endif 1268 ifp->if_watchdog = re_watchdog; 1269 ifp->if_init = re_init; 1270 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1271 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1272 IFQ_SET_READY(&ifp->if_snd); 1273 1274 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1275 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1276 1277 /* 1278 * Call MI attach routine. 1279 */ 1280 ether_ifattach(ifp, eaddr); 1281 1282#ifdef RE_DIAG 1283 /* 1284 * Perform hardware diagnostic on the original RTL8169. 1285 * Some 32-bit cards were incorrectly wired and would 1286 * malfunction if plugged into a 64-bit slot. 1287 */ 1288 1289 if (hwrev == RL_HWREV_8169) { 1290 error = re_diag(sc); 1291 if (error) { 1292 device_printf(dev, 1293 "attach aborted due to hardware diag failure\n"); 1294 ether_ifdetach(ifp); 1295 goto fail; 1296 } 1297 } 1298#endif 1299 1300 /* Hook interrupt last to avoid having to lock softc */ 1301 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE | 1302 INTR_FAST, re_intr, sc, &sc->rl_intrhand); 1303 if (error) { 1304 device_printf(dev, "couldn't set up irq\n"); 1305 ether_ifdetach(ifp); 1306 } 1307 1308fail: 1309 1310 if (error) 1311 re_detach(dev); 1312 1313 return (error); 1314} 1315 1316/* 1317 * Shutdown hardware and free up resources. This can be called any 1318 * time after the mutex has been initialized. It is called in both 1319 * the error case in attach and the normal detach case so it needs 1320 * to be careful about only freeing resources that have actually been 1321 * allocated. 1322 */ 1323static int 1324re_detach(dev) 1325 device_t dev; 1326{ 1327 struct rl_softc *sc; 1328 struct ifnet *ifp; 1329 int i; 1330 1331 sc = device_get_softc(dev); 1332 ifp = sc->rl_ifp; 1333 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1334 1335#ifdef DEVICE_POLLING 1336 if (ifp->if_capenable & IFCAP_POLLING) 1337 ether_poll_deregister(ifp); 1338#endif 1339 /* These should only be active if attach succeeded */ 1340 if (device_is_attached(dev)) { 1341 RL_LOCK(sc); 1342#if 0 1343 sc->suspended = 1; 1344#endif 1345 re_stop(sc); 1346 RL_UNLOCK(sc); 1347 callout_drain(&sc->rl_stat_callout); 1348 /* 1349 * Force off the IFF_UP flag here, in case someone 1350 * still had a BPF descriptor attached to this 1351 * interface. If they do, ether_ifdetach() will cause 1352 * the BPF code to try and clear the promisc mode 1353 * flag, which will bubble down to re_ioctl(), 1354 * which will try to call re_init() again. This will 1355 * turn the NIC back on and restart the MII ticker, 1356 * which will panic the system when the kernel tries 1357 * to invoke the re_tick() function that isn't there 1358 * anymore. 1359 */ 1360 ifp->if_flags &= ~IFF_UP; 1361 ether_ifdetach(ifp); 1362 } 1363 if (sc->rl_miibus) 1364 device_delete_child(dev, sc->rl_miibus); 1365 bus_generic_detach(dev); 1366 1367 /* 1368 * The rest is resource deallocation, so we should already be 1369 * stopped here. 1370 */ 1371 1372 if (sc->rl_intrhand) 1373 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1374 if (ifp != NULL) 1375 if_free(ifp); 1376 if (sc->rl_irq) 1377 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1378 if (sc->rl_res) 1379 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1380 1381 /* Yield the CPU long enough for any tasks to drain */ 1382 1383 tsleep(sc, PPAUSE, "rewait", hz); 1384 1385 /* Unload and free the RX DMA ring memory and map */ 1386 1387 if (sc->rl_ldata.rl_rx_list_tag) { 1388 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1389 sc->rl_ldata.rl_rx_list_map); 1390 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1391 sc->rl_ldata.rl_rx_list, 1392 sc->rl_ldata.rl_rx_list_map); 1393 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1394 } 1395 1396 /* Unload and free the TX DMA ring memory and map */ 1397 1398 if (sc->rl_ldata.rl_tx_list_tag) { 1399 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1400 sc->rl_ldata.rl_tx_list_map); 1401 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1402 sc->rl_ldata.rl_tx_list, 1403 sc->rl_ldata.rl_tx_list_map); 1404 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1405 } 1406 1407 /* Destroy all the RX and TX buffer maps */ 1408 1409 if (sc->rl_ldata.rl_mtag) { 1410 for (i = 0; i < RL_TX_DESC_CNT; i++) 1411 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1412 sc->rl_ldata.rl_tx_dmamap[i]); 1413 for (i = 0; i < RL_RX_DESC_CNT; i++) 1414 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1415 sc->rl_ldata.rl_rx_dmamap[i]); 1416 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1417 } 1418 1419 /* Unload and free the stats buffer and map */ 1420 1421 if (sc->rl_ldata.rl_stag) { 1422 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1423 sc->rl_ldata.rl_rx_list_map); 1424 bus_dmamem_free(sc->rl_ldata.rl_stag, 1425 sc->rl_ldata.rl_stats, 1426 sc->rl_ldata.rl_smap); 1427 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1428 } 1429 1430 if (sc->rl_parent_tag) 1431 bus_dma_tag_destroy(sc->rl_parent_tag); 1432 1433 mtx_destroy(&sc->rl_mtx); 1434 1435 return (0); 1436} 1437 1438static int 1439re_newbuf(sc, idx, m) 1440 struct rl_softc *sc; 1441 int idx; 1442 struct mbuf *m; 1443{ 1444 struct rl_dmaload_arg arg; 1445 struct mbuf *n = NULL; 1446 int error; 1447 1448 if (m == NULL) { 1449 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1450 if (n == NULL) 1451 return (ENOBUFS); 1452 m = n; 1453 } else 1454 m->m_data = m->m_ext.ext_buf; 1455 1456 m->m_len = m->m_pkthdr.len = MCLBYTES; 1457#ifdef RE_FIXUP_RX 1458 /* 1459 * This is part of an evil trick to deal with non-x86 platforms. 1460 * The RealTek chip requires RX buffers to be aligned on 64-bit 1461 * boundaries, but that will hose non-x86 machines. To get around 1462 * this, we leave some empty space at the start of each buffer 1463 * and for non-x86 hosts, we copy the buffer back six bytes 1464 * to achieve word alignment. This is slightly more efficient 1465 * than allocating a new buffer, copying the contents, and 1466 * discarding the old buffer. 1467 */ 1468 m_adj(m, RE_ETHER_ALIGN); 1469#endif 1470 arg.sc = sc; 1471 arg.rl_idx = idx; 1472 arg.rl_maxsegs = 1; 1473 arg.rl_flags = 0; 1474 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1475 1476 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1477 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1478 &arg, BUS_DMA_NOWAIT); 1479 if (error || arg.rl_maxsegs != 1) { 1480 if (n != NULL) 1481 m_freem(n); 1482 return (ENOMEM); 1483 } 1484 1485 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1486 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1487 1488 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1489 sc->rl_ldata.rl_rx_dmamap[idx], 1490 BUS_DMASYNC_PREREAD); 1491 1492 return (0); 1493} 1494 1495#ifdef RE_FIXUP_RX 1496static __inline void 1497re_fixup_rx(m) 1498 struct mbuf *m; 1499{ 1500 int i; 1501 uint16_t *src, *dst; 1502 1503 src = mtod(m, uint16_t *); 1504 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1505 1506 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1507 *dst++ = *src++; 1508 1509 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1510 1511 return; 1512} 1513#endif 1514 1515static int 1516re_tx_list_init(sc) 1517 struct rl_softc *sc; 1518{ 1519 1520 RL_LOCK_ASSERT(sc); 1521 1522 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1523 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1524 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1525 1526 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1527 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1528 sc->rl_ldata.rl_tx_prodidx = 0; 1529 sc->rl_ldata.rl_tx_considx = 0; 1530 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1531 1532 return (0); 1533} 1534 1535static int 1536re_rx_list_init(sc) 1537 struct rl_softc *sc; 1538{ 1539 int i; 1540 1541 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1542 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1543 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1544 1545 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1546 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1547 return (ENOBUFS); 1548 } 1549 1550 /* Flush the RX descriptors */ 1551 1552 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1553 sc->rl_ldata.rl_rx_list_map, 1554 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1555 1556 sc->rl_ldata.rl_rx_prodidx = 0; 1557 sc->rl_head = sc->rl_tail = NULL; 1558 1559 return (0); 1560} 1561 1562/* 1563 * RX handler for C+ and 8169. For the gigE chips, we support 1564 * the reception of jumbo frames that have been fragmented 1565 * across multiple 2K mbuf cluster buffers. 1566 */ 1567static int 1568re_rxeof(sc) 1569 struct rl_softc *sc; 1570{ 1571 struct mbuf *m; 1572 struct ifnet *ifp; 1573 int i, total_len; 1574 struct rl_desc *cur_rx; 1575 u_int32_t rxstat, rxvlan; 1576 int maxpkt = 16; 1577 1578 RL_LOCK_ASSERT(sc); 1579 1580 ifp = sc->rl_ifp; 1581 i = sc->rl_ldata.rl_rx_prodidx; 1582 1583 /* Invalidate the descriptor memory */ 1584 1585 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1586 sc->rl_ldata.rl_rx_list_map, 1587 BUS_DMASYNC_POSTREAD); 1588 1589 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) { 1590 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1591 m = sc->rl_ldata.rl_rx_mbuf[i]; 1592 total_len = RL_RXBYTES(cur_rx); 1593 rxstat = le32toh(cur_rx->rl_cmdstat); 1594 rxvlan = le32toh(cur_rx->rl_vlanctl); 1595 1596 /* Invalidate the RX mbuf and unload its map */ 1597 1598 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1599 sc->rl_ldata.rl_rx_dmamap[i], 1600 BUS_DMASYNC_POSTWRITE); 1601 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1602 sc->rl_ldata.rl_rx_dmamap[i]); 1603 1604 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1605 m->m_len = RE_RX_DESC_BUFLEN; 1606 if (sc->rl_head == NULL) 1607 sc->rl_head = sc->rl_tail = m; 1608 else { 1609 m->m_flags &= ~M_PKTHDR; 1610 sc->rl_tail->m_next = m; 1611 sc->rl_tail = m; 1612 } 1613 re_newbuf(sc, i, NULL); 1614 RL_DESC_INC(i); 1615 continue; 1616 } 1617 1618 /* 1619 * NOTE: for the 8139C+, the frame length field 1620 * is always 12 bits in size, but for the gigE chips, 1621 * it is 13 bits (since the max RX frame length is 16K). 1622 * Unfortunately, all 32 bits in the status word 1623 * were already used, so to make room for the extra 1624 * length bit, RealTek took out the 'frame alignment 1625 * error' bit and shifted the other status bits 1626 * over one slot. The OWN, EOR, FS and LS bits are 1627 * still in the same places. We have already extracted 1628 * the frame length and checked the OWN bit, so rather 1629 * than using an alternate bit mapping, we shift the 1630 * status bits one space to the right so we can evaluate 1631 * them using the 8169 status as though it was in the 1632 * same format as that of the 8139C+. 1633 */ 1634 if (sc->rl_type == RL_8169) 1635 rxstat >>= 1; 1636 1637 /* 1638 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1639 * set, but if CRC is clear, it will still be a valid frame. 1640 */ 1641 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1642 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1643 ifp->if_ierrors++; 1644 /* 1645 * If this is part of a multi-fragment packet, 1646 * discard all the pieces. 1647 */ 1648 if (sc->rl_head != NULL) { 1649 m_freem(sc->rl_head); 1650 sc->rl_head = sc->rl_tail = NULL; 1651 } 1652 re_newbuf(sc, i, m); 1653 RL_DESC_INC(i); 1654 continue; 1655 } 1656 1657 /* 1658 * If allocating a replacement mbuf fails, 1659 * reload the current one. 1660 */ 1661 1662 if (re_newbuf(sc, i, NULL)) { 1663 ifp->if_ierrors++; 1664 if (sc->rl_head != NULL) { 1665 m_freem(sc->rl_head); 1666 sc->rl_head = sc->rl_tail = NULL; 1667 } 1668 re_newbuf(sc, i, m); 1669 RL_DESC_INC(i); 1670 continue; 1671 } 1672 1673 RL_DESC_INC(i); 1674 1675 if (sc->rl_head != NULL) { 1676 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1677 if (m->m_len == 0) 1678 m->m_len = RE_RX_DESC_BUFLEN; 1679 /* 1680 * Special case: if there's 4 bytes or less 1681 * in this buffer, the mbuf can be discarded: 1682 * the last 4 bytes is the CRC, which we don't 1683 * care about anyway. 1684 */ 1685 if (m->m_len <= ETHER_CRC_LEN) { 1686 sc->rl_tail->m_len -= 1687 (ETHER_CRC_LEN - m->m_len); 1688 m_freem(m); 1689 } else { 1690 m->m_len -= ETHER_CRC_LEN; 1691 m->m_flags &= ~M_PKTHDR; 1692 sc->rl_tail->m_next = m; 1693 } 1694 m = sc->rl_head; 1695 sc->rl_head = sc->rl_tail = NULL; 1696 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1697 } else 1698 m->m_pkthdr.len = m->m_len = 1699 (total_len - ETHER_CRC_LEN); 1700 1701#ifdef RE_FIXUP_RX 1702 re_fixup_rx(m); 1703#endif 1704 ifp->if_ipackets++; 1705 m->m_pkthdr.rcvif = ifp; 1706 1707 /* Do RX checksumming if enabled */ 1708 1709 if (ifp->if_capenable & IFCAP_RXCSUM) { 1710 1711 /* Check IP header checksum */ 1712 if (rxstat & RL_RDESC_STAT_PROTOID) 1713 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1714 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1715 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1716 1717 /* Check TCP/UDP checksum */ 1718 if ((RL_TCPPKT(rxstat) && 1719 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1720 (RL_UDPPKT(rxstat) && 1721 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1722 m->m_pkthdr.csum_flags |= 1723 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1724 m->m_pkthdr.csum_data = 0xffff; 1725 } 1726 } 1727 maxpkt--; 1728 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1729 VLAN_INPUT_TAG(ifp, m, 1730 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA))); 1731 if (m == NULL) 1732 continue; 1733 } 1734 RL_UNLOCK(sc); 1735 (*ifp->if_input)(ifp, m); 1736 RL_LOCK(sc); 1737 } 1738 1739 /* Flush the RX DMA ring */ 1740 1741 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1742 sc->rl_ldata.rl_rx_list_map, 1743 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1744 1745 sc->rl_ldata.rl_rx_prodidx = i; 1746 1747 if (maxpkt) 1748 return(EAGAIN); 1749 1750 return(0); 1751} 1752 1753static void 1754re_txeof(sc) 1755 struct rl_softc *sc; 1756{ 1757 struct ifnet *ifp; 1758 u_int32_t txstat; 1759 int idx; 1760 1761 ifp = sc->rl_ifp; 1762 idx = sc->rl_ldata.rl_tx_considx; 1763 1764 /* Invalidate the TX descriptor list */ 1765 1766 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1767 sc->rl_ldata.rl_tx_list_map, 1768 BUS_DMASYNC_POSTREAD); 1769 1770 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1771 1772 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1773 if (txstat & RL_TDESC_CMD_OWN) 1774 break; 1775 1776 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0; 1777 1778 /* 1779 * We only stash mbufs in the last descriptor 1780 * in a fragment chain, which also happens to 1781 * be the only place where the TX status bits 1782 * are valid. 1783 */ 1784 1785 if (txstat & RL_TDESC_CMD_EOF) { 1786 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1787 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1788 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1789 sc->rl_ldata.rl_tx_dmamap[idx]); 1790 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1791 RL_TDESC_STAT_COLCNT)) 1792 ifp->if_collisions++; 1793 if (txstat & RL_TDESC_STAT_TXERRSUM) 1794 ifp->if_oerrors++; 1795 else 1796 ifp->if_opackets++; 1797 } 1798 sc->rl_ldata.rl_tx_free++; 1799 RL_DESC_INC(idx); 1800 } 1801 1802 /* No changes made to the TX ring, so no flush needed */ 1803 1804 if (sc->rl_ldata.rl_tx_free) { 1805 sc->rl_ldata.rl_tx_considx = idx; 1806 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1807 ifp->if_timer = 0; 1808 } 1809 1810 /* 1811 * Some chips will ignore a second TX request issued while an 1812 * existing transmission is in progress. If the transmitter goes 1813 * idle but there are still packets waiting to be sent, we need 1814 * to restart the channel here to flush them out. This only seems 1815 * to be required with the PCIe devices. 1816 */ 1817 1818 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) 1819 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1820 1821#ifdef RE_TX_MODERATION 1822 /* 1823 * If not all descriptors have been released reaped yet, 1824 * reload the timer so that we will eventually get another 1825 * interrupt that will cause us to re-enter this routine. 1826 * This is done in case the transmitter has gone idle. 1827 */ 1828 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1829 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1830#endif 1831 1832} 1833 1834static void 1835re_tick(xsc) 1836 void *xsc; 1837{ 1838 struct rl_softc *sc; 1839 struct mii_data *mii; 1840 struct ifnet *ifp; 1841 1842 sc = xsc; 1843 ifp = sc->rl_ifp; 1844 1845 RL_LOCK_ASSERT(sc); 1846 1847 mii = device_get_softc(sc->rl_miibus); 1848 1849 mii_tick(mii); 1850 if (sc->rl_link) { 1851 if (!(mii->mii_media_status & IFM_ACTIVE)) 1852 sc->rl_link = 0; 1853 } else { 1854 if (mii->mii_media_status & IFM_ACTIVE && 1855 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1856 sc->rl_link = 1; 1857 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1858 taskqueue_enqueue_fast(taskqueue_fast, 1859 &sc->rl_txtask); 1860 } 1861 } 1862 1863 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1864} 1865 1866#ifdef DEVICE_POLLING 1867static void 1868re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1869{ 1870 struct rl_softc *sc = ifp->if_softc; 1871 1872 RL_LOCK(sc); 1873 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1874 re_poll_locked(ifp, cmd, count); 1875 RL_UNLOCK(sc); 1876} 1877 1878static void 1879re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1880{ 1881 struct rl_softc *sc = ifp->if_softc; 1882 1883 RL_LOCK_ASSERT(sc); 1884 1885 sc->rxcycles = count; 1886 re_rxeof(sc); 1887 re_txeof(sc); 1888 1889 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1890 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 1891 1892 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1893 u_int16_t status; 1894 1895 status = CSR_READ_2(sc, RL_ISR); 1896 if (status == 0xffff) 1897 return; 1898 if (status) 1899 CSR_WRITE_2(sc, RL_ISR, status); 1900 1901 /* 1902 * XXX check behaviour on receiver stalls. 1903 */ 1904 1905 if (status & RL_ISR_SYSTEM_ERR) { 1906 re_reset(sc); 1907 re_init_locked(sc); 1908 } 1909 } 1910} 1911#endif /* DEVICE_POLLING */ 1912 1913static void 1914re_intr(arg) 1915 void *arg; 1916{ 1917 struct rl_softc *sc; 1918 struct ifnet *ifp; 1919 uint16_t status; 1920 1921 sc = arg; 1922 ifp = sc->rl_ifp; 1923 1924 status = CSR_READ_2(sc, RL_ISR); 1925 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 1926 return; 1927 CSR_WRITE_2(sc, RL_IMR, 0); 1928 1929 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 1930 1931 return; 1932} 1933 1934static void 1935re_int_task(arg, npending) 1936 void *arg; 1937 int npending; 1938{ 1939 struct rl_softc *sc; 1940 struct ifnet *ifp; 1941 u_int16_t status; 1942 int rval = 0; 1943 1944 sc = arg; 1945 ifp = sc->rl_ifp; 1946 1947 RL_LOCK(sc); 1948 1949 status = CSR_READ_2(sc, RL_ISR); 1950 CSR_WRITE_2(sc, RL_ISR, status); 1951 1952 if (sc->suspended || !(ifp->if_flags & IFF_UP)) { 1953 RL_UNLOCK(sc); 1954 return; 1955 } 1956 1957#ifdef DEVICE_POLLING 1958 if (ifp->if_capenable & IFCAP_POLLING) { 1959 RL_UNLOCK(sc); 1960 return; 1961 } 1962#endif 1963 1964 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 1965 rval = re_rxeof(sc); 1966 1967#ifdef RE_TX_MODERATION 1968 if (status & (RL_ISR_TIMEOUT_EXPIRED| 1969#else 1970 if (status & (RL_ISR_TX_OK| 1971#endif 1972 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 1973 re_txeof(sc); 1974 1975 if (status & RL_ISR_SYSTEM_ERR) { 1976 re_reset(sc); 1977 re_init_locked(sc); 1978 } 1979 1980 if (status & RL_ISR_LINKCHG) { 1981 callout_stop(&sc->rl_stat_callout); 1982 re_tick(sc); 1983 } 1984 1985 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1986 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 1987 1988 RL_UNLOCK(sc); 1989 1990 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 1991 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 1992 return; 1993 } 1994 1995 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1996 1997 return; 1998} 1999 2000static int 2001re_encap(sc, m_head, idx) 2002 struct rl_softc *sc; 2003 struct mbuf **m_head; 2004 int *idx; 2005{ 2006 struct mbuf *m_new = NULL; 2007 struct rl_dmaload_arg arg; 2008 bus_dmamap_t map; 2009 int error; 2010 struct m_tag *mtag; 2011 2012 RL_LOCK_ASSERT(sc); 2013 2014 if (sc->rl_ldata.rl_tx_free <= 4) 2015 return (EFBIG); 2016 2017 /* 2018 * Set up checksum offload. Note: checksum offload bits must 2019 * appear in all descriptors of a multi-descriptor transmit 2020 * attempt. This is according to testing done with an 8169 2021 * chip. This is a requirement. 2022 */ 2023 2024 arg.rl_flags = 0; 2025 2026 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2027 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 2028 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2029 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 2030 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2031 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 2032 2033 arg.sc = sc; 2034 arg.rl_idx = *idx; 2035 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2036 if (arg.rl_maxsegs > 4) 2037 arg.rl_maxsegs -= 4; 2038 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2039 2040 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 2041 2042 /* 2043 * With some of the RealTek chips, using the checksum offload 2044 * support in conjunction with the autopadding feature results 2045 * in the transmission of corrupt frames. For example, if we 2046 * need to send a really small IP fragment that's less than 60 2047 * bytes in size, and IP header checksumming is enabled, the 2048 * resulting ethernet frame that appears on the wire will 2049 * have garbled payload. To work around this, if TX checksum 2050 * offload is enabled, we always manually pad short frames out 2051 * to the minimum ethernet frame size. We do this by pretending 2052 * the mbuf chain has too many fragments so the coalescing code 2053 * below can assemble the packet into a single buffer that's 2054 * padded out to the mininum frame size. 2055 */ 2056 2057 if (arg.rl_flags && (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) 2058 error = EFBIG; 2059 else 2060 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2061 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2062 2063 if (error && error != EFBIG) { 2064 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", error); 2065 return (ENOBUFS); 2066 } 2067 2068 /* Too many segments to map, coalesce into a single mbuf */ 2069 2070 if (error || arg.rl_maxsegs == 0) { 2071 m_new = m_defrag(*m_head, M_DONTWAIT); 2072 if (m_new == NULL) 2073 return (ENOBUFS); 2074 else 2075 *m_head = m_new; 2076 2077 /* 2078 * Manually pad short frames, and zero the pad space 2079 * to avoid leaking data. 2080 */ 2081 2082 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) { 2083 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 2084 RL_MIN_FRAMELEN - m_new->m_pkthdr.len); 2085 m_new->m_pkthdr.len += RL_MIN_FRAMELEN - 2086 m_new->m_pkthdr.len; 2087 m_new->m_len = m_new->m_pkthdr.len; 2088 } 2089 2090 arg.sc = sc; 2091 arg.rl_idx = *idx; 2092 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2093 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2094 2095 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2096 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2097 if (error) { 2098 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", 2099 error); 2100 return (EFBIG); 2101 } 2102 } 2103 2104 /* 2105 * Insure that the map for this transmission 2106 * is placed at the array index of the last descriptor 2107 * in this chain. (Swap last and first dmamaps.) 2108 */ 2109 sc->rl_ldata.rl_tx_dmamap[*idx] = 2110 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 2111 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 2112 2113 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 2114 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 2115 2116 /* 2117 * Set up hardware VLAN tagging. Note: vlan tag info must 2118 * appear in the first descriptor of a multi-descriptor 2119 * transmission attempt. 2120 */ 2121 2122 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head); 2123 if (mtag != NULL) 2124 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 2125 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 2126 2127 /* Transfer ownership of packet to the chip. */ 2128 2129 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 2130 htole32(RL_TDESC_CMD_OWN); 2131 if (*idx != arg.rl_idx) 2132 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 2133 htole32(RL_TDESC_CMD_OWN); 2134 2135 RL_DESC_INC(arg.rl_idx); 2136 *idx = arg.rl_idx; 2137 2138 return (0); 2139} 2140 2141static void 2142re_tx_task(arg, npending) 2143 void *arg; 2144 int npending; 2145{ 2146 struct ifnet *ifp; 2147 2148 ifp = arg; 2149 re_start(ifp); 2150 2151 return; 2152} 2153 2154/* 2155 * Main transmit routine for C+ and gigE NICs. 2156 */ 2157static void 2158re_start(ifp) 2159 struct ifnet *ifp; 2160{ 2161 struct rl_softc *sc; 2162 struct mbuf *m_head = NULL; 2163 int idx, queued = 0; 2164 2165 sc = ifp->if_softc; 2166 2167 RL_LOCK(sc); 2168 2169 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 2170 RL_UNLOCK(sc); 2171 return; 2172 } 2173 2174 idx = sc->rl_ldata.rl_tx_prodidx; 2175 2176 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2177 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2178 if (m_head == NULL) 2179 break; 2180 2181 if (re_encap(sc, &m_head, &idx)) { 2182 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2183 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2184 break; 2185 } 2186 2187 /* 2188 * If there's a BPF listener, bounce a copy of this frame 2189 * to him. 2190 */ 2191 BPF_MTAP(ifp, m_head); 2192 2193 queued++; 2194 } 2195 2196 if (queued == 0) { 2197#ifdef RE_TX_MODERATION 2198 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 2199 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2200#endif 2201 RL_UNLOCK(sc); 2202 return; 2203 } 2204 2205 /* Flush the TX descriptors */ 2206 2207 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2208 sc->rl_ldata.rl_tx_list_map, 2209 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2210 2211 sc->rl_ldata.rl_tx_prodidx = idx; 2212 2213 /* 2214 * RealTek put the TX poll request register in a different 2215 * location on the 8169 gigE chip. I don't know why. 2216 */ 2217 2218 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2219 2220#ifdef RE_TX_MODERATION 2221 /* 2222 * Use the countdown timer for interrupt moderation. 2223 * 'TX done' interrupts are disabled. Instead, we reset the 2224 * countdown timer, which will begin counting until it hits 2225 * the value in the TIMERINT register, and then trigger an 2226 * interrupt. Each time we write to the TIMERCNT register, 2227 * the timer count is reset to 0. 2228 */ 2229 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2230#endif 2231 2232 /* 2233 * Set a timeout in case the chip goes out to lunch. 2234 */ 2235 2236 ifp->if_timer = 5; 2237 2238 RL_UNLOCK(sc); 2239 2240 return; 2241} 2242 2243static void 2244re_init(xsc) 2245 void *xsc; 2246{ 2247 struct rl_softc *sc = xsc; 2248 2249 RL_LOCK(sc); 2250 re_init_locked(sc); 2251 RL_UNLOCK(sc); 2252} 2253 2254static void 2255re_init_locked(sc) 2256 struct rl_softc *sc; 2257{ 2258 struct ifnet *ifp = sc->rl_ifp; 2259 struct mii_data *mii; 2260 u_int32_t rxcfg = 0; 2261 union { 2262 uint32_t align_dummy; 2263 u_char eaddr[ETHER_ADDR_LEN]; 2264 } eaddr; 2265 2266 RL_LOCK_ASSERT(sc); 2267 2268 mii = device_get_softc(sc->rl_miibus); 2269 2270 /* 2271 * Cancel pending I/O and free all RX/TX buffers. 2272 */ 2273 re_stop(sc); 2274 2275 /* 2276 * Enable C+ RX and TX mode, as well as VLAN stripping and 2277 * RX checksum offload. We must configure the C+ register 2278 * before all others. 2279 */ 2280 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2281 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2282 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB); 2283 2284 /* 2285 * Init our MAC address. Even though the chipset 2286 * documentation doesn't mention it, we need to enter "Config 2287 * register write enable" mode to modify the ID registers. 2288 */ 2289 /* Copy MAC address on stack to align. */ 2290 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2291 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2292 CSR_WRITE_4(sc, RL_IDR0, 2293 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2294 CSR_WRITE_4(sc, RL_IDR4, 2295 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2296 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2297 2298 /* 2299 * For C+ mode, initialize the RX descriptors and mbufs. 2300 */ 2301 re_rx_list_init(sc); 2302 re_tx_list_init(sc); 2303 2304 /* 2305 * Enable transmit and receive. 2306 */ 2307 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2308 2309 /* 2310 * Set the initial TX and RX configuration. 2311 */ 2312 if (sc->rl_testmode) { 2313 if (sc->rl_type == RL_8169) 2314 CSR_WRITE_4(sc, RL_TXCFG, 2315 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2316 else 2317 CSR_WRITE_4(sc, RL_TXCFG, 2318 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2319 } else 2320 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2321 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2322 2323 /* Set the individual bit to receive frames for this host only. */ 2324 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2325 rxcfg |= RL_RXCFG_RX_INDIV; 2326 2327 /* If we want promiscuous mode, set the allframes bit. */ 2328 if (ifp->if_flags & IFF_PROMISC) 2329 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2330 else 2331 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2332 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2333 2334 /* 2335 * Set capture broadcast bit to capture broadcast frames. 2336 */ 2337 if (ifp->if_flags & IFF_BROADCAST) 2338 rxcfg |= RL_RXCFG_RX_BROAD; 2339 else 2340 rxcfg &= ~RL_RXCFG_RX_BROAD; 2341 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2342 2343 /* 2344 * Program the multicast filter, if necessary. 2345 */ 2346 re_setmulti(sc); 2347 2348#ifdef DEVICE_POLLING 2349 /* 2350 * Disable interrupts if we are polling. 2351 */ 2352 if (ifp->if_capenable & IFCAP_POLLING) 2353 CSR_WRITE_2(sc, RL_IMR, 0); 2354 else /* otherwise ... */ 2355#endif 2356 2357 /* 2358 * Enable interrupts. 2359 */ 2360 if (sc->rl_testmode) 2361 CSR_WRITE_2(sc, RL_IMR, 0); 2362 else 2363 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2364 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2365 2366 /* Set initial TX threshold */ 2367 sc->rl_txthresh = RL_TX_THRESH_INIT; 2368 2369 /* Start RX/TX process. */ 2370 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2371#ifdef notdef 2372 /* Enable receiver and transmitter. */ 2373 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2374#endif 2375 /* 2376 * Load the addresses of the RX and TX lists into the chip. 2377 */ 2378 2379 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2380 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2381 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2382 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2383 2384 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2385 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2386 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2387 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2388 2389 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2390 2391#ifdef RE_TX_MODERATION 2392 /* 2393 * Initialize the timer interrupt register so that 2394 * a timer interrupt will be generated once the timer 2395 * reaches a certain number of ticks. The timer is 2396 * reloaded on each transmit. This gives us TX interrupt 2397 * moderation, which dramatically improves TX frame rate. 2398 */ 2399 if (sc->rl_type == RL_8169) 2400 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2401 else 2402 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2403#endif 2404 2405 /* 2406 * For 8169 gigE NICs, set the max allowed RX packet 2407 * size so we can receive jumbo frames. 2408 */ 2409 if (sc->rl_type == RL_8169) 2410 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2411 2412 if (sc->rl_testmode) 2413 return; 2414 2415 mii_mediachg(mii); 2416 2417 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2418 2419 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2420 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2421 2422 2423 sc->rl_link = 0; 2424 2425 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2426} 2427 2428/* 2429 * Set media options. 2430 */ 2431static int 2432re_ifmedia_upd(ifp) 2433 struct ifnet *ifp; 2434{ 2435 struct rl_softc *sc; 2436 struct mii_data *mii; 2437 2438 sc = ifp->if_softc; 2439 mii = device_get_softc(sc->rl_miibus); 2440 RL_LOCK(sc); 2441 mii_mediachg(mii); 2442 RL_UNLOCK(sc); 2443 2444 return (0); 2445} 2446 2447/* 2448 * Report current media status. 2449 */ 2450static void 2451re_ifmedia_sts(ifp, ifmr) 2452 struct ifnet *ifp; 2453 struct ifmediareq *ifmr; 2454{ 2455 struct rl_softc *sc; 2456 struct mii_data *mii; 2457 2458 sc = ifp->if_softc; 2459 mii = device_get_softc(sc->rl_miibus); 2460 2461 RL_LOCK(sc); 2462 mii_pollstat(mii); 2463 RL_UNLOCK(sc); 2464 ifmr->ifm_active = mii->mii_media_active; 2465 ifmr->ifm_status = mii->mii_media_status; 2466} 2467 2468static int 2469re_ioctl(ifp, command, data) 2470 struct ifnet *ifp; 2471 u_long command; 2472 caddr_t data; 2473{ 2474 struct rl_softc *sc = ifp->if_softc; 2475 struct ifreq *ifr = (struct ifreq *) data; 2476 struct mii_data *mii; 2477 int error = 0; 2478 2479 switch (command) { 2480 case SIOCSIFMTU: 2481 RL_LOCK(sc); 2482 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2483 error = EINVAL; 2484 ifp->if_mtu = ifr->ifr_mtu; 2485 RL_UNLOCK(sc); 2486 break; 2487 case SIOCSIFFLAGS: 2488 RL_LOCK(sc); 2489 if (ifp->if_flags & IFF_UP) 2490 re_init_locked(sc); 2491 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2492 re_stop(sc); 2493 RL_UNLOCK(sc); 2494 break; 2495 case SIOCADDMULTI: 2496 case SIOCDELMULTI: 2497 RL_LOCK(sc); 2498 re_setmulti(sc); 2499 RL_UNLOCK(sc); 2500 break; 2501 case SIOCGIFMEDIA: 2502 case SIOCSIFMEDIA: 2503 mii = device_get_softc(sc->rl_miibus); 2504 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2505 break; 2506 case SIOCSIFCAP: 2507 { 2508 int mask, reinit; 2509 2510 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2511 reinit = 0; 2512#ifdef DEVICE_POLLING 2513 if (mask & IFCAP_POLLING) { 2514 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2515 error = ether_poll_register(re_poll, ifp); 2516 if (error) 2517 return(error); 2518 RL_LOCK(sc); 2519 /* Disable interrupts */ 2520 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2521 ifp->if_capenable |= IFCAP_POLLING; 2522 RL_UNLOCK(sc); 2523 2524 } else { 2525 error = ether_poll_deregister(ifp); 2526 /* Enable interrupts. */ 2527 RL_LOCK(sc); 2528 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2529 ifp->if_capenable &= ~IFCAP_POLLING; 2530 RL_UNLOCK(sc); 2531 } 2532 } 2533#endif /* DEVICE_POLLING */ 2534 if (mask & IFCAP_HWCSUM) { 2535 ifp->if_capenable ^= IFCAP_HWCSUM; 2536 if (ifp->if_capenable & IFCAP_TXCSUM) 2537 ifp->if_hwassist = RE_CSUM_FEATURES; 2538 else 2539 ifp->if_hwassist = 0; 2540 reinit = 1; 2541 } 2542 if (mask & IFCAP_VLAN_HWTAGGING) { 2543 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2544 reinit = 1; 2545 } 2546 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2547 re_init(sc); 2548 } 2549 break; 2550 default: 2551 error = ether_ioctl(ifp, command, data); 2552 break; 2553 } 2554 2555 return (error); 2556} 2557 2558static void 2559re_watchdog(ifp) 2560 struct ifnet *ifp; 2561{ 2562 struct rl_softc *sc; 2563 2564 sc = ifp->if_softc; 2565 RL_LOCK(sc); 2566 if_printf(ifp, "watchdog timeout\n"); 2567 ifp->if_oerrors++; 2568 2569 re_txeof(sc); 2570 re_rxeof(sc); 2571 re_init_locked(sc); 2572 2573 RL_UNLOCK(sc); 2574} 2575 2576/* 2577 * Stop the adapter and free any mbufs allocated to the 2578 * RX and TX lists. 2579 */ 2580static void 2581re_stop(sc) 2582 struct rl_softc *sc; 2583{ 2584 register int i; 2585 struct ifnet *ifp; 2586 2587 RL_LOCK_ASSERT(sc); 2588 2589 ifp = sc->rl_ifp; 2590 ifp->if_timer = 0; 2591 2592 callout_stop(&sc->rl_stat_callout); 2593 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2594 2595 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2596 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2597 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2598 2599 if (sc->rl_head != NULL) { 2600 m_freem(sc->rl_head); 2601 sc->rl_head = sc->rl_tail = NULL; 2602 } 2603 2604 /* Free the TX list buffers. */ 2605 2606 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2607 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2608 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2609 sc->rl_ldata.rl_tx_dmamap[i]); 2610 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2611 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2612 } 2613 } 2614 2615 /* Free the RX list buffers. */ 2616 2617 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2618 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2619 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2620 sc->rl_ldata.rl_rx_dmamap[i]); 2621 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2622 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2623 } 2624 } 2625} 2626 2627/* 2628 * Device suspend routine. Stop the interface and save some PCI 2629 * settings in case the BIOS doesn't restore them properly on 2630 * resume. 2631 */ 2632static int 2633re_suspend(dev) 2634 device_t dev; 2635{ 2636 struct rl_softc *sc; 2637 2638 sc = device_get_softc(dev); 2639 2640 RL_LOCK(sc); 2641 re_stop(sc); 2642 sc->suspended = 1; 2643 RL_UNLOCK(sc); 2644 2645 return (0); 2646} 2647 2648/* 2649 * Device resume routine. Restore some PCI settings in case the BIOS 2650 * doesn't, re-enable busmastering, and restart the interface if 2651 * appropriate. 2652 */ 2653static int 2654re_resume(dev) 2655 device_t dev; 2656{ 2657 struct rl_softc *sc; 2658 struct ifnet *ifp; 2659 2660 sc = device_get_softc(dev); 2661 2662 RL_LOCK(sc); 2663 2664 ifp = sc->rl_ifp; 2665 2666 /* reinitialize interface if necessary */ 2667 if (ifp->if_flags & IFF_UP) 2668 re_init_locked(sc); 2669 2670 sc->suspended = 0; 2671 RL_UNLOCK(sc); 2672 2673 return (0); 2674} 2675 2676/* 2677 * Stop all chip I/O so that the kernel's probe routines don't 2678 * get confused by errant DMAs when rebooting. 2679 */ 2680static void 2681re_shutdown(dev) 2682 device_t dev; 2683{ 2684 struct rl_softc *sc; 2685 2686 sc = device_get_softc(dev); 2687 2688 RL_LOCK(sc); 2689 re_stop(sc); 2690 /* 2691 * Mark interface as down since otherwise we will panic if 2692 * interrupt comes in later on, which can happen in some 2693 * cases. 2694 */ 2695 sc->rl_ifp->if_flags &= ~IFF_UP; 2696 RL_UNLOCK(sc); 2697} 2698