if_re.c revision 160935
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 160935 2006-08-03 00:15:19Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/taskqueue.h> 127 128#include <net/if.h> 129#include <net/if_arp.h> 130#include <net/ethernet.h> 131#include <net/if_dl.h> 132#include <net/if_media.h> 133#include <net/if_types.h> 134#include <net/if_vlan_var.h> 135 136#include <net/bpf.h> 137 138#include <machine/bus.h> 139#include <machine/resource.h> 140#include <sys/bus.h> 141#include <sys/rman.h> 142 143#include <dev/mii/mii.h> 144#include <dev/mii/miivar.h> 145 146#include <dev/pci/pcireg.h> 147#include <dev/pci/pcivar.h> 148 149MODULE_DEPEND(re, pci, 1, 1, 1); 150MODULE_DEPEND(re, ether, 1, 1, 1); 151MODULE_DEPEND(re, miibus, 1, 1, 1); 152 153/* "device miibus" required. See GENERIC if you get errors here. */ 154#include "miibus_if.h" 155 156/* 157 * Default to using PIO access for this driver. 158 */ 159#define RE_USEIOSPACE 160 161#include <pci/if_rlreg.h> 162 163#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 164 165/* 166 * Various supported device vendors/types and their names. 167 */ 168static struct rl_type re_devs[] = { 169 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 171 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 172 "RealTek 8139C+ 10/100BaseTX" }, 173 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 174 "RealTek 8101E PCIe 10/100baseTX" }, 175 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 176 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 178 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 180 "RealTek 8169 Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 182 "RealTek 8169S Single-chip Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 184 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 186 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 188 "RealTek 8110S Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }, 195 { 0, 0, 0, NULL } 196}; 197 198static struct rl_hwrev re_hwrevs[] = { 199 { RL_HWREV_8139, RL_8139, "" }, 200 { RL_HWREV_8139A, RL_8139, "A" }, 201 { RL_HWREV_8139AG, RL_8139, "A-G" }, 202 { RL_HWREV_8139B, RL_8139, "B" }, 203 { RL_HWREV_8130, RL_8139, "8130" }, 204 { RL_HWREV_8139C, RL_8139, "C" }, 205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 207 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 208 { RL_HWREV_8169, RL_8169, "8169"}, 209 { RL_HWREV_8169S, RL_8169, "8169S"}, 210 { RL_HWREV_8110S, RL_8169, "8110S"}, 211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 213 { RL_HWREV_8100, RL_8139, "8100"}, 214 { RL_HWREV_8101, RL_8139, "8101"}, 215 { RL_HWREV_8100E, RL_8169, "8100E"}, 216 { RL_HWREV_8101E, RL_8169, "8101E"}, 217 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 218 { 0, 0, NULL } 219}; 220 221static int re_probe (device_t); 222static int re_attach (device_t); 223static int re_detach (device_t); 224 225static int re_encap (struct rl_softc *, struct mbuf **, int *); 226 227static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 228static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 229 bus_size_t, int); 230static int re_allocmem (device_t, struct rl_softc *); 231static int re_newbuf (struct rl_softc *, int, struct mbuf *); 232static int re_rx_list_init (struct rl_softc *); 233static int re_tx_list_init (struct rl_softc *); 234#ifdef RE_FIXUP_RX 235static __inline void re_fixup_rx 236 (struct mbuf *); 237#endif 238static int re_rxeof (struct rl_softc *); 239static void re_txeof (struct rl_softc *); 240#ifdef DEVICE_POLLING 241static void re_poll (struct ifnet *, enum poll_cmd, int); 242static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 243#endif 244static void re_intr (void *); 245static void re_tick (void *); 246static void re_tx_task (void *, int); 247static void re_int_task (void *, int); 248static void re_start (struct ifnet *); 249static int re_ioctl (struct ifnet *, u_long, caddr_t); 250static void re_init (void *); 251static void re_init_locked (struct rl_softc *); 252static void re_stop (struct rl_softc *); 253static void re_watchdog (struct ifnet *); 254static int re_suspend (device_t); 255static int re_resume (device_t); 256static void re_shutdown (device_t); 257static int re_ifmedia_upd (struct ifnet *); 258static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 259 260static void re_eeprom_putbyte (struct rl_softc *, int); 261static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 262static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 263static int re_gmii_readreg (device_t, int, int); 264static int re_gmii_writereg (device_t, int, int, int); 265 266static int re_miibus_readreg (device_t, int, int); 267static int re_miibus_writereg (device_t, int, int, int); 268static void re_miibus_statchg (device_t); 269 270static void re_setmulti (struct rl_softc *); 271static void re_reset (struct rl_softc *); 272 273#ifdef RE_DIAG 274static int re_diag (struct rl_softc *); 275#endif 276 277#ifdef RE_USEIOSPACE 278#define RL_RES SYS_RES_IOPORT 279#define RL_RID RL_PCI_LOIO 280#else 281#define RL_RES SYS_RES_MEMORY 282#define RL_RID RL_PCI_LOMEM 283#endif 284 285static device_method_t re_methods[] = { 286 /* Device interface */ 287 DEVMETHOD(device_probe, re_probe), 288 DEVMETHOD(device_attach, re_attach), 289 DEVMETHOD(device_detach, re_detach), 290 DEVMETHOD(device_suspend, re_suspend), 291 DEVMETHOD(device_resume, re_resume), 292 DEVMETHOD(device_shutdown, re_shutdown), 293 294 /* bus interface */ 295 DEVMETHOD(bus_print_child, bus_generic_print_child), 296 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 297 298 /* MII interface */ 299 DEVMETHOD(miibus_readreg, re_miibus_readreg), 300 DEVMETHOD(miibus_writereg, re_miibus_writereg), 301 DEVMETHOD(miibus_statchg, re_miibus_statchg), 302 303 { 0, 0 } 304}; 305 306static driver_t re_driver = { 307 "re", 308 re_methods, 309 sizeof(struct rl_softc) 310}; 311 312static devclass_t re_devclass; 313 314DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 315DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 316DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 317 318#define EE_SET(x) \ 319 CSR_WRITE_1(sc, RL_EECMD, \ 320 CSR_READ_1(sc, RL_EECMD) | x) 321 322#define EE_CLR(x) \ 323 CSR_WRITE_1(sc, RL_EECMD, \ 324 CSR_READ_1(sc, RL_EECMD) & ~x) 325 326/* 327 * Send a read command and address to the EEPROM, check for ACK. 328 */ 329static void 330re_eeprom_putbyte(sc, addr) 331 struct rl_softc *sc; 332 int addr; 333{ 334 register int d, i; 335 336 d = addr | (RL_9346_READ << sc->rl_eewidth); 337 338 /* 339 * Feed in each bit and strobe the clock. 340 */ 341 342 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 343 if (d & i) { 344 EE_SET(RL_EE_DATAIN); 345 } else { 346 EE_CLR(RL_EE_DATAIN); 347 } 348 DELAY(100); 349 EE_SET(RL_EE_CLK); 350 DELAY(150); 351 EE_CLR(RL_EE_CLK); 352 DELAY(100); 353 } 354 355 return; 356} 357 358/* 359 * Read a word of data stored in the EEPROM at address 'addr.' 360 */ 361static void 362re_eeprom_getword(sc, addr, dest) 363 struct rl_softc *sc; 364 int addr; 365 u_int16_t *dest; 366{ 367 register int i; 368 u_int16_t word = 0; 369 370 /* 371 * Send address of word we want to read. 372 */ 373 re_eeprom_putbyte(sc, addr); 374 375 /* 376 * Start reading bits from EEPROM. 377 */ 378 for (i = 0x8000; i; i >>= 1) { 379 EE_SET(RL_EE_CLK); 380 DELAY(100); 381 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 382 word |= i; 383 EE_CLR(RL_EE_CLK); 384 DELAY(100); 385 } 386 387 *dest = word; 388 389 return; 390} 391 392/* 393 * Read a sequence of words from the EEPROM. 394 */ 395static void 396re_read_eeprom(sc, dest, off, cnt) 397 struct rl_softc *sc; 398 caddr_t dest; 399 int off; 400 int cnt; 401{ 402 int i; 403 u_int16_t word = 0, *ptr; 404 405 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 406 407 DELAY(100); 408 409 for (i = 0; i < cnt; i++) { 410 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 411 re_eeprom_getword(sc, off + i, &word); 412 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 413 ptr = (u_int16_t *)(dest + (i * 2)); 414 *ptr = word; 415 } 416 417 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 418 419 return; 420} 421 422static int 423re_gmii_readreg(dev, phy, reg) 424 device_t dev; 425 int phy, reg; 426{ 427 struct rl_softc *sc; 428 u_int32_t rval; 429 int i; 430 431 if (phy != 1) 432 return (0); 433 434 sc = device_get_softc(dev); 435 436 /* Let the rgephy driver read the GMEDIASTAT register */ 437 438 if (reg == RL_GMEDIASTAT) { 439 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 440 return (rval); 441 } 442 443 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 444 DELAY(1000); 445 446 for (i = 0; i < RL_TIMEOUT; i++) { 447 rval = CSR_READ_4(sc, RL_PHYAR); 448 if (rval & RL_PHYAR_BUSY) 449 break; 450 DELAY(100); 451 } 452 453 if (i == RL_TIMEOUT) { 454 if_printf(sc->rl_ifp, "PHY read failed\n"); 455 return (0); 456 } 457 458 return (rval & RL_PHYAR_PHYDATA); 459} 460 461static int 462re_gmii_writereg(dev, phy, reg, data) 463 device_t dev; 464 int phy, reg, data; 465{ 466 struct rl_softc *sc; 467 u_int32_t rval; 468 int i; 469 470 sc = device_get_softc(dev); 471 472 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 473 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 474 DELAY(1000); 475 476 for (i = 0; i < RL_TIMEOUT; i++) { 477 rval = CSR_READ_4(sc, RL_PHYAR); 478 if (!(rval & RL_PHYAR_BUSY)) 479 break; 480 DELAY(100); 481 } 482 483 if (i == RL_TIMEOUT) { 484 if_printf(sc->rl_ifp, "PHY write failed\n"); 485 return (0); 486 } 487 488 return (0); 489} 490 491static int 492re_miibus_readreg(dev, phy, reg) 493 device_t dev; 494 int phy, reg; 495{ 496 struct rl_softc *sc; 497 u_int16_t rval = 0; 498 u_int16_t re8139_reg = 0; 499 500 sc = device_get_softc(dev); 501 502 if (sc->rl_type == RL_8169) { 503 rval = re_gmii_readreg(dev, phy, reg); 504 return (rval); 505 } 506 507 /* Pretend the internal PHY is only at address 0 */ 508 if (phy) { 509 return (0); 510 } 511 switch (reg) { 512 case MII_BMCR: 513 re8139_reg = RL_BMCR; 514 break; 515 case MII_BMSR: 516 re8139_reg = RL_BMSR; 517 break; 518 case MII_ANAR: 519 re8139_reg = RL_ANAR; 520 break; 521 case MII_ANER: 522 re8139_reg = RL_ANER; 523 break; 524 case MII_ANLPAR: 525 re8139_reg = RL_LPAR; 526 break; 527 case MII_PHYIDR1: 528 case MII_PHYIDR2: 529 return (0); 530 /* 531 * Allow the rlphy driver to read the media status 532 * register. If we have a link partner which does not 533 * support NWAY, this is the register which will tell 534 * us the results of parallel detection. 535 */ 536 case RL_MEDIASTAT: 537 rval = CSR_READ_1(sc, RL_MEDIASTAT); 538 return (rval); 539 default: 540 if_printf(sc->rl_ifp, "bad phy register\n"); 541 return (0); 542 } 543 rval = CSR_READ_2(sc, re8139_reg); 544 return (rval); 545} 546 547static int 548re_miibus_writereg(dev, phy, reg, data) 549 device_t dev; 550 int phy, reg, data; 551{ 552 struct rl_softc *sc; 553 u_int16_t re8139_reg = 0; 554 int rval = 0; 555 556 sc = device_get_softc(dev); 557 558 if (sc->rl_type == RL_8169) { 559 rval = re_gmii_writereg(dev, phy, reg, data); 560 return (rval); 561 } 562 563 /* Pretend the internal PHY is only at address 0 */ 564 if (phy) 565 return (0); 566 567 switch (reg) { 568 case MII_BMCR: 569 re8139_reg = RL_BMCR; 570 break; 571 case MII_BMSR: 572 re8139_reg = RL_BMSR; 573 break; 574 case MII_ANAR: 575 re8139_reg = RL_ANAR; 576 break; 577 case MII_ANER: 578 re8139_reg = RL_ANER; 579 break; 580 case MII_ANLPAR: 581 re8139_reg = RL_LPAR; 582 break; 583 case MII_PHYIDR1: 584 case MII_PHYIDR2: 585 return (0); 586 break; 587 default: 588 if_printf(sc->rl_ifp, "bad phy register\n"); 589 return (0); 590 } 591 CSR_WRITE_2(sc, re8139_reg, data); 592 return (0); 593} 594 595static void 596re_miibus_statchg(dev) 597 device_t dev; 598{ 599 600} 601 602/* 603 * Program the 64-bit multicast hash filter. 604 */ 605static void 606re_setmulti(sc) 607 struct rl_softc *sc; 608{ 609 struct ifnet *ifp; 610 int h = 0; 611 u_int32_t hashes[2] = { 0, 0 }; 612 struct ifmultiaddr *ifma; 613 u_int32_t rxfilt; 614 int mcnt = 0; 615 616 RL_LOCK_ASSERT(sc); 617 618 ifp = sc->rl_ifp; 619 620 rxfilt = CSR_READ_4(sc, RL_RXCFG); 621 622 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 623 rxfilt |= RL_RXCFG_RX_MULTI; 624 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 625 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 626 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 627 return; 628 } 629 630 /* first, zot all the existing hash bits */ 631 CSR_WRITE_4(sc, RL_MAR0, 0); 632 CSR_WRITE_4(sc, RL_MAR4, 0); 633 634 /* now program new ones */ 635 IF_ADDR_LOCK(ifp); 636 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 637 if (ifma->ifma_addr->sa_family != AF_LINK) 638 continue; 639 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 640 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 641 if (h < 32) 642 hashes[0] |= (1 << h); 643 else 644 hashes[1] |= (1 << (h - 32)); 645 mcnt++; 646 } 647 IF_ADDR_UNLOCK(ifp); 648 649 if (mcnt) 650 rxfilt |= RL_RXCFG_RX_MULTI; 651 else 652 rxfilt &= ~RL_RXCFG_RX_MULTI; 653 654 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 655 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 656 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 657} 658 659static void 660re_reset(sc) 661 struct rl_softc *sc; 662{ 663 register int i; 664 665 RL_LOCK_ASSERT(sc); 666 667 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 668 669 for (i = 0; i < RL_TIMEOUT; i++) { 670 DELAY(10); 671 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 672 break; 673 } 674 if (i == RL_TIMEOUT) 675 if_printf(sc->rl_ifp, "reset never completed!\n"); 676 677 CSR_WRITE_1(sc, 0x82, 1); 678} 679 680#ifdef RE_DIAG 681 682/* 683 * The following routine is designed to test for a defect on some 684 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 685 * lines connected to the bus, however for a 32-bit only card, they 686 * should be pulled high. The result of this defect is that the 687 * NIC will not work right if you plug it into a 64-bit slot: DMA 688 * operations will be done with 64-bit transfers, which will fail 689 * because the 64-bit data lines aren't connected. 690 * 691 * There's no way to work around this (short of talking a soldering 692 * iron to the board), however we can detect it. The method we use 693 * here is to put the NIC into digital loopback mode, set the receiver 694 * to promiscuous mode, and then try to send a frame. We then compare 695 * the frame data we sent to what was received. If the data matches, 696 * then the NIC is working correctly, otherwise we know the user has 697 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 698 * slot. In the latter case, there's no way the NIC can work correctly, 699 * so we print out a message on the console and abort the device attach. 700 */ 701 702static int 703re_diag(sc) 704 struct rl_softc *sc; 705{ 706 struct ifnet *ifp = sc->rl_ifp; 707 struct mbuf *m0; 708 struct ether_header *eh; 709 struct rl_desc *cur_rx; 710 u_int16_t status; 711 u_int32_t rxstat; 712 int total_len, i, error = 0, phyaddr; 713 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 714 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 715 716 /* Allocate a single mbuf */ 717 MGETHDR(m0, M_DONTWAIT, MT_DATA); 718 if (m0 == NULL) 719 return (ENOBUFS); 720 721 RL_LOCK(sc); 722 723 /* 724 * Initialize the NIC in test mode. This sets the chip up 725 * so that it can send and receive frames, but performs the 726 * following special functions: 727 * - Puts receiver in promiscuous mode 728 * - Enables digital loopback mode 729 * - Leaves interrupts turned off 730 */ 731 732 ifp->if_flags |= IFF_PROMISC; 733 sc->rl_testmode = 1; 734 re_reset(sc); 735 re_init_locked(sc); 736 sc->rl_link = 1; 737 if (sc->rl_type == RL_8169) 738 phyaddr = 1; 739 else 740 phyaddr = 0; 741 742 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 743 for (i = 0; i < RL_TIMEOUT; i++) { 744 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 745 if (!(status & BMCR_RESET)) 746 break; 747 } 748 749 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 750 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 751 752 DELAY(100000); 753 754 /* Put some data in the mbuf */ 755 756 eh = mtod(m0, struct ether_header *); 757 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 758 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 759 eh->ether_type = htons(ETHERTYPE_IP); 760 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 761 762 /* 763 * Queue the packet, start transmission. 764 * Note: IF_HANDOFF() ultimately calls re_start() for us. 765 */ 766 767 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 768 RL_UNLOCK(sc); 769 /* XXX: re_diag must not be called when in ALTQ mode */ 770 IF_HANDOFF(&ifp->if_snd, m0, ifp); 771 RL_LOCK(sc); 772 m0 = NULL; 773 774 /* Wait for it to propagate through the chip */ 775 776 DELAY(100000); 777 for (i = 0; i < RL_TIMEOUT; i++) { 778 status = CSR_READ_2(sc, RL_ISR); 779 CSR_WRITE_2(sc, RL_ISR, status); 780 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 781 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 782 break; 783 DELAY(10); 784 } 785 786 if (i == RL_TIMEOUT) { 787 if_printf(ifp, "diagnostic failed, failed to receive packet " 788 "in loopback mode\n"); 789 error = EIO; 790 goto done; 791 } 792 793 /* 794 * The packet should have been dumped into the first 795 * entry in the RX DMA ring. Grab it from there. 796 */ 797 798 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 799 sc->rl_ldata.rl_rx_list_map, 800 BUS_DMASYNC_POSTREAD); 801 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 802 sc->rl_ldata.rl_rx_dmamap[0], 803 BUS_DMASYNC_POSTWRITE); 804 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 805 sc->rl_ldata.rl_rx_dmamap[0]); 806 807 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 808 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 809 eh = mtod(m0, struct ether_header *); 810 811 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 812 total_len = RL_RXBYTES(cur_rx); 813 rxstat = le32toh(cur_rx->rl_cmdstat); 814 815 if (total_len != ETHER_MIN_LEN) { 816 if_printf(ifp, "diagnostic failed, received short packet\n"); 817 error = EIO; 818 goto done; 819 } 820 821 /* Test that the received packet data matches what we sent. */ 822 823 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 824 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 825 ntohs(eh->ether_type) != ETHERTYPE_IP) { 826 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 827 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 828 dst, ":", src, ":", ETHERTYPE_IP); 829 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 830 eh->ether_dhost, ":", eh->ether_shost, ":", 831 ntohs(eh->ether_type)); 832 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 833 "into a 64-bit PCI slot.\n"); 834 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 835 "for proper operation.\n"); 836 if_printf(ifp, "Read the re(4) man page for more details.\n"); 837 error = EIO; 838 } 839 840done: 841 /* Turn interface off, release resources */ 842 843 sc->rl_testmode = 0; 844 sc->rl_link = 0; 845 ifp->if_flags &= ~IFF_PROMISC; 846 re_stop(sc); 847 if (m0 != NULL) 848 m_freem(m0); 849 850 RL_UNLOCK(sc); 851 852 return (error); 853} 854 855#endif 856 857/* 858 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 859 * IDs against our list and return a device name if we find a match. 860 */ 861static int 862re_probe(dev) 863 device_t dev; 864{ 865 struct rl_type *t; 866 struct rl_softc *sc; 867 int rid; 868 u_int32_t hwrev; 869 870 t = re_devs; 871 sc = device_get_softc(dev); 872 873 while (t->rl_name != NULL) { 874 if ((pci_get_vendor(dev) == t->rl_vid) && 875 (pci_get_device(dev) == t->rl_did)) { 876 /* 877 * Only attach to rev. 3 of the Linksys EG1032 adapter. 878 * Rev. 2 i supported by sk(4). 879 */ 880 if ((t->rl_vid == LINKSYS_VENDORID) && 881 (t->rl_did == LINKSYS_DEVICEID_EG1032) && 882 (pci_get_subdevice(dev) != 883 LINKSYS_SUBDEVICE_EG1032_REV3)) { 884 t++; 885 continue; 886 } 887 888 /* 889 * Temporarily map the I/O space 890 * so we can read the chip ID register. 891 */ 892 rid = RL_RID; 893 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 894 RF_ACTIVE); 895 if (sc->rl_res == NULL) { 896 device_printf(dev, 897 "couldn't map ports/memory\n"); 898 return (ENXIO); 899 } 900 sc->rl_btag = rman_get_bustag(sc->rl_res); 901 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 902 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 903 bus_release_resource(dev, RL_RES, 904 RL_RID, sc->rl_res); 905 if (t->rl_basetype == hwrev) { 906 device_set_desc(dev, t->rl_name); 907 return (BUS_PROBE_DEFAULT); 908 } 909 } 910 t++; 911 } 912 913 return (ENXIO); 914} 915 916/* 917 * This routine takes the segment list provided as the result of 918 * a bus_dma_map_load() operation and assigns the addresses/lengths 919 * to RealTek DMA descriptors. This can be called either by the RX 920 * code or the TX code. In the RX case, we'll probably wind up mapping 921 * at most one segment. For the TX case, there could be any number of 922 * segments since TX packets may span multiple mbufs. In either case, 923 * if the number of segments is larger than the rl_maxsegs limit 924 * specified by the caller, we abort the mapping operation. Sadly, 925 * whoever designed the buffer mapping API did not provide a way to 926 * return an error from here, so we have to fake it a bit. 927 */ 928 929static void 930re_dma_map_desc(arg, segs, nseg, mapsize, error) 931 void *arg; 932 bus_dma_segment_t *segs; 933 int nseg; 934 bus_size_t mapsize; 935 int error; 936{ 937 struct rl_dmaload_arg *ctx; 938 struct rl_desc *d = NULL; 939 int i = 0, idx; 940 u_int32_t cmdstat; 941 int totlen = 0; 942 943 if (error) 944 return; 945 946 ctx = arg; 947 948 /* Signal error to caller if there's too many segments */ 949 if (nseg > ctx->rl_maxsegs) { 950 ctx->rl_maxsegs = 0; 951 return; 952 } 953 954 /* 955 * Map the segment array into descriptors. Note that we set the 956 * start-of-frame and end-of-frame markers for either TX or RX, but 957 * they really only have meaning in the TX case. (In the RX case, 958 * it's the chip that tells us where packets begin and end.) 959 * We also keep track of the end of the ring and set the 960 * end-of-ring bits as needed, and we set the ownership bits 961 * in all except the very first descriptor. (The caller will 962 * set this descriptor later when it start transmission or 963 * reception.) 964 */ 965 idx = ctx->rl_idx; 966 for (;;) { 967 d = &ctx->rl_ring[idx]; 968 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 969 ctx->rl_maxsegs = 0; 970 return; 971 } 972 cmdstat = segs[i].ds_len; 973 totlen += segs[i].ds_len; 974 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 975 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 976 if (i == 0) 977 cmdstat |= RL_TDESC_CMD_SOF; 978 else 979 cmdstat |= RL_TDESC_CMD_OWN; 980 if (idx == (RL_RX_DESC_CNT - 1)) 981 cmdstat |= RL_TDESC_CMD_EOR; 982 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 983 i++; 984 if (i == nseg) 985 break; 986 RL_DESC_INC(idx); 987 } 988 989 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 990 ctx->rl_maxsegs = nseg; 991 ctx->rl_idx = idx; 992} 993 994/* 995 * Map a single buffer address. 996 */ 997 998static void 999re_dma_map_addr(arg, segs, nseg, error) 1000 void *arg; 1001 bus_dma_segment_t *segs; 1002 int nseg; 1003 int error; 1004{ 1005 bus_addr_t *addr; 1006 1007 if (error) 1008 return; 1009 1010 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1011 addr = arg; 1012 *addr = segs->ds_addr; 1013} 1014 1015static int 1016re_allocmem(dev, sc) 1017 device_t dev; 1018 struct rl_softc *sc; 1019{ 1020 int error; 1021 int nseg; 1022 int i; 1023 1024 /* 1025 * Allocate map for RX mbufs. 1026 */ 1027 nseg = 32; 1028 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 1029 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1030 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 1031 NULL, NULL, &sc->rl_ldata.rl_mtag); 1032 if (error) { 1033 device_printf(dev, "could not allocate dma tag\n"); 1034 return (ENOMEM); 1035 } 1036 1037 /* 1038 * Allocate map for TX descriptor list. 1039 */ 1040 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1041 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1042 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1043 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1044 if (error) { 1045 device_printf(dev, "could not allocate dma tag\n"); 1046 return (ENOMEM); 1047 } 1048 1049 /* Allocate DMA'able memory for the TX ring */ 1050 1051 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1052 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1053 &sc->rl_ldata.rl_tx_list_map); 1054 if (error) 1055 return (ENOMEM); 1056 1057 /* Load the map for the TX ring. */ 1058 1059 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1060 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1061 RL_TX_LIST_SZ, re_dma_map_addr, 1062 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1063 1064 /* Create DMA maps for TX buffers */ 1065 1066 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1067 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1068 &sc->rl_ldata.rl_tx_dmamap[i]); 1069 if (error) { 1070 device_printf(dev, "can't create DMA map for TX\n"); 1071 return (ENOMEM); 1072 } 1073 } 1074 1075 /* 1076 * Allocate map for RX descriptor list. 1077 */ 1078 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1079 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1080 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1081 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1082 if (error) { 1083 device_printf(dev, "could not allocate dma tag\n"); 1084 return (ENOMEM); 1085 } 1086 1087 /* Allocate DMA'able memory for the RX ring */ 1088 1089 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1090 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1091 &sc->rl_ldata.rl_rx_list_map); 1092 if (error) 1093 return (ENOMEM); 1094 1095 /* Load the map for the RX ring. */ 1096 1097 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1098 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1099 RL_RX_LIST_SZ, re_dma_map_addr, 1100 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1101 1102 /* Create DMA maps for RX buffers */ 1103 1104 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1105 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1106 &sc->rl_ldata.rl_rx_dmamap[i]); 1107 if (error) { 1108 device_printf(dev, "can't create DMA map for RX\n"); 1109 return (ENOMEM); 1110 } 1111 } 1112 1113 return (0); 1114} 1115 1116/* 1117 * Attach the interface. Allocate softc structures, do ifmedia 1118 * setup and ethernet/BPF attach. 1119 */ 1120static int 1121re_attach(dev) 1122 device_t dev; 1123{ 1124 u_char eaddr[ETHER_ADDR_LEN]; 1125 u_int16_t as[ETHER_ADDR_LEN / 2]; 1126 struct rl_softc *sc; 1127 struct ifnet *ifp; 1128 struct rl_hwrev *hw_rev; 1129 int hwrev; 1130 u_int16_t re_did = 0; 1131 int error = 0, rid, i; 1132 1133 sc = device_get_softc(dev); 1134 sc->rl_dev = dev; 1135 1136 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1137 MTX_DEF); 1138 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1139 1140 /* 1141 * Map control/status registers. 1142 */ 1143 pci_enable_busmaster(dev); 1144 1145 rid = RL_RID; 1146 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1147 RF_ACTIVE); 1148 1149 if (sc->rl_res == NULL) { 1150 device_printf(dev, "couldn't map ports/memory\n"); 1151 error = ENXIO; 1152 goto fail; 1153 } 1154 1155 sc->rl_btag = rman_get_bustag(sc->rl_res); 1156 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1157 1158 /* Allocate interrupt */ 1159 rid = 0; 1160 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1161 RF_SHAREABLE | RF_ACTIVE); 1162 1163 if (sc->rl_irq == NULL) { 1164 device_printf(dev, "couldn't map interrupt\n"); 1165 error = ENXIO; 1166 goto fail; 1167 } 1168 1169 /* Reset the adapter. */ 1170 RL_LOCK(sc); 1171 re_reset(sc); 1172 RL_UNLOCK(sc); 1173 1174 hw_rev = re_hwrevs; 1175 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1176 while (hw_rev->rl_desc != NULL) { 1177 if (hw_rev->rl_rev == hwrev) { 1178 sc->rl_type = hw_rev->rl_type; 1179 break; 1180 } 1181 hw_rev++; 1182 } 1183 1184 sc->rl_eewidth = 6; 1185 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1186 if (re_did != 0x8129) 1187 sc->rl_eewidth = 8; 1188 1189 /* 1190 * Get station address from the EEPROM. 1191 */ 1192 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1193 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1194 as[i] = le16toh(as[i]); 1195 bcopy(as, eaddr, sizeof(eaddr)); 1196 1197 if (sc->rl_type == RL_8169) { 1198 /* Set RX length mask */ 1199 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1200 sc->rl_txstart = RL_GTXSTART; 1201 } else { 1202 /* Set RX length mask */ 1203 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1204 sc->rl_txstart = RL_TXSTART; 1205 } 1206 1207 /* 1208 * Allocate the parent bus DMA tag appropriate for PCI. 1209 */ 1210#define RL_NSEG_NEW 32 1211 error = bus_dma_tag_create(NULL, /* parent */ 1212 1, 0, /* alignment, boundary */ 1213 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1214 BUS_SPACE_MAXADDR, /* highaddr */ 1215 NULL, NULL, /* filter, filterarg */ 1216 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1217 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1218 BUS_DMA_ALLOCNOW, /* flags */ 1219 NULL, NULL, /* lockfunc, lockarg */ 1220 &sc->rl_parent_tag); 1221 if (error) 1222 goto fail; 1223 1224 error = re_allocmem(dev, sc); 1225 1226 if (error) 1227 goto fail; 1228 1229 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1230 if (ifp == NULL) { 1231 device_printf(dev, "can not if_alloc()\n"); 1232 error = ENOSPC; 1233 goto fail; 1234 } 1235 1236 /* Do MII setup */ 1237 if (mii_phy_probe(dev, &sc->rl_miibus, 1238 re_ifmedia_upd, re_ifmedia_sts)) { 1239 device_printf(dev, "MII without any phy!\n"); 1240 error = ENXIO; 1241 goto fail; 1242 } 1243 1244 ifp->if_softc = sc; 1245 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1246 ifp->if_mtu = ETHERMTU; 1247 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1248 ifp->if_ioctl = re_ioctl; 1249 ifp->if_capabilities = IFCAP_VLAN_MTU; 1250 ifp->if_start = re_start; 1251 ifp->if_hwassist = RE_CSUM_FEATURES; 1252 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1253 ifp->if_capenable = ifp->if_capabilities; 1254#ifdef DEVICE_POLLING 1255 ifp->if_capabilities |= IFCAP_POLLING; 1256#endif 1257 ifp->if_watchdog = re_watchdog; 1258 ifp->if_init = re_init; 1259 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1260 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1261 IFQ_SET_READY(&ifp->if_snd); 1262 1263 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1264 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1265 1266 /* 1267 * Call MI attach routine. 1268 */ 1269 ether_ifattach(ifp, eaddr); 1270 1271#ifdef RE_DIAG 1272 /* 1273 * Perform hardware diagnostic on the original RTL8169. 1274 * Some 32-bit cards were incorrectly wired and would 1275 * malfunction if plugged into a 64-bit slot. 1276 */ 1277 1278 if (hwrev == RL_HWREV_8169) { 1279 error = re_diag(sc); 1280 if (error) { 1281 device_printf(dev, 1282 "attach aborted due to hardware diag failure\n"); 1283 ether_ifdetach(ifp); 1284 goto fail; 1285 } 1286 } 1287#endif 1288 1289 /* Hook interrupt last to avoid having to lock softc */ 1290 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE | 1291 INTR_FAST, re_intr, sc, &sc->rl_intrhand); 1292 if (error) { 1293 device_printf(dev, "couldn't set up irq\n"); 1294 ether_ifdetach(ifp); 1295 } 1296 1297fail: 1298 1299 if (error) 1300 re_detach(dev); 1301 1302 return (error); 1303} 1304 1305/* 1306 * Shutdown hardware and free up resources. This can be called any 1307 * time after the mutex has been initialized. It is called in both 1308 * the error case in attach and the normal detach case so it needs 1309 * to be careful about only freeing resources that have actually been 1310 * allocated. 1311 */ 1312static int 1313re_detach(dev) 1314 device_t dev; 1315{ 1316 struct rl_softc *sc; 1317 struct ifnet *ifp; 1318 int i; 1319 1320 sc = device_get_softc(dev); 1321 ifp = sc->rl_ifp; 1322 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1323 1324#ifdef DEVICE_POLLING 1325 if (ifp->if_capenable & IFCAP_POLLING) 1326 ether_poll_deregister(ifp); 1327#endif 1328 /* These should only be active if attach succeeded */ 1329 if (device_is_attached(dev)) { 1330 RL_LOCK(sc); 1331#if 0 1332 sc->suspended = 1; 1333#endif 1334 re_stop(sc); 1335 RL_UNLOCK(sc); 1336 callout_drain(&sc->rl_stat_callout); 1337 /* 1338 * Force off the IFF_UP flag here, in case someone 1339 * still had a BPF descriptor attached to this 1340 * interface. If they do, ether_ifdetach() will cause 1341 * the BPF code to try and clear the promisc mode 1342 * flag, which will bubble down to re_ioctl(), 1343 * which will try to call re_init() again. This will 1344 * turn the NIC back on and restart the MII ticker, 1345 * which will panic the system when the kernel tries 1346 * to invoke the re_tick() function that isn't there 1347 * anymore. 1348 */ 1349 ifp->if_flags &= ~IFF_UP; 1350 ether_ifdetach(ifp); 1351 } 1352 if (sc->rl_miibus) 1353 device_delete_child(dev, sc->rl_miibus); 1354 bus_generic_detach(dev); 1355 1356 /* 1357 * The rest is resource deallocation, so we should already be 1358 * stopped here. 1359 */ 1360 1361 if (sc->rl_intrhand) 1362 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1363 if (ifp != NULL) 1364 if_free(ifp); 1365 if (sc->rl_irq) 1366 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1367 if (sc->rl_res) 1368 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1369 1370 /* Yield the CPU long enough for any tasks to drain */ 1371 1372 tsleep(sc, PPAUSE, "rewait", hz); 1373 1374 /* Unload and free the RX DMA ring memory and map */ 1375 1376 if (sc->rl_ldata.rl_rx_list_tag) { 1377 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1378 sc->rl_ldata.rl_rx_list_map); 1379 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1380 sc->rl_ldata.rl_rx_list, 1381 sc->rl_ldata.rl_rx_list_map); 1382 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1383 } 1384 1385 /* Unload and free the TX DMA ring memory and map */ 1386 1387 if (sc->rl_ldata.rl_tx_list_tag) { 1388 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1389 sc->rl_ldata.rl_tx_list_map); 1390 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1391 sc->rl_ldata.rl_tx_list, 1392 sc->rl_ldata.rl_tx_list_map); 1393 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1394 } 1395 1396 /* Destroy all the RX and TX buffer maps */ 1397 1398 if (sc->rl_ldata.rl_mtag) { 1399 for (i = 0; i < RL_TX_DESC_CNT; i++) 1400 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1401 sc->rl_ldata.rl_tx_dmamap[i]); 1402 for (i = 0; i < RL_RX_DESC_CNT; i++) 1403 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1404 sc->rl_ldata.rl_rx_dmamap[i]); 1405 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1406 } 1407 1408 /* Unload and free the stats buffer and map */ 1409 1410 if (sc->rl_ldata.rl_stag) { 1411 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1412 sc->rl_ldata.rl_rx_list_map); 1413 bus_dmamem_free(sc->rl_ldata.rl_stag, 1414 sc->rl_ldata.rl_stats, 1415 sc->rl_ldata.rl_smap); 1416 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1417 } 1418 1419 if (sc->rl_parent_tag) 1420 bus_dma_tag_destroy(sc->rl_parent_tag); 1421 1422 mtx_destroy(&sc->rl_mtx); 1423 1424 return (0); 1425} 1426 1427static int 1428re_newbuf(sc, idx, m) 1429 struct rl_softc *sc; 1430 int idx; 1431 struct mbuf *m; 1432{ 1433 struct rl_dmaload_arg arg; 1434 struct mbuf *n = NULL; 1435 int error; 1436 1437 if (m == NULL) { 1438 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1439 if (n == NULL) 1440 return (ENOBUFS); 1441 m = n; 1442 } else 1443 m->m_data = m->m_ext.ext_buf; 1444 1445 m->m_len = m->m_pkthdr.len = MCLBYTES; 1446#ifdef RE_FIXUP_RX 1447 /* 1448 * This is part of an evil trick to deal with non-x86 platforms. 1449 * The RealTek chip requires RX buffers to be aligned on 64-bit 1450 * boundaries, but that will hose non-x86 machines. To get around 1451 * this, we leave some empty space at the start of each buffer 1452 * and for non-x86 hosts, we copy the buffer back six bytes 1453 * to achieve word alignment. This is slightly more efficient 1454 * than allocating a new buffer, copying the contents, and 1455 * discarding the old buffer. 1456 */ 1457 m_adj(m, RE_ETHER_ALIGN); 1458#endif 1459 arg.sc = sc; 1460 arg.rl_idx = idx; 1461 arg.rl_maxsegs = 1; 1462 arg.rl_flags = 0; 1463 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1464 1465 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1466 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1467 &arg, BUS_DMA_NOWAIT); 1468 if (error || arg.rl_maxsegs != 1) { 1469 if (n != NULL) 1470 m_freem(n); 1471 return (ENOMEM); 1472 } 1473 1474 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1475 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1476 1477 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1478 sc->rl_ldata.rl_rx_dmamap[idx], 1479 BUS_DMASYNC_PREREAD); 1480 1481 return (0); 1482} 1483 1484#ifdef RE_FIXUP_RX 1485static __inline void 1486re_fixup_rx(m) 1487 struct mbuf *m; 1488{ 1489 int i; 1490 uint16_t *src, *dst; 1491 1492 src = mtod(m, uint16_t *); 1493 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1494 1495 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1496 *dst++ = *src++; 1497 1498 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1499 1500 return; 1501} 1502#endif 1503 1504static int 1505re_tx_list_init(sc) 1506 struct rl_softc *sc; 1507{ 1508 1509 RL_LOCK_ASSERT(sc); 1510 1511 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1512 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1513 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1514 1515 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1516 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1517 sc->rl_ldata.rl_tx_prodidx = 0; 1518 sc->rl_ldata.rl_tx_considx = 0; 1519 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1520 1521 return (0); 1522} 1523 1524static int 1525re_rx_list_init(sc) 1526 struct rl_softc *sc; 1527{ 1528 int i; 1529 1530 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1531 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1532 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1533 1534 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1535 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1536 return (ENOBUFS); 1537 } 1538 1539 /* Flush the RX descriptors */ 1540 1541 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1542 sc->rl_ldata.rl_rx_list_map, 1543 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1544 1545 sc->rl_ldata.rl_rx_prodidx = 0; 1546 sc->rl_head = sc->rl_tail = NULL; 1547 1548 return (0); 1549} 1550 1551/* 1552 * RX handler for C+ and 8169. For the gigE chips, we support 1553 * the reception of jumbo frames that have been fragmented 1554 * across multiple 2K mbuf cluster buffers. 1555 */ 1556static int 1557re_rxeof(sc) 1558 struct rl_softc *sc; 1559{ 1560 struct mbuf *m; 1561 struct ifnet *ifp; 1562 int i, total_len; 1563 struct rl_desc *cur_rx; 1564 u_int32_t rxstat, rxvlan; 1565 int maxpkt = 16; 1566 1567 RL_LOCK_ASSERT(sc); 1568 1569 ifp = sc->rl_ifp; 1570 i = sc->rl_ldata.rl_rx_prodidx; 1571 1572 /* Invalidate the descriptor memory */ 1573 1574 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1575 sc->rl_ldata.rl_rx_list_map, 1576 BUS_DMASYNC_POSTREAD); 1577 1578 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) { 1579 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1580 m = sc->rl_ldata.rl_rx_mbuf[i]; 1581 total_len = RL_RXBYTES(cur_rx); 1582 rxstat = le32toh(cur_rx->rl_cmdstat); 1583 rxvlan = le32toh(cur_rx->rl_vlanctl); 1584 1585 /* Invalidate the RX mbuf and unload its map */ 1586 1587 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1588 sc->rl_ldata.rl_rx_dmamap[i], 1589 BUS_DMASYNC_POSTWRITE); 1590 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1591 sc->rl_ldata.rl_rx_dmamap[i]); 1592 1593 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1594 m->m_len = RE_RX_DESC_BUFLEN; 1595 if (sc->rl_head == NULL) 1596 sc->rl_head = sc->rl_tail = m; 1597 else { 1598 m->m_flags &= ~M_PKTHDR; 1599 sc->rl_tail->m_next = m; 1600 sc->rl_tail = m; 1601 } 1602 re_newbuf(sc, i, NULL); 1603 RL_DESC_INC(i); 1604 continue; 1605 } 1606 1607 /* 1608 * NOTE: for the 8139C+, the frame length field 1609 * is always 12 bits in size, but for the gigE chips, 1610 * it is 13 bits (since the max RX frame length is 16K). 1611 * Unfortunately, all 32 bits in the status word 1612 * were already used, so to make room for the extra 1613 * length bit, RealTek took out the 'frame alignment 1614 * error' bit and shifted the other status bits 1615 * over one slot. The OWN, EOR, FS and LS bits are 1616 * still in the same places. We have already extracted 1617 * the frame length and checked the OWN bit, so rather 1618 * than using an alternate bit mapping, we shift the 1619 * status bits one space to the right so we can evaluate 1620 * them using the 8169 status as though it was in the 1621 * same format as that of the 8139C+. 1622 */ 1623 if (sc->rl_type == RL_8169) 1624 rxstat >>= 1; 1625 1626 /* 1627 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1628 * set, but if CRC is clear, it will still be a valid frame. 1629 */ 1630 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1631 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1632 ifp->if_ierrors++; 1633 /* 1634 * If this is part of a multi-fragment packet, 1635 * discard all the pieces. 1636 */ 1637 if (sc->rl_head != NULL) { 1638 m_freem(sc->rl_head); 1639 sc->rl_head = sc->rl_tail = NULL; 1640 } 1641 re_newbuf(sc, i, m); 1642 RL_DESC_INC(i); 1643 continue; 1644 } 1645 1646 /* 1647 * If allocating a replacement mbuf fails, 1648 * reload the current one. 1649 */ 1650 1651 if (re_newbuf(sc, i, NULL)) { 1652 ifp->if_ierrors++; 1653 if (sc->rl_head != NULL) { 1654 m_freem(sc->rl_head); 1655 sc->rl_head = sc->rl_tail = NULL; 1656 } 1657 re_newbuf(sc, i, m); 1658 RL_DESC_INC(i); 1659 continue; 1660 } 1661 1662 RL_DESC_INC(i); 1663 1664 if (sc->rl_head != NULL) { 1665 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1666 if (m->m_len == 0) 1667 m->m_len = RE_RX_DESC_BUFLEN; 1668 /* 1669 * Special case: if there's 4 bytes or less 1670 * in this buffer, the mbuf can be discarded: 1671 * the last 4 bytes is the CRC, which we don't 1672 * care about anyway. 1673 */ 1674 if (m->m_len <= ETHER_CRC_LEN) { 1675 sc->rl_tail->m_len -= 1676 (ETHER_CRC_LEN - m->m_len); 1677 m_freem(m); 1678 } else { 1679 m->m_len -= ETHER_CRC_LEN; 1680 m->m_flags &= ~M_PKTHDR; 1681 sc->rl_tail->m_next = m; 1682 } 1683 m = sc->rl_head; 1684 sc->rl_head = sc->rl_tail = NULL; 1685 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1686 } else 1687 m->m_pkthdr.len = m->m_len = 1688 (total_len - ETHER_CRC_LEN); 1689 1690#ifdef RE_FIXUP_RX 1691 re_fixup_rx(m); 1692#endif 1693 ifp->if_ipackets++; 1694 m->m_pkthdr.rcvif = ifp; 1695 1696 /* Do RX checksumming if enabled */ 1697 1698 if (ifp->if_capenable & IFCAP_RXCSUM) { 1699 1700 /* Check IP header checksum */ 1701 if (rxstat & RL_RDESC_STAT_PROTOID) 1702 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1703 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1704 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1705 1706 /* Check TCP/UDP checksum */ 1707 if ((RL_TCPPKT(rxstat) && 1708 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1709 (RL_UDPPKT(rxstat) && 1710 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1711 m->m_pkthdr.csum_flags |= 1712 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1713 m->m_pkthdr.csum_data = 0xffff; 1714 } 1715 } 1716 maxpkt--; 1717 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1718 VLAN_INPUT_TAG(ifp, m, 1719 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA))); 1720 if (m == NULL) 1721 continue; 1722 } 1723 RL_UNLOCK(sc); 1724 (*ifp->if_input)(ifp, m); 1725 RL_LOCK(sc); 1726 } 1727 1728 /* Flush the RX DMA ring */ 1729 1730 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1731 sc->rl_ldata.rl_rx_list_map, 1732 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1733 1734 sc->rl_ldata.rl_rx_prodidx = i; 1735 1736 if (maxpkt) 1737 return(EAGAIN); 1738 1739 return(0); 1740} 1741 1742static void 1743re_txeof(sc) 1744 struct rl_softc *sc; 1745{ 1746 struct ifnet *ifp; 1747 u_int32_t txstat; 1748 int idx; 1749 1750 ifp = sc->rl_ifp; 1751 idx = sc->rl_ldata.rl_tx_considx; 1752 1753 /* Invalidate the TX descriptor list */ 1754 1755 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1756 sc->rl_ldata.rl_tx_list_map, 1757 BUS_DMASYNC_POSTREAD); 1758 1759 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1760 1761 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1762 if (txstat & RL_TDESC_CMD_OWN) 1763 break; 1764 1765 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0; 1766 1767 /* 1768 * We only stash mbufs in the last descriptor 1769 * in a fragment chain, which also happens to 1770 * be the only place where the TX status bits 1771 * are valid. 1772 */ 1773 1774 if (txstat & RL_TDESC_CMD_EOF) { 1775 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1776 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1777 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1778 sc->rl_ldata.rl_tx_dmamap[idx]); 1779 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1780 RL_TDESC_STAT_COLCNT)) 1781 ifp->if_collisions++; 1782 if (txstat & RL_TDESC_STAT_TXERRSUM) 1783 ifp->if_oerrors++; 1784 else 1785 ifp->if_opackets++; 1786 } 1787 sc->rl_ldata.rl_tx_free++; 1788 RL_DESC_INC(idx); 1789 } 1790 1791 /* No changes made to the TX ring, so no flush needed */ 1792 1793 if (sc->rl_ldata.rl_tx_free) { 1794 sc->rl_ldata.rl_tx_considx = idx; 1795 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1796 ifp->if_timer = 0; 1797 } 1798 1799 /* 1800 * Some chips will ignore a second TX request issued while an 1801 * existing transmission is in progress. If the transmitter goes 1802 * idle but there are still packets waiting to be sent, we need 1803 * to restart the channel here to flush them out. This only seems 1804 * to be required with the PCIe devices. 1805 */ 1806 1807 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) 1808 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1809 1810#ifdef RE_TX_MODERATION 1811 /* 1812 * If not all descriptors have been released reaped yet, 1813 * reload the timer so that we will eventually get another 1814 * interrupt that will cause us to re-enter this routine. 1815 * This is done in case the transmitter has gone idle. 1816 */ 1817 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1818 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1819#endif 1820 1821} 1822 1823static void 1824re_tick(xsc) 1825 void *xsc; 1826{ 1827 struct rl_softc *sc; 1828 struct mii_data *mii; 1829 struct ifnet *ifp; 1830 1831 sc = xsc; 1832 ifp = sc->rl_ifp; 1833 1834 RL_LOCK_ASSERT(sc); 1835 1836 mii = device_get_softc(sc->rl_miibus); 1837 1838 mii_tick(mii); 1839 if (sc->rl_link) { 1840 if (!(mii->mii_media_status & IFM_ACTIVE)) 1841 sc->rl_link = 0; 1842 } else { 1843 if (mii->mii_media_status & IFM_ACTIVE && 1844 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1845 sc->rl_link = 1; 1846 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1847 taskqueue_enqueue_fast(taskqueue_fast, 1848 &sc->rl_txtask); 1849 } 1850 } 1851 1852 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1853} 1854 1855#ifdef DEVICE_POLLING 1856static void 1857re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1858{ 1859 struct rl_softc *sc = ifp->if_softc; 1860 1861 RL_LOCK(sc); 1862 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1863 re_poll_locked(ifp, cmd, count); 1864 RL_UNLOCK(sc); 1865} 1866 1867static void 1868re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1869{ 1870 struct rl_softc *sc = ifp->if_softc; 1871 1872 RL_LOCK_ASSERT(sc); 1873 1874 sc->rxcycles = count; 1875 re_rxeof(sc); 1876 re_txeof(sc); 1877 1878 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1879 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 1880 1881 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1882 u_int16_t status; 1883 1884 status = CSR_READ_2(sc, RL_ISR); 1885 if (status == 0xffff) 1886 return; 1887 if (status) 1888 CSR_WRITE_2(sc, RL_ISR, status); 1889 1890 /* 1891 * XXX check behaviour on receiver stalls. 1892 */ 1893 1894 if (status & RL_ISR_SYSTEM_ERR) { 1895 re_reset(sc); 1896 re_init_locked(sc); 1897 } 1898 } 1899} 1900#endif /* DEVICE_POLLING */ 1901 1902static void 1903re_intr(arg) 1904 void *arg; 1905{ 1906 struct rl_softc *sc; 1907 struct ifnet *ifp; 1908 uint16_t status; 1909 1910 sc = arg; 1911 ifp = sc->rl_ifp; 1912 1913 status = CSR_READ_2(sc, RL_ISR); 1914 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 1915 return; 1916 CSR_WRITE_2(sc, RL_IMR, 0); 1917 1918 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 1919 1920 return; 1921} 1922 1923static void 1924re_int_task(arg, npending) 1925 void *arg; 1926 int npending; 1927{ 1928 struct rl_softc *sc; 1929 struct ifnet *ifp; 1930 u_int16_t status; 1931 int rval = 0; 1932 1933 sc = arg; 1934 ifp = sc->rl_ifp; 1935 1936 RL_LOCK(sc); 1937 1938 status = CSR_READ_2(sc, RL_ISR); 1939 CSR_WRITE_2(sc, RL_ISR, status); 1940 1941 if (sc->suspended || !(ifp->if_flags & IFF_UP)) { 1942 RL_UNLOCK(sc); 1943 return; 1944 } 1945 1946#ifdef DEVICE_POLLING 1947 if (ifp->if_capenable & IFCAP_POLLING) { 1948 RL_UNLOCK(sc); 1949 return; 1950 } 1951#endif 1952 1953 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 1954 rval = re_rxeof(sc); 1955 1956#ifdef RE_TX_MODERATION 1957 if (status & (RL_ISR_TIMEOUT_EXPIRED| 1958#else 1959 if (status & (RL_ISR_TX_OK| 1960#endif 1961 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 1962 re_txeof(sc); 1963 1964 if (status & RL_ISR_SYSTEM_ERR) { 1965 re_reset(sc); 1966 re_init_locked(sc); 1967 } 1968 1969 if (status & RL_ISR_LINKCHG) { 1970 callout_stop(&sc->rl_stat_callout); 1971 re_tick(sc); 1972 } 1973 1974 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1975 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 1976 1977 RL_UNLOCK(sc); 1978 1979 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 1980 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 1981 return; 1982 } 1983 1984 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1985 1986 return; 1987} 1988 1989static int 1990re_encap(sc, m_head, idx) 1991 struct rl_softc *sc; 1992 struct mbuf **m_head; 1993 int *idx; 1994{ 1995 struct mbuf *m_new = NULL; 1996 struct rl_dmaload_arg arg; 1997 bus_dmamap_t map; 1998 int error; 1999 struct m_tag *mtag; 2000 2001 RL_LOCK_ASSERT(sc); 2002 2003 if (sc->rl_ldata.rl_tx_free <= 4) 2004 return (EFBIG); 2005 2006 /* 2007 * Set up checksum offload. Note: checksum offload bits must 2008 * appear in all descriptors of a multi-descriptor transmit 2009 * attempt. This is according to testing done with an 8169 2010 * chip. This is a requirement. 2011 */ 2012 2013 arg.rl_flags = 0; 2014 2015 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2016 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 2017 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2018 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 2019 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2020 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 2021 2022 arg.sc = sc; 2023 arg.rl_idx = *idx; 2024 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2025 if (arg.rl_maxsegs > 4) 2026 arg.rl_maxsegs -= 4; 2027 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2028 2029 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 2030 2031 /* 2032 * With some of the RealTek chips, using the checksum offload 2033 * support in conjunction with the autopadding feature results 2034 * in the transmission of corrupt frames. For example, if we 2035 * need to send a really small IP fragment that's less than 60 2036 * bytes in size, and IP header checksumming is enabled, the 2037 * resulting ethernet frame that appears on the wire will 2038 * have garbled payload. To work around this, if TX checksum 2039 * offload is enabled, we always manually pad short frames out 2040 * to the minimum ethernet frame size. We do this by pretending 2041 * the mbuf chain has too many fragments so the coalescing code 2042 * below can assemble the packet into a single buffer that's 2043 * padded out to the mininum frame size. 2044 */ 2045 2046 if (arg.rl_flags && (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) 2047 error = EFBIG; 2048 else 2049 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2050 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2051 2052 if (error && error != EFBIG) { 2053 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", error); 2054 return (ENOBUFS); 2055 } 2056 2057 /* Too many segments to map, coalesce into a single mbuf */ 2058 2059 if (error || arg.rl_maxsegs == 0) { 2060 m_new = m_defrag(*m_head, M_DONTWAIT); 2061 if (m_new == NULL) 2062 return (ENOBUFS); 2063 else 2064 *m_head = m_new; 2065 2066 /* 2067 * Manually pad short frames, and zero the pad space 2068 * to avoid leaking data. 2069 */ 2070 2071 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) { 2072 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 2073 RL_MIN_FRAMELEN - m_new->m_pkthdr.len); 2074 m_new->m_pkthdr.len += RL_MIN_FRAMELEN - 2075 m_new->m_pkthdr.len; 2076 m_new->m_len = m_new->m_pkthdr.len; 2077 } 2078 2079 arg.sc = sc; 2080 arg.rl_idx = *idx; 2081 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2082 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2083 2084 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2085 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2086 if (error) { 2087 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", 2088 error); 2089 return (EFBIG); 2090 } 2091 } 2092 2093 /* 2094 * Insure that the map for this transmission 2095 * is placed at the array index of the last descriptor 2096 * in this chain. (Swap last and first dmamaps.) 2097 */ 2098 sc->rl_ldata.rl_tx_dmamap[*idx] = 2099 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 2100 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 2101 2102 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 2103 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 2104 2105 /* 2106 * Set up hardware VLAN tagging. Note: vlan tag info must 2107 * appear in the first descriptor of a multi-descriptor 2108 * transmission attempt. 2109 */ 2110 2111 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head); 2112 if (mtag != NULL) 2113 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 2114 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 2115 2116 /* Transfer ownership of packet to the chip. */ 2117 2118 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 2119 htole32(RL_TDESC_CMD_OWN); 2120 if (*idx != arg.rl_idx) 2121 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 2122 htole32(RL_TDESC_CMD_OWN); 2123 2124 RL_DESC_INC(arg.rl_idx); 2125 *idx = arg.rl_idx; 2126 2127 return (0); 2128} 2129 2130static void 2131re_tx_task(arg, npending) 2132 void *arg; 2133 int npending; 2134{ 2135 struct ifnet *ifp; 2136 2137 ifp = arg; 2138 re_start(ifp); 2139 2140 return; 2141} 2142 2143/* 2144 * Main transmit routine for C+ and gigE NICs. 2145 */ 2146static void 2147re_start(ifp) 2148 struct ifnet *ifp; 2149{ 2150 struct rl_softc *sc; 2151 struct mbuf *m_head = NULL; 2152 int idx, queued = 0; 2153 2154 sc = ifp->if_softc; 2155 2156 RL_LOCK(sc); 2157 2158 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 2159 RL_UNLOCK(sc); 2160 return; 2161 } 2162 2163 idx = sc->rl_ldata.rl_tx_prodidx; 2164 2165 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2166 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2167 if (m_head == NULL) 2168 break; 2169 2170 if (re_encap(sc, &m_head, &idx)) { 2171 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2172 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2173 break; 2174 } 2175 2176 /* 2177 * If there's a BPF listener, bounce a copy of this frame 2178 * to him. 2179 */ 2180 BPF_MTAP(ifp, m_head); 2181 2182 queued++; 2183 } 2184 2185 if (queued == 0) { 2186#ifdef RE_TX_MODERATION 2187 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 2188 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2189#endif 2190 RL_UNLOCK(sc); 2191 return; 2192 } 2193 2194 /* Flush the TX descriptors */ 2195 2196 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2197 sc->rl_ldata.rl_tx_list_map, 2198 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2199 2200 sc->rl_ldata.rl_tx_prodidx = idx; 2201 2202 /* 2203 * RealTek put the TX poll request register in a different 2204 * location on the 8169 gigE chip. I don't know why. 2205 */ 2206 2207 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2208 2209#ifdef RE_TX_MODERATION 2210 /* 2211 * Use the countdown timer for interrupt moderation. 2212 * 'TX done' interrupts are disabled. Instead, we reset the 2213 * countdown timer, which will begin counting until it hits 2214 * the value in the TIMERINT register, and then trigger an 2215 * interrupt. Each time we write to the TIMERCNT register, 2216 * the timer count is reset to 0. 2217 */ 2218 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2219#endif 2220 2221 /* 2222 * Set a timeout in case the chip goes out to lunch. 2223 */ 2224 2225 ifp->if_timer = 5; 2226 2227 RL_UNLOCK(sc); 2228 2229 return; 2230} 2231 2232static void 2233re_init(xsc) 2234 void *xsc; 2235{ 2236 struct rl_softc *sc = xsc; 2237 2238 RL_LOCK(sc); 2239 re_init_locked(sc); 2240 RL_UNLOCK(sc); 2241} 2242 2243static void 2244re_init_locked(sc) 2245 struct rl_softc *sc; 2246{ 2247 struct ifnet *ifp = sc->rl_ifp; 2248 struct mii_data *mii; 2249 u_int32_t rxcfg = 0; 2250 union { 2251 uint32_t align_dummy; 2252 u_char eaddr[ETHER_ADDR_LEN]; 2253 } eaddr; 2254 2255 RL_LOCK_ASSERT(sc); 2256 2257 mii = device_get_softc(sc->rl_miibus); 2258 2259 /* 2260 * Cancel pending I/O and free all RX/TX buffers. 2261 */ 2262 re_stop(sc); 2263 2264 /* 2265 * Enable C+ RX and TX mode, as well as VLAN stripping and 2266 * RX checksum offload. We must configure the C+ register 2267 * before all others. 2268 */ 2269 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2270 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2271 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB); 2272 2273 /* 2274 * Init our MAC address. Even though the chipset 2275 * documentation doesn't mention it, we need to enter "Config 2276 * register write enable" mode to modify the ID registers. 2277 */ 2278 /* Copy MAC address on stack to align. */ 2279 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2280 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2281 CSR_WRITE_4(sc, RL_IDR0, 2282 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2283 CSR_WRITE_4(sc, RL_IDR4, 2284 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2285 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2286 2287 /* 2288 * For C+ mode, initialize the RX descriptors and mbufs. 2289 */ 2290 re_rx_list_init(sc); 2291 re_tx_list_init(sc); 2292 2293 /* 2294 * Enable transmit and receive. 2295 */ 2296 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2297 2298 /* 2299 * Set the initial TX and RX configuration. 2300 */ 2301 if (sc->rl_testmode) { 2302 if (sc->rl_type == RL_8169) 2303 CSR_WRITE_4(sc, RL_TXCFG, 2304 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2305 else 2306 CSR_WRITE_4(sc, RL_TXCFG, 2307 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2308 } else 2309 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2310 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2311 2312 /* Set the individual bit to receive frames for this host only. */ 2313 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2314 rxcfg |= RL_RXCFG_RX_INDIV; 2315 2316 /* If we want promiscuous mode, set the allframes bit. */ 2317 if (ifp->if_flags & IFF_PROMISC) 2318 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2319 else 2320 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2321 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2322 2323 /* 2324 * Set capture broadcast bit to capture broadcast frames. 2325 */ 2326 if (ifp->if_flags & IFF_BROADCAST) 2327 rxcfg |= RL_RXCFG_RX_BROAD; 2328 else 2329 rxcfg &= ~RL_RXCFG_RX_BROAD; 2330 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2331 2332 /* 2333 * Program the multicast filter, if necessary. 2334 */ 2335 re_setmulti(sc); 2336 2337#ifdef DEVICE_POLLING 2338 /* 2339 * Disable interrupts if we are polling. 2340 */ 2341 if (ifp->if_capenable & IFCAP_POLLING) 2342 CSR_WRITE_2(sc, RL_IMR, 0); 2343 else /* otherwise ... */ 2344#endif 2345 2346 /* 2347 * Enable interrupts. 2348 */ 2349 if (sc->rl_testmode) 2350 CSR_WRITE_2(sc, RL_IMR, 0); 2351 else 2352 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2353 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2354 2355 /* Set initial TX threshold */ 2356 sc->rl_txthresh = RL_TX_THRESH_INIT; 2357 2358 /* Start RX/TX process. */ 2359 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2360#ifdef notdef 2361 /* Enable receiver and transmitter. */ 2362 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2363#endif 2364 /* 2365 * Load the addresses of the RX and TX lists into the chip. 2366 */ 2367 2368 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2369 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2370 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2371 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2372 2373 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2374 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2375 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2376 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2377 2378 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2379 2380#ifdef RE_TX_MODERATION 2381 /* 2382 * Initialize the timer interrupt register so that 2383 * a timer interrupt will be generated once the timer 2384 * reaches a certain number of ticks. The timer is 2385 * reloaded on each transmit. This gives us TX interrupt 2386 * moderation, which dramatically improves TX frame rate. 2387 */ 2388 if (sc->rl_type == RL_8169) 2389 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2390 else 2391 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2392#endif 2393 2394 /* 2395 * For 8169 gigE NICs, set the max allowed RX packet 2396 * size so we can receive jumbo frames. 2397 */ 2398 if (sc->rl_type == RL_8169) 2399 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2400 2401 if (sc->rl_testmode) 2402 return; 2403 2404 mii_mediachg(mii); 2405 2406 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2407 2408 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2409 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2410 2411 2412 sc->rl_link = 0; 2413 2414 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2415} 2416 2417/* 2418 * Set media options. 2419 */ 2420static int 2421re_ifmedia_upd(ifp) 2422 struct ifnet *ifp; 2423{ 2424 struct rl_softc *sc; 2425 struct mii_data *mii; 2426 2427 sc = ifp->if_softc; 2428 mii = device_get_softc(sc->rl_miibus); 2429 RL_LOCK(sc); 2430 mii_mediachg(mii); 2431 RL_UNLOCK(sc); 2432 2433 return (0); 2434} 2435 2436/* 2437 * Report current media status. 2438 */ 2439static void 2440re_ifmedia_sts(ifp, ifmr) 2441 struct ifnet *ifp; 2442 struct ifmediareq *ifmr; 2443{ 2444 struct rl_softc *sc; 2445 struct mii_data *mii; 2446 2447 sc = ifp->if_softc; 2448 mii = device_get_softc(sc->rl_miibus); 2449 2450 RL_LOCK(sc); 2451 mii_pollstat(mii); 2452 RL_UNLOCK(sc); 2453 ifmr->ifm_active = mii->mii_media_active; 2454 ifmr->ifm_status = mii->mii_media_status; 2455} 2456 2457static int 2458re_ioctl(ifp, command, data) 2459 struct ifnet *ifp; 2460 u_long command; 2461 caddr_t data; 2462{ 2463 struct rl_softc *sc = ifp->if_softc; 2464 struct ifreq *ifr = (struct ifreq *) data; 2465 struct mii_data *mii; 2466 int error = 0; 2467 2468 switch (command) { 2469 case SIOCSIFMTU: 2470 RL_LOCK(sc); 2471 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2472 error = EINVAL; 2473 ifp->if_mtu = ifr->ifr_mtu; 2474 RL_UNLOCK(sc); 2475 break; 2476 case SIOCSIFFLAGS: 2477 RL_LOCK(sc); 2478 if (ifp->if_flags & IFF_UP) 2479 re_init_locked(sc); 2480 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2481 re_stop(sc); 2482 RL_UNLOCK(sc); 2483 break; 2484 case SIOCADDMULTI: 2485 case SIOCDELMULTI: 2486 RL_LOCK(sc); 2487 re_setmulti(sc); 2488 RL_UNLOCK(sc); 2489 break; 2490 case SIOCGIFMEDIA: 2491 case SIOCSIFMEDIA: 2492 mii = device_get_softc(sc->rl_miibus); 2493 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2494 break; 2495 case SIOCSIFCAP: 2496 { 2497 int mask, reinit; 2498 2499 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2500 reinit = 0; 2501#ifdef DEVICE_POLLING 2502 if (mask & IFCAP_POLLING) { 2503 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2504 error = ether_poll_register(re_poll, ifp); 2505 if (error) 2506 return(error); 2507 RL_LOCK(sc); 2508 /* Disable interrupts */ 2509 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2510 ifp->if_capenable |= IFCAP_POLLING; 2511 RL_UNLOCK(sc); 2512 2513 } else { 2514 error = ether_poll_deregister(ifp); 2515 /* Enable interrupts. */ 2516 RL_LOCK(sc); 2517 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2518 ifp->if_capenable &= ~IFCAP_POLLING; 2519 RL_UNLOCK(sc); 2520 } 2521 } 2522#endif /* DEVICE_POLLING */ 2523 if (mask & IFCAP_HWCSUM) { 2524 ifp->if_capenable ^= IFCAP_HWCSUM; 2525 if (ifp->if_capenable & IFCAP_TXCSUM) 2526 ifp->if_hwassist = RE_CSUM_FEATURES; 2527 else 2528 ifp->if_hwassist = 0; 2529 reinit = 1; 2530 } 2531 if (mask & IFCAP_VLAN_HWTAGGING) { 2532 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2533 reinit = 1; 2534 } 2535 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2536 re_init(sc); 2537 } 2538 break; 2539 default: 2540 error = ether_ioctl(ifp, command, data); 2541 break; 2542 } 2543 2544 return (error); 2545} 2546 2547static void 2548re_watchdog(ifp) 2549 struct ifnet *ifp; 2550{ 2551 struct rl_softc *sc; 2552 2553 sc = ifp->if_softc; 2554 RL_LOCK(sc); 2555 if_printf(ifp, "watchdog timeout\n"); 2556 ifp->if_oerrors++; 2557 2558 re_txeof(sc); 2559 re_rxeof(sc); 2560 re_init_locked(sc); 2561 2562 RL_UNLOCK(sc); 2563} 2564 2565/* 2566 * Stop the adapter and free any mbufs allocated to the 2567 * RX and TX lists. 2568 */ 2569static void 2570re_stop(sc) 2571 struct rl_softc *sc; 2572{ 2573 register int i; 2574 struct ifnet *ifp; 2575 2576 RL_LOCK_ASSERT(sc); 2577 2578 ifp = sc->rl_ifp; 2579 ifp->if_timer = 0; 2580 2581 callout_stop(&sc->rl_stat_callout); 2582 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2583 2584 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2585 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2586 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2587 2588 if (sc->rl_head != NULL) { 2589 m_freem(sc->rl_head); 2590 sc->rl_head = sc->rl_tail = NULL; 2591 } 2592 2593 /* Free the TX list buffers. */ 2594 2595 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2596 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2597 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2598 sc->rl_ldata.rl_tx_dmamap[i]); 2599 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2600 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2601 } 2602 } 2603 2604 /* Free the RX list buffers. */ 2605 2606 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2607 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2608 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2609 sc->rl_ldata.rl_rx_dmamap[i]); 2610 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2611 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2612 } 2613 } 2614} 2615 2616/* 2617 * Device suspend routine. Stop the interface and save some PCI 2618 * settings in case the BIOS doesn't restore them properly on 2619 * resume. 2620 */ 2621static int 2622re_suspend(dev) 2623 device_t dev; 2624{ 2625 struct rl_softc *sc; 2626 2627 sc = device_get_softc(dev); 2628 2629 RL_LOCK(sc); 2630 re_stop(sc); 2631 sc->suspended = 1; 2632 RL_UNLOCK(sc); 2633 2634 return (0); 2635} 2636 2637/* 2638 * Device resume routine. Restore some PCI settings in case the BIOS 2639 * doesn't, re-enable busmastering, and restart the interface if 2640 * appropriate. 2641 */ 2642static int 2643re_resume(dev) 2644 device_t dev; 2645{ 2646 struct rl_softc *sc; 2647 struct ifnet *ifp; 2648 2649 sc = device_get_softc(dev); 2650 2651 RL_LOCK(sc); 2652 2653 ifp = sc->rl_ifp; 2654 2655 /* reinitialize interface if necessary */ 2656 if (ifp->if_flags & IFF_UP) 2657 re_init_locked(sc); 2658 2659 sc->suspended = 0; 2660 RL_UNLOCK(sc); 2661 2662 return (0); 2663} 2664 2665/* 2666 * Stop all chip I/O so that the kernel's probe routines don't 2667 * get confused by errant DMAs when rebooting. 2668 */ 2669static void 2670re_shutdown(dev) 2671 device_t dev; 2672{ 2673 struct rl_softc *sc; 2674 2675 sc = device_get_softc(dev); 2676 2677 RL_LOCK(sc); 2678 re_stop(sc); 2679 /* 2680 * Mark interface as down since otherwise we will panic if 2681 * interrupt comes in later on, which can happen in some 2682 * cases. 2683 */ 2684 sc->rl_ifp->if_flags &= ~IFF_UP; 2685 RL_UNLOCK(sc); 2686} 2687