if_re.c revision 153512
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 153512 2005-12-18 18:24:27Z glebius $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124 125#include <net/if.h> 126#include <net/if_arp.h> 127#include <net/ethernet.h> 128#include <net/if_dl.h> 129#include <net/if_media.h> 130#include <net/if_types.h> 131#include <net/if_vlan_var.h> 132 133#include <net/bpf.h> 134 135#include <machine/bus.h> 136#include <machine/resource.h> 137#include <sys/bus.h> 138#include <sys/rman.h> 139 140#include <dev/mii/mii.h> 141#include <dev/mii/miivar.h> 142 143#include <dev/pci/pcireg.h> 144#include <dev/pci/pcivar.h> 145 146MODULE_DEPEND(re, pci, 1, 1, 1); 147MODULE_DEPEND(re, ether, 1, 1, 1); 148MODULE_DEPEND(re, miibus, 1, 1, 1); 149 150/* "device miibus" required. See GENERIC if you get errors here. */ 151#include "miibus_if.h" 152 153/* 154 * Default to using PIO access for this driver. 155 */ 156#define RE_USEIOSPACE 157 158#include <pci/if_rlreg.h> 159 160#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 161 162/* 163 * Various supported device vendors/types and their names. 164 */ 165static struct rl_type re_devs[] = { 166 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 167 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 168 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 169 "RealTek 8139C+ 10/100BaseTX" }, 170 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 171 "RealTek 8169 Gigabit Ethernet" }, 172 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 173 "RealTek 8169S Single-chip Gigabit Ethernet" }, 174 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB, 175 "RealTek 8169SB Single-chip Gigabit Ethernet" }, 176 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 177 "RealTek 8110S Single-chip Gigabit Ethernet" }, 178 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 179 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 180 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 181 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 182 { 0, 0, 0, NULL } 183}; 184 185static struct rl_hwrev re_hwrevs[] = { 186 { RL_HWREV_8139, RL_8139, "" }, 187 { RL_HWREV_8139A, RL_8139, "A" }, 188 { RL_HWREV_8139AG, RL_8139, "A-G" }, 189 { RL_HWREV_8139B, RL_8139, "B" }, 190 { RL_HWREV_8130, RL_8139, "8130" }, 191 { RL_HWREV_8139C, RL_8139, "C" }, 192 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 193 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 194 { RL_HWREV_8169, RL_8169, "8169"}, 195 { RL_HWREV_8169S, RL_8169, "8169S"}, 196 { RL_HWREV_8169SB, RL_8169, "8169SB"}, 197 { RL_HWREV_8110S, RL_8169, "8110S"}, 198 { RL_HWREV_8100, RL_8139, "8100"}, 199 { RL_HWREV_8101, RL_8139, "8101"}, 200 { 0, 0, NULL } 201}; 202 203static int re_probe (device_t); 204static int re_attach (device_t); 205static int re_detach (device_t); 206 207static int re_encap (struct rl_softc *, struct mbuf **, int *); 208 209static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 210static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 211 bus_size_t, int); 212static int re_allocmem (device_t, struct rl_softc *); 213static int re_newbuf (struct rl_softc *, int, struct mbuf *); 214static int re_rx_list_init (struct rl_softc *); 215static int re_tx_list_init (struct rl_softc *); 216#ifdef RE_FIXUP_RX 217static __inline void re_fixup_rx 218 (struct mbuf *); 219#endif 220static void re_rxeof (struct rl_softc *); 221static void re_txeof (struct rl_softc *); 222#ifdef DEVICE_POLLING 223static void re_poll (struct ifnet *, enum poll_cmd, int); 224static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 225#endif 226static void re_intr (void *); 227static void re_tick (void *); 228static void re_start (struct ifnet *); 229static void re_start_locked (struct ifnet *); 230static int re_ioctl (struct ifnet *, u_long, caddr_t); 231static void re_init (void *); 232static void re_init_locked (struct rl_softc *); 233static void re_stop (struct rl_softc *); 234static void re_watchdog (struct ifnet *); 235static int re_suspend (device_t); 236static int re_resume (device_t); 237static void re_shutdown (device_t); 238static int re_ifmedia_upd (struct ifnet *); 239static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 240 241static void re_eeprom_putbyte (struct rl_softc *, int); 242static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 243static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 244static int re_gmii_readreg (device_t, int, int); 245static int re_gmii_writereg (device_t, int, int, int); 246 247static int re_miibus_readreg (device_t, int, int); 248static int re_miibus_writereg (device_t, int, int, int); 249static void re_miibus_statchg (device_t); 250 251static void re_setmulti (struct rl_softc *); 252static void re_reset (struct rl_softc *); 253 254static int re_diag (struct rl_softc *); 255 256#ifdef RE_USEIOSPACE 257#define RL_RES SYS_RES_IOPORT 258#define RL_RID RL_PCI_LOIO 259#else 260#define RL_RES SYS_RES_MEMORY 261#define RL_RID RL_PCI_LOMEM 262#endif 263 264static device_method_t re_methods[] = { 265 /* Device interface */ 266 DEVMETHOD(device_probe, re_probe), 267 DEVMETHOD(device_attach, re_attach), 268 DEVMETHOD(device_detach, re_detach), 269 DEVMETHOD(device_suspend, re_suspend), 270 DEVMETHOD(device_resume, re_resume), 271 DEVMETHOD(device_shutdown, re_shutdown), 272 273 /* bus interface */ 274 DEVMETHOD(bus_print_child, bus_generic_print_child), 275 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 276 277 /* MII interface */ 278 DEVMETHOD(miibus_readreg, re_miibus_readreg), 279 DEVMETHOD(miibus_writereg, re_miibus_writereg), 280 DEVMETHOD(miibus_statchg, re_miibus_statchg), 281 282 { 0, 0 } 283}; 284 285static driver_t re_driver = { 286 "re", 287 re_methods, 288 sizeof(struct rl_softc) 289}; 290 291static devclass_t re_devclass; 292 293DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 294DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 295DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 296 297#define EE_SET(x) \ 298 CSR_WRITE_1(sc, RL_EECMD, \ 299 CSR_READ_1(sc, RL_EECMD) | x) 300 301#define EE_CLR(x) \ 302 CSR_WRITE_1(sc, RL_EECMD, \ 303 CSR_READ_1(sc, RL_EECMD) & ~x) 304 305/* 306 * Send a read command and address to the EEPROM, check for ACK. 307 */ 308static void 309re_eeprom_putbyte(sc, addr) 310 struct rl_softc *sc; 311 int addr; 312{ 313 register int d, i; 314 315 d = addr | sc->rl_eecmd_read; 316 317 /* 318 * Feed in each bit and strobe the clock. 319 */ 320 for (i = 0x400; i; i >>= 1) { 321 if (d & i) { 322 EE_SET(RL_EE_DATAIN); 323 } else { 324 EE_CLR(RL_EE_DATAIN); 325 } 326 DELAY(100); 327 EE_SET(RL_EE_CLK); 328 DELAY(150); 329 EE_CLR(RL_EE_CLK); 330 DELAY(100); 331 } 332} 333 334/* 335 * Read a word of data stored in the EEPROM at address 'addr.' 336 */ 337static void 338re_eeprom_getword(sc, addr, dest) 339 struct rl_softc *sc; 340 int addr; 341 u_int16_t *dest; 342{ 343 register int i; 344 u_int16_t word = 0; 345 346 /* Enter EEPROM access mode. */ 347 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 348 349 /* 350 * Send address of word we want to read. 351 */ 352 re_eeprom_putbyte(sc, addr); 353 354 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 355 356 /* 357 * Start reading bits from EEPROM. 358 */ 359 for (i = 0x8000; i; i >>= 1) { 360 EE_SET(RL_EE_CLK); 361 DELAY(100); 362 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 363 word |= i; 364 EE_CLR(RL_EE_CLK); 365 DELAY(100); 366 } 367 368 /* Turn off EEPROM access mode. */ 369 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 370 371 *dest = word; 372} 373 374/* 375 * Read a sequence of words from the EEPROM. 376 */ 377static void 378re_read_eeprom(sc, dest, off, cnt, swap) 379 struct rl_softc *sc; 380 caddr_t dest; 381 int off; 382 int cnt; 383 int swap; 384{ 385 int i; 386 u_int16_t word = 0, *ptr; 387 388 for (i = 0; i < cnt; i++) { 389 re_eeprom_getword(sc, off + i, &word); 390 ptr = (u_int16_t *)(dest + (i * 2)); 391 if (swap) 392 *ptr = ntohs(word); 393 else 394 *ptr = word; 395 } 396} 397 398static int 399re_gmii_readreg(dev, phy, reg) 400 device_t dev; 401 int phy, reg; 402{ 403 struct rl_softc *sc; 404 u_int32_t rval; 405 int i; 406 407 if (phy != 1) 408 return (0); 409 410 sc = device_get_softc(dev); 411 412 /* Let the rgephy driver read the GMEDIASTAT register */ 413 414 if (reg == RL_GMEDIASTAT) { 415 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 416 return (rval); 417 } 418 419 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 420 DELAY(1000); 421 422 for (i = 0; i < RL_TIMEOUT; i++) { 423 rval = CSR_READ_4(sc, RL_PHYAR); 424 if (rval & RL_PHYAR_BUSY) 425 break; 426 DELAY(100); 427 } 428 429 if (i == RL_TIMEOUT) { 430 if_printf(sc->rl_ifp, "PHY read failed\n"); 431 return (0); 432 } 433 434 return (rval & RL_PHYAR_PHYDATA); 435} 436 437static int 438re_gmii_writereg(dev, phy, reg, data) 439 device_t dev; 440 int phy, reg, data; 441{ 442 struct rl_softc *sc; 443 u_int32_t rval; 444 int i; 445 446 sc = device_get_softc(dev); 447 448 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 449 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 450 DELAY(1000); 451 452 for (i = 0; i < RL_TIMEOUT; i++) { 453 rval = CSR_READ_4(sc, RL_PHYAR); 454 if (!(rval & RL_PHYAR_BUSY)) 455 break; 456 DELAY(100); 457 } 458 459 if (i == RL_TIMEOUT) { 460 if_printf(sc->rl_ifp, "PHY write failed\n"); 461 return (0); 462 } 463 464 return (0); 465} 466 467static int 468re_miibus_readreg(dev, phy, reg) 469 device_t dev; 470 int phy, reg; 471{ 472 struct rl_softc *sc; 473 u_int16_t rval = 0; 474 u_int16_t re8139_reg = 0; 475 476 sc = device_get_softc(dev); 477 478 if (sc->rl_type == RL_8169) { 479 rval = re_gmii_readreg(dev, phy, reg); 480 return (rval); 481 } 482 483 /* Pretend the internal PHY is only at address 0 */ 484 if (phy) { 485 return (0); 486 } 487 switch (reg) { 488 case MII_BMCR: 489 re8139_reg = RL_BMCR; 490 break; 491 case MII_BMSR: 492 re8139_reg = RL_BMSR; 493 break; 494 case MII_ANAR: 495 re8139_reg = RL_ANAR; 496 break; 497 case MII_ANER: 498 re8139_reg = RL_ANER; 499 break; 500 case MII_ANLPAR: 501 re8139_reg = RL_LPAR; 502 break; 503 case MII_PHYIDR1: 504 case MII_PHYIDR2: 505 return (0); 506 /* 507 * Allow the rlphy driver to read the media status 508 * register. If we have a link partner which does not 509 * support NWAY, this is the register which will tell 510 * us the results of parallel detection. 511 */ 512 case RL_MEDIASTAT: 513 rval = CSR_READ_1(sc, RL_MEDIASTAT); 514 return (rval); 515 default: 516 if_printf(sc->rl_ifp, "bad phy register\n"); 517 return (0); 518 } 519 rval = CSR_READ_2(sc, re8139_reg); 520 return (rval); 521} 522 523static int 524re_miibus_writereg(dev, phy, reg, data) 525 device_t dev; 526 int phy, reg, data; 527{ 528 struct rl_softc *sc; 529 u_int16_t re8139_reg = 0; 530 int rval = 0; 531 532 sc = device_get_softc(dev); 533 534 if (sc->rl_type == RL_8169) { 535 rval = re_gmii_writereg(dev, phy, reg, data); 536 return (rval); 537 } 538 539 /* Pretend the internal PHY is only at address 0 */ 540 if (phy) 541 return (0); 542 543 switch (reg) { 544 case MII_BMCR: 545 re8139_reg = RL_BMCR; 546 break; 547 case MII_BMSR: 548 re8139_reg = RL_BMSR; 549 break; 550 case MII_ANAR: 551 re8139_reg = RL_ANAR; 552 break; 553 case MII_ANER: 554 re8139_reg = RL_ANER; 555 break; 556 case MII_ANLPAR: 557 re8139_reg = RL_LPAR; 558 break; 559 case MII_PHYIDR1: 560 case MII_PHYIDR2: 561 return (0); 562 break; 563 default: 564 if_printf(sc->rl_ifp, "bad phy register\n"); 565 return (0); 566 } 567 CSR_WRITE_2(sc, re8139_reg, data); 568 return (0); 569} 570 571static void 572re_miibus_statchg(dev) 573 device_t dev; 574{ 575 576} 577 578/* 579 * Program the 64-bit multicast hash filter. 580 */ 581static void 582re_setmulti(sc) 583 struct rl_softc *sc; 584{ 585 struct ifnet *ifp; 586 int h = 0; 587 u_int32_t hashes[2] = { 0, 0 }; 588 struct ifmultiaddr *ifma; 589 u_int32_t rxfilt; 590 int mcnt = 0; 591 592 RL_LOCK_ASSERT(sc); 593 594 ifp = sc->rl_ifp; 595 596 rxfilt = CSR_READ_4(sc, RL_RXCFG); 597 598 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 599 rxfilt |= RL_RXCFG_RX_MULTI; 600 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 601 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 602 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 603 return; 604 } 605 606 /* first, zot all the existing hash bits */ 607 CSR_WRITE_4(sc, RL_MAR0, 0); 608 CSR_WRITE_4(sc, RL_MAR4, 0); 609 610 /* now program new ones */ 611 IF_ADDR_LOCK(ifp); 612 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 613 if (ifma->ifma_addr->sa_family != AF_LINK) 614 continue; 615 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 616 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 617 if (h < 32) 618 hashes[0] |= (1 << h); 619 else 620 hashes[1] |= (1 << (h - 32)); 621 mcnt++; 622 } 623 IF_ADDR_UNLOCK(ifp); 624 625 if (mcnt) 626 rxfilt |= RL_RXCFG_RX_MULTI; 627 else 628 rxfilt &= ~RL_RXCFG_RX_MULTI; 629 630 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 631 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 632 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 633} 634 635static void 636re_reset(sc) 637 struct rl_softc *sc; 638{ 639 register int i; 640 641 RL_LOCK_ASSERT(sc); 642 643 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 644 645 for (i = 0; i < RL_TIMEOUT; i++) { 646 DELAY(10); 647 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 648 break; 649 } 650 if (i == RL_TIMEOUT) 651 if_printf(sc->rl_ifp, "reset never completed!\n"); 652 653 CSR_WRITE_1(sc, 0x82, 1); 654} 655 656/* 657 * The following routine is designed to test for a defect on some 658 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 659 * lines connected to the bus, however for a 32-bit only card, they 660 * should be pulled high. The result of this defect is that the 661 * NIC will not work right if you plug it into a 64-bit slot: DMA 662 * operations will be done with 64-bit transfers, which will fail 663 * because the 64-bit data lines aren't connected. 664 * 665 * There's no way to work around this (short of talking a soldering 666 * iron to the board), however we can detect it. The method we use 667 * here is to put the NIC into digital loopback mode, set the receiver 668 * to promiscuous mode, and then try to send a frame. We then compare 669 * the frame data we sent to what was received. If the data matches, 670 * then the NIC is working correctly, otherwise we know the user has 671 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 672 * slot. In the latter case, there's no way the NIC can work correctly, 673 * so we print out a message on the console and abort the device attach. 674 */ 675 676static int 677re_diag(sc) 678 struct rl_softc *sc; 679{ 680 struct ifnet *ifp = sc->rl_ifp; 681 struct mbuf *m0; 682 struct ether_header *eh; 683 struct rl_desc *cur_rx; 684 u_int16_t status; 685 u_int32_t rxstat; 686 int total_len, i, error = 0; 687 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 688 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 689 690 /* Allocate a single mbuf */ 691 MGETHDR(m0, M_DONTWAIT, MT_DATA); 692 if (m0 == NULL) 693 return (ENOBUFS); 694 695 RL_LOCK(sc); 696 697 /* 698 * Initialize the NIC in test mode. This sets the chip up 699 * so that it can send and receive frames, but performs the 700 * following special functions: 701 * - Puts receiver in promiscuous mode 702 * - Enables digital loopback mode 703 * - Leaves interrupts turned off 704 */ 705 706 ifp->if_flags |= IFF_PROMISC; 707 sc->rl_testmode = 1; 708 re_init_locked(sc); 709 re_stop(sc); 710 DELAY(100000); 711 re_init_locked(sc); 712 713 /* Put some data in the mbuf */ 714 715 eh = mtod(m0, struct ether_header *); 716 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 717 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 718 eh->ether_type = htons(ETHERTYPE_IP); 719 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 720 721 /* 722 * Queue the packet, start transmission. 723 * Note: IF_HANDOFF() ultimately calls re_start() for us. 724 */ 725 726 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 727 RL_UNLOCK(sc); 728 /* XXX: re_diag must not be called when in ALTQ mode */ 729 IF_HANDOFF(&ifp->if_snd, m0, ifp); 730 RL_LOCK(sc); 731 m0 = NULL; 732 733 /* Wait for it to propagate through the chip */ 734 735 DELAY(100000); 736 for (i = 0; i < RL_TIMEOUT; i++) { 737 status = CSR_READ_2(sc, RL_ISR); 738 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 739 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 740 break; 741 DELAY(10); 742 } 743 744 if (i == RL_TIMEOUT) { 745 if_printf(ifp, "diagnostic failed, failed to receive packet " 746 "in loopback mode\n"); 747 error = EIO; 748 goto done; 749 } 750 751 /* 752 * The packet should have been dumped into the first 753 * entry in the RX DMA ring. Grab it from there. 754 */ 755 756 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 757 sc->rl_ldata.rl_rx_list_map, 758 BUS_DMASYNC_POSTREAD); 759 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 760 sc->rl_ldata.rl_rx_dmamap[0], 761 BUS_DMASYNC_POSTWRITE); 762 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 763 sc->rl_ldata.rl_rx_dmamap[0]); 764 765 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 766 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 767 eh = mtod(m0, struct ether_header *); 768 769 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 770 total_len = RL_RXBYTES(cur_rx); 771 rxstat = le32toh(cur_rx->rl_cmdstat); 772 773 if (total_len != ETHER_MIN_LEN) { 774 if_printf(ifp, "diagnostic failed, received short packet\n"); 775 error = EIO; 776 goto done; 777 } 778 779 /* Test that the received packet data matches what we sent. */ 780 781 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 782 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 783 ntohs(eh->ether_type) != ETHERTYPE_IP) { 784 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 785 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 786 dst, ":", src, ":", ETHERTYPE_IP); 787 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 788 eh->ether_dhost, ":", eh->ether_shost, ":", 789 ntohs(eh->ether_type)); 790 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 791 "into a 64-bit PCI slot.\n"); 792 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 793 "for proper operation.\n"); 794 if_printf(ifp, "Read the re(4) man page for more details.\n"); 795 error = EIO; 796 } 797 798done: 799 /* Turn interface off, release resources */ 800 801 sc->rl_testmode = 0; 802 ifp->if_flags &= ~IFF_PROMISC; 803 re_stop(sc); 804 if (m0 != NULL) 805 m_freem(m0); 806 807 RL_UNLOCK(sc); 808 809 return (error); 810} 811 812/* 813 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 814 * IDs against our list and return a device name if we find a match. 815 */ 816static int 817re_probe(dev) 818 device_t dev; 819{ 820 struct rl_type *t; 821 struct rl_softc *sc; 822 int rid; 823 u_int32_t hwrev; 824 825 t = re_devs; 826 sc = device_get_softc(dev); 827 828 while (t->rl_name != NULL) { 829 if ((pci_get_vendor(dev) == t->rl_vid) && 830 (pci_get_device(dev) == t->rl_did)) { 831 /* 832 * Only attach to rev. 3 of the Linksys EG1032 adapter. 833 * Rev. 2 i supported by sk(4). 834 */ 835 if ((t->rl_vid == LINKSYS_VENDORID) && 836 (t->rl_did == LINKSYS_DEVICEID_EG1032) && 837 (pci_get_subdevice(dev) != 838 LINKSYS_SUBDEVICE_EG1032_REV3)) { 839 t++; 840 continue; 841 } 842 843 /* 844 * Temporarily map the I/O space 845 * so we can read the chip ID register. 846 */ 847 rid = RL_RID; 848 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 849 RF_ACTIVE); 850 if (sc->rl_res == NULL) { 851 device_printf(dev, 852 "couldn't map ports/memory\n"); 853 return (ENXIO); 854 } 855 sc->rl_btag = rman_get_bustag(sc->rl_res); 856 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 857 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 858 bus_release_resource(dev, RL_RES, 859 RL_RID, sc->rl_res); 860 if (t->rl_basetype == hwrev) { 861 device_set_desc(dev, t->rl_name); 862 return (BUS_PROBE_DEFAULT); 863 } 864 } 865 t++; 866 } 867 868 return (ENXIO); 869} 870 871/* 872 * This routine takes the segment list provided as the result of 873 * a bus_dma_map_load() operation and assigns the addresses/lengths 874 * to RealTek DMA descriptors. This can be called either by the RX 875 * code or the TX code. In the RX case, we'll probably wind up mapping 876 * at most one segment. For the TX case, there could be any number of 877 * segments since TX packets may span multiple mbufs. In either case, 878 * if the number of segments is larger than the rl_maxsegs limit 879 * specified by the caller, we abort the mapping operation. Sadly, 880 * whoever designed the buffer mapping API did not provide a way to 881 * return an error from here, so we have to fake it a bit. 882 */ 883 884static void 885re_dma_map_desc(arg, segs, nseg, mapsize, error) 886 void *arg; 887 bus_dma_segment_t *segs; 888 int nseg; 889 bus_size_t mapsize; 890 int error; 891{ 892 struct rl_dmaload_arg *ctx; 893 struct rl_desc *d = NULL; 894 int i = 0, idx; 895 896 if (error) 897 return; 898 899 ctx = arg; 900 901 /* Signal error to caller if there's too many segments */ 902 if (nseg > ctx->rl_maxsegs) { 903 ctx->rl_maxsegs = 0; 904 return; 905 } 906 907 /* 908 * Map the segment array into descriptors. Note that we set the 909 * start-of-frame and end-of-frame markers for either TX or RX, but 910 * they really only have meaning in the TX case. (In the RX case, 911 * it's the chip that tells us where packets begin and end.) 912 * We also keep track of the end of the ring and set the 913 * end-of-ring bits as needed, and we set the ownership bits 914 * in all except the very first descriptor. (The caller will 915 * set this descriptor later when it start transmission or 916 * reception.) 917 */ 918 idx = ctx->rl_idx; 919 for (;;) { 920 u_int32_t cmdstat; 921 d = &ctx->rl_ring[idx]; 922 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 923 ctx->rl_maxsegs = 0; 924 return; 925 } 926 cmdstat = segs[i].ds_len; 927 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 928 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 929 if (i == 0) 930 cmdstat |= RL_TDESC_CMD_SOF; 931 else 932 cmdstat |= RL_TDESC_CMD_OWN; 933 if (idx == (RL_RX_DESC_CNT - 1)) 934 cmdstat |= RL_TDESC_CMD_EOR; 935 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 936 i++; 937 if (i == nseg) 938 break; 939 RL_DESC_INC(idx); 940 } 941 942 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 943 ctx->rl_maxsegs = nseg; 944 ctx->rl_idx = idx; 945} 946 947/* 948 * Map a single buffer address. 949 */ 950 951static void 952re_dma_map_addr(arg, segs, nseg, error) 953 void *arg; 954 bus_dma_segment_t *segs; 955 int nseg; 956 int error; 957{ 958 bus_addr_t *addr; 959 960 if (error) 961 return; 962 963 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 964 addr = arg; 965 *addr = segs->ds_addr; 966} 967 968static int 969re_allocmem(dev, sc) 970 device_t dev; 971 struct rl_softc *sc; 972{ 973 int error; 974 int nseg; 975 int i; 976 977 /* 978 * Allocate map for RX mbufs. 979 */ 980 nseg = 32; 981 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 982 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 983 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 984 NULL, NULL, &sc->rl_ldata.rl_mtag); 985 if (error) { 986 device_printf(dev, "could not allocate dma tag\n"); 987 return (ENOMEM); 988 } 989 990 /* 991 * Allocate map for TX descriptor list. 992 */ 993 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 994 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 995 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 996 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 997 if (error) { 998 device_printf(dev, "could not allocate dma tag\n"); 999 return (ENOMEM); 1000 } 1001 1002 /* Allocate DMA'able memory for the TX ring */ 1003 1004 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1005 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1006 &sc->rl_ldata.rl_tx_list_map); 1007 if (error) 1008 return (ENOMEM); 1009 1010 /* Load the map for the TX ring. */ 1011 1012 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1013 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1014 RL_TX_LIST_SZ, re_dma_map_addr, 1015 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1016 1017 /* Create DMA maps for TX buffers */ 1018 1019 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1020 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1021 &sc->rl_ldata.rl_tx_dmamap[i]); 1022 if (error) { 1023 device_printf(dev, "can't create DMA map for TX\n"); 1024 return (ENOMEM); 1025 } 1026 } 1027 1028 /* 1029 * Allocate map for RX descriptor list. 1030 */ 1031 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1032 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1033 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1034 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1035 if (error) { 1036 device_printf(dev, "could not allocate dma tag\n"); 1037 return (ENOMEM); 1038 } 1039 1040 /* Allocate DMA'able memory for the RX ring */ 1041 1042 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1043 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1044 &sc->rl_ldata.rl_rx_list_map); 1045 if (error) 1046 return (ENOMEM); 1047 1048 /* Load the map for the RX ring. */ 1049 1050 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1051 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1052 RL_RX_LIST_SZ, re_dma_map_addr, 1053 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1054 1055 /* Create DMA maps for RX buffers */ 1056 1057 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1058 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1059 &sc->rl_ldata.rl_rx_dmamap[i]); 1060 if (error) { 1061 device_printf(dev, "can't create DMA map for RX\n"); 1062 return (ENOMEM); 1063 } 1064 } 1065 1066 return (0); 1067} 1068 1069/* 1070 * Attach the interface. Allocate softc structures, do ifmedia 1071 * setup and ethernet/BPF attach. 1072 */ 1073static int 1074re_attach(dev) 1075 device_t dev; 1076{ 1077 u_char eaddr[ETHER_ADDR_LEN]; 1078 u_int16_t as[3]; 1079 struct rl_softc *sc; 1080 struct ifnet *ifp; 1081 struct rl_hwrev *hw_rev; 1082 int hwrev; 1083 u_int16_t re_did = 0; 1084 int error = 0, rid, i; 1085 1086 sc = device_get_softc(dev); 1087 1088 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1089 MTX_DEF); 1090 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1091 1092 /* 1093 * Map control/status registers. 1094 */ 1095 pci_enable_busmaster(dev); 1096 1097 rid = RL_RID; 1098 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1099 RF_ACTIVE); 1100 1101 if (sc->rl_res == NULL) { 1102 device_printf(dev, "couldn't map ports/memory\n"); 1103 error = ENXIO; 1104 goto fail; 1105 } 1106 1107 sc->rl_btag = rman_get_bustag(sc->rl_res); 1108 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1109 1110 /* Allocate interrupt */ 1111 rid = 0; 1112 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1113 RF_SHAREABLE | RF_ACTIVE); 1114 1115 if (sc->rl_irq == NULL) { 1116 device_printf(dev, "couldn't map interrupt\n"); 1117 error = ENXIO; 1118 goto fail; 1119 } 1120 1121 /* Reset the adapter. */ 1122 RL_LOCK(sc); 1123 re_reset(sc); 1124 RL_UNLOCK(sc); 1125 1126 hw_rev = re_hwrevs; 1127 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1128 while (hw_rev->rl_desc != NULL) { 1129 if (hw_rev->rl_rev == hwrev) { 1130 sc->rl_type = hw_rev->rl_type; 1131 break; 1132 } 1133 hw_rev++; 1134 } 1135 1136 if (sc->rl_type == RL_8169) { 1137 1138 /* Set RX length mask */ 1139 1140 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1141 1142 /* Force station address autoload from the EEPROM */ 1143 1144 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1145 for (i = 0; i < RL_TIMEOUT; i++) { 1146 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1147 break; 1148 DELAY(100); 1149 } 1150 if (i == RL_TIMEOUT) 1151 device_printf(dev, "eeprom autoload timed out\n"); 1152 1153 for (i = 0; i < ETHER_ADDR_LEN; i++) 1154 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1155 } else { 1156 1157 /* Set RX length mask */ 1158 1159 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1160 1161 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1162 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1163 if (re_did != 0x8129) 1164 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1165 1166 /* 1167 * Get station address from the EEPROM. 1168 */ 1169 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1170 for (i = 0; i < 3; i++) { 1171 eaddr[(i * 2) + 0] = as[i] & 0xff; 1172 eaddr[(i * 2) + 1] = as[i] >> 8; 1173 } 1174 } 1175 1176 /* 1177 * Allocate the parent bus DMA tag appropriate for PCI. 1178 */ 1179#define RL_NSEG_NEW 32 1180 error = bus_dma_tag_create(NULL, /* parent */ 1181 1, 0, /* alignment, boundary */ 1182 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1183 BUS_SPACE_MAXADDR, /* highaddr */ 1184 NULL, NULL, /* filter, filterarg */ 1185 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1186 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1187 BUS_DMA_ALLOCNOW, /* flags */ 1188 NULL, NULL, /* lockfunc, lockarg */ 1189 &sc->rl_parent_tag); 1190 if (error) 1191 goto fail; 1192 1193 error = re_allocmem(dev, sc); 1194 1195 if (error) 1196 goto fail; 1197 1198 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1199 if (ifp == NULL) { 1200 device_printf(dev, "can not if_alloc()\n"); 1201 error = ENOSPC; 1202 goto fail; 1203 } 1204 1205 /* Do MII setup */ 1206 if (mii_phy_probe(dev, &sc->rl_miibus, 1207 re_ifmedia_upd, re_ifmedia_sts)) { 1208 device_printf(dev, "MII without any phy!\n"); 1209 error = ENXIO; 1210 goto fail; 1211 } 1212 1213 ifp->if_softc = sc; 1214 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1215 ifp->if_mtu = ETHERMTU; 1216 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1217 ifp->if_ioctl = re_ioctl; 1218 ifp->if_capabilities = IFCAP_VLAN_MTU; 1219 ifp->if_start = re_start; 1220 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0; 1221 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1222 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1223#ifdef DEVICE_POLLING 1224 ifp->if_capabilities |= IFCAP_POLLING; 1225#endif 1226 ifp->if_watchdog = re_watchdog; 1227 ifp->if_init = re_init; 1228 if (sc->rl_type == RL_8169) 1229 ifp->if_baudrate = 1000000000; 1230 else 1231 ifp->if_baudrate = 100000000; 1232 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1233 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1234 IFQ_SET_READY(&ifp->if_snd); 1235 1236 /* 1237 * Call MI attach routine. 1238 */ 1239 ether_ifattach(ifp, eaddr); 1240 1241 /* Perform hardware diagnostic. */ 1242 error = re_diag(sc); 1243 1244 if (error) { 1245 device_printf(dev, "attach aborted due to hardware diag failure\n"); 1246 ether_ifdetach(ifp); 1247 goto fail; 1248 } 1249 1250 /* Hook interrupt last to avoid having to lock softc */ 1251 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1252 re_intr, sc, &sc->rl_intrhand); 1253 if (error) { 1254 device_printf(dev, "couldn't set up irq\n"); 1255 ether_ifdetach(ifp); 1256 } 1257 1258fail: 1259 if (error) 1260 re_detach(dev); 1261 1262 return (error); 1263} 1264 1265/* 1266 * Shutdown hardware and free up resources. This can be called any 1267 * time after the mutex has been initialized. It is called in both 1268 * the error case in attach and the normal detach case so it needs 1269 * to be careful about only freeing resources that have actually been 1270 * allocated. 1271 */ 1272static int 1273re_detach(dev) 1274 device_t dev; 1275{ 1276 struct rl_softc *sc; 1277 struct ifnet *ifp; 1278 int i; 1279 1280 sc = device_get_softc(dev); 1281 ifp = sc->rl_ifp; 1282 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1283 1284#ifdef DEVICE_POLLING 1285 if (ifp->if_capenable & IFCAP_POLLING) 1286 ether_poll_deregister(ifp); 1287#endif 1288 1289 /* These should only be active if attach succeeded */ 1290 if (device_is_attached(dev)) { 1291 RL_LOCK(sc); 1292#if 0 1293 sc->suspended = 1; 1294#endif 1295 re_stop(sc); 1296 RL_UNLOCK(sc); 1297 callout_drain(&sc->rl_stat_callout); 1298 /* 1299 * Force off the IFF_UP flag here, in case someone 1300 * still had a BPF descriptor attached to this 1301 * interface. If they do, ether_ifdetach() will cause 1302 * the BPF code to try and clear the promisc mode 1303 * flag, which will bubble down to re_ioctl(), 1304 * which will try to call re_init() again. This will 1305 * turn the NIC back on and restart the MII ticker, 1306 * which will panic the system when the kernel tries 1307 * to invoke the re_tick() function that isn't there 1308 * anymore. 1309 */ 1310 ifp->if_flags &= ~IFF_UP; 1311 ether_ifdetach(ifp); 1312 } 1313 if (sc->rl_miibus) 1314 device_delete_child(dev, sc->rl_miibus); 1315 bus_generic_detach(dev); 1316 1317 /* 1318 * The rest is resource deallocation, so we should already be 1319 * stopped here. 1320 */ 1321 1322 if (sc->rl_intrhand) 1323 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1324 if (ifp != NULL) 1325 if_free(ifp); 1326 if (sc->rl_irq) 1327 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1328 if (sc->rl_res) 1329 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1330 1331 1332 /* Unload and free the RX DMA ring memory and map */ 1333 1334 if (sc->rl_ldata.rl_rx_list_tag) { 1335 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1336 sc->rl_ldata.rl_rx_list_map); 1337 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1338 sc->rl_ldata.rl_rx_list, 1339 sc->rl_ldata.rl_rx_list_map); 1340 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1341 } 1342 1343 /* Unload and free the TX DMA ring memory and map */ 1344 1345 if (sc->rl_ldata.rl_tx_list_tag) { 1346 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1347 sc->rl_ldata.rl_tx_list_map); 1348 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1349 sc->rl_ldata.rl_tx_list, 1350 sc->rl_ldata.rl_tx_list_map); 1351 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1352 } 1353 1354 /* Destroy all the RX and TX buffer maps */ 1355 1356 if (sc->rl_ldata.rl_mtag) { 1357 for (i = 0; i < RL_TX_DESC_CNT; i++) 1358 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1359 sc->rl_ldata.rl_tx_dmamap[i]); 1360 for (i = 0; i < RL_RX_DESC_CNT; i++) 1361 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1362 sc->rl_ldata.rl_rx_dmamap[i]); 1363 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1364 } 1365 1366 /* Unload and free the stats buffer and map */ 1367 1368 if (sc->rl_ldata.rl_stag) { 1369 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1370 sc->rl_ldata.rl_rx_list_map); 1371 bus_dmamem_free(sc->rl_ldata.rl_stag, 1372 sc->rl_ldata.rl_stats, 1373 sc->rl_ldata.rl_smap); 1374 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1375 } 1376 1377 if (sc->rl_parent_tag) 1378 bus_dma_tag_destroy(sc->rl_parent_tag); 1379 1380 mtx_destroy(&sc->rl_mtx); 1381 1382 return (0); 1383} 1384 1385static int 1386re_newbuf(sc, idx, m) 1387 struct rl_softc *sc; 1388 int idx; 1389 struct mbuf *m; 1390{ 1391 struct rl_dmaload_arg arg; 1392 struct mbuf *n = NULL; 1393 int error; 1394 1395 if (m == NULL) { 1396 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1397 if (n == NULL) 1398 return (ENOBUFS); 1399 m = n; 1400 } else 1401 m->m_data = m->m_ext.ext_buf; 1402 1403 m->m_len = m->m_pkthdr.len = MCLBYTES; 1404#ifdef RE_FIXUP_RX 1405 /* 1406 * This is part of an evil trick to deal with non-x86 platforms. 1407 * The RealTek chip requires RX buffers to be aligned on 64-bit 1408 * boundaries, but that will hose non-x86 machines. To get around 1409 * this, we leave some empty space at the start of each buffer 1410 * and for non-x86 hosts, we copy the buffer back six bytes 1411 * to achieve word alignment. This is slightly more efficient 1412 * than allocating a new buffer, copying the contents, and 1413 * discarding the old buffer. 1414 */ 1415 m_adj(m, RE_ETHER_ALIGN); 1416#endif 1417 arg.sc = sc; 1418 arg.rl_idx = idx; 1419 arg.rl_maxsegs = 1; 1420 arg.rl_flags = 0; 1421 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1422 1423 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1424 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1425 &arg, BUS_DMA_NOWAIT); 1426 if (error || arg.rl_maxsegs != 1) { 1427 if (n != NULL) 1428 m_freem(n); 1429 return (ENOMEM); 1430 } 1431 1432 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1433 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1434 1435 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1436 sc->rl_ldata.rl_rx_dmamap[idx], 1437 BUS_DMASYNC_PREREAD); 1438 1439 return (0); 1440} 1441 1442#ifdef RE_FIXUP_RX 1443static __inline void 1444re_fixup_rx(m) 1445 struct mbuf *m; 1446{ 1447 int i; 1448 uint16_t *src, *dst; 1449 1450 src = mtod(m, uint16_t *); 1451 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1452 1453 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1454 *dst++ = *src++; 1455 1456 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1457 1458 return; 1459} 1460#endif 1461 1462static int 1463re_tx_list_init(sc) 1464 struct rl_softc *sc; 1465{ 1466 1467 RL_LOCK_ASSERT(sc); 1468 1469 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1470 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1471 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1472 1473 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1474 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1475 sc->rl_ldata.rl_tx_prodidx = 0; 1476 sc->rl_ldata.rl_tx_considx = 0; 1477 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1478 1479 return (0); 1480} 1481 1482static int 1483re_rx_list_init(sc) 1484 struct rl_softc *sc; 1485{ 1486 int i; 1487 1488 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1489 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1490 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1491 1492 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1493 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1494 return (ENOBUFS); 1495 } 1496 1497 /* Flush the RX descriptors */ 1498 1499 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1500 sc->rl_ldata.rl_rx_list_map, 1501 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1502 1503 sc->rl_ldata.rl_rx_prodidx = 0; 1504 sc->rl_head = sc->rl_tail = NULL; 1505 1506 return (0); 1507} 1508 1509/* 1510 * RX handler for C+ and 8169. For the gigE chips, we support 1511 * the reception of jumbo frames that have been fragmented 1512 * across multiple 2K mbuf cluster buffers. 1513 */ 1514static void 1515re_rxeof(sc) 1516 struct rl_softc *sc; 1517{ 1518 struct mbuf *m; 1519 struct ifnet *ifp; 1520 int i, total_len; 1521 struct rl_desc *cur_rx; 1522 u_int32_t rxstat, rxvlan; 1523 1524 RL_LOCK_ASSERT(sc); 1525 1526 ifp = sc->rl_ifp; 1527 i = sc->rl_ldata.rl_rx_prodidx; 1528 1529 /* Invalidate the descriptor memory */ 1530 1531 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1532 sc->rl_ldata.rl_rx_list_map, 1533 BUS_DMASYNC_POSTREAD); 1534 1535 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1536 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1537 m = sc->rl_ldata.rl_rx_mbuf[i]; 1538 total_len = RL_RXBYTES(cur_rx); 1539 rxstat = le32toh(cur_rx->rl_cmdstat); 1540 rxvlan = le32toh(cur_rx->rl_vlanctl); 1541 1542 /* Invalidate the RX mbuf and unload its map */ 1543 1544 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1545 sc->rl_ldata.rl_rx_dmamap[i], 1546 BUS_DMASYNC_POSTWRITE); 1547 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1548 sc->rl_ldata.rl_rx_dmamap[i]); 1549 1550 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1551 m->m_len = RE_RX_DESC_BUFLEN; 1552 if (sc->rl_head == NULL) 1553 sc->rl_head = sc->rl_tail = m; 1554 else { 1555 m->m_flags &= ~M_PKTHDR; 1556 sc->rl_tail->m_next = m; 1557 sc->rl_tail = m; 1558 } 1559 re_newbuf(sc, i, NULL); 1560 RL_DESC_INC(i); 1561 continue; 1562 } 1563 1564 /* 1565 * NOTE: for the 8139C+, the frame length field 1566 * is always 12 bits in size, but for the gigE chips, 1567 * it is 13 bits (since the max RX frame length is 16K). 1568 * Unfortunately, all 32 bits in the status word 1569 * were already used, so to make room for the extra 1570 * length bit, RealTek took out the 'frame alignment 1571 * error' bit and shifted the other status bits 1572 * over one slot. The OWN, EOR, FS and LS bits are 1573 * still in the same places. We have already extracted 1574 * the frame length and checked the OWN bit, so rather 1575 * than using an alternate bit mapping, we shift the 1576 * status bits one space to the right so we can evaluate 1577 * them using the 8169 status as though it was in the 1578 * same format as that of the 8139C+. 1579 */ 1580 if (sc->rl_type == RL_8169) 1581 rxstat >>= 1; 1582 1583 /* 1584 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1585 * set, but if CRC is clear, it will still be a valid frame. 1586 */ 1587 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1588 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1589 ifp->if_ierrors++; 1590 /* 1591 * If this is part of a multi-fragment packet, 1592 * discard all the pieces. 1593 */ 1594 if (sc->rl_head != NULL) { 1595 m_freem(sc->rl_head); 1596 sc->rl_head = sc->rl_tail = NULL; 1597 } 1598 re_newbuf(sc, i, m); 1599 RL_DESC_INC(i); 1600 continue; 1601 } 1602 1603 /* 1604 * If allocating a replacement mbuf fails, 1605 * reload the current one. 1606 */ 1607 1608 if (re_newbuf(sc, i, NULL)) { 1609 ifp->if_ierrors++; 1610 if (sc->rl_head != NULL) { 1611 m_freem(sc->rl_head); 1612 sc->rl_head = sc->rl_tail = NULL; 1613 } 1614 re_newbuf(sc, i, m); 1615 RL_DESC_INC(i); 1616 continue; 1617 } 1618 1619 RL_DESC_INC(i); 1620 1621 if (sc->rl_head != NULL) { 1622 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1623 if (m->m_len == 0) 1624 m->m_len = RE_RX_DESC_BUFLEN; 1625 /* 1626 * Special case: if there's 4 bytes or less 1627 * in this buffer, the mbuf can be discarded: 1628 * the last 4 bytes is the CRC, which we don't 1629 * care about anyway. 1630 */ 1631 if (m->m_len <= ETHER_CRC_LEN) { 1632 sc->rl_tail->m_len -= 1633 (ETHER_CRC_LEN - m->m_len); 1634 m_freem(m); 1635 } else { 1636 m->m_len -= ETHER_CRC_LEN; 1637 m->m_flags &= ~M_PKTHDR; 1638 sc->rl_tail->m_next = m; 1639 } 1640 m = sc->rl_head; 1641 sc->rl_head = sc->rl_tail = NULL; 1642 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1643 } else 1644 m->m_pkthdr.len = m->m_len = 1645 (total_len - ETHER_CRC_LEN); 1646 1647#ifdef RE_FIXUP_RX 1648 re_fixup_rx(m); 1649#endif 1650 ifp->if_ipackets++; 1651 m->m_pkthdr.rcvif = ifp; 1652 1653 /* Do RX checksumming if enabled */ 1654 1655 if (ifp->if_capenable & IFCAP_RXCSUM) { 1656 1657 /* Check IP header checksum */ 1658 if (rxstat & RL_RDESC_STAT_PROTOID) 1659 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1660 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1661 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1662 1663 /* Check TCP/UDP checksum */ 1664 if ((RL_TCPPKT(rxstat) && 1665 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1666 (RL_UDPPKT(rxstat) && 1667 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1668 m->m_pkthdr.csum_flags |= 1669 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1670 m->m_pkthdr.csum_data = 0xffff; 1671 } 1672 } 1673 1674 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1675 VLAN_INPUT_TAG(ifp, m, 1676 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA))); 1677 if (m == NULL) 1678 continue; 1679 } 1680 RL_UNLOCK(sc); 1681 (*ifp->if_input)(ifp, m); 1682 RL_LOCK(sc); 1683 } 1684 1685 /* Flush the RX DMA ring */ 1686 1687 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1688 sc->rl_ldata.rl_rx_list_map, 1689 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1690 1691 sc->rl_ldata.rl_rx_prodidx = i; 1692} 1693 1694static void 1695re_txeof(sc) 1696 struct rl_softc *sc; 1697{ 1698 struct ifnet *ifp; 1699 u_int32_t txstat; 1700 int idx; 1701 1702 ifp = sc->rl_ifp; 1703 idx = sc->rl_ldata.rl_tx_considx; 1704 1705 /* Invalidate the TX descriptor list */ 1706 1707 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1708 sc->rl_ldata.rl_tx_list_map, 1709 BUS_DMASYNC_POSTREAD); 1710 1711 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1712 1713 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1714 if (txstat & RL_TDESC_CMD_OWN) 1715 break; 1716 1717 /* 1718 * We only stash mbufs in the last descriptor 1719 * in a fragment chain, which also happens to 1720 * be the only place where the TX status bits 1721 * are valid. 1722 */ 1723 1724 if (txstat & RL_TDESC_CMD_EOF) { 1725 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1726 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1727 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1728 sc->rl_ldata.rl_tx_dmamap[idx]); 1729 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1730 RL_TDESC_STAT_COLCNT)) 1731 ifp->if_collisions++; 1732 if (txstat & RL_TDESC_STAT_TXERRSUM) 1733 ifp->if_oerrors++; 1734 else 1735 ifp->if_opackets++; 1736 } 1737 sc->rl_ldata.rl_tx_free++; 1738 RL_DESC_INC(idx); 1739 } 1740 1741 /* No changes made to the TX ring, so no flush needed */ 1742 1743 if (idx != sc->rl_ldata.rl_tx_considx) { 1744 sc->rl_ldata.rl_tx_considx = idx; 1745 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1746 ifp->if_timer = 0; 1747 } 1748 1749 /* 1750 * If not all descriptors have been released reaped yet, 1751 * reload the timer so that we will eventually get another 1752 * interrupt that will cause us to re-enter this routine. 1753 * This is done in case the transmitter has gone idle. 1754 */ 1755 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1756 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1757} 1758 1759static void 1760re_tick(xsc) 1761 void *xsc; 1762{ 1763 struct rl_softc *sc; 1764 struct mii_data *mii; 1765 1766 sc = xsc; 1767 1768 RL_LOCK_ASSERT(sc); 1769 1770 mii = device_get_softc(sc->rl_miibus); 1771 1772 mii_tick(mii); 1773 1774 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1775} 1776 1777#ifdef DEVICE_POLLING 1778static void 1779re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1780{ 1781 struct rl_softc *sc = ifp->if_softc; 1782 1783 RL_LOCK(sc); 1784 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1785 re_poll_locked(ifp, cmd, count); 1786 RL_UNLOCK(sc); 1787} 1788 1789static void 1790re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1791{ 1792 struct rl_softc *sc = ifp->if_softc; 1793 1794 RL_LOCK_ASSERT(sc); 1795 1796 sc->rxcycles = count; 1797 re_rxeof(sc); 1798 re_txeof(sc); 1799 1800 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1801 re_start_locked(ifp); 1802 1803 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1804 u_int16_t status; 1805 1806 status = CSR_READ_2(sc, RL_ISR); 1807 if (status == 0xffff) 1808 return; 1809 if (status) 1810 CSR_WRITE_2(sc, RL_ISR, status); 1811 1812 /* 1813 * XXX check behaviour on receiver stalls. 1814 */ 1815 1816 if (status & RL_ISR_SYSTEM_ERR) { 1817 re_reset(sc); 1818 re_init_locked(sc); 1819 } 1820 } 1821} 1822#endif /* DEVICE_POLLING */ 1823 1824static void 1825re_intr(arg) 1826 void *arg; 1827{ 1828 struct rl_softc *sc; 1829 struct ifnet *ifp; 1830 u_int16_t status; 1831 1832 sc = arg; 1833 1834 RL_LOCK(sc); 1835 1836 ifp = sc->rl_ifp; 1837 1838 if (sc->suspended || !(ifp->if_flags & IFF_UP)) 1839 goto done_locked; 1840 1841#ifdef DEVICE_POLLING 1842 if (ifp->if_capenable & IFCAP_POLLING) 1843 goto done_locked; 1844#endif 1845 1846 for (;;) { 1847 1848 status = CSR_READ_2(sc, RL_ISR); 1849 /* If the card has gone away the read returns 0xffff. */ 1850 if (status == 0xffff) 1851 break; 1852 if (status) 1853 CSR_WRITE_2(sc, RL_ISR, status); 1854 1855 if ((status & RL_INTRS_CPLUS) == 0) 1856 break; 1857 1858 if (((status & RL_ISR_RX_OK) || 1859 (status & RL_ISR_RX_ERR)) && 1860 ifp->if_drv_flags & IFF_DRV_RUNNING) 1861 re_rxeof(sc); 1862 1863 if (((status & RL_ISR_TIMEOUT_EXPIRED) || 1864 (status & RL_ISR_TX_ERR) || 1865 (status & RL_ISR_TX_DESC_UNAVAIL)) && 1866 ifp->if_drv_flags & IFF_DRV_RUNNING) 1867 re_txeof(sc); 1868 1869 if (status & RL_ISR_SYSTEM_ERR) { 1870 re_reset(sc); 1871 re_init_locked(sc); 1872 } 1873 1874 if (status & RL_ISR_LINKCHG) { 1875 callout_stop(&sc->rl_stat_callout); 1876 re_tick(sc); 1877 } 1878 } 1879 1880 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1881 re_start_locked(ifp); 1882 1883done_locked: 1884 RL_UNLOCK(sc); 1885} 1886 1887static int 1888re_encap(sc, m_head, idx) 1889 struct rl_softc *sc; 1890 struct mbuf **m_head; 1891 int *idx; 1892{ 1893 struct mbuf *m_new = NULL; 1894 struct rl_dmaload_arg arg; 1895 bus_dmamap_t map; 1896 int error; 1897 struct m_tag *mtag; 1898 1899 RL_LOCK_ASSERT(sc); 1900 1901 if (sc->rl_ldata.rl_tx_free <= 4) 1902 return (EFBIG); 1903 1904 /* 1905 * Set up checksum offload. Note: checksum offload bits must 1906 * appear in all descriptors of a multi-descriptor transmit 1907 * attempt. This is according to testing done with an 8169 1908 * chip. This is a requirement. 1909 */ 1910 1911 arg.rl_flags = 0; 1912 1913 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1914 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1915 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1916 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1917 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1918 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1919 1920 arg.sc = sc; 1921 arg.rl_idx = *idx; 1922 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1923 if (arg.rl_maxsegs > 4) 1924 arg.rl_maxsegs -= 4; 1925 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1926 1927 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1928 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1929 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1930 1931 if (error && error != EFBIG) { 1932 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", error); 1933 return (ENOBUFS); 1934 } 1935 1936 /* Too many segments to map, coalesce into a single mbuf */ 1937 1938 if (error || arg.rl_maxsegs == 0) { 1939 m_new = m_defrag(*m_head, M_DONTWAIT); 1940 if (m_new == NULL) 1941 return (ENOBUFS); 1942 else 1943 *m_head = m_new; 1944 1945 arg.sc = sc; 1946 arg.rl_idx = *idx; 1947 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1948 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1949 1950 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1951 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1952 if (error) { 1953 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", 1954 error); 1955 return (EFBIG); 1956 } 1957 } 1958 1959 /* 1960 * Insure that the map for this transmission 1961 * is placed at the array index of the last descriptor 1962 * in this chain. (Swap last and first dmamaps.) 1963 */ 1964 sc->rl_ldata.rl_tx_dmamap[*idx] = 1965 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1966 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1967 1968 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 1969 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1970 1971 /* 1972 * Set up hardware VLAN tagging. Note: vlan tag info must 1973 * appear in the first descriptor of a multi-descriptor 1974 * transmission attempt. 1975 */ 1976 1977 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head); 1978 if (mtag != NULL) 1979 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1980 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1981 1982 /* Transfer ownership of packet to the chip. */ 1983 1984 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1985 htole32(RL_TDESC_CMD_OWN); 1986 if (*idx != arg.rl_idx) 1987 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1988 htole32(RL_TDESC_CMD_OWN); 1989 1990 RL_DESC_INC(arg.rl_idx); 1991 *idx = arg.rl_idx; 1992 1993 return (0); 1994} 1995 1996static void 1997re_start(ifp) 1998 struct ifnet *ifp; 1999{ 2000 struct rl_softc *sc; 2001 2002 sc = ifp->if_softc; 2003 RL_LOCK(sc); 2004 re_start_locked(ifp); 2005 RL_UNLOCK(sc); 2006} 2007 2008/* 2009 * Main transmit routine for C+ and gigE NICs. 2010 */ 2011static void 2012re_start_locked(ifp) 2013 struct ifnet *ifp; 2014{ 2015 struct rl_softc *sc; 2016 struct mbuf *m_head = NULL; 2017 int idx, queued = 0; 2018 2019 sc = ifp->if_softc; 2020 2021 RL_LOCK_ASSERT(sc); 2022 2023 idx = sc->rl_ldata.rl_tx_prodidx; 2024 2025 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2026 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2027 if (m_head == NULL) 2028 break; 2029 2030 if (re_encap(sc, &m_head, &idx)) { 2031 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2032 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2033 break; 2034 } 2035 2036 /* 2037 * If there's a BPF listener, bounce a copy of this frame 2038 * to him. 2039 */ 2040 BPF_MTAP(ifp, m_head); 2041 2042 queued++; 2043 } 2044 2045 if (queued == 0) 2046 return; 2047 2048 /* Flush the TX descriptors */ 2049 2050 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2051 sc->rl_ldata.rl_tx_list_map, 2052 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2053 2054 sc->rl_ldata.rl_tx_prodidx = idx; 2055 2056 /* 2057 * RealTek put the TX poll request register in a different 2058 * location on the 8169 gigE chip. I don't know why. 2059 */ 2060 2061 if (sc->rl_type == RL_8169) 2062 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2063 else 2064 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2065 2066 /* 2067 * Use the countdown timer for interrupt moderation. 2068 * 'TX done' interrupts are disabled. Instead, we reset the 2069 * countdown timer, which will begin counting until it hits 2070 * the value in the TIMERINT register, and then trigger an 2071 * interrupt. Each time we write to the TIMERCNT register, 2072 * the timer count is reset to 0. 2073 */ 2074 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2075 2076 /* 2077 * Set a timeout in case the chip goes out to lunch. 2078 */ 2079 ifp->if_timer = 5; 2080} 2081 2082static void 2083re_init(xsc) 2084 void *xsc; 2085{ 2086 struct rl_softc *sc = xsc; 2087 2088 RL_LOCK(sc); 2089 re_init_locked(sc); 2090 RL_UNLOCK(sc); 2091} 2092 2093static void 2094re_init_locked(sc) 2095 struct rl_softc *sc; 2096{ 2097 struct ifnet *ifp = sc->rl_ifp; 2098 struct mii_data *mii; 2099 u_int32_t rxcfg = 0; 2100 2101 RL_LOCK_ASSERT(sc); 2102 2103 mii = device_get_softc(sc->rl_miibus); 2104 2105 /* 2106 * Cancel pending I/O and free all RX/TX buffers. 2107 */ 2108 re_stop(sc); 2109 2110 /* 2111 * Enable C+ RX and TX mode, as well as VLAN stripping and 2112 * RX checksum offload. We must configure the C+ register 2113 * before all others. 2114 */ 2115 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2116 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2117 RL_CPLUSCMD_VLANSTRIP| 2118 (ifp->if_capenable & IFCAP_RXCSUM ? 2119 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2120 2121 /* 2122 * Init our MAC address. Even though the chipset 2123 * documentation doesn't mention it, we need to enter "Config 2124 * register write enable" mode to modify the ID registers. 2125 */ 2126 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2127 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2128 *(u_int32_t *)(&IF_LLADDR(sc->rl_ifp)[0])); 2129 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2130 *(u_int32_t *)(&IF_LLADDR(sc->rl_ifp)[4])); 2131 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2132 2133 /* 2134 * For C+ mode, initialize the RX descriptors and mbufs. 2135 */ 2136 re_rx_list_init(sc); 2137 re_tx_list_init(sc); 2138 2139 /* 2140 * Enable transmit and receive. 2141 */ 2142 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2143 2144 /* 2145 * Set the initial TX and RX configuration. 2146 */ 2147 if (sc->rl_testmode) { 2148 if (sc->rl_type == RL_8169) 2149 CSR_WRITE_4(sc, RL_TXCFG, 2150 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2151 else 2152 CSR_WRITE_4(sc, RL_TXCFG, 2153 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2154 } else 2155 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2156 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2157 2158 /* Set the individual bit to receive frames for this host only. */ 2159 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2160 rxcfg |= RL_RXCFG_RX_INDIV; 2161 2162 /* If we want promiscuous mode, set the allframes bit. */ 2163 if (ifp->if_flags & IFF_PROMISC) 2164 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2165 else 2166 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2167 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2168 2169 /* 2170 * Set capture broadcast bit to capture broadcast frames. 2171 */ 2172 if (ifp->if_flags & IFF_BROADCAST) 2173 rxcfg |= RL_RXCFG_RX_BROAD; 2174 else 2175 rxcfg &= ~RL_RXCFG_RX_BROAD; 2176 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2177 2178 /* 2179 * Program the multicast filter, if necessary. 2180 */ 2181 re_setmulti(sc); 2182 2183#ifdef DEVICE_POLLING 2184 /* 2185 * Disable interrupts if we are polling. 2186 */ 2187 if (ifp->if_capenable & IFCAP_POLLING) 2188 CSR_WRITE_2(sc, RL_IMR, 0); 2189 else /* otherwise ... */ 2190#endif 2191 /* 2192 * Enable interrupts. 2193 */ 2194 if (sc->rl_testmode) 2195 CSR_WRITE_2(sc, RL_IMR, 0); 2196 else 2197 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2198 2199 /* Set initial TX threshold */ 2200 sc->rl_txthresh = RL_TX_THRESH_INIT; 2201 2202 /* Start RX/TX process. */ 2203 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2204#ifdef notdef 2205 /* Enable receiver and transmitter. */ 2206 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2207#endif 2208 /* 2209 * Load the addresses of the RX and TX lists into the chip. 2210 */ 2211 2212 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2213 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2214 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2215 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2216 2217 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2218 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2219 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2220 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2221 2222 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2223 2224 /* 2225 * Initialize the timer interrupt register so that 2226 * a timer interrupt will be generated once the timer 2227 * reaches a certain number of ticks. The timer is 2228 * reloaded on each transmit. This gives us TX interrupt 2229 * moderation, which dramatically improves TX frame rate. 2230 */ 2231 if (sc->rl_type == RL_8169) 2232 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2233 else 2234 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2235 2236 /* 2237 * For 8169 gigE NICs, set the max allowed RX packet 2238 * size so we can receive jumbo frames. 2239 */ 2240 if (sc->rl_type == RL_8169) 2241 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2242 2243 if (sc->rl_testmode) 2244 return; 2245 2246 mii_mediachg(mii); 2247 2248 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2249 2250 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2251 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2252 2253 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2254} 2255 2256/* 2257 * Set media options. 2258 */ 2259static int 2260re_ifmedia_upd(ifp) 2261 struct ifnet *ifp; 2262{ 2263 struct rl_softc *sc; 2264 struct mii_data *mii; 2265 2266 sc = ifp->if_softc; 2267 mii = device_get_softc(sc->rl_miibus); 2268 RL_LOCK(sc); 2269 mii_mediachg(mii); 2270 RL_UNLOCK(sc); 2271 2272 return (0); 2273} 2274 2275/* 2276 * Report current media status. 2277 */ 2278static void 2279re_ifmedia_sts(ifp, ifmr) 2280 struct ifnet *ifp; 2281 struct ifmediareq *ifmr; 2282{ 2283 struct rl_softc *sc; 2284 struct mii_data *mii; 2285 2286 sc = ifp->if_softc; 2287 mii = device_get_softc(sc->rl_miibus); 2288 2289 RL_LOCK(sc); 2290 mii_pollstat(mii); 2291 RL_UNLOCK(sc); 2292 ifmr->ifm_active = mii->mii_media_active; 2293 ifmr->ifm_status = mii->mii_media_status; 2294} 2295 2296static int 2297re_ioctl(ifp, command, data) 2298 struct ifnet *ifp; 2299 u_long command; 2300 caddr_t data; 2301{ 2302 struct rl_softc *sc = ifp->if_softc; 2303 struct ifreq *ifr = (struct ifreq *) data; 2304 struct mii_data *mii; 2305 int error = 0; 2306 2307 switch (command) { 2308 case SIOCSIFMTU: 2309 RL_LOCK(sc); 2310 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2311 error = EINVAL; 2312 ifp->if_mtu = ifr->ifr_mtu; 2313 RL_UNLOCK(sc); 2314 break; 2315 case SIOCSIFFLAGS: 2316 RL_LOCK(sc); 2317 if (ifp->if_flags & IFF_UP) 2318 re_init_locked(sc); 2319 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2320 re_stop(sc); 2321 RL_UNLOCK(sc); 2322 break; 2323 case SIOCADDMULTI: 2324 case SIOCDELMULTI: 2325 RL_LOCK(sc); 2326 re_setmulti(sc); 2327 RL_UNLOCK(sc); 2328 break; 2329 case SIOCGIFMEDIA: 2330 case SIOCSIFMEDIA: 2331 mii = device_get_softc(sc->rl_miibus); 2332 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2333 break; 2334 case SIOCSIFCAP: 2335 { 2336 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2337#ifdef DEVICE_POLLING 2338 if (mask & IFCAP_POLLING) { 2339 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2340 error = ether_poll_register(re_poll, ifp); 2341 if (error) 2342 return(error); 2343 RL_LOCK(sc); 2344 /* Disable interrupts */ 2345 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2346 ifp->if_capenable |= IFCAP_POLLING; 2347 RL_UNLOCK(sc); 2348 2349 } else { 2350 error = ether_poll_deregister(ifp); 2351 /* Enable interrupts. */ 2352 RL_LOCK(sc); 2353 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2354 ifp->if_capenable &= ~IFCAP_POLLING; 2355 RL_UNLOCK(sc); 2356 } 2357 } 2358#endif /* DEVICE_POLLING */ 2359 if (mask & IFCAP_HWCSUM) { 2360 RL_LOCK(sc); 2361 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_HWCSUM; 2362 if (ifp->if_capenable & IFCAP_TXCSUM) 2363 ifp->if_hwassist = RE_CSUM_FEATURES; 2364 else 2365 ifp->if_hwassist = 0; 2366 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2367 re_init_locked(sc); 2368 RL_UNLOCK(sc); 2369 } 2370 } 2371 break; 2372 default: 2373 error = ether_ioctl(ifp, command, data); 2374 break; 2375 } 2376 2377 return (error); 2378} 2379 2380static void 2381re_watchdog(ifp) 2382 struct ifnet *ifp; 2383{ 2384 struct rl_softc *sc; 2385 2386 sc = ifp->if_softc; 2387 RL_LOCK(sc); 2388 if_printf(ifp, "watchdog timeout\n"); 2389 ifp->if_oerrors++; 2390 2391 re_txeof(sc); 2392 re_rxeof(sc); 2393 re_init_locked(sc); 2394 2395 RL_UNLOCK(sc); 2396} 2397 2398/* 2399 * Stop the adapter and free any mbufs allocated to the 2400 * RX and TX lists. 2401 */ 2402static void 2403re_stop(sc) 2404 struct rl_softc *sc; 2405{ 2406 register int i; 2407 struct ifnet *ifp; 2408 2409 RL_LOCK_ASSERT(sc); 2410 2411 ifp = sc->rl_ifp; 2412 ifp->if_timer = 0; 2413 2414 callout_stop(&sc->rl_stat_callout); 2415 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2416 2417 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2418 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2419 2420 if (sc->rl_head != NULL) { 2421 m_freem(sc->rl_head); 2422 sc->rl_head = sc->rl_tail = NULL; 2423 } 2424 2425 /* Free the TX list buffers. */ 2426 2427 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2428 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2429 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2430 sc->rl_ldata.rl_tx_dmamap[i]); 2431 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2432 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2433 } 2434 } 2435 2436 /* Free the RX list buffers. */ 2437 2438 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2439 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2440 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2441 sc->rl_ldata.rl_rx_dmamap[i]); 2442 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2443 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2444 } 2445 } 2446} 2447 2448/* 2449 * Device suspend routine. Stop the interface and save some PCI 2450 * settings in case the BIOS doesn't restore them properly on 2451 * resume. 2452 */ 2453static int 2454re_suspend(dev) 2455 device_t dev; 2456{ 2457 struct rl_softc *sc; 2458 2459 sc = device_get_softc(dev); 2460 2461 RL_LOCK(sc); 2462 re_stop(sc); 2463 sc->suspended = 1; 2464 RL_UNLOCK(sc); 2465 2466 return (0); 2467} 2468 2469/* 2470 * Device resume routine. Restore some PCI settings in case the BIOS 2471 * doesn't, re-enable busmastering, and restart the interface if 2472 * appropriate. 2473 */ 2474static int 2475re_resume(dev) 2476 device_t dev; 2477{ 2478 struct rl_softc *sc; 2479 struct ifnet *ifp; 2480 2481 sc = device_get_softc(dev); 2482 2483 RL_LOCK(sc); 2484 2485 ifp = sc->rl_ifp; 2486 2487 /* reinitialize interface if necessary */ 2488 if (ifp->if_flags & IFF_UP) 2489 re_init_locked(sc); 2490 2491 sc->suspended = 0; 2492 RL_UNLOCK(sc); 2493 2494 return (0); 2495} 2496 2497/* 2498 * Stop all chip I/O so that the kernel's probe routines don't 2499 * get confused by errant DMAs when rebooting. 2500 */ 2501static void 2502re_shutdown(dev) 2503 device_t dev; 2504{ 2505 struct rl_softc *sc; 2506 2507 sc = device_get_softc(dev); 2508 2509 RL_LOCK(sc); 2510 re_stop(sc); 2511 /* 2512 * Mark interface as down since otherwise we will panic if 2513 * interrupt comes in later on, which can happen in some 2514 * cases. 2515 */ 2516 sc->rl_ifp->if_flags &= ~IFF_UP; 2517 RL_UNLOCK(sc); 2518} 2519