if_re.c revision 150968
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 150968 2005-10-05 10:09:17Z glebius $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124 125#include <net/if.h> 126#include <net/if_arp.h> 127#include <net/ethernet.h> 128#include <net/if_dl.h> 129#include <net/if_media.h> 130#include <net/if_types.h> 131#include <net/if_vlan_var.h> 132 133#include <net/bpf.h> 134 135#include <machine/bus.h> 136#include <machine/resource.h> 137#include <sys/bus.h> 138#include <sys/rman.h> 139 140#include <dev/mii/mii.h> 141#include <dev/mii/miivar.h> 142 143#include <dev/pci/pcireg.h> 144#include <dev/pci/pcivar.h> 145 146MODULE_DEPEND(re, pci, 1, 1, 1); 147MODULE_DEPEND(re, ether, 1, 1, 1); 148MODULE_DEPEND(re, miibus, 1, 1, 1); 149 150/* "controller miibus0" required. See GENERIC if you get errors here. */ 151#include "miibus_if.h" 152 153/* 154 * Default to using PIO access for this driver. 155 */ 156#define RE_USEIOSPACE 157 158#include <pci/if_rlreg.h> 159 160#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 161 162/* 163 * Various supported device vendors/types and their names. 164 */ 165static struct rl_type re_devs[] = { 166 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 167 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 168 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 169 "RealTek 8139C+ 10/100BaseTX" }, 170 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 171 "RealTek 8169 Gigabit Ethernet" }, 172 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 173 "RealTek 8169S Single-chip Gigabit Ethernet" }, 174 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB, 175 "RealTek 8169SB Single-chip Gigabit Ethernet" }, 176 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 177 "RealTek 8110S Single-chip Gigabit Ethernet" }, 178 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 179 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 180 { 0, 0, 0, NULL } 181}; 182 183static struct rl_hwrev re_hwrevs[] = { 184 { RL_HWREV_8139, RL_8139, "" }, 185 { RL_HWREV_8139A, RL_8139, "A" }, 186 { RL_HWREV_8139AG, RL_8139, "A-G" }, 187 { RL_HWREV_8139B, RL_8139, "B" }, 188 { RL_HWREV_8130, RL_8139, "8130" }, 189 { RL_HWREV_8139C, RL_8139, "C" }, 190 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 191 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 192 { RL_HWREV_8169, RL_8169, "8169"}, 193 { RL_HWREV_8169S, RL_8169, "8169S"}, 194 { RL_HWREV_8169SB, RL_8169, "8169SB"}, 195 { RL_HWREV_8110S, RL_8169, "8110S"}, 196 { RL_HWREV_8100, RL_8139, "8100"}, 197 { RL_HWREV_8101, RL_8139, "8101"}, 198 { 0, 0, NULL } 199}; 200 201static int re_probe (device_t); 202static int re_attach (device_t); 203static int re_detach (device_t); 204 205static int re_encap (struct rl_softc *, struct mbuf **, int *); 206 207static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 208static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 209 bus_size_t, int); 210static int re_allocmem (device_t, struct rl_softc *); 211static int re_newbuf (struct rl_softc *, int, struct mbuf *); 212static int re_rx_list_init (struct rl_softc *); 213static int re_tx_list_init (struct rl_softc *); 214#ifdef RE_FIXUP_RX 215static __inline void re_fixup_rx 216 (struct mbuf *); 217#endif 218static void re_rxeof (struct rl_softc *); 219static void re_txeof (struct rl_softc *); 220#ifdef DEVICE_POLLING 221static void re_poll (struct ifnet *, enum poll_cmd, int); 222static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 223#endif 224static void re_intr (void *); 225static void re_tick (void *); 226static void re_start (struct ifnet *); 227static void re_start_locked (struct ifnet *); 228static int re_ioctl (struct ifnet *, u_long, caddr_t); 229static void re_init (void *); 230static void re_init_locked (struct rl_softc *); 231static void re_stop (struct rl_softc *); 232static void re_watchdog (struct ifnet *); 233static int re_suspend (device_t); 234static int re_resume (device_t); 235static void re_shutdown (device_t); 236static int re_ifmedia_upd (struct ifnet *); 237static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 238 239static void re_eeprom_putbyte (struct rl_softc *, int); 240static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 241static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 242static int re_gmii_readreg (device_t, int, int); 243static int re_gmii_writereg (device_t, int, int, int); 244 245static int re_miibus_readreg (device_t, int, int); 246static int re_miibus_writereg (device_t, int, int, int); 247static void re_miibus_statchg (device_t); 248 249static void re_setmulti (struct rl_softc *); 250static void re_reset (struct rl_softc *); 251 252static int re_diag (struct rl_softc *); 253 254#ifdef RE_USEIOSPACE 255#define RL_RES SYS_RES_IOPORT 256#define RL_RID RL_PCI_LOIO 257#else 258#define RL_RES SYS_RES_MEMORY 259#define RL_RID RL_PCI_LOMEM 260#endif 261 262static device_method_t re_methods[] = { 263 /* Device interface */ 264 DEVMETHOD(device_probe, re_probe), 265 DEVMETHOD(device_attach, re_attach), 266 DEVMETHOD(device_detach, re_detach), 267 DEVMETHOD(device_suspend, re_suspend), 268 DEVMETHOD(device_resume, re_resume), 269 DEVMETHOD(device_shutdown, re_shutdown), 270 271 /* bus interface */ 272 DEVMETHOD(bus_print_child, bus_generic_print_child), 273 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 274 275 /* MII interface */ 276 DEVMETHOD(miibus_readreg, re_miibus_readreg), 277 DEVMETHOD(miibus_writereg, re_miibus_writereg), 278 DEVMETHOD(miibus_statchg, re_miibus_statchg), 279 280 { 0, 0 } 281}; 282 283static driver_t re_driver = { 284 "re", 285 re_methods, 286 sizeof(struct rl_softc) 287}; 288 289static devclass_t re_devclass; 290 291DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 292DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 293DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 294 295#define EE_SET(x) \ 296 CSR_WRITE_1(sc, RL_EECMD, \ 297 CSR_READ_1(sc, RL_EECMD) | x) 298 299#define EE_CLR(x) \ 300 CSR_WRITE_1(sc, RL_EECMD, \ 301 CSR_READ_1(sc, RL_EECMD) & ~x) 302 303/* 304 * Send a read command and address to the EEPROM, check for ACK. 305 */ 306static void 307re_eeprom_putbyte(sc, addr) 308 struct rl_softc *sc; 309 int addr; 310{ 311 register int d, i; 312 313 d = addr | sc->rl_eecmd_read; 314 315 /* 316 * Feed in each bit and strobe the clock. 317 */ 318 for (i = 0x400; i; i >>= 1) { 319 if (d & i) { 320 EE_SET(RL_EE_DATAIN); 321 } else { 322 EE_CLR(RL_EE_DATAIN); 323 } 324 DELAY(100); 325 EE_SET(RL_EE_CLK); 326 DELAY(150); 327 EE_CLR(RL_EE_CLK); 328 DELAY(100); 329 } 330} 331 332/* 333 * Read a word of data stored in the EEPROM at address 'addr.' 334 */ 335static void 336re_eeprom_getword(sc, addr, dest) 337 struct rl_softc *sc; 338 int addr; 339 u_int16_t *dest; 340{ 341 register int i; 342 u_int16_t word = 0; 343 344 /* Enter EEPROM access mode. */ 345 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 346 347 /* 348 * Send address of word we want to read. 349 */ 350 re_eeprom_putbyte(sc, addr); 351 352 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 353 354 /* 355 * Start reading bits from EEPROM. 356 */ 357 for (i = 0x8000; i; i >>= 1) { 358 EE_SET(RL_EE_CLK); 359 DELAY(100); 360 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 361 word |= i; 362 EE_CLR(RL_EE_CLK); 363 DELAY(100); 364 } 365 366 /* Turn off EEPROM access mode. */ 367 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 368 369 *dest = word; 370} 371 372/* 373 * Read a sequence of words from the EEPROM. 374 */ 375static void 376re_read_eeprom(sc, dest, off, cnt, swap) 377 struct rl_softc *sc; 378 caddr_t dest; 379 int off; 380 int cnt; 381 int swap; 382{ 383 int i; 384 u_int16_t word = 0, *ptr; 385 386 for (i = 0; i < cnt; i++) { 387 re_eeprom_getword(sc, off + i, &word); 388 ptr = (u_int16_t *)(dest + (i * 2)); 389 if (swap) 390 *ptr = ntohs(word); 391 else 392 *ptr = word; 393 } 394} 395 396static int 397re_gmii_readreg(dev, phy, reg) 398 device_t dev; 399 int phy, reg; 400{ 401 struct rl_softc *sc; 402 u_int32_t rval; 403 int i; 404 405 if (phy != 1) 406 return (0); 407 408 sc = device_get_softc(dev); 409 410 /* Let the rgephy driver read the GMEDIASTAT register */ 411 412 if (reg == RL_GMEDIASTAT) { 413 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 414 return (rval); 415 } 416 417 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 418 DELAY(1000); 419 420 for (i = 0; i < RL_TIMEOUT; i++) { 421 rval = CSR_READ_4(sc, RL_PHYAR); 422 if (rval & RL_PHYAR_BUSY) 423 break; 424 DELAY(100); 425 } 426 427 if (i == RL_TIMEOUT) { 428 if_printf(sc->rl_ifp, "PHY read failed\n"); 429 return (0); 430 } 431 432 return (rval & RL_PHYAR_PHYDATA); 433} 434 435static int 436re_gmii_writereg(dev, phy, reg, data) 437 device_t dev; 438 int phy, reg, data; 439{ 440 struct rl_softc *sc; 441 u_int32_t rval; 442 int i; 443 444 sc = device_get_softc(dev); 445 446 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 447 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 448 DELAY(1000); 449 450 for (i = 0; i < RL_TIMEOUT; i++) { 451 rval = CSR_READ_4(sc, RL_PHYAR); 452 if (!(rval & RL_PHYAR_BUSY)) 453 break; 454 DELAY(100); 455 } 456 457 if (i == RL_TIMEOUT) { 458 if_printf(sc->rl_ifp, "PHY write failed\n"); 459 return (0); 460 } 461 462 return (0); 463} 464 465static int 466re_miibus_readreg(dev, phy, reg) 467 device_t dev; 468 int phy, reg; 469{ 470 struct rl_softc *sc; 471 u_int16_t rval = 0; 472 u_int16_t re8139_reg = 0; 473 474 sc = device_get_softc(dev); 475 476 if (sc->rl_type == RL_8169) { 477 rval = re_gmii_readreg(dev, phy, reg); 478 return (rval); 479 } 480 481 /* Pretend the internal PHY is only at address 0 */ 482 if (phy) { 483 return (0); 484 } 485 switch (reg) { 486 case MII_BMCR: 487 re8139_reg = RL_BMCR; 488 break; 489 case MII_BMSR: 490 re8139_reg = RL_BMSR; 491 break; 492 case MII_ANAR: 493 re8139_reg = RL_ANAR; 494 break; 495 case MII_ANER: 496 re8139_reg = RL_ANER; 497 break; 498 case MII_ANLPAR: 499 re8139_reg = RL_LPAR; 500 break; 501 case MII_PHYIDR1: 502 case MII_PHYIDR2: 503 return (0); 504 /* 505 * Allow the rlphy driver to read the media status 506 * register. If we have a link partner which does not 507 * support NWAY, this is the register which will tell 508 * us the results of parallel detection. 509 */ 510 case RL_MEDIASTAT: 511 rval = CSR_READ_1(sc, RL_MEDIASTAT); 512 return (rval); 513 default: 514 if_printf(sc->rl_ifp, "bad phy register\n"); 515 return (0); 516 } 517 rval = CSR_READ_2(sc, re8139_reg); 518 return (rval); 519} 520 521static int 522re_miibus_writereg(dev, phy, reg, data) 523 device_t dev; 524 int phy, reg, data; 525{ 526 struct rl_softc *sc; 527 u_int16_t re8139_reg = 0; 528 int rval = 0; 529 530 sc = device_get_softc(dev); 531 532 if (sc->rl_type == RL_8169) { 533 rval = re_gmii_writereg(dev, phy, reg, data); 534 return (rval); 535 } 536 537 /* Pretend the internal PHY is only at address 0 */ 538 if (phy) 539 return (0); 540 541 switch (reg) { 542 case MII_BMCR: 543 re8139_reg = RL_BMCR; 544 break; 545 case MII_BMSR: 546 re8139_reg = RL_BMSR; 547 break; 548 case MII_ANAR: 549 re8139_reg = RL_ANAR; 550 break; 551 case MII_ANER: 552 re8139_reg = RL_ANER; 553 break; 554 case MII_ANLPAR: 555 re8139_reg = RL_LPAR; 556 break; 557 case MII_PHYIDR1: 558 case MII_PHYIDR2: 559 return (0); 560 break; 561 default: 562 if_printf(sc->rl_ifp, "bad phy register\n"); 563 return (0); 564 } 565 CSR_WRITE_2(sc, re8139_reg, data); 566 return (0); 567} 568 569static void 570re_miibus_statchg(dev) 571 device_t dev; 572{ 573 574} 575 576/* 577 * Program the 64-bit multicast hash filter. 578 */ 579static void 580re_setmulti(sc) 581 struct rl_softc *sc; 582{ 583 struct ifnet *ifp; 584 int h = 0; 585 u_int32_t hashes[2] = { 0, 0 }; 586 struct ifmultiaddr *ifma; 587 u_int32_t rxfilt; 588 int mcnt = 0; 589 590 RL_LOCK_ASSERT(sc); 591 592 ifp = sc->rl_ifp; 593 594 rxfilt = CSR_READ_4(sc, RL_RXCFG); 595 596 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 597 rxfilt |= RL_RXCFG_RX_MULTI; 598 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 599 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 600 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 601 return; 602 } 603 604 /* first, zot all the existing hash bits */ 605 CSR_WRITE_4(sc, RL_MAR0, 0); 606 CSR_WRITE_4(sc, RL_MAR4, 0); 607 608 /* now program new ones */ 609 IF_ADDR_LOCK(ifp); 610 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 611 if (ifma->ifma_addr->sa_family != AF_LINK) 612 continue; 613 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 614 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 615 if (h < 32) 616 hashes[0] |= (1 << h); 617 else 618 hashes[1] |= (1 << (h - 32)); 619 mcnt++; 620 } 621 IF_ADDR_UNLOCK(ifp); 622 623 if (mcnt) 624 rxfilt |= RL_RXCFG_RX_MULTI; 625 else 626 rxfilt &= ~RL_RXCFG_RX_MULTI; 627 628 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 629 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 630 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 631} 632 633static void 634re_reset(sc) 635 struct rl_softc *sc; 636{ 637 register int i; 638 639 RL_LOCK_ASSERT(sc); 640 641 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 642 643 for (i = 0; i < RL_TIMEOUT; i++) { 644 DELAY(10); 645 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 646 break; 647 } 648 if (i == RL_TIMEOUT) 649 if_printf(sc->rl_ifp, "reset never completed!\n"); 650 651 CSR_WRITE_1(sc, 0x82, 1); 652} 653 654/* 655 * The following routine is designed to test for a defect on some 656 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 657 * lines connected to the bus, however for a 32-bit only card, they 658 * should be pulled high. The result of this defect is that the 659 * NIC will not work right if you plug it into a 64-bit slot: DMA 660 * operations will be done with 64-bit transfers, which will fail 661 * because the 64-bit data lines aren't connected. 662 * 663 * There's no way to work around this (short of talking a soldering 664 * iron to the board), however we can detect it. The method we use 665 * here is to put the NIC into digital loopback mode, set the receiver 666 * to promiscuous mode, and then try to send a frame. We then compare 667 * the frame data we sent to what was received. If the data matches, 668 * then the NIC is working correctly, otherwise we know the user has 669 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 670 * slot. In the latter case, there's no way the NIC can work correctly, 671 * so we print out a message on the console and abort the device attach. 672 */ 673 674static int 675re_diag(sc) 676 struct rl_softc *sc; 677{ 678 struct ifnet *ifp = sc->rl_ifp; 679 struct mbuf *m0; 680 struct ether_header *eh; 681 struct rl_desc *cur_rx; 682 u_int16_t status; 683 u_int32_t rxstat; 684 int total_len, i, error = 0; 685 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 686 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 687 688 /* Allocate a single mbuf */ 689 MGETHDR(m0, M_DONTWAIT, MT_DATA); 690 if (m0 == NULL) 691 return (ENOBUFS); 692 693 RL_LOCK(sc); 694 695 /* 696 * Initialize the NIC in test mode. This sets the chip up 697 * so that it can send and receive frames, but performs the 698 * following special functions: 699 * - Puts receiver in promiscuous mode 700 * - Enables digital loopback mode 701 * - Leaves interrupts turned off 702 */ 703 704 ifp->if_flags |= IFF_PROMISC; 705 sc->rl_testmode = 1; 706 re_init_locked(sc); 707 re_stop(sc); 708 DELAY(100000); 709 re_init_locked(sc); 710 711 /* Put some data in the mbuf */ 712 713 eh = mtod(m0, struct ether_header *); 714 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 715 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 716 eh->ether_type = htons(ETHERTYPE_IP); 717 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 718 719 /* 720 * Queue the packet, start transmission. 721 * Note: IF_HANDOFF() ultimately calls re_start() for us. 722 */ 723 724 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 725 RL_UNLOCK(sc); 726 /* XXX: re_diag must not be called when in ALTQ mode */ 727 IF_HANDOFF(&ifp->if_snd, m0, ifp); 728 RL_LOCK(sc); 729 m0 = NULL; 730 731 /* Wait for it to propagate through the chip */ 732 733 DELAY(100000); 734 for (i = 0; i < RL_TIMEOUT; i++) { 735 status = CSR_READ_2(sc, RL_ISR); 736 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 737 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 738 break; 739 DELAY(10); 740 } 741 742 if (i == RL_TIMEOUT) { 743 if_printf(ifp, "diagnostic failed, failed to receive packet " 744 "in loopback mode\n"); 745 error = EIO; 746 goto done; 747 } 748 749 /* 750 * The packet should have been dumped into the first 751 * entry in the RX DMA ring. Grab it from there. 752 */ 753 754 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 755 sc->rl_ldata.rl_rx_list_map, 756 BUS_DMASYNC_POSTREAD); 757 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 758 sc->rl_ldata.rl_rx_dmamap[0], 759 BUS_DMASYNC_POSTWRITE); 760 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 761 sc->rl_ldata.rl_rx_dmamap[0]); 762 763 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 764 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 765 eh = mtod(m0, struct ether_header *); 766 767 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 768 total_len = RL_RXBYTES(cur_rx); 769 rxstat = le32toh(cur_rx->rl_cmdstat); 770 771 if (total_len != ETHER_MIN_LEN) { 772 if_printf(ifp, "diagnostic failed, received short packet\n"); 773 error = EIO; 774 goto done; 775 } 776 777 /* Test that the received packet data matches what we sent. */ 778 779 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 780 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 781 ntohs(eh->ether_type) != ETHERTYPE_IP) { 782 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 783 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 784 dst, ":", src, ":", ETHERTYPE_IP); 785 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 786 eh->ether_dhost, ":", eh->ether_shost, ":", 787 ntohs(eh->ether_type)); 788 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 789 "into a 64-bit PCI slot.\n"); 790 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 791 "for proper operation.\n"); 792 if_printf(ifp, "Read the re(4) man page for more details.\n"); 793 error = EIO; 794 } 795 796done: 797 /* Turn interface off, release resources */ 798 799 sc->rl_testmode = 0; 800 ifp->if_flags &= ~IFF_PROMISC; 801 re_stop(sc); 802 if (m0 != NULL) 803 m_freem(m0); 804 805 RL_UNLOCK(sc); 806 807 return (error); 808} 809 810/* 811 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 812 * IDs against our list and return a device name if we find a match. 813 */ 814static int 815re_probe(dev) 816 device_t dev; 817{ 818 struct rl_type *t; 819 struct rl_softc *sc; 820 int rid; 821 u_int32_t hwrev; 822 823 t = re_devs; 824 sc = device_get_softc(dev); 825 826 while (t->rl_name != NULL) { 827 if ((pci_get_vendor(dev) == t->rl_vid) && 828 (pci_get_device(dev) == t->rl_did)) { 829 830 /* 831 * Temporarily map the I/O space 832 * so we can read the chip ID register. 833 */ 834 rid = RL_RID; 835 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 836 RF_ACTIVE); 837 if (sc->rl_res == NULL) { 838 device_printf(dev, 839 "couldn't map ports/memory\n"); 840 return (ENXIO); 841 } 842 sc->rl_btag = rman_get_bustag(sc->rl_res); 843 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 844 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 845 bus_release_resource(dev, RL_RES, 846 RL_RID, sc->rl_res); 847 if (t->rl_basetype == hwrev) { 848 device_set_desc(dev, t->rl_name); 849 return (BUS_PROBE_DEFAULT); 850 } 851 } 852 t++; 853 } 854 855 return (ENXIO); 856} 857 858/* 859 * This routine takes the segment list provided as the result of 860 * a bus_dma_map_load() operation and assigns the addresses/lengths 861 * to RealTek DMA descriptors. This can be called either by the RX 862 * code or the TX code. In the RX case, we'll probably wind up mapping 863 * at most one segment. For the TX case, there could be any number of 864 * segments since TX packets may span multiple mbufs. In either case, 865 * if the number of segments is larger than the rl_maxsegs limit 866 * specified by the caller, we abort the mapping operation. Sadly, 867 * whoever designed the buffer mapping API did not provide a way to 868 * return an error from here, so we have to fake it a bit. 869 */ 870 871static void 872re_dma_map_desc(arg, segs, nseg, mapsize, error) 873 void *arg; 874 bus_dma_segment_t *segs; 875 int nseg; 876 bus_size_t mapsize; 877 int error; 878{ 879 struct rl_dmaload_arg *ctx; 880 struct rl_desc *d = NULL; 881 int i = 0, idx; 882 883 if (error) 884 return; 885 886 ctx = arg; 887 888 /* Signal error to caller if there's too many segments */ 889 if (nseg > ctx->rl_maxsegs) { 890 ctx->rl_maxsegs = 0; 891 return; 892 } 893 894 /* 895 * Map the segment array into descriptors. Note that we set the 896 * start-of-frame and end-of-frame markers for either TX or RX, but 897 * they really only have meaning in the TX case. (In the RX case, 898 * it's the chip that tells us where packets begin and end.) 899 * We also keep track of the end of the ring and set the 900 * end-of-ring bits as needed, and we set the ownership bits 901 * in all except the very first descriptor. (The caller will 902 * set this descriptor later when it start transmission or 903 * reception.) 904 */ 905 idx = ctx->rl_idx; 906 for (;;) { 907 u_int32_t cmdstat; 908 d = &ctx->rl_ring[idx]; 909 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 910 ctx->rl_maxsegs = 0; 911 return; 912 } 913 cmdstat = segs[i].ds_len; 914 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 915 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 916 if (i == 0) 917 cmdstat |= RL_TDESC_CMD_SOF; 918 else 919 cmdstat |= RL_TDESC_CMD_OWN; 920 if (idx == (RL_RX_DESC_CNT - 1)) 921 cmdstat |= RL_TDESC_CMD_EOR; 922 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 923 i++; 924 if (i == nseg) 925 break; 926 RL_DESC_INC(idx); 927 } 928 929 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 930 ctx->rl_maxsegs = nseg; 931 ctx->rl_idx = idx; 932} 933 934/* 935 * Map a single buffer address. 936 */ 937 938static void 939re_dma_map_addr(arg, segs, nseg, error) 940 void *arg; 941 bus_dma_segment_t *segs; 942 int nseg; 943 int error; 944{ 945 bus_addr_t *addr; 946 947 if (error) 948 return; 949 950 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 951 addr = arg; 952 *addr = segs->ds_addr; 953} 954 955static int 956re_allocmem(dev, sc) 957 device_t dev; 958 struct rl_softc *sc; 959{ 960 int error; 961 int nseg; 962 int i; 963 964 /* 965 * Allocate map for RX mbufs. 966 */ 967 nseg = 32; 968 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 969 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 970 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 971 NULL, NULL, &sc->rl_ldata.rl_mtag); 972 if (error) { 973 device_printf(dev, "could not allocate dma tag\n"); 974 return (ENOMEM); 975 } 976 977 /* 978 * Allocate map for TX descriptor list. 979 */ 980 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 981 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 982 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 983 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 984 if (error) { 985 device_printf(dev, "could not allocate dma tag\n"); 986 return (ENOMEM); 987 } 988 989 /* Allocate DMA'able memory for the TX ring */ 990 991 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 992 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 993 &sc->rl_ldata.rl_tx_list_map); 994 if (error) 995 return (ENOMEM); 996 997 /* Load the map for the TX ring. */ 998 999 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1000 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1001 RL_TX_LIST_SZ, re_dma_map_addr, 1002 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1003 1004 /* Create DMA maps for TX buffers */ 1005 1006 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1007 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1008 &sc->rl_ldata.rl_tx_dmamap[i]); 1009 if (error) { 1010 device_printf(dev, "can't create DMA map for TX\n"); 1011 return (ENOMEM); 1012 } 1013 } 1014 1015 /* 1016 * Allocate map for RX descriptor list. 1017 */ 1018 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1019 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1020 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1021 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1022 if (error) { 1023 device_printf(dev, "could not allocate dma tag\n"); 1024 return (ENOMEM); 1025 } 1026 1027 /* Allocate DMA'able memory for the RX ring */ 1028 1029 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1030 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1031 &sc->rl_ldata.rl_rx_list_map); 1032 if (error) 1033 return (ENOMEM); 1034 1035 /* Load the map for the RX ring. */ 1036 1037 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1038 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1039 RL_RX_LIST_SZ, re_dma_map_addr, 1040 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1041 1042 /* Create DMA maps for RX buffers */ 1043 1044 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1045 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1046 &sc->rl_ldata.rl_rx_dmamap[i]); 1047 if (error) { 1048 device_printf(dev, "can't create DMA map for RX\n"); 1049 return (ENOMEM); 1050 } 1051 } 1052 1053 return (0); 1054} 1055 1056/* 1057 * Attach the interface. Allocate softc structures, do ifmedia 1058 * setup and ethernet/BPF attach. 1059 */ 1060static int 1061re_attach(dev) 1062 device_t dev; 1063{ 1064 u_char eaddr[ETHER_ADDR_LEN]; 1065 u_int16_t as[3]; 1066 struct rl_softc *sc; 1067 struct ifnet *ifp; 1068 struct rl_hwrev *hw_rev; 1069 int hwrev; 1070 u_int16_t re_did = 0; 1071 int error = 0, rid, i; 1072 1073 sc = device_get_softc(dev); 1074 1075 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1076 MTX_DEF); 1077 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1078 1079 /* 1080 * Map control/status registers. 1081 */ 1082 pci_enable_busmaster(dev); 1083 1084 rid = RL_RID; 1085 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1086 RF_ACTIVE); 1087 1088 if (sc->rl_res == NULL) { 1089 device_printf(dev, "couldn't map ports/memory\n"); 1090 error = ENXIO; 1091 goto fail; 1092 } 1093 1094 sc->rl_btag = rman_get_bustag(sc->rl_res); 1095 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1096 1097 /* Allocate interrupt */ 1098 rid = 0; 1099 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1100 RF_SHAREABLE | RF_ACTIVE); 1101 1102 if (sc->rl_irq == NULL) { 1103 device_printf(dev, "couldn't map interrupt\n"); 1104 error = ENXIO; 1105 goto fail; 1106 } 1107 1108 /* Reset the adapter. */ 1109 RL_LOCK(sc); 1110 re_reset(sc); 1111 RL_UNLOCK(sc); 1112 1113 hw_rev = re_hwrevs; 1114 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1115 while (hw_rev->rl_desc != NULL) { 1116 if (hw_rev->rl_rev == hwrev) { 1117 sc->rl_type = hw_rev->rl_type; 1118 break; 1119 } 1120 hw_rev++; 1121 } 1122 1123 if (sc->rl_type == RL_8169) { 1124 1125 /* Set RX length mask */ 1126 1127 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1128 1129 /* Force station address autoload from the EEPROM */ 1130 1131 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1132 for (i = 0; i < RL_TIMEOUT; i++) { 1133 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1134 break; 1135 DELAY(100); 1136 } 1137 if (i == RL_TIMEOUT) 1138 device_printf(dev, "eeprom autoload timed out\n"); 1139 1140 for (i = 0; i < ETHER_ADDR_LEN; i++) 1141 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1142 } else { 1143 1144 /* Set RX length mask */ 1145 1146 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1147 1148 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1149 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1150 if (re_did != 0x8129) 1151 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1152 1153 /* 1154 * Get station address from the EEPROM. 1155 */ 1156 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1157 for (i = 0; i < 3; i++) { 1158 eaddr[(i * 2) + 0] = as[i] & 0xff; 1159 eaddr[(i * 2) + 1] = as[i] >> 8; 1160 } 1161 } 1162 1163 /* 1164 * Allocate the parent bus DMA tag appropriate for PCI. 1165 */ 1166#define RL_NSEG_NEW 32 1167 error = bus_dma_tag_create(NULL, /* parent */ 1168 1, 0, /* alignment, boundary */ 1169 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1170 BUS_SPACE_MAXADDR, /* highaddr */ 1171 NULL, NULL, /* filter, filterarg */ 1172 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1173 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1174 BUS_DMA_ALLOCNOW, /* flags */ 1175 NULL, NULL, /* lockfunc, lockarg */ 1176 &sc->rl_parent_tag); 1177 if (error) 1178 goto fail; 1179 1180 error = re_allocmem(dev, sc); 1181 1182 if (error) 1183 goto fail; 1184 1185 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1186 if (ifp == NULL) { 1187 device_printf(dev, "can not if_alloc()\n"); 1188 error = ENOSPC; 1189 goto fail; 1190 } 1191 1192 /* Do MII setup */ 1193 if (mii_phy_probe(dev, &sc->rl_miibus, 1194 re_ifmedia_upd, re_ifmedia_sts)) { 1195 device_printf(dev, "MII without any phy!\n"); 1196 error = ENXIO; 1197 goto fail; 1198 } 1199 1200 ifp->if_softc = sc; 1201 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1202 ifp->if_mtu = ETHERMTU; 1203 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1204 ifp->if_ioctl = re_ioctl; 1205 ifp->if_capabilities = IFCAP_VLAN_MTU; 1206 ifp->if_start = re_start; 1207 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0; 1208 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1209 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1210#ifdef DEVICE_POLLING 1211 ifp->if_capabilities |= IFCAP_POLLING; 1212#endif 1213 ifp->if_watchdog = re_watchdog; 1214 ifp->if_init = re_init; 1215 if (sc->rl_type == RL_8169) 1216 ifp->if_baudrate = 1000000000; 1217 else 1218 ifp->if_baudrate = 100000000; 1219 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1220 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1221 IFQ_SET_READY(&ifp->if_snd); 1222 1223 /* 1224 * Call MI attach routine. 1225 */ 1226 ether_ifattach(ifp, eaddr); 1227 1228 /* Perform hardware diagnostic. */ 1229 error = re_diag(sc); 1230 1231 if (error) { 1232 device_printf(dev, "attach aborted due to hardware diag failure\n"); 1233 ether_ifdetach(ifp); 1234 goto fail; 1235 } 1236 1237 /* Hook interrupt last to avoid having to lock softc */ 1238 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1239 re_intr, sc, &sc->rl_intrhand); 1240 if (error) { 1241 device_printf(dev, "couldn't set up irq\n"); 1242 ether_ifdetach(ifp); 1243 } 1244 1245fail: 1246 if (error) 1247 re_detach(dev); 1248 1249 return (error); 1250} 1251 1252/* 1253 * Shutdown hardware and free up resources. This can be called any 1254 * time after the mutex has been initialized. It is called in both 1255 * the error case in attach and the normal detach case so it needs 1256 * to be careful about only freeing resources that have actually been 1257 * allocated. 1258 */ 1259static int 1260re_detach(dev) 1261 device_t dev; 1262{ 1263 struct rl_softc *sc; 1264 struct ifnet *ifp; 1265 int i; 1266 1267 sc = device_get_softc(dev); 1268 ifp = sc->rl_ifp; 1269 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1270 1271#ifdef DEVICE_POLLING 1272 if (ifp->if_capenable & IFCAP_POLLING) 1273 ether_poll_deregister(ifp); 1274#endif 1275 1276 /* These should only be active if attach succeeded */ 1277 if (device_is_attached(dev)) { 1278 RL_LOCK(sc); 1279#if 0 1280 sc->suspended = 1; 1281#endif 1282 re_stop(sc); 1283 RL_UNLOCK(sc); 1284 callout_drain(&sc->rl_stat_callout); 1285 /* 1286 * Force off the IFF_UP flag here, in case someone 1287 * still had a BPF descriptor attached to this 1288 * interface. If they do, ether_ifdetach() will cause 1289 * the BPF code to try and clear the promisc mode 1290 * flag, which will bubble down to re_ioctl(), 1291 * which will try to call re_init() again. This will 1292 * turn the NIC back on and restart the MII ticker, 1293 * which will panic the system when the kernel tries 1294 * to invoke the re_tick() function that isn't there 1295 * anymore. 1296 */ 1297 ifp->if_flags &= ~IFF_UP; 1298 ether_ifdetach(ifp); 1299 } 1300 if (sc->rl_miibus) 1301 device_delete_child(dev, sc->rl_miibus); 1302 bus_generic_detach(dev); 1303 1304 /* 1305 * The rest is resource deallocation, so we should already be 1306 * stopped here. 1307 */ 1308 1309 if (sc->rl_intrhand) 1310 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1311 if (ifp != NULL) 1312 if_free(ifp); 1313 if (sc->rl_irq) 1314 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1315 if (sc->rl_res) 1316 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1317 1318 1319 /* Unload and free the RX DMA ring memory and map */ 1320 1321 if (sc->rl_ldata.rl_rx_list_tag) { 1322 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1323 sc->rl_ldata.rl_rx_list_map); 1324 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1325 sc->rl_ldata.rl_rx_list, 1326 sc->rl_ldata.rl_rx_list_map); 1327 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1328 } 1329 1330 /* Unload and free the TX DMA ring memory and map */ 1331 1332 if (sc->rl_ldata.rl_tx_list_tag) { 1333 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1334 sc->rl_ldata.rl_tx_list_map); 1335 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1336 sc->rl_ldata.rl_tx_list, 1337 sc->rl_ldata.rl_tx_list_map); 1338 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1339 } 1340 1341 /* Destroy all the RX and TX buffer maps */ 1342 1343 if (sc->rl_ldata.rl_mtag) { 1344 for (i = 0; i < RL_TX_DESC_CNT; i++) 1345 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1346 sc->rl_ldata.rl_tx_dmamap[i]); 1347 for (i = 0; i < RL_RX_DESC_CNT; i++) 1348 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1349 sc->rl_ldata.rl_rx_dmamap[i]); 1350 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1351 } 1352 1353 /* Unload and free the stats buffer and map */ 1354 1355 if (sc->rl_ldata.rl_stag) { 1356 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1357 sc->rl_ldata.rl_rx_list_map); 1358 bus_dmamem_free(sc->rl_ldata.rl_stag, 1359 sc->rl_ldata.rl_stats, 1360 sc->rl_ldata.rl_smap); 1361 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1362 } 1363 1364 if (sc->rl_parent_tag) 1365 bus_dma_tag_destroy(sc->rl_parent_tag); 1366 1367 mtx_destroy(&sc->rl_mtx); 1368 1369 return (0); 1370} 1371 1372static int 1373re_newbuf(sc, idx, m) 1374 struct rl_softc *sc; 1375 int idx; 1376 struct mbuf *m; 1377{ 1378 struct rl_dmaload_arg arg; 1379 struct mbuf *n = NULL; 1380 int error; 1381 1382 if (m == NULL) { 1383 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1384 if (n == NULL) 1385 return (ENOBUFS); 1386 m = n; 1387 } else 1388 m->m_data = m->m_ext.ext_buf; 1389 1390 m->m_len = m->m_pkthdr.len = MCLBYTES; 1391#ifdef RE_FIXUP_RX 1392 /* 1393 * This is part of an evil trick to deal with non-x86 platforms. 1394 * The RealTek chip requires RX buffers to be aligned on 64-bit 1395 * boundaries, but that will hose non-x86 machines. To get around 1396 * this, we leave some empty space at the start of each buffer 1397 * and for non-x86 hosts, we copy the buffer back six bytes 1398 * to achieve word alignment. This is slightly more efficient 1399 * than allocating a new buffer, copying the contents, and 1400 * discarding the old buffer. 1401 */ 1402 m_adj(m, RE_ETHER_ALIGN); 1403#endif 1404 arg.sc = sc; 1405 arg.rl_idx = idx; 1406 arg.rl_maxsegs = 1; 1407 arg.rl_flags = 0; 1408 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1409 1410 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1411 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1412 &arg, BUS_DMA_NOWAIT); 1413 if (error || arg.rl_maxsegs != 1) { 1414 if (n != NULL) 1415 m_freem(n); 1416 return (ENOMEM); 1417 } 1418 1419 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1420 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1421 1422 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1423 sc->rl_ldata.rl_rx_dmamap[idx], 1424 BUS_DMASYNC_PREREAD); 1425 1426 return (0); 1427} 1428 1429#ifdef RE_FIXUP_RX 1430static __inline void 1431re_fixup_rx(m) 1432 struct mbuf *m; 1433{ 1434 int i; 1435 uint16_t *src, *dst; 1436 1437 src = mtod(m, uint16_t *); 1438 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1439 1440 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1441 *dst++ = *src++; 1442 1443 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1444 1445 return; 1446} 1447#endif 1448 1449static int 1450re_tx_list_init(sc) 1451 struct rl_softc *sc; 1452{ 1453 1454 RL_LOCK_ASSERT(sc); 1455 1456 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1457 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1458 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1459 1460 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1461 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1462 sc->rl_ldata.rl_tx_prodidx = 0; 1463 sc->rl_ldata.rl_tx_considx = 0; 1464 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1465 1466 return (0); 1467} 1468 1469static int 1470re_rx_list_init(sc) 1471 struct rl_softc *sc; 1472{ 1473 int i; 1474 1475 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1476 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1477 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1478 1479 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1480 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1481 return (ENOBUFS); 1482 } 1483 1484 /* Flush the RX descriptors */ 1485 1486 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1487 sc->rl_ldata.rl_rx_list_map, 1488 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1489 1490 sc->rl_ldata.rl_rx_prodidx = 0; 1491 sc->rl_head = sc->rl_tail = NULL; 1492 1493 return (0); 1494} 1495 1496/* 1497 * RX handler for C+ and 8169. For the gigE chips, we support 1498 * the reception of jumbo frames that have been fragmented 1499 * across multiple 2K mbuf cluster buffers. 1500 */ 1501static void 1502re_rxeof(sc) 1503 struct rl_softc *sc; 1504{ 1505 struct mbuf *m; 1506 struct ifnet *ifp; 1507 int i, total_len; 1508 struct rl_desc *cur_rx; 1509 u_int32_t rxstat, rxvlan; 1510 1511 RL_LOCK_ASSERT(sc); 1512 1513 ifp = sc->rl_ifp; 1514 i = sc->rl_ldata.rl_rx_prodidx; 1515 1516 /* Invalidate the descriptor memory */ 1517 1518 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1519 sc->rl_ldata.rl_rx_list_map, 1520 BUS_DMASYNC_POSTREAD); 1521 1522 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1523 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1524 m = sc->rl_ldata.rl_rx_mbuf[i]; 1525 total_len = RL_RXBYTES(cur_rx); 1526 rxstat = le32toh(cur_rx->rl_cmdstat); 1527 rxvlan = le32toh(cur_rx->rl_vlanctl); 1528 1529 /* Invalidate the RX mbuf and unload its map */ 1530 1531 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1532 sc->rl_ldata.rl_rx_dmamap[i], 1533 BUS_DMASYNC_POSTWRITE); 1534 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1535 sc->rl_ldata.rl_rx_dmamap[i]); 1536 1537 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1538 m->m_len = RE_RX_DESC_BUFLEN; 1539 if (sc->rl_head == NULL) 1540 sc->rl_head = sc->rl_tail = m; 1541 else { 1542 m->m_flags &= ~M_PKTHDR; 1543 sc->rl_tail->m_next = m; 1544 sc->rl_tail = m; 1545 } 1546 re_newbuf(sc, i, NULL); 1547 RL_DESC_INC(i); 1548 continue; 1549 } 1550 1551 /* 1552 * NOTE: for the 8139C+, the frame length field 1553 * is always 12 bits in size, but for the gigE chips, 1554 * it is 13 bits (since the max RX frame length is 16K). 1555 * Unfortunately, all 32 bits in the status word 1556 * were already used, so to make room for the extra 1557 * length bit, RealTek took out the 'frame alignment 1558 * error' bit and shifted the other status bits 1559 * over one slot. The OWN, EOR, FS and LS bits are 1560 * still in the same places. We have already extracted 1561 * the frame length and checked the OWN bit, so rather 1562 * than using an alternate bit mapping, we shift the 1563 * status bits one space to the right so we can evaluate 1564 * them using the 8169 status as though it was in the 1565 * same format as that of the 8139C+. 1566 */ 1567 if (sc->rl_type == RL_8169) 1568 rxstat >>= 1; 1569 1570 /* 1571 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1572 * set, but if CRC is clear, it will still be a valid frame. 1573 */ 1574 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1575 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1576 ifp->if_ierrors++; 1577 /* 1578 * If this is part of a multi-fragment packet, 1579 * discard all the pieces. 1580 */ 1581 if (sc->rl_head != NULL) { 1582 m_freem(sc->rl_head); 1583 sc->rl_head = sc->rl_tail = NULL; 1584 } 1585 re_newbuf(sc, i, m); 1586 RL_DESC_INC(i); 1587 continue; 1588 } 1589 1590 /* 1591 * If allocating a replacement mbuf fails, 1592 * reload the current one. 1593 */ 1594 1595 if (re_newbuf(sc, i, NULL)) { 1596 ifp->if_ierrors++; 1597 if (sc->rl_head != NULL) { 1598 m_freem(sc->rl_head); 1599 sc->rl_head = sc->rl_tail = NULL; 1600 } 1601 re_newbuf(sc, i, m); 1602 RL_DESC_INC(i); 1603 continue; 1604 } 1605 1606 RL_DESC_INC(i); 1607 1608 if (sc->rl_head != NULL) { 1609 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1610 if (m->m_len == 0) 1611 m->m_len = RE_RX_DESC_BUFLEN; 1612 /* 1613 * Special case: if there's 4 bytes or less 1614 * in this buffer, the mbuf can be discarded: 1615 * the last 4 bytes is the CRC, which we don't 1616 * care about anyway. 1617 */ 1618 if (m->m_len <= ETHER_CRC_LEN) { 1619 sc->rl_tail->m_len -= 1620 (ETHER_CRC_LEN - m->m_len); 1621 m_freem(m); 1622 } else { 1623 m->m_len -= ETHER_CRC_LEN; 1624 m->m_flags &= ~M_PKTHDR; 1625 sc->rl_tail->m_next = m; 1626 } 1627 m = sc->rl_head; 1628 sc->rl_head = sc->rl_tail = NULL; 1629 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1630 } else 1631 m->m_pkthdr.len = m->m_len = 1632 (total_len - ETHER_CRC_LEN); 1633 1634#ifdef RE_FIXUP_RX 1635 re_fixup_rx(m); 1636#endif 1637 ifp->if_ipackets++; 1638 m->m_pkthdr.rcvif = ifp; 1639 1640 /* Do RX checksumming if enabled */ 1641 1642 if (ifp->if_capenable & IFCAP_RXCSUM) { 1643 1644 /* Check IP header checksum */ 1645 if (rxstat & RL_RDESC_STAT_PROTOID) 1646 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1647 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1648 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1649 1650 /* Check TCP/UDP checksum */ 1651 if ((RL_TCPPKT(rxstat) && 1652 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1653 (RL_UDPPKT(rxstat) && 1654 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1655 m->m_pkthdr.csum_flags |= 1656 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1657 m->m_pkthdr.csum_data = 0xffff; 1658 } 1659 } 1660 1661 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1662 VLAN_INPUT_TAG(ifp, m, 1663 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1664 RL_UNLOCK(sc); 1665 (*ifp->if_input)(ifp, m); 1666 RL_LOCK(sc); 1667 } 1668 1669 /* Flush the RX DMA ring */ 1670 1671 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1672 sc->rl_ldata.rl_rx_list_map, 1673 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1674 1675 sc->rl_ldata.rl_rx_prodidx = i; 1676} 1677 1678static void 1679re_txeof(sc) 1680 struct rl_softc *sc; 1681{ 1682 struct ifnet *ifp; 1683 u_int32_t txstat; 1684 int idx; 1685 1686 ifp = sc->rl_ifp; 1687 idx = sc->rl_ldata.rl_tx_considx; 1688 1689 /* Invalidate the TX descriptor list */ 1690 1691 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1692 sc->rl_ldata.rl_tx_list_map, 1693 BUS_DMASYNC_POSTREAD); 1694 1695 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1696 1697 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1698 if (txstat & RL_TDESC_CMD_OWN) 1699 break; 1700 1701 /* 1702 * We only stash mbufs in the last descriptor 1703 * in a fragment chain, which also happens to 1704 * be the only place where the TX status bits 1705 * are valid. 1706 */ 1707 1708 if (txstat & RL_TDESC_CMD_EOF) { 1709 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1710 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1711 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1712 sc->rl_ldata.rl_tx_dmamap[idx]); 1713 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1714 RL_TDESC_STAT_COLCNT)) 1715 ifp->if_collisions++; 1716 if (txstat & RL_TDESC_STAT_TXERRSUM) 1717 ifp->if_oerrors++; 1718 else 1719 ifp->if_opackets++; 1720 } 1721 sc->rl_ldata.rl_tx_free++; 1722 RL_DESC_INC(idx); 1723 } 1724 1725 /* No changes made to the TX ring, so no flush needed */ 1726 1727 if (idx != sc->rl_ldata.rl_tx_considx) { 1728 sc->rl_ldata.rl_tx_considx = idx; 1729 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1730 ifp->if_timer = 0; 1731 } 1732 1733 /* 1734 * If not all descriptors have been released reaped yet, 1735 * reload the timer so that we will eventually get another 1736 * interrupt that will cause us to re-enter this routine. 1737 * This is done in case the transmitter has gone idle. 1738 */ 1739 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1740 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1741} 1742 1743static void 1744re_tick(xsc) 1745 void *xsc; 1746{ 1747 struct rl_softc *sc; 1748 struct mii_data *mii; 1749 1750 sc = xsc; 1751 1752 RL_LOCK_ASSERT(sc); 1753 1754 mii = device_get_softc(sc->rl_miibus); 1755 1756 mii_tick(mii); 1757 1758 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1759} 1760 1761#ifdef DEVICE_POLLING 1762static void 1763re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1764{ 1765 struct rl_softc *sc = ifp->if_softc; 1766 1767 RL_LOCK(sc); 1768 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1769 re_poll_locked(ifp, cmd, count); 1770 RL_UNLOCK(sc); 1771} 1772 1773static void 1774re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1775{ 1776 struct rl_softc *sc = ifp->if_softc; 1777 1778 RL_LOCK_ASSERT(sc); 1779 1780 sc->rxcycles = count; 1781 re_rxeof(sc); 1782 re_txeof(sc); 1783 1784 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1785 re_start_locked(ifp); 1786 1787 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1788 u_int16_t status; 1789 1790 status = CSR_READ_2(sc, RL_ISR); 1791 if (status == 0xffff) 1792 return; 1793 if (status) 1794 CSR_WRITE_2(sc, RL_ISR, status); 1795 1796 /* 1797 * XXX check behaviour on receiver stalls. 1798 */ 1799 1800 if (status & RL_ISR_SYSTEM_ERR) { 1801 re_reset(sc); 1802 re_init_locked(sc); 1803 } 1804 } 1805} 1806#endif /* DEVICE_POLLING */ 1807 1808static void 1809re_intr(arg) 1810 void *arg; 1811{ 1812 struct rl_softc *sc; 1813 struct ifnet *ifp; 1814 u_int16_t status; 1815 1816 sc = arg; 1817 1818 RL_LOCK(sc); 1819 1820 ifp = sc->rl_ifp; 1821 1822 if (sc->suspended || !(ifp->if_flags & IFF_UP)) 1823 goto done_locked; 1824 1825#ifdef DEVICE_POLLING 1826 if (ifp->if_capenable & IFCAP_POLLING) 1827 goto done_locked; 1828#endif 1829 1830 for (;;) { 1831 1832 status = CSR_READ_2(sc, RL_ISR); 1833 /* If the card has gone away the read returns 0xffff. */ 1834 if (status == 0xffff) 1835 break; 1836 if (status) 1837 CSR_WRITE_2(sc, RL_ISR, status); 1838 1839 if ((status & RL_INTRS_CPLUS) == 0) 1840 break; 1841 1842 if ((status & RL_ISR_RX_OK) || 1843 (status & RL_ISR_RX_ERR)) 1844 re_rxeof(sc); 1845 1846 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1847 (status & RL_ISR_TX_ERR) || 1848 (status & RL_ISR_TX_DESC_UNAVAIL)) 1849 re_txeof(sc); 1850 1851 if (status & RL_ISR_SYSTEM_ERR) { 1852 re_reset(sc); 1853 re_init_locked(sc); 1854 } 1855 1856 if (status & RL_ISR_LINKCHG) { 1857 callout_stop(&sc->rl_stat_callout); 1858 re_tick(sc); 1859 } 1860 } 1861 1862 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1863 re_start_locked(ifp); 1864 1865done_locked: 1866 RL_UNLOCK(sc); 1867} 1868 1869static int 1870re_encap(sc, m_head, idx) 1871 struct rl_softc *sc; 1872 struct mbuf **m_head; 1873 int *idx; 1874{ 1875 struct mbuf *m_new = NULL; 1876 struct rl_dmaload_arg arg; 1877 bus_dmamap_t map; 1878 int error; 1879 struct m_tag *mtag; 1880 1881 RL_LOCK_ASSERT(sc); 1882 1883 if (sc->rl_ldata.rl_tx_free <= 4) 1884 return (EFBIG); 1885 1886 /* 1887 * Set up checksum offload. Note: checksum offload bits must 1888 * appear in all descriptors of a multi-descriptor transmit 1889 * attempt. This is according to testing done with an 8169 1890 * chip. This is a requirement. 1891 */ 1892 1893 arg.rl_flags = 0; 1894 1895 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1896 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1897 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1898 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1899 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1900 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1901 1902 arg.sc = sc; 1903 arg.rl_idx = *idx; 1904 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1905 if (arg.rl_maxsegs > 4) 1906 arg.rl_maxsegs -= 4; 1907 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1908 1909 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1910 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1911 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1912 1913 if (error && error != EFBIG) { 1914 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", error); 1915 return (ENOBUFS); 1916 } 1917 1918 /* Too many segments to map, coalesce into a single mbuf */ 1919 1920 if (error || arg.rl_maxsegs == 0) { 1921 m_new = m_defrag(*m_head, M_DONTWAIT); 1922 if (m_new == NULL) 1923 return (ENOBUFS); 1924 else 1925 *m_head = m_new; 1926 1927 arg.sc = sc; 1928 arg.rl_idx = *idx; 1929 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1930 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1931 1932 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1933 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1934 if (error) { 1935 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", 1936 error); 1937 return (EFBIG); 1938 } 1939 } 1940 1941 /* 1942 * Insure that the map for this transmission 1943 * is placed at the array index of the last descriptor 1944 * in this chain. (Swap last and first dmamaps.) 1945 */ 1946 sc->rl_ldata.rl_tx_dmamap[*idx] = 1947 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1948 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1949 1950 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 1951 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1952 1953 /* 1954 * Set up hardware VLAN tagging. Note: vlan tag info must 1955 * appear in the first descriptor of a multi-descriptor 1956 * transmission attempt. 1957 */ 1958 1959 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head); 1960 if (mtag != NULL) 1961 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1962 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1963 1964 /* Transfer ownership of packet to the chip. */ 1965 1966 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1967 htole32(RL_TDESC_CMD_OWN); 1968 if (*idx != arg.rl_idx) 1969 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1970 htole32(RL_TDESC_CMD_OWN); 1971 1972 RL_DESC_INC(arg.rl_idx); 1973 *idx = arg.rl_idx; 1974 1975 return (0); 1976} 1977 1978static void 1979re_start(ifp) 1980 struct ifnet *ifp; 1981{ 1982 struct rl_softc *sc; 1983 1984 sc = ifp->if_softc; 1985 RL_LOCK(sc); 1986 re_start_locked(ifp); 1987 RL_UNLOCK(sc); 1988} 1989 1990/* 1991 * Main transmit routine for C+ and gigE NICs. 1992 */ 1993static void 1994re_start_locked(ifp) 1995 struct ifnet *ifp; 1996{ 1997 struct rl_softc *sc; 1998 struct mbuf *m_head = NULL; 1999 int idx, queued = 0; 2000 2001 sc = ifp->if_softc; 2002 2003 RL_LOCK_ASSERT(sc); 2004 2005 idx = sc->rl_ldata.rl_tx_prodidx; 2006 2007 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2008 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2009 if (m_head == NULL) 2010 break; 2011 2012 if (re_encap(sc, &m_head, &idx)) { 2013 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2014 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2015 break; 2016 } 2017 2018 /* 2019 * If there's a BPF listener, bounce a copy of this frame 2020 * to him. 2021 */ 2022 BPF_MTAP(ifp, m_head); 2023 2024 queued++; 2025 } 2026 2027 if (queued == 0) 2028 return; 2029 2030 /* Flush the TX descriptors */ 2031 2032 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2033 sc->rl_ldata.rl_tx_list_map, 2034 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2035 2036 sc->rl_ldata.rl_tx_prodidx = idx; 2037 2038 /* 2039 * RealTek put the TX poll request register in a different 2040 * location on the 8169 gigE chip. I don't know why. 2041 */ 2042 2043 if (sc->rl_type == RL_8169) 2044 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2045 else 2046 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2047 2048 /* 2049 * Use the countdown timer for interrupt moderation. 2050 * 'TX done' interrupts are disabled. Instead, we reset the 2051 * countdown timer, which will begin counting until it hits 2052 * the value in the TIMERINT register, and then trigger an 2053 * interrupt. Each time we write to the TIMERCNT register, 2054 * the timer count is reset to 0. 2055 */ 2056 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2057 2058 /* 2059 * Set a timeout in case the chip goes out to lunch. 2060 */ 2061 ifp->if_timer = 5; 2062} 2063 2064static void 2065re_init(xsc) 2066 void *xsc; 2067{ 2068 struct rl_softc *sc = xsc; 2069 2070 RL_LOCK(sc); 2071 re_init_locked(sc); 2072 RL_UNLOCK(sc); 2073} 2074 2075static void 2076re_init_locked(sc) 2077 struct rl_softc *sc; 2078{ 2079 struct ifnet *ifp = sc->rl_ifp; 2080 struct mii_data *mii; 2081 u_int32_t rxcfg = 0; 2082 2083 RL_LOCK_ASSERT(sc); 2084 2085 mii = device_get_softc(sc->rl_miibus); 2086 2087 /* 2088 * Cancel pending I/O and free all RX/TX buffers. 2089 */ 2090 re_stop(sc); 2091 2092 /* 2093 * Enable C+ RX and TX mode, as well as VLAN stripping and 2094 * RX checksum offload. We must configure the C+ register 2095 * before all others. 2096 */ 2097 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2098 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2099 RL_CPLUSCMD_VLANSTRIP| 2100 (ifp->if_capenable & IFCAP_RXCSUM ? 2101 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2102 2103 /* 2104 * Init our MAC address. Even though the chipset 2105 * documentation doesn't mention it, we need to enter "Config 2106 * register write enable" mode to modify the ID registers. 2107 */ 2108 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2109 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2110 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[0])); 2111 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2112 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[4])); 2113 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2114 2115 /* 2116 * For C+ mode, initialize the RX descriptors and mbufs. 2117 */ 2118 re_rx_list_init(sc); 2119 re_tx_list_init(sc); 2120 2121 /* 2122 * Enable transmit and receive. 2123 */ 2124 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2125 2126 /* 2127 * Set the initial TX and RX configuration. 2128 */ 2129 if (sc->rl_testmode) { 2130 if (sc->rl_type == RL_8169) 2131 CSR_WRITE_4(sc, RL_TXCFG, 2132 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2133 else 2134 CSR_WRITE_4(sc, RL_TXCFG, 2135 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2136 } else 2137 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2138 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2139 2140 /* Set the individual bit to receive frames for this host only. */ 2141 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2142 rxcfg |= RL_RXCFG_RX_INDIV; 2143 2144 /* If we want promiscuous mode, set the allframes bit. */ 2145 if (ifp->if_flags & IFF_PROMISC) 2146 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2147 else 2148 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2149 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2150 2151 /* 2152 * Set capture broadcast bit to capture broadcast frames. 2153 */ 2154 if (ifp->if_flags & IFF_BROADCAST) 2155 rxcfg |= RL_RXCFG_RX_BROAD; 2156 else 2157 rxcfg &= ~RL_RXCFG_RX_BROAD; 2158 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2159 2160 /* 2161 * Program the multicast filter, if necessary. 2162 */ 2163 re_setmulti(sc); 2164 2165#ifdef DEVICE_POLLING 2166 /* 2167 * Disable interrupts if we are polling. 2168 */ 2169 if (ifp->if_capenable & IFCAP_POLLING) 2170 CSR_WRITE_2(sc, RL_IMR, 0); 2171 else /* otherwise ... */ 2172#endif 2173 /* 2174 * Enable interrupts. 2175 */ 2176 if (sc->rl_testmode) 2177 CSR_WRITE_2(sc, RL_IMR, 0); 2178 else 2179 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2180 2181 /* Set initial TX threshold */ 2182 sc->rl_txthresh = RL_TX_THRESH_INIT; 2183 2184 /* Start RX/TX process. */ 2185 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2186#ifdef notdef 2187 /* Enable receiver and transmitter. */ 2188 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2189#endif 2190 /* 2191 * Load the addresses of the RX and TX lists into the chip. 2192 */ 2193 2194 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2195 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2196 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2197 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2198 2199 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2200 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2201 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2202 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2203 2204 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2205 2206 /* 2207 * Initialize the timer interrupt register so that 2208 * a timer interrupt will be generated once the timer 2209 * reaches a certain number of ticks. The timer is 2210 * reloaded on each transmit. This gives us TX interrupt 2211 * moderation, which dramatically improves TX frame rate. 2212 */ 2213 if (sc->rl_type == RL_8169) 2214 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2215 else 2216 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2217 2218 /* 2219 * For 8169 gigE NICs, set the max allowed RX packet 2220 * size so we can receive jumbo frames. 2221 */ 2222 if (sc->rl_type == RL_8169) 2223 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2224 2225 if (sc->rl_testmode) 2226 return; 2227 2228 mii_mediachg(mii); 2229 2230 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2231 2232 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2233 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2234 2235 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2236} 2237 2238/* 2239 * Set media options. 2240 */ 2241static int 2242re_ifmedia_upd(ifp) 2243 struct ifnet *ifp; 2244{ 2245 struct rl_softc *sc; 2246 struct mii_data *mii; 2247 2248 sc = ifp->if_softc; 2249 mii = device_get_softc(sc->rl_miibus); 2250 RL_LOCK(sc); 2251 mii_mediachg(mii); 2252 RL_UNLOCK(sc); 2253 2254 return (0); 2255} 2256 2257/* 2258 * Report current media status. 2259 */ 2260static void 2261re_ifmedia_sts(ifp, ifmr) 2262 struct ifnet *ifp; 2263 struct ifmediareq *ifmr; 2264{ 2265 struct rl_softc *sc; 2266 struct mii_data *mii; 2267 2268 sc = ifp->if_softc; 2269 mii = device_get_softc(sc->rl_miibus); 2270 2271 RL_LOCK(sc); 2272 mii_pollstat(mii); 2273 RL_UNLOCK(sc); 2274 ifmr->ifm_active = mii->mii_media_active; 2275 ifmr->ifm_status = mii->mii_media_status; 2276} 2277 2278static int 2279re_ioctl(ifp, command, data) 2280 struct ifnet *ifp; 2281 u_long command; 2282 caddr_t data; 2283{ 2284 struct rl_softc *sc = ifp->if_softc; 2285 struct ifreq *ifr = (struct ifreq *) data; 2286 struct mii_data *mii; 2287 int error = 0; 2288 2289 switch (command) { 2290 case SIOCSIFMTU: 2291 RL_LOCK(sc); 2292 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2293 error = EINVAL; 2294 ifp->if_mtu = ifr->ifr_mtu; 2295 RL_UNLOCK(sc); 2296 break; 2297 case SIOCSIFFLAGS: 2298 RL_LOCK(sc); 2299 if (ifp->if_flags & IFF_UP) 2300 re_init_locked(sc); 2301 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2302 re_stop(sc); 2303 RL_UNLOCK(sc); 2304 break; 2305 case SIOCADDMULTI: 2306 case SIOCDELMULTI: 2307 RL_LOCK(sc); 2308 re_setmulti(sc); 2309 RL_UNLOCK(sc); 2310 break; 2311 case SIOCGIFMEDIA: 2312 case SIOCSIFMEDIA: 2313 mii = device_get_softc(sc->rl_miibus); 2314 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2315 break; 2316 case SIOCSIFCAP: 2317 { 2318 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2319#ifdef DEVICE_POLLING 2320 if (mask & IFCAP_POLLING) { 2321 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2322 error = ether_poll_register(re_poll, ifp); 2323 if (error) 2324 return(error); 2325 RL_LOCK(sc); 2326 /* Disable interrupts */ 2327 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2328 ifp->if_capenable |= IFCAP_POLLING; 2329 RL_UNLOCK(sc); 2330 2331 } else { 2332 error = ether_poll_deregister(ifp); 2333 /* Enable interrupts. */ 2334 RL_LOCK(sc); 2335 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2336 ifp->if_capenable &= ~IFCAP_POLLING; 2337 RL_UNLOCK(sc); 2338 } 2339 } 2340#endif /* DEVICE_POLLING */ 2341 if (mask & IFCAP_HWCSUM) { 2342 RL_LOCK(sc); 2343 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_HWCSUM; 2344 if (ifp->if_capenable & IFCAP_TXCSUM) 2345 ifp->if_hwassist = RE_CSUM_FEATURES; 2346 else 2347 ifp->if_hwassist = 0; 2348 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2349 re_init_locked(sc); 2350 RL_UNLOCK(sc); 2351 } 2352 } 2353 break; 2354 default: 2355 error = ether_ioctl(ifp, command, data); 2356 break; 2357 } 2358 2359 return (error); 2360} 2361 2362static void 2363re_watchdog(ifp) 2364 struct ifnet *ifp; 2365{ 2366 struct rl_softc *sc; 2367 2368 sc = ifp->if_softc; 2369 RL_LOCK(sc); 2370 if_printf(ifp, "watchdog timeout\n"); 2371 ifp->if_oerrors++; 2372 2373 re_txeof(sc); 2374 re_rxeof(sc); 2375 re_init_locked(sc); 2376 2377 RL_UNLOCK(sc); 2378} 2379 2380/* 2381 * Stop the adapter and free any mbufs allocated to the 2382 * RX and TX lists. 2383 */ 2384static void 2385re_stop(sc) 2386 struct rl_softc *sc; 2387{ 2388 register int i; 2389 struct ifnet *ifp; 2390 2391 RL_LOCK_ASSERT(sc); 2392 2393 ifp = sc->rl_ifp; 2394 ifp->if_timer = 0; 2395 2396 callout_stop(&sc->rl_stat_callout); 2397 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2398 2399 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2400 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2401 2402 if (sc->rl_head != NULL) { 2403 m_freem(sc->rl_head); 2404 sc->rl_head = sc->rl_tail = NULL; 2405 } 2406 2407 /* Free the TX list buffers. */ 2408 2409 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2410 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2411 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2412 sc->rl_ldata.rl_tx_dmamap[i]); 2413 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2414 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2415 } 2416 } 2417 2418 /* Free the RX list buffers. */ 2419 2420 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2421 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2422 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2423 sc->rl_ldata.rl_rx_dmamap[i]); 2424 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2425 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2426 } 2427 } 2428} 2429 2430/* 2431 * Device suspend routine. Stop the interface and save some PCI 2432 * settings in case the BIOS doesn't restore them properly on 2433 * resume. 2434 */ 2435static int 2436re_suspend(dev) 2437 device_t dev; 2438{ 2439 struct rl_softc *sc; 2440 2441 sc = device_get_softc(dev); 2442 2443 RL_LOCK(sc); 2444 re_stop(sc); 2445 sc->suspended = 1; 2446 RL_UNLOCK(sc); 2447 2448 return (0); 2449} 2450 2451/* 2452 * Device resume routine. Restore some PCI settings in case the BIOS 2453 * doesn't, re-enable busmastering, and restart the interface if 2454 * appropriate. 2455 */ 2456static int 2457re_resume(dev) 2458 device_t dev; 2459{ 2460 struct rl_softc *sc; 2461 struct ifnet *ifp; 2462 2463 sc = device_get_softc(dev); 2464 2465 RL_LOCK(sc); 2466 2467 ifp = sc->rl_ifp; 2468 2469 /* reinitialize interface if necessary */ 2470 if (ifp->if_flags & IFF_UP) 2471 re_init_locked(sc); 2472 2473 sc->suspended = 0; 2474 RL_UNLOCK(sc); 2475 2476 return (0); 2477} 2478 2479/* 2480 * Stop all chip I/O so that the kernel's probe routines don't 2481 * get confused by errant DMAs when rebooting. 2482 */ 2483static void 2484re_shutdown(dev) 2485 device_t dev; 2486{ 2487 struct rl_softc *sc; 2488 2489 sc = device_get_softc(dev); 2490 2491 RL_LOCK(sc); 2492 re_stop(sc); 2493 /* 2494 * Mark interface as down since otherwise we will panic if 2495 * interrupt comes in later on, which can happen in some 2496 * cases. 2497 */ 2498 sc->rl_ifp->if_flags &= ~IFF_UP; 2499 RL_UNLOCK(sc); 2500} 2501