if_re.c revision 150789
11541Srgrimes/*- 21541Srgrimes * Copyright (c) 1997, 1998-2003 31541Srgrimes * Bill Paul <wpaul@windriver.com>. All rights reserved. 41541Srgrimes * 51541Srgrimes * Redistribution and use in source and binary forms, with or without 61541Srgrimes * modification, are permitted provided that the following conditions 71541Srgrimes * are met: 81541Srgrimes * 1. Redistributions of source code must retain the above copyright 91541Srgrimes * notice, this list of conditions and the following disclaimer. 101541Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 111541Srgrimes * notice, this list of conditions and the following disclaimer in the 121541Srgrimes * documentation and/or other materials provided with the distribution. 131541Srgrimes * 3. All advertising materials mentioning features or use of this software 141541Srgrimes * must display the following acknowledgement: 151541Srgrimes * This product includes software developed by Bill Paul. 161541Srgrimes * 4. Neither the name of the author nor the names of any co-contributors 171541Srgrimes * may be used to endorse or promote products derived from this software 181541Srgrimes * without specific prior written permission. 191541Srgrimes * 201541Srgrimes * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 211541Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 221541Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 231541Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 241541Srgrimes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 251541Srgrimes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 261541Srgrimes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 271541Srgrimes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 281541Srgrimes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 291541Srgrimes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 301541Srgrimes * THE POSSIBILITY OF SUCH DAMAGE. 311541Srgrimes */ 321541Srgrimes 331541Srgrimes#include <sys/cdefs.h> 341541Srgrimes__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 150789 2005-10-01 18:56:19Z glebius $"); 351541Srgrimes 361541Srgrimes/* 371541Srgrimes * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 381541Srgrimes * 391541Srgrimes * Written by Bill Paul <wpaul@windriver.com> 401541Srgrimes * Senior Networking Software Engineer 411541Srgrimes * Wind River Systems 421541Srgrimes */ 431541Srgrimes 441541Srgrimes/* 451541Srgrimes * This driver is designed to support RealTek's next generation of 461541Srgrimes * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 471541Srgrimes * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 481541Srgrimes * and the RTL8110S. 491541Srgrimes * 501541Srgrimes * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#include <sys/param.h> 112#include <sys/endian.h> 113#include <sys/systm.h> 114#include <sys/sockio.h> 115#include <sys/mbuf.h> 116#include <sys/malloc.h> 117#include <sys/module.h> 118#include <sys/kernel.h> 119#include <sys/socket.h> 120 121#include <net/if.h> 122#include <net/if_arp.h> 123#include <net/ethernet.h> 124#include <net/if_dl.h> 125#include <net/if_media.h> 126#include <net/if_types.h> 127#include <net/if_vlan_var.h> 128 129#include <net/bpf.h> 130 131#include <machine/bus.h> 132#include <machine/resource.h> 133#include <sys/bus.h> 134#include <sys/rman.h> 135 136#include <dev/mii/mii.h> 137#include <dev/mii/miivar.h> 138 139#include <dev/pci/pcireg.h> 140#include <dev/pci/pcivar.h> 141 142MODULE_DEPEND(re, pci, 1, 1, 1); 143MODULE_DEPEND(re, ether, 1, 1, 1); 144MODULE_DEPEND(re, miibus, 1, 1, 1); 145 146/* "controller miibus0" required. See GENERIC if you get errors here. */ 147#include "miibus_if.h" 148 149/* 150 * Default to using PIO access for this driver. 151 */ 152#define RE_USEIOSPACE 153 154#include <pci/if_rlreg.h> 155 156#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 157 158/* 159 * Various supported device vendors/types and their names. 160 */ 161static struct rl_type re_devs[] = { 162 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 163 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 164 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 165 "RealTek 8139C+ 10/100BaseTX" }, 166 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 167 "RealTek 8169 Gigabit Ethernet" }, 168 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 169 "RealTek 8169S Single-chip Gigabit Ethernet" }, 170 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB, 171 "RealTek 8169SB Single-chip Gigabit Ethernet" }, 172 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 173 "RealTek 8110S Single-chip Gigabit Ethernet" }, 174 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 175 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 176 { 0, 0, 0, NULL } 177}; 178 179static struct rl_hwrev re_hwrevs[] = { 180 { RL_HWREV_8139, RL_8139, "" }, 181 { RL_HWREV_8139A, RL_8139, "A" }, 182 { RL_HWREV_8139AG, RL_8139, "A-G" }, 183 { RL_HWREV_8139B, RL_8139, "B" }, 184 { RL_HWREV_8130, RL_8139, "8130" }, 185 { RL_HWREV_8139C, RL_8139, "C" }, 186 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 187 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 188 { RL_HWREV_8169, RL_8169, "8169"}, 189 { RL_HWREV_8169S, RL_8169, "8169S"}, 190 { RL_HWREV_8169SB, RL_8169, "8169SB"}, 191 { RL_HWREV_8110S, RL_8169, "8110S"}, 192 { RL_HWREV_8100, RL_8139, "8100"}, 193 { RL_HWREV_8101, RL_8139, "8101"}, 194 { 0, 0, NULL } 195}; 196 197static int re_probe (device_t); 198static int re_attach (device_t); 199static int re_detach (device_t); 200 201static int re_encap (struct rl_softc *, struct mbuf **, int *); 202 203static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 204static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 205 bus_size_t, int); 206static int re_allocmem (device_t, struct rl_softc *); 207static int re_newbuf (struct rl_softc *, int, struct mbuf *); 208static int re_rx_list_init (struct rl_softc *); 209static int re_tx_list_init (struct rl_softc *); 210#ifdef RE_FIXUP_RX 211static __inline void re_fixup_rx 212 (struct mbuf *); 213#endif 214static void re_rxeof (struct rl_softc *); 215static void re_txeof (struct rl_softc *); 216#ifdef DEVICE_POLLING 217static void re_poll (struct ifnet *, enum poll_cmd, int); 218static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 219#endif 220static void re_intr (void *); 221static void re_tick (void *); 222static void re_start (struct ifnet *); 223static void re_start_locked (struct ifnet *); 224static int re_ioctl (struct ifnet *, u_long, caddr_t); 225static void re_init (void *); 226static void re_init_locked (struct rl_softc *); 227static void re_stop (struct rl_softc *); 228static void re_watchdog (struct ifnet *); 229static int re_suspend (device_t); 230static int re_resume (device_t); 231static void re_shutdown (device_t); 232static int re_ifmedia_upd (struct ifnet *); 233static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 234 235static void re_eeprom_putbyte (struct rl_softc *, int); 236static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 237static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 238static int re_gmii_readreg (device_t, int, int); 239static int re_gmii_writereg (device_t, int, int, int); 240 241static int re_miibus_readreg (device_t, int, int); 242static int re_miibus_writereg (device_t, int, int, int); 243static void re_miibus_statchg (device_t); 244 245static void re_setmulti (struct rl_softc *); 246static void re_reset (struct rl_softc *); 247 248static int re_diag (struct rl_softc *); 249 250#ifdef RE_USEIOSPACE 251#define RL_RES SYS_RES_IOPORT 252#define RL_RID RL_PCI_LOIO 253#else 254#define RL_RES SYS_RES_MEMORY 255#define RL_RID RL_PCI_LOMEM 256#endif 257 258static device_method_t re_methods[] = { 259 /* Device interface */ 260 DEVMETHOD(device_probe, re_probe), 261 DEVMETHOD(device_attach, re_attach), 262 DEVMETHOD(device_detach, re_detach), 263 DEVMETHOD(device_suspend, re_suspend), 264 DEVMETHOD(device_resume, re_resume), 265 DEVMETHOD(device_shutdown, re_shutdown), 266 267 /* bus interface */ 268 DEVMETHOD(bus_print_child, bus_generic_print_child), 269 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 270 271 /* MII interface */ 272 DEVMETHOD(miibus_readreg, re_miibus_readreg), 273 DEVMETHOD(miibus_writereg, re_miibus_writereg), 274 DEVMETHOD(miibus_statchg, re_miibus_statchg), 275 276 { 0, 0 } 277}; 278 279static driver_t re_driver = { 280 "re", 281 re_methods, 282 sizeof(struct rl_softc) 283}; 284 285static devclass_t re_devclass; 286 287DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 288DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 289DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 290 291#define EE_SET(x) \ 292 CSR_WRITE_1(sc, RL_EECMD, \ 293 CSR_READ_1(sc, RL_EECMD) | x) 294 295#define EE_CLR(x) \ 296 CSR_WRITE_1(sc, RL_EECMD, \ 297 CSR_READ_1(sc, RL_EECMD) & ~x) 298 299/* 300 * Send a read command and address to the EEPROM, check for ACK. 301 */ 302static void 303re_eeprom_putbyte(sc, addr) 304 struct rl_softc *sc; 305 int addr; 306{ 307 register int d, i; 308 309 d = addr | sc->rl_eecmd_read; 310 311 /* 312 * Feed in each bit and strobe the clock. 313 */ 314 for (i = 0x400; i; i >>= 1) { 315 if (d & i) { 316 EE_SET(RL_EE_DATAIN); 317 } else { 318 EE_CLR(RL_EE_DATAIN); 319 } 320 DELAY(100); 321 EE_SET(RL_EE_CLK); 322 DELAY(150); 323 EE_CLR(RL_EE_CLK); 324 DELAY(100); 325 } 326} 327 328/* 329 * Read a word of data stored in the EEPROM at address 'addr.' 330 */ 331static void 332re_eeprom_getword(sc, addr, dest) 333 struct rl_softc *sc; 334 int addr; 335 u_int16_t *dest; 336{ 337 register int i; 338 u_int16_t word = 0; 339 340 /* Enter EEPROM access mode. */ 341 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 342 343 /* 344 * Send address of word we want to read. 345 */ 346 re_eeprom_putbyte(sc, addr); 347 348 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 349 350 /* 351 * Start reading bits from EEPROM. 352 */ 353 for (i = 0x8000; i; i >>= 1) { 354 EE_SET(RL_EE_CLK); 355 DELAY(100); 356 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 357 word |= i; 358 EE_CLR(RL_EE_CLK); 359 DELAY(100); 360 } 361 362 /* Turn off EEPROM access mode. */ 363 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 364 365 *dest = word; 366} 367 368/* 369 * Read a sequence of words from the EEPROM. 370 */ 371static void 372re_read_eeprom(sc, dest, off, cnt, swap) 373 struct rl_softc *sc; 374 caddr_t dest; 375 int off; 376 int cnt; 377 int swap; 378{ 379 int i; 380 u_int16_t word = 0, *ptr; 381 382 for (i = 0; i < cnt; i++) { 383 re_eeprom_getword(sc, off + i, &word); 384 ptr = (u_int16_t *)(dest + (i * 2)); 385 if (swap) 386 *ptr = ntohs(word); 387 else 388 *ptr = word; 389 } 390} 391 392static int 393re_gmii_readreg(dev, phy, reg) 394 device_t dev; 395 int phy, reg; 396{ 397 struct rl_softc *sc; 398 u_int32_t rval; 399 int i; 400 401 if (phy != 1) 402 return (0); 403 404 sc = device_get_softc(dev); 405 406 /* Let the rgephy driver read the GMEDIASTAT register */ 407 408 if (reg == RL_GMEDIASTAT) { 409 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 410 return (rval); 411 } 412 413 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 414 DELAY(1000); 415 416 for (i = 0; i < RL_TIMEOUT; i++) { 417 rval = CSR_READ_4(sc, RL_PHYAR); 418 if (rval & RL_PHYAR_BUSY) 419 break; 420 DELAY(100); 421 } 422 423 if (i == RL_TIMEOUT) { 424 if_printf(sc->rl_ifp, "PHY read failed\n"); 425 return (0); 426 } 427 428 return (rval & RL_PHYAR_PHYDATA); 429} 430 431static int 432re_gmii_writereg(dev, phy, reg, data) 433 device_t dev; 434 int phy, reg, data; 435{ 436 struct rl_softc *sc; 437 u_int32_t rval; 438 int i; 439 440 sc = device_get_softc(dev); 441 442 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 443 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 444 DELAY(1000); 445 446 for (i = 0; i < RL_TIMEOUT; i++) { 447 rval = CSR_READ_4(sc, RL_PHYAR); 448 if (!(rval & RL_PHYAR_BUSY)) 449 break; 450 DELAY(100); 451 } 452 453 if (i == RL_TIMEOUT) { 454 if_printf(sc->rl_ifp, "PHY write failed\n"); 455 return (0); 456 } 457 458 return (0); 459} 460 461static int 462re_miibus_readreg(dev, phy, reg) 463 device_t dev; 464 int phy, reg; 465{ 466 struct rl_softc *sc; 467 u_int16_t rval = 0; 468 u_int16_t re8139_reg = 0; 469 470 sc = device_get_softc(dev); 471 472 if (sc->rl_type == RL_8169) { 473 rval = re_gmii_readreg(dev, phy, reg); 474 return (rval); 475 } 476 477 /* Pretend the internal PHY is only at address 0 */ 478 if (phy) { 479 return (0); 480 } 481 switch (reg) { 482 case MII_BMCR: 483 re8139_reg = RL_BMCR; 484 break; 485 case MII_BMSR: 486 re8139_reg = RL_BMSR; 487 break; 488 case MII_ANAR: 489 re8139_reg = RL_ANAR; 490 break; 491 case MII_ANER: 492 re8139_reg = RL_ANER; 493 break; 494 case MII_ANLPAR: 495 re8139_reg = RL_LPAR; 496 break; 497 case MII_PHYIDR1: 498 case MII_PHYIDR2: 499 return (0); 500 /* 501 * Allow the rlphy driver to read the media status 502 * register. If we have a link partner which does not 503 * support NWAY, this is the register which will tell 504 * us the results of parallel detection. 505 */ 506 case RL_MEDIASTAT: 507 rval = CSR_READ_1(sc, RL_MEDIASTAT); 508 return (rval); 509 default: 510 if_printf(sc->rl_ifp, "bad phy register\n"); 511 return (0); 512 } 513 rval = CSR_READ_2(sc, re8139_reg); 514 return (rval); 515} 516 517static int 518re_miibus_writereg(dev, phy, reg, data) 519 device_t dev; 520 int phy, reg, data; 521{ 522 struct rl_softc *sc; 523 u_int16_t re8139_reg = 0; 524 int rval = 0; 525 526 sc = device_get_softc(dev); 527 528 if (sc->rl_type == RL_8169) { 529 rval = re_gmii_writereg(dev, phy, reg, data); 530 return (rval); 531 } 532 533 /* Pretend the internal PHY is only at address 0 */ 534 if (phy) 535 return (0); 536 537 switch (reg) { 538 case MII_BMCR: 539 re8139_reg = RL_BMCR; 540 break; 541 case MII_BMSR: 542 re8139_reg = RL_BMSR; 543 break; 544 case MII_ANAR: 545 re8139_reg = RL_ANAR; 546 break; 547 case MII_ANER: 548 re8139_reg = RL_ANER; 549 break; 550 case MII_ANLPAR: 551 re8139_reg = RL_LPAR; 552 break; 553 case MII_PHYIDR1: 554 case MII_PHYIDR2: 555 return (0); 556 break; 557 default: 558 if_printf(sc->rl_ifp, "bad phy register\n"); 559 return (0); 560 } 561 CSR_WRITE_2(sc, re8139_reg, data); 562 return (0); 563} 564 565static void 566re_miibus_statchg(dev) 567 device_t dev; 568{ 569 570} 571 572/* 573 * Program the 64-bit multicast hash filter. 574 */ 575static void 576re_setmulti(sc) 577 struct rl_softc *sc; 578{ 579 struct ifnet *ifp; 580 int h = 0; 581 u_int32_t hashes[2] = { 0, 0 }; 582 struct ifmultiaddr *ifma; 583 u_int32_t rxfilt; 584 int mcnt = 0; 585 586 RL_LOCK_ASSERT(sc); 587 588 ifp = sc->rl_ifp; 589 590 rxfilt = CSR_READ_4(sc, RL_RXCFG); 591 592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 593 rxfilt |= RL_RXCFG_RX_MULTI; 594 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 595 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 596 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 597 return; 598 } 599 600 /* first, zot all the existing hash bits */ 601 CSR_WRITE_4(sc, RL_MAR0, 0); 602 CSR_WRITE_4(sc, RL_MAR4, 0); 603 604 /* now program new ones */ 605 IF_ADDR_LOCK(ifp); 606 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 607 if (ifma->ifma_addr->sa_family != AF_LINK) 608 continue; 609 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 610 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 611 if (h < 32) 612 hashes[0] |= (1 << h); 613 else 614 hashes[1] |= (1 << (h - 32)); 615 mcnt++; 616 } 617 IF_ADDR_UNLOCK(ifp); 618 619 if (mcnt) 620 rxfilt |= RL_RXCFG_RX_MULTI; 621 else 622 rxfilt &= ~RL_RXCFG_RX_MULTI; 623 624 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 625 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 626 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 627} 628 629static void 630re_reset(sc) 631 struct rl_softc *sc; 632{ 633 register int i; 634 635 RL_LOCK_ASSERT(sc); 636 637 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 638 639 for (i = 0; i < RL_TIMEOUT; i++) { 640 DELAY(10); 641 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 642 break; 643 } 644 if (i == RL_TIMEOUT) 645 if_printf(sc->rl_ifp, "reset never completed!\n"); 646 647 CSR_WRITE_1(sc, 0x82, 1); 648} 649 650/* 651 * The following routine is designed to test for a defect on some 652 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 653 * lines connected to the bus, however for a 32-bit only card, they 654 * should be pulled high. The result of this defect is that the 655 * NIC will not work right if you plug it into a 64-bit slot: DMA 656 * operations will be done with 64-bit transfers, which will fail 657 * because the 64-bit data lines aren't connected. 658 * 659 * There's no way to work around this (short of talking a soldering 660 * iron to the board), however we can detect it. The method we use 661 * here is to put the NIC into digital loopback mode, set the receiver 662 * to promiscuous mode, and then try to send a frame. We then compare 663 * the frame data we sent to what was received. If the data matches, 664 * then the NIC is working correctly, otherwise we know the user has 665 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 666 * slot. In the latter case, there's no way the NIC can work correctly, 667 * so we print out a message on the console and abort the device attach. 668 */ 669 670static int 671re_diag(sc) 672 struct rl_softc *sc; 673{ 674 struct ifnet *ifp = sc->rl_ifp; 675 struct mbuf *m0; 676 struct ether_header *eh; 677 struct rl_desc *cur_rx; 678 u_int16_t status; 679 u_int32_t rxstat; 680 int total_len, i, error = 0; 681 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 682 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 683 684 /* Allocate a single mbuf */ 685 MGETHDR(m0, M_DONTWAIT, MT_DATA); 686 if (m0 == NULL) 687 return (ENOBUFS); 688 689 RL_LOCK(sc); 690 691 /* 692 * Initialize the NIC in test mode. This sets the chip up 693 * so that it can send and receive frames, but performs the 694 * following special functions: 695 * - Puts receiver in promiscuous mode 696 * - Enables digital loopback mode 697 * - Leaves interrupts turned off 698 */ 699 700 ifp->if_flags |= IFF_PROMISC; 701 sc->rl_testmode = 1; 702 re_init_locked(sc); 703 re_stop(sc); 704 DELAY(100000); 705 re_init_locked(sc); 706 707 /* Put some data in the mbuf */ 708 709 eh = mtod(m0, struct ether_header *); 710 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 711 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 712 eh->ether_type = htons(ETHERTYPE_IP); 713 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 714 715 /* 716 * Queue the packet, start transmission. 717 * Note: IF_HANDOFF() ultimately calls re_start() for us. 718 */ 719 720 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 721 RL_UNLOCK(sc); 722 /* XXX: re_diag must not be called when in ALTQ mode */ 723 IF_HANDOFF(&ifp->if_snd, m0, ifp); 724 RL_LOCK(sc); 725 m0 = NULL; 726 727 /* Wait for it to propagate through the chip */ 728 729 DELAY(100000); 730 for (i = 0; i < RL_TIMEOUT; i++) { 731 status = CSR_READ_2(sc, RL_ISR); 732 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 733 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 734 break; 735 DELAY(10); 736 } 737 738 if (i == RL_TIMEOUT) { 739 if_printf(ifp, "diagnostic failed, failed to receive packet " 740 "in loopback mode\n"); 741 error = EIO; 742 goto done; 743 } 744 745 /* 746 * The packet should have been dumped into the first 747 * entry in the RX DMA ring. Grab it from there. 748 */ 749 750 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 751 sc->rl_ldata.rl_rx_list_map, 752 BUS_DMASYNC_POSTREAD); 753 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 754 sc->rl_ldata.rl_rx_dmamap[0], 755 BUS_DMASYNC_POSTWRITE); 756 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 757 sc->rl_ldata.rl_rx_dmamap[0]); 758 759 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 760 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 761 eh = mtod(m0, struct ether_header *); 762 763 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 764 total_len = RL_RXBYTES(cur_rx); 765 rxstat = le32toh(cur_rx->rl_cmdstat); 766 767 if (total_len != ETHER_MIN_LEN) { 768 if_printf(ifp, "diagnostic failed, received short packet\n"); 769 error = EIO; 770 goto done; 771 } 772 773 /* Test that the received packet data matches what we sent. */ 774 775 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 776 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 777 ntohs(eh->ether_type) != ETHERTYPE_IP) { 778 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 779 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 780 dst, ":", src, ":", ETHERTYPE_IP); 781 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 782 eh->ether_dhost, ":", eh->ether_shost, ":", 783 ntohs(eh->ether_type)); 784 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 785 "into a 64-bit PCI slot.\n"); 786 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 787 "for proper operation.\n"); 788 if_printf(ifp, "Read the re(4) man page for more details.\n"); 789 error = EIO; 790 } 791 792done: 793 /* Turn interface off, release resources */ 794 795 sc->rl_testmode = 0; 796 ifp->if_flags &= ~IFF_PROMISC; 797 re_stop(sc); 798 if (m0 != NULL) 799 m_freem(m0); 800 801 RL_UNLOCK(sc); 802 803 return (error); 804} 805 806/* 807 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 808 * IDs against our list and return a device name if we find a match. 809 */ 810static int 811re_probe(dev) 812 device_t dev; 813{ 814 struct rl_type *t; 815 struct rl_softc *sc; 816 int rid; 817 u_int32_t hwrev; 818 819 t = re_devs; 820 sc = device_get_softc(dev); 821 822 while (t->rl_name != NULL) { 823 if ((pci_get_vendor(dev) == t->rl_vid) && 824 (pci_get_device(dev) == t->rl_did)) { 825 826 /* 827 * Temporarily map the I/O space 828 * so we can read the chip ID register. 829 */ 830 rid = RL_RID; 831 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 832 RF_ACTIVE); 833 if (sc->rl_res == NULL) { 834 device_printf(dev, 835 "couldn't map ports/memory\n"); 836 return (ENXIO); 837 } 838 sc->rl_btag = rman_get_bustag(sc->rl_res); 839 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 840 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 841 bus_release_resource(dev, RL_RES, 842 RL_RID, sc->rl_res); 843 if (t->rl_basetype == hwrev) { 844 device_set_desc(dev, t->rl_name); 845 return (BUS_PROBE_DEFAULT); 846 } 847 } 848 t++; 849 } 850 851 return (ENXIO); 852} 853 854/* 855 * This routine takes the segment list provided as the result of 856 * a bus_dma_map_load() operation and assigns the addresses/lengths 857 * to RealTek DMA descriptors. This can be called either by the RX 858 * code or the TX code. In the RX case, we'll probably wind up mapping 859 * at most one segment. For the TX case, there could be any number of 860 * segments since TX packets may span multiple mbufs. In either case, 861 * if the number of segments is larger than the rl_maxsegs limit 862 * specified by the caller, we abort the mapping operation. Sadly, 863 * whoever designed the buffer mapping API did not provide a way to 864 * return an error from here, so we have to fake it a bit. 865 */ 866 867static void 868re_dma_map_desc(arg, segs, nseg, mapsize, error) 869 void *arg; 870 bus_dma_segment_t *segs; 871 int nseg; 872 bus_size_t mapsize; 873 int error; 874{ 875 struct rl_dmaload_arg *ctx; 876 struct rl_desc *d = NULL; 877 int i = 0, idx; 878 879 if (error) 880 return; 881 882 ctx = arg; 883 884 /* Signal error to caller if there's too many segments */ 885 if (nseg > ctx->rl_maxsegs) { 886 ctx->rl_maxsegs = 0; 887 return; 888 } 889 890 /* 891 * Map the segment array into descriptors. Note that we set the 892 * start-of-frame and end-of-frame markers for either TX or RX, but 893 * they really only have meaning in the TX case. (In the RX case, 894 * it's the chip that tells us where packets begin and end.) 895 * We also keep track of the end of the ring and set the 896 * end-of-ring bits as needed, and we set the ownership bits 897 * in all except the very first descriptor. (The caller will 898 * set this descriptor later when it start transmission or 899 * reception.) 900 */ 901 idx = ctx->rl_idx; 902 for (;;) { 903 u_int32_t cmdstat; 904 d = &ctx->rl_ring[idx]; 905 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 906 ctx->rl_maxsegs = 0; 907 return; 908 } 909 cmdstat = segs[i].ds_len; 910 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 911 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 912 if (i == 0) 913 cmdstat |= RL_TDESC_CMD_SOF; 914 else 915 cmdstat |= RL_TDESC_CMD_OWN; 916 if (idx == (RL_RX_DESC_CNT - 1)) 917 cmdstat |= RL_TDESC_CMD_EOR; 918 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 919 i++; 920 if (i == nseg) 921 break; 922 RL_DESC_INC(idx); 923 } 924 925 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 926 ctx->rl_maxsegs = nseg; 927 ctx->rl_idx = idx; 928} 929 930/* 931 * Map a single buffer address. 932 */ 933 934static void 935re_dma_map_addr(arg, segs, nseg, error) 936 void *arg; 937 bus_dma_segment_t *segs; 938 int nseg; 939 int error; 940{ 941 bus_addr_t *addr; 942 943 if (error) 944 return; 945 946 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 947 addr = arg; 948 *addr = segs->ds_addr; 949} 950 951static int 952re_allocmem(dev, sc) 953 device_t dev; 954 struct rl_softc *sc; 955{ 956 int error; 957 int nseg; 958 int i; 959 960 /* 961 * Allocate map for RX mbufs. 962 */ 963 nseg = 32; 964 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 965 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 966 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 967 NULL, NULL, &sc->rl_ldata.rl_mtag); 968 if (error) { 969 device_printf(dev, "could not allocate dma tag\n"); 970 return (ENOMEM); 971 } 972 973 /* 974 * Allocate map for TX descriptor list. 975 */ 976 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 977 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 978 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 979 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 980 if (error) { 981 device_printf(dev, "could not allocate dma tag\n"); 982 return (ENOMEM); 983 } 984 985 /* Allocate DMA'able memory for the TX ring */ 986 987 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 988 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 989 &sc->rl_ldata.rl_tx_list_map); 990 if (error) 991 return (ENOMEM); 992 993 /* Load the map for the TX ring. */ 994 995 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 996 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 997 RL_TX_LIST_SZ, re_dma_map_addr, 998 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 999 1000 /* Create DMA maps for TX buffers */ 1001 1002 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1003 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1004 &sc->rl_ldata.rl_tx_dmamap[i]); 1005 if (error) { 1006 device_printf(dev, "can't create DMA map for TX\n"); 1007 return (ENOMEM); 1008 } 1009 } 1010 1011 /* 1012 * Allocate map for RX descriptor list. 1013 */ 1014 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1015 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1016 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1017 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1018 if (error) { 1019 device_printf(dev, "could not allocate dma tag\n"); 1020 return (ENOMEM); 1021 } 1022 1023 /* Allocate DMA'able memory for the RX ring */ 1024 1025 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1026 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1027 &sc->rl_ldata.rl_rx_list_map); 1028 if (error) 1029 return (ENOMEM); 1030 1031 /* Load the map for the RX ring. */ 1032 1033 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1034 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1035 RL_RX_LIST_SZ, re_dma_map_addr, 1036 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1037 1038 /* Create DMA maps for RX buffers */ 1039 1040 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1041 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1042 &sc->rl_ldata.rl_rx_dmamap[i]); 1043 if (error) { 1044 device_printf(dev, "can't create DMA map for RX\n"); 1045 return (ENOMEM); 1046 } 1047 } 1048 1049 return (0); 1050} 1051 1052/* 1053 * Attach the interface. Allocate softc structures, do ifmedia 1054 * setup and ethernet/BPF attach. 1055 */ 1056static int 1057re_attach(dev) 1058 device_t dev; 1059{ 1060 u_char eaddr[ETHER_ADDR_LEN]; 1061 u_int16_t as[3]; 1062 struct rl_softc *sc; 1063 struct ifnet *ifp; 1064 struct rl_hwrev *hw_rev; 1065 int hwrev; 1066 u_int16_t re_did = 0; 1067 int error = 0, rid, i; 1068 1069 sc = device_get_softc(dev); 1070 1071 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1072 MTX_DEF); 1073 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1074 1075 /* 1076 * Map control/status registers. 1077 */ 1078 pci_enable_busmaster(dev); 1079 1080 rid = RL_RID; 1081 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1082 RF_ACTIVE); 1083 1084 if (sc->rl_res == NULL) { 1085 device_printf(dev, "couldn't map ports/memory\n"); 1086 error = ENXIO; 1087 goto fail; 1088 } 1089 1090 sc->rl_btag = rman_get_bustag(sc->rl_res); 1091 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1092 1093 /* Allocate interrupt */ 1094 rid = 0; 1095 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1096 RF_SHAREABLE | RF_ACTIVE); 1097 1098 if (sc->rl_irq == NULL) { 1099 device_printf(dev, "couldn't map interrupt\n"); 1100 error = ENXIO; 1101 goto fail; 1102 } 1103 1104 /* Reset the adapter. */ 1105 RL_LOCK(sc); 1106 re_reset(sc); 1107 RL_UNLOCK(sc); 1108 1109 hw_rev = re_hwrevs; 1110 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1111 while (hw_rev->rl_desc != NULL) { 1112 if (hw_rev->rl_rev == hwrev) { 1113 sc->rl_type = hw_rev->rl_type; 1114 break; 1115 } 1116 hw_rev++; 1117 } 1118 1119 if (sc->rl_type == RL_8169) { 1120 1121 /* Set RX length mask */ 1122 1123 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1124 1125 /* Force station address autoload from the EEPROM */ 1126 1127 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1128 for (i = 0; i < RL_TIMEOUT; i++) { 1129 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1130 break; 1131 DELAY(100); 1132 } 1133 if (i == RL_TIMEOUT) 1134 device_printf(dev, "eeprom autoload timed out\n"); 1135 1136 for (i = 0; i < ETHER_ADDR_LEN; i++) 1137 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1138 } else { 1139 1140 /* Set RX length mask */ 1141 1142 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1143 1144 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1145 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1146 if (re_did != 0x8129) 1147 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1148 1149 /* 1150 * Get station address from the EEPROM. 1151 */ 1152 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1153 for (i = 0; i < 3; i++) { 1154 eaddr[(i * 2) + 0] = as[i] & 0xff; 1155 eaddr[(i * 2) + 1] = as[i] >> 8; 1156 } 1157 } 1158 1159 /* 1160 * Allocate the parent bus DMA tag appropriate for PCI. 1161 */ 1162#define RL_NSEG_NEW 32 1163 error = bus_dma_tag_create(NULL, /* parent */ 1164 1, 0, /* alignment, boundary */ 1165 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1166 BUS_SPACE_MAXADDR, /* highaddr */ 1167 NULL, NULL, /* filter, filterarg */ 1168 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1169 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1170 BUS_DMA_ALLOCNOW, /* flags */ 1171 NULL, NULL, /* lockfunc, lockarg */ 1172 &sc->rl_parent_tag); 1173 if (error) 1174 goto fail; 1175 1176 error = re_allocmem(dev, sc); 1177 1178 if (error) 1179 goto fail; 1180 1181 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1182 if (ifp == NULL) { 1183 device_printf(dev, "can not if_alloc()\n"); 1184 error = ENOSPC; 1185 goto fail; 1186 } 1187 1188 /* Do MII setup */ 1189 if (mii_phy_probe(dev, &sc->rl_miibus, 1190 re_ifmedia_upd, re_ifmedia_sts)) { 1191 device_printf(dev, "MII without any phy!\n"); 1192 error = ENXIO; 1193 goto fail; 1194 } 1195 1196 ifp->if_softc = sc; 1197 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1198 ifp->if_mtu = ETHERMTU; 1199 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1200 ifp->if_ioctl = re_ioctl; 1201 ifp->if_capabilities = IFCAP_VLAN_MTU; 1202 ifp->if_start = re_start; 1203 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0; 1204 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1205 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1206#ifdef DEVICE_POLLING 1207 ifp->if_capabilities |= IFCAP_POLLING; 1208#endif 1209 ifp->if_watchdog = re_watchdog; 1210 ifp->if_init = re_init; 1211 if (sc->rl_type == RL_8169) 1212 ifp->if_baudrate = 1000000000; 1213 else 1214 ifp->if_baudrate = 100000000; 1215 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1216 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1217 IFQ_SET_READY(&ifp->if_snd); 1218 1219 /* 1220 * Call MI attach routine. 1221 */ 1222 ether_ifattach(ifp, eaddr); 1223 1224 /* Perform hardware diagnostic. */ 1225 error = re_diag(sc); 1226 1227 if (error) { 1228 device_printf(dev, "attach aborted due to hardware diag failure\n"); 1229 ether_ifdetach(ifp); 1230 goto fail; 1231 } 1232 1233 /* Hook interrupt last to avoid having to lock softc */ 1234 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1235 re_intr, sc, &sc->rl_intrhand); 1236 if (error) { 1237 device_printf(dev, "couldn't set up irq\n"); 1238 ether_ifdetach(ifp); 1239 } 1240 1241fail: 1242 if (error) 1243 re_detach(dev); 1244 1245 return (error); 1246} 1247 1248/* 1249 * Shutdown hardware and free up resources. This can be called any 1250 * time after the mutex has been initialized. It is called in both 1251 * the error case in attach and the normal detach case so it needs 1252 * to be careful about only freeing resources that have actually been 1253 * allocated. 1254 */ 1255static int 1256re_detach(dev) 1257 device_t dev; 1258{ 1259 struct rl_softc *sc; 1260 struct ifnet *ifp; 1261 int i; 1262 1263 sc = device_get_softc(dev); 1264 ifp = sc->rl_ifp; 1265 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1266 1267#ifdef DEVICE_POLLING 1268 if (ifp->if_capenable & IFCAP_POLLING) 1269 ether_poll_deregister(ifp); 1270#endif 1271 1272 /* These should only be active if attach succeeded */ 1273 if (device_is_attached(dev)) { 1274 RL_LOCK(sc); 1275#if 0 1276 sc->suspended = 1; 1277#endif 1278 re_stop(sc); 1279 RL_UNLOCK(sc); 1280 callout_drain(&sc->rl_stat_callout); 1281 /* 1282 * Force off the IFF_UP flag here, in case someone 1283 * still had a BPF descriptor attached to this 1284 * interface. If they do, ether_ifdetach() will cause 1285 * the BPF code to try and clear the promisc mode 1286 * flag, which will bubble down to re_ioctl(), 1287 * which will try to call re_init() again. This will 1288 * turn the NIC back on and restart the MII ticker, 1289 * which will panic the system when the kernel tries 1290 * to invoke the re_tick() function that isn't there 1291 * anymore. 1292 */ 1293 ifp->if_flags &= ~IFF_UP; 1294 ether_ifdetach(ifp); 1295 } 1296 if (sc->rl_miibus) 1297 device_delete_child(dev, sc->rl_miibus); 1298 bus_generic_detach(dev); 1299 1300 /* 1301 * The rest is resource deallocation, so we should already be 1302 * stopped here. 1303 */ 1304 1305 if (sc->rl_intrhand) 1306 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1307 if (ifp != NULL) 1308 if_free(ifp); 1309 if (sc->rl_irq) 1310 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1311 if (sc->rl_res) 1312 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1313 1314 1315 /* Unload and free the RX DMA ring memory and map */ 1316 1317 if (sc->rl_ldata.rl_rx_list_tag) { 1318 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1319 sc->rl_ldata.rl_rx_list_map); 1320 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1321 sc->rl_ldata.rl_rx_list, 1322 sc->rl_ldata.rl_rx_list_map); 1323 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1324 } 1325 1326 /* Unload and free the TX DMA ring memory and map */ 1327 1328 if (sc->rl_ldata.rl_tx_list_tag) { 1329 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1330 sc->rl_ldata.rl_tx_list_map); 1331 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1332 sc->rl_ldata.rl_tx_list, 1333 sc->rl_ldata.rl_tx_list_map); 1334 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1335 } 1336 1337 /* Destroy all the RX and TX buffer maps */ 1338 1339 if (sc->rl_ldata.rl_mtag) { 1340 for (i = 0; i < RL_TX_DESC_CNT; i++) 1341 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1342 sc->rl_ldata.rl_tx_dmamap[i]); 1343 for (i = 0; i < RL_RX_DESC_CNT; i++) 1344 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1345 sc->rl_ldata.rl_rx_dmamap[i]); 1346 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1347 } 1348 1349 /* Unload and free the stats buffer and map */ 1350 1351 if (sc->rl_ldata.rl_stag) { 1352 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1353 sc->rl_ldata.rl_rx_list_map); 1354 bus_dmamem_free(sc->rl_ldata.rl_stag, 1355 sc->rl_ldata.rl_stats, 1356 sc->rl_ldata.rl_smap); 1357 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1358 } 1359 1360 if (sc->rl_parent_tag) 1361 bus_dma_tag_destroy(sc->rl_parent_tag); 1362 1363 mtx_destroy(&sc->rl_mtx); 1364 1365 return (0); 1366} 1367 1368static int 1369re_newbuf(sc, idx, m) 1370 struct rl_softc *sc; 1371 int idx; 1372 struct mbuf *m; 1373{ 1374 struct rl_dmaload_arg arg; 1375 struct mbuf *n = NULL; 1376 int error; 1377 1378 if (m == NULL) { 1379 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1380 if (n == NULL) 1381 return (ENOBUFS); 1382 m = n; 1383 } else 1384 m->m_data = m->m_ext.ext_buf; 1385 1386 m->m_len = m->m_pkthdr.len = MCLBYTES; 1387#ifdef RE_FIXUP_RX 1388 /* 1389 * This is part of an evil trick to deal with non-x86 platforms. 1390 * The RealTek chip requires RX buffers to be aligned on 64-bit 1391 * boundaries, but that will hose non-x86 machines. To get around 1392 * this, we leave some empty space at the start of each buffer 1393 * and for non-x86 hosts, we copy the buffer back six bytes 1394 * to achieve word alignment. This is slightly more efficient 1395 * than allocating a new buffer, copying the contents, and 1396 * discarding the old buffer. 1397 */ 1398 m_adj(m, RE_ETHER_ALIGN); 1399#endif 1400 arg.sc = sc; 1401 arg.rl_idx = idx; 1402 arg.rl_maxsegs = 1; 1403 arg.rl_flags = 0; 1404 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1405 1406 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1407 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1408 &arg, BUS_DMA_NOWAIT); 1409 if (error || arg.rl_maxsegs != 1) { 1410 if (n != NULL) 1411 m_freem(n); 1412 return (ENOMEM); 1413 } 1414 1415 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1416 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1417 1418 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1419 sc->rl_ldata.rl_rx_dmamap[idx], 1420 BUS_DMASYNC_PREREAD); 1421 1422 return (0); 1423} 1424 1425#ifdef RE_FIXUP_RX 1426static __inline void 1427re_fixup_rx(m) 1428 struct mbuf *m; 1429{ 1430 int i; 1431 uint16_t *src, *dst; 1432 1433 src = mtod(m, uint16_t *); 1434 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1435 1436 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1437 *dst++ = *src++; 1438 1439 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1440 1441 return; 1442} 1443#endif 1444 1445static int 1446re_tx_list_init(sc) 1447 struct rl_softc *sc; 1448{ 1449 1450 RL_LOCK_ASSERT(sc); 1451 1452 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1453 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1454 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1455 1456 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1457 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1458 sc->rl_ldata.rl_tx_prodidx = 0; 1459 sc->rl_ldata.rl_tx_considx = 0; 1460 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1461 1462 return (0); 1463} 1464 1465static int 1466re_rx_list_init(sc) 1467 struct rl_softc *sc; 1468{ 1469 int i; 1470 1471 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1472 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1473 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1474 1475 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1476 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1477 return (ENOBUFS); 1478 } 1479 1480 /* Flush the RX descriptors */ 1481 1482 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1483 sc->rl_ldata.rl_rx_list_map, 1484 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1485 1486 sc->rl_ldata.rl_rx_prodidx = 0; 1487 sc->rl_head = sc->rl_tail = NULL; 1488 1489 return (0); 1490} 1491 1492/* 1493 * RX handler for C+ and 8169. For the gigE chips, we support 1494 * the reception of jumbo frames that have been fragmented 1495 * across multiple 2K mbuf cluster buffers. 1496 */ 1497static void 1498re_rxeof(sc) 1499 struct rl_softc *sc; 1500{ 1501 struct mbuf *m; 1502 struct ifnet *ifp; 1503 int i, total_len; 1504 struct rl_desc *cur_rx; 1505 u_int32_t rxstat, rxvlan; 1506 1507 RL_LOCK_ASSERT(sc); 1508 1509 ifp = sc->rl_ifp; 1510 i = sc->rl_ldata.rl_rx_prodidx; 1511 1512 /* Invalidate the descriptor memory */ 1513 1514 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1515 sc->rl_ldata.rl_rx_list_map, 1516 BUS_DMASYNC_POSTREAD); 1517 1518 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1519 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1520 m = sc->rl_ldata.rl_rx_mbuf[i]; 1521 total_len = RL_RXBYTES(cur_rx); 1522 rxstat = le32toh(cur_rx->rl_cmdstat); 1523 rxvlan = le32toh(cur_rx->rl_vlanctl); 1524 1525 /* Invalidate the RX mbuf and unload its map */ 1526 1527 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1528 sc->rl_ldata.rl_rx_dmamap[i], 1529 BUS_DMASYNC_POSTWRITE); 1530 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1531 sc->rl_ldata.rl_rx_dmamap[i]); 1532 1533 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1534 m->m_len = RE_RX_DESC_BUFLEN; 1535 if (sc->rl_head == NULL) 1536 sc->rl_head = sc->rl_tail = m; 1537 else { 1538 m->m_flags &= ~M_PKTHDR; 1539 sc->rl_tail->m_next = m; 1540 sc->rl_tail = m; 1541 } 1542 re_newbuf(sc, i, NULL); 1543 RL_DESC_INC(i); 1544 continue; 1545 } 1546 1547 /* 1548 * NOTE: for the 8139C+, the frame length field 1549 * is always 12 bits in size, but for the gigE chips, 1550 * it is 13 bits (since the max RX frame length is 16K). 1551 * Unfortunately, all 32 bits in the status word 1552 * were already used, so to make room for the extra 1553 * length bit, RealTek took out the 'frame alignment 1554 * error' bit and shifted the other status bits 1555 * over one slot. The OWN, EOR, FS and LS bits are 1556 * still in the same places. We have already extracted 1557 * the frame length and checked the OWN bit, so rather 1558 * than using an alternate bit mapping, we shift the 1559 * status bits one space to the right so we can evaluate 1560 * them using the 8169 status as though it was in the 1561 * same format as that of the 8139C+. 1562 */ 1563 if (sc->rl_type == RL_8169) 1564 rxstat >>= 1; 1565 1566 /* 1567 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1568 * set, but if CRC is clear, it will still be a valid frame. 1569 */ 1570 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1571 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1572 ifp->if_ierrors++; 1573 /* 1574 * If this is part of a multi-fragment packet, 1575 * discard all the pieces. 1576 */ 1577 if (sc->rl_head != NULL) { 1578 m_freem(sc->rl_head); 1579 sc->rl_head = sc->rl_tail = NULL; 1580 } 1581 re_newbuf(sc, i, m); 1582 RL_DESC_INC(i); 1583 continue; 1584 } 1585 1586 /* 1587 * If allocating a replacement mbuf fails, 1588 * reload the current one. 1589 */ 1590 1591 if (re_newbuf(sc, i, NULL)) { 1592 ifp->if_ierrors++; 1593 if (sc->rl_head != NULL) { 1594 m_freem(sc->rl_head); 1595 sc->rl_head = sc->rl_tail = NULL; 1596 } 1597 re_newbuf(sc, i, m); 1598 RL_DESC_INC(i); 1599 continue; 1600 } 1601 1602 RL_DESC_INC(i); 1603 1604 if (sc->rl_head != NULL) { 1605 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1606 if (m->m_len == 0) 1607 m->m_len = RE_RX_DESC_BUFLEN; 1608 /* 1609 * Special case: if there's 4 bytes or less 1610 * in this buffer, the mbuf can be discarded: 1611 * the last 4 bytes is the CRC, which we don't 1612 * care about anyway. 1613 */ 1614 if (m->m_len <= ETHER_CRC_LEN) { 1615 sc->rl_tail->m_len -= 1616 (ETHER_CRC_LEN - m->m_len); 1617 m_freem(m); 1618 } else { 1619 m->m_len -= ETHER_CRC_LEN; 1620 m->m_flags &= ~M_PKTHDR; 1621 sc->rl_tail->m_next = m; 1622 } 1623 m = sc->rl_head; 1624 sc->rl_head = sc->rl_tail = NULL; 1625 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1626 } else 1627 m->m_pkthdr.len = m->m_len = 1628 (total_len - ETHER_CRC_LEN); 1629 1630#ifdef RE_FIXUP_RX 1631 re_fixup_rx(m); 1632#endif 1633 ifp->if_ipackets++; 1634 m->m_pkthdr.rcvif = ifp; 1635 1636 /* Do RX checksumming if enabled */ 1637 1638 if (ifp->if_capenable & IFCAP_RXCSUM) { 1639 1640 /* Check IP header checksum */ 1641 if (rxstat & RL_RDESC_STAT_PROTOID) 1642 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1643 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1644 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1645 1646 /* Check TCP/UDP checksum */ 1647 if ((RL_TCPPKT(rxstat) && 1648 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1649 (RL_UDPPKT(rxstat) && 1650 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1651 m->m_pkthdr.csum_flags |= 1652 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1653 m->m_pkthdr.csum_data = 0xffff; 1654 } 1655 } 1656 1657 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1658 VLAN_INPUT_TAG(ifp, m, 1659 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1660 RL_UNLOCK(sc); 1661 (*ifp->if_input)(ifp, m); 1662 RL_LOCK(sc); 1663 } 1664 1665 /* Flush the RX DMA ring */ 1666 1667 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1668 sc->rl_ldata.rl_rx_list_map, 1669 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1670 1671 sc->rl_ldata.rl_rx_prodidx = i; 1672} 1673 1674static void 1675re_txeof(sc) 1676 struct rl_softc *sc; 1677{ 1678 struct ifnet *ifp; 1679 u_int32_t txstat; 1680 int idx; 1681 1682 ifp = sc->rl_ifp; 1683 idx = sc->rl_ldata.rl_tx_considx; 1684 1685 /* Invalidate the TX descriptor list */ 1686 1687 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1688 sc->rl_ldata.rl_tx_list_map, 1689 BUS_DMASYNC_POSTREAD); 1690 1691 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1692 1693 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1694 if (txstat & RL_TDESC_CMD_OWN) 1695 break; 1696 1697 /* 1698 * We only stash mbufs in the last descriptor 1699 * in a fragment chain, which also happens to 1700 * be the only place where the TX status bits 1701 * are valid. 1702 */ 1703 1704 if (txstat & RL_TDESC_CMD_EOF) { 1705 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1706 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1707 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1708 sc->rl_ldata.rl_tx_dmamap[idx]); 1709 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1710 RL_TDESC_STAT_COLCNT)) 1711 ifp->if_collisions++; 1712 if (txstat & RL_TDESC_STAT_TXERRSUM) 1713 ifp->if_oerrors++; 1714 else 1715 ifp->if_opackets++; 1716 } 1717 sc->rl_ldata.rl_tx_free++; 1718 RL_DESC_INC(idx); 1719 } 1720 1721 /* No changes made to the TX ring, so no flush needed */ 1722 1723 if (idx != sc->rl_ldata.rl_tx_considx) { 1724 sc->rl_ldata.rl_tx_considx = idx; 1725 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1726 ifp->if_timer = 0; 1727 } 1728 1729 /* 1730 * If not all descriptors have been released reaped yet, 1731 * reload the timer so that we will eventually get another 1732 * interrupt that will cause us to re-enter this routine. 1733 * This is done in case the transmitter has gone idle. 1734 */ 1735 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1736 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1737} 1738 1739static void 1740re_tick(xsc) 1741 void *xsc; 1742{ 1743 struct rl_softc *sc; 1744 struct mii_data *mii; 1745 1746 sc = xsc; 1747 1748 RL_LOCK_ASSERT(sc); 1749 1750 mii = device_get_softc(sc->rl_miibus); 1751 1752 mii_tick(mii); 1753 1754 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1755} 1756 1757#ifdef DEVICE_POLLING 1758static void 1759re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1760{ 1761 struct rl_softc *sc = ifp->if_softc; 1762 1763 RL_LOCK(sc); 1764 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1765 re_poll_locked(ifp, cmd, count); 1766 RL_UNLOCK(sc); 1767} 1768 1769static void 1770re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1771{ 1772 struct rl_softc *sc = ifp->if_softc; 1773 1774 RL_LOCK_ASSERT(sc); 1775 1776 sc->rxcycles = count; 1777 re_rxeof(sc); 1778 re_txeof(sc); 1779 1780 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1781 re_start_locked(ifp); 1782 1783 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1784 u_int16_t status; 1785 1786 status = CSR_READ_2(sc, RL_ISR); 1787 if (status == 0xffff) 1788 return; 1789 if (status) 1790 CSR_WRITE_2(sc, RL_ISR, status); 1791 1792 /* 1793 * XXX check behaviour on receiver stalls. 1794 */ 1795 1796 if (status & RL_ISR_SYSTEM_ERR) { 1797 re_reset(sc); 1798 re_init_locked(sc); 1799 } 1800 } 1801} 1802#endif /* DEVICE_POLLING */ 1803 1804static void 1805re_intr(arg) 1806 void *arg; 1807{ 1808 struct rl_softc *sc; 1809 struct ifnet *ifp; 1810 u_int16_t status; 1811 1812 sc = arg; 1813 1814 RL_LOCK(sc); 1815 1816 ifp = sc->rl_ifp; 1817 1818 if (sc->suspended || !(ifp->if_flags & IFF_UP)) 1819 goto done_locked; 1820 1821#ifdef DEVICE_POLLING 1822 if (ifp->if_capenable & IFCAP_POLLING) 1823 goto done_locked; 1824#endif 1825 1826 for (;;) { 1827 1828 status = CSR_READ_2(sc, RL_ISR); 1829 /* If the card has gone away the read returns 0xffff. */ 1830 if (status == 0xffff) 1831 break; 1832 if (status) 1833 CSR_WRITE_2(sc, RL_ISR, status); 1834 1835 if ((status & RL_INTRS_CPLUS) == 0) 1836 break; 1837 1838 if ((status & RL_ISR_RX_OK) || 1839 (status & RL_ISR_RX_ERR)) 1840 re_rxeof(sc); 1841 1842 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1843 (status & RL_ISR_TX_ERR) || 1844 (status & RL_ISR_TX_DESC_UNAVAIL)) 1845 re_txeof(sc); 1846 1847 if (status & RL_ISR_SYSTEM_ERR) { 1848 re_reset(sc); 1849 re_init_locked(sc); 1850 } 1851 1852 if (status & RL_ISR_LINKCHG) { 1853 callout_stop(&sc->rl_stat_callout); 1854 re_tick(sc); 1855 } 1856 } 1857 1858 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1859 re_start_locked(ifp); 1860 1861done_locked: 1862 RL_UNLOCK(sc); 1863} 1864 1865static int 1866re_encap(sc, m_head, idx) 1867 struct rl_softc *sc; 1868 struct mbuf **m_head; 1869 int *idx; 1870{ 1871 struct mbuf *m_new = NULL; 1872 struct rl_dmaload_arg arg; 1873 bus_dmamap_t map; 1874 int error; 1875 struct m_tag *mtag; 1876 1877 RL_LOCK_ASSERT(sc); 1878 1879 if (sc->rl_ldata.rl_tx_free <= 4) 1880 return (EFBIG); 1881 1882 /* 1883 * Set up checksum offload. Note: checksum offload bits must 1884 * appear in all descriptors of a multi-descriptor transmit 1885 * attempt. This is according to testing done with an 8169 1886 * chip. This is a requirement. 1887 */ 1888 1889 arg.rl_flags = 0; 1890 1891 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1892 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1893 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1894 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1895 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1896 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1897 1898 arg.sc = sc; 1899 arg.rl_idx = *idx; 1900 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1901 if (arg.rl_maxsegs > 4) 1902 arg.rl_maxsegs -= 4; 1903 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1904 1905 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1906 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1907 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1908 1909 if (error && error != EFBIG) { 1910 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", error); 1911 return (ENOBUFS); 1912 } 1913 1914 /* Too many segments to map, coalesce into a single mbuf */ 1915 1916 if (error || arg.rl_maxsegs == 0) { 1917 m_new = m_defrag(*m_head, M_DONTWAIT); 1918 if (m_new == NULL) 1919 return (ENOBUFS); 1920 else 1921 *m_head = m_new; 1922 1923 arg.sc = sc; 1924 arg.rl_idx = *idx; 1925 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1926 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1927 1928 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1929 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1930 if (error) { 1931 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", 1932 error); 1933 return (EFBIG); 1934 } 1935 } 1936 1937 /* 1938 * Insure that the map for this transmission 1939 * is placed at the array index of the last descriptor 1940 * in this chain. (Swap last and first dmamaps.) 1941 */ 1942 sc->rl_ldata.rl_tx_dmamap[*idx] = 1943 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1944 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1945 1946 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 1947 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1948 1949 /* 1950 * Set up hardware VLAN tagging. Note: vlan tag info must 1951 * appear in the first descriptor of a multi-descriptor 1952 * transmission attempt. 1953 */ 1954 1955 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head); 1956 if (mtag != NULL) 1957 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1958 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1959 1960 /* Transfer ownership of packet to the chip. */ 1961 1962 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1963 htole32(RL_TDESC_CMD_OWN); 1964 if (*idx != arg.rl_idx) 1965 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1966 htole32(RL_TDESC_CMD_OWN); 1967 1968 RL_DESC_INC(arg.rl_idx); 1969 *idx = arg.rl_idx; 1970 1971 return (0); 1972} 1973 1974static void 1975re_start(ifp) 1976 struct ifnet *ifp; 1977{ 1978 struct rl_softc *sc; 1979 1980 sc = ifp->if_softc; 1981 RL_LOCK(sc); 1982 re_start_locked(ifp); 1983 RL_UNLOCK(sc); 1984} 1985 1986/* 1987 * Main transmit routine for C+ and gigE NICs. 1988 */ 1989static void 1990re_start_locked(ifp) 1991 struct ifnet *ifp; 1992{ 1993 struct rl_softc *sc; 1994 struct mbuf *m_head = NULL; 1995 int idx, queued = 0; 1996 1997 sc = ifp->if_softc; 1998 1999 RL_LOCK_ASSERT(sc); 2000 2001 idx = sc->rl_ldata.rl_tx_prodidx; 2002 2003 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2004 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2005 if (m_head == NULL) 2006 break; 2007 2008 if (re_encap(sc, &m_head, &idx)) { 2009 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2010 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2011 break; 2012 } 2013 2014 /* 2015 * If there's a BPF listener, bounce a copy of this frame 2016 * to him. 2017 */ 2018 BPF_MTAP(ifp, m_head); 2019 2020 queued++; 2021 } 2022 2023 if (queued == 0) 2024 return; 2025 2026 /* Flush the TX descriptors */ 2027 2028 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2029 sc->rl_ldata.rl_tx_list_map, 2030 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2031 2032 sc->rl_ldata.rl_tx_prodidx = idx; 2033 2034 /* 2035 * RealTek put the TX poll request register in a different 2036 * location on the 8169 gigE chip. I don't know why. 2037 */ 2038 2039 if (sc->rl_type == RL_8169) 2040 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2041 else 2042 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2043 2044 /* 2045 * Use the countdown timer for interrupt moderation. 2046 * 'TX done' interrupts are disabled. Instead, we reset the 2047 * countdown timer, which will begin counting until it hits 2048 * the value in the TIMERINT register, and then trigger an 2049 * interrupt. Each time we write to the TIMERCNT register, 2050 * the timer count is reset to 0. 2051 */ 2052 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2053 2054 /* 2055 * Set a timeout in case the chip goes out to lunch. 2056 */ 2057 ifp->if_timer = 5; 2058} 2059 2060static void 2061re_init(xsc) 2062 void *xsc; 2063{ 2064 struct rl_softc *sc = xsc; 2065 2066 RL_LOCK(sc); 2067 re_init_locked(sc); 2068 RL_UNLOCK(sc); 2069} 2070 2071static void 2072re_init_locked(sc) 2073 struct rl_softc *sc; 2074{ 2075 struct ifnet *ifp = sc->rl_ifp; 2076 struct mii_data *mii; 2077 u_int32_t rxcfg = 0; 2078 2079 RL_LOCK_ASSERT(sc); 2080 2081 mii = device_get_softc(sc->rl_miibus); 2082 2083 /* 2084 * Cancel pending I/O and free all RX/TX buffers. 2085 */ 2086 re_stop(sc); 2087 2088 /* 2089 * Enable C+ RX and TX mode, as well as VLAN stripping and 2090 * RX checksum offload. We must configure the C+ register 2091 * before all others. 2092 */ 2093 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2094 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2095 RL_CPLUSCMD_VLANSTRIP| 2096 (ifp->if_capenable & IFCAP_RXCSUM ? 2097 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2098 2099 /* 2100 * Init our MAC address. Even though the chipset 2101 * documentation doesn't mention it, we need to enter "Config 2102 * register write enable" mode to modify the ID registers. 2103 */ 2104 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2105 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2106 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[0])); 2107 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2108 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[4])); 2109 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2110 2111 /* 2112 * For C+ mode, initialize the RX descriptors and mbufs. 2113 */ 2114 re_rx_list_init(sc); 2115 re_tx_list_init(sc); 2116 2117 /* 2118 * Enable transmit and receive. 2119 */ 2120 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2121 2122 /* 2123 * Set the initial TX and RX configuration. 2124 */ 2125 if (sc->rl_testmode) { 2126 if (sc->rl_type == RL_8169) 2127 CSR_WRITE_4(sc, RL_TXCFG, 2128 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2129 else 2130 CSR_WRITE_4(sc, RL_TXCFG, 2131 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2132 } else 2133 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2134 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2135 2136 /* Set the individual bit to receive frames for this host only. */ 2137 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2138 rxcfg |= RL_RXCFG_RX_INDIV; 2139 2140 /* If we want promiscuous mode, set the allframes bit. */ 2141 if (ifp->if_flags & IFF_PROMISC) 2142 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2143 else 2144 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2145 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2146 2147 /* 2148 * Set capture broadcast bit to capture broadcast frames. 2149 */ 2150 if (ifp->if_flags & IFF_BROADCAST) 2151 rxcfg |= RL_RXCFG_RX_BROAD; 2152 else 2153 rxcfg &= ~RL_RXCFG_RX_BROAD; 2154 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2155 2156 /* 2157 * Program the multicast filter, if necessary. 2158 */ 2159 re_setmulti(sc); 2160 2161#ifdef DEVICE_POLLING 2162 /* 2163 * Disable interrupts if we are polling. 2164 */ 2165 if (ifp->if_capenable & IFCAP_POLLING) 2166 CSR_WRITE_2(sc, RL_IMR, 0); 2167 else /* otherwise ... */ 2168#endif 2169 /* 2170 * Enable interrupts. 2171 */ 2172 if (sc->rl_testmode) 2173 CSR_WRITE_2(sc, RL_IMR, 0); 2174 else 2175 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2176 2177 /* Set initial TX threshold */ 2178 sc->rl_txthresh = RL_TX_THRESH_INIT; 2179 2180 /* Start RX/TX process. */ 2181 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2182#ifdef notdef 2183 /* Enable receiver and transmitter. */ 2184 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2185#endif 2186 /* 2187 * Load the addresses of the RX and TX lists into the chip. 2188 */ 2189 2190 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2191 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2192 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2193 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2194 2195 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2196 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2197 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2198 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2199 2200 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2201 2202 /* 2203 * Initialize the timer interrupt register so that 2204 * a timer interrupt will be generated once the timer 2205 * reaches a certain number of ticks. The timer is 2206 * reloaded on each transmit. This gives us TX interrupt 2207 * moderation, which dramatically improves TX frame rate. 2208 */ 2209 if (sc->rl_type == RL_8169) 2210 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2211 else 2212 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2213 2214 /* 2215 * For 8169 gigE NICs, set the max allowed RX packet 2216 * size so we can receive jumbo frames. 2217 */ 2218 if (sc->rl_type == RL_8169) 2219 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2220 2221 if (sc->rl_testmode) 2222 return; 2223 2224 mii_mediachg(mii); 2225 2226 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2227 2228 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2229 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2230 2231 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2232} 2233 2234/* 2235 * Set media options. 2236 */ 2237static int 2238re_ifmedia_upd(ifp) 2239 struct ifnet *ifp; 2240{ 2241 struct rl_softc *sc; 2242 struct mii_data *mii; 2243 2244 sc = ifp->if_softc; 2245 mii = device_get_softc(sc->rl_miibus); 2246 RL_LOCK(sc); 2247 mii_mediachg(mii); 2248 RL_UNLOCK(sc); 2249 2250 return (0); 2251} 2252 2253/* 2254 * Report current media status. 2255 */ 2256static void 2257re_ifmedia_sts(ifp, ifmr) 2258 struct ifnet *ifp; 2259 struct ifmediareq *ifmr; 2260{ 2261 struct rl_softc *sc; 2262 struct mii_data *mii; 2263 2264 sc = ifp->if_softc; 2265 mii = device_get_softc(sc->rl_miibus); 2266 2267 RL_LOCK(sc); 2268 mii_pollstat(mii); 2269 RL_UNLOCK(sc); 2270 ifmr->ifm_active = mii->mii_media_active; 2271 ifmr->ifm_status = mii->mii_media_status; 2272} 2273 2274static int 2275re_ioctl(ifp, command, data) 2276 struct ifnet *ifp; 2277 u_long command; 2278 caddr_t data; 2279{ 2280 struct rl_softc *sc = ifp->if_softc; 2281 struct ifreq *ifr = (struct ifreq *) data; 2282 struct mii_data *mii; 2283 int error = 0; 2284 2285 switch (command) { 2286 case SIOCSIFMTU: 2287 RL_LOCK(sc); 2288 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2289 error = EINVAL; 2290 ifp->if_mtu = ifr->ifr_mtu; 2291 RL_UNLOCK(sc); 2292 break; 2293 case SIOCSIFFLAGS: 2294 RL_LOCK(sc); 2295 if (ifp->if_flags & IFF_UP) 2296 re_init_locked(sc); 2297 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2298 re_stop(sc); 2299 RL_UNLOCK(sc); 2300 break; 2301 case SIOCADDMULTI: 2302 case SIOCDELMULTI: 2303 RL_LOCK(sc); 2304 re_setmulti(sc); 2305 RL_UNLOCK(sc); 2306 break; 2307 case SIOCGIFMEDIA: 2308 case SIOCSIFMEDIA: 2309 mii = device_get_softc(sc->rl_miibus); 2310 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2311 break; 2312 case SIOCSIFCAP: 2313 { 2314 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2315#ifdef DEVICE_POLLING 2316 if (mask & IFCAP_POLLING) { 2317 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2318 error = ether_poll_register(re_poll, ifp); 2319 if (error) 2320 return(error); 2321 RL_LOCK(sc); 2322 /* Disable interrupts */ 2323 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2324 ifp->if_capenable |= IFCAP_POLLING; 2325 RL_UNLOCK(sc); 2326 2327 } else { 2328 error = ether_poll_deregister(ifp); 2329 /* Enable interrupts. */ 2330 RL_LOCK(sc); 2331 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2332 ifp->if_capenable &= ~IFCAP_POLLING; 2333 RL_UNLOCK(sc); 2334 } 2335 } 2336#endif /* DEVICE_POLLING */ 2337 if (mask & IFCAP_HWCSUM) { 2338 RL_LOCK(sc); 2339 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_HWCSUM; 2340 if (ifp->if_capenable & IFCAP_TXCSUM) 2341 ifp->if_hwassist = RE_CSUM_FEATURES; 2342 else 2343 ifp->if_hwassist = 0; 2344 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2345 re_init_locked(sc); 2346 RL_UNLOCK(sc); 2347 } 2348 } 2349 break; 2350 default: 2351 error = ether_ioctl(ifp, command, data); 2352 break; 2353 } 2354 2355 return (error); 2356} 2357 2358static void 2359re_watchdog(ifp) 2360 struct ifnet *ifp; 2361{ 2362 struct rl_softc *sc; 2363 2364 sc = ifp->if_softc; 2365 RL_LOCK(sc); 2366 if_printf(ifp, "watchdog timeout\n"); 2367 ifp->if_oerrors++; 2368 2369 re_txeof(sc); 2370 re_rxeof(sc); 2371 re_init_locked(sc); 2372 2373 RL_UNLOCK(sc); 2374} 2375 2376/* 2377 * Stop the adapter and free any mbufs allocated to the 2378 * RX and TX lists. 2379 */ 2380static void 2381re_stop(sc) 2382 struct rl_softc *sc; 2383{ 2384 register int i; 2385 struct ifnet *ifp; 2386 2387 RL_LOCK_ASSERT(sc); 2388 2389 ifp = sc->rl_ifp; 2390 ifp->if_timer = 0; 2391 2392 callout_stop(&sc->rl_stat_callout); 2393 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2394 2395 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2396 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2397 2398 if (sc->rl_head != NULL) { 2399 m_freem(sc->rl_head); 2400 sc->rl_head = sc->rl_tail = NULL; 2401 } 2402 2403 /* Free the TX list buffers. */ 2404 2405 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2406 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2407 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2408 sc->rl_ldata.rl_tx_dmamap[i]); 2409 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2410 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2411 } 2412 } 2413 2414 /* Free the RX list buffers. */ 2415 2416 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2417 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2418 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2419 sc->rl_ldata.rl_rx_dmamap[i]); 2420 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2421 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2422 } 2423 } 2424} 2425 2426/* 2427 * Device suspend routine. Stop the interface and save some PCI 2428 * settings in case the BIOS doesn't restore them properly on 2429 * resume. 2430 */ 2431static int 2432re_suspend(dev) 2433 device_t dev; 2434{ 2435 struct rl_softc *sc; 2436 2437 sc = device_get_softc(dev); 2438 2439 RL_LOCK(sc); 2440 re_stop(sc); 2441 sc->suspended = 1; 2442 RL_UNLOCK(sc); 2443 2444 return (0); 2445} 2446 2447/* 2448 * Device resume routine. Restore some PCI settings in case the BIOS 2449 * doesn't, re-enable busmastering, and restart the interface if 2450 * appropriate. 2451 */ 2452static int 2453re_resume(dev) 2454 device_t dev; 2455{ 2456 struct rl_softc *sc; 2457 struct ifnet *ifp; 2458 2459 sc = device_get_softc(dev); 2460 2461 RL_LOCK(sc); 2462 2463 ifp = sc->rl_ifp; 2464 2465 /* reinitialize interface if necessary */ 2466 if (ifp->if_flags & IFF_UP) 2467 re_init_locked(sc); 2468 2469 sc->suspended = 0; 2470 RL_UNLOCK(sc); 2471 2472 return (0); 2473} 2474 2475/* 2476 * Stop all chip I/O so that the kernel's probe routines don't 2477 * get confused by errant DMAs when rebooting. 2478 */ 2479static void 2480re_shutdown(dev) 2481 device_t dev; 2482{ 2483 struct rl_softc *sc; 2484 2485 sc = device_get_softc(dev); 2486 2487 RL_LOCK(sc); 2488 re_stop(sc); 2489 /* 2490 * Mark interface as down since otherwise we will panic if 2491 * interrupt comes in later on, which can happen in some 2492 * cases. 2493 */ 2494 sc->rl_ifp->if_flags &= ~IFF_UP; 2495 RL_UNLOCK(sc); 2496} 2497