if_re.c revision 147256
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 147256 2005-06-10 16:49:24Z brooks $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#include <sys/param.h> 112#include <sys/endian.h> 113#include <sys/systm.h> 114#include <sys/sockio.h> 115#include <sys/mbuf.h> 116#include <sys/malloc.h> 117#include <sys/module.h> 118#include <sys/kernel.h> 119#include <sys/socket.h> 120 121#include <net/if.h> 122#include <net/if_arp.h> 123#include <net/ethernet.h> 124#include <net/if_dl.h> 125#include <net/if_media.h> 126#include <net/if_types.h> 127#include <net/if_vlan_var.h> 128 129#include <net/bpf.h> 130 131#include <machine/bus.h> 132#include <machine/resource.h> 133#include <sys/bus.h> 134#include <sys/rman.h> 135 136#include <dev/mii/mii.h> 137#include <dev/mii/miivar.h> 138 139#include <dev/pci/pcireg.h> 140#include <dev/pci/pcivar.h> 141 142MODULE_DEPEND(re, pci, 1, 1, 1); 143MODULE_DEPEND(re, ether, 1, 1, 1); 144MODULE_DEPEND(re, miibus, 1, 1, 1); 145 146/* "controller miibus0" required. See GENERIC if you get errors here. */ 147#include "miibus_if.h" 148 149/* 150 * Default to using PIO access for this driver. 151 */ 152#define RE_USEIOSPACE 153 154#include <pci/if_rlreg.h> 155 156#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 157 158/* 159 * Various supported device vendors/types and their names. 160 */ 161static struct rl_type re_devs[] = { 162 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 163 "RealTek 8139C+ 10/100BaseTX" }, 164 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 165 "RealTek 8169 Gigabit Ethernet" }, 166 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 167 "RealTek 8169S Single-chip Gigabit Ethernet" }, 168 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB, 169 "RealTek 8169SB Single-chip Gigabit Ethernet" }, 170 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 171 "RealTek 8110S Single-chip Gigabit Ethernet" }, 172 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 173 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 174 { 0, 0, 0, NULL } 175}; 176 177static struct rl_hwrev re_hwrevs[] = { 178 { RL_HWREV_8139, RL_8139, "" }, 179 { RL_HWREV_8139A, RL_8139, "A" }, 180 { RL_HWREV_8139AG, RL_8139, "A-G" }, 181 { RL_HWREV_8139B, RL_8139, "B" }, 182 { RL_HWREV_8130, RL_8139, "8130" }, 183 { RL_HWREV_8139C, RL_8139, "C" }, 184 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 185 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 186 { RL_HWREV_8169, RL_8169, "8169"}, 187 { RL_HWREV_8169S, RL_8169, "8169S"}, 188 { RL_HWREV_8169SB, RL_8169, "8169SB"}, 189 { RL_HWREV_8110S, RL_8169, "8110S"}, 190 { RL_HWREV_8100, RL_8139, "8100"}, 191 { RL_HWREV_8101, RL_8139, "8101"}, 192 { 0, 0, NULL } 193}; 194 195static int re_probe (device_t); 196static int re_attach (device_t); 197static int re_detach (device_t); 198 199static int re_encap (struct rl_softc *, struct mbuf **, int *); 200 201static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 202static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 203 bus_size_t, int); 204static int re_allocmem (device_t, struct rl_softc *); 205static int re_newbuf (struct rl_softc *, int, struct mbuf *); 206static int re_rx_list_init (struct rl_softc *); 207static int re_tx_list_init (struct rl_softc *); 208#ifdef RE_FIXUP_RX 209static __inline void re_fixup_rx 210 (struct mbuf *); 211#endif 212static void re_rxeof (struct rl_softc *); 213static void re_txeof (struct rl_softc *); 214#ifdef DEVICE_POLLING 215static void re_poll (struct ifnet *, enum poll_cmd, int); 216static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 217#endif 218static void re_intr (void *); 219static void re_tick (void *); 220static void re_tick_locked (struct rl_softc *); 221static void re_start (struct ifnet *); 222static void re_start_locked (struct ifnet *); 223static int re_ioctl (struct ifnet *, u_long, caddr_t); 224static void re_init (void *); 225static void re_init_locked (struct rl_softc *); 226static void re_stop (struct rl_softc *); 227static void re_watchdog (struct ifnet *); 228static int re_suspend (device_t); 229static int re_resume (device_t); 230static void re_shutdown (device_t); 231static int re_ifmedia_upd (struct ifnet *); 232static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 233 234static void re_eeprom_putbyte (struct rl_softc *, int); 235static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 236static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 237static int re_gmii_readreg (device_t, int, int); 238static int re_gmii_writereg (device_t, int, int, int); 239 240static int re_miibus_readreg (device_t, int, int); 241static int re_miibus_writereg (device_t, int, int, int); 242static void re_miibus_statchg (device_t); 243 244static void re_setmulti (struct rl_softc *); 245static void re_reset (struct rl_softc *); 246 247static int re_diag (struct rl_softc *); 248 249#ifdef RE_USEIOSPACE 250#define RL_RES SYS_RES_IOPORT 251#define RL_RID RL_PCI_LOIO 252#else 253#define RL_RES SYS_RES_MEMORY 254#define RL_RID RL_PCI_LOMEM 255#endif 256 257static device_method_t re_methods[] = { 258 /* Device interface */ 259 DEVMETHOD(device_probe, re_probe), 260 DEVMETHOD(device_attach, re_attach), 261 DEVMETHOD(device_detach, re_detach), 262 DEVMETHOD(device_suspend, re_suspend), 263 DEVMETHOD(device_resume, re_resume), 264 DEVMETHOD(device_shutdown, re_shutdown), 265 266 /* bus interface */ 267 DEVMETHOD(bus_print_child, bus_generic_print_child), 268 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 269 270 /* MII interface */ 271 DEVMETHOD(miibus_readreg, re_miibus_readreg), 272 DEVMETHOD(miibus_writereg, re_miibus_writereg), 273 DEVMETHOD(miibus_statchg, re_miibus_statchg), 274 275 { 0, 0 } 276}; 277 278static driver_t re_driver = { 279 "re", 280 re_methods, 281 sizeof(struct rl_softc) 282}; 283 284static devclass_t re_devclass; 285 286DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 287DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 288DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 289 290#define EE_SET(x) \ 291 CSR_WRITE_1(sc, RL_EECMD, \ 292 CSR_READ_1(sc, RL_EECMD) | x) 293 294#define EE_CLR(x) \ 295 CSR_WRITE_1(sc, RL_EECMD, \ 296 CSR_READ_1(sc, RL_EECMD) & ~x) 297 298/* 299 * Send a read command and address to the EEPROM, check for ACK. 300 */ 301static void 302re_eeprom_putbyte(sc, addr) 303 struct rl_softc *sc; 304 int addr; 305{ 306 register int d, i; 307 308 d = addr | sc->rl_eecmd_read; 309 310 /* 311 * Feed in each bit and strobe the clock. 312 */ 313 for (i = 0x400; i; i >>= 1) { 314 if (d & i) { 315 EE_SET(RL_EE_DATAIN); 316 } else { 317 EE_CLR(RL_EE_DATAIN); 318 } 319 DELAY(100); 320 EE_SET(RL_EE_CLK); 321 DELAY(150); 322 EE_CLR(RL_EE_CLK); 323 DELAY(100); 324 } 325} 326 327/* 328 * Read a word of data stored in the EEPROM at address 'addr.' 329 */ 330static void 331re_eeprom_getword(sc, addr, dest) 332 struct rl_softc *sc; 333 int addr; 334 u_int16_t *dest; 335{ 336 register int i; 337 u_int16_t word = 0; 338 339 /* Enter EEPROM access mode. */ 340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 341 342 /* 343 * Send address of word we want to read. 344 */ 345 re_eeprom_putbyte(sc, addr); 346 347 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 348 349 /* 350 * Start reading bits from EEPROM. 351 */ 352 for (i = 0x8000; i; i >>= 1) { 353 EE_SET(RL_EE_CLK); 354 DELAY(100); 355 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 356 word |= i; 357 EE_CLR(RL_EE_CLK); 358 DELAY(100); 359 } 360 361 /* Turn off EEPROM access mode. */ 362 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 363 364 *dest = word; 365} 366 367/* 368 * Read a sequence of words from the EEPROM. 369 */ 370static void 371re_read_eeprom(sc, dest, off, cnt, swap) 372 struct rl_softc *sc; 373 caddr_t dest; 374 int off; 375 int cnt; 376 int swap; 377{ 378 int i; 379 u_int16_t word = 0, *ptr; 380 381 for (i = 0; i < cnt; i++) { 382 re_eeprom_getword(sc, off + i, &word); 383 ptr = (u_int16_t *)(dest + (i * 2)); 384 if (swap) 385 *ptr = ntohs(word); 386 else 387 *ptr = word; 388 } 389} 390 391static int 392re_gmii_readreg(dev, phy, reg) 393 device_t dev; 394 int phy, reg; 395{ 396 struct rl_softc *sc; 397 u_int32_t rval; 398 int i; 399 400 if (phy != 1) 401 return (0); 402 403 sc = device_get_softc(dev); 404 405 /* Let the rgephy driver read the GMEDIASTAT register */ 406 407 if (reg == RL_GMEDIASTAT) { 408 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 409 return (rval); 410 } 411 412 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 413 DELAY(1000); 414 415 for (i = 0; i < RL_TIMEOUT; i++) { 416 rval = CSR_READ_4(sc, RL_PHYAR); 417 if (rval & RL_PHYAR_BUSY) 418 break; 419 DELAY(100); 420 } 421 422 if (i == RL_TIMEOUT) { 423 printf ("re%d: PHY read failed\n", sc->rl_unit); 424 return (0); 425 } 426 427 return (rval & RL_PHYAR_PHYDATA); 428} 429 430static int 431re_gmii_writereg(dev, phy, reg, data) 432 device_t dev; 433 int phy, reg, data; 434{ 435 struct rl_softc *sc; 436 u_int32_t rval; 437 int i; 438 439 sc = device_get_softc(dev); 440 441 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 442 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 443 DELAY(1000); 444 445 for (i = 0; i < RL_TIMEOUT; i++) { 446 rval = CSR_READ_4(sc, RL_PHYAR); 447 if (!(rval & RL_PHYAR_BUSY)) 448 break; 449 DELAY(100); 450 } 451 452 if (i == RL_TIMEOUT) { 453 printf ("re%d: PHY write failed\n", sc->rl_unit); 454 return (0); 455 } 456 457 return (0); 458} 459 460static int 461re_miibus_readreg(dev, phy, reg) 462 device_t dev; 463 int phy, reg; 464{ 465 struct rl_softc *sc; 466 u_int16_t rval = 0; 467 u_int16_t re8139_reg = 0; 468 469 sc = device_get_softc(dev); 470 471 if (sc->rl_type == RL_8169) { 472 rval = re_gmii_readreg(dev, phy, reg); 473 return (rval); 474 } 475 476 /* Pretend the internal PHY is only at address 0 */ 477 if (phy) { 478 return (0); 479 } 480 switch (reg) { 481 case MII_BMCR: 482 re8139_reg = RL_BMCR; 483 break; 484 case MII_BMSR: 485 re8139_reg = RL_BMSR; 486 break; 487 case MII_ANAR: 488 re8139_reg = RL_ANAR; 489 break; 490 case MII_ANER: 491 re8139_reg = RL_ANER; 492 break; 493 case MII_ANLPAR: 494 re8139_reg = RL_LPAR; 495 break; 496 case MII_PHYIDR1: 497 case MII_PHYIDR2: 498 return (0); 499 /* 500 * Allow the rlphy driver to read the media status 501 * register. If we have a link partner which does not 502 * support NWAY, this is the register which will tell 503 * us the results of parallel detection. 504 */ 505 case RL_MEDIASTAT: 506 rval = CSR_READ_1(sc, RL_MEDIASTAT); 507 return (rval); 508 default: 509 printf("re%d: bad phy register\n", sc->rl_unit); 510 return (0); 511 } 512 rval = CSR_READ_2(sc, re8139_reg); 513 return (rval); 514} 515 516static int 517re_miibus_writereg(dev, phy, reg, data) 518 device_t dev; 519 int phy, reg, data; 520{ 521 struct rl_softc *sc; 522 u_int16_t re8139_reg = 0; 523 int rval = 0; 524 525 sc = device_get_softc(dev); 526 527 if (sc->rl_type == RL_8169) { 528 rval = re_gmii_writereg(dev, phy, reg, data); 529 return (rval); 530 } 531 532 /* Pretend the internal PHY is only at address 0 */ 533 if (phy) 534 return (0); 535 536 switch (reg) { 537 case MII_BMCR: 538 re8139_reg = RL_BMCR; 539 break; 540 case MII_BMSR: 541 re8139_reg = RL_BMSR; 542 break; 543 case MII_ANAR: 544 re8139_reg = RL_ANAR; 545 break; 546 case MII_ANER: 547 re8139_reg = RL_ANER; 548 break; 549 case MII_ANLPAR: 550 re8139_reg = RL_LPAR; 551 break; 552 case MII_PHYIDR1: 553 case MII_PHYIDR2: 554 return (0); 555 break; 556 default: 557 printf("re%d: bad phy register\n", sc->rl_unit); 558 return (0); 559 } 560 CSR_WRITE_2(sc, re8139_reg, data); 561 return (0); 562} 563 564static void 565re_miibus_statchg(dev) 566 device_t dev; 567{ 568 569} 570 571/* 572 * Program the 64-bit multicast hash filter. 573 */ 574static void 575re_setmulti(sc) 576 struct rl_softc *sc; 577{ 578 struct ifnet *ifp; 579 int h = 0; 580 u_int32_t hashes[2] = { 0, 0 }; 581 struct ifmultiaddr *ifma; 582 u_int32_t rxfilt; 583 int mcnt = 0; 584 585 RL_LOCK_ASSERT(sc); 586 587 ifp = sc->rl_ifp; 588 589 rxfilt = CSR_READ_4(sc, RL_RXCFG); 590 591 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 592 rxfilt |= RL_RXCFG_RX_MULTI; 593 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 594 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 595 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 596 return; 597 } 598 599 /* first, zot all the existing hash bits */ 600 CSR_WRITE_4(sc, RL_MAR0, 0); 601 CSR_WRITE_4(sc, RL_MAR4, 0); 602 603 /* now program new ones */ 604 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 605 if (ifma->ifma_addr->sa_family != AF_LINK) 606 continue; 607 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 608 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 609 if (h < 32) 610 hashes[0] |= (1 << h); 611 else 612 hashes[1] |= (1 << (h - 32)); 613 mcnt++; 614 } 615 616 if (mcnt) 617 rxfilt |= RL_RXCFG_RX_MULTI; 618 else 619 rxfilt &= ~RL_RXCFG_RX_MULTI; 620 621 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 622 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 623 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 624} 625 626static void 627re_reset(sc) 628 struct rl_softc *sc; 629{ 630 register int i; 631 632 RL_LOCK_ASSERT(sc); 633 634 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 635 636 for (i = 0; i < RL_TIMEOUT; i++) { 637 DELAY(10); 638 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 639 break; 640 } 641 if (i == RL_TIMEOUT) 642 printf("re%d: reset never completed!\n", sc->rl_unit); 643 644 CSR_WRITE_1(sc, 0x82, 1); 645} 646 647/* 648 * The following routine is designed to test for a defect on some 649 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 650 * lines connected to the bus, however for a 32-bit only card, they 651 * should be pulled high. The result of this defect is that the 652 * NIC will not work right if you plug it into a 64-bit slot: DMA 653 * operations will be done with 64-bit transfers, which will fail 654 * because the 64-bit data lines aren't connected. 655 * 656 * There's no way to work around this (short of talking a soldering 657 * iron to the board), however we can detect it. The method we use 658 * here is to put the NIC into digital loopback mode, set the receiver 659 * to promiscuous mode, and then try to send a frame. We then compare 660 * the frame data we sent to what was received. If the data matches, 661 * then the NIC is working correctly, otherwise we know the user has 662 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 663 * slot. In the latter case, there's no way the NIC can work correctly, 664 * so we print out a message on the console and abort the device attach. 665 */ 666 667static int 668re_diag(sc) 669 struct rl_softc *sc; 670{ 671 struct ifnet *ifp = sc->rl_ifp; 672 struct mbuf *m0; 673 struct ether_header *eh; 674 struct rl_desc *cur_rx; 675 u_int16_t status; 676 u_int32_t rxstat; 677 int total_len, i, error = 0; 678 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 679 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 680 681 /* Allocate a single mbuf */ 682 MGETHDR(m0, M_DONTWAIT, MT_DATA); 683 if (m0 == NULL) 684 return (ENOBUFS); 685 686 RL_LOCK(sc); 687 688 /* 689 * Initialize the NIC in test mode. This sets the chip up 690 * so that it can send and receive frames, but performs the 691 * following special functions: 692 * - Puts receiver in promiscuous mode 693 * - Enables digital loopback mode 694 * - Leaves interrupts turned off 695 */ 696 697 ifp->if_flags |= IFF_PROMISC; 698 sc->rl_testmode = 1; 699 re_init_locked(sc); 700 re_stop(sc); 701 DELAY(100000); 702 re_init_locked(sc); 703 704 /* Put some data in the mbuf */ 705 706 eh = mtod(m0, struct ether_header *); 707 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 708 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 709 eh->ether_type = htons(ETHERTYPE_IP); 710 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 711 712 /* 713 * Queue the packet, start transmission. 714 * Note: IF_HANDOFF() ultimately calls re_start() for us. 715 */ 716 717 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 718 RL_UNLOCK(sc); 719 /* XXX: re_diag must not be called when in ALTQ mode */ 720 IF_HANDOFF(&ifp->if_snd, m0, ifp); 721 RL_LOCK(sc); 722 m0 = NULL; 723 724 /* Wait for it to propagate through the chip */ 725 726 DELAY(100000); 727 for (i = 0; i < RL_TIMEOUT; i++) { 728 status = CSR_READ_2(sc, RL_ISR); 729 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 730 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 731 break; 732 DELAY(10); 733 } 734 735 if (i == RL_TIMEOUT) { 736 printf("re%d: diagnostic failed, failed to receive packet " 737 "in loopback mode\n", sc->rl_unit); 738 error = EIO; 739 goto done; 740 } 741 742 /* 743 * The packet should have been dumped into the first 744 * entry in the RX DMA ring. Grab it from there. 745 */ 746 747 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 748 sc->rl_ldata.rl_rx_list_map, 749 BUS_DMASYNC_POSTREAD); 750 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 751 sc->rl_ldata.rl_rx_dmamap[0], 752 BUS_DMASYNC_POSTWRITE); 753 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 754 sc->rl_ldata.rl_rx_dmamap[0]); 755 756 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 757 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 758 eh = mtod(m0, struct ether_header *); 759 760 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 761 total_len = RL_RXBYTES(cur_rx); 762 rxstat = le32toh(cur_rx->rl_cmdstat); 763 764 if (total_len != ETHER_MIN_LEN) { 765 printf("re%d: diagnostic failed, received short packet\n", 766 sc->rl_unit); 767 error = EIO; 768 goto done; 769 } 770 771 /* Test that the received packet data matches what we sent. */ 772 773 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 774 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 775 ntohs(eh->ether_type) != ETHERTYPE_IP) { 776 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 777 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 778 dst, ":", src, ":", ETHERTYPE_IP); 779 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 780 eh->ether_dhost, ":", eh->ether_shost, ":", 781 ntohs(eh->ether_type)); 782 printf("re%d: You may have a defective 32-bit NIC plugged " 783 "into a 64-bit PCI slot.\n", sc->rl_unit); 784 printf("re%d: Please re-install the NIC in a 32-bit slot " 785 "for proper operation.\n", sc->rl_unit); 786 printf("re%d: Read the re(4) man page for more details.\n", 787 sc->rl_unit); 788 error = EIO; 789 } 790 791done: 792 /* Turn interface off, release resources */ 793 794 sc->rl_testmode = 0; 795 ifp->if_flags &= ~IFF_PROMISC; 796 re_stop(sc); 797 if (m0 != NULL) 798 m_freem(m0); 799 800 RL_UNLOCK(sc); 801 802 return (error); 803} 804 805/* 806 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 807 * IDs against our list and return a device name if we find a match. 808 */ 809static int 810re_probe(dev) 811 device_t dev; 812{ 813 struct rl_type *t; 814 struct rl_softc *sc; 815 int rid; 816 u_int32_t hwrev; 817 818 t = re_devs; 819 sc = device_get_softc(dev); 820 821 while (t->rl_name != NULL) { 822 if ((pci_get_vendor(dev) == t->rl_vid) && 823 (pci_get_device(dev) == t->rl_did)) { 824 825 /* 826 * Temporarily map the I/O space 827 * so we can read the chip ID register. 828 */ 829 rid = RL_RID; 830 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 831 RF_ACTIVE); 832 if (sc->rl_res == NULL) { 833 device_printf(dev, 834 "couldn't map ports/memory\n"); 835 return (ENXIO); 836 } 837 sc->rl_btag = rman_get_bustag(sc->rl_res); 838 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 839 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 840 bus_release_resource(dev, RL_RES, 841 RL_RID, sc->rl_res); 842 if (t->rl_basetype == hwrev) { 843 device_set_desc(dev, t->rl_name); 844 return (BUS_PROBE_DEFAULT); 845 } 846 } 847 t++; 848 } 849 850 return (ENXIO); 851} 852 853/* 854 * This routine takes the segment list provided as the result of 855 * a bus_dma_map_load() operation and assigns the addresses/lengths 856 * to RealTek DMA descriptors. This can be called either by the RX 857 * code or the TX code. In the RX case, we'll probably wind up mapping 858 * at most one segment. For the TX case, there could be any number of 859 * segments since TX packets may span multiple mbufs. In either case, 860 * if the number of segments is larger than the rl_maxsegs limit 861 * specified by the caller, we abort the mapping operation. Sadly, 862 * whoever designed the buffer mapping API did not provide a way to 863 * return an error from here, so we have to fake it a bit. 864 */ 865 866static void 867re_dma_map_desc(arg, segs, nseg, mapsize, error) 868 void *arg; 869 bus_dma_segment_t *segs; 870 int nseg; 871 bus_size_t mapsize; 872 int error; 873{ 874 struct rl_dmaload_arg *ctx; 875 struct rl_desc *d = NULL; 876 int i = 0, idx; 877 878 if (error) 879 return; 880 881 ctx = arg; 882 883 /* Signal error to caller if there's too many segments */ 884 if (nseg > ctx->rl_maxsegs) { 885 ctx->rl_maxsegs = 0; 886 return; 887 } 888 889 /* 890 * Map the segment array into descriptors. Note that we set the 891 * start-of-frame and end-of-frame markers for either TX or RX, but 892 * they really only have meaning in the TX case. (In the RX case, 893 * it's the chip that tells us where packets begin and end.) 894 * We also keep track of the end of the ring and set the 895 * end-of-ring bits as needed, and we set the ownership bits 896 * in all except the very first descriptor. (The caller will 897 * set this descriptor later when it start transmission or 898 * reception.) 899 */ 900 idx = ctx->rl_idx; 901 for (;;) { 902 u_int32_t cmdstat; 903 d = &ctx->rl_ring[idx]; 904 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 905 ctx->rl_maxsegs = 0; 906 return; 907 } 908 cmdstat = segs[i].ds_len; 909 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 910 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 911 if (i == 0) 912 cmdstat |= RL_TDESC_CMD_SOF; 913 else 914 cmdstat |= RL_TDESC_CMD_OWN; 915 if (idx == (RL_RX_DESC_CNT - 1)) 916 cmdstat |= RL_TDESC_CMD_EOR; 917 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 918 i++; 919 if (i == nseg) 920 break; 921 RL_DESC_INC(idx); 922 } 923 924 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 925 ctx->rl_maxsegs = nseg; 926 ctx->rl_idx = idx; 927} 928 929/* 930 * Map a single buffer address. 931 */ 932 933static void 934re_dma_map_addr(arg, segs, nseg, error) 935 void *arg; 936 bus_dma_segment_t *segs; 937 int nseg; 938 int error; 939{ 940 u_int32_t *addr; 941 942 if (error) 943 return; 944 945 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 946 addr = arg; 947 *addr = segs->ds_addr; 948} 949 950static int 951re_allocmem(dev, sc) 952 device_t dev; 953 struct rl_softc *sc; 954{ 955 int error; 956 int nseg; 957 int i; 958 959 /* 960 * Allocate map for RX mbufs. 961 */ 962 nseg = 32; 963 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 964 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 965 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 966 NULL, NULL, &sc->rl_ldata.rl_mtag); 967 if (error) { 968 device_printf(dev, "could not allocate dma tag\n"); 969 return (ENOMEM); 970 } 971 972 /* 973 * Allocate map for TX descriptor list. 974 */ 975 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 976 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 977 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 978 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 979 if (error) { 980 device_printf(dev, "could not allocate dma tag\n"); 981 return (ENOMEM); 982 } 983 984 /* Allocate DMA'able memory for the TX ring */ 985 986 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 987 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 988 &sc->rl_ldata.rl_tx_list_map); 989 if (error) 990 return (ENOMEM); 991 992 /* Load the map for the TX ring. */ 993 994 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 995 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 996 RL_TX_LIST_SZ, re_dma_map_addr, 997 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 998 999 /* Create DMA maps for TX buffers */ 1000 1001 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1002 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1003 &sc->rl_ldata.rl_tx_dmamap[i]); 1004 if (error) { 1005 device_printf(dev, "can't create DMA map for TX\n"); 1006 return (ENOMEM); 1007 } 1008 } 1009 1010 /* 1011 * Allocate map for RX descriptor list. 1012 */ 1013 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1014 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1015 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1016 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1017 if (error) { 1018 device_printf(dev, "could not allocate dma tag\n"); 1019 return (ENOMEM); 1020 } 1021 1022 /* Allocate DMA'able memory for the RX ring */ 1023 1024 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1025 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1026 &sc->rl_ldata.rl_rx_list_map); 1027 if (error) 1028 return (ENOMEM); 1029 1030 /* Load the map for the RX ring. */ 1031 1032 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1033 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1034 RL_RX_LIST_SZ, re_dma_map_addr, 1035 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1036 1037 /* Create DMA maps for RX buffers */ 1038 1039 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1040 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1041 &sc->rl_ldata.rl_rx_dmamap[i]); 1042 if (error) { 1043 device_printf(dev, "can't create DMA map for RX\n"); 1044 return (ENOMEM); 1045 } 1046 } 1047 1048 return (0); 1049} 1050 1051/* 1052 * Attach the interface. Allocate softc structures, do ifmedia 1053 * setup and ethernet/BPF attach. 1054 */ 1055static int 1056re_attach(dev) 1057 device_t dev; 1058{ 1059 u_char eaddr[ETHER_ADDR_LEN]; 1060 u_int16_t as[3]; 1061 struct rl_softc *sc; 1062 struct ifnet *ifp; 1063 struct rl_hwrev *hw_rev; 1064 int hwrev; 1065 u_int16_t re_did = 0; 1066 int unit, error = 0, rid, i; 1067 1068 sc = device_get_softc(dev); 1069 unit = device_get_unit(dev); 1070 1071 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1072 MTX_DEF); 1073 /* 1074 * Map control/status registers. 1075 */ 1076 pci_enable_busmaster(dev); 1077 1078 rid = RL_RID; 1079 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1080 RF_ACTIVE); 1081 1082 if (sc->rl_res == NULL) { 1083 printf ("re%d: couldn't map ports/memory\n", unit); 1084 error = ENXIO; 1085 goto fail; 1086 } 1087 1088 sc->rl_btag = rman_get_bustag(sc->rl_res); 1089 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1090 1091 /* Allocate interrupt */ 1092 rid = 0; 1093 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1094 RF_SHAREABLE | RF_ACTIVE); 1095 1096 if (sc->rl_irq == NULL) { 1097 printf("re%d: couldn't map interrupt\n", unit); 1098 error = ENXIO; 1099 goto fail; 1100 } 1101 1102 /* Reset the adapter. */ 1103 RL_LOCK(sc); 1104 re_reset(sc); 1105 RL_UNLOCK(sc); 1106 1107 hw_rev = re_hwrevs; 1108 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1109 while (hw_rev->rl_desc != NULL) { 1110 if (hw_rev->rl_rev == hwrev) { 1111 sc->rl_type = hw_rev->rl_type; 1112 break; 1113 } 1114 hw_rev++; 1115 } 1116 1117 if (sc->rl_type == RL_8169) { 1118 1119 /* Set RX length mask */ 1120 1121 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1122 1123 /* Force station address autoload from the EEPROM */ 1124 1125 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1126 for (i = 0; i < RL_TIMEOUT; i++) { 1127 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1128 break; 1129 DELAY(100); 1130 } 1131 if (i == RL_TIMEOUT) 1132 printf ("re%d: eeprom autoload timed out\n", unit); 1133 1134 for (i = 0; i < ETHER_ADDR_LEN; i++) 1135 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1136 } else { 1137 1138 /* Set RX length mask */ 1139 1140 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1141 1142 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1143 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1144 if (re_did != 0x8129) 1145 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1146 1147 /* 1148 * Get station address from the EEPROM. 1149 */ 1150 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1151 for (i = 0; i < 3; i++) { 1152 eaddr[(i * 2) + 0] = as[i] & 0xff; 1153 eaddr[(i * 2) + 1] = as[i] >> 8; 1154 } 1155 } 1156 1157 sc->rl_unit = unit; 1158 1159 /* 1160 * Allocate the parent bus DMA tag appropriate for PCI. 1161 */ 1162#define RL_NSEG_NEW 32 1163 error = bus_dma_tag_create(NULL, /* parent */ 1164 1, 0, /* alignment, boundary */ 1165 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1166 BUS_SPACE_MAXADDR, /* highaddr */ 1167 NULL, NULL, /* filter, filterarg */ 1168 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1169 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1170 BUS_DMA_ALLOCNOW, /* flags */ 1171 NULL, NULL, /* lockfunc, lockarg */ 1172 &sc->rl_parent_tag); 1173 if (error) 1174 goto fail; 1175 1176 error = re_allocmem(dev, sc); 1177 1178 if (error) 1179 goto fail; 1180 1181 /* Do MII setup */ 1182 if (mii_phy_probe(dev, &sc->rl_miibus, 1183 re_ifmedia_upd, re_ifmedia_sts)) { 1184 printf("re%d: MII without any phy!\n", sc->rl_unit); 1185 error = ENXIO; 1186 goto fail; 1187 } 1188 1189 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1190 if (ifp == NULL) { 1191 printf("re%d: can not if_alloc()\n", sc->rl_unit); 1192 error = ENOSPC; 1193 goto fail; 1194 } 1195 ifp->if_softc = sc; 1196 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1197 ifp->if_mtu = ETHERMTU; 1198 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1199 ifp->if_ioctl = re_ioctl; 1200 ifp->if_capabilities = IFCAP_VLAN_MTU; 1201 ifp->if_start = re_start; 1202 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0; 1203 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1204#ifdef DEVICE_POLLING 1205 ifp->if_capabilities |= IFCAP_POLLING; 1206#endif 1207 ifp->if_watchdog = re_watchdog; 1208 ifp->if_init = re_init; 1209 if (sc->rl_type == RL_8169) 1210 ifp->if_baudrate = 1000000000; 1211 else 1212 ifp->if_baudrate = 100000000; 1213 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1214 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1215 IFQ_SET_READY(&ifp->if_snd); 1216 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1217 1218 callout_handle_init(&sc->rl_stat_ch); 1219 1220 /* 1221 * Call MI attach routine. 1222 */ 1223 ether_ifattach(ifp, eaddr); 1224 1225 /* Perform hardware diagnostic. */ 1226 error = re_diag(sc); 1227 1228 if (error) { 1229 printf("re%d: attach aborted due to hardware diag failure\n", 1230 unit); 1231 ether_ifdetach(ifp); 1232 if_free(ifp); 1233 goto fail; 1234 } 1235 1236 /* Hook interrupt last to avoid having to lock softc */ 1237 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1238 re_intr, sc, &sc->rl_intrhand); 1239 if (error) { 1240 printf("re%d: couldn't set up irq\n", unit); 1241 ether_ifdetach(ifp); 1242 if_free(ifp); 1243 } 1244 1245fail: 1246 if (error) 1247 re_detach(dev); 1248 1249 return (error); 1250} 1251 1252/* 1253 * Shutdown hardware and free up resources. This can be called any 1254 * time after the mutex has been initialized. It is called in both 1255 * the error case in attach and the normal detach case so it needs 1256 * to be careful about only freeing resources that have actually been 1257 * allocated. 1258 */ 1259static int 1260re_detach(dev) 1261 device_t dev; 1262{ 1263 struct rl_softc *sc; 1264 struct ifnet *ifp; 1265 int i; 1266 int attached; 1267 1268 sc = device_get_softc(dev); 1269 ifp = sc->rl_ifp; 1270 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1271 1272 attached = device_is_attached(dev); 1273 /* These should only be active if attach succeeded */ 1274 if (attached) 1275 ether_ifdetach(ifp); 1276 if (ifp == NULL) 1277 if_free(ifp); 1278 1279 RL_LOCK(sc); 1280#if 0 1281 sc->suspended = 1; 1282#endif 1283 1284 /* These should only be active if attach succeeded */ 1285 if (attached) { 1286 re_stop(sc); 1287 /* 1288 * Force off the IFF_UP flag here, in case someone 1289 * still had a BPF descriptor attached to this 1290 * interface. If they do, ether_ifdetach() will cause 1291 * the BPF code to try and clear the promisc mode 1292 * flag, which will bubble down to re_ioctl(), 1293 * which will try to call re_init() again. This will 1294 * turn the NIC back on and restart the MII ticker, 1295 * which will panic the system when the kernel tries 1296 * to invoke the re_tick() function that isn't there 1297 * anymore. 1298 */ 1299 ifp->if_flags &= ~IFF_UP; 1300 } 1301 if (sc->rl_miibus) 1302 device_delete_child(dev, sc->rl_miibus); 1303 bus_generic_detach(dev); 1304 1305 /* 1306 * The rest is resource deallocation, so we should already be 1307 * stopped here. 1308 */ 1309 RL_UNLOCK(sc); 1310 1311 if (sc->rl_intrhand) 1312 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1313 if (sc->rl_irq) 1314 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1315 if (sc->rl_res) 1316 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1317 1318 1319 /* Unload and free the RX DMA ring memory and map */ 1320 1321 if (sc->rl_ldata.rl_rx_list_tag) { 1322 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1323 sc->rl_ldata.rl_rx_list_map); 1324 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1325 sc->rl_ldata.rl_rx_list, 1326 sc->rl_ldata.rl_rx_list_map); 1327 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1328 } 1329 1330 /* Unload and free the TX DMA ring memory and map */ 1331 1332 if (sc->rl_ldata.rl_tx_list_tag) { 1333 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1334 sc->rl_ldata.rl_tx_list_map); 1335 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1336 sc->rl_ldata.rl_tx_list, 1337 sc->rl_ldata.rl_tx_list_map); 1338 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1339 } 1340 1341 /* Destroy all the RX and TX buffer maps */ 1342 1343 if (sc->rl_ldata.rl_mtag) { 1344 for (i = 0; i < RL_TX_DESC_CNT; i++) 1345 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1346 sc->rl_ldata.rl_tx_dmamap[i]); 1347 for (i = 0; i < RL_RX_DESC_CNT; i++) 1348 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1349 sc->rl_ldata.rl_rx_dmamap[i]); 1350 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1351 } 1352 1353 /* Unload and free the stats buffer and map */ 1354 1355 if (sc->rl_ldata.rl_stag) { 1356 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1357 sc->rl_ldata.rl_rx_list_map); 1358 bus_dmamem_free(sc->rl_ldata.rl_stag, 1359 sc->rl_ldata.rl_stats, 1360 sc->rl_ldata.rl_smap); 1361 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1362 } 1363 1364 if (sc->rl_parent_tag) 1365 bus_dma_tag_destroy(sc->rl_parent_tag); 1366 1367 mtx_destroy(&sc->rl_mtx); 1368 1369 return (0); 1370} 1371 1372static int 1373re_newbuf(sc, idx, m) 1374 struct rl_softc *sc; 1375 int idx; 1376 struct mbuf *m; 1377{ 1378 struct rl_dmaload_arg arg; 1379 struct mbuf *n = NULL; 1380 int error; 1381 1382 if (m == NULL) { 1383 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1384 if (n == NULL) 1385 return (ENOBUFS); 1386 m = n; 1387 } else 1388 m->m_data = m->m_ext.ext_buf; 1389 1390 m->m_len = m->m_pkthdr.len = MCLBYTES; 1391#ifdef RE_FIXUP_RX 1392 /* 1393 * This is part of an evil trick to deal with non-x86 platforms. 1394 * The RealTek chip requires RX buffers to be aligned on 64-bit 1395 * boundaries, but that will hose non-x86 machines. To get around 1396 * this, we leave some empty space at the start of each buffer 1397 * and for non-x86 hosts, we copy the buffer back six bytes 1398 * to achieve word alignment. This is slightly more efficient 1399 * than allocating a new buffer, copying the contents, and 1400 * discarding the old buffer. 1401 */ 1402 m_adj(m, RE_ETHER_ALIGN); 1403#endif 1404 arg.sc = sc; 1405 arg.rl_idx = idx; 1406 arg.rl_maxsegs = 1; 1407 arg.rl_flags = 0; 1408 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1409 1410 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1411 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1412 &arg, BUS_DMA_NOWAIT); 1413 if (error || arg.rl_maxsegs != 1) { 1414 if (n != NULL) 1415 m_freem(n); 1416 return (ENOMEM); 1417 } 1418 1419 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1420 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1421 1422 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1423 sc->rl_ldata.rl_rx_dmamap[idx], 1424 BUS_DMASYNC_PREREAD); 1425 1426 return (0); 1427} 1428 1429#ifdef RE_FIXUP_RX 1430static __inline void 1431re_fixup_rx(m) 1432 struct mbuf *m; 1433{ 1434 int i; 1435 uint16_t *src, *dst; 1436 1437 src = mtod(m, uint16_t *); 1438 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1439 1440 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1441 *dst++ = *src++; 1442 1443 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1444 1445 return; 1446} 1447#endif 1448 1449static int 1450re_tx_list_init(sc) 1451 struct rl_softc *sc; 1452{ 1453 1454 RL_LOCK_ASSERT(sc); 1455 1456 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1457 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1458 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1459 1460 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1461 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1462 sc->rl_ldata.rl_tx_prodidx = 0; 1463 sc->rl_ldata.rl_tx_considx = 0; 1464 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1465 1466 return (0); 1467} 1468 1469static int 1470re_rx_list_init(sc) 1471 struct rl_softc *sc; 1472{ 1473 int i; 1474 1475 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1476 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1477 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1478 1479 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1480 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1481 return (ENOBUFS); 1482 } 1483 1484 /* Flush the RX descriptors */ 1485 1486 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1487 sc->rl_ldata.rl_rx_list_map, 1488 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1489 1490 sc->rl_ldata.rl_rx_prodidx = 0; 1491 sc->rl_head = sc->rl_tail = NULL; 1492 1493 return (0); 1494} 1495 1496/* 1497 * RX handler for C+ and 8169. For the gigE chips, we support 1498 * the reception of jumbo frames that have been fragmented 1499 * across multiple 2K mbuf cluster buffers. 1500 */ 1501static void 1502re_rxeof(sc) 1503 struct rl_softc *sc; 1504{ 1505 struct mbuf *m; 1506 struct ifnet *ifp; 1507 int i, total_len; 1508 struct rl_desc *cur_rx; 1509 u_int32_t rxstat, rxvlan; 1510 1511 RL_LOCK_ASSERT(sc); 1512 1513 ifp = sc->rl_ifp; 1514 i = sc->rl_ldata.rl_rx_prodidx; 1515 1516 /* Invalidate the descriptor memory */ 1517 1518 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1519 sc->rl_ldata.rl_rx_list_map, 1520 BUS_DMASYNC_POSTREAD); 1521 1522 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1523 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1524 m = sc->rl_ldata.rl_rx_mbuf[i]; 1525 total_len = RL_RXBYTES(cur_rx); 1526 rxstat = le32toh(cur_rx->rl_cmdstat); 1527 rxvlan = le32toh(cur_rx->rl_vlanctl); 1528 1529 /* Invalidate the RX mbuf and unload its map */ 1530 1531 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1532 sc->rl_ldata.rl_rx_dmamap[i], 1533 BUS_DMASYNC_POSTWRITE); 1534 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1535 sc->rl_ldata.rl_rx_dmamap[i]); 1536 1537 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1538 m->m_len = RE_RX_DESC_BUFLEN; 1539 if (sc->rl_head == NULL) 1540 sc->rl_head = sc->rl_tail = m; 1541 else { 1542 m->m_flags &= ~M_PKTHDR; 1543 sc->rl_tail->m_next = m; 1544 sc->rl_tail = m; 1545 } 1546 re_newbuf(sc, i, NULL); 1547 RL_DESC_INC(i); 1548 continue; 1549 } 1550 1551 /* 1552 * NOTE: for the 8139C+, the frame length field 1553 * is always 12 bits in size, but for the gigE chips, 1554 * it is 13 bits (since the max RX frame length is 16K). 1555 * Unfortunately, all 32 bits in the status word 1556 * were already used, so to make room for the extra 1557 * length bit, RealTek took out the 'frame alignment 1558 * error' bit and shifted the other status bits 1559 * over one slot. The OWN, EOR, FS and LS bits are 1560 * still in the same places. We have already extracted 1561 * the frame length and checked the OWN bit, so rather 1562 * than using an alternate bit mapping, we shift the 1563 * status bits one space to the right so we can evaluate 1564 * them using the 8169 status as though it was in the 1565 * same format as that of the 8139C+. 1566 */ 1567 if (sc->rl_type == RL_8169) 1568 rxstat >>= 1; 1569 1570 /* 1571 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1572 * set, but if CRC is clear, it will still be a valid frame. 1573 */ 1574 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1575 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1576 ifp->if_ierrors++; 1577 /* 1578 * If this is part of a multi-fragment packet, 1579 * discard all the pieces. 1580 */ 1581 if (sc->rl_head != NULL) { 1582 m_freem(sc->rl_head); 1583 sc->rl_head = sc->rl_tail = NULL; 1584 } 1585 re_newbuf(sc, i, m); 1586 RL_DESC_INC(i); 1587 continue; 1588 } 1589 1590 /* 1591 * If allocating a replacement mbuf fails, 1592 * reload the current one. 1593 */ 1594 1595 if (re_newbuf(sc, i, NULL)) { 1596 ifp->if_ierrors++; 1597 if (sc->rl_head != NULL) { 1598 m_freem(sc->rl_head); 1599 sc->rl_head = sc->rl_tail = NULL; 1600 } 1601 re_newbuf(sc, i, m); 1602 RL_DESC_INC(i); 1603 continue; 1604 } 1605 1606 RL_DESC_INC(i); 1607 1608 if (sc->rl_head != NULL) { 1609 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1610 if (m->m_len == 0) 1611 m->m_len = RE_RX_DESC_BUFLEN; 1612 /* 1613 * Special case: if there's 4 bytes or less 1614 * in this buffer, the mbuf can be discarded: 1615 * the last 4 bytes is the CRC, which we don't 1616 * care about anyway. 1617 */ 1618 if (m->m_len <= ETHER_CRC_LEN) { 1619 sc->rl_tail->m_len -= 1620 (ETHER_CRC_LEN - m->m_len); 1621 m_freem(m); 1622 } else { 1623 m->m_len -= ETHER_CRC_LEN; 1624 m->m_flags &= ~M_PKTHDR; 1625 sc->rl_tail->m_next = m; 1626 } 1627 m = sc->rl_head; 1628 sc->rl_head = sc->rl_tail = NULL; 1629 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1630 } else 1631 m->m_pkthdr.len = m->m_len = 1632 (total_len - ETHER_CRC_LEN); 1633 1634#ifdef RE_FIXUP_RX 1635 re_fixup_rx(m); 1636#endif 1637 ifp->if_ipackets++; 1638 m->m_pkthdr.rcvif = ifp; 1639 1640 /* Do RX checksumming if enabled */ 1641 1642 if (ifp->if_capenable & IFCAP_RXCSUM) { 1643 1644 /* Check IP header checksum */ 1645 if (rxstat & RL_RDESC_STAT_PROTOID) 1646 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1647 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1648 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1649 1650 /* Check TCP/UDP checksum */ 1651 if ((RL_TCPPKT(rxstat) && 1652 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1653 (RL_UDPPKT(rxstat) && 1654 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1655 m->m_pkthdr.csum_flags |= 1656 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1657 m->m_pkthdr.csum_data = 0xffff; 1658 } 1659 } 1660 1661 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1662 VLAN_INPUT_TAG(ifp, m, 1663 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1664 RL_UNLOCK(sc); 1665 (*ifp->if_input)(ifp, m); 1666 RL_LOCK(sc); 1667 } 1668 1669 /* Flush the RX DMA ring */ 1670 1671 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1672 sc->rl_ldata.rl_rx_list_map, 1673 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1674 1675 sc->rl_ldata.rl_rx_prodidx = i; 1676} 1677 1678static void 1679re_txeof(sc) 1680 struct rl_softc *sc; 1681{ 1682 struct ifnet *ifp; 1683 u_int32_t txstat; 1684 int idx; 1685 1686 ifp = sc->rl_ifp; 1687 idx = sc->rl_ldata.rl_tx_considx; 1688 1689 /* Invalidate the TX descriptor list */ 1690 1691 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1692 sc->rl_ldata.rl_tx_list_map, 1693 BUS_DMASYNC_POSTREAD); 1694 1695 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1696 1697 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1698 if (txstat & RL_TDESC_CMD_OWN) 1699 break; 1700 1701 /* 1702 * We only stash mbufs in the last descriptor 1703 * in a fragment chain, which also happens to 1704 * be the only place where the TX status bits 1705 * are valid. 1706 */ 1707 1708 if (txstat & RL_TDESC_CMD_EOF) { 1709 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1710 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1711 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1712 sc->rl_ldata.rl_tx_dmamap[idx]); 1713 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1714 RL_TDESC_STAT_COLCNT)) 1715 ifp->if_collisions++; 1716 if (txstat & RL_TDESC_STAT_TXERRSUM) 1717 ifp->if_oerrors++; 1718 else 1719 ifp->if_opackets++; 1720 } 1721 sc->rl_ldata.rl_tx_free++; 1722 RL_DESC_INC(idx); 1723 } 1724 1725 /* No changes made to the TX ring, so no flush needed */ 1726 1727 if (idx != sc->rl_ldata.rl_tx_considx) { 1728 sc->rl_ldata.rl_tx_considx = idx; 1729 ifp->if_flags &= ~IFF_OACTIVE; 1730 ifp->if_timer = 0; 1731 } 1732 1733 /* 1734 * If not all descriptors have been released reaped yet, 1735 * reload the timer so that we will eventually get another 1736 * interrupt that will cause us to re-enter this routine. 1737 * This is done in case the transmitter has gone idle. 1738 */ 1739 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1740 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1741} 1742 1743static void 1744re_tick(xsc) 1745 void *xsc; 1746{ 1747 struct rl_softc *sc; 1748 1749 sc = xsc; 1750 RL_LOCK(sc); 1751 re_tick_locked(sc); 1752 RL_UNLOCK(sc); 1753} 1754 1755static void 1756re_tick_locked(sc) 1757 struct rl_softc *sc; 1758{ 1759 struct mii_data *mii; 1760 1761 RL_LOCK_ASSERT(sc); 1762 1763 mii = device_get_softc(sc->rl_miibus); 1764 1765 mii_tick(mii); 1766 1767 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1768} 1769 1770#ifdef DEVICE_POLLING 1771static void 1772re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1773{ 1774 struct rl_softc *sc = ifp->if_softc; 1775 1776 RL_LOCK(sc); 1777 re_poll_locked(ifp, cmd, count); 1778 RL_UNLOCK(sc); 1779} 1780 1781static void 1782re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1783{ 1784 struct rl_softc *sc = ifp->if_softc; 1785 1786 RL_LOCK_ASSERT(sc); 1787 1788 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1789 ether_poll_deregister(ifp); 1790 cmd = POLL_DEREGISTER; 1791 } 1792 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1793 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1794 return; 1795 } 1796 1797 sc->rxcycles = count; 1798 re_rxeof(sc); 1799 re_txeof(sc); 1800 1801 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1802 re_start_locked(ifp); 1803 1804 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1805 u_int16_t status; 1806 1807 status = CSR_READ_2(sc, RL_ISR); 1808 if (status == 0xffff) 1809 return; 1810 if (status) 1811 CSR_WRITE_2(sc, RL_ISR, status); 1812 1813 /* 1814 * XXX check behaviour on receiver stalls. 1815 */ 1816 1817 if (status & RL_ISR_SYSTEM_ERR) { 1818 re_reset(sc); 1819 re_init_locked(sc); 1820 } 1821 } 1822} 1823#endif /* DEVICE_POLLING */ 1824 1825static void 1826re_intr(arg) 1827 void *arg; 1828{ 1829 struct rl_softc *sc; 1830 struct ifnet *ifp; 1831 u_int16_t status; 1832 1833 sc = arg; 1834 1835 RL_LOCK(sc); 1836 1837 ifp = sc->rl_ifp; 1838 1839 if (sc->suspended || !(ifp->if_flags & IFF_UP)) 1840 goto done_locked; 1841 1842#ifdef DEVICE_POLLING 1843 if (ifp->if_flags & IFF_POLLING) 1844 goto done_locked; 1845 if ((ifp->if_capenable & IFCAP_POLLING) && 1846 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1847 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1848 re_poll_locked(ifp, 0, 1); 1849 goto done_locked; 1850 } 1851#endif /* DEVICE_POLLING */ 1852 1853 for (;;) { 1854 1855 status = CSR_READ_2(sc, RL_ISR); 1856 /* If the card has gone away the read returns 0xffff. */ 1857 if (status == 0xffff) 1858 break; 1859 if (status) 1860 CSR_WRITE_2(sc, RL_ISR, status); 1861 1862 if ((status & RL_INTRS_CPLUS) == 0) 1863 break; 1864 1865 if ((status & RL_ISR_RX_OK) || 1866 (status & RL_ISR_RX_ERR)) 1867 re_rxeof(sc); 1868 1869 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1870 (status & RL_ISR_TX_ERR) || 1871 (status & RL_ISR_TX_DESC_UNAVAIL)) 1872 re_txeof(sc); 1873 1874 if (status & RL_ISR_SYSTEM_ERR) { 1875 re_reset(sc); 1876 re_init_locked(sc); 1877 } 1878 1879 if (status & RL_ISR_LINKCHG) { 1880 untimeout(re_tick, sc, sc->rl_stat_ch); 1881 re_tick_locked(sc); 1882 } 1883 } 1884 1885 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1886 re_start_locked(ifp); 1887 1888done_locked: 1889 RL_UNLOCK(sc); 1890} 1891 1892static int 1893re_encap(sc, m_head, idx) 1894 struct rl_softc *sc; 1895 struct mbuf **m_head; 1896 int *idx; 1897{ 1898 struct mbuf *m_new = NULL; 1899 struct rl_dmaload_arg arg; 1900 bus_dmamap_t map; 1901 int error; 1902 struct m_tag *mtag; 1903 1904 RL_LOCK_ASSERT(sc); 1905 1906 if (sc->rl_ldata.rl_tx_free <= 4) 1907 return (EFBIG); 1908 1909 /* 1910 * Set up checksum offload. Note: checksum offload bits must 1911 * appear in all descriptors of a multi-descriptor transmit 1912 * attempt. This is according to testing done with an 8169 1913 * chip. This is a requirement. 1914 */ 1915 1916 arg.rl_flags = 0; 1917 1918 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1919 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1920 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1921 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1922 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1923 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1924 1925 arg.sc = sc; 1926 arg.rl_idx = *idx; 1927 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1928 if (arg.rl_maxsegs > 4) 1929 arg.rl_maxsegs -= 4; 1930 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1931 1932 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1933 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1934 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1935 1936 if (error && error != EFBIG) { 1937 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1938 return (ENOBUFS); 1939 } 1940 1941 /* Too many segments to map, coalesce into a single mbuf */ 1942 1943 if (error || arg.rl_maxsegs == 0) { 1944 m_new = m_defrag(*m_head, M_DONTWAIT); 1945 if (m_new == NULL) 1946 return (ENOBUFS); 1947 else 1948 *m_head = m_new; 1949 1950 arg.sc = sc; 1951 arg.rl_idx = *idx; 1952 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1953 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1954 1955 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1956 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1957 if (error) { 1958 printf("re%d: can't map mbuf (error %d)\n", 1959 sc->rl_unit, error); 1960 return (EFBIG); 1961 } 1962 } 1963 1964 /* 1965 * Insure that the map for this transmission 1966 * is placed at the array index of the last descriptor 1967 * in this chain. (Swap last and first dmamaps.) 1968 */ 1969 sc->rl_ldata.rl_tx_dmamap[*idx] = 1970 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1971 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1972 1973 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 1974 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1975 1976 /* 1977 * Set up hardware VLAN tagging. Note: vlan tag info must 1978 * appear in the first descriptor of a multi-descriptor 1979 * transmission attempt. 1980 */ 1981 1982 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head); 1983 if (mtag != NULL) 1984 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1985 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1986 1987 /* Transfer ownership of packet to the chip. */ 1988 1989 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1990 htole32(RL_TDESC_CMD_OWN); 1991 if (*idx != arg.rl_idx) 1992 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1993 htole32(RL_TDESC_CMD_OWN); 1994 1995 RL_DESC_INC(arg.rl_idx); 1996 *idx = arg.rl_idx; 1997 1998 return (0); 1999} 2000 2001static void 2002re_start(ifp) 2003 struct ifnet *ifp; 2004{ 2005 struct rl_softc *sc; 2006 2007 sc = ifp->if_softc; 2008 RL_LOCK(sc); 2009 re_start_locked(ifp); 2010 RL_UNLOCK(sc); 2011} 2012 2013/* 2014 * Main transmit routine for C+ and gigE NICs. 2015 */ 2016static void 2017re_start_locked(ifp) 2018 struct ifnet *ifp; 2019{ 2020 struct rl_softc *sc; 2021 struct mbuf *m_head = NULL; 2022 int idx, queued = 0; 2023 2024 sc = ifp->if_softc; 2025 2026 RL_LOCK_ASSERT(sc); 2027 2028 idx = sc->rl_ldata.rl_tx_prodidx; 2029 2030 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2031 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2032 if (m_head == NULL) 2033 break; 2034 2035 if (re_encap(sc, &m_head, &idx)) { 2036 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2037 ifp->if_flags |= IFF_OACTIVE; 2038 break; 2039 } 2040 2041 /* 2042 * If there's a BPF listener, bounce a copy of this frame 2043 * to him. 2044 */ 2045 BPF_MTAP(ifp, m_head); 2046 2047 queued++; 2048 } 2049 2050 if (queued == 0) 2051 return; 2052 2053 /* Flush the TX descriptors */ 2054 2055 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2056 sc->rl_ldata.rl_tx_list_map, 2057 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2058 2059 sc->rl_ldata.rl_tx_prodidx = idx; 2060 2061 /* 2062 * RealTek put the TX poll request register in a different 2063 * location on the 8169 gigE chip. I don't know why. 2064 */ 2065 2066 if (sc->rl_type == RL_8169) 2067 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2068 else 2069 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2070 2071 /* 2072 * Use the countdown timer for interrupt moderation. 2073 * 'TX done' interrupts are disabled. Instead, we reset the 2074 * countdown timer, which will begin counting until it hits 2075 * the value in the TIMERINT register, and then trigger an 2076 * interrupt. Each time we write to the TIMERCNT register, 2077 * the timer count is reset to 0. 2078 */ 2079 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2080 2081 /* 2082 * Set a timeout in case the chip goes out to lunch. 2083 */ 2084 ifp->if_timer = 5; 2085} 2086 2087static void 2088re_init(xsc) 2089 void *xsc; 2090{ 2091 struct rl_softc *sc = xsc; 2092 2093 RL_LOCK(sc); 2094 re_init_locked(sc); 2095 RL_UNLOCK(sc); 2096} 2097 2098static void 2099re_init_locked(sc) 2100 struct rl_softc *sc; 2101{ 2102 struct ifnet *ifp = sc->rl_ifp; 2103 struct mii_data *mii; 2104 u_int32_t rxcfg = 0; 2105 2106 RL_LOCK_ASSERT(sc); 2107 2108 mii = device_get_softc(sc->rl_miibus); 2109 2110 /* 2111 * Cancel pending I/O and free all RX/TX buffers. 2112 */ 2113 re_stop(sc); 2114 2115 /* 2116 * Enable C+ RX and TX mode, as well as VLAN stripping and 2117 * RX checksum offload. We must configure the C+ register 2118 * before all others. 2119 */ 2120 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2121 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2122 RL_CPLUSCMD_VLANSTRIP| 2123 (ifp->if_capenable & IFCAP_RXCSUM ? 2124 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2125 2126 /* 2127 * Init our MAC address. Even though the chipset 2128 * documentation doesn't mention it, we need to enter "Config 2129 * register write enable" mode to modify the ID registers. 2130 */ 2131 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2132 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2133 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[0])); 2134 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2135 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[4])); 2136 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2137 2138 /* 2139 * For C+ mode, initialize the RX descriptors and mbufs. 2140 */ 2141 re_rx_list_init(sc); 2142 re_tx_list_init(sc); 2143 2144 /* 2145 * Enable transmit and receive. 2146 */ 2147 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2148 2149 /* 2150 * Set the initial TX and RX configuration. 2151 */ 2152 if (sc->rl_testmode) { 2153 if (sc->rl_type == RL_8169) 2154 CSR_WRITE_4(sc, RL_TXCFG, 2155 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2156 else 2157 CSR_WRITE_4(sc, RL_TXCFG, 2158 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2159 } else 2160 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2161 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2162 2163 /* Set the individual bit to receive frames for this host only. */ 2164 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2165 rxcfg |= RL_RXCFG_RX_INDIV; 2166 2167 /* If we want promiscuous mode, set the allframes bit. */ 2168 if (ifp->if_flags & IFF_PROMISC) 2169 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2170 else 2171 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2172 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2173 2174 /* 2175 * Set capture broadcast bit to capture broadcast frames. 2176 */ 2177 if (ifp->if_flags & IFF_BROADCAST) 2178 rxcfg |= RL_RXCFG_RX_BROAD; 2179 else 2180 rxcfg &= ~RL_RXCFG_RX_BROAD; 2181 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2182 2183 /* 2184 * Program the multicast filter, if necessary. 2185 */ 2186 re_setmulti(sc); 2187 2188#ifdef DEVICE_POLLING 2189 /* 2190 * Disable interrupts if we are polling. 2191 */ 2192 if (ifp->if_flags & IFF_POLLING) 2193 CSR_WRITE_2(sc, RL_IMR, 0); 2194 else /* otherwise ... */ 2195#endif /* DEVICE_POLLING */ 2196 /* 2197 * Enable interrupts. 2198 */ 2199 if (sc->rl_testmode) 2200 CSR_WRITE_2(sc, RL_IMR, 0); 2201 else 2202 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2203 2204 /* Set initial TX threshold */ 2205 sc->rl_txthresh = RL_TX_THRESH_INIT; 2206 2207 /* Start RX/TX process. */ 2208 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2209#ifdef notdef 2210 /* Enable receiver and transmitter. */ 2211 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2212#endif 2213 /* 2214 * Load the addresses of the RX and TX lists into the chip. 2215 */ 2216 2217 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2218 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2219 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2220 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2221 2222 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2223 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2224 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2225 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2226 2227 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2228 2229 /* 2230 * Initialize the timer interrupt register so that 2231 * a timer interrupt will be generated once the timer 2232 * reaches a certain number of ticks. The timer is 2233 * reloaded on each transmit. This gives us TX interrupt 2234 * moderation, which dramatically improves TX frame rate. 2235 */ 2236 if (sc->rl_type == RL_8169) 2237 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2238 else 2239 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2240 2241 /* 2242 * For 8169 gigE NICs, set the max allowed RX packet 2243 * size so we can receive jumbo frames. 2244 */ 2245 if (sc->rl_type == RL_8169) 2246 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2247 2248 if (sc->rl_testmode) 2249 return; 2250 2251 mii_mediachg(mii); 2252 2253 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2254 2255 ifp->if_flags |= IFF_RUNNING; 2256 ifp->if_flags &= ~IFF_OACTIVE; 2257 2258 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2259} 2260 2261/* 2262 * Set media options. 2263 */ 2264static int 2265re_ifmedia_upd(ifp) 2266 struct ifnet *ifp; 2267{ 2268 struct rl_softc *sc; 2269 struct mii_data *mii; 2270 2271 sc = ifp->if_softc; 2272 mii = device_get_softc(sc->rl_miibus); 2273 mii_mediachg(mii); 2274 2275 return (0); 2276} 2277 2278/* 2279 * Report current media status. 2280 */ 2281static void 2282re_ifmedia_sts(ifp, ifmr) 2283 struct ifnet *ifp; 2284 struct ifmediareq *ifmr; 2285{ 2286 struct rl_softc *sc; 2287 struct mii_data *mii; 2288 2289 sc = ifp->if_softc; 2290 mii = device_get_softc(sc->rl_miibus); 2291 2292 mii_pollstat(mii); 2293 ifmr->ifm_active = mii->mii_media_active; 2294 ifmr->ifm_status = mii->mii_media_status; 2295} 2296 2297static int 2298re_ioctl(ifp, command, data) 2299 struct ifnet *ifp; 2300 u_long command; 2301 caddr_t data; 2302{ 2303 struct rl_softc *sc = ifp->if_softc; 2304 struct ifreq *ifr = (struct ifreq *) data; 2305 struct mii_data *mii; 2306 int error = 0; 2307 2308 switch (command) { 2309 case SIOCSIFMTU: 2310 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2311 error = EINVAL; 2312 ifp->if_mtu = ifr->ifr_mtu; 2313 break; 2314 case SIOCSIFFLAGS: 2315 RL_LOCK(sc); 2316 if (ifp->if_flags & IFF_UP) 2317 re_init_locked(sc); 2318 else if (ifp->if_flags & IFF_RUNNING) 2319 re_stop(sc); 2320 RL_UNLOCK(sc); 2321 error = 0; 2322 break; 2323 case SIOCADDMULTI: 2324 case SIOCDELMULTI: 2325 RL_LOCK(sc); 2326 re_setmulti(sc); 2327 RL_UNLOCK(sc); 2328 error = 0; 2329 break; 2330 case SIOCGIFMEDIA: 2331 case SIOCSIFMEDIA: 2332 mii = device_get_softc(sc->rl_miibus); 2333 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2334 break; 2335 case SIOCSIFCAP: 2336 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2337 ifp->if_capenable |= 2338 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2339 if (ifp->if_capenable & IFCAP_TXCSUM) 2340 ifp->if_hwassist = RE_CSUM_FEATURES; 2341 else 2342 ifp->if_hwassist = 0; 2343 if (ifp->if_flags & IFF_RUNNING) 2344 re_init(sc); 2345 break; 2346 default: 2347 error = ether_ioctl(ifp, command, data); 2348 break; 2349 } 2350 2351 return (error); 2352} 2353 2354static void 2355re_watchdog(ifp) 2356 struct ifnet *ifp; 2357{ 2358 struct rl_softc *sc; 2359 2360 sc = ifp->if_softc; 2361 RL_LOCK(sc); 2362 printf("re%d: watchdog timeout\n", sc->rl_unit); 2363 ifp->if_oerrors++; 2364 2365 re_txeof(sc); 2366 re_rxeof(sc); 2367 re_init_locked(sc); 2368 2369 RL_UNLOCK(sc); 2370} 2371 2372/* 2373 * Stop the adapter and free any mbufs allocated to the 2374 * RX and TX lists. 2375 */ 2376static void 2377re_stop(sc) 2378 struct rl_softc *sc; 2379{ 2380 register int i; 2381 struct ifnet *ifp; 2382 2383 RL_LOCK_ASSERT(sc); 2384 2385 ifp = sc->rl_ifp; 2386 ifp->if_timer = 0; 2387 2388 untimeout(re_tick, sc, sc->rl_stat_ch); 2389 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2390#ifdef DEVICE_POLLING 2391 ether_poll_deregister(ifp); 2392#endif /* DEVICE_POLLING */ 2393 2394 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2395 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2396 2397 if (sc->rl_head != NULL) { 2398 m_freem(sc->rl_head); 2399 sc->rl_head = sc->rl_tail = NULL; 2400 } 2401 2402 /* Free the TX list buffers. */ 2403 2404 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2405 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2406 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2407 sc->rl_ldata.rl_tx_dmamap[i]); 2408 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2409 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2410 } 2411 } 2412 2413 /* Free the RX list buffers. */ 2414 2415 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2416 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2417 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2418 sc->rl_ldata.rl_rx_dmamap[i]); 2419 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2420 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2421 } 2422 } 2423} 2424 2425/* 2426 * Device suspend routine. Stop the interface and save some PCI 2427 * settings in case the BIOS doesn't restore them properly on 2428 * resume. 2429 */ 2430static int 2431re_suspend(dev) 2432 device_t dev; 2433{ 2434 struct rl_softc *sc; 2435 2436 sc = device_get_softc(dev); 2437 2438 RL_LOCK(sc); 2439 re_stop(sc); 2440 sc->suspended = 1; 2441 RL_UNLOCK(sc); 2442 2443 return (0); 2444} 2445 2446/* 2447 * Device resume routine. Restore some PCI settings in case the BIOS 2448 * doesn't, re-enable busmastering, and restart the interface if 2449 * appropriate. 2450 */ 2451static int 2452re_resume(dev) 2453 device_t dev; 2454{ 2455 struct rl_softc *sc; 2456 struct ifnet *ifp; 2457 2458 sc = device_get_softc(dev); 2459 2460 RL_LOCK(sc); 2461 2462 ifp = sc->rl_ifp; 2463 2464 /* reinitialize interface if necessary */ 2465 if (ifp->if_flags & IFF_UP) 2466 re_init_locked(sc); 2467 2468 sc->suspended = 0; 2469 RL_UNLOCK(sc); 2470 2471 return (0); 2472} 2473 2474/* 2475 * Stop all chip I/O so that the kernel's probe routines don't 2476 * get confused by errant DMAs when rebooting. 2477 */ 2478static void 2479re_shutdown(dev) 2480 device_t dev; 2481{ 2482 struct rl_softc *sc; 2483 2484 sc = device_get_softc(dev); 2485 2486 RL_LOCK(sc); 2487 re_stop(sc); 2488 RL_UNLOCK(sc); 2489} 2490