if_re.c revision 142890
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 142890 2005-03-01 08:58:06Z imp $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#include <sys/param.h> 112#include <sys/endian.h> 113#include <sys/systm.h> 114#include <sys/sockio.h> 115#include <sys/mbuf.h> 116#include <sys/malloc.h> 117#include <sys/module.h> 118#include <sys/kernel.h> 119#include <sys/socket.h> 120 121#include <net/if.h> 122#include <net/if_arp.h> 123#include <net/ethernet.h> 124#include <net/if_dl.h> 125#include <net/if_media.h> 126#include <net/if_vlan_var.h> 127 128#include <net/bpf.h> 129 130#include <machine/bus_pio.h> 131#include <machine/bus_memio.h> 132#include <machine/bus.h> 133#include <machine/resource.h> 134#include <sys/bus.h> 135#include <sys/rman.h> 136 137#include <dev/mii/mii.h> 138#include <dev/mii/miivar.h> 139 140#include <dev/pci/pcireg.h> 141#include <dev/pci/pcivar.h> 142 143MODULE_DEPEND(re, pci, 1, 1, 1); 144MODULE_DEPEND(re, ether, 1, 1, 1); 145MODULE_DEPEND(re, miibus, 1, 1, 1); 146 147/* "controller miibus0" required. See GENERIC if you get errors here. */ 148#include "miibus_if.h" 149 150/* 151 * Default to using PIO access for this driver. 152 */ 153#define RE_USEIOSPACE 154 155#include <pci/if_rlreg.h> 156 157#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 159/* 160 * Various supported device vendors/types and their names. 161 */ 162static struct rl_type re_devs[] = { 163 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 164 "RealTek 8139C+ 10/100BaseTX" }, 165 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 166 "RealTek 8169 Gigabit Ethernet" }, 167 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 168 "RealTek 8169S Single-chip Gigabit Ethernet" }, 169 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB, 170 "RealTek 8169SB Single-chip Gigabit Ethernet" }, 171 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 172 "RealTek 8110S Single-chip Gigabit Ethernet" }, 173 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 174 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 175 { 0, 0, 0, NULL } 176}; 177 178static struct rl_hwrev re_hwrevs[] = { 179 { RL_HWREV_8139, RL_8139, "" }, 180 { RL_HWREV_8139A, RL_8139, "A" }, 181 { RL_HWREV_8139AG, RL_8139, "A-G" }, 182 { RL_HWREV_8139B, RL_8139, "B" }, 183 { RL_HWREV_8130, RL_8139, "8130" }, 184 { RL_HWREV_8139C, RL_8139, "C" }, 185 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 186 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 187 { RL_HWREV_8169, RL_8169, "8169"}, 188 { RL_HWREV_8169S, RL_8169, "8169S"}, 189 { RL_HWREV_8169SB, RL_8169, "8169SB"}, 190 { RL_HWREV_8110S, RL_8169, "8110S"}, 191 { RL_HWREV_8100, RL_8139, "8100"}, 192 { RL_HWREV_8101, RL_8139, "8101"}, 193 { 0, 0, NULL } 194}; 195 196static int re_probe (device_t); 197static int re_attach (device_t); 198static int re_detach (device_t); 199 200static int re_encap (struct rl_softc *, struct mbuf **, int *); 201 202static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 203static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 204 bus_size_t, int); 205static int re_allocmem (device_t, struct rl_softc *); 206static int re_newbuf (struct rl_softc *, int, struct mbuf *); 207static int re_rx_list_init (struct rl_softc *); 208static int re_tx_list_init (struct rl_softc *); 209#ifdef RE_FIXUP_RX 210static __inline void re_fixup_rx 211 (struct mbuf *); 212#endif 213static void re_rxeof (struct rl_softc *); 214static void re_txeof (struct rl_softc *); 215#ifdef DEVICE_POLLING 216static void re_poll (struct ifnet *, enum poll_cmd, int); 217static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 218#endif 219static void re_intr (void *); 220static void re_tick (void *); 221static void re_tick_locked (struct rl_softc *); 222static void re_start (struct ifnet *); 223static void re_start_locked (struct ifnet *); 224static int re_ioctl (struct ifnet *, u_long, caddr_t); 225static void re_init (void *); 226static void re_init_locked (struct rl_softc *); 227static void re_stop (struct rl_softc *); 228static void re_watchdog (struct ifnet *); 229static int re_suspend (device_t); 230static int re_resume (device_t); 231static void re_shutdown (device_t); 232static int re_ifmedia_upd (struct ifnet *); 233static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 234 235static void re_eeprom_putbyte (struct rl_softc *, int); 236static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 237static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 238static int re_gmii_readreg (device_t, int, int); 239static int re_gmii_writereg (device_t, int, int, int); 240 241static int re_miibus_readreg (device_t, int, int); 242static int re_miibus_writereg (device_t, int, int, int); 243static void re_miibus_statchg (device_t); 244 245static void re_setmulti (struct rl_softc *); 246static void re_reset (struct rl_softc *); 247 248static int re_diag (struct rl_softc *); 249 250#ifdef RE_USEIOSPACE 251#define RL_RES SYS_RES_IOPORT 252#define RL_RID RL_PCI_LOIO 253#else 254#define RL_RES SYS_RES_MEMORY 255#define RL_RID RL_PCI_LOMEM 256#endif 257 258static device_method_t re_methods[] = { 259 /* Device interface */ 260 DEVMETHOD(device_probe, re_probe), 261 DEVMETHOD(device_attach, re_attach), 262 DEVMETHOD(device_detach, re_detach), 263 DEVMETHOD(device_suspend, re_suspend), 264 DEVMETHOD(device_resume, re_resume), 265 DEVMETHOD(device_shutdown, re_shutdown), 266 267 /* bus interface */ 268 DEVMETHOD(bus_print_child, bus_generic_print_child), 269 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 270 271 /* MII interface */ 272 DEVMETHOD(miibus_readreg, re_miibus_readreg), 273 DEVMETHOD(miibus_writereg, re_miibus_writereg), 274 DEVMETHOD(miibus_statchg, re_miibus_statchg), 275 276 { 0, 0 } 277}; 278 279static driver_t re_driver = { 280 "re", 281 re_methods, 282 sizeof(struct rl_softc) 283}; 284 285static devclass_t re_devclass; 286 287DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 288DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 289DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 290 291#define EE_SET(x) \ 292 CSR_WRITE_1(sc, RL_EECMD, \ 293 CSR_READ_1(sc, RL_EECMD) | x) 294 295#define EE_CLR(x) \ 296 CSR_WRITE_1(sc, RL_EECMD, \ 297 CSR_READ_1(sc, RL_EECMD) & ~x) 298 299/* 300 * Send a read command and address to the EEPROM, check for ACK. 301 */ 302static void 303re_eeprom_putbyte(sc, addr) 304 struct rl_softc *sc; 305 int addr; 306{ 307 register int d, i; 308 309 d = addr | sc->rl_eecmd_read; 310 311 /* 312 * Feed in each bit and strobe the clock. 313 */ 314 for (i = 0x400; i; i >>= 1) { 315 if (d & i) { 316 EE_SET(RL_EE_DATAIN); 317 } else { 318 EE_CLR(RL_EE_DATAIN); 319 } 320 DELAY(100); 321 EE_SET(RL_EE_CLK); 322 DELAY(150); 323 EE_CLR(RL_EE_CLK); 324 DELAY(100); 325 } 326} 327 328/* 329 * Read a word of data stored in the EEPROM at address 'addr.' 330 */ 331static void 332re_eeprom_getword(sc, addr, dest) 333 struct rl_softc *sc; 334 int addr; 335 u_int16_t *dest; 336{ 337 register int i; 338 u_int16_t word = 0; 339 340 /* Enter EEPROM access mode. */ 341 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 342 343 /* 344 * Send address of word we want to read. 345 */ 346 re_eeprom_putbyte(sc, addr); 347 348 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 349 350 /* 351 * Start reading bits from EEPROM. 352 */ 353 for (i = 0x8000; i; i >>= 1) { 354 EE_SET(RL_EE_CLK); 355 DELAY(100); 356 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 357 word |= i; 358 EE_CLR(RL_EE_CLK); 359 DELAY(100); 360 } 361 362 /* Turn off EEPROM access mode. */ 363 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 364 365 *dest = word; 366} 367 368/* 369 * Read a sequence of words from the EEPROM. 370 */ 371static void 372re_read_eeprom(sc, dest, off, cnt, swap) 373 struct rl_softc *sc; 374 caddr_t dest; 375 int off; 376 int cnt; 377 int swap; 378{ 379 int i; 380 u_int16_t word = 0, *ptr; 381 382 for (i = 0; i < cnt; i++) { 383 re_eeprom_getword(sc, off + i, &word); 384 ptr = (u_int16_t *)(dest + (i * 2)); 385 if (swap) 386 *ptr = ntohs(word); 387 else 388 *ptr = word; 389 } 390} 391 392static int 393re_gmii_readreg(dev, phy, reg) 394 device_t dev; 395 int phy, reg; 396{ 397 struct rl_softc *sc; 398 u_int32_t rval; 399 int i; 400 401 if (phy != 1) 402 return (0); 403 404 sc = device_get_softc(dev); 405 406 /* Let the rgephy driver read the GMEDIASTAT register */ 407 408 if (reg == RL_GMEDIASTAT) { 409 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 410 return (rval); 411 } 412 413 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 414 DELAY(1000); 415 416 for (i = 0; i < RL_TIMEOUT; i++) { 417 rval = CSR_READ_4(sc, RL_PHYAR); 418 if (rval & RL_PHYAR_BUSY) 419 break; 420 DELAY(100); 421 } 422 423 if (i == RL_TIMEOUT) { 424 printf ("re%d: PHY read failed\n", sc->rl_unit); 425 return (0); 426 } 427 428 return (rval & RL_PHYAR_PHYDATA); 429} 430 431static int 432re_gmii_writereg(dev, phy, reg, data) 433 device_t dev; 434 int phy, reg, data; 435{ 436 struct rl_softc *sc; 437 u_int32_t rval; 438 int i; 439 440 sc = device_get_softc(dev); 441 442 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 443 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 444 DELAY(1000); 445 446 for (i = 0; i < RL_TIMEOUT; i++) { 447 rval = CSR_READ_4(sc, RL_PHYAR); 448 if (!(rval & RL_PHYAR_BUSY)) 449 break; 450 DELAY(100); 451 } 452 453 if (i == RL_TIMEOUT) { 454 printf ("re%d: PHY write failed\n", sc->rl_unit); 455 return (0); 456 } 457 458 return (0); 459} 460 461static int 462re_miibus_readreg(dev, phy, reg) 463 device_t dev; 464 int phy, reg; 465{ 466 struct rl_softc *sc; 467 u_int16_t rval = 0; 468 u_int16_t re8139_reg = 0; 469 470 sc = device_get_softc(dev); 471 472 if (sc->rl_type == RL_8169) { 473 rval = re_gmii_readreg(dev, phy, reg); 474 return (rval); 475 } 476 477 /* Pretend the internal PHY is only at address 0 */ 478 if (phy) { 479 return (0); 480 } 481 switch (reg) { 482 case MII_BMCR: 483 re8139_reg = RL_BMCR; 484 break; 485 case MII_BMSR: 486 re8139_reg = RL_BMSR; 487 break; 488 case MII_ANAR: 489 re8139_reg = RL_ANAR; 490 break; 491 case MII_ANER: 492 re8139_reg = RL_ANER; 493 break; 494 case MII_ANLPAR: 495 re8139_reg = RL_LPAR; 496 break; 497 case MII_PHYIDR1: 498 case MII_PHYIDR2: 499 return (0); 500 /* 501 * Allow the rlphy driver to read the media status 502 * register. If we have a link partner which does not 503 * support NWAY, this is the register which will tell 504 * us the results of parallel detection. 505 */ 506 case RL_MEDIASTAT: 507 rval = CSR_READ_1(sc, RL_MEDIASTAT); 508 return (rval); 509 default: 510 printf("re%d: bad phy register\n", sc->rl_unit); 511 return (0); 512 } 513 rval = CSR_READ_2(sc, re8139_reg); 514 return (rval); 515} 516 517static int 518re_miibus_writereg(dev, phy, reg, data) 519 device_t dev; 520 int phy, reg, data; 521{ 522 struct rl_softc *sc; 523 u_int16_t re8139_reg = 0; 524 int rval = 0; 525 526 sc = device_get_softc(dev); 527 528 if (sc->rl_type == RL_8169) { 529 rval = re_gmii_writereg(dev, phy, reg, data); 530 return (rval); 531 } 532 533 /* Pretend the internal PHY is only at address 0 */ 534 if (phy) 535 return (0); 536 537 switch (reg) { 538 case MII_BMCR: 539 re8139_reg = RL_BMCR; 540 break; 541 case MII_BMSR: 542 re8139_reg = RL_BMSR; 543 break; 544 case MII_ANAR: 545 re8139_reg = RL_ANAR; 546 break; 547 case MII_ANER: 548 re8139_reg = RL_ANER; 549 break; 550 case MII_ANLPAR: 551 re8139_reg = RL_LPAR; 552 break; 553 case MII_PHYIDR1: 554 case MII_PHYIDR2: 555 return (0); 556 break; 557 default: 558 printf("re%d: bad phy register\n", sc->rl_unit); 559 return (0); 560 } 561 CSR_WRITE_2(sc, re8139_reg, data); 562 return (0); 563} 564 565static void 566re_miibus_statchg(dev) 567 device_t dev; 568{ 569 570} 571 572/* 573 * Program the 64-bit multicast hash filter. 574 */ 575static void 576re_setmulti(sc) 577 struct rl_softc *sc; 578{ 579 struct ifnet *ifp; 580 int h = 0; 581 u_int32_t hashes[2] = { 0, 0 }; 582 struct ifmultiaddr *ifma; 583 u_int32_t rxfilt; 584 int mcnt = 0; 585 586 RL_LOCK_ASSERT(sc); 587 588 ifp = &sc->arpcom.ac_if; 589 590 rxfilt = CSR_READ_4(sc, RL_RXCFG); 591 592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 593 rxfilt |= RL_RXCFG_RX_MULTI; 594 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 595 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 596 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 597 return; 598 } 599 600 /* first, zot all the existing hash bits */ 601 CSR_WRITE_4(sc, RL_MAR0, 0); 602 CSR_WRITE_4(sc, RL_MAR4, 0); 603 604 /* now program new ones */ 605 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 606 if (ifma->ifma_addr->sa_family != AF_LINK) 607 continue; 608 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 609 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 610 if (h < 32) 611 hashes[0] |= (1 << h); 612 else 613 hashes[1] |= (1 << (h - 32)); 614 mcnt++; 615 } 616 617 if (mcnt) 618 rxfilt |= RL_RXCFG_RX_MULTI; 619 else 620 rxfilt &= ~RL_RXCFG_RX_MULTI; 621 622 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 623 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 624 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 625} 626 627static void 628re_reset(sc) 629 struct rl_softc *sc; 630{ 631 register int i; 632 633 RL_LOCK_ASSERT(sc); 634 635 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 636 637 for (i = 0; i < RL_TIMEOUT; i++) { 638 DELAY(10); 639 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 640 break; 641 } 642 if (i == RL_TIMEOUT) 643 printf("re%d: reset never completed!\n", sc->rl_unit); 644 645 CSR_WRITE_1(sc, 0x82, 1); 646} 647 648/* 649 * The following routine is designed to test for a defect on some 650 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 651 * lines connected to the bus, however for a 32-bit only card, they 652 * should be pulled high. The result of this defect is that the 653 * NIC will not work right if you plug it into a 64-bit slot: DMA 654 * operations will be done with 64-bit transfers, which will fail 655 * because the 64-bit data lines aren't connected. 656 * 657 * There's no way to work around this (short of talking a soldering 658 * iron to the board), however we can detect it. The method we use 659 * here is to put the NIC into digital loopback mode, set the receiver 660 * to promiscuous mode, and then try to send a frame. We then compare 661 * the frame data we sent to what was received. If the data matches, 662 * then the NIC is working correctly, otherwise we know the user has 663 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 664 * slot. In the latter case, there's no way the NIC can work correctly, 665 * so we print out a message on the console and abort the device attach. 666 */ 667 668static int 669re_diag(sc) 670 struct rl_softc *sc; 671{ 672 struct ifnet *ifp = &sc->arpcom.ac_if; 673 struct mbuf *m0; 674 struct ether_header *eh; 675 struct rl_desc *cur_rx; 676 u_int16_t status; 677 u_int32_t rxstat; 678 int total_len, i, error = 0; 679 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 680 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 681 682 /* Allocate a single mbuf */ 683 MGETHDR(m0, M_DONTWAIT, MT_DATA); 684 if (m0 == NULL) 685 return (ENOBUFS); 686 687 RL_LOCK(sc); 688 689 /* 690 * Initialize the NIC in test mode. This sets the chip up 691 * so that it can send and receive frames, but performs the 692 * following special functions: 693 * - Puts receiver in promiscuous mode 694 * - Enables digital loopback mode 695 * - Leaves interrupts turned off 696 */ 697 698 ifp->if_flags |= IFF_PROMISC; 699 sc->rl_testmode = 1; 700 re_init_locked(sc); 701 re_stop(sc); 702 DELAY(100000); 703 re_init_locked(sc); 704 705 /* Put some data in the mbuf */ 706 707 eh = mtod(m0, struct ether_header *); 708 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 709 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 710 eh->ether_type = htons(ETHERTYPE_IP); 711 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 712 713 /* 714 * Queue the packet, start transmission. 715 * Note: IF_HANDOFF() ultimately calls re_start() for us. 716 */ 717 718 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 719 RL_UNLOCK(sc); 720 IF_HANDOFF(&ifp->if_snd, m0, ifp); 721 RL_LOCK(sc); 722 m0 = NULL; 723 724 /* Wait for it to propagate through the chip */ 725 726 DELAY(100000); 727 for (i = 0; i < RL_TIMEOUT; i++) { 728 status = CSR_READ_2(sc, RL_ISR); 729 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 730 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 731 break; 732 DELAY(10); 733 } 734 735 if (i == RL_TIMEOUT) { 736 printf("re%d: diagnostic failed, failed to receive packet " 737 "in loopback mode\n", sc->rl_unit); 738 error = EIO; 739 goto done; 740 } 741 742 /* 743 * The packet should have been dumped into the first 744 * entry in the RX DMA ring. Grab it from there. 745 */ 746 747 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 748 sc->rl_ldata.rl_rx_list_map, 749 BUS_DMASYNC_POSTREAD); 750 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 751 sc->rl_ldata.rl_rx_dmamap[0], 752 BUS_DMASYNC_POSTWRITE); 753 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 754 sc->rl_ldata.rl_rx_dmamap[0]); 755 756 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 757 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 758 eh = mtod(m0, struct ether_header *); 759 760 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 761 total_len = RL_RXBYTES(cur_rx); 762 rxstat = le32toh(cur_rx->rl_cmdstat); 763 764 if (total_len != ETHER_MIN_LEN) { 765 printf("re%d: diagnostic failed, received short packet\n", 766 sc->rl_unit); 767 error = EIO; 768 goto done; 769 } 770 771 /* Test that the received packet data matches what we sent. */ 772 773 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 774 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 775 ntohs(eh->ether_type) != ETHERTYPE_IP) { 776 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 777 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 778 dst, ":", src, ":", ETHERTYPE_IP); 779 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 780 eh->ether_dhost, ":", eh->ether_shost, ":", 781 ntohs(eh->ether_type)); 782 printf("re%d: You may have a defective 32-bit NIC plugged " 783 "into a 64-bit PCI slot.\n", sc->rl_unit); 784 printf("re%d: Please re-install the NIC in a 32-bit slot " 785 "for proper operation.\n", sc->rl_unit); 786 printf("re%d: Read the re(4) man page for more details.\n", 787 sc->rl_unit); 788 error = EIO; 789 } 790 791done: 792 /* Turn interface off, release resources */ 793 794 sc->rl_testmode = 0; 795 ifp->if_flags &= ~IFF_PROMISC; 796 re_stop(sc); 797 if (m0 != NULL) 798 m_freem(m0); 799 800 RL_UNLOCK(sc); 801 802 return (error); 803} 804 805/* 806 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 807 * IDs against our list and return a device name if we find a match. 808 */ 809static int 810re_probe(dev) 811 device_t dev; 812{ 813 struct rl_type *t; 814 struct rl_softc *sc; 815 int rid; 816 u_int32_t hwrev; 817 818 t = re_devs; 819 sc = device_get_softc(dev); 820 821 while (t->rl_name != NULL) { 822 if ((pci_get_vendor(dev) == t->rl_vid) && 823 (pci_get_device(dev) == t->rl_did)) { 824 825 /* 826 * Temporarily map the I/O space 827 * so we can read the chip ID register. 828 */ 829 rid = RL_RID; 830 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 831 RF_ACTIVE); 832 if (sc->rl_res == NULL) { 833 device_printf(dev, 834 "couldn't map ports/memory\n"); 835 return (ENXIO); 836 } 837 sc->rl_btag = rman_get_bustag(sc->rl_res); 838 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 839 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 840 bus_release_resource(dev, RL_RES, 841 RL_RID, sc->rl_res); 842 if (t->rl_basetype == hwrev) { 843 device_set_desc(dev, t->rl_name); 844 return (BUS_PROBE_DEFAULT); 845 } 846 } 847 t++; 848 } 849 850 return (ENXIO); 851} 852 853/* 854 * This routine takes the segment list provided as the result of 855 * a bus_dma_map_load() operation and assigns the addresses/lengths 856 * to RealTek DMA descriptors. This can be called either by the RX 857 * code or the TX code. In the RX case, we'll probably wind up mapping 858 * at most one segment. For the TX case, there could be any number of 859 * segments since TX packets may span multiple mbufs. In either case, 860 * if the number of segments is larger than the rl_maxsegs limit 861 * specified by the caller, we abort the mapping operation. Sadly, 862 * whoever designed the buffer mapping API did not provide a way to 863 * return an error from here, so we have to fake it a bit. 864 */ 865 866static void 867re_dma_map_desc(arg, segs, nseg, mapsize, error) 868 void *arg; 869 bus_dma_segment_t *segs; 870 int nseg; 871 bus_size_t mapsize; 872 int error; 873{ 874 struct rl_dmaload_arg *ctx; 875 struct rl_desc *d = NULL; 876 int i = 0, idx; 877 878 if (error) 879 return; 880 881 ctx = arg; 882 883 /* Signal error to caller if there's too many segments */ 884 if (nseg > ctx->rl_maxsegs) { 885 ctx->rl_maxsegs = 0; 886 return; 887 } 888 889 /* 890 * Map the segment array into descriptors. Note that we set the 891 * start-of-frame and end-of-frame markers for either TX or RX, but 892 * they really only have meaning in the TX case. (In the RX case, 893 * it's the chip that tells us where packets begin and end.) 894 * We also keep track of the end of the ring and set the 895 * end-of-ring bits as needed, and we set the ownership bits 896 * in all except the very first descriptor. (The caller will 897 * set this descriptor later when it start transmission or 898 * reception.) 899 */ 900 idx = ctx->rl_idx; 901 for (;;) { 902 u_int32_t cmdstat; 903 d = &ctx->rl_ring[idx]; 904 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 905 ctx->rl_maxsegs = 0; 906 return; 907 } 908 cmdstat = segs[i].ds_len; 909 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 910 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 911 if (i == 0) 912 cmdstat |= RL_TDESC_CMD_SOF; 913 else 914 cmdstat |= RL_TDESC_CMD_OWN; 915 if (idx == (RL_RX_DESC_CNT - 1)) 916 cmdstat |= RL_TDESC_CMD_EOR; 917 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 918 i++; 919 if (i == nseg) 920 break; 921 RL_DESC_INC(idx); 922 } 923 924 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 925 ctx->rl_maxsegs = nseg; 926 ctx->rl_idx = idx; 927} 928 929/* 930 * Map a single buffer address. 931 */ 932 933static void 934re_dma_map_addr(arg, segs, nseg, error) 935 void *arg; 936 bus_dma_segment_t *segs; 937 int nseg; 938 int error; 939{ 940 u_int32_t *addr; 941 942 if (error) 943 return; 944 945 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 946 addr = arg; 947 *addr = segs->ds_addr; 948} 949 950static int 951re_allocmem(dev, sc) 952 device_t dev; 953 struct rl_softc *sc; 954{ 955 int error; 956 int nseg; 957 int i; 958 959 /* 960 * Allocate map for RX mbufs. 961 */ 962 nseg = 32; 963 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 964 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 965 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 966 NULL, NULL, &sc->rl_ldata.rl_mtag); 967 if (error) { 968 device_printf(dev, "could not allocate dma tag\n"); 969 return (ENOMEM); 970 } 971 972 /* 973 * Allocate map for TX descriptor list. 974 */ 975 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 976 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 977 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 978 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 979 if (error) { 980 device_printf(dev, "could not allocate dma tag\n"); 981 return (ENOMEM); 982 } 983 984 /* Allocate DMA'able memory for the TX ring */ 985 986 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 987 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 988 &sc->rl_ldata.rl_tx_list_map); 989 if (error) 990 return (ENOMEM); 991 992 /* Load the map for the TX ring. */ 993 994 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 995 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 996 RL_TX_LIST_SZ, re_dma_map_addr, 997 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 998 999 /* Create DMA maps for TX buffers */ 1000 1001 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1002 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1003 &sc->rl_ldata.rl_tx_dmamap[i]); 1004 if (error) { 1005 device_printf(dev, "can't create DMA map for TX\n"); 1006 return (ENOMEM); 1007 } 1008 } 1009 1010 /* 1011 * Allocate map for RX descriptor list. 1012 */ 1013 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1014 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1015 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1016 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1017 if (error) { 1018 device_printf(dev, "could not allocate dma tag\n"); 1019 return (ENOMEM); 1020 } 1021 1022 /* Allocate DMA'able memory for the RX ring */ 1023 1024 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1025 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1026 &sc->rl_ldata.rl_rx_list_map); 1027 if (error) 1028 return (ENOMEM); 1029 1030 /* Load the map for the RX ring. */ 1031 1032 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1033 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1034 RL_RX_LIST_SZ, re_dma_map_addr, 1035 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1036 1037 /* Create DMA maps for RX buffers */ 1038 1039 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1040 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1041 &sc->rl_ldata.rl_rx_dmamap[i]); 1042 if (error) { 1043 device_printf(dev, "can't create DMA map for RX\n"); 1044 return (ENOMEM); 1045 } 1046 } 1047 1048 return (0); 1049} 1050 1051/* 1052 * Attach the interface. Allocate softc structures, do ifmedia 1053 * setup and ethernet/BPF attach. 1054 */ 1055static int 1056re_attach(dev) 1057 device_t dev; 1058{ 1059 u_char eaddr[ETHER_ADDR_LEN]; 1060 u_int16_t as[3]; 1061 struct rl_softc *sc; 1062 struct ifnet *ifp; 1063 struct rl_hwrev *hw_rev; 1064 int hwrev; 1065 u_int16_t re_did = 0; 1066 int unit, error = 0, rid, i; 1067 1068 sc = device_get_softc(dev); 1069 unit = device_get_unit(dev); 1070 1071 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1072 MTX_DEF); 1073 /* 1074 * Map control/status registers. 1075 */ 1076 pci_enable_busmaster(dev); 1077 1078 rid = RL_RID; 1079 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1080 RF_ACTIVE); 1081 1082 if (sc->rl_res == NULL) { 1083 printf ("re%d: couldn't map ports/memory\n", unit); 1084 error = ENXIO; 1085 goto fail; 1086 } 1087 1088 sc->rl_btag = rman_get_bustag(sc->rl_res); 1089 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1090 1091 /* Allocate interrupt */ 1092 rid = 0; 1093 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1094 RF_SHAREABLE | RF_ACTIVE); 1095 1096 if (sc->rl_irq == NULL) { 1097 printf("re%d: couldn't map interrupt\n", unit); 1098 error = ENXIO; 1099 goto fail; 1100 } 1101 1102 /* Reset the adapter. */ 1103 RL_LOCK(sc); 1104 re_reset(sc); 1105 RL_UNLOCK(sc); 1106 1107 hw_rev = re_hwrevs; 1108 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1109 while (hw_rev->rl_desc != NULL) { 1110 if (hw_rev->rl_rev == hwrev) { 1111 sc->rl_type = hw_rev->rl_type; 1112 break; 1113 } 1114 hw_rev++; 1115 } 1116 1117 if (sc->rl_type == RL_8169) { 1118 1119 /* Set RX length mask */ 1120 1121 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1122 1123 /* Force station address autoload from the EEPROM */ 1124 1125 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1126 for (i = 0; i < RL_TIMEOUT; i++) { 1127 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1128 break; 1129 DELAY(100); 1130 } 1131 if (i == RL_TIMEOUT) 1132 printf ("re%d: eeprom autoload timed out\n", unit); 1133 1134 for (i = 0; i < ETHER_ADDR_LEN; i++) 1135 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1136 } else { 1137 1138 /* Set RX length mask */ 1139 1140 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1141 1142 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1143 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1144 if (re_did != 0x8129) 1145 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1146 1147 /* 1148 * Get station address from the EEPROM. 1149 */ 1150 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1151 for (i = 0; i < 3; i++) { 1152 eaddr[(i * 2) + 0] = as[i] & 0xff; 1153 eaddr[(i * 2) + 1] = as[i] >> 8; 1154 } 1155 } 1156 1157 sc->rl_unit = unit; 1158 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1159 1160 /* 1161 * Allocate the parent bus DMA tag appropriate for PCI. 1162 */ 1163#define RL_NSEG_NEW 32 1164 error = bus_dma_tag_create(NULL, /* parent */ 1165 1, 0, /* alignment, boundary */ 1166 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1167 BUS_SPACE_MAXADDR, /* highaddr */ 1168 NULL, NULL, /* filter, filterarg */ 1169 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1170 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1171 BUS_DMA_ALLOCNOW, /* flags */ 1172 NULL, NULL, /* lockfunc, lockarg */ 1173 &sc->rl_parent_tag); 1174 if (error) 1175 goto fail; 1176 1177 error = re_allocmem(dev, sc); 1178 1179 if (error) 1180 goto fail; 1181 1182 /* Do MII setup */ 1183 if (mii_phy_probe(dev, &sc->rl_miibus, 1184 re_ifmedia_upd, re_ifmedia_sts)) { 1185 printf("re%d: MII without any phy!\n", sc->rl_unit); 1186 error = ENXIO; 1187 goto fail; 1188 } 1189 1190 ifp = &sc->arpcom.ac_if; 1191 ifp->if_softc = sc; 1192 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1193 ifp->if_mtu = ETHERMTU; 1194 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1195 ifp->if_ioctl = re_ioctl; 1196 ifp->if_capabilities = IFCAP_VLAN_MTU; 1197 ifp->if_start = re_start; 1198 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0; 1199 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1200#ifdef DEVICE_POLLING 1201 ifp->if_capabilities |= IFCAP_POLLING; 1202#endif 1203 ifp->if_watchdog = re_watchdog; 1204 ifp->if_init = re_init; 1205 if (sc->rl_type == RL_8169) 1206 ifp->if_baudrate = 1000000000; 1207 else 1208 ifp->if_baudrate = 100000000; 1209 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; 1210 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1211 1212 callout_handle_init(&sc->rl_stat_ch); 1213 1214 /* 1215 * Call MI attach routine. 1216 */ 1217 ether_ifattach(ifp, eaddr); 1218 1219 /* Perform hardware diagnostic. */ 1220 error = re_diag(sc); 1221 1222 if (error) { 1223 printf("re%d: attach aborted due to hardware diag failure\n", 1224 unit); 1225 ether_ifdetach(ifp); 1226 goto fail; 1227 } 1228 1229 /* Hook interrupt last to avoid having to lock softc */ 1230 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1231 re_intr, sc, &sc->rl_intrhand); 1232 if (error) { 1233 printf("re%d: couldn't set up irq\n", unit); 1234 ether_ifdetach(ifp); 1235 } 1236 1237fail: 1238 if (error) 1239 re_detach(dev); 1240 1241 return (error); 1242} 1243 1244/* 1245 * Shutdown hardware and free up resources. This can be called any 1246 * time after the mutex has been initialized. It is called in both 1247 * the error case in attach and the normal detach case so it needs 1248 * to be careful about only freeing resources that have actually been 1249 * allocated. 1250 */ 1251static int 1252re_detach(dev) 1253 device_t dev; 1254{ 1255 struct rl_softc *sc; 1256 struct ifnet *ifp; 1257 int i; 1258 int attached; 1259 1260 sc = device_get_softc(dev); 1261 ifp = &sc->arpcom.ac_if; 1262 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1263 1264 attached = device_is_attached(dev); 1265 /* These should only be active if attach succeeded */ 1266 if (attached) 1267 ether_ifdetach(ifp); 1268 1269 RL_LOCK(sc); 1270#if 0 1271 sc->suspended = 1; 1272#endif 1273 1274 /* These should only be active if attach succeeded */ 1275 if (attached) { 1276 re_stop(sc); 1277 /* 1278 * Force off the IFF_UP flag here, in case someone 1279 * still had a BPF descriptor attached to this 1280 * interface. If they do, ether_ifdetach() will cause 1281 * the BPF code to try and clear the promisc mode 1282 * flag, which will bubble down to re_ioctl(), 1283 * which will try to call re_init() again. This will 1284 * turn the NIC back on and restart the MII ticker, 1285 * which will panic the system when the kernel tries 1286 * to invoke the re_tick() function that isn't there 1287 * anymore. 1288 */ 1289 ifp->if_flags &= ~IFF_UP; 1290 } 1291 if (sc->rl_miibus) 1292 device_delete_child(dev, sc->rl_miibus); 1293 bus_generic_detach(dev); 1294 1295 /* 1296 * The rest is resource deallocation, so we should already be 1297 * stopped here. 1298 */ 1299 RL_UNLOCK(sc); 1300 1301 if (sc->rl_intrhand) 1302 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1303 if (sc->rl_irq) 1304 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1305 if (sc->rl_res) 1306 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1307 1308 1309 /* Unload and free the RX DMA ring memory and map */ 1310 1311 if (sc->rl_ldata.rl_rx_list_tag) { 1312 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1313 sc->rl_ldata.rl_rx_list_map); 1314 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1315 sc->rl_ldata.rl_rx_list, 1316 sc->rl_ldata.rl_rx_list_map); 1317 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1318 } 1319 1320 /* Unload and free the TX DMA ring memory and map */ 1321 1322 if (sc->rl_ldata.rl_tx_list_tag) { 1323 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1324 sc->rl_ldata.rl_tx_list_map); 1325 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1326 sc->rl_ldata.rl_tx_list, 1327 sc->rl_ldata.rl_tx_list_map); 1328 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1329 } 1330 1331 /* Destroy all the RX and TX buffer maps */ 1332 1333 if (sc->rl_ldata.rl_mtag) { 1334 for (i = 0; i < RL_TX_DESC_CNT; i++) 1335 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1336 sc->rl_ldata.rl_tx_dmamap[i]); 1337 for (i = 0; i < RL_RX_DESC_CNT; i++) 1338 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1339 sc->rl_ldata.rl_rx_dmamap[i]); 1340 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1341 } 1342 1343 /* Unload and free the stats buffer and map */ 1344 1345 if (sc->rl_ldata.rl_stag) { 1346 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1347 sc->rl_ldata.rl_rx_list_map); 1348 bus_dmamem_free(sc->rl_ldata.rl_stag, 1349 sc->rl_ldata.rl_stats, 1350 sc->rl_ldata.rl_smap); 1351 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1352 } 1353 1354 if (sc->rl_parent_tag) 1355 bus_dma_tag_destroy(sc->rl_parent_tag); 1356 1357 mtx_destroy(&sc->rl_mtx); 1358 1359 return (0); 1360} 1361 1362static int 1363re_newbuf(sc, idx, m) 1364 struct rl_softc *sc; 1365 int idx; 1366 struct mbuf *m; 1367{ 1368 struct rl_dmaload_arg arg; 1369 struct mbuf *n = NULL; 1370 int error; 1371 1372 if (m == NULL) { 1373 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1374 if (n == NULL) 1375 return (ENOBUFS); 1376 m = n; 1377 } else 1378 m->m_data = m->m_ext.ext_buf; 1379 1380 m->m_len = m->m_pkthdr.len = MCLBYTES; 1381#ifdef RE_FIXUP_RX 1382 /* 1383 * This is part of an evil trick to deal with non-x86 platforms. 1384 * The RealTek chip requires RX buffers to be aligned on 64-bit 1385 * boundaries, but that will hose non-x86 machines. To get around 1386 * this, we leave some empty space at the start of each buffer 1387 * and for non-x86 hosts, we copy the buffer back six bytes 1388 * to achieve word alignment. This is slightly more efficient 1389 * than allocating a new buffer, copying the contents, and 1390 * discarding the old buffer. 1391 */ 1392 m_adj(m, RE_ETHER_ALIGN); 1393#endif 1394 arg.sc = sc; 1395 arg.rl_idx = idx; 1396 arg.rl_maxsegs = 1; 1397 arg.rl_flags = 0; 1398 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1399 1400 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1401 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1402 &arg, BUS_DMA_NOWAIT); 1403 if (error || arg.rl_maxsegs != 1) { 1404 if (n != NULL) 1405 m_freem(n); 1406 return (ENOMEM); 1407 } 1408 1409 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1410 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1411 1412 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1413 sc->rl_ldata.rl_rx_dmamap[idx], 1414 BUS_DMASYNC_PREREAD); 1415 1416 return (0); 1417} 1418 1419#ifdef RE_FIXUP_RX 1420static __inline void 1421re_fixup_rx(m) 1422 struct mbuf *m; 1423{ 1424 int i; 1425 uint16_t *src, *dst; 1426 1427 src = mtod(m, uint16_t *); 1428 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1429 1430 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1431 *dst++ = *src++; 1432 1433 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1434 1435 return; 1436} 1437#endif 1438 1439static int 1440re_tx_list_init(sc) 1441 struct rl_softc *sc; 1442{ 1443 1444 RL_LOCK_ASSERT(sc); 1445 1446 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1447 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1448 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1449 1450 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1451 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1452 sc->rl_ldata.rl_tx_prodidx = 0; 1453 sc->rl_ldata.rl_tx_considx = 0; 1454 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1455 1456 return (0); 1457} 1458 1459static int 1460re_rx_list_init(sc) 1461 struct rl_softc *sc; 1462{ 1463 int i; 1464 1465 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1466 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1467 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1468 1469 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1470 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1471 return (ENOBUFS); 1472 } 1473 1474 /* Flush the RX descriptors */ 1475 1476 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1477 sc->rl_ldata.rl_rx_list_map, 1478 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1479 1480 sc->rl_ldata.rl_rx_prodidx = 0; 1481 sc->rl_head = sc->rl_tail = NULL; 1482 1483 return (0); 1484} 1485 1486/* 1487 * RX handler for C+ and 8169. For the gigE chips, we support 1488 * the reception of jumbo frames that have been fragmented 1489 * across multiple 2K mbuf cluster buffers. 1490 */ 1491static void 1492re_rxeof(sc) 1493 struct rl_softc *sc; 1494{ 1495 struct mbuf *m; 1496 struct ifnet *ifp; 1497 int i, total_len; 1498 struct rl_desc *cur_rx; 1499 u_int32_t rxstat, rxvlan; 1500 1501 RL_LOCK_ASSERT(sc); 1502 1503 ifp = &sc->arpcom.ac_if; 1504 i = sc->rl_ldata.rl_rx_prodidx; 1505 1506 /* Invalidate the descriptor memory */ 1507 1508 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1509 sc->rl_ldata.rl_rx_list_map, 1510 BUS_DMASYNC_POSTREAD); 1511 1512 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1513 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1514 m = sc->rl_ldata.rl_rx_mbuf[i]; 1515 total_len = RL_RXBYTES(cur_rx); 1516 rxstat = le32toh(cur_rx->rl_cmdstat); 1517 rxvlan = le32toh(cur_rx->rl_vlanctl); 1518 1519 /* Invalidate the RX mbuf and unload its map */ 1520 1521 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1522 sc->rl_ldata.rl_rx_dmamap[i], 1523 BUS_DMASYNC_POSTWRITE); 1524 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1525 sc->rl_ldata.rl_rx_dmamap[i]); 1526 1527 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1528 m->m_len = RE_RX_DESC_BUFLEN; 1529 if (sc->rl_head == NULL) 1530 sc->rl_head = sc->rl_tail = m; 1531 else { 1532 m->m_flags &= ~M_PKTHDR; 1533 sc->rl_tail->m_next = m; 1534 sc->rl_tail = m; 1535 } 1536 re_newbuf(sc, i, NULL); 1537 RL_DESC_INC(i); 1538 continue; 1539 } 1540 1541 /* 1542 * NOTE: for the 8139C+, the frame length field 1543 * is always 12 bits in size, but for the gigE chips, 1544 * it is 13 bits (since the max RX frame length is 16K). 1545 * Unfortunately, all 32 bits in the status word 1546 * were already used, so to make room for the extra 1547 * length bit, RealTek took out the 'frame alignment 1548 * error' bit and shifted the other status bits 1549 * over one slot. The OWN, EOR, FS and LS bits are 1550 * still in the same places. We have already extracted 1551 * the frame length and checked the OWN bit, so rather 1552 * than using an alternate bit mapping, we shift the 1553 * status bits one space to the right so we can evaluate 1554 * them using the 8169 status as though it was in the 1555 * same format as that of the 8139C+. 1556 */ 1557 if (sc->rl_type == RL_8169) 1558 rxstat >>= 1; 1559 1560 /* 1561 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1562 * set, but if CRC is clear, it will still be a valid frame. 1563 */ 1564 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1565 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1566 ifp->if_ierrors++; 1567 /* 1568 * If this is part of a multi-fragment packet, 1569 * discard all the pieces. 1570 */ 1571 if (sc->rl_head != NULL) { 1572 m_freem(sc->rl_head); 1573 sc->rl_head = sc->rl_tail = NULL; 1574 } 1575 re_newbuf(sc, i, m); 1576 RL_DESC_INC(i); 1577 continue; 1578 } 1579 1580 /* 1581 * If allocating a replacement mbuf fails, 1582 * reload the current one. 1583 */ 1584 1585 if (re_newbuf(sc, i, NULL)) { 1586 ifp->if_ierrors++; 1587 if (sc->rl_head != NULL) { 1588 m_freem(sc->rl_head); 1589 sc->rl_head = sc->rl_tail = NULL; 1590 } 1591 re_newbuf(sc, i, m); 1592 RL_DESC_INC(i); 1593 continue; 1594 } 1595 1596 RL_DESC_INC(i); 1597 1598 if (sc->rl_head != NULL) { 1599 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1600 if (m->m_len == 0) 1601 m->m_len = RE_RX_DESC_BUFLEN; 1602 /* 1603 * Special case: if there's 4 bytes or less 1604 * in this buffer, the mbuf can be discarded: 1605 * the last 4 bytes is the CRC, which we don't 1606 * care about anyway. 1607 */ 1608 if (m->m_len <= ETHER_CRC_LEN) { 1609 sc->rl_tail->m_len -= 1610 (ETHER_CRC_LEN - m->m_len); 1611 m_freem(m); 1612 } else { 1613 m->m_len -= ETHER_CRC_LEN; 1614 m->m_flags &= ~M_PKTHDR; 1615 sc->rl_tail->m_next = m; 1616 } 1617 m = sc->rl_head; 1618 sc->rl_head = sc->rl_tail = NULL; 1619 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1620 } else 1621 m->m_pkthdr.len = m->m_len = 1622 (total_len - ETHER_CRC_LEN); 1623 1624#ifdef RE_FIXUP_RX 1625 re_fixup_rx(m); 1626#endif 1627 ifp->if_ipackets++; 1628 m->m_pkthdr.rcvif = ifp; 1629 1630 /* Do RX checksumming if enabled */ 1631 1632 if (ifp->if_capenable & IFCAP_RXCSUM) { 1633 1634 /* Check IP header checksum */ 1635 if (rxstat & RL_RDESC_STAT_PROTOID) 1636 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1637 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1638 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1639 1640 /* Check TCP/UDP checksum */ 1641 if ((RL_TCPPKT(rxstat) && 1642 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1643 (RL_UDPPKT(rxstat) && 1644 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1645 m->m_pkthdr.csum_flags |= 1646 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1647 m->m_pkthdr.csum_data = 0xffff; 1648 } 1649 } 1650 1651 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1652 VLAN_INPUT_TAG(ifp, m, 1653 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1654 RL_UNLOCK(sc); 1655 (*ifp->if_input)(ifp, m); 1656 RL_LOCK(sc); 1657 } 1658 1659 /* Flush the RX DMA ring */ 1660 1661 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1662 sc->rl_ldata.rl_rx_list_map, 1663 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1664 1665 sc->rl_ldata.rl_rx_prodidx = i; 1666} 1667 1668static void 1669re_txeof(sc) 1670 struct rl_softc *sc; 1671{ 1672 struct ifnet *ifp; 1673 u_int32_t txstat; 1674 int idx; 1675 1676 ifp = &sc->arpcom.ac_if; 1677 idx = sc->rl_ldata.rl_tx_considx; 1678 1679 /* Invalidate the TX descriptor list */ 1680 1681 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1682 sc->rl_ldata.rl_tx_list_map, 1683 BUS_DMASYNC_POSTREAD); 1684 1685 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1686 1687 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1688 if (txstat & RL_TDESC_CMD_OWN) 1689 break; 1690 1691 /* 1692 * We only stash mbufs in the last descriptor 1693 * in a fragment chain, which also happens to 1694 * be the only place where the TX status bits 1695 * are valid. 1696 */ 1697 1698 if (txstat & RL_TDESC_CMD_EOF) { 1699 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1700 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1701 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1702 sc->rl_ldata.rl_tx_dmamap[idx]); 1703 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1704 RL_TDESC_STAT_COLCNT)) 1705 ifp->if_collisions++; 1706 if (txstat & RL_TDESC_STAT_TXERRSUM) 1707 ifp->if_oerrors++; 1708 else 1709 ifp->if_opackets++; 1710 } 1711 sc->rl_ldata.rl_tx_free++; 1712 RL_DESC_INC(idx); 1713 } 1714 1715 /* No changes made to the TX ring, so no flush needed */ 1716 1717 if (idx != sc->rl_ldata.rl_tx_considx) { 1718 sc->rl_ldata.rl_tx_considx = idx; 1719 ifp->if_flags &= ~IFF_OACTIVE; 1720 ifp->if_timer = 0; 1721 } 1722 1723 /* 1724 * If not all descriptors have been released reaped yet, 1725 * reload the timer so that we will eventually get another 1726 * interrupt that will cause us to re-enter this routine. 1727 * This is done in case the transmitter has gone idle. 1728 */ 1729 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1730 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1731} 1732 1733static void 1734re_tick(xsc) 1735 void *xsc; 1736{ 1737 struct rl_softc *sc; 1738 1739 sc = xsc; 1740 RL_LOCK(sc); 1741 re_tick_locked(sc); 1742 RL_UNLOCK(sc); 1743} 1744 1745static void 1746re_tick_locked(sc) 1747 struct rl_softc *sc; 1748{ 1749 struct mii_data *mii; 1750 1751 RL_LOCK_ASSERT(sc); 1752 1753 mii = device_get_softc(sc->rl_miibus); 1754 1755 mii_tick(mii); 1756 1757 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1758} 1759 1760#ifdef DEVICE_POLLING 1761static void 1762re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1763{ 1764 struct rl_softc *sc = ifp->if_softc; 1765 1766 RL_LOCK(sc); 1767 re_poll_locked(ifp, cmd, count); 1768 RL_UNLOCK(sc); 1769} 1770 1771static void 1772re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1773{ 1774 struct rl_softc *sc = ifp->if_softc; 1775 1776 RL_LOCK_ASSERT(sc); 1777 1778 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1779 ether_poll_deregister(ifp); 1780 cmd = POLL_DEREGISTER; 1781 } 1782 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1783 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1784 return; 1785 } 1786 1787 sc->rxcycles = count; 1788 re_rxeof(sc); 1789 re_txeof(sc); 1790 1791 if (ifp->if_snd.ifq_head != NULL) 1792 re_start_locked(ifp); 1793 1794 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1795 u_int16_t status; 1796 1797 status = CSR_READ_2(sc, RL_ISR); 1798 if (status == 0xffff) 1799 return; 1800 if (status) 1801 CSR_WRITE_2(sc, RL_ISR, status); 1802 1803 /* 1804 * XXX check behaviour on receiver stalls. 1805 */ 1806 1807 if (status & RL_ISR_SYSTEM_ERR) { 1808 re_reset(sc); 1809 re_init_locked(sc); 1810 } 1811 } 1812} 1813#endif /* DEVICE_POLLING */ 1814 1815static void 1816re_intr(arg) 1817 void *arg; 1818{ 1819 struct rl_softc *sc; 1820 struct ifnet *ifp; 1821 u_int16_t status; 1822 1823 sc = arg; 1824 1825 RL_LOCK(sc); 1826 1827 ifp = &sc->arpcom.ac_if; 1828 1829 if (sc->suspended || !(ifp->if_flags & IFF_UP)) 1830 goto done_locked; 1831 1832#ifdef DEVICE_POLLING 1833 if (ifp->if_flags & IFF_POLLING) 1834 goto done_locked; 1835 if ((ifp->if_capenable & IFCAP_POLLING) && 1836 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1837 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1838 re_poll_locked(ifp, 0, 1); 1839 goto done_locked; 1840 } 1841#endif /* DEVICE_POLLING */ 1842 1843 for (;;) { 1844 1845 status = CSR_READ_2(sc, RL_ISR); 1846 /* If the card has gone away the read returns 0xffff. */ 1847 if (status == 0xffff) 1848 break; 1849 if (status) 1850 CSR_WRITE_2(sc, RL_ISR, status); 1851 1852 if ((status & RL_INTRS_CPLUS) == 0) 1853 break; 1854 1855 if ((status & RL_ISR_RX_OK) || 1856 (status & RL_ISR_RX_ERR)) 1857 re_rxeof(sc); 1858 1859 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1860 (status & RL_ISR_TX_ERR) || 1861 (status & RL_ISR_TX_DESC_UNAVAIL)) 1862 re_txeof(sc); 1863 1864 if (status & RL_ISR_SYSTEM_ERR) { 1865 re_reset(sc); 1866 re_init_locked(sc); 1867 } 1868 1869 if (status & RL_ISR_LINKCHG) { 1870 untimeout(re_tick, sc, sc->rl_stat_ch); 1871 re_tick_locked(sc); 1872 } 1873 } 1874 1875 if (ifp->if_snd.ifq_head != NULL) 1876 re_start_locked(ifp); 1877 1878done_locked: 1879 RL_UNLOCK(sc); 1880} 1881 1882static int 1883re_encap(sc, m_head, idx) 1884 struct rl_softc *sc; 1885 struct mbuf **m_head; 1886 int *idx; 1887{ 1888 struct mbuf *m_new = NULL; 1889 struct rl_dmaload_arg arg; 1890 bus_dmamap_t map; 1891 int error; 1892 struct m_tag *mtag; 1893 1894 RL_LOCK_ASSERT(sc); 1895 1896 if (sc->rl_ldata.rl_tx_free <= 4) 1897 return (EFBIG); 1898 1899 /* 1900 * Set up checksum offload. Note: checksum offload bits must 1901 * appear in all descriptors of a multi-descriptor transmit 1902 * attempt. This is according to testing done with an 8169 1903 * chip. This is a requirement. 1904 */ 1905 1906 arg.rl_flags = 0; 1907 1908 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1909 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1910 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1911 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1912 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1913 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1914 1915 arg.sc = sc; 1916 arg.rl_idx = *idx; 1917 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1918 if (arg.rl_maxsegs > 4) 1919 arg.rl_maxsegs -= 4; 1920 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1921 1922 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1923 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1924 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1925 1926 if (error && error != EFBIG) { 1927 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1928 return (ENOBUFS); 1929 } 1930 1931 /* Too many segments to map, coalesce into a single mbuf */ 1932 1933 if (error || arg.rl_maxsegs == 0) { 1934 m_new = m_defrag(*m_head, M_DONTWAIT); 1935 if (m_new == NULL) 1936 return (ENOBUFS); 1937 else 1938 *m_head = m_new; 1939 1940 arg.sc = sc; 1941 arg.rl_idx = *idx; 1942 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1943 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1944 1945 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1946 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1947 if (error) { 1948 printf("re%d: can't map mbuf (error %d)\n", 1949 sc->rl_unit, error); 1950 return (EFBIG); 1951 } 1952 } 1953 1954 /* 1955 * Insure that the map for this transmission 1956 * is placed at the array index of the last descriptor 1957 * in this chain. (Swap last and first dmamaps.) 1958 */ 1959 sc->rl_ldata.rl_tx_dmamap[*idx] = 1960 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1961 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1962 1963 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 1964 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1965 1966 /* 1967 * Set up hardware VLAN tagging. Note: vlan tag info must 1968 * appear in the first descriptor of a multi-descriptor 1969 * transmission attempt. 1970 */ 1971 1972 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, *m_head); 1973 if (mtag != NULL) 1974 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1975 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1976 1977 /* Transfer ownership of packet to the chip. */ 1978 1979 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1980 htole32(RL_TDESC_CMD_OWN); 1981 if (*idx != arg.rl_idx) 1982 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1983 htole32(RL_TDESC_CMD_OWN); 1984 1985 RL_DESC_INC(arg.rl_idx); 1986 *idx = arg.rl_idx; 1987 1988 return (0); 1989} 1990 1991static void 1992re_start(ifp) 1993 struct ifnet *ifp; 1994{ 1995 struct rl_softc *sc; 1996 1997 sc = ifp->if_softc; 1998 RL_LOCK(sc); 1999 re_start_locked(ifp); 2000 RL_UNLOCK(sc); 2001} 2002 2003/* 2004 * Main transmit routine for C+ and gigE NICs. 2005 */ 2006static void 2007re_start_locked(ifp) 2008 struct ifnet *ifp; 2009{ 2010 struct rl_softc *sc; 2011 struct mbuf *m_head = NULL; 2012 int idx; 2013 2014 sc = ifp->if_softc; 2015 2016 RL_LOCK_ASSERT(sc); 2017 2018 idx = sc->rl_ldata.rl_tx_prodidx; 2019 2020 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2021 IF_DEQUEUE(&ifp->if_snd, m_head); 2022 if (m_head == NULL) 2023 break; 2024 2025 if (re_encap(sc, &m_head, &idx)) { 2026 IF_PREPEND(&ifp->if_snd, m_head); 2027 ifp->if_flags |= IFF_OACTIVE; 2028 break; 2029 } 2030 2031 /* 2032 * If there's a BPF listener, bounce a copy of this frame 2033 * to him. 2034 */ 2035 BPF_MTAP(ifp, m_head); 2036 } 2037 2038 /* Flush the TX descriptors */ 2039 2040 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2041 sc->rl_ldata.rl_tx_list_map, 2042 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2043 2044 sc->rl_ldata.rl_tx_prodidx = idx; 2045 2046 /* 2047 * RealTek put the TX poll request register in a different 2048 * location on the 8169 gigE chip. I don't know why. 2049 */ 2050 2051 if (sc->rl_type == RL_8169) 2052 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2053 else 2054 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2055 2056 /* 2057 * Use the countdown timer for interrupt moderation. 2058 * 'TX done' interrupts are disabled. Instead, we reset the 2059 * countdown timer, which will begin counting until it hits 2060 * the value in the TIMERINT register, and then trigger an 2061 * interrupt. Each time we write to the TIMERCNT register, 2062 * the timer count is reset to 0. 2063 */ 2064 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2065 2066 /* 2067 * Set a timeout in case the chip goes out to lunch. 2068 */ 2069 ifp->if_timer = 5; 2070} 2071 2072static void 2073re_init(xsc) 2074 void *xsc; 2075{ 2076 struct rl_softc *sc = xsc; 2077 2078 RL_LOCK(sc); 2079 re_init_locked(sc); 2080 RL_UNLOCK(sc); 2081} 2082 2083static void 2084re_init_locked(sc) 2085 struct rl_softc *sc; 2086{ 2087 struct ifnet *ifp = &sc->arpcom.ac_if; 2088 struct mii_data *mii; 2089 u_int32_t rxcfg = 0; 2090 2091 RL_LOCK_ASSERT(sc); 2092 2093 mii = device_get_softc(sc->rl_miibus); 2094 2095 /* 2096 * Cancel pending I/O and free all RX/TX buffers. 2097 */ 2098 re_stop(sc); 2099 2100 /* 2101 * Enable C+ RX and TX mode, as well as VLAN stripping and 2102 * RX checksum offload. We must configure the C+ register 2103 * before all others. 2104 */ 2105 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2106 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2107 RL_CPLUSCMD_VLANSTRIP| 2108 (ifp->if_capenable & IFCAP_RXCSUM ? 2109 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2110 2111 /* 2112 * Init our MAC address. Even though the chipset 2113 * documentation doesn't mention it, we need to enter "Config 2114 * register write enable" mode to modify the ID registers. 2115 */ 2116 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2117 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2118 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2119 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2120 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2121 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2122 2123 /* 2124 * For C+ mode, initialize the RX descriptors and mbufs. 2125 */ 2126 re_rx_list_init(sc); 2127 re_tx_list_init(sc); 2128 2129 /* 2130 * Enable transmit and receive. 2131 */ 2132 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2133 2134 /* 2135 * Set the initial TX and RX configuration. 2136 */ 2137 if (sc->rl_testmode) { 2138 if (sc->rl_type == RL_8169) 2139 CSR_WRITE_4(sc, RL_TXCFG, 2140 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2141 else 2142 CSR_WRITE_4(sc, RL_TXCFG, 2143 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2144 } else 2145 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2146 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2147 2148 /* Set the individual bit to receive frames for this host only. */ 2149 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2150 rxcfg |= RL_RXCFG_RX_INDIV; 2151 2152 /* If we want promiscuous mode, set the allframes bit. */ 2153 if (ifp->if_flags & IFF_PROMISC) 2154 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2155 else 2156 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2157 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2158 2159 /* 2160 * Set capture broadcast bit to capture broadcast frames. 2161 */ 2162 if (ifp->if_flags & IFF_BROADCAST) 2163 rxcfg |= RL_RXCFG_RX_BROAD; 2164 else 2165 rxcfg &= ~RL_RXCFG_RX_BROAD; 2166 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2167 2168 /* 2169 * Program the multicast filter, if necessary. 2170 */ 2171 re_setmulti(sc); 2172 2173#ifdef DEVICE_POLLING 2174 /* 2175 * Disable interrupts if we are polling. 2176 */ 2177 if (ifp->if_flags & IFF_POLLING) 2178 CSR_WRITE_2(sc, RL_IMR, 0); 2179 else /* otherwise ... */ 2180#endif /* DEVICE_POLLING */ 2181 /* 2182 * Enable interrupts. 2183 */ 2184 if (sc->rl_testmode) 2185 CSR_WRITE_2(sc, RL_IMR, 0); 2186 else 2187 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2188 2189 /* Set initial TX threshold */ 2190 sc->rl_txthresh = RL_TX_THRESH_INIT; 2191 2192 /* Start RX/TX process. */ 2193 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2194#ifdef notdef 2195 /* Enable receiver and transmitter. */ 2196 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2197#endif 2198 /* 2199 * Load the addresses of the RX and TX lists into the chip. 2200 */ 2201 2202 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2203 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2204 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2205 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2206 2207 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2208 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2209 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2210 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2211 2212 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2213 2214 /* 2215 * Initialize the timer interrupt register so that 2216 * a timer interrupt will be generated once the timer 2217 * reaches a certain number of ticks. The timer is 2218 * reloaded on each transmit. This gives us TX interrupt 2219 * moderation, which dramatically improves TX frame rate. 2220 */ 2221 if (sc->rl_type == RL_8169) 2222 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2223 else 2224 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2225 2226 /* 2227 * For 8169 gigE NICs, set the max allowed RX packet 2228 * size so we can receive jumbo frames. 2229 */ 2230 if (sc->rl_type == RL_8169) 2231 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2232 2233 if (sc->rl_testmode) 2234 return; 2235 2236 mii_mediachg(mii); 2237 2238 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2239 2240 ifp->if_flags |= IFF_RUNNING; 2241 ifp->if_flags &= ~IFF_OACTIVE; 2242 2243 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2244} 2245 2246/* 2247 * Set media options. 2248 */ 2249static int 2250re_ifmedia_upd(ifp) 2251 struct ifnet *ifp; 2252{ 2253 struct rl_softc *sc; 2254 struct mii_data *mii; 2255 2256 sc = ifp->if_softc; 2257 mii = device_get_softc(sc->rl_miibus); 2258 mii_mediachg(mii); 2259 2260 return (0); 2261} 2262 2263/* 2264 * Report current media status. 2265 */ 2266static void 2267re_ifmedia_sts(ifp, ifmr) 2268 struct ifnet *ifp; 2269 struct ifmediareq *ifmr; 2270{ 2271 struct rl_softc *sc; 2272 struct mii_data *mii; 2273 2274 sc = ifp->if_softc; 2275 mii = device_get_softc(sc->rl_miibus); 2276 2277 mii_pollstat(mii); 2278 ifmr->ifm_active = mii->mii_media_active; 2279 ifmr->ifm_status = mii->mii_media_status; 2280} 2281 2282static int 2283re_ioctl(ifp, command, data) 2284 struct ifnet *ifp; 2285 u_long command; 2286 caddr_t data; 2287{ 2288 struct rl_softc *sc = ifp->if_softc; 2289 struct ifreq *ifr = (struct ifreq *) data; 2290 struct mii_data *mii; 2291 int error = 0; 2292 2293 switch (command) { 2294 case SIOCSIFMTU: 2295 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2296 error = EINVAL; 2297 ifp->if_mtu = ifr->ifr_mtu; 2298 break; 2299 case SIOCSIFFLAGS: 2300 RL_LOCK(sc); 2301 if (ifp->if_flags & IFF_UP) 2302 re_init_locked(sc); 2303 else if (ifp->if_flags & IFF_RUNNING) 2304 re_stop(sc); 2305 RL_UNLOCK(sc); 2306 error = 0; 2307 break; 2308 case SIOCADDMULTI: 2309 case SIOCDELMULTI: 2310 RL_LOCK(sc); 2311 re_setmulti(sc); 2312 RL_UNLOCK(sc); 2313 error = 0; 2314 break; 2315 case SIOCGIFMEDIA: 2316 case SIOCSIFMEDIA: 2317 mii = device_get_softc(sc->rl_miibus); 2318 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2319 break; 2320 case SIOCSIFCAP: 2321 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2322 ifp->if_capenable |= 2323 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2324 if (ifp->if_capenable & IFCAP_TXCSUM) 2325 ifp->if_hwassist = RE_CSUM_FEATURES; 2326 else 2327 ifp->if_hwassist = 0; 2328 if (ifp->if_flags & IFF_RUNNING) 2329 re_init(sc); 2330 break; 2331 default: 2332 error = ether_ioctl(ifp, command, data); 2333 break; 2334 } 2335 2336 return (error); 2337} 2338 2339static void 2340re_watchdog(ifp) 2341 struct ifnet *ifp; 2342{ 2343 struct rl_softc *sc; 2344 2345 sc = ifp->if_softc; 2346 RL_LOCK(sc); 2347 printf("re%d: watchdog timeout\n", sc->rl_unit); 2348 ifp->if_oerrors++; 2349 2350 re_txeof(sc); 2351 re_rxeof(sc); 2352 re_init_locked(sc); 2353 2354 RL_UNLOCK(sc); 2355} 2356 2357/* 2358 * Stop the adapter and free any mbufs allocated to the 2359 * RX and TX lists. 2360 */ 2361static void 2362re_stop(sc) 2363 struct rl_softc *sc; 2364{ 2365 register int i; 2366 struct ifnet *ifp; 2367 2368 RL_LOCK_ASSERT(sc); 2369 2370 ifp = &sc->arpcom.ac_if; 2371 ifp->if_timer = 0; 2372 2373 untimeout(re_tick, sc, sc->rl_stat_ch); 2374 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2375#ifdef DEVICE_POLLING 2376 ether_poll_deregister(ifp); 2377#endif /* DEVICE_POLLING */ 2378 2379 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2380 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2381 2382 if (sc->rl_head != NULL) { 2383 m_freem(sc->rl_head); 2384 sc->rl_head = sc->rl_tail = NULL; 2385 } 2386 2387 /* Free the TX list buffers. */ 2388 2389 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2390 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2391 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2392 sc->rl_ldata.rl_tx_dmamap[i]); 2393 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2394 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2395 } 2396 } 2397 2398 /* Free the RX list buffers. */ 2399 2400 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2401 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2402 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2403 sc->rl_ldata.rl_rx_dmamap[i]); 2404 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2405 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2406 } 2407 } 2408} 2409 2410/* 2411 * Device suspend routine. Stop the interface and save some PCI 2412 * settings in case the BIOS doesn't restore them properly on 2413 * resume. 2414 */ 2415static int 2416re_suspend(dev) 2417 device_t dev; 2418{ 2419 struct rl_softc *sc; 2420 2421 sc = device_get_softc(dev); 2422 2423 RL_LOCK(sc); 2424 re_stop(sc); 2425 sc->suspended = 1; 2426 RL_UNLOCK(sc); 2427 2428 return (0); 2429} 2430 2431/* 2432 * Device resume routine. Restore some PCI settings in case the BIOS 2433 * doesn't, re-enable busmastering, and restart the interface if 2434 * appropriate. 2435 */ 2436static int 2437re_resume(dev) 2438 device_t dev; 2439{ 2440 struct rl_softc *sc; 2441 struct ifnet *ifp; 2442 2443 sc = device_get_softc(dev); 2444 2445 RL_LOCK(sc); 2446 2447 ifp = &sc->arpcom.ac_if; 2448 2449 /* reinitialize interface if necessary */ 2450 if (ifp->if_flags & IFF_UP) 2451 re_init_locked(sc); 2452 2453 sc->suspended = 0; 2454 RL_UNLOCK(sc); 2455 2456 return (0); 2457} 2458 2459/* 2460 * Stop all chip I/O so that the kernel's probe routines don't 2461 * get confused by errant DMAs when rebooting. 2462 */ 2463static void 2464re_shutdown(dev) 2465 device_t dev; 2466{ 2467 struct rl_softc *sc; 2468 2469 sc = device_get_softc(dev); 2470 2471 RL_LOCK(sc); 2472 re_stop(sc); 2473 RL_UNLOCK(sc); 2474} 2475