if_re.c revision 131668
1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 131668 2004-07-06 02:48:29Z bms $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7.5K, so the max MTU possible with this 108 * driver is 7500 bytes. 109 */ 110 111#include <sys/param.h> 112#include <sys/endian.h> 113#include <sys/systm.h> 114#include <sys/sockio.h> 115#include <sys/mbuf.h> 116#include <sys/malloc.h> 117#include <sys/module.h> 118#include <sys/kernel.h> 119#include <sys/socket.h> 120 121#include <net/if.h> 122#include <net/if_arp.h> 123#include <net/ethernet.h> 124#include <net/if_dl.h> 125#include <net/if_media.h> 126#include <net/if_vlan_var.h> 127 128#include <net/bpf.h> 129 130#include <machine/bus_pio.h> 131#include <machine/bus_memio.h> 132#include <machine/bus.h> 133#include <machine/resource.h> 134#include <sys/bus.h> 135#include <sys/rman.h> 136 137#include <dev/mii/mii.h> 138#include <dev/mii/miivar.h> 139 140#include <dev/pci/pcireg.h> 141#include <dev/pci/pcivar.h> 142 143MODULE_DEPEND(re, pci, 1, 1, 1); 144MODULE_DEPEND(re, ether, 1, 1, 1); 145MODULE_DEPEND(re, miibus, 1, 1, 1); 146 147/* "controller miibus0" required. See GENERIC if you get errors here. */ 148#include "miibus_if.h" 149 150/* 151 * Default to using PIO access for this driver. 152 */ 153#define RE_USEIOSPACE 154 155#include <pci/if_rlreg.h> 156 157#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 159/* 160 * Various supported device vendors/types and their names. 161 */ 162static struct rl_type re_devs[] = { 163 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 164 "RealTek 8139C+ 10/100BaseTX" }, 165 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 166 "RealTek 8169 Gigabit Ethernet" }, 167 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 168 "RealTek 8169S Single-chip Gigabit Ethernet" }, 169 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 170 "RealTek 8110S Single-chip Gigabit Ethernet" }, 171 { 0, 0, 0, NULL } 172}; 173 174static struct rl_hwrev re_hwrevs[] = { 175 { RL_HWREV_8139, RL_8139, "" }, 176 { RL_HWREV_8139A, RL_8139, "A" }, 177 { RL_HWREV_8139AG, RL_8139, "A-G" }, 178 { RL_HWREV_8139B, RL_8139, "B" }, 179 { RL_HWREV_8130, RL_8139, "8130" }, 180 { RL_HWREV_8139C, RL_8139, "C" }, 181 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 182 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 183 { RL_HWREV_8169, RL_8169, "8169"}, 184 { RL_HWREV_8169S, RL_8169, "8169S"}, 185 { RL_HWREV_8110S, RL_8169, "8110S"}, 186 { RL_HWREV_8100, RL_8139, "8100"}, 187 { RL_HWREV_8101, RL_8139, "8101"}, 188 { 0, 0, NULL } 189}; 190 191static int re_probe (device_t); 192static int re_attach (device_t); 193static int re_detach (device_t); 194 195static int re_encap (struct rl_softc *, struct mbuf *, int *); 196 197static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 198static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 199 bus_size_t, int); 200static int re_allocmem (device_t, struct rl_softc *); 201static int re_newbuf (struct rl_softc *, int, struct mbuf *); 202static int re_rx_list_init (struct rl_softc *); 203static int re_tx_list_init (struct rl_softc *); 204static void re_rxeof (struct rl_softc *); 205static void re_txeof (struct rl_softc *); 206static void re_intr (void *); 207static void re_tick (void *); 208static void re_start (struct ifnet *); 209static int re_ioctl (struct ifnet *, u_long, caddr_t); 210static void re_init (void *); 211static void re_stop (struct rl_softc *); 212static void re_watchdog (struct ifnet *); 213static int re_suspend (device_t); 214static int re_resume (device_t); 215static void re_shutdown (device_t); 216static int re_ifmedia_upd (struct ifnet *); 217static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 218 219static void re_eeprom_putbyte (struct rl_softc *, int); 220static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 221static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 222static int re_gmii_readreg (device_t, int, int); 223static int re_gmii_writereg (device_t, int, int, int); 224 225static int re_miibus_readreg (device_t, int, int); 226static int re_miibus_writereg (device_t, int, int, int); 227static void re_miibus_statchg (device_t); 228 229static void re_setmulti (struct rl_softc *); 230static void re_reset (struct rl_softc *); 231 232static int re_diag (struct rl_softc *); 233 234#ifdef RE_USEIOSPACE 235#define RL_RES SYS_RES_IOPORT 236#define RL_RID RL_PCI_LOIO 237#else 238#define RL_RES SYS_RES_MEMORY 239#define RL_RID RL_PCI_LOMEM 240#endif 241 242static device_method_t re_methods[] = { 243 /* Device interface */ 244 DEVMETHOD(device_probe, re_probe), 245 DEVMETHOD(device_attach, re_attach), 246 DEVMETHOD(device_detach, re_detach), 247 DEVMETHOD(device_suspend, re_suspend), 248 DEVMETHOD(device_resume, re_resume), 249 DEVMETHOD(device_shutdown, re_shutdown), 250 251 /* bus interface */ 252 DEVMETHOD(bus_print_child, bus_generic_print_child), 253 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 254 255 /* MII interface */ 256 DEVMETHOD(miibus_readreg, re_miibus_readreg), 257 DEVMETHOD(miibus_writereg, re_miibus_writereg), 258 DEVMETHOD(miibus_statchg, re_miibus_statchg), 259 260 { 0, 0 } 261}; 262 263static driver_t re_driver = { 264 "re", 265 re_methods, 266 sizeof(struct rl_softc) 267}; 268 269static devclass_t re_devclass; 270 271DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 272DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 273DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 274 275#define EE_SET(x) \ 276 CSR_WRITE_1(sc, RL_EECMD, \ 277 CSR_READ_1(sc, RL_EECMD) | x) 278 279#define EE_CLR(x) \ 280 CSR_WRITE_1(sc, RL_EECMD, \ 281 CSR_READ_1(sc, RL_EECMD) & ~x) 282 283/* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286static void 287re_eeprom_putbyte(sc, addr) 288 struct rl_softc *sc; 289 int addr; 290{ 291 register int d, i; 292 293 d = addr | sc->rl_eecmd_read; 294 295 /* 296 * Feed in each bit and strobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 EE_SET(RL_EE_DATAIN); 301 } else { 302 EE_CLR(RL_EE_DATAIN); 303 } 304 DELAY(100); 305 EE_SET(RL_EE_CLK); 306 DELAY(150); 307 EE_CLR(RL_EE_CLK); 308 DELAY(100); 309 } 310} 311 312/* 313 * Read a word of data stored in the EEPROM at address 'addr.' 314 */ 315static void 316re_eeprom_getword(sc, addr, dest) 317 struct rl_softc *sc; 318 int addr; 319 u_int16_t *dest; 320{ 321 register int i; 322 u_int16_t word = 0; 323 324 /* Enter EEPROM access mode. */ 325 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 326 327 /* 328 * Send address of word we want to read. 329 */ 330 re_eeprom_putbyte(sc, addr); 331 332 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 333 334 /* 335 * Start reading bits from EEPROM. 336 */ 337 for (i = 0x8000; i; i >>= 1) { 338 EE_SET(RL_EE_CLK); 339 DELAY(100); 340 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 341 word |= i; 342 EE_CLR(RL_EE_CLK); 343 DELAY(100); 344 } 345 346 /* Turn off EEPROM access mode. */ 347 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 348 349 *dest = word; 350} 351 352/* 353 * Read a sequence of words from the EEPROM. 354 */ 355static void 356re_read_eeprom(sc, dest, off, cnt, swap) 357 struct rl_softc *sc; 358 caddr_t dest; 359 int off; 360 int cnt; 361 int swap; 362{ 363 int i; 364 u_int16_t word = 0, *ptr; 365 366 for (i = 0; i < cnt; i++) { 367 re_eeprom_getword(sc, off + i, &word); 368 ptr = (u_int16_t *)(dest + (i * 2)); 369 if (swap) 370 *ptr = ntohs(word); 371 else 372 *ptr = word; 373 } 374} 375 376static int 377re_gmii_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380{ 381 struct rl_softc *sc; 382 u_int32_t rval; 383 int i; 384 385 if (phy != 1) 386 return (0); 387 388 sc = device_get_softc(dev); 389 390 /* Let the rgephy driver read the GMEDIASTAT register */ 391 392 if (reg == RL_GMEDIASTAT) { 393 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 394 return (rval); 395 } 396 397 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 398 DELAY(1000); 399 400 for (i = 0; i < RL_TIMEOUT; i++) { 401 rval = CSR_READ_4(sc, RL_PHYAR); 402 if (rval & RL_PHYAR_BUSY) 403 break; 404 DELAY(100); 405 } 406 407 if (i == RL_TIMEOUT) { 408 printf ("re%d: PHY read failed\n", sc->rl_unit); 409 return (0); 410 } 411 412 return (rval & RL_PHYAR_PHYDATA); 413} 414 415static int 416re_gmii_writereg(dev, phy, reg, data) 417 device_t dev; 418 int phy, reg, data; 419{ 420 struct rl_softc *sc; 421 u_int32_t rval; 422 int i; 423 424 sc = device_get_softc(dev); 425 426 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 427 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 428 DELAY(1000); 429 430 for (i = 0; i < RL_TIMEOUT; i++) { 431 rval = CSR_READ_4(sc, RL_PHYAR); 432 if (!(rval & RL_PHYAR_BUSY)) 433 break; 434 DELAY(100); 435 } 436 437 if (i == RL_TIMEOUT) { 438 printf ("re%d: PHY write failed\n", sc->rl_unit); 439 return (0); 440 } 441 442 return (0); 443} 444 445static int 446re_miibus_readreg(dev, phy, reg) 447 device_t dev; 448 int phy, reg; 449{ 450 struct rl_softc *sc; 451 u_int16_t rval = 0; 452 u_int16_t re8139_reg = 0; 453 454 sc = device_get_softc(dev); 455 RL_LOCK(sc); 456 457 if (sc->rl_type == RL_8169) { 458 rval = re_gmii_readreg(dev, phy, reg); 459 RL_UNLOCK(sc); 460 return (rval); 461 } 462 463 /* Pretend the internal PHY is only at address 0 */ 464 if (phy) { 465 RL_UNLOCK(sc); 466 return (0); 467 } 468 switch (reg) { 469 case MII_BMCR: 470 re8139_reg = RL_BMCR; 471 break; 472 case MII_BMSR: 473 re8139_reg = RL_BMSR; 474 break; 475 case MII_ANAR: 476 re8139_reg = RL_ANAR; 477 break; 478 case MII_ANER: 479 re8139_reg = RL_ANER; 480 break; 481 case MII_ANLPAR: 482 re8139_reg = RL_LPAR; 483 break; 484 case MII_PHYIDR1: 485 case MII_PHYIDR2: 486 RL_UNLOCK(sc); 487 return (0); 488 /* 489 * Allow the rlphy driver to read the media status 490 * register. If we have a link partner which does not 491 * support NWAY, this is the register which will tell 492 * us the results of parallel detection. 493 */ 494 case RL_MEDIASTAT: 495 rval = CSR_READ_1(sc, RL_MEDIASTAT); 496 RL_UNLOCK(sc); 497 return (rval); 498 default: 499 printf("re%d: bad phy register\n", sc->rl_unit); 500 RL_UNLOCK(sc); 501 return (0); 502 } 503 rval = CSR_READ_2(sc, re8139_reg); 504 RL_UNLOCK(sc); 505 return (rval); 506} 507 508static int 509re_miibus_writereg(dev, phy, reg, data) 510 device_t dev; 511 int phy, reg, data; 512{ 513 struct rl_softc *sc; 514 u_int16_t re8139_reg = 0; 515 int rval = 0; 516 517 sc = device_get_softc(dev); 518 RL_LOCK(sc); 519 520 if (sc->rl_type == RL_8169) { 521 rval = re_gmii_writereg(dev, phy, reg, data); 522 RL_UNLOCK(sc); 523 return (rval); 524 } 525 526 /* Pretend the internal PHY is only at address 0 */ 527 if (phy) { 528 RL_UNLOCK(sc); 529 return (0); 530 } 531 switch (reg) { 532 case MII_BMCR: 533 re8139_reg = RL_BMCR; 534 break; 535 case MII_BMSR: 536 re8139_reg = RL_BMSR; 537 break; 538 case MII_ANAR: 539 re8139_reg = RL_ANAR; 540 break; 541 case MII_ANER: 542 re8139_reg = RL_ANER; 543 break; 544 case MII_ANLPAR: 545 re8139_reg = RL_LPAR; 546 break; 547 case MII_PHYIDR1: 548 case MII_PHYIDR2: 549 RL_UNLOCK(sc); 550 return (0); 551 break; 552 default: 553 printf("re%d: bad phy register\n", sc->rl_unit); 554 RL_UNLOCK(sc); 555 return (0); 556 } 557 CSR_WRITE_2(sc, re8139_reg, data); 558 RL_UNLOCK(sc); 559 return (0); 560} 561 562static void 563re_miibus_statchg(dev) 564 device_t dev; 565{ 566 567} 568 569/* 570 * Program the 64-bit multicast hash filter. 571 */ 572static void 573re_setmulti(sc) 574 struct rl_softc *sc; 575{ 576 struct ifnet *ifp; 577 int h = 0; 578 u_int32_t hashes[2] = { 0, 0 }; 579 struct ifmultiaddr *ifma; 580 u_int32_t rxfilt; 581 int mcnt = 0; 582 583 ifp = &sc->arpcom.ac_if; 584 585 rxfilt = CSR_READ_4(sc, RL_RXCFG); 586 587 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 588 rxfilt |= RL_RXCFG_RX_MULTI; 589 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 590 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 591 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 592 return; 593 } 594 595 /* first, zot all the existing hash bits */ 596 CSR_WRITE_4(sc, RL_MAR0, 0); 597 CSR_WRITE_4(sc, RL_MAR4, 0); 598 599 /* now program new ones */ 600 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 601 if (ifma->ifma_addr->sa_family != AF_LINK) 602 continue; 603 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 604 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 605 if (h < 32) 606 hashes[0] |= (1 << h); 607 else 608 hashes[1] |= (1 << (h - 32)); 609 mcnt++; 610 } 611 612 if (mcnt) 613 rxfilt |= RL_RXCFG_RX_MULTI; 614 else 615 rxfilt &= ~RL_RXCFG_RX_MULTI; 616 617 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 618 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 619 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 620} 621 622static void 623re_reset(sc) 624 struct rl_softc *sc; 625{ 626 register int i; 627 628 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 629 630 for (i = 0; i < RL_TIMEOUT; i++) { 631 DELAY(10); 632 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 633 break; 634 } 635 if (i == RL_TIMEOUT) 636 printf("re%d: reset never completed!\n", sc->rl_unit); 637 638 CSR_WRITE_1(sc, 0x82, 1); 639} 640 641/* 642 * The following routine is designed to test for a defect on some 643 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 644 * lines connected to the bus, however for a 32-bit only card, they 645 * should be pulled high. The result of this defect is that the 646 * NIC will not work right if you plug it into a 64-bit slot: DMA 647 * operations will be done with 64-bit transfers, which will fail 648 * because the 64-bit data lines aren't connected. 649 * 650 * There's no way to work around this (short of talking a soldering 651 * iron to the board), however we can detect it. The method we use 652 * here is to put the NIC into digital loopback mode, set the receiver 653 * to promiscuous mode, and then try to send a frame. We then compare 654 * the frame data we sent to what was received. If the data matches, 655 * then the NIC is working correctly, otherwise we know the user has 656 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 657 * slot. In the latter case, there's no way the NIC can work correctly, 658 * so we print out a message on the console and abort the device attach. 659 */ 660 661static int 662re_diag(sc) 663 struct rl_softc *sc; 664{ 665 struct ifnet *ifp = &sc->arpcom.ac_if; 666 struct mbuf *m0; 667 struct ether_header *eh; 668 struct rl_desc *cur_rx; 669 u_int16_t status; 670 u_int32_t rxstat; 671 int total_len, i, error = 0; 672 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 673 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 674 675 /* Allocate a single mbuf */ 676 677 MGETHDR(m0, M_DONTWAIT, MT_DATA); 678 if (m0 == NULL) 679 return (ENOBUFS); 680 681 /* 682 * Initialize the NIC in test mode. This sets the chip up 683 * so that it can send and receive frames, but performs the 684 * following special functions: 685 * - Puts receiver in promiscuous mode 686 * - Enables digital loopback mode 687 * - Leaves interrupts turned off 688 */ 689 690 ifp->if_flags |= IFF_PROMISC; 691 sc->rl_testmode = 1; 692 re_init(sc); 693 re_stop(sc); 694 DELAY(100000); 695 re_init(sc); 696 697 /* Put some data in the mbuf */ 698 699 eh = mtod(m0, struct ether_header *); 700 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 701 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 702 eh->ether_type = htons(ETHERTYPE_IP); 703 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 704 705 /* 706 * Queue the packet, start transmission. 707 * Note: IF_HANDOFF() ultimately calls re_start() for us. 708 */ 709 710 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 711 IF_HANDOFF(&ifp->if_snd, m0, ifp); 712 m0 = NULL; 713 714 /* Wait for it to propagate through the chip */ 715 716 DELAY(100000); 717 for (i = 0; i < RL_TIMEOUT; i++) { 718 status = CSR_READ_2(sc, RL_ISR); 719 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 720 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 721 break; 722 DELAY(10); 723 } 724 725 if (i == RL_TIMEOUT) { 726 printf("re%d: diagnostic failed, failed to receive packet " 727 "in loopback mode\n", sc->rl_unit); 728 error = EIO; 729 goto done; 730 } 731 732 /* 733 * The packet should have been dumped into the first 734 * entry in the RX DMA ring. Grab it from there. 735 */ 736 737 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 738 sc->rl_ldata.rl_rx_list_map, 739 BUS_DMASYNC_POSTREAD); 740 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 741 sc->rl_ldata.rl_rx_dmamap[0], 742 BUS_DMASYNC_POSTWRITE); 743 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 744 sc->rl_ldata.rl_rx_dmamap[0]); 745 746 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 747 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 748 eh = mtod(m0, struct ether_header *); 749 750 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 751 total_len = RL_RXBYTES(cur_rx); 752 rxstat = le32toh(cur_rx->rl_cmdstat); 753 754 if (total_len != ETHER_MIN_LEN) { 755 printf("re%d: diagnostic failed, received short packet\n", 756 sc->rl_unit); 757 error = EIO; 758 goto done; 759 } 760 761 /* Test that the received packet data matches what we sent. */ 762 763 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 764 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 765 ntohs(eh->ether_type) != ETHERTYPE_IP) { 766 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 767 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 768 dst, ":", src, ":", ETHERTYPE_IP); 769 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 770 eh->ether_dhost, ":", eh->ether_shost, ":", 771 ntohs(eh->ether_type)); 772 printf("re%d: You may have a defective 32-bit NIC plugged " 773 "into a 64-bit PCI slot.\n", sc->rl_unit); 774 printf("re%d: Please re-install the NIC in a 32-bit slot " 775 "for proper operation.\n", sc->rl_unit); 776 printf("re%d: Read the re(4) man page for more details.\n", 777 sc->rl_unit); 778 error = EIO; 779 } 780 781done: 782 /* Turn interface off, release resources */ 783 784 sc->rl_testmode = 0; 785 ifp->if_flags &= ~IFF_PROMISC; 786 re_stop(sc); 787 if (m0 != NULL) 788 m_freem(m0); 789 790 return (error); 791} 792 793/* 794 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 795 * IDs against our list and return a device name if we find a match. 796 */ 797static int 798re_probe(dev) 799 device_t dev; 800{ 801 struct rl_type *t; 802 struct rl_softc *sc; 803 int rid; 804 u_int32_t hwrev; 805 806 t = re_devs; 807 sc = device_get_softc(dev); 808 809 while (t->rl_name != NULL) { 810 if ((pci_get_vendor(dev) == t->rl_vid) && 811 (pci_get_device(dev) == t->rl_did)) { 812 813 /* 814 * Temporarily map the I/O space 815 * so we can read the chip ID register. 816 */ 817 rid = RL_RID; 818 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 819 RF_ACTIVE); 820 if (sc->rl_res == NULL) { 821 device_printf(dev, 822 "couldn't map ports/memory\n"); 823 return (ENXIO); 824 } 825 sc->rl_btag = rman_get_bustag(sc->rl_res); 826 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 827 mtx_init(&sc->rl_mtx, 828 device_get_nameunit(dev), 829 MTX_NETWORK_LOCK, MTX_DEF); 830 RL_LOCK(sc); 831 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 832 bus_release_resource(dev, RL_RES, 833 RL_RID, sc->rl_res); 834 RL_UNLOCK(sc); 835 mtx_destroy(&sc->rl_mtx); 836 if (t->rl_basetype == hwrev) { 837 device_set_desc(dev, t->rl_name); 838 return (0); 839 } 840 } 841 t++; 842 } 843 844 return (ENXIO); 845} 846 847/* 848 * This routine takes the segment list provided as the result of 849 * a bus_dma_map_load() operation and assigns the addresses/lengths 850 * to RealTek DMA descriptors. This can be called either by the RX 851 * code or the TX code. In the RX case, we'll probably wind up mapping 852 * at most one segment. For the TX case, there could be any number of 853 * segments since TX packets may span multiple mbufs. In either case, 854 * if the number of segments is larger than the rl_maxsegs limit 855 * specified by the caller, we abort the mapping operation. Sadly, 856 * whoever designed the buffer mapping API did not provide a way to 857 * return an error from here, so we have to fake it a bit. 858 */ 859 860static void 861re_dma_map_desc(arg, segs, nseg, mapsize, error) 862 void *arg; 863 bus_dma_segment_t *segs; 864 int nseg; 865 bus_size_t mapsize; 866 int error; 867{ 868 struct rl_dmaload_arg *ctx; 869 struct rl_desc *d = NULL; 870 int i = 0, idx; 871 872 if (error) 873 return; 874 875 ctx = arg; 876 877 /* Signal error to caller if there's too many segments */ 878 if (nseg > ctx->rl_maxsegs) { 879 ctx->rl_maxsegs = 0; 880 return; 881 } 882 883 /* 884 * Map the segment array into descriptors. Note that we set the 885 * start-of-frame and end-of-frame markers for either TX or RX, but 886 * they really only have meaning in the TX case. (In the RX case, 887 * it's the chip that tells us where packets begin and end.) 888 * We also keep track of the end of the ring and set the 889 * end-of-ring bits as needed, and we set the ownership bits 890 * in all except the very first descriptor. (The caller will 891 * set this descriptor later when it start transmission or 892 * reception.) 893 */ 894 idx = ctx->rl_idx; 895 for (;;) { 896 u_int32_t cmdstat; 897 d = &ctx->rl_ring[idx]; 898 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 899 ctx->rl_maxsegs = 0; 900 return; 901 } 902 cmdstat = segs[i].ds_len; 903 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 904 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 905 if (i == 0) 906 cmdstat |= RL_TDESC_CMD_SOF; 907 else 908 cmdstat |= RL_TDESC_CMD_OWN; 909 if (idx == (RL_RX_DESC_CNT - 1)) 910 cmdstat |= RL_TDESC_CMD_EOR; 911 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 912 i++; 913 if (i == nseg) 914 break; 915 RL_DESC_INC(idx); 916 } 917 918 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 919 ctx->rl_maxsegs = nseg; 920 ctx->rl_idx = idx; 921} 922 923/* 924 * Map a single buffer address. 925 */ 926 927static void 928re_dma_map_addr(arg, segs, nseg, error) 929 void *arg; 930 bus_dma_segment_t *segs; 931 int nseg; 932 int error; 933{ 934 u_int32_t *addr; 935 936 if (error) 937 return; 938 939 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 940 addr = arg; 941 *addr = segs->ds_addr; 942} 943 944static int 945re_allocmem(dev, sc) 946 device_t dev; 947 struct rl_softc *sc; 948{ 949 int error; 950 int nseg; 951 int i; 952 953 /* 954 * Allocate map for RX mbufs. 955 */ 956 nseg = 32; 957 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 958 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 959 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 960 NULL, NULL, &sc->rl_ldata.rl_mtag); 961 if (error) { 962 device_printf(dev, "could not allocate dma tag\n"); 963 return (ENOMEM); 964 } 965 966 /* 967 * Allocate map for TX descriptor list. 968 */ 969 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 970 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 971 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 972 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 973 if (error) { 974 device_printf(dev, "could not allocate dma tag\n"); 975 return (ENOMEM); 976 } 977 978 /* Allocate DMA'able memory for the TX ring */ 979 980 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 981 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 982 &sc->rl_ldata.rl_tx_list_map); 983 if (error) 984 return (ENOMEM); 985 986 /* Load the map for the TX ring. */ 987 988 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 989 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 990 RL_TX_LIST_SZ, re_dma_map_addr, 991 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 992 993 /* Create DMA maps for TX buffers */ 994 995 for (i = 0; i < RL_TX_DESC_CNT; i++) { 996 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 997 &sc->rl_ldata.rl_tx_dmamap[i]); 998 if (error) { 999 device_printf(dev, "can't create DMA map for TX\n"); 1000 return (ENOMEM); 1001 } 1002 } 1003 1004 /* 1005 * Allocate map for RX descriptor list. 1006 */ 1007 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1008 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1009 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1010 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1011 if (error) { 1012 device_printf(dev, "could not allocate dma tag\n"); 1013 return (ENOMEM); 1014 } 1015 1016 /* Allocate DMA'able memory for the RX ring */ 1017 1018 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1019 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1020 &sc->rl_ldata.rl_rx_list_map); 1021 if (error) 1022 return (ENOMEM); 1023 1024 /* Load the map for the RX ring. */ 1025 1026 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1027 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1028 RL_TX_LIST_SZ, re_dma_map_addr, 1029 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1030 1031 /* Create DMA maps for RX buffers */ 1032 1033 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1034 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1035 &sc->rl_ldata.rl_rx_dmamap[i]); 1036 if (error) { 1037 device_printf(dev, "can't create DMA map for RX\n"); 1038 return (ENOMEM); 1039 } 1040 } 1041 1042 return (0); 1043} 1044 1045/* 1046 * Attach the interface. Allocate softc structures, do ifmedia 1047 * setup and ethernet/BPF attach. 1048 */ 1049static int 1050re_attach(dev) 1051 device_t dev; 1052{ 1053 u_char eaddr[ETHER_ADDR_LEN]; 1054 u_int16_t as[3]; 1055 struct rl_softc *sc; 1056 struct ifnet *ifp; 1057 struct rl_hwrev *hw_rev; 1058 int hwrev; 1059 u_int16_t re_did = 0; 1060 int unit, error = 0, rid, i; 1061 1062 sc = device_get_softc(dev); 1063 unit = device_get_unit(dev); 1064 1065 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1066 MTX_DEF | MTX_RECURSE); 1067 /* 1068 * Map control/status registers. 1069 */ 1070 pci_enable_busmaster(dev); 1071 1072 rid = RL_RID; 1073 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1074 RF_ACTIVE); 1075 1076 if (sc->rl_res == NULL) { 1077 printf ("re%d: couldn't map ports/memory\n", unit); 1078 error = ENXIO; 1079 goto fail; 1080 } 1081 1082 sc->rl_btag = rman_get_bustag(sc->rl_res); 1083 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1084 1085 /* Allocate interrupt */ 1086 rid = 0; 1087 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1088 RF_SHAREABLE | RF_ACTIVE); 1089 1090 if (sc->rl_irq == NULL) { 1091 printf("re%d: couldn't map interrupt\n", unit); 1092 error = ENXIO; 1093 goto fail; 1094 } 1095 1096 /* Reset the adapter. */ 1097 re_reset(sc); 1098 1099 hw_rev = re_hwrevs; 1100 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1101 while (hw_rev->rl_desc != NULL) { 1102 if (hw_rev->rl_rev == hwrev) { 1103 sc->rl_type = hw_rev->rl_type; 1104 break; 1105 } 1106 hw_rev++; 1107 } 1108 1109 if (sc->rl_type == RL_8169) { 1110 1111 /* Set RX length mask */ 1112 1113 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1114 1115 /* Force station address autoload from the EEPROM */ 1116 1117 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1118 for (i = 0; i < RL_TIMEOUT; i++) { 1119 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1120 break; 1121 DELAY(100); 1122 } 1123 if (i == RL_TIMEOUT) 1124 printf ("re%d: eeprom autoload timed out\n", unit); 1125 1126 for (i = 0; i < ETHER_ADDR_LEN; i++) 1127 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1128 } else { 1129 1130 /* Set RX length mask */ 1131 1132 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1133 1134 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1135 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1136 if (re_did != 0x8129) 1137 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1138 1139 /* 1140 * Get station address from the EEPROM. 1141 */ 1142 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1143 for (i = 0; i < 3; i++) { 1144 eaddr[(i * 2) + 0] = as[i] & 0xff; 1145 eaddr[(i * 2) + 1] = as[i] >> 8; 1146 } 1147 } 1148 1149 sc->rl_unit = unit; 1150 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1151 1152 /* 1153 * Allocate the parent bus DMA tag appropriate for PCI. 1154 */ 1155#define RL_NSEG_NEW 32 1156 error = bus_dma_tag_create(NULL, /* parent */ 1157 1, 0, /* alignment, boundary */ 1158 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1159 BUS_SPACE_MAXADDR, /* highaddr */ 1160 NULL, NULL, /* filter, filterarg */ 1161 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1162 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1163 BUS_DMA_ALLOCNOW, /* flags */ 1164 NULL, NULL, /* lockfunc, lockarg */ 1165 &sc->rl_parent_tag); 1166 if (error) 1167 goto fail; 1168 1169 error = re_allocmem(dev, sc); 1170 1171 if (error) 1172 goto fail; 1173 1174 /* Do MII setup */ 1175 if (mii_phy_probe(dev, &sc->rl_miibus, 1176 re_ifmedia_upd, re_ifmedia_sts)) { 1177 printf("re%d: MII without any phy!\n", sc->rl_unit); 1178 error = ENXIO; 1179 goto fail; 1180 } 1181 1182 ifp = &sc->arpcom.ac_if; 1183 ifp->if_softc = sc; 1184 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1185 ifp->if_mtu = ETHERMTU; 1186 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1187 ifp->if_ioctl = re_ioctl; 1188 ifp->if_capabilities = IFCAP_VLAN_MTU; 1189 ifp->if_start = re_start; 1190 ifp->if_hwassist = RE_CSUM_FEATURES; 1191 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1192#ifdef DEVICE_POLLING 1193 ifp->if_capabilities |= IFCAP_POLLING; 1194#endif 1195 ifp->if_watchdog = re_watchdog; 1196 ifp->if_init = re_init; 1197 if (sc->rl_type == RL_8169) 1198 ifp->if_baudrate = 1000000000; 1199 else 1200 ifp->if_baudrate = 100000000; 1201 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; 1202 ifp->if_capenable = ifp->if_capabilities; 1203 1204 callout_handle_init(&sc->rl_stat_ch); 1205 1206 /* 1207 * Call MI attach routine. 1208 */ 1209 ether_ifattach(ifp, eaddr); 1210 1211 /* Perform hardware diagnostic. */ 1212 error = re_diag(sc); 1213 1214 if (error) { 1215 printf("re%d: attach aborted due to hardware diag failure\n", 1216 unit); 1217 ether_ifdetach(ifp); 1218 goto fail; 1219 } 1220 1221 /* Hook interrupt last to avoid having to lock softc */ 1222 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1223 re_intr, sc, &sc->rl_intrhand); 1224 1225 if (error) { 1226 printf("re%d: couldn't set up irq\n", unit); 1227 ether_ifdetach(ifp); 1228 goto fail; 1229 } 1230 1231fail: 1232 if (error) 1233 re_detach(dev); 1234 1235 return (error); 1236} 1237 1238/* 1239 * Shutdown hardware and free up resources. This can be called any 1240 * time after the mutex has been initialized. It is called in both 1241 * the error case in attach and the normal detach case so it needs 1242 * to be careful about only freeing resources that have actually been 1243 * allocated. 1244 */ 1245static int 1246re_detach(dev) 1247 device_t dev; 1248{ 1249 struct rl_softc *sc; 1250 struct ifnet *ifp; 1251 int i; 1252 1253 sc = device_get_softc(dev); 1254 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1255 RL_LOCK(sc); 1256 ifp = &sc->arpcom.ac_if; 1257 1258 /* These should only be active if attach succeeded */ 1259 if (device_is_attached(dev)) { 1260 re_stop(sc); 1261 /* 1262 * Force off the IFF_UP flag here, in case someone 1263 * still had a BPF descriptor attached to this 1264 * interface. If they do, ether_ifattach() will cause 1265 * the BPF code to try and clear the promisc mode 1266 * flag, which will bubble down to re_ioctl(), 1267 * which will try to call re_init() again. This will 1268 * turn the NIC back on and restart the MII ticker, 1269 * which will panic the system when the kernel tries 1270 * to invoke the re_tick() function that isn't there 1271 * anymore. 1272 */ 1273 ifp->if_flags &= ~IFF_UP; 1274 ether_ifdetach(ifp); 1275 } 1276 if (sc->rl_miibus) 1277 device_delete_child(dev, sc->rl_miibus); 1278 bus_generic_detach(dev); 1279 1280 if (sc->rl_intrhand) 1281 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1282 if (sc->rl_irq) 1283 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1284 if (sc->rl_res) 1285 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1286 1287 1288 /* Unload and free the RX DMA ring memory and map */ 1289 1290 if (sc->rl_ldata.rl_rx_list_tag) { 1291 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1292 sc->rl_ldata.rl_rx_list_map); 1293 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1294 sc->rl_ldata.rl_rx_list, 1295 sc->rl_ldata.rl_rx_list_map); 1296 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1297 } 1298 1299 /* Unload and free the TX DMA ring memory and map */ 1300 1301 if (sc->rl_ldata.rl_tx_list_tag) { 1302 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1303 sc->rl_ldata.rl_tx_list_map); 1304 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1305 sc->rl_ldata.rl_tx_list, 1306 sc->rl_ldata.rl_tx_list_map); 1307 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1308 } 1309 1310 /* Destroy all the RX and TX buffer maps */ 1311 1312 if (sc->rl_ldata.rl_mtag) { 1313 for (i = 0; i < RL_TX_DESC_CNT; i++) 1314 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1315 sc->rl_ldata.rl_tx_dmamap[i]); 1316 for (i = 0; i < RL_RX_DESC_CNT; i++) 1317 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1318 sc->rl_ldata.rl_rx_dmamap[i]); 1319 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1320 } 1321 1322 /* Unload and free the stats buffer and map */ 1323 1324 if (sc->rl_ldata.rl_stag) { 1325 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1326 sc->rl_ldata.rl_rx_list_map); 1327 bus_dmamem_free(sc->rl_ldata.rl_stag, 1328 sc->rl_ldata.rl_stats, 1329 sc->rl_ldata.rl_smap); 1330 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1331 } 1332 1333 if (sc->rl_parent_tag) 1334 bus_dma_tag_destroy(sc->rl_parent_tag); 1335 1336 RL_UNLOCK(sc); 1337 mtx_destroy(&sc->rl_mtx); 1338 1339 return (0); 1340} 1341 1342static int 1343re_newbuf(sc, idx, m) 1344 struct rl_softc *sc; 1345 int idx; 1346 struct mbuf *m; 1347{ 1348 struct rl_dmaload_arg arg; 1349 struct mbuf *n = NULL; 1350 int error; 1351 1352 if (m == NULL) { 1353 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1354 if (n == NULL) 1355 return (ENOBUFS); 1356 m = n; 1357 } else 1358 m->m_data = m->m_ext.ext_buf; 1359 1360 /* 1361 * Initialize mbuf length fields and fixup 1362 * alignment so that the frame payload is 1363 * longword aligned. 1364 */ 1365 m->m_len = m->m_pkthdr.len = MCLBYTES; 1366 m_adj(m, ETHER_ALIGN); 1367 1368 arg.sc = sc; 1369 arg.rl_idx = idx; 1370 arg.rl_maxsegs = 1; 1371 arg.rl_flags = 0; 1372 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1373 1374 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1375 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1376 &arg, BUS_DMA_NOWAIT); 1377 if (error || arg.rl_maxsegs != 1) { 1378 if (n != NULL) 1379 m_freem(n); 1380 return (ENOMEM); 1381 } 1382 1383 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1384 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1385 1386 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1387 sc->rl_ldata.rl_rx_dmamap[idx], 1388 BUS_DMASYNC_PREREAD); 1389 1390 return (0); 1391} 1392 1393static int 1394re_tx_list_init(sc) 1395 struct rl_softc *sc; 1396{ 1397 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1398 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1399 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1400 1401 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1402 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1403 sc->rl_ldata.rl_tx_prodidx = 0; 1404 sc->rl_ldata.rl_tx_considx = 0; 1405 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1406 1407 return (0); 1408} 1409 1410static int 1411re_rx_list_init(sc) 1412 struct rl_softc *sc; 1413{ 1414 int i; 1415 1416 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1417 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1418 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1419 1420 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1421 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1422 return (ENOBUFS); 1423 } 1424 1425 /* Flush the RX descriptors */ 1426 1427 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1428 sc->rl_ldata.rl_rx_list_map, 1429 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1430 1431 sc->rl_ldata.rl_rx_prodidx = 0; 1432 sc->rl_head = sc->rl_tail = NULL; 1433 1434 return (0); 1435} 1436 1437/* 1438 * RX handler for C+ and 8169. For the gigE chips, we support 1439 * the reception of jumbo frames that have been fragmented 1440 * across multiple 2K mbuf cluster buffers. 1441 */ 1442static void 1443re_rxeof(sc) 1444 struct rl_softc *sc; 1445{ 1446 struct mbuf *m; 1447 struct ifnet *ifp; 1448 int i, total_len; 1449 struct rl_desc *cur_rx; 1450 u_int32_t rxstat, rxvlan; 1451 1452 RL_LOCK_ASSERT(sc); 1453 1454 ifp = &sc->arpcom.ac_if; 1455 i = sc->rl_ldata.rl_rx_prodidx; 1456 1457 /* Invalidate the descriptor memory */ 1458 1459 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1460 sc->rl_ldata.rl_rx_list_map, 1461 BUS_DMASYNC_POSTREAD); 1462 1463 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1464 1465 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1466 m = sc->rl_ldata.rl_rx_mbuf[i]; 1467 total_len = RL_RXBYTES(cur_rx); 1468 rxstat = le32toh(cur_rx->rl_cmdstat); 1469 rxvlan = le32toh(cur_rx->rl_vlanctl); 1470 1471 /* Invalidate the RX mbuf and unload its map */ 1472 1473 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1474 sc->rl_ldata.rl_rx_dmamap[i], 1475 BUS_DMASYNC_POSTWRITE); 1476 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1477 sc->rl_ldata.rl_rx_dmamap[i]); 1478 1479 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1480 m->m_len = MCLBYTES - ETHER_ALIGN; 1481 if (sc->rl_head == NULL) 1482 sc->rl_head = sc->rl_tail = m; 1483 else { 1484 m->m_flags &= ~M_PKTHDR; 1485 sc->rl_tail->m_next = m; 1486 sc->rl_tail = m; 1487 } 1488 re_newbuf(sc, i, NULL); 1489 RL_DESC_INC(i); 1490 continue; 1491 } 1492 1493 /* 1494 * NOTE: for the 8139C+, the frame length field 1495 * is always 12 bits in size, but for the gigE chips, 1496 * it is 13 bits (since the max RX frame length is 16K). 1497 * Unfortunately, all 32 bits in the status word 1498 * were already used, so to make room for the extra 1499 * length bit, RealTek took out the 'frame alignment 1500 * error' bit and shifted the other status bits 1501 * over one slot. The OWN, EOR, FS and LS bits are 1502 * still in the same places. We have already extracted 1503 * the frame length and checked the OWN bit, so rather 1504 * than using an alternate bit mapping, we shift the 1505 * status bits one space to the right so we can evaluate 1506 * them using the 8169 status as though it was in the 1507 * same format as that of the 8139C+. 1508 */ 1509 if (sc->rl_type == RL_8169) 1510 rxstat >>= 1; 1511 1512 if (rxstat & RL_RDESC_STAT_RXERRSUM) { 1513 ifp->if_ierrors++; 1514 /* 1515 * If this is part of a multi-fragment packet, 1516 * discard all the pieces. 1517 */ 1518 if (sc->rl_head != NULL) { 1519 m_freem(sc->rl_head); 1520 sc->rl_head = sc->rl_tail = NULL; 1521 } 1522 re_newbuf(sc, i, m); 1523 RL_DESC_INC(i); 1524 continue; 1525 } 1526 1527 /* 1528 * If allocating a replacement mbuf fails, 1529 * reload the current one. 1530 */ 1531 1532 if (re_newbuf(sc, i, NULL)) { 1533 ifp->if_ierrors++; 1534 if (sc->rl_head != NULL) { 1535 m_freem(sc->rl_head); 1536 sc->rl_head = sc->rl_tail = NULL; 1537 } 1538 re_newbuf(sc, i, m); 1539 RL_DESC_INC(i); 1540 continue; 1541 } 1542 1543 RL_DESC_INC(i); 1544 1545 if (sc->rl_head != NULL) { 1546 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1547 /* 1548 * Special case: if there's 4 bytes or less 1549 * in this buffer, the mbuf can be discarded: 1550 * the last 4 bytes is the CRC, which we don't 1551 * care about anyway. 1552 */ 1553 if (m->m_len <= ETHER_CRC_LEN) { 1554 sc->rl_tail->m_len -= 1555 (ETHER_CRC_LEN - m->m_len); 1556 m_freem(m); 1557 } else { 1558 m->m_len -= ETHER_CRC_LEN; 1559 m->m_flags &= ~M_PKTHDR; 1560 sc->rl_tail->m_next = m; 1561 } 1562 m = sc->rl_head; 1563 sc->rl_head = sc->rl_tail = NULL; 1564 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1565 } else 1566 m->m_pkthdr.len = m->m_len = 1567 (total_len - ETHER_CRC_LEN); 1568 1569 ifp->if_ipackets++; 1570 m->m_pkthdr.rcvif = ifp; 1571 1572 /* Do RX checksumming if enabled */ 1573 1574 if (ifp->if_capenable & IFCAP_RXCSUM) { 1575 1576 /* Check IP header checksum */ 1577 if (rxstat & RL_RDESC_STAT_PROTOID) 1578 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1579 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1580 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1581 1582 /* Check TCP/UDP checksum */ 1583 if ((RL_TCPPKT(rxstat) && 1584 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1585 (RL_UDPPKT(rxstat) && 1586 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1587 m->m_pkthdr.csum_flags |= 1588 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1589 m->m_pkthdr.csum_data = 0xffff; 1590 } 1591 } 1592 1593 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1594 VLAN_INPUT_TAG(ifp, m, 1595 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1596 RL_UNLOCK(sc); 1597 (*ifp->if_input)(ifp, m); 1598 RL_LOCK(sc); 1599 } 1600 1601 /* Flush the RX DMA ring */ 1602 1603 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1604 sc->rl_ldata.rl_rx_list_map, 1605 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1606 1607 sc->rl_ldata.rl_rx_prodidx = i; 1608} 1609 1610static void 1611re_txeof(sc) 1612 struct rl_softc *sc; 1613{ 1614 struct ifnet *ifp; 1615 u_int32_t txstat; 1616 int idx; 1617 1618 ifp = &sc->arpcom.ac_if; 1619 idx = sc->rl_ldata.rl_tx_considx; 1620 1621 /* Invalidate the TX descriptor list */ 1622 1623 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1624 sc->rl_ldata.rl_tx_list_map, 1625 BUS_DMASYNC_POSTREAD); 1626 1627 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1628 1629 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1630 if (txstat & RL_TDESC_CMD_OWN) 1631 break; 1632 1633 /* 1634 * We only stash mbufs in the last descriptor 1635 * in a fragment chain, which also happens to 1636 * be the only place where the TX status bits 1637 * are valid. 1638 */ 1639 1640 if (txstat & RL_TDESC_CMD_EOF) { 1641 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1642 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1643 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1644 sc->rl_ldata.rl_tx_dmamap[idx]); 1645 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1646 RL_TDESC_STAT_COLCNT)) 1647 ifp->if_collisions++; 1648 if (txstat & RL_TDESC_STAT_TXERRSUM) 1649 ifp->if_oerrors++; 1650 else 1651 ifp->if_opackets++; 1652 } 1653 sc->rl_ldata.rl_tx_free++; 1654 RL_DESC_INC(idx); 1655 } 1656 1657 /* No changes made to the TX ring, so no flush needed */ 1658 1659 if (idx != sc->rl_ldata.rl_tx_considx) { 1660 sc->rl_ldata.rl_tx_considx = idx; 1661 ifp->if_flags &= ~IFF_OACTIVE; 1662 ifp->if_timer = 0; 1663 } 1664 1665 /* 1666 * If not all descriptors have been released reaped yet, 1667 * reload the timer so that we will eventually get another 1668 * interrupt that will cause us to re-enter this routine. 1669 * This is done in case the transmitter has gone idle. 1670 */ 1671 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1672 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1673} 1674 1675static void 1676re_tick(xsc) 1677 void *xsc; 1678{ 1679 struct rl_softc *sc; 1680 struct mii_data *mii; 1681 1682 sc = xsc; 1683 RL_LOCK(sc); 1684 mii = device_get_softc(sc->rl_miibus); 1685 1686 mii_tick(mii); 1687 1688 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1689 RL_UNLOCK(sc); 1690} 1691 1692#ifdef DEVICE_POLLING 1693static void 1694re_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1695{ 1696 struct rl_softc *sc = ifp->if_softc; 1697 1698 RL_LOCK(sc); 1699 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1700 ether_poll_deregister(ifp); 1701 cmd = POLL_DEREGISTER; 1702 } 1703 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1704 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1705 goto done; 1706 } 1707 1708 sc->rxcycles = count; 1709 re_rxeof(sc); 1710 re_txeof(sc); 1711 1712 if (ifp->if_snd.ifq_head != NULL) 1713 (*ifp->if_start)(ifp); 1714 1715 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1716 u_int16_t status; 1717 1718 status = CSR_READ_2(sc, RL_ISR); 1719 if (status == 0xffff) 1720 goto done; 1721 if (status) 1722 CSR_WRITE_2(sc, RL_ISR, status); 1723 1724 /* 1725 * XXX check behaviour on receiver stalls. 1726 */ 1727 1728 if (status & RL_ISR_SYSTEM_ERR) { 1729 re_reset(sc); 1730 re_init(sc); 1731 } 1732 } 1733done: 1734 RL_UNLOCK(sc); 1735} 1736#endif /* DEVICE_POLLING */ 1737 1738static void 1739re_intr(arg) 1740 void *arg; 1741{ 1742 struct rl_softc *sc; 1743 struct ifnet *ifp; 1744 u_int16_t status; 1745 1746 sc = arg; 1747 1748 if (sc->suspended) { 1749 return; 1750 } 1751 1752 RL_LOCK(sc); 1753 ifp = &sc->arpcom.ac_if; 1754 1755 if (!(ifp->if_flags & IFF_UP)) { 1756 RL_UNLOCK(sc); 1757 return; 1758 } 1759 1760#ifdef DEVICE_POLLING 1761 if (ifp->if_flags & IFF_POLLING) 1762 goto done; 1763 if ((ifp->if_capenable & IFCAP_POLLING) && 1764 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1765 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1766 re_poll(ifp, 0, 1); 1767 goto done; 1768 } 1769#endif /* DEVICE_POLLING */ 1770 1771 for (;;) { 1772 1773 status = CSR_READ_2(sc, RL_ISR); 1774 /* If the card has gone away the read returns 0xffff. */ 1775 if (status == 0xffff) 1776 break; 1777 if (status) 1778 CSR_WRITE_2(sc, RL_ISR, status); 1779 1780 if ((status & RL_INTRS_CPLUS) == 0) 1781 break; 1782 1783 if (status & RL_ISR_RX_OK) 1784 re_rxeof(sc); 1785 1786 if (status & RL_ISR_RX_ERR) 1787 re_rxeof(sc); 1788 1789 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1790 (status & RL_ISR_TX_ERR) || 1791 (status & RL_ISR_TX_DESC_UNAVAIL)) 1792 re_txeof(sc); 1793 1794 if (status & RL_ISR_SYSTEM_ERR) { 1795 re_reset(sc); 1796 re_init(sc); 1797 } 1798 1799 if (status & RL_ISR_LINKCHG) { 1800 untimeout(re_tick, sc, sc->rl_stat_ch); 1801 re_tick(sc); 1802 } 1803 } 1804 1805 if (ifp->if_snd.ifq_head != NULL) 1806 (*ifp->if_start)(ifp); 1807 1808#ifdef DEVICE_POLLING 1809done: 1810#endif 1811 RL_UNLOCK(sc); 1812} 1813 1814static int 1815re_encap(sc, m_head, idx) 1816 struct rl_softc *sc; 1817 struct mbuf *m_head; 1818 int *idx; 1819{ 1820 struct mbuf *m_new = NULL; 1821 struct rl_dmaload_arg arg; 1822 bus_dmamap_t map; 1823 int error; 1824 struct m_tag *mtag; 1825 1826 if (sc->rl_ldata.rl_tx_free <= 4) 1827 return (EFBIG); 1828 1829 /* 1830 * Set up checksum offload. Note: checksum offload bits must 1831 * appear in all descriptors of a multi-descriptor transmit 1832 * attempt. (This is according to testing done with an 8169 1833 * chip. I'm not sure if this is a requirement or a bug.) 1834 */ 1835 1836 arg.rl_flags = 0; 1837 1838 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1839 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1840 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1841 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1842 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1843 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1844 1845 arg.sc = sc; 1846 arg.rl_idx = *idx; 1847 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1848 if (arg.rl_maxsegs > 4) 1849 arg.rl_maxsegs -= 4; 1850 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1851 1852 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1853 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1854 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1855 1856 if (error && error != EFBIG) { 1857 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1858 return (ENOBUFS); 1859 } 1860 1861 /* Too many segments to map, coalesce into a single mbuf */ 1862 1863 if (error || arg.rl_maxsegs == 0) { 1864 m_new = m_defrag(m_head, M_DONTWAIT); 1865 if (m_new == NULL) 1866 return (1); 1867 else 1868 m_head = m_new; 1869 1870 arg.sc = sc; 1871 arg.rl_idx = *idx; 1872 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1873 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1874 1875 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1876 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1877 if (error) { 1878 printf("re%d: can't map mbuf (error %d)\n", 1879 sc->rl_unit, error); 1880 return (EFBIG); 1881 } 1882 } 1883 1884 /* 1885 * Insure that the map for this transmission 1886 * is placed at the array index of the last descriptor 1887 * in this chain. 1888 */ 1889 sc->rl_ldata.rl_tx_dmamap[*idx] = 1890 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1891 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1892 1893 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head; 1894 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1895 1896 /* 1897 * Set up hardware VLAN tagging. Note: vlan tag info must 1898 * appear in the first descriptor of a multi-descriptor 1899 * transmission attempt. 1900 */ 1901 1902 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1903 if (mtag != NULL) 1904 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1905 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1906 1907 /* Transfer ownership of packet to the chip. */ 1908 1909 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1910 htole32(RL_TDESC_CMD_OWN); 1911 if (*idx != arg.rl_idx) 1912 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1913 htole32(RL_TDESC_CMD_OWN); 1914 1915 RL_DESC_INC(arg.rl_idx); 1916 *idx = arg.rl_idx; 1917 1918 return (0); 1919} 1920 1921/* 1922 * Main transmit routine for C+ and gigE NICs. 1923 */ 1924 1925static void 1926re_start(ifp) 1927 struct ifnet *ifp; 1928{ 1929 struct rl_softc *sc; 1930 struct mbuf *m_head = NULL; 1931 int idx; 1932 1933 sc = ifp->if_softc; 1934 RL_LOCK(sc); 1935 1936 idx = sc->rl_ldata.rl_tx_prodidx; 1937 1938 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 1939 IF_DEQUEUE(&ifp->if_snd, m_head); 1940 if (m_head == NULL) 1941 break; 1942 1943 if (re_encap(sc, m_head, &idx)) { 1944 IF_PREPEND(&ifp->if_snd, m_head); 1945 ifp->if_flags |= IFF_OACTIVE; 1946 break; 1947 } 1948 1949 /* 1950 * If there's a BPF listener, bounce a copy of this frame 1951 * to him. 1952 */ 1953 BPF_MTAP(ifp, m_head); 1954 } 1955 1956 /* Flush the TX descriptors */ 1957 1958 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1959 sc->rl_ldata.rl_tx_list_map, 1960 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1961 1962 sc->rl_ldata.rl_tx_prodidx = idx; 1963 1964 /* 1965 * RealTek put the TX poll request register in a different 1966 * location on the 8169 gigE chip. I don't know why. 1967 */ 1968 1969 if (sc->rl_type == RL_8169) 1970 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 1971 else 1972 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 1973 1974 /* 1975 * Use the countdown timer for interrupt moderation. 1976 * 'TX done' interrupts are disabled. Instead, we reset the 1977 * countdown timer, which will begin counting until it hits 1978 * the value in the TIMERINT register, and then trigger an 1979 * interrupt. Each time we write to the TIMERCNT register, 1980 * the timer count is reset to 0. 1981 */ 1982 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1983 1984 RL_UNLOCK(sc); 1985 1986 /* 1987 * Set a timeout in case the chip goes out to lunch. 1988 */ 1989 ifp->if_timer = 5; 1990} 1991 1992static void 1993re_init(xsc) 1994 void *xsc; 1995{ 1996 struct rl_softc *sc = xsc; 1997 struct ifnet *ifp = &sc->arpcom.ac_if; 1998 struct mii_data *mii; 1999 u_int32_t rxcfg = 0; 2000 2001 RL_LOCK(sc); 2002 mii = device_get_softc(sc->rl_miibus); 2003 2004 /* 2005 * Cancel pending I/O and free all RX/TX buffers. 2006 */ 2007 re_stop(sc); 2008 2009 /* 2010 * Enable C+ RX and TX mode, as well as VLAN stripping and 2011 * RX checksum offload. We must configure the C+ register 2012 * before all others. 2013 */ 2014 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2015 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2016 RL_CPLUSCMD_VLANSTRIP| 2017 (ifp->if_capenable & IFCAP_RXCSUM ? 2018 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2019 2020 /* 2021 * Init our MAC address. Even though the chipset 2022 * documentation doesn't mention it, we need to enter "Config 2023 * register write enable" mode to modify the ID registers. 2024 */ 2025 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2026 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2027 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2028 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2029 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2030 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2031 2032 /* 2033 * For C+ mode, initialize the RX descriptors and mbufs. 2034 */ 2035 re_rx_list_init(sc); 2036 re_tx_list_init(sc); 2037 2038 /* 2039 * Enable transmit and receive. 2040 */ 2041 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2042 2043 /* 2044 * Set the initial TX and RX configuration. 2045 */ 2046 if (sc->rl_testmode) { 2047 if (sc->rl_type == RL_8169) 2048 CSR_WRITE_4(sc, RL_TXCFG, 2049 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2050 else 2051 CSR_WRITE_4(sc, RL_TXCFG, 2052 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2053 } else 2054 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2055 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2056 2057 /* Set the individual bit to receive frames for this host only. */ 2058 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2059 rxcfg |= RL_RXCFG_RX_INDIV; 2060 2061 /* If we want promiscuous mode, set the allframes bit. */ 2062 if (ifp->if_flags & IFF_PROMISC) { 2063 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2064 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2065 } else { 2066 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2067 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2068 } 2069 2070 /* 2071 * Set capture broadcast bit to capture broadcast frames. 2072 */ 2073 if (ifp->if_flags & IFF_BROADCAST) { 2074 rxcfg |= RL_RXCFG_RX_BROAD; 2075 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2076 } else { 2077 rxcfg &= ~RL_RXCFG_RX_BROAD; 2078 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2079 } 2080 2081 /* 2082 * Program the multicast filter, if necessary. 2083 */ 2084 re_setmulti(sc); 2085 2086#ifdef DEVICE_POLLING 2087 /* 2088 * Disable interrupts if we are polling. 2089 */ 2090 if (ifp->if_flags & IFF_POLLING) 2091 CSR_WRITE_2(sc, RL_IMR, 0); 2092 else /* otherwise ... */ 2093#endif /* DEVICE_POLLING */ 2094 /* 2095 * Enable interrupts. 2096 */ 2097 if (sc->rl_testmode) 2098 CSR_WRITE_2(sc, RL_IMR, 0); 2099 else 2100 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2101 2102 /* Set initial TX threshold */ 2103 sc->rl_txthresh = RL_TX_THRESH_INIT; 2104 2105 /* Start RX/TX process. */ 2106 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2107#ifdef notdef 2108 /* Enable receiver and transmitter. */ 2109 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2110#endif 2111 /* 2112 * Load the addresses of the RX and TX lists into the chip. 2113 */ 2114 2115 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2116 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2117 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2118 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2119 2120 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2121 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2122 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2123 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2124 2125 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2126 2127 /* 2128 * Initialize the timer interrupt register so that 2129 * a timer interrupt will be generated once the timer 2130 * reaches a certain number of ticks. The timer is 2131 * reloaded on each transmit. This gives us TX interrupt 2132 * moderation, which dramatically improves TX frame rate. 2133 */ 2134 2135 if (sc->rl_type == RL_8169) 2136 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2137 else 2138 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2139 2140 /* 2141 * For 8169 gigE NICs, set the max allowed RX packet 2142 * size so we can receive jumbo frames. 2143 */ 2144 if (sc->rl_type == RL_8169) 2145 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2146 2147 if (sc->rl_testmode) { 2148 RL_UNLOCK(sc); 2149 return; 2150 } 2151 2152 mii_mediachg(mii); 2153 2154 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2155 2156 ifp->if_flags |= IFF_RUNNING; 2157 ifp->if_flags &= ~IFF_OACTIVE; 2158 2159 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2160 RL_UNLOCK(sc); 2161} 2162 2163/* 2164 * Set media options. 2165 */ 2166static int 2167re_ifmedia_upd(ifp) 2168 struct ifnet *ifp; 2169{ 2170 struct rl_softc *sc; 2171 struct mii_data *mii; 2172 2173 sc = ifp->if_softc; 2174 mii = device_get_softc(sc->rl_miibus); 2175 mii_mediachg(mii); 2176 2177 return (0); 2178} 2179 2180/* 2181 * Report current media status. 2182 */ 2183static void 2184re_ifmedia_sts(ifp, ifmr) 2185 struct ifnet *ifp; 2186 struct ifmediareq *ifmr; 2187{ 2188 struct rl_softc *sc; 2189 struct mii_data *mii; 2190 2191 sc = ifp->if_softc; 2192 mii = device_get_softc(sc->rl_miibus); 2193 2194 mii_pollstat(mii); 2195 ifmr->ifm_active = mii->mii_media_active; 2196 ifmr->ifm_status = mii->mii_media_status; 2197} 2198 2199static int 2200re_ioctl(ifp, command, data) 2201 struct ifnet *ifp; 2202 u_long command; 2203 caddr_t data; 2204{ 2205 struct rl_softc *sc = ifp->if_softc; 2206 struct ifreq *ifr = (struct ifreq *) data; 2207 struct mii_data *mii; 2208 int error = 0; 2209 2210 RL_LOCK(sc); 2211 2212 switch (command) { 2213 case SIOCSIFMTU: 2214 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2215 error = EINVAL; 2216 ifp->if_mtu = ifr->ifr_mtu; 2217 break; 2218 case SIOCSIFFLAGS: 2219 if (ifp->if_flags & IFF_UP) { 2220 re_init(sc); 2221 } else { 2222 if (ifp->if_flags & IFF_RUNNING) 2223 re_stop(sc); 2224 } 2225 error = 0; 2226 break; 2227 case SIOCADDMULTI: 2228 case SIOCDELMULTI: 2229 re_setmulti(sc); 2230 error = 0; 2231 break; 2232 case SIOCGIFMEDIA: 2233 case SIOCSIFMEDIA: 2234 mii = device_get_softc(sc->rl_miibus); 2235 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2236 break; 2237 case SIOCSIFCAP: 2238 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2239 ifp->if_capenable |= 2240 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2241 if (ifp->if_capenable & IFCAP_TXCSUM) 2242 ifp->if_hwassist = RE_CSUM_FEATURES; 2243 else 2244 ifp->if_hwassist = 0; 2245 if (ifp->if_flags & IFF_RUNNING) 2246 re_init(sc); 2247 break; 2248 default: 2249 error = ether_ioctl(ifp, command, data); 2250 break; 2251 } 2252 2253 RL_UNLOCK(sc); 2254 2255 return (error); 2256} 2257 2258static void 2259re_watchdog(ifp) 2260 struct ifnet *ifp; 2261{ 2262 struct rl_softc *sc; 2263 2264 sc = ifp->if_softc; 2265 RL_LOCK(sc); 2266 printf("re%d: watchdog timeout\n", sc->rl_unit); 2267 ifp->if_oerrors++; 2268 2269 re_txeof(sc); 2270 re_rxeof(sc); 2271 2272 re_init(sc); 2273 2274 RL_UNLOCK(sc); 2275} 2276 2277/* 2278 * Stop the adapter and free any mbufs allocated to the 2279 * RX and TX lists. 2280 */ 2281static void 2282re_stop(sc) 2283 struct rl_softc *sc; 2284{ 2285 register int i; 2286 struct ifnet *ifp; 2287 2288 RL_LOCK(sc); 2289 ifp = &sc->arpcom.ac_if; 2290 ifp->if_timer = 0; 2291 2292 untimeout(re_tick, sc, sc->rl_stat_ch); 2293 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2294#ifdef DEVICE_POLLING 2295 ether_poll_deregister(ifp); 2296#endif /* DEVICE_POLLING */ 2297 2298 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2299 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2300 2301 if (sc->rl_head != NULL) { 2302 m_freem(sc->rl_head); 2303 sc->rl_head = sc->rl_tail = NULL; 2304 } 2305 2306 /* Free the TX list buffers. */ 2307 2308 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2309 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2310 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2311 sc->rl_ldata.rl_tx_dmamap[i]); 2312 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2313 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2314 } 2315 } 2316 2317 /* Free the RX list buffers. */ 2318 2319 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2320 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2321 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2322 sc->rl_ldata.rl_rx_dmamap[i]); 2323 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2324 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2325 } 2326 } 2327 2328 RL_UNLOCK(sc); 2329} 2330 2331/* 2332 * Device suspend routine. Stop the interface and save some PCI 2333 * settings in case the BIOS doesn't restore them properly on 2334 * resume. 2335 */ 2336static int 2337re_suspend(dev) 2338 device_t dev; 2339{ 2340 struct rl_softc *sc; 2341 2342 sc = device_get_softc(dev); 2343 2344 re_stop(sc); 2345 sc->suspended = 1; 2346 2347 return (0); 2348} 2349 2350/* 2351 * Device resume routine. Restore some PCI settings in case the BIOS 2352 * doesn't, re-enable busmastering, and restart the interface if 2353 * appropriate. 2354 */ 2355static int 2356re_resume(dev) 2357 device_t dev; 2358{ 2359 struct rl_softc *sc; 2360 struct ifnet *ifp; 2361 2362 sc = device_get_softc(dev); 2363 ifp = &sc->arpcom.ac_if; 2364 2365 /* reinitialize interface if necessary */ 2366 if (ifp->if_flags & IFF_UP) 2367 re_init(sc); 2368 2369 sc->suspended = 0; 2370 2371 return (0); 2372} 2373 2374/* 2375 * Stop all chip I/O so that the kernel's probe routines don't 2376 * get confused by errant DMAs when rebooting. 2377 */ 2378static void 2379re_shutdown(dev) 2380 device_t dev; 2381{ 2382 struct rl_softc *sc; 2383 2384 sc = device_get_softc(dev); 2385 2386 re_stop(sc); 2387} 2388