if_re.c revision 130270
1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 130270 2004-06-09 14:34:04Z naddy $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7.5K, so the max MTU possible with this 108 * driver is 7500 bytes. 109 */ 110 111#include <sys/param.h> 112#include <sys/endian.h> 113#include <sys/systm.h> 114#include <sys/sockio.h> 115#include <sys/mbuf.h> 116#include <sys/malloc.h> 117#include <sys/module.h> 118#include <sys/kernel.h> 119#include <sys/socket.h> 120 121#include <net/if.h> 122#include <net/if_arp.h> 123#include <net/ethernet.h> 124#include <net/if_dl.h> 125#include <net/if_media.h> 126#include <net/if_vlan_var.h> 127 128#include <net/bpf.h> 129 130#include <machine/bus_pio.h> 131#include <machine/bus_memio.h> 132#include <machine/bus.h> 133#include <machine/resource.h> 134#include <sys/bus.h> 135#include <sys/rman.h> 136 137#include <dev/mii/mii.h> 138#include <dev/mii/miivar.h> 139 140#include <dev/pci/pcireg.h> 141#include <dev/pci/pcivar.h> 142 143MODULE_DEPEND(re, pci, 1, 1, 1); 144MODULE_DEPEND(re, ether, 1, 1, 1); 145MODULE_DEPEND(re, miibus, 1, 1, 1); 146 147/* "controller miibus0" required. See GENERIC if you get errors here. */ 148#include "miibus_if.h" 149 150/* 151 * Default to using PIO access for this driver. 152 */ 153#define RE_USEIOSPACE 154 155#include <pci/if_rlreg.h> 156 157#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 159/* 160 * Various supported device vendors/types and their names. 161 */ 162static struct rl_type re_devs[] = { 163 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 164 "RealTek 8139C+ 10/100BaseTX" }, 165 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 166 "RealTek 8169 Gigabit Ethernet" }, 167 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 168 "RealTek 8169S Single-chip Gigabit Ethernet" }, 169 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 170 "RealTek 8110S Single-chip Gigabit Ethernet" }, 171 { 0, 0, 0, NULL } 172}; 173 174static struct rl_hwrev re_hwrevs[] = { 175 { RL_HWREV_8139, RL_8139, "" }, 176 { RL_HWREV_8139A, RL_8139, "A" }, 177 { RL_HWREV_8139AG, RL_8139, "A-G" }, 178 { RL_HWREV_8139B, RL_8139, "B" }, 179 { RL_HWREV_8130, RL_8139, "8130" }, 180 { RL_HWREV_8139C, RL_8139, "C" }, 181 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 182 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 183 { RL_HWREV_8169, RL_8169, "8169"}, 184 { RL_HWREV_8169S, RL_8169, "8169S"}, 185 { RL_HWREV_8110S, RL_8169, "8110S"}, 186 { RL_HWREV_8100, RL_8139, "8100"}, 187 { RL_HWREV_8101, RL_8139, "8101"}, 188 { 0, 0, NULL } 189}; 190 191static int re_probe (device_t); 192static int re_attach (device_t); 193static int re_detach (device_t); 194 195static int re_encap (struct rl_softc *, struct mbuf *, int *); 196 197static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 198static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 199 bus_size_t, int); 200static int re_allocmem (device_t, struct rl_softc *); 201static int re_newbuf (struct rl_softc *, int, struct mbuf *); 202static int re_rx_list_init (struct rl_softc *); 203static int re_tx_list_init (struct rl_softc *); 204static void re_rxeof (struct rl_softc *); 205static void re_txeof (struct rl_softc *); 206static void re_intr (void *); 207static void re_tick (void *); 208static void re_start (struct ifnet *); 209static int re_ioctl (struct ifnet *, u_long, caddr_t); 210static void re_init (void *); 211static void re_stop (struct rl_softc *); 212static void re_watchdog (struct ifnet *); 213static int re_suspend (device_t); 214static int re_resume (device_t); 215static void re_shutdown (device_t); 216static int re_ifmedia_upd (struct ifnet *); 217static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 218 219static void re_eeprom_putbyte (struct rl_softc *, int); 220static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 221static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 222static int re_gmii_readreg (device_t, int, int); 223static int re_gmii_writereg (device_t, int, int, int); 224 225static int re_miibus_readreg (device_t, int, int); 226static int re_miibus_writereg (device_t, int, int, int); 227static void re_miibus_statchg (device_t); 228 229static void re_setmulti (struct rl_softc *); 230static void re_reset (struct rl_softc *); 231 232static int re_diag (struct rl_softc *); 233 234#ifdef RE_USEIOSPACE 235#define RL_RES SYS_RES_IOPORT 236#define RL_RID RL_PCI_LOIO 237#else 238#define RL_RES SYS_RES_MEMORY 239#define RL_RID RL_PCI_LOMEM 240#endif 241 242static device_method_t re_methods[] = { 243 /* Device interface */ 244 DEVMETHOD(device_probe, re_probe), 245 DEVMETHOD(device_attach, re_attach), 246 DEVMETHOD(device_detach, re_detach), 247 DEVMETHOD(device_suspend, re_suspend), 248 DEVMETHOD(device_resume, re_resume), 249 DEVMETHOD(device_shutdown, re_shutdown), 250 251 /* bus interface */ 252 DEVMETHOD(bus_print_child, bus_generic_print_child), 253 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 254 255 /* MII interface */ 256 DEVMETHOD(miibus_readreg, re_miibus_readreg), 257 DEVMETHOD(miibus_writereg, re_miibus_writereg), 258 DEVMETHOD(miibus_statchg, re_miibus_statchg), 259 260 { 0, 0 } 261}; 262 263static driver_t re_driver = { 264 "re", 265 re_methods, 266 sizeof(struct rl_softc) 267}; 268 269static devclass_t re_devclass; 270 271DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 272DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 273DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 274 275#define EE_SET(x) \ 276 CSR_WRITE_1(sc, RL_EECMD, \ 277 CSR_READ_1(sc, RL_EECMD) | x) 278 279#define EE_CLR(x) \ 280 CSR_WRITE_1(sc, RL_EECMD, \ 281 CSR_READ_1(sc, RL_EECMD) & ~x) 282 283/* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286static void 287re_eeprom_putbyte(sc, addr) 288 struct rl_softc *sc; 289 int addr; 290{ 291 register int d, i; 292 293 d = addr | sc->rl_eecmd_read; 294 295 /* 296 * Feed in each bit and strobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 EE_SET(RL_EE_DATAIN); 301 } else { 302 EE_CLR(RL_EE_DATAIN); 303 } 304 DELAY(100); 305 EE_SET(RL_EE_CLK); 306 DELAY(150); 307 EE_CLR(RL_EE_CLK); 308 DELAY(100); 309 } 310 311 return; 312} 313 314/* 315 * Read a word of data stored in the EEPROM at address 'addr.' 316 */ 317static void 318re_eeprom_getword(sc, addr, dest) 319 struct rl_softc *sc; 320 int addr; 321 u_int16_t *dest; 322{ 323 register int i; 324 u_int16_t word = 0; 325 326 /* Enter EEPROM access mode. */ 327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 328 329 /* 330 * Send address of word we want to read. 331 */ 332 re_eeprom_putbyte(sc, addr); 333 334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 335 336 /* 337 * Start reading bits from EEPROM. 338 */ 339 for (i = 0x8000; i; i >>= 1) { 340 EE_SET(RL_EE_CLK); 341 DELAY(100); 342 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 343 word |= i; 344 EE_CLR(RL_EE_CLK); 345 DELAY(100); 346 } 347 348 /* Turn off EEPROM access mode. */ 349 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 350 351 *dest = word; 352 353 return; 354} 355 356/* 357 * Read a sequence of words from the EEPROM. 358 */ 359static void 360re_read_eeprom(sc, dest, off, cnt, swap) 361 struct rl_softc *sc; 362 caddr_t dest; 363 int off; 364 int cnt; 365 int swap; 366{ 367 int i; 368 u_int16_t word = 0, *ptr; 369 370 for (i = 0; i < cnt; i++) { 371 re_eeprom_getword(sc, off + i, &word); 372 ptr = (u_int16_t *)(dest + (i * 2)); 373 if (swap) 374 *ptr = ntohs(word); 375 else 376 *ptr = word; 377 } 378 379 return; 380} 381 382static int 383re_gmii_readreg(dev, phy, reg) 384 device_t dev; 385 int phy, reg; 386{ 387 struct rl_softc *sc; 388 u_int32_t rval; 389 int i; 390 391 if (phy != 1) 392 return(0); 393 394 sc = device_get_softc(dev); 395 396 /* Let the rgephy driver read the GMEDIASTAT register */ 397 398 if (reg == RL_GMEDIASTAT) { 399 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 400 return(rval); 401 } 402 403 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 404 DELAY(1000); 405 406 for (i = 0; i < RL_TIMEOUT; i++) { 407 rval = CSR_READ_4(sc, RL_PHYAR); 408 if (rval & RL_PHYAR_BUSY) 409 break; 410 DELAY(100); 411 } 412 413 if (i == RL_TIMEOUT) { 414 printf ("re%d: PHY read failed\n", sc->rl_unit); 415 return (0); 416 } 417 418 return (rval & RL_PHYAR_PHYDATA); 419} 420 421static int 422re_gmii_writereg(dev, phy, reg, data) 423 device_t dev; 424 int phy, reg, data; 425{ 426 struct rl_softc *sc; 427 u_int32_t rval; 428 int i; 429 430 sc = device_get_softc(dev); 431 432 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 433 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 434 DELAY(1000); 435 436 for (i = 0; i < RL_TIMEOUT; i++) { 437 rval = CSR_READ_4(sc, RL_PHYAR); 438 if (!(rval & RL_PHYAR_BUSY)) 439 break; 440 DELAY(100); 441 } 442 443 if (i == RL_TIMEOUT) { 444 printf ("re%d: PHY write failed\n", sc->rl_unit); 445 return (0); 446 } 447 448 return (0); 449} 450 451static int 452re_miibus_readreg(dev, phy, reg) 453 device_t dev; 454 int phy, reg; 455{ 456 struct rl_softc *sc; 457 u_int16_t rval = 0; 458 u_int16_t re8139_reg = 0; 459 460 sc = device_get_softc(dev); 461 RL_LOCK(sc); 462 463 if (sc->rl_type == RL_8169) { 464 rval = re_gmii_readreg(dev, phy, reg); 465 RL_UNLOCK(sc); 466 return (rval); 467 } 468 469 /* Pretend the internal PHY is only at address 0 */ 470 if (phy) { 471 RL_UNLOCK(sc); 472 return(0); 473 } 474 switch(reg) { 475 case MII_BMCR: 476 re8139_reg = RL_BMCR; 477 break; 478 case MII_BMSR: 479 re8139_reg = RL_BMSR; 480 break; 481 case MII_ANAR: 482 re8139_reg = RL_ANAR; 483 break; 484 case MII_ANER: 485 re8139_reg = RL_ANER; 486 break; 487 case MII_ANLPAR: 488 re8139_reg = RL_LPAR; 489 break; 490 case MII_PHYIDR1: 491 case MII_PHYIDR2: 492 RL_UNLOCK(sc); 493 return(0); 494 /* 495 * Allow the rlphy driver to read the media status 496 * register. If we have a link partner which does not 497 * support NWAY, this is the register which will tell 498 * us the results of parallel detection. 499 */ 500 case RL_MEDIASTAT: 501 rval = CSR_READ_1(sc, RL_MEDIASTAT); 502 RL_UNLOCK(sc); 503 return(rval); 504 default: 505 printf("re%d: bad phy register\n", sc->rl_unit); 506 RL_UNLOCK(sc); 507 return(0); 508 } 509 rval = CSR_READ_2(sc, re8139_reg); 510 RL_UNLOCK(sc); 511 return(rval); 512} 513 514static int 515re_miibus_writereg(dev, phy, reg, data) 516 device_t dev; 517 int phy, reg, data; 518{ 519 struct rl_softc *sc; 520 u_int16_t re8139_reg = 0; 521 int rval = 0; 522 523 sc = device_get_softc(dev); 524 RL_LOCK(sc); 525 526 if (sc->rl_type == RL_8169) { 527 rval = re_gmii_writereg(dev, phy, reg, data); 528 RL_UNLOCK(sc); 529 return (rval); 530 } 531 532 /* Pretend the internal PHY is only at address 0 */ 533 if (phy) { 534 RL_UNLOCK(sc); 535 return(0); 536 } 537 switch(reg) { 538 case MII_BMCR: 539 re8139_reg = RL_BMCR; 540 break; 541 case MII_BMSR: 542 re8139_reg = RL_BMSR; 543 break; 544 case MII_ANAR: 545 re8139_reg = RL_ANAR; 546 break; 547 case MII_ANER: 548 re8139_reg = RL_ANER; 549 break; 550 case MII_ANLPAR: 551 re8139_reg = RL_LPAR; 552 break; 553 case MII_PHYIDR1: 554 case MII_PHYIDR2: 555 RL_UNLOCK(sc); 556 return(0); 557 break; 558 default: 559 printf("re%d: bad phy register\n", sc->rl_unit); 560 RL_UNLOCK(sc); 561 return(0); 562 } 563 CSR_WRITE_2(sc, re8139_reg, data); 564 RL_UNLOCK(sc); 565 return(0); 566} 567 568static void 569re_miibus_statchg(dev) 570 device_t dev; 571{ 572 return; 573} 574 575/* 576 * Program the 64-bit multicast hash filter. 577 */ 578static void 579re_setmulti(sc) 580 struct rl_softc *sc; 581{ 582 struct ifnet *ifp; 583 int h = 0; 584 u_int32_t hashes[2] = { 0, 0 }; 585 struct ifmultiaddr *ifma; 586 u_int32_t rxfilt; 587 int mcnt = 0; 588 589 ifp = &sc->arpcom.ac_if; 590 591 rxfilt = CSR_READ_4(sc, RL_RXCFG); 592 593 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 594 rxfilt |= RL_RXCFG_RX_MULTI; 595 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 596 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 597 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 598 return; 599 } 600 601 /* first, zot all the existing hash bits */ 602 CSR_WRITE_4(sc, RL_MAR0, 0); 603 CSR_WRITE_4(sc, RL_MAR4, 0); 604 605 /* now program new ones */ 606 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 607 if (ifma->ifma_addr->sa_family != AF_LINK) 608 continue; 609 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 610 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 611 if (h < 32) 612 hashes[0] |= (1 << h); 613 else 614 hashes[1] |= (1 << (h - 32)); 615 mcnt++; 616 } 617 618 if (mcnt) 619 rxfilt |= RL_RXCFG_RX_MULTI; 620 else 621 rxfilt &= ~RL_RXCFG_RX_MULTI; 622 623 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 624 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 625 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 626 627 return; 628} 629 630static void 631re_reset(sc) 632 struct rl_softc *sc; 633{ 634 register int i; 635 636 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 637 638 for (i = 0; i < RL_TIMEOUT; i++) { 639 DELAY(10); 640 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 641 break; 642 } 643 if (i == RL_TIMEOUT) 644 printf("re%d: reset never completed!\n", sc->rl_unit); 645 646 CSR_WRITE_1(sc, 0x82, 1); 647 648 return; 649} 650 651/* 652 * The following routine is designed to test for a defect on some 653 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 654 * lines connected to the bus, however for a 32-bit only card, they 655 * should be pulled high. The result of this defect is that the 656 * NIC will not work right if you plug it into a 64-bit slot: DMA 657 * operations will be done with 64-bit transfers, which will fail 658 * because the 64-bit data lines aren't connected. 659 * 660 * There's no way to work around this (short of talking a soldering 661 * iron to the board), however we can detect it. The method we use 662 * here is to put the NIC into digital loopback mode, set the receiver 663 * to promiscuous mode, and then try to send a frame. We then compare 664 * the frame data we sent to what was received. If the data matches, 665 * then the NIC is working correctly, otherwise we know the user has 666 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 667 * slot. In the latter case, there's no way the NIC can work correctly, 668 * so we print out a message on the console and abort the device attach. 669 */ 670 671static int 672re_diag(sc) 673 struct rl_softc *sc; 674{ 675 struct ifnet *ifp = &sc->arpcom.ac_if; 676 struct mbuf *m0; 677 struct ether_header *eh; 678 struct rl_desc *cur_rx; 679 u_int16_t status; 680 u_int32_t rxstat; 681 int total_len, i, error = 0; 682 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 683 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 684 685 /* Allocate a single mbuf */ 686 687 MGETHDR(m0, M_DONTWAIT, MT_DATA); 688 if (m0 == NULL) 689 return(ENOBUFS); 690 691 /* 692 * Initialize the NIC in test mode. This sets the chip up 693 * so that it can send and receive frames, but performs the 694 * following special functions: 695 * - Puts receiver in promiscuous mode 696 * - Enables digital loopback mode 697 * - Leaves interrupts turned off 698 */ 699 700 ifp->if_flags |= IFF_PROMISC; 701 sc->rl_testmode = 1; 702 re_init(sc); 703 re_stop(sc); 704 DELAY(100000); 705 re_init(sc); 706 707 /* Put some data in the mbuf */ 708 709 eh = mtod(m0, struct ether_header *); 710 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 711 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 712 eh->ether_type = htons(ETHERTYPE_IP); 713 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 714 715 /* 716 * Queue the packet, start transmission. 717 * Note: IF_HANDOFF() ultimately calls re_start() for us. 718 */ 719 720 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 721 IF_HANDOFF(&ifp->if_snd, m0, ifp); 722 m0 = NULL; 723 724 /* Wait for it to propagate through the chip */ 725 726 DELAY(100000); 727 for (i = 0; i < RL_TIMEOUT; i++) { 728 status = CSR_READ_2(sc, RL_ISR); 729 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 730 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 731 break; 732 DELAY(10); 733 } 734 735 if (i == RL_TIMEOUT) { 736 printf("re%d: diagnostic failed, failed to receive packet " 737 "in loopback mode\n", sc->rl_unit); 738 error = EIO; 739 goto done; 740 } 741 742 /* 743 * The packet should have been dumped into the first 744 * entry in the RX DMA ring. Grab it from there. 745 */ 746 747 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 748 sc->rl_ldata.rl_rx_list_map, 749 BUS_DMASYNC_POSTREAD); 750 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 751 sc->rl_ldata.rl_rx_dmamap[0], 752 BUS_DMASYNC_POSTWRITE); 753 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 754 sc->rl_ldata.rl_rx_dmamap[0]); 755 756 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 757 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 758 eh = mtod(m0, struct ether_header *); 759 760 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 761 total_len = RL_RXBYTES(cur_rx); 762 rxstat = le32toh(cur_rx->rl_cmdstat); 763 764 if (total_len != ETHER_MIN_LEN) { 765 printf("re%d: diagnostic failed, received short packet\n", 766 sc->rl_unit); 767 error = EIO; 768 goto done; 769 } 770 771 /* Test that the received packet data matches what we sent. */ 772 773 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 774 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 775 ntohs(eh->ether_type) != ETHERTYPE_IP) { 776 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 777 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 778 dst, ":", src, ":", ETHERTYPE_IP); 779 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 780 eh->ether_dhost, ":", eh->ether_shost, ":", 781 ntohs(eh->ether_type)); 782 printf("re%d: You may have a defective 32-bit NIC plugged " 783 "into a 64-bit PCI slot.\n", sc->rl_unit); 784 printf("re%d: Please re-install the NIC in a 32-bit slot " 785 "for proper operation.\n", sc->rl_unit); 786 printf("re%d: Read the re(4) man page for more details.\n", 787 sc->rl_unit); 788 error = EIO; 789 } 790 791done: 792 /* Turn interface off, release resources */ 793 794 sc->rl_testmode = 0; 795 ifp->if_flags &= ~IFF_PROMISC; 796 re_stop(sc); 797 if (m0 != NULL) 798 m_freem(m0); 799 800 return (error); 801} 802 803/* 804 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 805 * IDs against our list and return a device name if we find a match. 806 */ 807static int 808re_probe(dev) 809 device_t dev; 810{ 811 struct rl_type *t; 812 struct rl_softc *sc; 813 int rid; 814 u_int32_t hwrev; 815 816 t = re_devs; 817 sc = device_get_softc(dev); 818 819 while(t->rl_name != NULL) { 820 if ((pci_get_vendor(dev) == t->rl_vid) && 821 (pci_get_device(dev) == t->rl_did)) { 822 823 /* 824 * Temporarily map the I/O space 825 * so we can read the chip ID register. 826 */ 827 rid = RL_RID; 828 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 829 RF_ACTIVE); 830 if (sc->rl_res == NULL) { 831 device_printf(dev, 832 "couldn't map ports/memory\n"); 833 return(ENXIO); 834 } 835 sc->rl_btag = rman_get_bustag(sc->rl_res); 836 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 837 mtx_init(&sc->rl_mtx, 838 device_get_nameunit(dev), 839 MTX_NETWORK_LOCK, MTX_DEF); 840 RL_LOCK(sc); 841 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 842 bus_release_resource(dev, RL_RES, 843 RL_RID, sc->rl_res); 844 RL_UNLOCK(sc); 845 mtx_destroy(&sc->rl_mtx); 846 if (t->rl_basetype == hwrev) { 847 device_set_desc(dev, t->rl_name); 848 return(0); 849 } 850 } 851 t++; 852 } 853 854 return(ENXIO); 855} 856 857/* 858 * This routine takes the segment list provided as the result of 859 * a bus_dma_map_load() operation and assigns the addresses/lengths 860 * to RealTek DMA descriptors. This can be called either by the RX 861 * code or the TX code. In the RX case, we'll probably wind up mapping 862 * at most one segment. For the TX case, there could be any number of 863 * segments since TX packets may span multiple mbufs. In either case, 864 * if the number of segments is larger than the rl_maxsegs limit 865 * specified by the caller, we abort the mapping operation. Sadly, 866 * whoever designed the buffer mapping API did not provide a way to 867 * return an error from here, so we have to fake it a bit. 868 */ 869 870static void 871re_dma_map_desc(arg, segs, nseg, mapsize, error) 872 void *arg; 873 bus_dma_segment_t *segs; 874 int nseg; 875 bus_size_t mapsize; 876 int error; 877{ 878 struct rl_dmaload_arg *ctx; 879 struct rl_desc *d = NULL; 880 int i = 0, idx; 881 882 if (error) 883 return; 884 885 ctx = arg; 886 887 /* Signal error to caller if there's too many segments */ 888 if (nseg > ctx->rl_maxsegs) { 889 ctx->rl_maxsegs = 0; 890 return; 891 } 892 893 /* 894 * Map the segment array into descriptors. Note that we set the 895 * start-of-frame and end-of-frame markers for either TX or RX, but 896 * they really only have meaning in the TX case. (In the RX case, 897 * it's the chip that tells us where packets begin and end.) 898 * We also keep track of the end of the ring and set the 899 * end-of-ring bits as needed, and we set the ownership bits 900 * in all except the very first descriptor. (The caller will 901 * set this descriptor later when it start transmission or 902 * reception.) 903 */ 904 idx = ctx->rl_idx; 905 while(1) { 906 u_int32_t cmdstat; 907 d = &ctx->rl_ring[idx]; 908 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 909 ctx->rl_maxsegs = 0; 910 return; 911 } 912 cmdstat = segs[i].ds_len; 913 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 914 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 915 if (i == 0) 916 cmdstat |= RL_TDESC_CMD_SOF; 917 else 918 cmdstat |= RL_TDESC_CMD_OWN; 919 if (idx == (RL_RX_DESC_CNT - 1)) 920 cmdstat |= RL_TDESC_CMD_EOR; 921 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 922 i++; 923 if (i == nseg) 924 break; 925 RL_DESC_INC(idx); 926 } 927 928 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 929 ctx->rl_maxsegs = nseg; 930 ctx->rl_idx = idx; 931 932 return; 933} 934 935/* 936 * Map a single buffer address. 937 */ 938 939static void 940re_dma_map_addr(arg, segs, nseg, error) 941 void *arg; 942 bus_dma_segment_t *segs; 943 int nseg; 944 int error; 945{ 946 u_int32_t *addr; 947 948 if (error) 949 return; 950 951 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 952 addr = arg; 953 *addr = segs->ds_addr; 954 955 return; 956} 957 958static int 959re_allocmem(dev, sc) 960 device_t dev; 961 struct rl_softc *sc; 962{ 963 int error; 964 int nseg; 965 int i; 966 967 /* 968 * Allocate map for RX mbufs. 969 */ 970 nseg = 32; 971 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 972 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 973 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 974 NULL, NULL, &sc->rl_ldata.rl_mtag); 975 if (error) { 976 device_printf(dev, "could not allocate dma tag\n"); 977 return (ENOMEM); 978 } 979 980 /* 981 * Allocate map for TX descriptor list. 982 */ 983 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 984 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 985 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 986 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 987 if (error) { 988 device_printf(dev, "could not allocate dma tag\n"); 989 return (ENOMEM); 990 } 991 992 /* Allocate DMA'able memory for the TX ring */ 993 994 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 995 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 996 &sc->rl_ldata.rl_tx_list_map); 997 if (error) 998 return (ENOMEM); 999 1000 /* Load the map for the TX ring. */ 1001 1002 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1003 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1004 RL_TX_LIST_SZ, re_dma_map_addr, 1005 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1006 1007 /* Create DMA maps for TX buffers */ 1008 1009 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1010 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1011 &sc->rl_ldata.rl_tx_dmamap[i]); 1012 if (error) { 1013 device_printf(dev, "can't create DMA map for TX\n"); 1014 return(ENOMEM); 1015 } 1016 } 1017 1018 /* 1019 * Allocate map for RX descriptor list. 1020 */ 1021 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1022 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1023 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1024 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1025 if (error) { 1026 device_printf(dev, "could not allocate dma tag\n"); 1027 return (ENOMEM); 1028 } 1029 1030 /* Allocate DMA'able memory for the RX ring */ 1031 1032 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1033 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1034 &sc->rl_ldata.rl_rx_list_map); 1035 if (error) 1036 return (ENOMEM); 1037 1038 /* Load the map for the RX ring. */ 1039 1040 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1041 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1042 RL_TX_LIST_SZ, re_dma_map_addr, 1043 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1044 1045 /* Create DMA maps for RX buffers */ 1046 1047 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1048 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1049 &sc->rl_ldata.rl_rx_dmamap[i]); 1050 if (error) { 1051 device_printf(dev, "can't create DMA map for RX\n"); 1052 return(ENOMEM); 1053 } 1054 } 1055 1056 return(0); 1057} 1058 1059/* 1060 * Attach the interface. Allocate softc structures, do ifmedia 1061 * setup and ethernet/BPF attach. 1062 */ 1063static int 1064re_attach(dev) 1065 device_t dev; 1066{ 1067 u_char eaddr[ETHER_ADDR_LEN]; 1068 u_int16_t as[3]; 1069 struct rl_softc *sc; 1070 struct ifnet *ifp; 1071 struct rl_hwrev *hw_rev; 1072 int hwrev; 1073 u_int16_t re_did = 0; 1074 int unit, error = 0, rid, i; 1075 1076 sc = device_get_softc(dev); 1077 unit = device_get_unit(dev); 1078 1079 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1080 MTX_DEF | MTX_RECURSE); 1081#ifndef BURN_BRIDGES 1082 /* 1083 * Handle power management nonsense. 1084 */ 1085 1086 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1087 u_int32_t iobase, membase, irq; 1088 1089 /* Save important PCI config data. */ 1090 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 1091 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 1092 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 1093 1094 /* Reset the power state. */ 1095 printf("re%d: chip is is in D%d power mode " 1096 "-- setting to D0\n", unit, 1097 pci_get_powerstate(dev)); 1098 1099 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1100 1101 /* Restore PCI config data. */ 1102 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 1103 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 1104 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 1105 } 1106#endif 1107 /* 1108 * Map control/status registers. 1109 */ 1110 pci_enable_busmaster(dev); 1111 1112 rid = RL_RID; 1113 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1114 RF_ACTIVE); 1115 1116 if (sc->rl_res == NULL) { 1117 printf ("re%d: couldn't map ports/memory\n", unit); 1118 error = ENXIO; 1119 goto fail; 1120 } 1121 1122 sc->rl_btag = rman_get_bustag(sc->rl_res); 1123 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1124 1125 /* Allocate interrupt */ 1126 rid = 0; 1127 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1128 RF_SHAREABLE | RF_ACTIVE); 1129 1130 if (sc->rl_irq == NULL) { 1131 printf("re%d: couldn't map interrupt\n", unit); 1132 error = ENXIO; 1133 goto fail; 1134 } 1135 1136 /* Reset the adapter. */ 1137 re_reset(sc); 1138 1139 hw_rev = re_hwrevs; 1140 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1141 while (hw_rev->rl_desc != NULL) { 1142 if (hw_rev->rl_rev == hwrev) { 1143 sc->rl_type = hw_rev->rl_type; 1144 break; 1145 } 1146 hw_rev++; 1147 } 1148 1149 if (sc->rl_type == RL_8169) { 1150 1151 /* Set RX length mask */ 1152 1153 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1154 1155 /* Force station address autoload from the EEPROM */ 1156 1157 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1158 for (i = 0; i < RL_TIMEOUT; i++) { 1159 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1160 break; 1161 DELAY(100); 1162 } 1163 if (i == RL_TIMEOUT) 1164 printf ("re%d: eeprom autoload timed out\n", unit); 1165 1166 for (i = 0; i < ETHER_ADDR_LEN; i++) 1167 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1168 } else { 1169 1170 /* Set RX length mask */ 1171 1172 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1173 1174 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1175 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1176 if (re_did != 0x8129) 1177 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1178 1179 /* 1180 * Get station address from the EEPROM. 1181 */ 1182 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1183 for (i = 0; i < 3; i++) { 1184 eaddr[(i * 2) + 0] = as[i] & 0xff; 1185 eaddr[(i * 2) + 1] = as[i] >> 8; 1186 } 1187 } 1188 1189 sc->rl_unit = unit; 1190 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1191 1192 /* 1193 * Allocate the parent bus DMA tag appropriate for PCI. 1194 */ 1195#define RL_NSEG_NEW 32 1196 error = bus_dma_tag_create(NULL, /* parent */ 1197 1, 0, /* alignment, boundary */ 1198 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1199 BUS_SPACE_MAXADDR, /* highaddr */ 1200 NULL, NULL, /* filter, filterarg */ 1201 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1202 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1203 BUS_DMA_ALLOCNOW, /* flags */ 1204 NULL, NULL, /* lockfunc, lockarg */ 1205 &sc->rl_parent_tag); 1206 if (error) 1207 goto fail; 1208 1209 error = re_allocmem(dev, sc); 1210 1211 if (error) 1212 goto fail; 1213 1214 /* Do MII setup */ 1215 if (mii_phy_probe(dev, &sc->rl_miibus, 1216 re_ifmedia_upd, re_ifmedia_sts)) { 1217 printf("re%d: MII without any phy!\n", sc->rl_unit); 1218 error = ENXIO; 1219 goto fail; 1220 } 1221 1222 ifp = &sc->arpcom.ac_if; 1223 ifp->if_softc = sc; 1224 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1225 ifp->if_mtu = ETHERMTU; 1226 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1227 ifp->if_ioctl = re_ioctl; 1228 ifp->if_capabilities = IFCAP_VLAN_MTU; 1229 ifp->if_start = re_start; 1230 ifp->if_hwassist = RE_CSUM_FEATURES; 1231 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1232#ifdef DEVICE_POLLING 1233 ifp->if_capabilities |= IFCAP_POLLING; 1234#endif 1235 ifp->if_watchdog = re_watchdog; 1236 ifp->if_init = re_init; 1237 if (sc->rl_type == RL_8169) 1238 ifp->if_baudrate = 1000000000; 1239 else 1240 ifp->if_baudrate = 100000000; 1241 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; 1242 ifp->if_capenable = ifp->if_capabilities; 1243 1244 callout_handle_init(&sc->rl_stat_ch); 1245 1246 /* 1247 * Call MI attach routine. 1248 */ 1249 ether_ifattach(ifp, eaddr); 1250 1251 /* Perform hardware diagnostic. */ 1252 error = re_diag(sc); 1253 1254 if (error) { 1255 printf("re%d: attach aborted due to hardware diag failure\n", 1256 unit); 1257 ether_ifdetach(ifp); 1258 goto fail; 1259 } 1260 1261 /* Hook interrupt last to avoid having to lock softc */ 1262 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1263 re_intr, sc, &sc->rl_intrhand); 1264 1265 if (error) { 1266 printf("re%d: couldn't set up irq\n", unit); 1267 ether_ifdetach(ifp); 1268 goto fail; 1269 } 1270 1271fail: 1272 if (error) 1273 re_detach(dev); 1274 1275 return (error); 1276} 1277 1278/* 1279 * Shutdown hardware and free up resources. This can be called any 1280 * time after the mutex has been initialized. It is called in both 1281 * the error case in attach and the normal detach case so it needs 1282 * to be careful about only freeing resources that have actually been 1283 * allocated. 1284 */ 1285static int 1286re_detach(dev) 1287 device_t dev; 1288{ 1289 struct rl_softc *sc; 1290 struct ifnet *ifp; 1291 int i; 1292 1293 sc = device_get_softc(dev); 1294 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1295 RL_LOCK(sc); 1296 ifp = &sc->arpcom.ac_if; 1297 1298 /* These should only be active if attach succeeded */ 1299 if (device_is_attached(dev)) { 1300 re_stop(sc); 1301 /* 1302 * Force off the IFF_UP flag here, in case someone 1303 * still had a BPF descriptor attached to this 1304 * interface. If they do, ether_ifattach() will cause 1305 * the BPF code to try and clear the promisc mode 1306 * flag, which will bubble down to re_ioctl(), 1307 * which will try to call re_init() again. This will 1308 * turn the NIC back on and restart the MII ticker, 1309 * which will panic the system when the kernel tries 1310 * to invoke the re_tick() function that isn't there 1311 * anymore. 1312 */ 1313 ifp->if_flags &= ~IFF_UP; 1314 ether_ifdetach(ifp); 1315 } 1316 if (sc->rl_miibus) 1317 device_delete_child(dev, sc->rl_miibus); 1318 bus_generic_detach(dev); 1319 1320 if (sc->rl_intrhand) 1321 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1322 if (sc->rl_irq) 1323 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1324 if (sc->rl_res) 1325 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1326 1327 1328 /* Unload and free the RX DMA ring memory and map */ 1329 1330 if (sc->rl_ldata.rl_rx_list_tag) { 1331 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1332 sc->rl_ldata.rl_rx_list_map); 1333 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1334 sc->rl_ldata.rl_rx_list, 1335 sc->rl_ldata.rl_rx_list_map); 1336 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1337 } 1338 1339 /* Unload and free the TX DMA ring memory and map */ 1340 1341 if (sc->rl_ldata.rl_tx_list_tag) { 1342 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1343 sc->rl_ldata.rl_tx_list_map); 1344 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1345 sc->rl_ldata.rl_tx_list, 1346 sc->rl_ldata.rl_tx_list_map); 1347 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1348 } 1349 1350 /* Destroy all the RX and TX buffer maps */ 1351 1352 if (sc->rl_ldata.rl_mtag) { 1353 for (i = 0; i < RL_TX_DESC_CNT; i++) 1354 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1355 sc->rl_ldata.rl_tx_dmamap[i]); 1356 for (i = 0; i < RL_RX_DESC_CNT; i++) 1357 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1358 sc->rl_ldata.rl_rx_dmamap[i]); 1359 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1360 } 1361 1362 /* Unload and free the stats buffer and map */ 1363 1364 if (sc->rl_ldata.rl_stag) { 1365 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1366 sc->rl_ldata.rl_rx_list_map); 1367 bus_dmamem_free(sc->rl_ldata.rl_stag, 1368 sc->rl_ldata.rl_stats, 1369 sc->rl_ldata.rl_smap); 1370 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1371 } 1372 1373 if (sc->rl_parent_tag) 1374 bus_dma_tag_destroy(sc->rl_parent_tag); 1375 1376 RL_UNLOCK(sc); 1377 mtx_destroy(&sc->rl_mtx); 1378 1379 return(0); 1380} 1381 1382static int 1383re_newbuf(sc, idx, m) 1384 struct rl_softc *sc; 1385 int idx; 1386 struct mbuf *m; 1387{ 1388 struct rl_dmaload_arg arg; 1389 struct mbuf *n = NULL; 1390 int error; 1391 1392 if (m == NULL) { 1393 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1394 if (n == NULL) 1395 return(ENOBUFS); 1396 m = n; 1397 } else 1398 m->m_data = m->m_ext.ext_buf; 1399 1400 /* 1401 * Initialize mbuf length fields and fixup 1402 * alignment so that the frame payload is 1403 * longword aligned. 1404 */ 1405 m->m_len = m->m_pkthdr.len = MCLBYTES; 1406 m_adj(m, ETHER_ALIGN); 1407 1408 arg.sc = sc; 1409 arg.rl_idx = idx; 1410 arg.rl_maxsegs = 1; 1411 arg.rl_flags = 0; 1412 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1413 1414 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1415 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1416 &arg, BUS_DMA_NOWAIT); 1417 if (error || arg.rl_maxsegs != 1) { 1418 if (n != NULL) 1419 m_freem(n); 1420 return (ENOMEM); 1421 } 1422 1423 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1424 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1425 1426 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1427 sc->rl_ldata.rl_rx_dmamap[idx], 1428 BUS_DMASYNC_PREREAD); 1429 1430 return(0); 1431} 1432 1433static int 1434re_tx_list_init(sc) 1435 struct rl_softc *sc; 1436{ 1437 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1438 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1439 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1440 1441 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1442 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1443 sc->rl_ldata.rl_tx_prodidx = 0; 1444 sc->rl_ldata.rl_tx_considx = 0; 1445 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1446 1447 return(0); 1448} 1449 1450static int 1451re_rx_list_init(sc) 1452 struct rl_softc *sc; 1453{ 1454 int i; 1455 1456 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1457 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1458 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1459 1460 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1461 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1462 return(ENOBUFS); 1463 } 1464 1465 /* Flush the RX descriptors */ 1466 1467 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1468 sc->rl_ldata.rl_rx_list_map, 1469 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1470 1471 sc->rl_ldata.rl_rx_prodidx = 0; 1472 sc->rl_head = sc->rl_tail = NULL; 1473 1474 return(0); 1475} 1476 1477/* 1478 * RX handler for C+ and 8169. For the gigE chips, we support 1479 * the reception of jumbo frames that have been fragmented 1480 * across multiple 2K mbuf cluster buffers. 1481 */ 1482static void 1483re_rxeof(sc) 1484 struct rl_softc *sc; 1485{ 1486 struct mbuf *m; 1487 struct ifnet *ifp; 1488 int i, total_len; 1489 struct rl_desc *cur_rx; 1490 u_int32_t rxstat, rxvlan; 1491 1492 RL_LOCK_ASSERT(sc); 1493 1494 ifp = &sc->arpcom.ac_if; 1495 i = sc->rl_ldata.rl_rx_prodidx; 1496 1497 /* Invalidate the descriptor memory */ 1498 1499 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1500 sc->rl_ldata.rl_rx_list_map, 1501 BUS_DMASYNC_POSTREAD); 1502 1503 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1504 1505 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1506 m = sc->rl_ldata.rl_rx_mbuf[i]; 1507 total_len = RL_RXBYTES(cur_rx); 1508 rxstat = le32toh(cur_rx->rl_cmdstat); 1509 rxvlan = le32toh(cur_rx->rl_vlanctl); 1510 1511 /* Invalidate the RX mbuf and unload its map */ 1512 1513 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1514 sc->rl_ldata.rl_rx_dmamap[i], 1515 BUS_DMASYNC_POSTWRITE); 1516 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1517 sc->rl_ldata.rl_rx_dmamap[i]); 1518 1519 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1520 m->m_len = MCLBYTES - ETHER_ALIGN; 1521 if (sc->rl_head == NULL) 1522 sc->rl_head = sc->rl_tail = m; 1523 else { 1524 m->m_flags &= ~M_PKTHDR; 1525 sc->rl_tail->m_next = m; 1526 sc->rl_tail = m; 1527 } 1528 re_newbuf(sc, i, NULL); 1529 RL_DESC_INC(i); 1530 continue; 1531 } 1532 1533 /* 1534 * NOTE: for the 8139C+, the frame length field 1535 * is always 12 bits in size, but for the gigE chips, 1536 * it is 13 bits (since the max RX frame length is 16K). 1537 * Unfortunately, all 32 bits in the status word 1538 * were already used, so to make room for the extra 1539 * length bit, RealTek took out the 'frame alignment 1540 * error' bit and shifted the other status bits 1541 * over one slot. The OWN, EOR, FS and LS bits are 1542 * still in the same places. We have already extracted 1543 * the frame length and checked the OWN bit, so rather 1544 * than using an alternate bit mapping, we shift the 1545 * status bits one space to the right so we can evaluate 1546 * them using the 8169 status as though it was in the 1547 * same format as that of the 8139C+. 1548 */ 1549 if (sc->rl_type == RL_8169) 1550 rxstat >>= 1; 1551 1552 if (rxstat & RL_RDESC_STAT_RXERRSUM) { 1553 ifp->if_ierrors++; 1554 /* 1555 * If this is part of a multi-fragment packet, 1556 * discard all the pieces. 1557 */ 1558 if (sc->rl_head != NULL) { 1559 m_freem(sc->rl_head); 1560 sc->rl_head = sc->rl_tail = NULL; 1561 } 1562 re_newbuf(sc, i, m); 1563 RL_DESC_INC(i); 1564 continue; 1565 } 1566 1567 /* 1568 * If allocating a replacement mbuf fails, 1569 * reload the current one. 1570 */ 1571 1572 if (re_newbuf(sc, i, NULL)) { 1573 ifp->if_ierrors++; 1574 if (sc->rl_head != NULL) { 1575 m_freem(sc->rl_head); 1576 sc->rl_head = sc->rl_tail = NULL; 1577 } 1578 re_newbuf(sc, i, m); 1579 RL_DESC_INC(i); 1580 continue; 1581 } 1582 1583 RL_DESC_INC(i); 1584 1585 if (sc->rl_head != NULL) { 1586 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1587 /* 1588 * Special case: if there's 4 bytes or less 1589 * in this buffer, the mbuf can be discarded: 1590 * the last 4 bytes is the CRC, which we don't 1591 * care about anyway. 1592 */ 1593 if (m->m_len <= ETHER_CRC_LEN) { 1594 sc->rl_tail->m_len -= 1595 (ETHER_CRC_LEN - m->m_len); 1596 m_freem(m); 1597 } else { 1598 m->m_len -= ETHER_CRC_LEN; 1599 m->m_flags &= ~M_PKTHDR; 1600 sc->rl_tail->m_next = m; 1601 } 1602 m = sc->rl_head; 1603 sc->rl_head = sc->rl_tail = NULL; 1604 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1605 } else 1606 m->m_pkthdr.len = m->m_len = 1607 (total_len - ETHER_CRC_LEN); 1608 1609 ifp->if_ipackets++; 1610 m->m_pkthdr.rcvif = ifp; 1611 1612 /* Do RX checksumming if enabled */ 1613 1614 if (ifp->if_capenable & IFCAP_RXCSUM) { 1615 1616 /* Check IP header checksum */ 1617 if (rxstat & RL_RDESC_STAT_PROTOID) 1618 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1619 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1620 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1621 1622 /* Check TCP/UDP checksum */ 1623 if ((RL_TCPPKT(rxstat) && 1624 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1625 (RL_UDPPKT(rxstat) && 1626 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1627 m->m_pkthdr.csum_flags |= 1628 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1629 m->m_pkthdr.csum_data = 0xffff; 1630 } 1631 } 1632 1633 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1634 VLAN_INPUT_TAG(ifp, m, 1635 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1636 RL_UNLOCK(sc); 1637 (*ifp->if_input)(ifp, m); 1638 RL_LOCK(sc); 1639 } 1640 1641 /* Flush the RX DMA ring */ 1642 1643 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1644 sc->rl_ldata.rl_rx_list_map, 1645 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1646 1647 sc->rl_ldata.rl_rx_prodidx = i; 1648 1649 return; 1650} 1651 1652static void 1653re_txeof(sc) 1654 struct rl_softc *sc; 1655{ 1656 struct ifnet *ifp; 1657 u_int32_t txstat; 1658 int idx; 1659 1660 ifp = &sc->arpcom.ac_if; 1661 idx = sc->rl_ldata.rl_tx_considx; 1662 1663 /* Invalidate the TX descriptor list */ 1664 1665 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1666 sc->rl_ldata.rl_tx_list_map, 1667 BUS_DMASYNC_POSTREAD); 1668 1669 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1670 1671 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1672 if (txstat & RL_TDESC_CMD_OWN) 1673 break; 1674 1675 /* 1676 * We only stash mbufs in the last descriptor 1677 * in a fragment chain, which also happens to 1678 * be the only place where the TX status bits 1679 * are valid. 1680 */ 1681 1682 if (txstat & RL_TDESC_CMD_EOF) { 1683 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1684 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1685 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1686 sc->rl_ldata.rl_tx_dmamap[idx]); 1687 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1688 RL_TDESC_STAT_COLCNT)) 1689 ifp->if_collisions++; 1690 if (txstat & RL_TDESC_STAT_TXERRSUM) 1691 ifp->if_oerrors++; 1692 else 1693 ifp->if_opackets++; 1694 } 1695 sc->rl_ldata.rl_tx_free++; 1696 RL_DESC_INC(idx); 1697 } 1698 1699 /* No changes made to the TX ring, so no flush needed */ 1700 1701 if (idx != sc->rl_ldata.rl_tx_considx) { 1702 sc->rl_ldata.rl_tx_considx = idx; 1703 ifp->if_flags &= ~IFF_OACTIVE; 1704 ifp->if_timer = 0; 1705 } 1706 1707 /* 1708 * If not all descriptors have been released reaped yet, 1709 * reload the timer so that we will eventually get another 1710 * interrupt that will cause us to re-enter this routine. 1711 * This is done in case the transmitter has gone idle. 1712 */ 1713 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1714 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1715 1716 return; 1717} 1718 1719static void 1720re_tick(xsc) 1721 void *xsc; 1722{ 1723 struct rl_softc *sc; 1724 struct mii_data *mii; 1725 1726 sc = xsc; 1727 RL_LOCK(sc); 1728 mii = device_get_softc(sc->rl_miibus); 1729 1730 mii_tick(mii); 1731 1732 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1733 RL_UNLOCK(sc); 1734 1735 return; 1736} 1737 1738#ifdef DEVICE_POLLING 1739static void 1740re_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1741{ 1742 struct rl_softc *sc = ifp->if_softc; 1743 1744 RL_LOCK(sc); 1745 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1746 ether_poll_deregister(ifp); 1747 cmd = POLL_DEREGISTER; 1748 } 1749 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1750 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1751 goto done; 1752 } 1753 1754 sc->rxcycles = count; 1755 re_rxeof(sc); 1756 re_txeof(sc); 1757 1758 if (ifp->if_snd.ifq_head != NULL) 1759 (*ifp->if_start)(ifp); 1760 1761 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1762 u_int16_t status; 1763 1764 status = CSR_READ_2(sc, RL_ISR); 1765 if (status == 0xffff) 1766 goto done; 1767 if (status) 1768 CSR_WRITE_2(sc, RL_ISR, status); 1769 1770 /* 1771 * XXX check behaviour on receiver stalls. 1772 */ 1773 1774 if (status & RL_ISR_SYSTEM_ERR) { 1775 re_reset(sc); 1776 re_init(sc); 1777 } 1778 } 1779done: 1780 RL_UNLOCK(sc); 1781} 1782#endif /* DEVICE_POLLING */ 1783 1784static void 1785re_intr(arg) 1786 void *arg; 1787{ 1788 struct rl_softc *sc; 1789 struct ifnet *ifp; 1790 u_int16_t status; 1791 1792 sc = arg; 1793 1794 if (sc->suspended) { 1795 return; 1796 } 1797 1798 RL_LOCK(sc); 1799 ifp = &sc->arpcom.ac_if; 1800 1801 if (!(ifp->if_flags & IFF_UP)) { 1802 RL_UNLOCK(sc); 1803 return; 1804 } 1805 1806#ifdef DEVICE_POLLING 1807 if (ifp->if_flags & IFF_POLLING) 1808 goto done; 1809 if ((ifp->if_capenable & IFCAP_POLLING) && 1810 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1811 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1812 re_poll(ifp, 0, 1); 1813 goto done; 1814 } 1815#endif /* DEVICE_POLLING */ 1816 1817 for (;;) { 1818 1819 status = CSR_READ_2(sc, RL_ISR); 1820 /* If the card has gone away the read returns 0xffff. */ 1821 if (status == 0xffff) 1822 break; 1823 if (status) 1824 CSR_WRITE_2(sc, RL_ISR, status); 1825 1826 if ((status & RL_INTRS_CPLUS) == 0) 1827 break; 1828 1829 if (status & RL_ISR_RX_OK) 1830 re_rxeof(sc); 1831 1832 if (status & RL_ISR_RX_ERR) 1833 re_rxeof(sc); 1834 1835 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1836 (status & RL_ISR_TX_ERR) || 1837 (status & RL_ISR_TX_DESC_UNAVAIL)) 1838 re_txeof(sc); 1839 1840 if (status & RL_ISR_SYSTEM_ERR) { 1841 re_reset(sc); 1842 re_init(sc); 1843 } 1844 1845 if (status & RL_ISR_LINKCHG) { 1846 untimeout(re_tick, sc, sc->rl_stat_ch); 1847 re_tick(sc); 1848 } 1849 } 1850 1851 if (ifp->if_snd.ifq_head != NULL) 1852 (*ifp->if_start)(ifp); 1853 1854#ifdef DEVICE_POLLING 1855done: 1856#endif 1857 RL_UNLOCK(sc); 1858 1859 return; 1860} 1861 1862static int 1863re_encap(sc, m_head, idx) 1864 struct rl_softc *sc; 1865 struct mbuf *m_head; 1866 int *idx; 1867{ 1868 struct mbuf *m_new = NULL; 1869 struct rl_dmaload_arg arg; 1870 bus_dmamap_t map; 1871 int error; 1872 struct m_tag *mtag; 1873 1874 if (sc->rl_ldata.rl_tx_free <= 4) 1875 return(EFBIG); 1876 1877 /* 1878 * Set up checksum offload. Note: checksum offload bits must 1879 * appear in all descriptors of a multi-descriptor transmit 1880 * attempt. (This is according to testing done with an 8169 1881 * chip. I'm not sure if this is a requirement or a bug.) 1882 */ 1883 1884 arg.rl_flags = 0; 1885 1886 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1887 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1888 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1889 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1890 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1891 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1892 1893 arg.sc = sc; 1894 arg.rl_idx = *idx; 1895 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1896 if (arg.rl_maxsegs > 4) 1897 arg.rl_maxsegs -= 4; 1898 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1899 1900 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1901 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1902 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1903 1904 if (error && error != EFBIG) { 1905 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1906 return(ENOBUFS); 1907 } 1908 1909 /* Too many segments to map, coalesce into a single mbuf */ 1910 1911 if (error || arg.rl_maxsegs == 0) { 1912 m_new = m_defrag(m_head, M_DONTWAIT); 1913 if (m_new == NULL) 1914 return(1); 1915 else 1916 m_head = m_new; 1917 1918 arg.sc = sc; 1919 arg.rl_idx = *idx; 1920 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1921 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1922 1923 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1924 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1925 if (error) { 1926 printf("re%d: can't map mbuf (error %d)\n", 1927 sc->rl_unit, error); 1928 return(EFBIG); 1929 } 1930 } 1931 1932 /* 1933 * Insure that the map for this transmission 1934 * is placed at the array index of the last descriptor 1935 * in this chain. 1936 */ 1937 sc->rl_ldata.rl_tx_dmamap[*idx] = 1938 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1939 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1940 1941 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head; 1942 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1943 1944 /* 1945 * Set up hardware VLAN tagging. Note: vlan tag info must 1946 * appear in the first descriptor of a multi-descriptor 1947 * transmission attempt. 1948 */ 1949 1950 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1951 if (mtag != NULL) 1952 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1953 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1954 1955 /* Transfer ownership of packet to the chip. */ 1956 1957 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1958 htole32(RL_TDESC_CMD_OWN); 1959 if (*idx != arg.rl_idx) 1960 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1961 htole32(RL_TDESC_CMD_OWN); 1962 1963 RL_DESC_INC(arg.rl_idx); 1964 *idx = arg.rl_idx; 1965 1966 return(0); 1967} 1968 1969/* 1970 * Main transmit routine for C+ and gigE NICs. 1971 */ 1972 1973static void 1974re_start(ifp) 1975 struct ifnet *ifp; 1976{ 1977 struct rl_softc *sc; 1978 struct mbuf *m_head = NULL; 1979 int idx; 1980 1981 sc = ifp->if_softc; 1982 RL_LOCK(sc); 1983 1984 idx = sc->rl_ldata.rl_tx_prodidx; 1985 1986 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 1987 IF_DEQUEUE(&ifp->if_snd, m_head); 1988 if (m_head == NULL) 1989 break; 1990 1991 if (re_encap(sc, m_head, &idx)) { 1992 IF_PREPEND(&ifp->if_snd, m_head); 1993 ifp->if_flags |= IFF_OACTIVE; 1994 break; 1995 } 1996 1997 /* 1998 * If there's a BPF listener, bounce a copy of this frame 1999 * to him. 2000 */ 2001 BPF_MTAP(ifp, m_head); 2002 } 2003 2004 /* Flush the TX descriptors */ 2005 2006 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2007 sc->rl_ldata.rl_tx_list_map, 2008 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2009 2010 sc->rl_ldata.rl_tx_prodidx = idx; 2011 2012 /* 2013 * RealTek put the TX poll request register in a different 2014 * location on the 8169 gigE chip. I don't know why. 2015 */ 2016 2017 if (sc->rl_type == RL_8169) 2018 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2019 else 2020 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2021 2022 /* 2023 * Use the countdown timer for interrupt moderation. 2024 * 'TX done' interrupts are disabled. Instead, we reset the 2025 * countdown timer, which will begin counting until it hits 2026 * the value in the TIMERINT register, and then trigger an 2027 * interrupt. Each time we write to the TIMERCNT register, 2028 * the timer count is reset to 0. 2029 */ 2030 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2031 2032 RL_UNLOCK(sc); 2033 2034 /* 2035 * Set a timeout in case the chip goes out to lunch. 2036 */ 2037 ifp->if_timer = 5; 2038 2039 return; 2040} 2041 2042static void 2043re_init(xsc) 2044 void *xsc; 2045{ 2046 struct rl_softc *sc = xsc; 2047 struct ifnet *ifp = &sc->arpcom.ac_if; 2048 struct mii_data *mii; 2049 u_int32_t rxcfg = 0; 2050 2051 RL_LOCK(sc); 2052 mii = device_get_softc(sc->rl_miibus); 2053 2054 /* 2055 * Cancel pending I/O and free all RX/TX buffers. 2056 */ 2057 re_stop(sc); 2058 2059 /* 2060 * Enable C+ RX and TX mode, as well as VLAN stripping and 2061 * RX checksum offload. We must configure the C+ register 2062 * before all others. 2063 */ 2064 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2065 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2066 RL_CPLUSCMD_VLANSTRIP| 2067 (ifp->if_capenable & IFCAP_RXCSUM ? 2068 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2069 2070 /* 2071 * Init our MAC address. Even though the chipset 2072 * documentation doesn't mention it, we need to enter "Config 2073 * register write enable" mode to modify the ID registers. 2074 */ 2075 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2076 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2077 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2078 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2079 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2080 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2081 2082 /* 2083 * For C+ mode, initialize the RX descriptors and mbufs. 2084 */ 2085 re_rx_list_init(sc); 2086 re_tx_list_init(sc); 2087 2088 /* 2089 * Enable transmit and receive. 2090 */ 2091 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2092 2093 /* 2094 * Set the initial TX and RX configuration. 2095 */ 2096 if (sc->rl_testmode) { 2097 if (sc->rl_type == RL_8169) 2098 CSR_WRITE_4(sc, RL_TXCFG, 2099 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2100 else 2101 CSR_WRITE_4(sc, RL_TXCFG, 2102 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2103 } else 2104 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2105 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2106 2107 /* Set the individual bit to receive frames for this host only. */ 2108 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2109 rxcfg |= RL_RXCFG_RX_INDIV; 2110 2111 /* If we want promiscuous mode, set the allframes bit. */ 2112 if (ifp->if_flags & IFF_PROMISC) { 2113 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2114 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2115 } else { 2116 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2117 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2118 } 2119 2120 /* 2121 * Set capture broadcast bit to capture broadcast frames. 2122 */ 2123 if (ifp->if_flags & IFF_BROADCAST) { 2124 rxcfg |= RL_RXCFG_RX_BROAD; 2125 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2126 } else { 2127 rxcfg &= ~RL_RXCFG_RX_BROAD; 2128 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2129 } 2130 2131 /* 2132 * Program the multicast filter, if necessary. 2133 */ 2134 re_setmulti(sc); 2135 2136#ifdef DEVICE_POLLING 2137 /* 2138 * Disable interrupts if we are polling. 2139 */ 2140 if (ifp->if_flags & IFF_POLLING) 2141 CSR_WRITE_2(sc, RL_IMR, 0); 2142 else /* otherwise ... */ 2143#endif /* DEVICE_POLLING */ 2144 /* 2145 * Enable interrupts. 2146 */ 2147 if (sc->rl_testmode) 2148 CSR_WRITE_2(sc, RL_IMR, 0); 2149 else 2150 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2151 2152 /* Set initial TX threshold */ 2153 sc->rl_txthresh = RL_TX_THRESH_INIT; 2154 2155 /* Start RX/TX process. */ 2156 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2157#ifdef notdef 2158 /* Enable receiver and transmitter. */ 2159 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2160#endif 2161 /* 2162 * Load the addresses of the RX and TX lists into the chip. 2163 */ 2164 2165 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2166 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2167 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2168 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2169 2170 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2171 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2172 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2173 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2174 2175 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2176 2177 /* 2178 * Initialize the timer interrupt register so that 2179 * a timer interrupt will be generated once the timer 2180 * reaches a certain number of ticks. The timer is 2181 * reloaded on each transmit. This gives us TX interrupt 2182 * moderation, which dramatically improves TX frame rate. 2183 */ 2184 2185 if (sc->rl_type == RL_8169) 2186 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2187 else 2188 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2189 2190 /* 2191 * For 8169 gigE NICs, set the max allowed RX packet 2192 * size so we can receive jumbo frames. 2193 */ 2194 if (sc->rl_type == RL_8169) 2195 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2196 2197 if (sc->rl_testmode) { 2198 RL_UNLOCK(sc); 2199 return; 2200 } 2201 2202 mii_mediachg(mii); 2203 2204 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2205 2206 ifp->if_flags |= IFF_RUNNING; 2207 ifp->if_flags &= ~IFF_OACTIVE; 2208 2209 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2210 RL_UNLOCK(sc); 2211 2212 return; 2213} 2214 2215/* 2216 * Set media options. 2217 */ 2218static int 2219re_ifmedia_upd(ifp) 2220 struct ifnet *ifp; 2221{ 2222 struct rl_softc *sc; 2223 struct mii_data *mii; 2224 2225 sc = ifp->if_softc; 2226 mii = device_get_softc(sc->rl_miibus); 2227 mii_mediachg(mii); 2228 2229 return(0); 2230} 2231 2232/* 2233 * Report current media status. 2234 */ 2235static void 2236re_ifmedia_sts(ifp, ifmr) 2237 struct ifnet *ifp; 2238 struct ifmediareq *ifmr; 2239{ 2240 struct rl_softc *sc; 2241 struct mii_data *mii; 2242 2243 sc = ifp->if_softc; 2244 mii = device_get_softc(sc->rl_miibus); 2245 2246 mii_pollstat(mii); 2247 ifmr->ifm_active = mii->mii_media_active; 2248 ifmr->ifm_status = mii->mii_media_status; 2249 2250 return; 2251} 2252 2253static int 2254re_ioctl(ifp, command, data) 2255 struct ifnet *ifp; 2256 u_long command; 2257 caddr_t data; 2258{ 2259 struct rl_softc *sc = ifp->if_softc; 2260 struct ifreq *ifr = (struct ifreq *) data; 2261 struct mii_data *mii; 2262 int error = 0; 2263 2264 RL_LOCK(sc); 2265 2266 switch(command) { 2267 case SIOCSIFMTU: 2268 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2269 error = EINVAL; 2270 ifp->if_mtu = ifr->ifr_mtu; 2271 break; 2272 case SIOCSIFFLAGS: 2273 if (ifp->if_flags & IFF_UP) { 2274 re_init(sc); 2275 } else { 2276 if (ifp->if_flags & IFF_RUNNING) 2277 re_stop(sc); 2278 } 2279 error = 0; 2280 break; 2281 case SIOCADDMULTI: 2282 case SIOCDELMULTI: 2283 re_setmulti(sc); 2284 error = 0; 2285 break; 2286 case SIOCGIFMEDIA: 2287 case SIOCSIFMEDIA: 2288 mii = device_get_softc(sc->rl_miibus); 2289 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2290 break; 2291 case SIOCSIFCAP: 2292 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2293 ifp->if_capenable |= 2294 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2295 if (ifp->if_capenable & IFCAP_TXCSUM) 2296 ifp->if_hwassist = RE_CSUM_FEATURES; 2297 else 2298 ifp->if_hwassist = 0; 2299 if (ifp->if_flags & IFF_RUNNING) 2300 re_init(sc); 2301 break; 2302 default: 2303 error = ether_ioctl(ifp, command, data); 2304 break; 2305 } 2306 2307 RL_UNLOCK(sc); 2308 2309 return(error); 2310} 2311 2312static void 2313re_watchdog(ifp) 2314 struct ifnet *ifp; 2315{ 2316 struct rl_softc *sc; 2317 2318 sc = ifp->if_softc; 2319 RL_LOCK(sc); 2320 printf("re%d: watchdog timeout\n", sc->rl_unit); 2321 ifp->if_oerrors++; 2322 2323 re_txeof(sc); 2324 re_rxeof(sc); 2325 2326 re_init(sc); 2327 2328 RL_UNLOCK(sc); 2329 2330 return; 2331} 2332 2333/* 2334 * Stop the adapter and free any mbufs allocated to the 2335 * RX and TX lists. 2336 */ 2337static void 2338re_stop(sc) 2339 struct rl_softc *sc; 2340{ 2341 register int i; 2342 struct ifnet *ifp; 2343 2344 RL_LOCK(sc); 2345 ifp = &sc->arpcom.ac_if; 2346 ifp->if_timer = 0; 2347 2348 untimeout(re_tick, sc, sc->rl_stat_ch); 2349 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2350#ifdef DEVICE_POLLING 2351 ether_poll_deregister(ifp); 2352#endif /* DEVICE_POLLING */ 2353 2354 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2355 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2356 2357 if (sc->rl_head != NULL) { 2358 m_freem(sc->rl_head); 2359 sc->rl_head = sc->rl_tail = NULL; 2360 } 2361 2362 /* Free the TX list buffers. */ 2363 2364 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2365 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2366 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2367 sc->rl_ldata.rl_tx_dmamap[i]); 2368 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2369 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2370 } 2371 } 2372 2373 /* Free the RX list buffers. */ 2374 2375 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2376 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2377 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2378 sc->rl_ldata.rl_rx_dmamap[i]); 2379 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2380 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2381 } 2382 } 2383 2384 RL_UNLOCK(sc); 2385 return; 2386} 2387 2388/* 2389 * Device suspend routine. Stop the interface and save some PCI 2390 * settings in case the BIOS doesn't restore them properly on 2391 * resume. 2392 */ 2393static int 2394re_suspend(dev) 2395 device_t dev; 2396{ 2397#ifndef BURN_BRIDGES 2398 register int i; 2399#endif 2400 struct rl_softc *sc; 2401 2402 sc = device_get_softc(dev); 2403 2404 re_stop(sc); 2405 2406#ifndef BURN_BRIDGES 2407 for (i = 0; i < 5; i++) 2408 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2409 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2410 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2411 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2412 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2413#endif 2414 2415 sc->suspended = 1; 2416 2417 return (0); 2418} 2419 2420/* 2421 * Device resume routine. Restore some PCI settings in case the BIOS 2422 * doesn't, re-enable busmastering, and restart the interface if 2423 * appropriate. 2424 */ 2425static int 2426re_resume(dev) 2427 device_t dev; 2428{ 2429#ifndef BURN_BRIDGES 2430 register int i; 2431#endif 2432 struct rl_softc *sc; 2433 struct ifnet *ifp; 2434 2435 sc = device_get_softc(dev); 2436 ifp = &sc->arpcom.ac_if; 2437 2438#ifndef BURN_BRIDGES 2439 /* better way to do this? */ 2440 for (i = 0; i < 5; i++) 2441 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2442 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2443 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2444 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2445 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2446 2447 /* reenable busmastering */ 2448 pci_enable_busmaster(dev); 2449 pci_enable_io(dev, RL_RES); 2450#endif 2451 2452 /* reinitialize interface if necessary */ 2453 if (ifp->if_flags & IFF_UP) 2454 re_init(sc); 2455 2456 sc->suspended = 0; 2457 2458 return (0); 2459} 2460 2461/* 2462 * Stop all chip I/O so that the kernel's probe routines don't 2463 * get confused by errant DMAs when rebooting. 2464 */ 2465static void 2466re_shutdown(dev) 2467 device_t dev; 2468{ 2469 struct rl_softc *sc; 2470 2471 sc = device_get_softc(dev); 2472 2473 re_stop(sc); 2474 2475 return; 2476} 2477