if_re.c revision 129879
1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 129879 2004-05-30 20:08:47Z phk $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7.5K, so the max MTU possible with this 108 * driver is 7500 bytes. 109 */ 110 111#include <sys/param.h> 112#include <sys/endian.h> 113#include <sys/systm.h> 114#include <sys/sockio.h> 115#include <sys/mbuf.h> 116#include <sys/malloc.h> 117#include <sys/module.h> 118#include <sys/kernel.h> 119#include <sys/socket.h> 120 121#include <net/if.h> 122#include <net/if_arp.h> 123#include <net/ethernet.h> 124#include <net/if_dl.h> 125#include <net/if_media.h> 126#include <net/if_vlan_var.h> 127 128#include <net/bpf.h> 129 130#include <machine/bus_pio.h> 131#include <machine/bus_memio.h> 132#include <machine/bus.h> 133#include <machine/resource.h> 134#include <sys/bus.h> 135#include <sys/rman.h> 136 137#include <dev/mii/mii.h> 138#include <dev/mii/miivar.h> 139 140#include <dev/pci/pcireg.h> 141#include <dev/pci/pcivar.h> 142 143MODULE_DEPEND(re, pci, 1, 1, 1); 144MODULE_DEPEND(re, ether, 1, 1, 1); 145MODULE_DEPEND(re, miibus, 1, 1, 1); 146 147/* "controller miibus0" required. See GENERIC if you get errors here. */ 148#include "miibus_if.h" 149 150/* 151 * Default to using PIO access for this driver. 152 */ 153#define RE_USEIOSPACE 154 155#include <pci/if_rlreg.h> 156 157#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 159/* 160 * Various supported device vendors/types and their names. 161 */ 162static struct rl_type re_devs[] = { 163 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 164 "RealTek 8139C+ 10/100BaseTX" }, 165 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 166 "RealTek 8169 Gigabit Ethernet" }, 167 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 168 "RealTek 8169S Single-chip Gigabit Ethernet" }, 169 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 170 "RealTek 8110S Single-chip Gigabit Ethernet" }, 171 { 0, 0, 0, NULL } 172}; 173 174static struct rl_hwrev re_hwrevs[] = { 175 { RL_HWREV_8139, RL_8139, "" }, 176 { RL_HWREV_8139A, RL_8139, "A" }, 177 { RL_HWREV_8139AG, RL_8139, "A-G" }, 178 { RL_HWREV_8139B, RL_8139, "B" }, 179 { RL_HWREV_8130, RL_8139, "8130" }, 180 { RL_HWREV_8139C, RL_8139, "C" }, 181 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 182 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 183 { RL_HWREV_8169, RL_8169, "8169"}, 184 { RL_HWREV_8169S, RL_8169, "8169S"}, 185 { RL_HWREV_8110S, RL_8169, "8110S"}, 186 { RL_HWREV_8100, RL_8139, "8100"}, 187 { RL_HWREV_8101, RL_8139, "8101"}, 188 { 0, 0, NULL } 189}; 190 191static int re_probe (device_t); 192static int re_attach (device_t); 193static int re_detach (device_t); 194 195static int re_encap (struct rl_softc *, struct mbuf *, int *); 196 197static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 198static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 199 bus_size_t, int); 200static int re_allocmem (device_t, struct rl_softc *); 201static int re_newbuf (struct rl_softc *, int, struct mbuf *); 202static int re_rx_list_init (struct rl_softc *); 203static int re_tx_list_init (struct rl_softc *); 204static void re_rxeof (struct rl_softc *); 205static void re_txeof (struct rl_softc *); 206static void re_intr (void *); 207static void re_tick (void *); 208static void re_start (struct ifnet *); 209static int re_ioctl (struct ifnet *, u_long, caddr_t); 210static void re_init (void *); 211static void re_stop (struct rl_softc *); 212static void re_watchdog (struct ifnet *); 213static int re_suspend (device_t); 214static int re_resume (device_t); 215static void re_shutdown (device_t); 216static int re_ifmedia_upd (struct ifnet *); 217static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 218 219static void re_eeprom_putbyte (struct rl_softc *, int); 220static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 221static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 222static int re_gmii_readreg (device_t, int, int); 223static int re_gmii_writereg (device_t, int, int, int); 224 225static int re_miibus_readreg (device_t, int, int); 226static int re_miibus_writereg (device_t, int, int, int); 227static void re_miibus_statchg (device_t); 228 229static uint32_t re_mchash (const uint8_t *); 230static void re_setmulti (struct rl_softc *); 231static void re_reset (struct rl_softc *); 232 233static int re_diag (struct rl_softc *); 234 235#ifdef RE_USEIOSPACE 236#define RL_RES SYS_RES_IOPORT 237#define RL_RID RL_PCI_LOIO 238#else 239#define RL_RES SYS_RES_MEMORY 240#define RL_RID RL_PCI_LOMEM 241#endif 242 243static device_method_t re_methods[] = { 244 /* Device interface */ 245 DEVMETHOD(device_probe, re_probe), 246 DEVMETHOD(device_attach, re_attach), 247 DEVMETHOD(device_detach, re_detach), 248 DEVMETHOD(device_suspend, re_suspend), 249 DEVMETHOD(device_resume, re_resume), 250 DEVMETHOD(device_shutdown, re_shutdown), 251 252 /* bus interface */ 253 DEVMETHOD(bus_print_child, bus_generic_print_child), 254 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 255 256 /* MII interface */ 257 DEVMETHOD(miibus_readreg, re_miibus_readreg), 258 DEVMETHOD(miibus_writereg, re_miibus_writereg), 259 DEVMETHOD(miibus_statchg, re_miibus_statchg), 260 261 { 0, 0 } 262}; 263 264static driver_t re_driver = { 265 "re", 266 re_methods, 267 sizeof(struct rl_softc) 268}; 269 270static devclass_t re_devclass; 271 272DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 273DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 274DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 275 276#define EE_SET(x) \ 277 CSR_WRITE_1(sc, RL_EECMD, \ 278 CSR_READ_1(sc, RL_EECMD) | x) 279 280#define EE_CLR(x) \ 281 CSR_WRITE_1(sc, RL_EECMD, \ 282 CSR_READ_1(sc, RL_EECMD) & ~x) 283 284/* 285 * Send a read command and address to the EEPROM, check for ACK. 286 */ 287static void 288re_eeprom_putbyte(sc, addr) 289 struct rl_softc *sc; 290 int addr; 291{ 292 register int d, i; 293 294 d = addr | sc->rl_eecmd_read; 295 296 /* 297 * Feed in each bit and strobe the clock. 298 */ 299 for (i = 0x400; i; i >>= 1) { 300 if (d & i) { 301 EE_SET(RL_EE_DATAIN); 302 } else { 303 EE_CLR(RL_EE_DATAIN); 304 } 305 DELAY(100); 306 EE_SET(RL_EE_CLK); 307 DELAY(150); 308 EE_CLR(RL_EE_CLK); 309 DELAY(100); 310 } 311 312 return; 313} 314 315/* 316 * Read a word of data stored in the EEPROM at address 'addr.' 317 */ 318static void 319re_eeprom_getword(sc, addr, dest) 320 struct rl_softc *sc; 321 int addr; 322 u_int16_t *dest; 323{ 324 register int i; 325 u_int16_t word = 0; 326 327 /* Enter EEPROM access mode. */ 328 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 329 330 /* 331 * Send address of word we want to read. 332 */ 333 re_eeprom_putbyte(sc, addr); 334 335 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 336 337 /* 338 * Start reading bits from EEPROM. 339 */ 340 for (i = 0x8000; i; i >>= 1) { 341 EE_SET(RL_EE_CLK); 342 DELAY(100); 343 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 344 word |= i; 345 EE_CLR(RL_EE_CLK); 346 DELAY(100); 347 } 348 349 /* Turn off EEPROM access mode. */ 350 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 351 352 *dest = word; 353 354 return; 355} 356 357/* 358 * Read a sequence of words from the EEPROM. 359 */ 360static void 361re_read_eeprom(sc, dest, off, cnt, swap) 362 struct rl_softc *sc; 363 caddr_t dest; 364 int off; 365 int cnt; 366 int swap; 367{ 368 int i; 369 u_int16_t word = 0, *ptr; 370 371 for (i = 0; i < cnt; i++) { 372 re_eeprom_getword(sc, off + i, &word); 373 ptr = (u_int16_t *)(dest + (i * 2)); 374 if (swap) 375 *ptr = ntohs(word); 376 else 377 *ptr = word; 378 } 379 380 return; 381} 382 383static int 384re_gmii_readreg(dev, phy, reg) 385 device_t dev; 386 int phy, reg; 387{ 388 struct rl_softc *sc; 389 u_int32_t rval; 390 int i; 391 392 if (phy != 1) 393 return(0); 394 395 sc = device_get_softc(dev); 396 397 /* Let the rgephy driver read the GMEDIASTAT register */ 398 399 if (reg == RL_GMEDIASTAT) { 400 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 401 return(rval); 402 } 403 404 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 405 DELAY(1000); 406 407 for (i = 0; i < RL_TIMEOUT; i++) { 408 rval = CSR_READ_4(sc, RL_PHYAR); 409 if (rval & RL_PHYAR_BUSY) 410 break; 411 DELAY(100); 412 } 413 414 if (i == RL_TIMEOUT) { 415 printf ("re%d: PHY read failed\n", sc->rl_unit); 416 return (0); 417 } 418 419 return (rval & RL_PHYAR_PHYDATA); 420} 421 422static int 423re_gmii_writereg(dev, phy, reg, data) 424 device_t dev; 425 int phy, reg, data; 426{ 427 struct rl_softc *sc; 428 u_int32_t rval; 429 int i; 430 431 sc = device_get_softc(dev); 432 433 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 434 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 435 DELAY(1000); 436 437 for (i = 0; i < RL_TIMEOUT; i++) { 438 rval = CSR_READ_4(sc, RL_PHYAR); 439 if (!(rval & RL_PHYAR_BUSY)) 440 break; 441 DELAY(100); 442 } 443 444 if (i == RL_TIMEOUT) { 445 printf ("re%d: PHY write failed\n", sc->rl_unit); 446 return (0); 447 } 448 449 return (0); 450} 451 452static int 453re_miibus_readreg(dev, phy, reg) 454 device_t dev; 455 int phy, reg; 456{ 457 struct rl_softc *sc; 458 u_int16_t rval = 0; 459 u_int16_t re8139_reg = 0; 460 461 sc = device_get_softc(dev); 462 RL_LOCK(sc); 463 464 if (sc->rl_type == RL_8169) { 465 rval = re_gmii_readreg(dev, phy, reg); 466 RL_UNLOCK(sc); 467 return (rval); 468 } 469 470 /* Pretend the internal PHY is only at address 0 */ 471 if (phy) { 472 RL_UNLOCK(sc); 473 return(0); 474 } 475 switch(reg) { 476 case MII_BMCR: 477 re8139_reg = RL_BMCR; 478 break; 479 case MII_BMSR: 480 re8139_reg = RL_BMSR; 481 break; 482 case MII_ANAR: 483 re8139_reg = RL_ANAR; 484 break; 485 case MII_ANER: 486 re8139_reg = RL_ANER; 487 break; 488 case MII_ANLPAR: 489 re8139_reg = RL_LPAR; 490 break; 491 case MII_PHYIDR1: 492 case MII_PHYIDR2: 493 RL_UNLOCK(sc); 494 return(0); 495 /* 496 * Allow the rlphy driver to read the media status 497 * register. If we have a link partner which does not 498 * support NWAY, this is the register which will tell 499 * us the results of parallel detection. 500 */ 501 case RL_MEDIASTAT: 502 rval = CSR_READ_1(sc, RL_MEDIASTAT); 503 RL_UNLOCK(sc); 504 return(rval); 505 default: 506 printf("re%d: bad phy register\n", sc->rl_unit); 507 RL_UNLOCK(sc); 508 return(0); 509 } 510 rval = CSR_READ_2(sc, re8139_reg); 511 RL_UNLOCK(sc); 512 return(rval); 513} 514 515static int 516re_miibus_writereg(dev, phy, reg, data) 517 device_t dev; 518 int phy, reg, data; 519{ 520 struct rl_softc *sc; 521 u_int16_t re8139_reg = 0; 522 int rval = 0; 523 524 sc = device_get_softc(dev); 525 RL_LOCK(sc); 526 527 if (sc->rl_type == RL_8169) { 528 rval = re_gmii_writereg(dev, phy, reg, data); 529 RL_UNLOCK(sc); 530 return (rval); 531 } 532 533 /* Pretend the internal PHY is only at address 0 */ 534 if (phy) { 535 RL_UNLOCK(sc); 536 return(0); 537 } 538 switch(reg) { 539 case MII_BMCR: 540 re8139_reg = RL_BMCR; 541 break; 542 case MII_BMSR: 543 re8139_reg = RL_BMSR; 544 break; 545 case MII_ANAR: 546 re8139_reg = RL_ANAR; 547 break; 548 case MII_ANER: 549 re8139_reg = RL_ANER; 550 break; 551 case MII_ANLPAR: 552 re8139_reg = RL_LPAR; 553 break; 554 case MII_PHYIDR1: 555 case MII_PHYIDR2: 556 RL_UNLOCK(sc); 557 return(0); 558 break; 559 default: 560 printf("re%d: bad phy register\n", sc->rl_unit); 561 RL_UNLOCK(sc); 562 return(0); 563 } 564 CSR_WRITE_2(sc, re8139_reg, data); 565 RL_UNLOCK(sc); 566 return(0); 567} 568 569static void 570re_miibus_statchg(dev) 571 device_t dev; 572{ 573 return; 574} 575 576/* 577 * Calculate CRC of a multicast group address, return the upper 6 bits. 578 */ 579static uint32_t 580re_mchash(addr) 581 const uint8_t *addr; 582{ 583 uint32_t crc, carry; 584 int idx, bit; 585 uint8_t data; 586 587 /* Compute CRC for the address value. */ 588 crc = 0xFFFFFFFF; /* initial value */ 589 590 for (idx = 0; idx < 6; idx++) { 591 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 592 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 593 crc <<= 1; 594 if (carry) 595 crc = (crc ^ 0x04c11db6) | carry; 596 } 597 } 598 599 /* return the filter bit position */ 600 return(crc >> 26); 601} 602 603/* 604 * Program the 64-bit multicast hash filter. 605 */ 606static void 607re_setmulti(sc) 608 struct rl_softc *sc; 609{ 610 struct ifnet *ifp; 611 int h = 0; 612 u_int32_t hashes[2] = { 0, 0 }; 613 struct ifmultiaddr *ifma; 614 u_int32_t rxfilt; 615 int mcnt = 0; 616 617 ifp = &sc->arpcom.ac_if; 618 619 rxfilt = CSR_READ_4(sc, RL_RXCFG); 620 621 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 622 rxfilt |= RL_RXCFG_RX_MULTI; 623 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 624 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 625 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 626 return; 627 } 628 629 /* first, zot all the existing hash bits */ 630 CSR_WRITE_4(sc, RL_MAR0, 0); 631 CSR_WRITE_4(sc, RL_MAR4, 0); 632 633 /* now program new ones */ 634 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 635 if (ifma->ifma_addr->sa_family != AF_LINK) 636 continue; 637 h = re_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 638 if (h < 32) 639 hashes[0] |= (1 << h); 640 else 641 hashes[1] |= (1 << (h - 32)); 642 mcnt++; 643 } 644 645 if (mcnt) 646 rxfilt |= RL_RXCFG_RX_MULTI; 647 else 648 rxfilt &= ~RL_RXCFG_RX_MULTI; 649 650 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 651 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 652 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 653 654 return; 655} 656 657static void 658re_reset(sc) 659 struct rl_softc *sc; 660{ 661 register int i; 662 663 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 664 665 for (i = 0; i < RL_TIMEOUT; i++) { 666 DELAY(10); 667 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 668 break; 669 } 670 if (i == RL_TIMEOUT) 671 printf("re%d: reset never completed!\n", sc->rl_unit); 672 673 CSR_WRITE_1(sc, 0x82, 1); 674 675 return; 676} 677 678/* 679 * The following routine is designed to test for a defect on some 680 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 681 * lines connected to the bus, however for a 32-bit only card, they 682 * should be pulled high. The result of this defect is that the 683 * NIC will not work right if you plug it into a 64-bit slot: DMA 684 * operations will be done with 64-bit transfers, which will fail 685 * because the 64-bit data lines aren't connected. 686 * 687 * There's no way to work around this (short of talking a soldering 688 * iron to the board), however we can detect it. The method we use 689 * here is to put the NIC into digital loopback mode, set the receiver 690 * to promiscuous mode, and then try to send a frame. We then compare 691 * the frame data we sent to what was received. If the data matches, 692 * then the NIC is working correctly, otherwise we know the user has 693 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 694 * slot. In the latter case, there's no way the NIC can work correctly, 695 * so we print out a message on the console and abort the device attach. 696 */ 697 698static int 699re_diag(sc) 700 struct rl_softc *sc; 701{ 702 struct ifnet *ifp = &sc->arpcom.ac_if; 703 struct mbuf *m0; 704 struct ether_header *eh; 705 struct rl_desc *cur_rx; 706 u_int16_t status; 707 u_int32_t rxstat; 708 int total_len, i, error = 0; 709 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 710 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 711 712 /* Allocate a single mbuf */ 713 714 MGETHDR(m0, M_DONTWAIT, MT_DATA); 715 if (m0 == NULL) 716 return(ENOBUFS); 717 718 /* 719 * Initialize the NIC in test mode. This sets the chip up 720 * so that it can send and receive frames, but performs the 721 * following special functions: 722 * - Puts receiver in promiscuous mode 723 * - Enables digital loopback mode 724 * - Leaves interrupts turned off 725 */ 726 727 ifp->if_flags |= IFF_PROMISC; 728 sc->rl_testmode = 1; 729 re_init(sc); 730 re_stop(sc); 731 DELAY(100000); 732 re_init(sc); 733 734 /* Put some data in the mbuf */ 735 736 eh = mtod(m0, struct ether_header *); 737 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 738 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 739 eh->ether_type = htons(ETHERTYPE_IP); 740 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 741 742 /* 743 * Queue the packet, start transmission. 744 * Note: IF_HANDOFF() ultimately calls re_start() for us. 745 */ 746 747 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 748 IF_HANDOFF(&ifp->if_snd, m0, ifp); 749 m0 = NULL; 750 751 /* Wait for it to propagate through the chip */ 752 753 DELAY(100000); 754 for (i = 0; i < RL_TIMEOUT; i++) { 755 status = CSR_READ_2(sc, RL_ISR); 756 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 757 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 758 break; 759 DELAY(10); 760 } 761 762 if (i == RL_TIMEOUT) { 763 printf("re%d: diagnostic failed, failed to receive packet " 764 "in loopback mode\n", sc->rl_unit); 765 error = EIO; 766 goto done; 767 } 768 769 /* 770 * The packet should have been dumped into the first 771 * entry in the RX DMA ring. Grab it from there. 772 */ 773 774 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 775 sc->rl_ldata.rl_rx_list_map, 776 BUS_DMASYNC_POSTREAD); 777 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 778 sc->rl_ldata.rl_rx_dmamap[0], 779 BUS_DMASYNC_POSTWRITE); 780 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 781 sc->rl_ldata.rl_rx_dmamap[0]); 782 783 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 784 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 785 eh = mtod(m0, struct ether_header *); 786 787 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 788 total_len = RL_RXBYTES(cur_rx); 789 rxstat = le32toh(cur_rx->rl_cmdstat); 790 791 if (total_len != ETHER_MIN_LEN) { 792 printf("re%d: diagnostic failed, received short packet\n", 793 sc->rl_unit); 794 error = EIO; 795 goto done; 796 } 797 798 /* Test that the received packet data matches what we sent. */ 799 800 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 801 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 802 ntohs(eh->ether_type) != ETHERTYPE_IP) { 803 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 804 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 805 dst, ":", src, ":", ETHERTYPE_IP); 806 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 807 eh->ether_dhost, ":", eh->ether_shost, ":", 808 ntohs(eh->ether_type)); 809 printf("re%d: You may have a defective 32-bit NIC plugged " 810 "into a 64-bit PCI slot.\n", sc->rl_unit); 811 printf("re%d: Please re-install the NIC in a 32-bit slot " 812 "for proper operation.\n", sc->rl_unit); 813 printf("re%d: Read the re(4) man page for more details.\n", 814 sc->rl_unit); 815 error = EIO; 816 } 817 818done: 819 /* Turn interface off, release resources */ 820 821 sc->rl_testmode = 0; 822 ifp->if_flags &= ~IFF_PROMISC; 823 re_stop(sc); 824 if (m0 != NULL) 825 m_freem(m0); 826 827 return (error); 828} 829 830/* 831 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 832 * IDs against our list and return a device name if we find a match. 833 */ 834static int 835re_probe(dev) 836 device_t dev; 837{ 838 struct rl_type *t; 839 struct rl_softc *sc; 840 int rid; 841 u_int32_t hwrev; 842 843 t = re_devs; 844 sc = device_get_softc(dev); 845 846 while(t->rl_name != NULL) { 847 if ((pci_get_vendor(dev) == t->rl_vid) && 848 (pci_get_device(dev) == t->rl_did)) { 849 850 /* 851 * Temporarily map the I/O space 852 * so we can read the chip ID register. 853 */ 854 rid = RL_RID; 855 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 856 RF_ACTIVE); 857 if (sc->rl_res == NULL) { 858 device_printf(dev, 859 "couldn't map ports/memory\n"); 860 return(ENXIO); 861 } 862 sc->rl_btag = rman_get_bustag(sc->rl_res); 863 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 864 mtx_init(&sc->rl_mtx, 865 device_get_nameunit(dev), 866 MTX_NETWORK_LOCK, MTX_DEF); 867 RL_LOCK(sc); 868 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 869 bus_release_resource(dev, RL_RES, 870 RL_RID, sc->rl_res); 871 RL_UNLOCK(sc); 872 mtx_destroy(&sc->rl_mtx); 873 if (t->rl_basetype == hwrev) { 874 device_set_desc(dev, t->rl_name); 875 return(0); 876 } 877 } 878 t++; 879 } 880 881 return(ENXIO); 882} 883 884/* 885 * This routine takes the segment list provided as the result of 886 * a bus_dma_map_load() operation and assigns the addresses/lengths 887 * to RealTek DMA descriptors. This can be called either by the RX 888 * code or the TX code. In the RX case, we'll probably wind up mapping 889 * at most one segment. For the TX case, there could be any number of 890 * segments since TX packets may span multiple mbufs. In either case, 891 * if the number of segments is larger than the rl_maxsegs limit 892 * specified by the caller, we abort the mapping operation. Sadly, 893 * whoever designed the buffer mapping API did not provide a way to 894 * return an error from here, so we have to fake it a bit. 895 */ 896 897static void 898re_dma_map_desc(arg, segs, nseg, mapsize, error) 899 void *arg; 900 bus_dma_segment_t *segs; 901 int nseg; 902 bus_size_t mapsize; 903 int error; 904{ 905 struct rl_dmaload_arg *ctx; 906 struct rl_desc *d = NULL; 907 int i = 0, idx; 908 909 if (error) 910 return; 911 912 ctx = arg; 913 914 /* Signal error to caller if there's too many segments */ 915 if (nseg > ctx->rl_maxsegs) { 916 ctx->rl_maxsegs = 0; 917 return; 918 } 919 920 /* 921 * Map the segment array into descriptors. Note that we set the 922 * start-of-frame and end-of-frame markers for either TX or RX, but 923 * they really only have meaning in the TX case. (In the RX case, 924 * it's the chip that tells us where packets begin and end.) 925 * We also keep track of the end of the ring and set the 926 * end-of-ring bits as needed, and we set the ownership bits 927 * in all except the very first descriptor. (The caller will 928 * set this descriptor later when it start transmission or 929 * reception.) 930 */ 931 idx = ctx->rl_idx; 932 while(1) { 933 u_int32_t cmdstat; 934 d = &ctx->rl_ring[idx]; 935 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 936 ctx->rl_maxsegs = 0; 937 return; 938 } 939 cmdstat = segs[i].ds_len; 940 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 941 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 942 if (i == 0) 943 cmdstat |= RL_TDESC_CMD_SOF; 944 else 945 cmdstat |= RL_TDESC_CMD_OWN; 946 if (idx == (RL_RX_DESC_CNT - 1)) 947 cmdstat |= RL_TDESC_CMD_EOR; 948 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 949 i++; 950 if (i == nseg) 951 break; 952 RL_DESC_INC(idx); 953 } 954 955 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 956 ctx->rl_maxsegs = nseg; 957 ctx->rl_idx = idx; 958 959 return; 960} 961 962/* 963 * Map a single buffer address. 964 */ 965 966static void 967re_dma_map_addr(arg, segs, nseg, error) 968 void *arg; 969 bus_dma_segment_t *segs; 970 int nseg; 971 int error; 972{ 973 u_int32_t *addr; 974 975 if (error) 976 return; 977 978 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 979 addr = arg; 980 *addr = segs->ds_addr; 981 982 return; 983} 984 985static int 986re_allocmem(dev, sc) 987 device_t dev; 988 struct rl_softc *sc; 989{ 990 int error; 991 int nseg; 992 int i; 993 994 /* 995 * Allocate map for RX mbufs. 996 */ 997 nseg = 32; 998 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 999 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1000 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 1001 NULL, NULL, &sc->rl_ldata.rl_mtag); 1002 if (error) { 1003 device_printf(dev, "could not allocate dma tag\n"); 1004 return (ENOMEM); 1005 } 1006 1007 /* 1008 * Allocate map for TX descriptor list. 1009 */ 1010 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1011 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1012 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1013 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1014 if (error) { 1015 device_printf(dev, "could not allocate dma tag\n"); 1016 return (ENOMEM); 1017 } 1018 1019 /* Allocate DMA'able memory for the TX ring */ 1020 1021 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1022 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1023 &sc->rl_ldata.rl_tx_list_map); 1024 if (error) 1025 return (ENOMEM); 1026 1027 /* Load the map for the TX ring. */ 1028 1029 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1030 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1031 RL_TX_LIST_SZ, re_dma_map_addr, 1032 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1033 1034 /* Create DMA maps for TX buffers */ 1035 1036 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1037 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1038 &sc->rl_ldata.rl_tx_dmamap[i]); 1039 if (error) { 1040 device_printf(dev, "can't create DMA map for TX\n"); 1041 return(ENOMEM); 1042 } 1043 } 1044 1045 /* 1046 * Allocate map for RX descriptor list. 1047 */ 1048 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1049 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1050 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1051 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1052 if (error) { 1053 device_printf(dev, "could not allocate dma tag\n"); 1054 return (ENOMEM); 1055 } 1056 1057 /* Allocate DMA'able memory for the RX ring */ 1058 1059 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1060 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1061 &sc->rl_ldata.rl_rx_list_map); 1062 if (error) 1063 return (ENOMEM); 1064 1065 /* Load the map for the RX ring. */ 1066 1067 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1068 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1069 RL_TX_LIST_SZ, re_dma_map_addr, 1070 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1071 1072 /* Create DMA maps for RX buffers */ 1073 1074 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1075 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1076 &sc->rl_ldata.rl_rx_dmamap[i]); 1077 if (error) { 1078 device_printf(dev, "can't create DMA map for RX\n"); 1079 return(ENOMEM); 1080 } 1081 } 1082 1083 return(0); 1084} 1085 1086/* 1087 * Attach the interface. Allocate softc structures, do ifmedia 1088 * setup and ethernet/BPF attach. 1089 */ 1090static int 1091re_attach(dev) 1092 device_t dev; 1093{ 1094 u_char eaddr[ETHER_ADDR_LEN]; 1095 u_int16_t as[3]; 1096 struct rl_softc *sc; 1097 struct ifnet *ifp; 1098 struct rl_hwrev *hw_rev; 1099 int hwrev; 1100 u_int16_t re_did = 0; 1101 int unit, error = 0, rid, i; 1102 1103 sc = device_get_softc(dev); 1104 unit = device_get_unit(dev); 1105 1106 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1107 MTX_DEF | MTX_RECURSE); 1108#ifndef BURN_BRIDGES 1109 /* 1110 * Handle power management nonsense. 1111 */ 1112 1113 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1114 u_int32_t iobase, membase, irq; 1115 1116 /* Save important PCI config data. */ 1117 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 1118 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 1119 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 1120 1121 /* Reset the power state. */ 1122 printf("re%d: chip is is in D%d power mode " 1123 "-- setting to D0\n", unit, 1124 pci_get_powerstate(dev)); 1125 1126 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1127 1128 /* Restore PCI config data. */ 1129 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 1130 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 1131 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 1132 } 1133#endif 1134 /* 1135 * Map control/status registers. 1136 */ 1137 pci_enable_busmaster(dev); 1138 1139 rid = RL_RID; 1140 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1141 RF_ACTIVE); 1142 1143 if (sc->rl_res == NULL) { 1144 printf ("re%d: couldn't map ports/memory\n", unit); 1145 error = ENXIO; 1146 goto fail; 1147 } 1148 1149 sc->rl_btag = rman_get_bustag(sc->rl_res); 1150 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1151 1152 /* Allocate interrupt */ 1153 rid = 0; 1154 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1155 RF_SHAREABLE | RF_ACTIVE); 1156 1157 if (sc->rl_irq == NULL) { 1158 printf("re%d: couldn't map interrupt\n", unit); 1159 error = ENXIO; 1160 goto fail; 1161 } 1162 1163 /* Reset the adapter. */ 1164 re_reset(sc); 1165 1166 hw_rev = re_hwrevs; 1167 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1168 while (hw_rev->rl_desc != NULL) { 1169 if (hw_rev->rl_rev == hwrev) { 1170 sc->rl_type = hw_rev->rl_type; 1171 break; 1172 } 1173 hw_rev++; 1174 } 1175 1176 if (sc->rl_type == RL_8169) { 1177 1178 /* Set RX length mask */ 1179 1180 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1181 1182 /* Force station address autoload from the EEPROM */ 1183 1184 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1185 for (i = 0; i < RL_TIMEOUT; i++) { 1186 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1187 break; 1188 DELAY(100); 1189 } 1190 if (i == RL_TIMEOUT) 1191 printf ("re%d: eeprom autoload timed out\n", unit); 1192 1193 for (i = 0; i < ETHER_ADDR_LEN; i++) 1194 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1195 } else { 1196 1197 /* Set RX length mask */ 1198 1199 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1200 1201 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1202 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1203 if (re_did != 0x8129) 1204 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1205 1206 /* 1207 * Get station address from the EEPROM. 1208 */ 1209 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1210 for (i = 0; i < 3; i++) { 1211 eaddr[(i * 2) + 0] = as[i] & 0xff; 1212 eaddr[(i * 2) + 1] = as[i] >> 8; 1213 } 1214 } 1215 1216 sc->rl_unit = unit; 1217 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1218 1219 /* 1220 * Allocate the parent bus DMA tag appropriate for PCI. 1221 */ 1222#define RL_NSEG_NEW 32 1223 error = bus_dma_tag_create(NULL, /* parent */ 1224 1, 0, /* alignment, boundary */ 1225 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1226 BUS_SPACE_MAXADDR, /* highaddr */ 1227 NULL, NULL, /* filter, filterarg */ 1228 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1229 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1230 BUS_DMA_ALLOCNOW, /* flags */ 1231 NULL, NULL, /* lockfunc, lockarg */ 1232 &sc->rl_parent_tag); 1233 if (error) 1234 goto fail; 1235 1236 error = re_allocmem(dev, sc); 1237 1238 if (error) 1239 goto fail; 1240 1241 /* Do MII setup */ 1242 if (mii_phy_probe(dev, &sc->rl_miibus, 1243 re_ifmedia_upd, re_ifmedia_sts)) { 1244 printf("re%d: MII without any phy!\n", sc->rl_unit); 1245 error = ENXIO; 1246 goto fail; 1247 } 1248 1249 ifp = &sc->arpcom.ac_if; 1250 ifp->if_softc = sc; 1251 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1252 ifp->if_mtu = ETHERMTU; 1253 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1254 ifp->if_ioctl = re_ioctl; 1255 ifp->if_capabilities = IFCAP_VLAN_MTU; 1256 ifp->if_start = re_start; 1257 ifp->if_hwassist = RE_CSUM_FEATURES; 1258 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1259#ifdef DEVICE_POLLING 1260 ifp->if_capabilities |= IFCAP_POLLING; 1261#endif 1262 ifp->if_watchdog = re_watchdog; 1263 ifp->if_init = re_init; 1264 if (sc->rl_type == RL_8169) 1265 ifp->if_baudrate = 1000000000; 1266 else 1267 ifp->if_baudrate = 100000000; 1268 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; 1269 ifp->if_capenable = ifp->if_capabilities; 1270 1271 callout_handle_init(&sc->rl_stat_ch); 1272 1273 /* 1274 * Call MI attach routine. 1275 */ 1276 ether_ifattach(ifp, eaddr); 1277 1278 /* Perform hardware diagnostic. */ 1279 error = re_diag(sc); 1280 1281 if (error) { 1282 printf("re%d: attach aborted due to hardware diag failure\n", 1283 unit); 1284 ether_ifdetach(ifp); 1285 goto fail; 1286 } 1287 1288 /* Hook interrupt last to avoid having to lock softc */ 1289 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1290 re_intr, sc, &sc->rl_intrhand); 1291 1292 if (error) { 1293 printf("re%d: couldn't set up irq\n", unit); 1294 ether_ifdetach(ifp); 1295 goto fail; 1296 } 1297 1298fail: 1299 if (error) 1300 re_detach(dev); 1301 1302 return (error); 1303} 1304 1305/* 1306 * Shutdown hardware and free up resources. This can be called any 1307 * time after the mutex has been initialized. It is called in both 1308 * the error case in attach and the normal detach case so it needs 1309 * to be careful about only freeing resources that have actually been 1310 * allocated. 1311 */ 1312static int 1313re_detach(dev) 1314 device_t dev; 1315{ 1316 struct rl_softc *sc; 1317 struct ifnet *ifp; 1318 int i; 1319 1320 sc = device_get_softc(dev); 1321 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1322 RL_LOCK(sc); 1323 ifp = &sc->arpcom.ac_if; 1324 1325 /* These should only be active if attach succeeded */ 1326 if (device_is_attached(dev)) { 1327 re_stop(sc); 1328 /* 1329 * Force off the IFF_UP flag here, in case someone 1330 * still had a BPF descriptor attached to this 1331 * interface. If they do, ether_ifattach() will cause 1332 * the BPF code to try and clear the promisc mode 1333 * flag, which will bubble down to re_ioctl(), 1334 * which will try to call re_init() again. This will 1335 * turn the NIC back on and restart the MII ticker, 1336 * which will panic the system when the kernel tries 1337 * to invoke the re_tick() function that isn't there 1338 * anymore. 1339 */ 1340 ifp->if_flags &= ~IFF_UP; 1341 ether_ifdetach(ifp); 1342 } 1343 if (sc->rl_miibus) 1344 device_delete_child(dev, sc->rl_miibus); 1345 bus_generic_detach(dev); 1346 1347 if (sc->rl_intrhand) 1348 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1349 if (sc->rl_irq) 1350 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1351 if (sc->rl_res) 1352 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1353 1354 1355 /* Unload and free the RX DMA ring memory and map */ 1356 1357 if (sc->rl_ldata.rl_rx_list_tag) { 1358 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1359 sc->rl_ldata.rl_rx_list_map); 1360 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1361 sc->rl_ldata.rl_rx_list, 1362 sc->rl_ldata.rl_rx_list_map); 1363 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1364 } 1365 1366 /* Unload and free the TX DMA ring memory and map */ 1367 1368 if (sc->rl_ldata.rl_tx_list_tag) { 1369 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1370 sc->rl_ldata.rl_tx_list_map); 1371 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1372 sc->rl_ldata.rl_tx_list, 1373 sc->rl_ldata.rl_tx_list_map); 1374 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1375 } 1376 1377 /* Destroy all the RX and TX buffer maps */ 1378 1379 if (sc->rl_ldata.rl_mtag) { 1380 for (i = 0; i < RL_TX_DESC_CNT; i++) 1381 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1382 sc->rl_ldata.rl_tx_dmamap[i]); 1383 for (i = 0; i < RL_RX_DESC_CNT; i++) 1384 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1385 sc->rl_ldata.rl_rx_dmamap[i]); 1386 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1387 } 1388 1389 /* Unload and free the stats buffer and map */ 1390 1391 if (sc->rl_ldata.rl_stag) { 1392 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1393 sc->rl_ldata.rl_rx_list_map); 1394 bus_dmamem_free(sc->rl_ldata.rl_stag, 1395 sc->rl_ldata.rl_stats, 1396 sc->rl_ldata.rl_smap); 1397 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1398 } 1399 1400 if (sc->rl_parent_tag) 1401 bus_dma_tag_destroy(sc->rl_parent_tag); 1402 1403 RL_UNLOCK(sc); 1404 mtx_destroy(&sc->rl_mtx); 1405 1406 return(0); 1407} 1408 1409static int 1410re_newbuf(sc, idx, m) 1411 struct rl_softc *sc; 1412 int idx; 1413 struct mbuf *m; 1414{ 1415 struct rl_dmaload_arg arg; 1416 struct mbuf *n = NULL; 1417 int error; 1418 1419 if (m == NULL) { 1420 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1421 if (n == NULL) 1422 return(ENOBUFS); 1423 m = n; 1424 } else 1425 m->m_data = m->m_ext.ext_buf; 1426 1427 /* 1428 * Initialize mbuf length fields and fixup 1429 * alignment so that the frame payload is 1430 * longword aligned. 1431 */ 1432 m->m_len = m->m_pkthdr.len = MCLBYTES; 1433 m_adj(m, ETHER_ALIGN); 1434 1435 arg.sc = sc; 1436 arg.rl_idx = idx; 1437 arg.rl_maxsegs = 1; 1438 arg.rl_flags = 0; 1439 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1440 1441 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1442 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1443 &arg, BUS_DMA_NOWAIT); 1444 if (error || arg.rl_maxsegs != 1) { 1445 if (n != NULL) 1446 m_freem(n); 1447 return (ENOMEM); 1448 } 1449 1450 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1451 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1452 1453 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1454 sc->rl_ldata.rl_rx_dmamap[idx], 1455 BUS_DMASYNC_PREREAD); 1456 1457 return(0); 1458} 1459 1460static int 1461re_tx_list_init(sc) 1462 struct rl_softc *sc; 1463{ 1464 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1465 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1466 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1467 1468 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1469 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1470 sc->rl_ldata.rl_tx_prodidx = 0; 1471 sc->rl_ldata.rl_tx_considx = 0; 1472 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1473 1474 return(0); 1475} 1476 1477static int 1478re_rx_list_init(sc) 1479 struct rl_softc *sc; 1480{ 1481 int i; 1482 1483 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1484 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1485 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1486 1487 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1488 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1489 return(ENOBUFS); 1490 } 1491 1492 /* Flush the RX descriptors */ 1493 1494 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1495 sc->rl_ldata.rl_rx_list_map, 1496 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1497 1498 sc->rl_ldata.rl_rx_prodidx = 0; 1499 sc->rl_head = sc->rl_tail = NULL; 1500 1501 return(0); 1502} 1503 1504/* 1505 * RX handler for C+ and 8169. For the gigE chips, we support 1506 * the reception of jumbo frames that have been fragmented 1507 * across multiple 2K mbuf cluster buffers. 1508 */ 1509static void 1510re_rxeof(sc) 1511 struct rl_softc *sc; 1512{ 1513 struct mbuf *m; 1514 struct ifnet *ifp; 1515 int i, total_len; 1516 struct rl_desc *cur_rx; 1517 u_int32_t rxstat, rxvlan; 1518 1519 RL_LOCK_ASSERT(sc); 1520 1521 ifp = &sc->arpcom.ac_if; 1522 i = sc->rl_ldata.rl_rx_prodidx; 1523 1524 /* Invalidate the descriptor memory */ 1525 1526 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1527 sc->rl_ldata.rl_rx_list_map, 1528 BUS_DMASYNC_POSTREAD); 1529 1530 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1531 1532 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1533 m = sc->rl_ldata.rl_rx_mbuf[i]; 1534 total_len = RL_RXBYTES(cur_rx); 1535 rxstat = le32toh(cur_rx->rl_cmdstat); 1536 rxvlan = le32toh(cur_rx->rl_vlanctl); 1537 1538 /* Invalidate the RX mbuf and unload its map */ 1539 1540 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1541 sc->rl_ldata.rl_rx_dmamap[i], 1542 BUS_DMASYNC_POSTWRITE); 1543 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1544 sc->rl_ldata.rl_rx_dmamap[i]); 1545 1546 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1547 m->m_len = MCLBYTES - ETHER_ALIGN; 1548 if (sc->rl_head == NULL) 1549 sc->rl_head = sc->rl_tail = m; 1550 else { 1551 m->m_flags &= ~M_PKTHDR; 1552 sc->rl_tail->m_next = m; 1553 sc->rl_tail = m; 1554 } 1555 re_newbuf(sc, i, NULL); 1556 RL_DESC_INC(i); 1557 continue; 1558 } 1559 1560 /* 1561 * NOTE: for the 8139C+, the frame length field 1562 * is always 12 bits in size, but for the gigE chips, 1563 * it is 13 bits (since the max RX frame length is 16K). 1564 * Unfortunately, all 32 bits in the status word 1565 * were already used, so to make room for the extra 1566 * length bit, RealTek took out the 'frame alignment 1567 * error' bit and shifted the other status bits 1568 * over one slot. The OWN, EOR, FS and LS bits are 1569 * still in the same places. We have already extracted 1570 * the frame length and checked the OWN bit, so rather 1571 * than using an alternate bit mapping, we shift the 1572 * status bits one space to the right so we can evaluate 1573 * them using the 8169 status as though it was in the 1574 * same format as that of the 8139C+. 1575 */ 1576 if (sc->rl_type == RL_8169) 1577 rxstat >>= 1; 1578 1579 if (rxstat & RL_RDESC_STAT_RXERRSUM) { 1580 ifp->if_ierrors++; 1581 /* 1582 * If this is part of a multi-fragment packet, 1583 * discard all the pieces. 1584 */ 1585 if (sc->rl_head != NULL) { 1586 m_freem(sc->rl_head); 1587 sc->rl_head = sc->rl_tail = NULL; 1588 } 1589 re_newbuf(sc, i, m); 1590 RL_DESC_INC(i); 1591 continue; 1592 } 1593 1594 /* 1595 * If allocating a replacement mbuf fails, 1596 * reload the current one. 1597 */ 1598 1599 if (re_newbuf(sc, i, NULL)) { 1600 ifp->if_ierrors++; 1601 if (sc->rl_head != NULL) { 1602 m_freem(sc->rl_head); 1603 sc->rl_head = sc->rl_tail = NULL; 1604 } 1605 re_newbuf(sc, i, m); 1606 RL_DESC_INC(i); 1607 continue; 1608 } 1609 1610 RL_DESC_INC(i); 1611 1612 if (sc->rl_head != NULL) { 1613 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1614 /* 1615 * Special case: if there's 4 bytes or less 1616 * in this buffer, the mbuf can be discarded: 1617 * the last 4 bytes is the CRC, which we don't 1618 * care about anyway. 1619 */ 1620 if (m->m_len <= ETHER_CRC_LEN) { 1621 sc->rl_tail->m_len -= 1622 (ETHER_CRC_LEN - m->m_len); 1623 m_freem(m); 1624 } else { 1625 m->m_len -= ETHER_CRC_LEN; 1626 m->m_flags &= ~M_PKTHDR; 1627 sc->rl_tail->m_next = m; 1628 } 1629 m = sc->rl_head; 1630 sc->rl_head = sc->rl_tail = NULL; 1631 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1632 } else 1633 m->m_pkthdr.len = m->m_len = 1634 (total_len - ETHER_CRC_LEN); 1635 1636 ifp->if_ipackets++; 1637 m->m_pkthdr.rcvif = ifp; 1638 1639 /* Do RX checksumming if enabled */ 1640 1641 if (ifp->if_capenable & IFCAP_RXCSUM) { 1642 1643 /* Check IP header checksum */ 1644 if (rxstat & RL_RDESC_STAT_PROTOID) 1645 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1646 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1647 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1648 1649 /* Check TCP/UDP checksum */ 1650 if ((RL_TCPPKT(rxstat) && 1651 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1652 (RL_UDPPKT(rxstat) && 1653 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1654 m->m_pkthdr.csum_flags |= 1655 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1656 m->m_pkthdr.csum_data = 0xffff; 1657 } 1658 } 1659 1660 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1661 VLAN_INPUT_TAG(ifp, m, 1662 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1663 RL_UNLOCK(sc); 1664 (*ifp->if_input)(ifp, m); 1665 RL_LOCK(sc); 1666 } 1667 1668 /* Flush the RX DMA ring */ 1669 1670 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1671 sc->rl_ldata.rl_rx_list_map, 1672 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1673 1674 sc->rl_ldata.rl_rx_prodidx = i; 1675 1676 return; 1677} 1678 1679static void 1680re_txeof(sc) 1681 struct rl_softc *sc; 1682{ 1683 struct ifnet *ifp; 1684 u_int32_t txstat; 1685 int idx; 1686 1687 ifp = &sc->arpcom.ac_if; 1688 idx = sc->rl_ldata.rl_tx_considx; 1689 1690 /* Invalidate the TX descriptor list */ 1691 1692 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1693 sc->rl_ldata.rl_tx_list_map, 1694 BUS_DMASYNC_POSTREAD); 1695 1696 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1697 1698 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1699 if (txstat & RL_TDESC_CMD_OWN) 1700 break; 1701 1702 /* 1703 * We only stash mbufs in the last descriptor 1704 * in a fragment chain, which also happens to 1705 * be the only place where the TX status bits 1706 * are valid. 1707 */ 1708 1709 if (txstat & RL_TDESC_CMD_EOF) { 1710 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1711 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1712 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1713 sc->rl_ldata.rl_tx_dmamap[idx]); 1714 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1715 RL_TDESC_STAT_COLCNT)) 1716 ifp->if_collisions++; 1717 if (txstat & RL_TDESC_STAT_TXERRSUM) 1718 ifp->if_oerrors++; 1719 else 1720 ifp->if_opackets++; 1721 } 1722 sc->rl_ldata.rl_tx_free++; 1723 RL_DESC_INC(idx); 1724 } 1725 1726 /* No changes made to the TX ring, so no flush needed */ 1727 1728 if (idx != sc->rl_ldata.rl_tx_considx) { 1729 sc->rl_ldata.rl_tx_considx = idx; 1730 ifp->if_flags &= ~IFF_OACTIVE; 1731 ifp->if_timer = 0; 1732 } 1733 1734 /* 1735 * If not all descriptors have been released reaped yet, 1736 * reload the timer so that we will eventually get another 1737 * interrupt that will cause us to re-enter this routine. 1738 * This is done in case the transmitter has gone idle. 1739 */ 1740 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1741 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1742 1743 return; 1744} 1745 1746static void 1747re_tick(xsc) 1748 void *xsc; 1749{ 1750 struct rl_softc *sc; 1751 struct mii_data *mii; 1752 1753 sc = xsc; 1754 RL_LOCK(sc); 1755 mii = device_get_softc(sc->rl_miibus); 1756 1757 mii_tick(mii); 1758 1759 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1760 RL_UNLOCK(sc); 1761 1762 return; 1763} 1764 1765#ifdef DEVICE_POLLING 1766static void 1767re_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1768{ 1769 struct rl_softc *sc = ifp->if_softc; 1770 1771 RL_LOCK(sc); 1772 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1773 ether_poll_deregister(ifp); 1774 cmd = POLL_DEREGISTER; 1775 } 1776 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1777 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1778 goto done; 1779 } 1780 1781 sc->rxcycles = count; 1782 re_rxeof(sc); 1783 re_txeof(sc); 1784 1785 if (ifp->if_snd.ifq_head != NULL) 1786 (*ifp->if_start)(ifp); 1787 1788 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1789 u_int16_t status; 1790 1791 status = CSR_READ_2(sc, RL_ISR); 1792 if (status == 0xffff) 1793 goto done; 1794 if (status) 1795 CSR_WRITE_2(sc, RL_ISR, status); 1796 1797 /* 1798 * XXX check behaviour on receiver stalls. 1799 */ 1800 1801 if (status & RL_ISR_SYSTEM_ERR) { 1802 re_reset(sc); 1803 re_init(sc); 1804 } 1805 } 1806done: 1807 RL_UNLOCK(sc); 1808} 1809#endif /* DEVICE_POLLING */ 1810 1811static void 1812re_intr(arg) 1813 void *arg; 1814{ 1815 struct rl_softc *sc; 1816 struct ifnet *ifp; 1817 u_int16_t status; 1818 1819 sc = arg; 1820 1821 if (sc->suspended) { 1822 return; 1823 } 1824 1825 RL_LOCK(sc); 1826 ifp = &sc->arpcom.ac_if; 1827 1828 if (!(ifp->if_flags & IFF_UP)) { 1829 RL_UNLOCK(sc); 1830 return; 1831 } 1832 1833#ifdef DEVICE_POLLING 1834 if (ifp->if_flags & IFF_POLLING) 1835 goto done; 1836 if ((ifp->if_capenable & IFCAP_POLLING) && 1837 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1838 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1839 re_poll(ifp, 0, 1); 1840 goto done; 1841 } 1842#endif /* DEVICE_POLLING */ 1843 1844 for (;;) { 1845 1846 status = CSR_READ_2(sc, RL_ISR); 1847 /* If the card has gone away the read returns 0xffff. */ 1848 if (status == 0xffff) 1849 break; 1850 if (status) 1851 CSR_WRITE_2(sc, RL_ISR, status); 1852 1853 if ((status & RL_INTRS_CPLUS) == 0) 1854 break; 1855 1856 if (status & RL_ISR_RX_OK) 1857 re_rxeof(sc); 1858 1859 if (status & RL_ISR_RX_ERR) 1860 re_rxeof(sc); 1861 1862 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1863 (status & RL_ISR_TX_ERR) || 1864 (status & RL_ISR_TX_DESC_UNAVAIL)) 1865 re_txeof(sc); 1866 1867 if (status & RL_ISR_SYSTEM_ERR) { 1868 re_reset(sc); 1869 re_init(sc); 1870 } 1871 1872 if (status & RL_ISR_LINKCHG) { 1873 untimeout(re_tick, sc, sc->rl_stat_ch); 1874 re_tick(sc); 1875 } 1876 } 1877 1878 if (ifp->if_snd.ifq_head != NULL) 1879 (*ifp->if_start)(ifp); 1880 1881#ifdef DEVICE_POLLING 1882done: 1883#endif 1884 RL_UNLOCK(sc); 1885 1886 return; 1887} 1888 1889static int 1890re_encap(sc, m_head, idx) 1891 struct rl_softc *sc; 1892 struct mbuf *m_head; 1893 int *idx; 1894{ 1895 struct mbuf *m_new = NULL; 1896 struct rl_dmaload_arg arg; 1897 bus_dmamap_t map; 1898 int error; 1899 struct m_tag *mtag; 1900 1901 if (sc->rl_ldata.rl_tx_free <= 4) 1902 return(EFBIG); 1903 1904 /* 1905 * Set up checksum offload. Note: checksum offload bits must 1906 * appear in all descriptors of a multi-descriptor transmit 1907 * attempt. (This is according to testing done with an 8169 1908 * chip. I'm not sure if this is a requirement or a bug.) 1909 */ 1910 1911 arg.rl_flags = 0; 1912 1913 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1914 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1915 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1916 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1917 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1918 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1919 1920 arg.sc = sc; 1921 arg.rl_idx = *idx; 1922 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1923 if (arg.rl_maxsegs > 4) 1924 arg.rl_maxsegs -= 4; 1925 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1926 1927 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1928 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1929 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1930 1931 if (error && error != EFBIG) { 1932 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1933 return(ENOBUFS); 1934 } 1935 1936 /* Too many segments to map, coalesce into a single mbuf */ 1937 1938 if (error || arg.rl_maxsegs == 0) { 1939 m_new = m_defrag(m_head, M_DONTWAIT); 1940 if (m_new == NULL) 1941 return(1); 1942 else 1943 m_head = m_new; 1944 1945 arg.sc = sc; 1946 arg.rl_idx = *idx; 1947 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1948 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1949 1950 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1951 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1952 if (error) { 1953 printf("re%d: can't map mbuf (error %d)\n", 1954 sc->rl_unit, error); 1955 return(EFBIG); 1956 } 1957 } 1958 1959 /* 1960 * Insure that the map for this transmission 1961 * is placed at the array index of the last descriptor 1962 * in this chain. 1963 */ 1964 sc->rl_ldata.rl_tx_dmamap[*idx] = 1965 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1966 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1967 1968 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head; 1969 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1970 1971 /* 1972 * Set up hardware VLAN tagging. Note: vlan tag info must 1973 * appear in the first descriptor of a multi-descriptor 1974 * transmission attempt. 1975 */ 1976 1977 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1978 if (mtag != NULL) 1979 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1980 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1981 1982 /* Transfer ownership of packet to the chip. */ 1983 1984 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1985 htole32(RL_TDESC_CMD_OWN); 1986 if (*idx != arg.rl_idx) 1987 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1988 htole32(RL_TDESC_CMD_OWN); 1989 1990 RL_DESC_INC(arg.rl_idx); 1991 *idx = arg.rl_idx; 1992 1993 return(0); 1994} 1995 1996/* 1997 * Main transmit routine for C+ and gigE NICs. 1998 */ 1999 2000static void 2001re_start(ifp) 2002 struct ifnet *ifp; 2003{ 2004 struct rl_softc *sc; 2005 struct mbuf *m_head = NULL; 2006 int idx; 2007 2008 sc = ifp->if_softc; 2009 RL_LOCK(sc); 2010 2011 idx = sc->rl_ldata.rl_tx_prodidx; 2012 2013 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2014 IF_DEQUEUE(&ifp->if_snd, m_head); 2015 if (m_head == NULL) 2016 break; 2017 2018 if (re_encap(sc, m_head, &idx)) { 2019 IF_PREPEND(&ifp->if_snd, m_head); 2020 ifp->if_flags |= IFF_OACTIVE; 2021 break; 2022 } 2023 2024 /* 2025 * If there's a BPF listener, bounce a copy of this frame 2026 * to him. 2027 */ 2028 BPF_MTAP(ifp, m_head); 2029 } 2030 2031 /* Flush the TX descriptors */ 2032 2033 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2034 sc->rl_ldata.rl_tx_list_map, 2035 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2036 2037 sc->rl_ldata.rl_tx_prodidx = idx; 2038 2039 /* 2040 * RealTek put the TX poll request register in a different 2041 * location on the 8169 gigE chip. I don't know why. 2042 */ 2043 2044 if (sc->rl_type == RL_8169) 2045 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2046 else 2047 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2048 2049 /* 2050 * Use the countdown timer for interrupt moderation. 2051 * 'TX done' interrupts are disabled. Instead, we reset the 2052 * countdown timer, which will begin counting until it hits 2053 * the value in the TIMERINT register, and then trigger an 2054 * interrupt. Each time we write to the TIMERCNT register, 2055 * the timer count is reset to 0. 2056 */ 2057 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2058 2059 RL_UNLOCK(sc); 2060 2061 /* 2062 * Set a timeout in case the chip goes out to lunch. 2063 */ 2064 ifp->if_timer = 5; 2065 2066 return; 2067} 2068 2069static void 2070re_init(xsc) 2071 void *xsc; 2072{ 2073 struct rl_softc *sc = xsc; 2074 struct ifnet *ifp = &sc->arpcom.ac_if; 2075 struct mii_data *mii; 2076 u_int32_t rxcfg = 0; 2077 2078 RL_LOCK(sc); 2079 mii = device_get_softc(sc->rl_miibus); 2080 2081 /* 2082 * Cancel pending I/O and free all RX/TX buffers. 2083 */ 2084 re_stop(sc); 2085 2086 /* 2087 * Enable C+ RX and TX mode, as well as VLAN stripping and 2088 * RX checksum offload. We must configure the C+ register 2089 * before all others. 2090 */ 2091 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2092 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2093 RL_CPLUSCMD_VLANSTRIP| 2094 (ifp->if_capenable & IFCAP_RXCSUM ? 2095 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2096 2097 /* 2098 * Init our MAC address. Even though the chipset 2099 * documentation doesn't mention it, we need to enter "Config 2100 * register write enable" mode to modify the ID registers. 2101 */ 2102 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2103 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2104 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2105 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2106 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2107 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2108 2109 /* 2110 * For C+ mode, initialize the RX descriptors and mbufs. 2111 */ 2112 re_rx_list_init(sc); 2113 re_tx_list_init(sc); 2114 2115 /* 2116 * Enable transmit and receive. 2117 */ 2118 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2119 2120 /* 2121 * Set the initial TX and RX configuration. 2122 */ 2123 if (sc->rl_testmode) { 2124 if (sc->rl_type == RL_8169) 2125 CSR_WRITE_4(sc, RL_TXCFG, 2126 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2127 else 2128 CSR_WRITE_4(sc, RL_TXCFG, 2129 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2130 } else 2131 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2132 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2133 2134 /* Set the individual bit to receive frames for this host only. */ 2135 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2136 rxcfg |= RL_RXCFG_RX_INDIV; 2137 2138 /* If we want promiscuous mode, set the allframes bit. */ 2139 if (ifp->if_flags & IFF_PROMISC) { 2140 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2141 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2142 } else { 2143 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2144 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2145 } 2146 2147 /* 2148 * Set capture broadcast bit to capture broadcast frames. 2149 */ 2150 if (ifp->if_flags & IFF_BROADCAST) { 2151 rxcfg |= RL_RXCFG_RX_BROAD; 2152 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2153 } else { 2154 rxcfg &= ~RL_RXCFG_RX_BROAD; 2155 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2156 } 2157 2158 /* 2159 * Program the multicast filter, if necessary. 2160 */ 2161 re_setmulti(sc); 2162 2163#ifdef DEVICE_POLLING 2164 /* 2165 * Disable interrupts if we are polling. 2166 */ 2167 if (ifp->if_flags & IFF_POLLING) 2168 CSR_WRITE_2(sc, RL_IMR, 0); 2169 else /* otherwise ... */ 2170#endif /* DEVICE_POLLING */ 2171 /* 2172 * Enable interrupts. 2173 */ 2174 if (sc->rl_testmode) 2175 CSR_WRITE_2(sc, RL_IMR, 0); 2176 else 2177 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2178 2179 /* Set initial TX threshold */ 2180 sc->rl_txthresh = RL_TX_THRESH_INIT; 2181 2182 /* Start RX/TX process. */ 2183 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2184#ifdef notdef 2185 /* Enable receiver and transmitter. */ 2186 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2187#endif 2188 /* 2189 * Load the addresses of the RX and TX lists into the chip. 2190 */ 2191 2192 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2193 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2194 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2195 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2196 2197 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2198 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2199 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2200 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2201 2202 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2203 2204 /* 2205 * Initialize the timer interrupt register so that 2206 * a timer interrupt will be generated once the timer 2207 * reaches a certain number of ticks. The timer is 2208 * reloaded on each transmit. This gives us TX interrupt 2209 * moderation, which dramatically improves TX frame rate. 2210 */ 2211 2212 if (sc->rl_type == RL_8169) 2213 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2214 else 2215 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2216 2217 /* 2218 * For 8169 gigE NICs, set the max allowed RX packet 2219 * size so we can receive jumbo frames. 2220 */ 2221 if (sc->rl_type == RL_8169) 2222 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2223 2224 if (sc->rl_testmode) { 2225 RL_UNLOCK(sc); 2226 return; 2227 } 2228 2229 mii_mediachg(mii); 2230 2231 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2232 2233 ifp->if_flags |= IFF_RUNNING; 2234 ifp->if_flags &= ~IFF_OACTIVE; 2235 2236 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2237 RL_UNLOCK(sc); 2238 2239 return; 2240} 2241 2242/* 2243 * Set media options. 2244 */ 2245static int 2246re_ifmedia_upd(ifp) 2247 struct ifnet *ifp; 2248{ 2249 struct rl_softc *sc; 2250 struct mii_data *mii; 2251 2252 sc = ifp->if_softc; 2253 mii = device_get_softc(sc->rl_miibus); 2254 mii_mediachg(mii); 2255 2256 return(0); 2257} 2258 2259/* 2260 * Report current media status. 2261 */ 2262static void 2263re_ifmedia_sts(ifp, ifmr) 2264 struct ifnet *ifp; 2265 struct ifmediareq *ifmr; 2266{ 2267 struct rl_softc *sc; 2268 struct mii_data *mii; 2269 2270 sc = ifp->if_softc; 2271 mii = device_get_softc(sc->rl_miibus); 2272 2273 mii_pollstat(mii); 2274 ifmr->ifm_active = mii->mii_media_active; 2275 ifmr->ifm_status = mii->mii_media_status; 2276 2277 return; 2278} 2279 2280static int 2281re_ioctl(ifp, command, data) 2282 struct ifnet *ifp; 2283 u_long command; 2284 caddr_t data; 2285{ 2286 struct rl_softc *sc = ifp->if_softc; 2287 struct ifreq *ifr = (struct ifreq *) data; 2288 struct mii_data *mii; 2289 int error = 0; 2290 2291 RL_LOCK(sc); 2292 2293 switch(command) { 2294 case SIOCSIFMTU: 2295 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2296 error = EINVAL; 2297 ifp->if_mtu = ifr->ifr_mtu; 2298 break; 2299 case SIOCSIFFLAGS: 2300 if (ifp->if_flags & IFF_UP) { 2301 re_init(sc); 2302 } else { 2303 if (ifp->if_flags & IFF_RUNNING) 2304 re_stop(sc); 2305 } 2306 error = 0; 2307 break; 2308 case SIOCADDMULTI: 2309 case SIOCDELMULTI: 2310 re_setmulti(sc); 2311 error = 0; 2312 break; 2313 case SIOCGIFMEDIA: 2314 case SIOCSIFMEDIA: 2315 mii = device_get_softc(sc->rl_miibus); 2316 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2317 break; 2318 case SIOCSIFCAP: 2319 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2320 ifp->if_capenable |= 2321 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2322 if (ifp->if_capenable & IFCAP_TXCSUM) 2323 ifp->if_hwassist = RE_CSUM_FEATURES; 2324 else 2325 ifp->if_hwassist = 0; 2326 if (ifp->if_flags & IFF_RUNNING) 2327 re_init(sc); 2328 break; 2329 default: 2330 error = ether_ioctl(ifp, command, data); 2331 break; 2332 } 2333 2334 RL_UNLOCK(sc); 2335 2336 return(error); 2337} 2338 2339static void 2340re_watchdog(ifp) 2341 struct ifnet *ifp; 2342{ 2343 struct rl_softc *sc; 2344 2345 sc = ifp->if_softc; 2346 RL_LOCK(sc); 2347 printf("re%d: watchdog timeout\n", sc->rl_unit); 2348 ifp->if_oerrors++; 2349 2350 re_txeof(sc); 2351 re_rxeof(sc); 2352 2353 re_init(sc); 2354 2355 RL_UNLOCK(sc); 2356 2357 return; 2358} 2359 2360/* 2361 * Stop the adapter and free any mbufs allocated to the 2362 * RX and TX lists. 2363 */ 2364static void 2365re_stop(sc) 2366 struct rl_softc *sc; 2367{ 2368 register int i; 2369 struct ifnet *ifp; 2370 2371 RL_LOCK(sc); 2372 ifp = &sc->arpcom.ac_if; 2373 ifp->if_timer = 0; 2374 2375 untimeout(re_tick, sc, sc->rl_stat_ch); 2376 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2377#ifdef DEVICE_POLLING 2378 ether_poll_deregister(ifp); 2379#endif /* DEVICE_POLLING */ 2380 2381 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2382 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2383 2384 if (sc->rl_head != NULL) { 2385 m_freem(sc->rl_head); 2386 sc->rl_head = sc->rl_tail = NULL; 2387 } 2388 2389 /* Free the TX list buffers. */ 2390 2391 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2392 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2393 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2394 sc->rl_ldata.rl_tx_dmamap[i]); 2395 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2396 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2397 } 2398 } 2399 2400 /* Free the RX list buffers. */ 2401 2402 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2403 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2404 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2405 sc->rl_ldata.rl_rx_dmamap[i]); 2406 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2407 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2408 } 2409 } 2410 2411 RL_UNLOCK(sc); 2412 return; 2413} 2414 2415/* 2416 * Device suspend routine. Stop the interface and save some PCI 2417 * settings in case the BIOS doesn't restore them properly on 2418 * resume. 2419 */ 2420static int 2421re_suspend(dev) 2422 device_t dev; 2423{ 2424#ifndef BURN_BRIDGES 2425 register int i; 2426#endif 2427 struct rl_softc *sc; 2428 2429 sc = device_get_softc(dev); 2430 2431 re_stop(sc); 2432 2433#ifndef BURN_BRIDGES 2434 for (i = 0; i < 5; i++) 2435 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2436 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2437 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2438 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2439 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2440#endif 2441 2442 sc->suspended = 1; 2443 2444 return (0); 2445} 2446 2447/* 2448 * Device resume routine. Restore some PCI settings in case the BIOS 2449 * doesn't, re-enable busmastering, and restart the interface if 2450 * appropriate. 2451 */ 2452static int 2453re_resume(dev) 2454 device_t dev; 2455{ 2456#ifndef BURN_BRIDGES 2457 register int i; 2458#endif 2459 struct rl_softc *sc; 2460 struct ifnet *ifp; 2461 2462 sc = device_get_softc(dev); 2463 ifp = &sc->arpcom.ac_if; 2464 2465#ifndef BURN_BRIDGES 2466 /* better way to do this? */ 2467 for (i = 0; i < 5; i++) 2468 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2469 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2470 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2471 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2472 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2473 2474 /* reenable busmastering */ 2475 pci_enable_busmaster(dev); 2476 pci_enable_io(dev, RL_RES); 2477#endif 2478 2479 /* reinitialize interface if necessary */ 2480 if (ifp->if_flags & IFF_UP) 2481 re_init(sc); 2482 2483 sc->suspended = 0; 2484 2485 return (0); 2486} 2487 2488/* 2489 * Stop all chip I/O so that the kernel's probe routines don't 2490 * get confused by errant DMAs when rebooting. 2491 */ 2492static void 2493re_shutdown(dev) 2494 device_t dev; 2495{ 2496 struct rl_softc *sc; 2497 2498 sc = device_get_softc(dev); 2499 2500 re_stop(sc); 2501 2502 return; 2503} 2504