if_re.c revision 121816
1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 35 * 36 * Written by Bill Paul <wpaul@windriver.com> 37 * Senior Networking Software Engineer 38 * Wind River Systems 39 */ 40 41/* 42 * This driver is designed to support RealTek's next generation of 43 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 44 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 45 * and the RTL8110S. 46 * 47 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 48 * with the older 8139 family, however it also supports a special 49 * C+ mode of operation that provides several new performance enhancing 50 * features. These include: 51 * 52 * o Descriptor based DMA mechanism. Each descriptor represents 53 * a single packet fragment. Data buffers may be aligned on 54 * any byte boundary. 55 * 56 * o 64-bit DMA 57 * 58 * o TCP/IP checksum offload for both RX and TX 59 * 60 * o High and normal priority transmit DMA rings 61 * 62 * o VLAN tag insertion and extraction 63 * 64 * o TCP large send (segmentation offload) 65 * 66 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 67 * programming API is fairly straightforward. The RX filtering, EEPROM 68 * access and PHY access is the same as it is on the older 8139 series 69 * chips. 70 * 71 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 72 * same programming API and feature set as the 8139C+ with the following 73 * differences and additions: 74 * 75 * o 1000Mbps mode 76 * 77 * o Jumbo frames 78 * 79 * o GMII and TBI ports/registers for interfacing with copper 80 * or fiber PHYs 81 * 82 * o RX and TX DMA rings can have up to 1024 descriptors 83 * (the 8139C+ allows a maximum of 64) 84 * 85 * o Slight differences in register layout from the 8139C+ 86 * 87 * The TX start and timer interrupt registers are at different locations 88 * on the 8169 than they are on the 8139C+. Also, the status word in the 89 * RX descriptor has a slightly different bit layout. The 8169 does not 90 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 91 * copper gigE PHY. 92 * 93 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 94 * (the 'S' stands for 'single-chip'). These devices have the same 95 * programming API as the older 8169, but also have some vendor-specific 96 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 97 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 98 * 99 * This driver takes advantage of the RX and TX checksum offload and 100 * VLAN tag insertion/extraction features. It also implements TX 101 * interrupt moderation using the timer interrupt registers, which 102 * significantly reduces TX interrupt load. There is also support 103 * for jumbo frames, however the 8169/8169S/8110S can not transmit 104 * jumbo frames larger than 7.5K, so the max MTU possible with this 105 * driver is 7500 bytes. 106 */ 107 108#include <sys/cdefs.h> 109__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 121816 2003-10-31 18:32:15Z brooks $"); 110 111#include <sys/param.h> 112#include <sys/endian.h> 113#include <sys/systm.h> 114#include <sys/sockio.h> 115#include <sys/mbuf.h> 116#include <sys/malloc.h> 117#include <sys/kernel.h> 118#include <sys/socket.h> 119 120#include <net/if.h> 121#include <net/if_arp.h> 122#include <net/ethernet.h> 123#include <net/if_dl.h> 124#include <net/if_media.h> 125#include <net/if_vlan_var.h> 126 127#include <net/bpf.h> 128 129#include <machine/bus_pio.h> 130#include <machine/bus_memio.h> 131#include <machine/bus.h> 132#include <machine/resource.h> 133#include <sys/bus.h> 134#include <sys/rman.h> 135 136#include <dev/mii/mii.h> 137#include <dev/mii/miivar.h> 138 139#include <dev/pci/pcireg.h> 140#include <dev/pci/pcivar.h> 141 142MODULE_DEPEND(re, pci, 1, 1, 1); 143MODULE_DEPEND(re, ether, 1, 1, 1); 144MODULE_DEPEND(re, miibus, 1, 1, 1); 145 146/* "controller miibus0" required. See GENERIC if you get errors here. */ 147#include "miibus_if.h" 148 149/* 150 * Default to using PIO access for this driver. 151 */ 152#define RE_USEIOSPACE 153 154#include <pci/if_rlreg.h> 155 156#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 157 158/* 159 * Various supported device vendors/types and their names. 160 */ 161static struct rl_type re_devs[] = { 162 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 163 "RealTek 8139C+ 10/100BaseTX" }, 164 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 165 "RealTek 8169 Gigabit Ethernet" }, 166 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 167 "RealTek 8169S Single-chip Gigabit Ethernet" }, 168 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 169 "RealTek 8110S Single-chip Gigabit Ethernet" }, 170 { 0, 0, 0, NULL } 171}; 172 173static struct rl_hwrev re_hwrevs[] = { 174 { RL_HWREV_8139, RL_8139, "" }, 175 { RL_HWREV_8139A, RL_8139, "A" }, 176 { RL_HWREV_8139AG, RL_8139, "A-G" }, 177 { RL_HWREV_8139B, RL_8139, "B" }, 178 { RL_HWREV_8130, RL_8139, "8130" }, 179 { RL_HWREV_8139C, RL_8139, "C" }, 180 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 181 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 182 { RL_HWREV_8169, RL_8169, "8169"}, 183 { RL_HWREV_8169S, RL_8169, "8169S"}, 184 { RL_HWREV_8110S, RL_8169, "8110S"}, 185 { RL_HWREV_8100, RL_8139, "8100"}, 186 { RL_HWREV_8101, RL_8139, "8101"}, 187 { 0, 0, NULL } 188}; 189 190static int re_probe (device_t); 191static int re_attach (device_t); 192static int re_detach (device_t); 193 194static int re_encap (struct rl_softc *, struct mbuf *, int *); 195 196static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 197static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 198 bus_size_t, int); 199static int re_allocmem (device_t, struct rl_softc *); 200static int re_newbuf (struct rl_softc *, int, struct mbuf *); 201static int re_rx_list_init (struct rl_softc *); 202static int re_tx_list_init (struct rl_softc *); 203static void re_rxeof (struct rl_softc *); 204static void re_txeof (struct rl_softc *); 205static void re_intr (void *); 206static void re_tick (void *); 207static void re_start (struct ifnet *); 208static int re_ioctl (struct ifnet *, u_long, caddr_t); 209static void re_init (void *); 210static void re_stop (struct rl_softc *); 211static void re_watchdog (struct ifnet *); 212static int re_suspend (device_t); 213static int re_resume (device_t); 214static void re_shutdown (device_t); 215static int re_ifmedia_upd (struct ifnet *); 216static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 217 218static void re_eeprom_putbyte (struct rl_softc *, int); 219static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 220static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 221static int re_gmii_readreg (device_t, int, int); 222static int re_gmii_writereg (device_t, int, int, int); 223 224static int re_miibus_readreg (device_t, int, int); 225static int re_miibus_writereg (device_t, int, int, int); 226static void re_miibus_statchg (device_t); 227 228static u_int8_t re_calchash (caddr_t); 229static void re_setmulti (struct rl_softc *); 230static void re_reset (struct rl_softc *); 231 232static int re_diag (struct rl_softc *); 233 234#ifdef RE_USEIOSPACE 235#define RL_RES SYS_RES_IOPORT 236#define RL_RID RL_PCI_LOIO 237#else 238#define RL_RES SYS_RES_MEMORY 239#define RL_RID RL_PCI_LOMEM 240#endif 241 242static device_method_t re_methods[] = { 243 /* Device interface */ 244 DEVMETHOD(device_probe, re_probe), 245 DEVMETHOD(device_attach, re_attach), 246 DEVMETHOD(device_detach, re_detach), 247 DEVMETHOD(device_suspend, re_suspend), 248 DEVMETHOD(device_resume, re_resume), 249 DEVMETHOD(device_shutdown, re_shutdown), 250 251 /* bus interface */ 252 DEVMETHOD(bus_print_child, bus_generic_print_child), 253 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 254 255 /* MII interface */ 256 DEVMETHOD(miibus_readreg, re_miibus_readreg), 257 DEVMETHOD(miibus_writereg, re_miibus_writereg), 258 DEVMETHOD(miibus_statchg, re_miibus_statchg), 259 260 { 0, 0 } 261}; 262 263static driver_t re_driver = { 264 "re", 265 re_methods, 266 sizeof(struct rl_softc) 267}; 268 269static devclass_t re_devclass; 270 271DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 272DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 273DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 274 275#define EE_SET(x) \ 276 CSR_WRITE_1(sc, RL_EECMD, \ 277 CSR_READ_1(sc, RL_EECMD) | x) 278 279#define EE_CLR(x) \ 280 CSR_WRITE_1(sc, RL_EECMD, \ 281 CSR_READ_1(sc, RL_EECMD) & ~x) 282 283/* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286static void 287re_eeprom_putbyte(sc, addr) 288 struct rl_softc *sc; 289 int addr; 290{ 291 register int d, i; 292 293 d = addr | sc->rl_eecmd_read; 294 295 /* 296 * Feed in each bit and strobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 EE_SET(RL_EE_DATAIN); 301 } else { 302 EE_CLR(RL_EE_DATAIN); 303 } 304 DELAY(100); 305 EE_SET(RL_EE_CLK); 306 DELAY(150); 307 EE_CLR(RL_EE_CLK); 308 DELAY(100); 309 } 310 311 return; 312} 313 314/* 315 * Read a word of data stored in the EEPROM at address 'addr.' 316 */ 317static void 318re_eeprom_getword(sc, addr, dest) 319 struct rl_softc *sc; 320 int addr; 321 u_int16_t *dest; 322{ 323 register int i; 324 u_int16_t word = 0; 325 326 /* Enter EEPROM access mode. */ 327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 328 329 /* 330 * Send address of word we want to read. 331 */ 332 re_eeprom_putbyte(sc, addr); 333 334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 335 336 /* 337 * Start reading bits from EEPROM. 338 */ 339 for (i = 0x8000; i; i >>= 1) { 340 EE_SET(RL_EE_CLK); 341 DELAY(100); 342 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 343 word |= i; 344 EE_CLR(RL_EE_CLK); 345 DELAY(100); 346 } 347 348 /* Turn off EEPROM access mode. */ 349 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 350 351 *dest = word; 352 353 return; 354} 355 356/* 357 * Read a sequence of words from the EEPROM. 358 */ 359static void 360re_read_eeprom(sc, dest, off, cnt, swap) 361 struct rl_softc *sc; 362 caddr_t dest; 363 int off; 364 int cnt; 365 int swap; 366{ 367 int i; 368 u_int16_t word = 0, *ptr; 369 370 for (i = 0; i < cnt; i++) { 371 re_eeprom_getword(sc, off + i, &word); 372 ptr = (u_int16_t *)(dest + (i * 2)); 373 if (swap) 374 *ptr = ntohs(word); 375 else 376 *ptr = word; 377 } 378 379 return; 380} 381 382static int 383re_gmii_readreg(dev, phy, reg) 384 device_t dev; 385 int phy, reg; 386{ 387 struct rl_softc *sc; 388 u_int32_t rval; 389 int i; 390 391 if (phy != 1) 392 return(0); 393 394 sc = device_get_softc(dev); 395 396 /* Let the rgephy driver read the GMEDIASTAT register */ 397 398 if (reg == RL_GMEDIASTAT) { 399 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 400 return(rval); 401 } 402 403 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 404 DELAY(1000); 405 406 for (i = 0; i < RL_TIMEOUT; i++) { 407 rval = CSR_READ_4(sc, RL_PHYAR); 408 if (rval & RL_PHYAR_BUSY) 409 break; 410 DELAY(100); 411 } 412 413 if (i == RL_TIMEOUT) { 414 printf ("re%d: PHY read failed\n", sc->rl_unit); 415 return (0); 416 } 417 418 return (rval & RL_PHYAR_PHYDATA); 419} 420 421static int 422re_gmii_writereg(dev, phy, reg, data) 423 device_t dev; 424 int phy, reg, data; 425{ 426 struct rl_softc *sc; 427 u_int32_t rval; 428 int i; 429 430 sc = device_get_softc(dev); 431 432 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 433 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 434 DELAY(1000); 435 436 for (i = 0; i < RL_TIMEOUT; i++) { 437 rval = CSR_READ_4(sc, RL_PHYAR); 438 if (!(rval & RL_PHYAR_BUSY)) 439 break; 440 DELAY(100); 441 } 442 443 if (i == RL_TIMEOUT) { 444 printf ("re%d: PHY write failed\n", sc->rl_unit); 445 return (0); 446 } 447 448 return (0); 449} 450 451static int 452re_miibus_readreg(dev, phy, reg) 453 device_t dev; 454 int phy, reg; 455{ 456 struct rl_softc *sc; 457 u_int16_t rval = 0; 458 u_int16_t re8139_reg = 0; 459 460 sc = device_get_softc(dev); 461 RL_LOCK(sc); 462 463 if (sc->rl_type == RL_8169) { 464 rval = re_gmii_readreg(dev, phy, reg); 465 RL_UNLOCK(sc); 466 return (rval); 467 } 468 469 /* Pretend the internal PHY is only at address 0 */ 470 if (phy) { 471 RL_UNLOCK(sc); 472 return(0); 473 } 474 switch(reg) { 475 case MII_BMCR: 476 re8139_reg = RL_BMCR; 477 break; 478 case MII_BMSR: 479 re8139_reg = RL_BMSR; 480 break; 481 case MII_ANAR: 482 re8139_reg = RL_ANAR; 483 break; 484 case MII_ANER: 485 re8139_reg = RL_ANER; 486 break; 487 case MII_ANLPAR: 488 re8139_reg = RL_LPAR; 489 break; 490 case MII_PHYIDR1: 491 case MII_PHYIDR2: 492 RL_UNLOCK(sc); 493 return(0); 494 /* 495 * Allow the rlphy driver to read the media status 496 * register. If we have a link partner which does not 497 * support NWAY, this is the register which will tell 498 * us the results of parallel detection. 499 */ 500 case RL_MEDIASTAT: 501 rval = CSR_READ_1(sc, RL_MEDIASTAT); 502 RL_UNLOCK(sc); 503 return(rval); 504 default: 505 printf("re%d: bad phy register\n", sc->rl_unit); 506 RL_UNLOCK(sc); 507 return(0); 508 } 509 rval = CSR_READ_2(sc, re8139_reg); 510 RL_UNLOCK(sc); 511 return(rval); 512} 513 514static int 515re_miibus_writereg(dev, phy, reg, data) 516 device_t dev; 517 int phy, reg, data; 518{ 519 struct rl_softc *sc; 520 u_int16_t re8139_reg = 0; 521 int rval = 0; 522 523 sc = device_get_softc(dev); 524 RL_LOCK(sc); 525 526 if (sc->rl_type == RL_8169) { 527 rval = re_gmii_writereg(dev, phy, reg, data); 528 RL_UNLOCK(sc); 529 return (rval); 530 } 531 532 /* Pretend the internal PHY is only at address 0 */ 533 if (phy) { 534 RL_UNLOCK(sc); 535 return(0); 536 } 537 switch(reg) { 538 case MII_BMCR: 539 re8139_reg = RL_BMCR; 540 break; 541 case MII_BMSR: 542 re8139_reg = RL_BMSR; 543 break; 544 case MII_ANAR: 545 re8139_reg = RL_ANAR; 546 break; 547 case MII_ANER: 548 re8139_reg = RL_ANER; 549 break; 550 case MII_ANLPAR: 551 re8139_reg = RL_LPAR; 552 break; 553 case MII_PHYIDR1: 554 case MII_PHYIDR2: 555 RL_UNLOCK(sc); 556 return(0); 557 break; 558 default: 559 printf("re%d: bad phy register\n", sc->rl_unit); 560 RL_UNLOCK(sc); 561 return(0); 562 } 563 CSR_WRITE_2(sc, re8139_reg, data); 564 RL_UNLOCK(sc); 565 return(0); 566} 567 568static void 569re_miibus_statchg(dev) 570 device_t dev; 571{ 572 return; 573} 574 575/* 576 * Calculate CRC of a multicast group address, return the upper 6 bits. 577 */ 578static u_int8_t 579re_calchash(addr) 580 caddr_t addr; 581{ 582 u_int32_t crc, carry; 583 int i, j; 584 u_int8_t c; 585 586 /* Compute CRC for the address value. */ 587 crc = 0xFFFFFFFF; /* initial value */ 588 589 for (i = 0; i < 6; i++) { 590 c = *(addr + i); 591 for (j = 0; j < 8; j++) { 592 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 593 crc <<= 1; 594 c >>= 1; 595 if (carry) 596 crc = (crc ^ 0x04c11db6) | carry; 597 } 598 } 599 600 /* return the filter bit position */ 601 return(crc >> 26); 602} 603 604/* 605 * Program the 64-bit multicast hash filter. 606 */ 607static void 608re_setmulti(sc) 609 struct rl_softc *sc; 610{ 611 struct ifnet *ifp; 612 int h = 0; 613 u_int32_t hashes[2] = { 0, 0 }; 614 struct ifmultiaddr *ifma; 615 u_int32_t rxfilt; 616 int mcnt = 0; 617 618 ifp = &sc->arpcom.ac_if; 619 620 rxfilt = CSR_READ_4(sc, RL_RXCFG); 621 622 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 623 rxfilt |= RL_RXCFG_RX_MULTI; 624 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 625 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 626 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 627 return; 628 } 629 630 /* first, zot all the existing hash bits */ 631 CSR_WRITE_4(sc, RL_MAR0, 0); 632 CSR_WRITE_4(sc, RL_MAR4, 0); 633 634 /* now program new ones */ 635 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 636 if (ifma->ifma_addr->sa_family != AF_LINK) 637 continue; 638 h = re_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 639 if (h < 32) 640 hashes[0] |= (1 << h); 641 else 642 hashes[1] |= (1 << (h - 32)); 643 mcnt++; 644 } 645 646 if (mcnt) 647 rxfilt |= RL_RXCFG_RX_MULTI; 648 else 649 rxfilt &= ~RL_RXCFG_RX_MULTI; 650 651 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 652 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 653 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 654 655 return; 656} 657 658static void 659re_reset(sc) 660 struct rl_softc *sc; 661{ 662 register int i; 663 664 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 665 666 for (i = 0; i < RL_TIMEOUT; i++) { 667 DELAY(10); 668 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 669 break; 670 } 671 if (i == RL_TIMEOUT) 672 printf("re%d: reset never completed!\n", sc->rl_unit); 673 674 CSR_WRITE_1(sc, 0x82, 1); 675 676 return; 677} 678 679/* 680 * The following routine is designed to test for a defect on some 681 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 682 * lines connected to the bus, however for a 32-bit only card, they 683 * should be pulled high. The result of this defect is that the 684 * NIC will not work right if you plug it into a 64-bit slot: DMA 685 * operations will be done with 64-bit transfers, which will fail 686 * because the 64-bit data lines aren't connected. 687 * 688 * There's no way to work around this (short of talking a soldering 689 * iron to the board), however we can detect it. The method we use 690 * here is to put the NIC into digital loopback mode, set the receiver 691 * to promiscuous mode, and then try to send a frame. We then compare 692 * the frame data we sent to what was received. If the data matches, 693 * then the NIC is working correctly, otherwise we know the user has 694 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 695 * slot. In the latter case, there's no way the NIC can work correctly, 696 * so we print out a message on the console and abort the device attach. 697 */ 698 699static int 700re_diag(sc) 701 struct rl_softc *sc; 702{ 703 struct ifnet *ifp = &sc->arpcom.ac_if; 704 struct mbuf *m0; 705 struct ether_header *eh; 706 struct rl_desc *cur_rx; 707 u_int16_t status; 708 u_int32_t rxstat; 709 int total_len, i, error = 0; 710 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 711 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 712 713 /* Allocate a single mbuf */ 714 715 MGETHDR(m0, M_DONTWAIT, MT_DATA); 716 if (m0 == NULL) 717 return(ENOBUFS); 718 719 /* 720 * Initialize the NIC in test mode. This sets the chip up 721 * so that it can send and receive frames, but performs the 722 * following special functions: 723 * - Puts receiver in promiscuous mode 724 * - Enables digital loopback mode 725 * - Leaves interrupts turned off 726 */ 727 728 ifp->if_flags |= IFF_PROMISC; 729 sc->rl_testmode = 1; 730 re_init(sc); 731 re_stop(sc); 732 DELAY(100000); 733 re_init(sc); 734 735 /* Put some data in the mbuf */ 736 737 eh = mtod(m0, struct ether_header *); 738 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 739 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 740 eh->ether_type = htons(ETHERTYPE_IP); 741 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 742 743 /* 744 * Queue the packet, start transmission. 745 * Note: IF_HANDOFF() ultimately calls re_start() for us. 746 */ 747 748 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 749 IF_HANDOFF(&ifp->if_snd, m0, ifp); 750 m0 = NULL; 751 752 /* Wait for it to propagate through the chip */ 753 754 DELAY(100000); 755 for (i = 0; i < RL_TIMEOUT; i++) { 756 status = CSR_READ_2(sc, RL_ISR); 757 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 758 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 759 break; 760 DELAY(10); 761 } 762 763 if (i == RL_TIMEOUT) { 764 printf("re%d: diagnostic failed, failed to receive packet " 765 "in loopback mode\n", sc->rl_unit); 766 error = EIO; 767 goto done; 768 } 769 770 /* 771 * The packet should have been dumped into the first 772 * entry in the RX DMA ring. Grab it from there. 773 */ 774 775 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 776 sc->rl_ldata.rl_rx_list_map, 777 BUS_DMASYNC_POSTREAD); 778 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 779 sc->rl_ldata.rl_rx_dmamap[0], 780 BUS_DMASYNC_POSTWRITE); 781 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 782 sc->rl_ldata.rl_rx_dmamap[0]); 783 784 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 785 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 786 eh = mtod(m0, struct ether_header *); 787 788 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 789 total_len = RL_RXBYTES(cur_rx); 790 rxstat = le32toh(cur_rx->rl_cmdstat); 791 792 if (total_len != ETHER_MIN_LEN) { 793 printf("re%d: diagnostic failed, received short packet\n", 794 sc->rl_unit); 795 error = EIO; 796 goto done; 797 } 798 799 /* Test that the received packet data matches what we sent. */ 800 801 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 802 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 803 ntohs(eh->ether_type) != ETHERTYPE_IP) { 804 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 805 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 806 dst, ":", src, ":", ETHERTYPE_IP); 807 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 808 eh->ether_dhost, ":", eh->ether_shost, ":", 809 ntohs(eh->ether_type)); 810 printf("re%d: You may have a defective 32-bit NIC plugged " 811 "into a 64-bit PCI slot.\n", sc->rl_unit); 812 printf("re%d: Please re-install the NIC in a 32-bit slot " 813 "for proper operation.\n", sc->rl_unit); 814 printf("re%d: Read the re(4) man page for more details.\n", 815 sc->rl_unit); 816 error = EIO; 817 } 818 819done: 820 /* Turn interface off, release resources */ 821 822 sc->rl_testmode = 0; 823 ifp->if_flags &= ~IFF_PROMISC; 824 re_stop(sc); 825 if (m0 != NULL) 826 m_freem(m0); 827 828 return (error); 829} 830 831/* 832 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 833 * IDs against our list and return a device name if we find a match. 834 */ 835static int 836re_probe(dev) 837 device_t dev; 838{ 839 struct rl_type *t; 840 struct rl_softc *sc; 841 int rid; 842 u_int32_t hwrev; 843 844 t = re_devs; 845 sc = device_get_softc(dev); 846 847 while(t->rl_name != NULL) { 848 if ((pci_get_vendor(dev) == t->rl_vid) && 849 (pci_get_device(dev) == t->rl_did)) { 850 851 /* 852 * Temporarily map the I/O space 853 * so we can read the chip ID register. 854 */ 855 rid = RL_RID; 856 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 857 0, ~0, 1, RF_ACTIVE); 858 if (sc->rl_res == NULL) { 859 device_printf(dev, 860 "couldn't map ports/memory\n"); 861 return(ENXIO); 862 } 863 sc->rl_btag = rman_get_bustag(sc->rl_res); 864 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 865 mtx_init(&sc->rl_mtx, 866 device_get_nameunit(dev), 867 MTX_NETWORK_LOCK, MTX_DEF); 868 RL_LOCK(sc); 869 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 870 bus_release_resource(dev, RL_RES, 871 RL_RID, sc->rl_res); 872 RL_UNLOCK(sc); 873 mtx_destroy(&sc->rl_mtx); 874 if (t->rl_basetype == hwrev) { 875 device_set_desc(dev, t->rl_name); 876 return(0); 877 } 878 } 879 t++; 880 } 881 882 return(ENXIO); 883} 884 885/* 886 * This routine takes the segment list provided as the result of 887 * a bus_dma_map_load() operation and assigns the addresses/lengths 888 * to RealTek DMA descriptors. This can be called either by the RX 889 * code or the TX code. In the RX case, we'll probably wind up mapping 890 * at most one segment. For the TX case, there could be any number of 891 * segments since TX packets may span multiple mbufs. In either case, 892 * if the number of segments is larger than the rl_maxsegs limit 893 * specified by the caller, we abort the mapping operation. Sadly, 894 * whoever designed the buffer mapping API did not provide a way to 895 * return an error from here, so we have to fake it a bit. 896 */ 897 898static void 899re_dma_map_desc(arg, segs, nseg, mapsize, error) 900 void *arg; 901 bus_dma_segment_t *segs; 902 int nseg; 903 bus_size_t mapsize; 904 int error; 905{ 906 struct rl_dmaload_arg *ctx; 907 struct rl_desc *d = NULL; 908 int i = 0, idx; 909 910 if (error) 911 return; 912 913 ctx = arg; 914 915 /* Signal error to caller if there's too many segments */ 916 if (nseg > ctx->rl_maxsegs) { 917 ctx->rl_maxsegs = 0; 918 return; 919 } 920 921 /* 922 * Map the segment array into descriptors. Note that we set the 923 * start-of-frame and end-of-frame markers for either TX or RX, but 924 * they really only have meaning in the TX case. (In the RX case, 925 * it's the chip that tells us where packets begin and end.) 926 * We also keep track of the end of the ring and set the 927 * end-of-ring bits as needed, and we set the ownership bits 928 * in all except the very first descriptor. (The caller will 929 * set this descriptor later when it start transmission or 930 * reception.) 931 */ 932 idx = ctx->rl_idx; 933 while(1) { 934 u_int32_t cmdstat; 935 d = &ctx->rl_ring[idx]; 936 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 937 ctx->rl_maxsegs = 0; 938 return; 939 } 940 cmdstat = segs[i].ds_len; 941 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 942 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 943 if (i == 0) 944 cmdstat |= RL_TDESC_CMD_SOF; 945 else 946 cmdstat |= RL_TDESC_CMD_OWN; 947 if (idx == (RL_RX_DESC_CNT - 1)) 948 cmdstat |= RL_TDESC_CMD_EOR; 949 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 950 i++; 951 if (i == nseg) 952 break; 953 RL_DESC_INC(idx); 954 } 955 956 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 957 ctx->rl_maxsegs = nseg; 958 ctx->rl_idx = idx; 959 960 return; 961} 962 963/* 964 * Map a single buffer address. 965 */ 966 967static void 968re_dma_map_addr(arg, segs, nseg, error) 969 void *arg; 970 bus_dma_segment_t *segs; 971 int nseg; 972 int error; 973{ 974 u_int32_t *addr; 975 976 if (error) 977 return; 978 979 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 980 addr = arg; 981 *addr = segs->ds_addr; 982 983 return; 984} 985 986static int 987re_allocmem(dev, sc) 988 device_t dev; 989 struct rl_softc *sc; 990{ 991 int error; 992 int nseg; 993 int i; 994 995 /* 996 * Allocate map for RX mbufs. 997 */ 998 nseg = 32; 999 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 1000 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1001 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 1002 NULL, NULL, &sc->rl_ldata.rl_mtag); 1003 if (error) { 1004 device_printf(dev, "could not allocate dma tag\n"); 1005 return (ENOMEM); 1006 } 1007 1008 /* 1009 * Allocate map for TX descriptor list. 1010 */ 1011 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1012 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1013 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1014 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1015 if (error) { 1016 device_printf(dev, "could not allocate dma tag\n"); 1017 return (ENOMEM); 1018 } 1019 1020 /* Allocate DMA'able memory for the TX ring */ 1021 1022 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1023 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1024 &sc->rl_ldata.rl_tx_list_map); 1025 if (error) 1026 return (ENOMEM); 1027 1028 /* Load the map for the TX ring. */ 1029 1030 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1031 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1032 RL_TX_LIST_SZ, re_dma_map_addr, 1033 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1034 1035 /* Create DMA maps for TX buffers */ 1036 1037 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1038 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1039 &sc->rl_ldata.rl_tx_dmamap[i]); 1040 if (error) { 1041 device_printf(dev, "can't create DMA map for TX\n"); 1042 return(ENOMEM); 1043 } 1044 } 1045 1046 /* 1047 * Allocate map for RX descriptor list. 1048 */ 1049 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1050 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1051 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1052 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1053 if (error) { 1054 device_printf(dev, "could not allocate dma tag\n"); 1055 return (ENOMEM); 1056 } 1057 1058 /* Allocate DMA'able memory for the RX ring */ 1059 1060 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1061 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1062 &sc->rl_ldata.rl_rx_list_map); 1063 if (error) 1064 return (ENOMEM); 1065 1066 /* Load the map for the RX ring. */ 1067 1068 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1069 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1070 RL_TX_LIST_SZ, re_dma_map_addr, 1071 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1072 1073 /* Create DMA maps for RX buffers */ 1074 1075 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1076 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1077 &sc->rl_ldata.rl_rx_dmamap[i]); 1078 if (error) { 1079 device_printf(dev, "can't create DMA map for RX\n"); 1080 return(ENOMEM); 1081 } 1082 } 1083 1084 return(0); 1085} 1086 1087/* 1088 * Attach the interface. Allocate softc structures, do ifmedia 1089 * setup and ethernet/BPF attach. 1090 */ 1091static int 1092re_attach(dev) 1093 device_t dev; 1094{ 1095 u_char eaddr[ETHER_ADDR_LEN]; 1096 u_int16_t as[3]; 1097 struct rl_softc *sc; 1098 struct ifnet *ifp; 1099 struct rl_hwrev *hw_rev; 1100 int hwrev; 1101 u_int16_t re_did = 0; 1102 int unit, error = 0, rid, i; 1103 1104 sc = device_get_softc(dev); 1105 unit = device_get_unit(dev); 1106 1107 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1108 MTX_DEF | MTX_RECURSE); 1109#ifndef BURN_BRIDGES 1110 /* 1111 * Handle power management nonsense. 1112 */ 1113 1114 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1115 u_int32_t iobase, membase, irq; 1116 1117 /* Save important PCI config data. */ 1118 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 1119 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 1120 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 1121 1122 /* Reset the power state. */ 1123 printf("re%d: chip is is in D%d power mode " 1124 "-- setting to D0\n", unit, 1125 pci_get_powerstate(dev)); 1126 1127 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1128 1129 /* Restore PCI config data. */ 1130 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 1131 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 1132 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 1133 } 1134#endif 1135 /* 1136 * Map control/status registers. 1137 */ 1138 pci_enable_busmaster(dev); 1139 1140 rid = RL_RID; 1141 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 1142 0, ~0, 1, RF_ACTIVE); 1143 1144 if (sc->rl_res == NULL) { 1145 printf ("re%d: couldn't map ports/memory\n", unit); 1146 error = ENXIO; 1147 goto fail; 1148 } 1149 1150 sc->rl_btag = rman_get_bustag(sc->rl_res); 1151 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1152 1153 /* Allocate interrupt */ 1154 rid = 0; 1155 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1156 RF_SHAREABLE | RF_ACTIVE); 1157 1158 if (sc->rl_irq == NULL) { 1159 printf("re%d: couldn't map interrupt\n", unit); 1160 error = ENXIO; 1161 goto fail; 1162 } 1163 1164 /* Reset the adapter. */ 1165 re_reset(sc); 1166 1167 hw_rev = re_hwrevs; 1168 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1169 while (hw_rev->rl_desc != NULL) { 1170 if (hw_rev->rl_rev == hwrev) { 1171 sc->rl_type = hw_rev->rl_type; 1172 break; 1173 } 1174 hw_rev++; 1175 } 1176 1177 if (sc->rl_type == RL_8169) { 1178 1179 /* Set RX length mask */ 1180 1181 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1182 1183 /* Force station address autoload from the EEPROM */ 1184 1185 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1186 for (i = 0; i < RL_TIMEOUT; i++) { 1187 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1188 break; 1189 DELAY(100); 1190 } 1191 if (i == RL_TIMEOUT) 1192 printf ("re%d: eeprom autoload timed out\n", unit); 1193 1194 for (i = 0; i < ETHER_ADDR_LEN; i++) 1195 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1196 } else { 1197 1198 /* Set RX length mask */ 1199 1200 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1201 1202 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1203 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1204 if (re_did != 0x8129) 1205 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1206 1207 /* 1208 * Get station address from the EEPROM. 1209 */ 1210 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1211 for (i = 0; i < 3; i++) { 1212 eaddr[(i * 2) + 0] = as[i] & 0xff; 1213 eaddr[(i * 2) + 1] = as[i] >> 8; 1214 } 1215 } 1216 1217 /* 1218 * A RealTek chip was detected. Inform the world. 1219 */ 1220 printf("re%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1221 1222 sc->rl_unit = unit; 1223 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1224 1225 /* 1226 * Allocate the parent bus DMA tag appropriate for PCI. 1227 */ 1228#define RL_NSEG_NEW 32 1229 error = bus_dma_tag_create(NULL, /* parent */ 1230 1, 0, /* alignment, boundary */ 1231 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1232 BUS_SPACE_MAXADDR, /* highaddr */ 1233 NULL, NULL, /* filter, filterarg */ 1234 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1235 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1236 BUS_DMA_ALLOCNOW, /* flags */ 1237 NULL, NULL, /* lockfunc, lockarg */ 1238 &sc->rl_parent_tag); 1239 if (error) 1240 goto fail; 1241 1242 error = re_allocmem(dev, sc); 1243 1244 if (error) 1245 goto fail; 1246 1247 /* Do MII setup */ 1248 if (mii_phy_probe(dev, &sc->rl_miibus, 1249 re_ifmedia_upd, re_ifmedia_sts)) { 1250 printf("re%d: MII without any phy!\n", sc->rl_unit); 1251 error = ENXIO; 1252 goto fail; 1253 } 1254 1255 ifp = &sc->arpcom.ac_if; 1256 ifp->if_softc = sc; 1257 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1258 ifp->if_mtu = ETHERMTU; 1259 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1260 ifp->if_ioctl = re_ioctl; 1261 ifp->if_output = ether_output; 1262 ifp->if_capabilities = IFCAP_VLAN_MTU; 1263 ifp->if_start = re_start; 1264 ifp->if_hwassist = RE_CSUM_FEATURES; 1265 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1266 ifp->if_watchdog = re_watchdog; 1267 ifp->if_init = re_init; 1268 if (sc->rl_type == RL_8169) 1269 ifp->if_baudrate = 1000000000; 1270 else 1271 ifp->if_baudrate = 100000000; 1272 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; 1273 ifp->if_capenable = ifp->if_capabilities; 1274 1275 callout_handle_init(&sc->rl_stat_ch); 1276 1277 /* 1278 * Call MI attach routine. 1279 */ 1280 ether_ifattach(ifp, eaddr); 1281 1282 /* Perform hardware diagnostic. */ 1283 error = re_diag(sc); 1284 1285 if (error) { 1286 printf("re%d: attach aborted due to hardware diag failure\n", 1287 unit); 1288 ether_ifdetach(ifp); 1289 goto fail; 1290 } 1291 1292 /* Hook interrupt last to avoid having to lock softc */ 1293 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1294 re_intr, sc, &sc->rl_intrhand); 1295 1296 if (error) { 1297 printf("re%d: couldn't set up irq\n", unit); 1298 ether_ifdetach(ifp); 1299 goto fail; 1300 } 1301 1302fail: 1303 if (error) 1304 re_detach(dev); 1305 1306 return (error); 1307} 1308 1309/* 1310 * Shutdown hardware and free up resources. This can be called any 1311 * time after the mutex has been initialized. It is called in both 1312 * the error case in attach and the normal detach case so it needs 1313 * to be careful about only freeing resources that have actually been 1314 * allocated. 1315 */ 1316static int 1317re_detach(dev) 1318 device_t dev; 1319{ 1320 struct rl_softc *sc; 1321 struct ifnet *ifp; 1322 int i; 1323 1324 sc = device_get_softc(dev); 1325 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1326 RL_LOCK(sc); 1327 ifp = &sc->arpcom.ac_if; 1328 1329 /* These should only be active if attach succeeded */ 1330 if (device_is_attached(dev)) { 1331 re_stop(sc); 1332 /* 1333 * Force off the IFF_UP flag here, in case someone 1334 * still had a BPF descriptor attached to this 1335 * interface. If they do, ether_ifattach() will cause 1336 * the BPF code to try and clear the promisc mode 1337 * flag, which will bubble down to re_ioctl(), 1338 * which will try to call re_init() again. This will 1339 * turn the NIC back on and restart the MII ticker, 1340 * which will panic the system when the kernel tries 1341 * to invoke the re_tick() function that isn't there 1342 * anymore. 1343 */ 1344 ifp->if_flags &= ~IFF_UP; 1345 ether_ifdetach(ifp); 1346 } 1347 if (sc->rl_miibus) 1348 device_delete_child(dev, sc->rl_miibus); 1349 bus_generic_detach(dev); 1350 1351 if (sc->rl_intrhand) 1352 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1353 if (sc->rl_irq) 1354 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1355 if (sc->rl_res) 1356 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1357 1358 1359 /* Unload and free the RX DMA ring memory and map */ 1360 1361 if (sc->rl_ldata.rl_rx_list_tag) { 1362 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1363 sc->rl_ldata.rl_rx_list_map); 1364 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1365 sc->rl_ldata.rl_rx_list, 1366 sc->rl_ldata.rl_rx_list_map); 1367 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1368 } 1369 1370 /* Unload and free the TX DMA ring memory and map */ 1371 1372 if (sc->rl_ldata.rl_tx_list_tag) { 1373 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1374 sc->rl_ldata.rl_tx_list_map); 1375 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1376 sc->rl_ldata.rl_tx_list, 1377 sc->rl_ldata.rl_tx_list_map); 1378 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1379 } 1380 1381 /* Destroy all the RX and TX buffer maps */ 1382 1383 if (sc->rl_ldata.rl_mtag) { 1384 for (i = 0; i < RL_TX_DESC_CNT; i++) 1385 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1386 sc->rl_ldata.rl_tx_dmamap[i]); 1387 for (i = 0; i < RL_RX_DESC_CNT; i++) 1388 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1389 sc->rl_ldata.rl_rx_dmamap[i]); 1390 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1391 } 1392 1393 /* Unload and free the stats buffer and map */ 1394 1395 if (sc->rl_ldata.rl_stag) { 1396 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1397 sc->rl_ldata.rl_rx_list_map); 1398 bus_dmamem_free(sc->rl_ldata.rl_stag, 1399 sc->rl_ldata.rl_stats, 1400 sc->rl_ldata.rl_smap); 1401 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1402 } 1403 1404 if (sc->rl_parent_tag) 1405 bus_dma_tag_destroy(sc->rl_parent_tag); 1406 1407 RL_UNLOCK(sc); 1408 mtx_destroy(&sc->rl_mtx); 1409 1410 return(0); 1411} 1412 1413static int 1414re_newbuf(sc, idx, m) 1415 struct rl_softc *sc; 1416 int idx; 1417 struct mbuf *m; 1418{ 1419 struct rl_dmaload_arg arg; 1420 struct mbuf *n = NULL; 1421 int error; 1422 1423 if (m == NULL) { 1424 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1425 if (n == NULL) 1426 return(ENOBUFS); 1427 m = n; 1428 } else 1429 m->m_data = m->m_ext.ext_buf; 1430 1431 /* 1432 * Initialize mbuf length fields and fixup 1433 * alignment so that the frame payload is 1434 * longword aligned. 1435 */ 1436 m->m_len = m->m_pkthdr.len = MCLBYTES; 1437 m_adj(m, ETHER_ALIGN); 1438 1439 arg.sc = sc; 1440 arg.rl_idx = idx; 1441 arg.rl_maxsegs = 1; 1442 arg.rl_flags = 0; 1443 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1444 1445 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1446 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1447 &arg, BUS_DMA_NOWAIT); 1448 if (error || arg.rl_maxsegs != 1) { 1449 if (n != NULL) 1450 m_freem(n); 1451 return (ENOMEM); 1452 } 1453 1454 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1455 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1456 1457 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1458 sc->rl_ldata.rl_rx_dmamap[idx], 1459 BUS_DMASYNC_PREREAD); 1460 1461 return(0); 1462} 1463 1464static int 1465re_tx_list_init(sc) 1466 struct rl_softc *sc; 1467{ 1468 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1469 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1470 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1471 1472 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1473 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1474 sc->rl_ldata.rl_tx_prodidx = 0; 1475 sc->rl_ldata.rl_tx_considx = 0; 1476 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1477 1478 return(0); 1479} 1480 1481static int 1482re_rx_list_init(sc) 1483 struct rl_softc *sc; 1484{ 1485 int i; 1486 1487 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1488 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1489 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1490 1491 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1492 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1493 return(ENOBUFS); 1494 } 1495 1496 /* Flush the RX descriptors */ 1497 1498 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1499 sc->rl_ldata.rl_rx_list_map, 1500 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1501 1502 sc->rl_ldata.rl_rx_prodidx = 0; 1503 sc->rl_head = sc->rl_tail = NULL; 1504 1505 return(0); 1506} 1507 1508/* 1509 * RX handler for C+ and 8169. For the gigE chips, we support 1510 * the reception of jumbo frames that have been fragmented 1511 * across multiple 2K mbuf cluster buffers. 1512 */ 1513static void 1514re_rxeof(sc) 1515 struct rl_softc *sc; 1516{ 1517 struct mbuf *m; 1518 struct ifnet *ifp; 1519 int i, total_len; 1520 struct rl_desc *cur_rx; 1521 u_int32_t rxstat, rxvlan; 1522 1523 ifp = &sc->arpcom.ac_if; 1524 i = sc->rl_ldata.rl_rx_prodidx; 1525 1526 /* Invalidate the descriptor memory */ 1527 1528 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1529 sc->rl_ldata.rl_rx_list_map, 1530 BUS_DMASYNC_POSTREAD); 1531 1532 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1533 1534 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1535 m = sc->rl_ldata.rl_rx_mbuf[i]; 1536 total_len = RL_RXBYTES(cur_rx); 1537 rxstat = le32toh(cur_rx->rl_cmdstat); 1538 rxvlan = le32toh(cur_rx->rl_vlanctl); 1539 1540 /* Invalidate the RX mbuf and unload its map */ 1541 1542 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1543 sc->rl_ldata.rl_rx_dmamap[i], 1544 BUS_DMASYNC_POSTWRITE); 1545 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1546 sc->rl_ldata.rl_rx_dmamap[i]); 1547 1548 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1549 m->m_len = MCLBYTES - ETHER_ALIGN; 1550 if (sc->rl_head == NULL) 1551 sc->rl_head = sc->rl_tail = m; 1552 else { 1553 m->m_flags &= ~M_PKTHDR; 1554 sc->rl_tail->m_next = m; 1555 sc->rl_tail = m; 1556 } 1557 re_newbuf(sc, i, NULL); 1558 RL_DESC_INC(i); 1559 continue; 1560 } 1561 1562 /* 1563 * NOTE: for the 8139C+, the frame length field 1564 * is always 12 bits in size, but for the gigE chips, 1565 * it is 13 bits (since the max RX frame length is 16K). 1566 * Unfortunately, all 32 bits in the status word 1567 * were already used, so to make room for the extra 1568 * length bit, RealTek took out the 'frame alignment 1569 * error' bit and shifted the other status bits 1570 * over one slot. The OWN, EOR, FS and LS bits are 1571 * still in the same places. We have already extracted 1572 * the frame length and checked the OWN bit, so rather 1573 * than using an alternate bit mapping, we shift the 1574 * status bits one space to the right so we can evaluate 1575 * them using the 8169 status as though it was in the 1576 * same format as that of the 8139C+. 1577 */ 1578 if (sc->rl_type == RL_8169) 1579 rxstat >>= 1; 1580 1581 if (rxstat & RL_RDESC_STAT_RXERRSUM) { 1582 ifp->if_ierrors++; 1583 /* 1584 * If this is part of a multi-fragment packet, 1585 * discard all the pieces. 1586 */ 1587 if (sc->rl_head != NULL) { 1588 m_freem(sc->rl_head); 1589 sc->rl_head = sc->rl_tail = NULL; 1590 } 1591 re_newbuf(sc, i, m); 1592 RL_DESC_INC(i); 1593 continue; 1594 } 1595 1596 /* 1597 * If allocating a replacement mbuf fails, 1598 * reload the current one. 1599 */ 1600 1601 if (re_newbuf(sc, i, NULL)) { 1602 ifp->if_ierrors++; 1603 if (sc->rl_head != NULL) { 1604 m_freem(sc->rl_head); 1605 sc->rl_head = sc->rl_tail = NULL; 1606 } 1607 re_newbuf(sc, i, m); 1608 RL_DESC_INC(i); 1609 continue; 1610 } 1611 1612 RL_DESC_INC(i); 1613 1614 if (sc->rl_head != NULL) { 1615 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1616 /* 1617 * Special case: if there's 4 bytes or less 1618 * in this buffer, the mbuf can be discarded: 1619 * the last 4 bytes is the CRC, which we don't 1620 * care about anyway. 1621 */ 1622 if (m->m_len <= ETHER_CRC_LEN) { 1623 sc->rl_tail->m_len -= 1624 (ETHER_CRC_LEN - m->m_len); 1625 m_freem(m); 1626 } else { 1627 m->m_len -= ETHER_CRC_LEN; 1628 m->m_flags &= ~M_PKTHDR; 1629 sc->rl_tail->m_next = m; 1630 } 1631 m = sc->rl_head; 1632 sc->rl_head = sc->rl_tail = NULL; 1633 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1634 } else 1635 m->m_pkthdr.len = m->m_len = 1636 (total_len - ETHER_CRC_LEN); 1637 1638 ifp->if_ipackets++; 1639 m->m_pkthdr.rcvif = ifp; 1640 1641 /* Do RX checksumming if enabled */ 1642 1643 if (ifp->if_capenable & IFCAP_RXCSUM) { 1644 1645 /* Check IP header checksum */ 1646 if (rxstat & RL_RDESC_STAT_PROTOID) 1647 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1648 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1649 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1650 1651 /* Check TCP/UDP checksum */ 1652 if ((RL_TCPPKT(rxstat) && 1653 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1654 (RL_UDPPKT(rxstat) && 1655 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1656 m->m_pkthdr.csum_flags |= 1657 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1658 m->m_pkthdr.csum_data = 0xffff; 1659 } 1660 } 1661 1662 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1663 VLAN_INPUT_TAG(ifp, m, 1664 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1665 (*ifp->if_input)(ifp, m); 1666 } 1667 1668 /* Flush the RX DMA ring */ 1669 1670 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1671 sc->rl_ldata.rl_rx_list_map, 1672 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1673 1674 sc->rl_ldata.rl_rx_prodidx = i; 1675 1676 return; 1677} 1678 1679static void 1680re_txeof(sc) 1681 struct rl_softc *sc; 1682{ 1683 struct ifnet *ifp; 1684 u_int32_t txstat; 1685 int idx; 1686 1687 ifp = &sc->arpcom.ac_if; 1688 idx = sc->rl_ldata.rl_tx_considx; 1689 1690 /* Invalidate the TX descriptor list */ 1691 1692 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1693 sc->rl_ldata.rl_tx_list_map, 1694 BUS_DMASYNC_POSTREAD); 1695 1696 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1697 1698 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1699 if (txstat & RL_TDESC_CMD_OWN) 1700 break; 1701 1702 /* 1703 * We only stash mbufs in the last descriptor 1704 * in a fragment chain, which also happens to 1705 * be the only place where the TX status bits 1706 * are valid. 1707 */ 1708 1709 if (txstat & RL_TDESC_CMD_EOF) { 1710 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1711 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1712 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1713 sc->rl_ldata.rl_tx_dmamap[idx]); 1714 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1715 RL_TDESC_STAT_COLCNT)) 1716 ifp->if_collisions++; 1717 if (txstat & RL_TDESC_STAT_TXERRSUM) 1718 ifp->if_oerrors++; 1719 else 1720 ifp->if_opackets++; 1721 } 1722 sc->rl_ldata.rl_tx_free++; 1723 RL_DESC_INC(idx); 1724 } 1725 1726 /* No changes made to the TX ring, so no flush needed */ 1727 1728 if (idx != sc->rl_ldata.rl_tx_considx) { 1729 sc->rl_ldata.rl_tx_considx = idx; 1730 ifp->if_flags &= ~IFF_OACTIVE; 1731 ifp->if_timer = 0; 1732 } 1733 1734 /* 1735 * If not all descriptors have been released reaped yet, 1736 * reload the timer so that we will eventually get another 1737 * interrupt that will cause us to re-enter this routine. 1738 * This is done in case the transmitter has gone idle. 1739 */ 1740 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1741 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1742 1743 return; 1744} 1745 1746static void 1747re_tick(xsc) 1748 void *xsc; 1749{ 1750 struct rl_softc *sc; 1751 struct mii_data *mii; 1752 1753 sc = xsc; 1754 RL_LOCK(sc); 1755 mii = device_get_softc(sc->rl_miibus); 1756 1757 mii_tick(mii); 1758 1759 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1760 RL_UNLOCK(sc); 1761 1762 return; 1763} 1764 1765#ifdef DEVICE_POLLING 1766static void 1767re_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1768{ 1769 struct rl_softc *sc = ifp->if_softc; 1770 1771 RL_LOCK(sc); 1772 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1773 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1774 goto done; 1775 } 1776 1777 sc->rxcycles = count; 1778 re_rxeof(sc); 1779 re_txeof(sc); 1780 1781 if (ifp->if_snd.ifq_head != NULL) 1782 (*ifp->if_start)(ifp); 1783 1784 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1785 u_int16_t status; 1786 1787 status = CSR_READ_2(sc, RL_ISR); 1788 if (status == 0xffff) 1789 goto done; 1790 if (status) 1791 CSR_WRITE_2(sc, RL_ISR, status); 1792 1793 /* 1794 * XXX check behaviour on receiver stalls. 1795 */ 1796 1797 if (status & RL_ISR_SYSTEM_ERR) { 1798 re_reset(sc); 1799 re_init(sc); 1800 } 1801 } 1802done: 1803 RL_UNLOCK(sc); 1804} 1805#endif /* DEVICE_POLLING */ 1806 1807static void 1808re_intr(arg) 1809 void *arg; 1810{ 1811 struct rl_softc *sc; 1812 struct ifnet *ifp; 1813 u_int16_t status; 1814 1815 sc = arg; 1816 1817 if (sc->suspended) { 1818 return; 1819 } 1820 1821 RL_LOCK(sc); 1822 ifp = &sc->arpcom.ac_if; 1823 1824 if (!(ifp->if_flags & IFF_UP)) { 1825 RL_UNLOCK(sc); 1826 return; 1827 } 1828 1829#ifdef DEVICE_POLLING 1830 if (ifp->if_flags & IFF_POLLING) 1831 goto done; 1832 if (ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1833 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1834 re_poll(ifp, 0, 1); 1835 goto done; 1836 } 1837#endif /* DEVICE_POLLING */ 1838 1839 for (;;) { 1840 1841 status = CSR_READ_2(sc, RL_ISR); 1842 /* If the card has gone away the read returns 0xffff. */ 1843 if (status == 0xffff) 1844 break; 1845 if (status) 1846 CSR_WRITE_2(sc, RL_ISR, status); 1847 1848 if ((status & RL_INTRS_CPLUS) == 0) 1849 break; 1850 1851 if (status & RL_ISR_RX_OK) 1852 re_rxeof(sc); 1853 1854 if (status & RL_ISR_RX_ERR) 1855 re_rxeof(sc); 1856 1857 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1858 (status & RL_ISR_TX_ERR) || 1859 (status & RL_ISR_TX_DESC_UNAVAIL)) 1860 re_txeof(sc); 1861 1862 if (status & RL_ISR_SYSTEM_ERR) { 1863 re_reset(sc); 1864 re_init(sc); 1865 } 1866 1867 if (status & RL_ISR_LINKCHG) { 1868 untimeout(re_tick, sc, sc->rl_stat_ch); 1869 re_tick(sc); 1870 } 1871 } 1872 1873 if (ifp->if_snd.ifq_head != NULL) 1874 (*ifp->if_start)(ifp); 1875 1876#ifdef DEVICE_POLLING 1877done: 1878#endif 1879 RL_UNLOCK(sc); 1880 1881 return; 1882} 1883 1884static int 1885re_encap(sc, m_head, idx) 1886 struct rl_softc *sc; 1887 struct mbuf *m_head; 1888 int *idx; 1889{ 1890 struct mbuf *m_new = NULL; 1891 struct rl_dmaload_arg arg; 1892 bus_dmamap_t map; 1893 int error; 1894 struct m_tag *mtag; 1895 1896 if (sc->rl_ldata.rl_tx_free <= 4) 1897 return(EFBIG); 1898 1899 /* 1900 * Set up checksum offload. Note: checksum offload bits must 1901 * appear in all descriptors of a multi-descriptor transmit 1902 * attempt. (This is according to testing done with an 8169 1903 * chip. I'm not sure if this is a requirement or a bug.) 1904 */ 1905 1906 arg.rl_flags = 0; 1907 1908 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1909 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1910 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1911 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1912 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1913 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1914 1915 arg.sc = sc; 1916 arg.rl_idx = *idx; 1917 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1918 if (arg.rl_maxsegs > 4) 1919 arg.rl_maxsegs -= 4; 1920 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1921 1922 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1923 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1924 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1925 1926 if (error && error != EFBIG) { 1927 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1928 return(ENOBUFS); 1929 } 1930 1931 /* Too many segments to map, coalesce into a single mbuf */ 1932 1933 if (error || arg.rl_maxsegs == 0) { 1934 m_new = m_defrag(m_head, M_DONTWAIT); 1935 if (m_new == NULL) 1936 return(1); 1937 else 1938 m_head = m_new; 1939 1940 arg.sc = sc; 1941 arg.rl_idx = *idx; 1942 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1943 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1944 1945 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1946 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1947 if (error) { 1948 printf("re%d: can't map mbuf (error %d)\n", 1949 sc->rl_unit, error); 1950 return(EFBIG); 1951 } 1952 } 1953 1954 /* 1955 * Insure that the map for this transmission 1956 * is placed at the array index of the last descriptor 1957 * in this chain. 1958 */ 1959 sc->rl_ldata.rl_tx_dmamap[*idx] = 1960 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1961 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1962 1963 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head; 1964 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1965 1966 /* 1967 * Set up hardware VLAN tagging. Note: vlan tag info must 1968 * appear in the first descriptor of a multi-descriptor 1969 * transmission attempt. 1970 */ 1971 1972 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1973 if (mtag != NULL) 1974 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1975 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1976 1977 /* Transfer ownership of packet to the chip. */ 1978 1979 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1980 htole32(RL_TDESC_CMD_OWN); 1981 if (*idx != arg.rl_idx) 1982 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1983 htole32(RL_TDESC_CMD_OWN); 1984 1985 RL_DESC_INC(arg.rl_idx); 1986 *idx = arg.rl_idx; 1987 1988 return(0); 1989} 1990 1991/* 1992 * Main transmit routine for C+ and gigE NICs. 1993 */ 1994 1995static void 1996re_start(ifp) 1997 struct ifnet *ifp; 1998{ 1999 struct rl_softc *sc; 2000 struct mbuf *m_head = NULL; 2001 int idx; 2002 2003 sc = ifp->if_softc; 2004 RL_LOCK(sc); 2005 2006 idx = sc->rl_ldata.rl_tx_prodidx; 2007 2008 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2009 IF_DEQUEUE(&ifp->if_snd, m_head); 2010 if (m_head == NULL) 2011 break; 2012 2013 if (re_encap(sc, m_head, &idx)) { 2014 IF_PREPEND(&ifp->if_snd, m_head); 2015 ifp->if_flags |= IFF_OACTIVE; 2016 break; 2017 } 2018 2019 /* 2020 * If there's a BPF listener, bounce a copy of this frame 2021 * to him. 2022 */ 2023 BPF_MTAP(ifp, m_head); 2024 } 2025 2026 /* Flush the TX descriptors */ 2027 2028 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2029 sc->rl_ldata.rl_tx_list_map, 2030 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2031 2032 sc->rl_ldata.rl_tx_prodidx = idx; 2033 2034 /* 2035 * RealTek put the TX poll request register in a different 2036 * location on the 8169 gigE chip. I don't know why. 2037 */ 2038 2039 if (sc->rl_type == RL_8169) 2040 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2041 else 2042 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2043 2044 /* 2045 * Use the countdown timer for interrupt moderation. 2046 * 'TX done' interrupts are disabled. Instead, we reset the 2047 * countdown timer, which will begin counting until it hits 2048 * the value in the TIMERINT register, and then trigger an 2049 * interrupt. Each time we write to the TIMERCNT register, 2050 * the timer count is reset to 0. 2051 */ 2052 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2053 2054 RL_UNLOCK(sc); 2055 2056 /* 2057 * Set a timeout in case the chip goes out to lunch. 2058 */ 2059 ifp->if_timer = 5; 2060 2061 return; 2062} 2063 2064static void 2065re_init(xsc) 2066 void *xsc; 2067{ 2068 struct rl_softc *sc = xsc; 2069 struct ifnet *ifp = &sc->arpcom.ac_if; 2070 struct mii_data *mii; 2071 u_int32_t rxcfg = 0; 2072 2073 RL_LOCK(sc); 2074 mii = device_get_softc(sc->rl_miibus); 2075 2076 /* 2077 * Cancel pending I/O and free all RX/TX buffers. 2078 */ 2079 re_stop(sc); 2080 2081 /* 2082 * Enable C+ RX and TX mode, as well as VLAN stripping and 2083 * RX checksum offload. We must configure the C+ register 2084 * before all others. 2085 */ 2086 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2087 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2088 RL_CPLUSCMD_VLANSTRIP| 2089 (ifp->if_capenable & IFCAP_RXCSUM ? 2090 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2091 2092 /* 2093 * Init our MAC address. Even though the chipset 2094 * documentation doesn't mention it, we need to enter "Config 2095 * register write enable" mode to modify the ID registers. 2096 */ 2097 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2098 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2099 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2100 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2101 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2102 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2103 2104 /* 2105 * For C+ mode, initialize the RX descriptors and mbufs. 2106 */ 2107 re_rx_list_init(sc); 2108 re_tx_list_init(sc); 2109 2110 /* 2111 * Enable transmit and receive. 2112 */ 2113 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2114 2115 /* 2116 * Set the initial TX and RX configuration. 2117 */ 2118 if (sc->rl_testmode) { 2119 if (sc->rl_type == RL_8169) 2120 CSR_WRITE_4(sc, RL_TXCFG, 2121 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2122 else 2123 CSR_WRITE_4(sc, RL_TXCFG, 2124 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2125 } else 2126 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2127 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2128 2129 /* Set the individual bit to receive frames for this host only. */ 2130 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2131 rxcfg |= RL_RXCFG_RX_INDIV; 2132 2133 /* If we want promiscuous mode, set the allframes bit. */ 2134 if (ifp->if_flags & IFF_PROMISC) { 2135 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2136 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2137 } else { 2138 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2139 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2140 } 2141 2142 /* 2143 * Set capture broadcast bit to capture broadcast frames. 2144 */ 2145 if (ifp->if_flags & IFF_BROADCAST) { 2146 rxcfg |= RL_RXCFG_RX_BROAD; 2147 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2148 } else { 2149 rxcfg &= ~RL_RXCFG_RX_BROAD; 2150 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2151 } 2152 2153 /* 2154 * Program the multicast filter, if necessary. 2155 */ 2156 re_setmulti(sc); 2157 2158#ifdef DEVICE_POLLING 2159 /* 2160 * Disable interrupts if we are polling. 2161 */ 2162 if (ifp->if_flags & IFF_POLLING) 2163 CSR_WRITE_2(sc, RL_IMR, 0); 2164 else /* otherwise ... */ 2165#endif /* DEVICE_POLLING */ 2166 /* 2167 * Enable interrupts. 2168 */ 2169 if (sc->rl_testmode) 2170 CSR_WRITE_2(sc, RL_IMR, 0); 2171 else 2172 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2173 2174 /* Set initial TX threshold */ 2175 sc->rl_txthresh = RL_TX_THRESH_INIT; 2176 2177 /* Start RX/TX process. */ 2178 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2179#ifdef notdef 2180 /* Enable receiver and transmitter. */ 2181 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2182#endif 2183 /* 2184 * Load the addresses of the RX and TX lists into the chip. 2185 */ 2186 2187 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2188 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2189 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2190 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2191 2192 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2193 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2194 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2195 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2196 2197 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2198 2199 /* 2200 * Initialize the timer interrupt register so that 2201 * a timer interrupt will be generated once the timer 2202 * reaches a certain number of ticks. The timer is 2203 * reloaded on each transmit. This gives us TX interrupt 2204 * moderation, which dramatically improves TX frame rate. 2205 */ 2206 2207 if (sc->rl_type == RL_8169) 2208 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2209 else 2210 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2211 2212 /* 2213 * For 8169 gigE NICs, set the max allowed RX packet 2214 * size so we can receive jumbo frames. 2215 */ 2216 if (sc->rl_type == RL_8169) 2217 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2218 2219 if (sc->rl_testmode) { 2220 RL_UNLOCK(sc); 2221 return; 2222 } 2223 2224 mii_mediachg(mii); 2225 2226 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2227 2228 ifp->if_flags |= IFF_RUNNING; 2229 ifp->if_flags &= ~IFF_OACTIVE; 2230 2231 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2232 RL_UNLOCK(sc); 2233 2234 return; 2235} 2236 2237/* 2238 * Set media options. 2239 */ 2240static int 2241re_ifmedia_upd(ifp) 2242 struct ifnet *ifp; 2243{ 2244 struct rl_softc *sc; 2245 struct mii_data *mii; 2246 2247 sc = ifp->if_softc; 2248 mii = device_get_softc(sc->rl_miibus); 2249 mii_mediachg(mii); 2250 2251 return(0); 2252} 2253 2254/* 2255 * Report current media status. 2256 */ 2257static void 2258re_ifmedia_sts(ifp, ifmr) 2259 struct ifnet *ifp; 2260 struct ifmediareq *ifmr; 2261{ 2262 struct rl_softc *sc; 2263 struct mii_data *mii; 2264 2265 sc = ifp->if_softc; 2266 mii = device_get_softc(sc->rl_miibus); 2267 2268 mii_pollstat(mii); 2269 ifmr->ifm_active = mii->mii_media_active; 2270 ifmr->ifm_status = mii->mii_media_status; 2271 2272 return; 2273} 2274 2275static int 2276re_ioctl(ifp, command, data) 2277 struct ifnet *ifp; 2278 u_long command; 2279 caddr_t data; 2280{ 2281 struct rl_softc *sc = ifp->if_softc; 2282 struct ifreq *ifr = (struct ifreq *) data; 2283 struct mii_data *mii; 2284 int error = 0; 2285 2286 RL_LOCK(sc); 2287 2288 switch(command) { 2289 case SIOCSIFMTU: 2290 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2291 error = EINVAL; 2292 ifp->if_mtu = ifr->ifr_mtu; 2293 break; 2294 case SIOCSIFFLAGS: 2295 if (ifp->if_flags & IFF_UP) { 2296 re_init(sc); 2297 } else { 2298 if (ifp->if_flags & IFF_RUNNING) 2299 re_stop(sc); 2300 } 2301 error = 0; 2302 break; 2303 case SIOCADDMULTI: 2304 case SIOCDELMULTI: 2305 re_setmulti(sc); 2306 error = 0; 2307 break; 2308 case SIOCGIFMEDIA: 2309 case SIOCSIFMEDIA: 2310 mii = device_get_softc(sc->rl_miibus); 2311 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2312 break; 2313 case SIOCSIFCAP: 2314 ifp->if_capenable = ifr->ifr_reqcap; 2315 if (ifp->if_capenable & IFCAP_TXCSUM) 2316 ifp->if_hwassist = RE_CSUM_FEATURES; 2317 else 2318 ifp->if_hwassist = 0; 2319 if (ifp->if_flags & IFF_RUNNING) 2320 re_init(sc); 2321 break; 2322 default: 2323 error = ether_ioctl(ifp, command, data); 2324 break; 2325 } 2326 2327 RL_UNLOCK(sc); 2328 2329 return(error); 2330} 2331 2332static void 2333re_watchdog(ifp) 2334 struct ifnet *ifp; 2335{ 2336 struct rl_softc *sc; 2337 2338 sc = ifp->if_softc; 2339 RL_LOCK(sc); 2340 printf("re%d: watchdog timeout\n", sc->rl_unit); 2341 ifp->if_oerrors++; 2342 2343 re_txeof(sc); 2344 re_rxeof(sc); 2345 2346 re_init(sc); 2347 2348 RL_UNLOCK(sc); 2349 2350 return; 2351} 2352 2353/* 2354 * Stop the adapter and free any mbufs allocated to the 2355 * RX and TX lists. 2356 */ 2357static void 2358re_stop(sc) 2359 struct rl_softc *sc; 2360{ 2361 register int i; 2362 struct ifnet *ifp; 2363 2364 RL_LOCK(sc); 2365 ifp = &sc->arpcom.ac_if; 2366 ifp->if_timer = 0; 2367 2368 untimeout(re_tick, sc, sc->rl_stat_ch); 2369 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2370#ifdef DEVICE_POLLING 2371 ether_poll_deregister(ifp); 2372#endif /* DEVICE_POLLING */ 2373 2374 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2375 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2376 2377 if (sc->rl_head != NULL) { 2378 m_freem(sc->rl_head); 2379 sc->rl_head = sc->rl_tail = NULL; 2380 } 2381 2382 /* Free the TX list buffers. */ 2383 2384 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2385 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2386 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2387 sc->rl_ldata.rl_tx_dmamap[i]); 2388 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2389 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2390 } 2391 } 2392 2393 /* Free the RX list buffers. */ 2394 2395 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2396 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2397 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2398 sc->rl_ldata.rl_rx_dmamap[i]); 2399 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2400 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2401 } 2402 } 2403 2404 RL_UNLOCK(sc); 2405 return; 2406} 2407 2408/* 2409 * Device suspend routine. Stop the interface and save some PCI 2410 * settings in case the BIOS doesn't restore them properly on 2411 * resume. 2412 */ 2413static int 2414re_suspend(dev) 2415 device_t dev; 2416{ 2417 register int i; 2418 struct rl_softc *sc; 2419 2420 sc = device_get_softc(dev); 2421 2422 re_stop(sc); 2423 2424 for (i = 0; i < 5; i++) 2425 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2426 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2427 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2428 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2429 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2430 2431 sc->suspended = 1; 2432 2433 return (0); 2434} 2435 2436/* 2437 * Device resume routine. Restore some PCI settings in case the BIOS 2438 * doesn't, re-enable busmastering, and restart the interface if 2439 * appropriate. 2440 */ 2441static int 2442re_resume(dev) 2443 device_t dev; 2444{ 2445 register int i; 2446 struct rl_softc *sc; 2447 struct ifnet *ifp; 2448 2449 sc = device_get_softc(dev); 2450 ifp = &sc->arpcom.ac_if; 2451 2452 /* better way to do this? */ 2453 for (i = 0; i < 5; i++) 2454 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2455 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2456 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2457 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2458 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2459 2460 /* reenable busmastering */ 2461 pci_enable_busmaster(dev); 2462 pci_enable_io(dev, RL_RES); 2463 2464 /* reinitialize interface if necessary */ 2465 if (ifp->if_flags & IFF_UP) 2466 re_init(sc); 2467 2468 sc->suspended = 0; 2469 2470 return (0); 2471} 2472 2473/* 2474 * Stop all chip I/O so that the kernel's probe routines don't 2475 * get confused by errant DMAs when rebooting. 2476 */ 2477static void 2478re_shutdown(dev) 2479 device_t dev; 2480{ 2481 struct rl_softc *sc; 2482 2483 sc = device_get_softc(dev); 2484 2485 re_stop(sc); 2486 2487 return; 2488} 2489