if_re.c revision 119982
1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 35 * 36 * Written by Bill Paul <wpaul@windriver.com> 37 * Senior Networking Software Engineer 38 * Wind River Systems 39 */ 40 41/* 42 * This driver is designed to support RealTek's next generation of 43 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 44 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 45 * and the RTL8110S. 46 * 47 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 48 * with the older 8139 family, however it also supports a special 49 * C+ mode of operation that provides several new performance enhancing 50 * features. These include: 51 * 52 * o Descriptor based DMA mechanism. Each descriptor represents 53 * a single packet fragment. Data buffers may be aligned on 54 * any byte boundary. 55 * 56 * o 64-bit DMA 57 * 58 * o TCP/IP checksum offload for both RX and TX 59 * 60 * o High and normal priority transmit DMA rings 61 * 62 * o VLAN tag insertion and extraction 63 * 64 * o TCP large send (segmentation offload) 65 * 66 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 67 * programming API is fairly straightforward. The RX filtering, EEPROM 68 * access and PHY access is the same as it is on the older 8139 series 69 * chips. 70 * 71 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 72 * same programming API and feature set as the 8139C+ with the following 73 * differences and additions: 74 * 75 * o 1000Mbps mode 76 * 77 * o Jumbo frames 78 * 79 * o GMII and TBI ports/registers for interfacing with copper 80 * or fiber PHYs 81 * 82 * o RX and TX DMA rings can have up to 1024 descriptors 83 * (the 8139C+ allows a maximum of 64) 84 * 85 * o Slight differences in register layout from the 8139C+ 86 * 87 * The TX start and timer interrupt registers are at different locations 88 * on the 8169 than they are on the 8139C+. Also, the status word in the 89 * RX descriptor has a slightly different bit layout. The 8169 does not 90 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 91 * copper gigE PHY. 92 * 93 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 94 * (the 'S' stands for 'single-chip'). These devices have the same 95 * programming API as the older 8169, but also have some vendor-specific 96 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 97 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 98 * 99 * This driver takes advantage of the RX and TX checksum offload and 100 * VLAN tag insertion/extraction features. It also implements TX 101 * interrupt moderation using the timer interrupt registers, which 102 * significantly reduces TX interrupt load. There is also support 103 * for jumbo frames, however the 8169/8169S/8110S can not transmit 104 * jumbo frames larger than 7.5K, so the max MTU possible with this 105 * driver is 7500 bytes. 106 */ 107 108#include <sys/cdefs.h> 109__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 119982 2003-09-11 07:54:16Z wpaul $"); 110 111#include <sys/param.h> 112#include <sys/endian.h> 113#include <sys/systm.h> 114#include <sys/sockio.h> 115#include <sys/mbuf.h> 116#include <sys/malloc.h> 117#include <sys/kernel.h> 118#include <sys/socket.h> 119 120#include <net/if.h> 121#include <net/if_arp.h> 122#include <net/ethernet.h> 123#include <net/if_dl.h> 124#include <net/if_media.h> 125#include <net/if_vlan_var.h> 126 127#include <net/bpf.h> 128 129#include <machine/bus_pio.h> 130#include <machine/bus_memio.h> 131#include <machine/bus.h> 132#include <machine/resource.h> 133#include <sys/bus.h> 134#include <sys/rman.h> 135 136#include <dev/mii/mii.h> 137#include <dev/mii/miivar.h> 138 139#include <dev/pci/pcireg.h> 140#include <dev/pci/pcivar.h> 141 142MODULE_DEPEND(re, pci, 1, 1, 1); 143MODULE_DEPEND(re, ether, 1, 1, 1); 144MODULE_DEPEND(re, miibus, 1, 1, 1); 145 146/* "controller miibus0" required. See GENERIC if you get errors here. */ 147#include "miibus_if.h" 148 149/* 150 * Default to using PIO access for this driver. 151 */ 152#define RE_USEIOSPACE 153 154#include <pci/if_rlreg.h> 155 156#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 157 158/* 159 * Various supported device vendors/types and their names. 160 */ 161static struct rl_type re_devs[] = { 162 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 163 "RealTek 8139C+ 10/100BaseTX" }, 164 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 165 "RealTek 8169 Gigabit Ethernet" }, 166 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 167 "RealTek 8169S Single-chip Gigabit Ethernet" }, 168 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 169 "RealTek 8110S Single-chip Gigabit Ethernet" }, 170 { 0, 0, 0, NULL } 171}; 172 173static struct rl_hwrev re_hwrevs[] = { 174 { RL_HWREV_8139, RL_8139, "" }, 175 { RL_HWREV_8139A, RL_8139, "A" }, 176 { RL_HWREV_8139AG, RL_8139, "A-G" }, 177 { RL_HWREV_8139B, RL_8139, "B" }, 178 { RL_HWREV_8130, RL_8139, "8130" }, 179 { RL_HWREV_8139C, RL_8139, "C" }, 180 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 181 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 182 { RL_HWREV_8169, RL_8169, "8169"}, 183 { RL_HWREV_8169S, RL_8169, "8169S"}, 184 { RL_HWREV_8110S, RL_8169, "8110S"}, 185 { RL_HWREV_8100, RL_8139, "8100"}, 186 { RL_HWREV_8101, RL_8139, "8101"}, 187 { 0, 0, NULL } 188}; 189 190static int re_probe (device_t); 191static int re_attach (device_t); 192static int re_detach (device_t); 193 194static int re_encap (struct rl_softc *, struct mbuf *, int *); 195 196static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 197static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 198 bus_size_t, int); 199static int re_allocmem (device_t, struct rl_softc *); 200static int re_newbuf (struct rl_softc *, int, struct mbuf *); 201static int re_rx_list_init (struct rl_softc *); 202static int re_tx_list_init (struct rl_softc *); 203static void re_rxeof (struct rl_softc *); 204static void re_txeof (struct rl_softc *); 205static void re_intr (void *); 206static void re_tick (void *); 207static void re_start (struct ifnet *); 208static int re_ioctl (struct ifnet *, u_long, caddr_t); 209static void re_init (void *); 210static void re_stop (struct rl_softc *); 211static void re_watchdog (struct ifnet *); 212static int re_suspend (device_t); 213static int re_resume (device_t); 214static void re_shutdown (device_t); 215static int re_ifmedia_upd (struct ifnet *); 216static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 217 218static void re_eeprom_putbyte (struct rl_softc *, int); 219static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 220static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 221static int re_gmii_readreg (device_t, int, int); 222static int re_gmii_writereg (device_t, int, int, int); 223 224static int re_miibus_readreg (device_t, int, int); 225static int re_miibus_writereg (device_t, int, int, int); 226static void re_miibus_statchg (device_t); 227 228static u_int8_t re_calchash (caddr_t); 229static void re_setmulti (struct rl_softc *); 230static void re_reset (struct rl_softc *); 231 232static int re_diag (struct rl_softc *); 233 234#ifdef RE_USEIOSPACE 235#define RL_RES SYS_RES_IOPORT 236#define RL_RID RL_PCI_LOIO 237#else 238#define RL_RES SYS_RES_MEMORY 239#define RL_RID RL_PCI_LOMEM 240#endif 241 242static device_method_t re_methods[] = { 243 /* Device interface */ 244 DEVMETHOD(device_probe, re_probe), 245 DEVMETHOD(device_attach, re_attach), 246 DEVMETHOD(device_detach, re_detach), 247 DEVMETHOD(device_suspend, re_suspend), 248 DEVMETHOD(device_resume, re_resume), 249 DEVMETHOD(device_shutdown, re_shutdown), 250 251 /* bus interface */ 252 DEVMETHOD(bus_print_child, bus_generic_print_child), 253 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 254 255 /* MII interface */ 256 DEVMETHOD(miibus_readreg, re_miibus_readreg), 257 DEVMETHOD(miibus_writereg, re_miibus_writereg), 258 DEVMETHOD(miibus_statchg, re_miibus_statchg), 259 260 { 0, 0 } 261}; 262 263static driver_t re_driver = { 264 "re", 265 re_methods, 266 sizeof(struct rl_softc) 267}; 268 269static devclass_t re_devclass; 270 271DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 272DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 273DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 274 275#define EE_SET(x) \ 276 CSR_WRITE_1(sc, RL_EECMD, \ 277 CSR_READ_1(sc, RL_EECMD) | x) 278 279#define EE_CLR(x) \ 280 CSR_WRITE_1(sc, RL_EECMD, \ 281 CSR_READ_1(sc, RL_EECMD) & ~x) 282 283/* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286static void 287re_eeprom_putbyte(sc, addr) 288 struct rl_softc *sc; 289 int addr; 290{ 291 register int d, i; 292 293 d = addr | sc->rl_eecmd_read; 294 295 /* 296 * Feed in each bit and strobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 EE_SET(RL_EE_DATAIN); 301 } else { 302 EE_CLR(RL_EE_DATAIN); 303 } 304 DELAY(100); 305 EE_SET(RL_EE_CLK); 306 DELAY(150); 307 EE_CLR(RL_EE_CLK); 308 DELAY(100); 309 } 310 311 return; 312} 313 314/* 315 * Read a word of data stored in the EEPROM at address 'addr.' 316 */ 317static void 318re_eeprom_getword(sc, addr, dest) 319 struct rl_softc *sc; 320 int addr; 321 u_int16_t *dest; 322{ 323 register int i; 324 u_int16_t word = 0; 325 326 /* Enter EEPROM access mode. */ 327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 328 329 /* 330 * Send address of word we want to read. 331 */ 332 re_eeprom_putbyte(sc, addr); 333 334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 335 336 /* 337 * Start reading bits from EEPROM. 338 */ 339 for (i = 0x8000; i; i >>= 1) { 340 EE_SET(RL_EE_CLK); 341 DELAY(100); 342 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 343 word |= i; 344 EE_CLR(RL_EE_CLK); 345 DELAY(100); 346 } 347 348 /* Turn off EEPROM access mode. */ 349 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 350 351 *dest = word; 352 353 return; 354} 355 356/* 357 * Read a sequence of words from the EEPROM. 358 */ 359static void 360re_read_eeprom(sc, dest, off, cnt, swap) 361 struct rl_softc *sc; 362 caddr_t dest; 363 int off; 364 int cnt; 365 int swap; 366{ 367 int i; 368 u_int16_t word = 0, *ptr; 369 370 for (i = 0; i < cnt; i++) { 371 re_eeprom_getword(sc, off + i, &word); 372 ptr = (u_int16_t *)(dest + (i * 2)); 373 if (swap) 374 *ptr = ntohs(word); 375 else 376 *ptr = word; 377 } 378 379 return; 380} 381 382static int 383re_gmii_readreg(dev, phy, reg) 384 device_t dev; 385 int phy, reg; 386{ 387 struct rl_softc *sc; 388 u_int32_t rval; 389 int i; 390 391 if (phy != 1) 392 return(0); 393 394 sc = device_get_softc(dev); 395 396 /* Let the rgephy driver read the GMEDIASTAT register */ 397 398 if (reg == RL_GMEDIASTAT) { 399 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 400 return(rval); 401 } 402 403 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 404 DELAY(1000); 405 406 for (i = 0; i < RL_TIMEOUT; i++) { 407 rval = CSR_READ_4(sc, RL_PHYAR); 408 if (rval & RL_PHYAR_BUSY) 409 break; 410 DELAY(100); 411 } 412 413 if (i == RL_TIMEOUT) { 414 printf ("re%d: PHY read failed\n", sc->rl_unit); 415 return (0); 416 } 417 418 return (rval & RL_PHYAR_PHYDATA); 419} 420 421static int 422re_gmii_writereg(dev, phy, reg, data) 423 device_t dev; 424 int phy, reg, data; 425{ 426 struct rl_softc *sc; 427 u_int32_t rval; 428 int i; 429 430 sc = device_get_softc(dev); 431 432 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 433 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 434 DELAY(1000); 435 436 for (i = 0; i < RL_TIMEOUT; i++) { 437 rval = CSR_READ_4(sc, RL_PHYAR); 438 if (!(rval & RL_PHYAR_BUSY)) 439 break; 440 DELAY(100); 441 } 442 443 if (i == RL_TIMEOUT) { 444 printf ("re%d: PHY write failed\n", sc->rl_unit); 445 return (0); 446 } 447 448 return (0); 449} 450 451static int 452re_miibus_readreg(dev, phy, reg) 453 device_t dev; 454 int phy, reg; 455{ 456 struct rl_softc *sc; 457 u_int16_t rval = 0; 458 u_int16_t re8139_reg = 0; 459 460 sc = device_get_softc(dev); 461 RL_LOCK(sc); 462 463 if (sc->rl_type == RL_8169) { 464 rval = re_gmii_readreg(dev, phy, reg); 465 RL_UNLOCK(sc); 466 return (rval); 467 } 468 469 /* Pretend the internal PHY is only at address 0 */ 470 if (phy) { 471 RL_UNLOCK(sc); 472 return(0); 473 } 474 switch(reg) { 475 case MII_BMCR: 476 re8139_reg = RL_BMCR; 477 break; 478 case MII_BMSR: 479 re8139_reg = RL_BMSR; 480 break; 481 case MII_ANAR: 482 re8139_reg = RL_ANAR; 483 break; 484 case MII_ANER: 485 re8139_reg = RL_ANER; 486 break; 487 case MII_ANLPAR: 488 re8139_reg = RL_LPAR; 489 break; 490 case MII_PHYIDR1: 491 case MII_PHYIDR2: 492 RL_UNLOCK(sc); 493 return(0); 494 /* 495 * Allow the rlphy driver to read the media status 496 * register. If we have a link partner which does not 497 * support NWAY, this is the register which will tell 498 * us the results of parallel detection. 499 */ 500 case RL_MEDIASTAT: 501 rval = CSR_READ_1(sc, RL_MEDIASTAT); 502 RL_UNLOCK(sc); 503 return(rval); 504 default: 505 printf("re%d: bad phy register\n", sc->rl_unit); 506 RL_UNLOCK(sc); 507 return(0); 508 } 509 rval = CSR_READ_2(sc, re8139_reg); 510 RL_UNLOCK(sc); 511 return(rval); 512} 513 514static int 515re_miibus_writereg(dev, phy, reg, data) 516 device_t dev; 517 int phy, reg, data; 518{ 519 struct rl_softc *sc; 520 u_int16_t re8139_reg = 0; 521 int rval = 0; 522 523 sc = device_get_softc(dev); 524 RL_LOCK(sc); 525 526 if (sc->rl_type == RL_8169) { 527 rval = re_gmii_writereg(dev, phy, reg, data); 528 RL_UNLOCK(sc); 529 return (rval); 530 } 531 532 /* Pretend the internal PHY is only at address 0 */ 533 if (phy) { 534 RL_UNLOCK(sc); 535 return(0); 536 } 537 switch(reg) { 538 case MII_BMCR: 539 re8139_reg = RL_BMCR; 540 break; 541 case MII_BMSR: 542 re8139_reg = RL_BMSR; 543 break; 544 case MII_ANAR: 545 re8139_reg = RL_ANAR; 546 break; 547 case MII_ANER: 548 re8139_reg = RL_ANER; 549 break; 550 case MII_ANLPAR: 551 re8139_reg = RL_LPAR; 552 break; 553 case MII_PHYIDR1: 554 case MII_PHYIDR2: 555 RL_UNLOCK(sc); 556 return(0); 557 break; 558 default: 559 printf("re%d: bad phy register\n", sc->rl_unit); 560 RL_UNLOCK(sc); 561 return(0); 562 } 563 CSR_WRITE_2(sc, re8139_reg, data); 564 RL_UNLOCK(sc); 565 return(0); 566} 567 568static void 569re_miibus_statchg(dev) 570 device_t dev; 571{ 572 return; 573} 574 575/* 576 * Calculate CRC of a multicast group address, return the upper 6 bits. 577 */ 578static u_int8_t 579re_calchash(addr) 580 caddr_t addr; 581{ 582 u_int32_t crc, carry; 583 int i, j; 584 u_int8_t c; 585 586 /* Compute CRC for the address value. */ 587 crc = 0xFFFFFFFF; /* initial value */ 588 589 for (i = 0; i < 6; i++) { 590 c = *(addr + i); 591 for (j = 0; j < 8; j++) { 592 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 593 crc <<= 1; 594 c >>= 1; 595 if (carry) 596 crc = (crc ^ 0x04c11db6) | carry; 597 } 598 } 599 600 /* return the filter bit position */ 601 return(crc >> 26); 602} 603 604/* 605 * Program the 64-bit multicast hash filter. 606 */ 607static void 608re_setmulti(sc) 609 struct rl_softc *sc; 610{ 611 struct ifnet *ifp; 612 int h = 0; 613 u_int32_t hashes[2] = { 0, 0 }; 614 struct ifmultiaddr *ifma; 615 u_int32_t rxfilt; 616 int mcnt = 0; 617 618 ifp = &sc->arpcom.ac_if; 619 620 rxfilt = CSR_READ_4(sc, RL_RXCFG); 621 622 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 623 rxfilt |= RL_RXCFG_RX_MULTI; 624 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 625 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 626 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 627 return; 628 } 629 630 /* first, zot all the existing hash bits */ 631 CSR_WRITE_4(sc, RL_MAR0, 0); 632 CSR_WRITE_4(sc, RL_MAR4, 0); 633 634 /* now program new ones */ 635 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 636 if (ifma->ifma_addr->sa_family != AF_LINK) 637 continue; 638 h = re_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 639 if (h < 32) 640 hashes[0] |= (1 << h); 641 else 642 hashes[1] |= (1 << (h - 32)); 643 mcnt++; 644 } 645 646 if (mcnt) 647 rxfilt |= RL_RXCFG_RX_MULTI; 648 else 649 rxfilt &= ~RL_RXCFG_RX_MULTI; 650 651 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 652 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 653 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 654 655 return; 656} 657 658static void 659re_reset(sc) 660 struct rl_softc *sc; 661{ 662 register int i; 663 664 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 665 666 for (i = 0; i < RL_TIMEOUT; i++) { 667 DELAY(10); 668 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 669 break; 670 } 671 if (i == RL_TIMEOUT) 672 printf("re%d: reset never completed!\n", sc->rl_unit); 673 674 CSR_WRITE_1(sc, 0x82, 1); 675 676 return; 677} 678 679/* 680 * The following routine is designed to test for a defect on some 681 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 682 * lines connected to the bus, however for a 32-bit only card, they 683 * should be pulled high. The result of this defect is that the 684 * NIC will not work right if you plug it into a 64-bit slot: DMA 685 * operations will be done with 64-bit transfers, which will fail 686 * because the 64-bit data lines aren't connected. 687 * 688 * There's no way to work around this (short of talking a soldering 689 * iron to the board), however we can detect it. The method we use 690 * here is to put the NIC into digital loopback mode, set the receiver 691 * to promiscuous mode, and then try to send a frame. We then compare 692 * the frame data we sent to what was received. If the data matches, 693 * then the NIC is working correctly, otherwise we know the user has 694 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 695 * slot. In the latter case, there's no way the NIC can work correctly, 696 * so we print out a message on the console and abort the device attach. 697 */ 698 699static int 700re_diag(sc) 701 struct rl_softc *sc; 702{ 703 struct ifnet *ifp = &sc->arpcom.ac_if; 704 struct mbuf *m0; 705 struct ether_header *eh; 706 struct rl_desc *cur_rx; 707 u_int16_t status; 708 u_int32_t rxstat; 709 int total_len, i, error = 0; 710 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 711 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 712 713 /* Allocate a single mbuf */ 714 715 MGETHDR(m0, M_DONTWAIT, MT_DATA); 716 if (m0 == NULL) 717 return(ENOBUFS); 718 719 /* 720 * Initialize the NIC in test mode. This sets the chip up 721 * so that it can send and receive frames, but performs the 722 * following special functions: 723 * - Puts receiver in promiscuous mode 724 * - Enables digital loopback mode 725 * - Leaves interrupts turned off 726 */ 727 728 ifp->if_flags |= IFF_PROMISC; 729 sc->rl_testmode = 1; 730 re_init(sc); 731 re_stop(sc); 732 DELAY(100000); 733 re_init(sc); 734 735 /* Put some data in the mbuf */ 736 737 eh = mtod(m0, struct ether_header *); 738 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 739 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 740 eh->ether_type = htons(ETHERTYPE_IP); 741 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 742 743 /* Queue the packet, start transmission */ 744 745 IF_HANDOFF(&ifp->if_snd, m0, ifp); 746 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 747 re_start(ifp); 748 m0 = NULL; 749 750 /* Wait for it to propagate through the chip */ 751 752 DELAY(100000); 753 for (i = 0; i < RL_TIMEOUT; i++) { 754 status = CSR_READ_2(sc, RL_ISR); 755 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 756 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 757 break; 758 DELAY(10); 759 } 760 761 if (i == RL_TIMEOUT) { 762 printf("re%d: diagnostic failed, failed to receive packet " 763 "in loopback mode\n", sc->rl_unit); 764 error = EIO; 765 goto done; 766 } 767 768 /* 769 * The packet should have been dumped into the first 770 * entry in the RX DMA ring. Grab it from there. 771 */ 772 773 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 774 sc->rl_ldata.rl_rx_list_map, 775 BUS_DMASYNC_POSTREAD); 776 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 777 sc->rl_ldata.rl_rx_dmamap[0], 778 BUS_DMASYNC_POSTWRITE); 779 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 780 sc->rl_ldata.rl_rx_dmamap[0]); 781 782 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 783 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 784 eh = mtod(m0, struct ether_header *); 785 786 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 787 total_len = RL_RXBYTES(cur_rx); 788 rxstat = le32toh(cur_rx->rl_cmdstat); 789 790 if (total_len != ETHER_MIN_LEN) { 791 printf("re%d: diagnostic failed, received short packet\n", 792 sc->rl_unit); 793 error = EIO; 794 goto done; 795 } 796 797 /* Test that the received packet data matches what we sent. */ 798 799 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 800 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 801 ntohs(eh->ether_type) != ETHERTYPE_IP) { 802 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 803 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 804 dst, ":", src, ":", ETHERTYPE_IP); 805 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 806 eh->ether_dhost, ":", eh->ether_shost, ":", 807 ntohs(eh->ether_type)); 808 printf("re%d: You may have a defective 32-bit NIC plugged " 809 "into a 64-bit PCI slot.\n", sc->rl_unit); 810 printf("re%d: Please re-install the NIC in a 32-bit slot " 811 "for proper operation.\n", sc->rl_unit); 812 printf("re%d: Read the re(4) man page for more details.\n", 813 sc->rl_unit); 814 error = EIO; 815 } 816 817done: 818 /* Turn interface off, release resources */ 819 820 sc->rl_testmode = 0; 821 ifp->if_flags &= ~IFF_PROMISC; 822 re_stop(sc); 823 if (m0 != NULL) 824 m_freem(m0); 825 826 return (error); 827} 828 829/* 830 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 831 * IDs against our list and return a device name if we find a match. 832 */ 833static int 834re_probe(dev) 835 device_t dev; 836{ 837 struct rl_type *t; 838 struct rl_softc *sc; 839 int rid; 840 u_int32_t hwrev; 841 842 t = re_devs; 843 sc = device_get_softc(dev); 844 845 while(t->rl_name != NULL) { 846 if ((pci_get_vendor(dev) == t->rl_vid) && 847 (pci_get_device(dev) == t->rl_did)) { 848 849 /* 850 * Temporarily map the I/O space 851 * so we can read the chip ID register. 852 */ 853 rid = RL_RID; 854 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 855 0, ~0, 1, RF_ACTIVE); 856 if (sc->rl_res == NULL) { 857 device_printf(dev, 858 "couldn't map ports/memory\n"); 859 return(ENXIO); 860 } 861 sc->rl_btag = rman_get_bustag(sc->rl_res); 862 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 863 mtx_init(&sc->rl_mtx, 864 device_get_nameunit(dev), 865 MTX_NETWORK_LOCK, MTX_DEF); 866 RL_LOCK(sc); 867 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 868 bus_release_resource(dev, RL_RES, 869 RL_RID, sc->rl_res); 870 RL_UNLOCK(sc); 871 mtx_destroy(&sc->rl_mtx); 872 if (t->rl_basetype == hwrev) { 873 device_set_desc(dev, t->rl_name); 874 return(0); 875 } 876 } 877 t++; 878 } 879 880 return(ENXIO); 881} 882 883/* 884 * This routine takes the segment list provided as the result of 885 * a bus_dma_map_load() operation and assigns the addresses/lengths 886 * to RealTek DMA descriptors. This can be called either by the RX 887 * code or the TX code. In the RX case, we'll probably wind up mapping 888 * at most one segment. For the TX case, there could be any number of 889 * segments since TX packets may span multiple mbufs. In either case, 890 * if the number of segments is larger than the rl_maxsegs limit 891 * specified by the caller, we abort the mapping operation. Sadly, 892 * whoever designed the buffer mapping API did not provide a way to 893 * return an error from here, so we have to fake it a bit. 894 */ 895 896static void 897re_dma_map_desc(arg, segs, nseg, mapsize, error) 898 void *arg; 899 bus_dma_segment_t *segs; 900 int nseg; 901 bus_size_t mapsize; 902 int error; 903{ 904 struct rl_dmaload_arg *ctx; 905 struct rl_desc *d = NULL; 906 int i = 0, idx; 907 908 if (error) 909 return; 910 911 ctx = arg; 912 913 /* Signal error to caller if there's too many segments */ 914 if (nseg > ctx->rl_maxsegs) { 915 ctx->rl_maxsegs = 0; 916 return; 917 } 918 919 /* 920 * Map the segment array into descriptors. Note that we set the 921 * start-of-frame and end-of-frame markers for either TX or RX, but 922 * they really only have meaning in the TX case. (In the RX case, 923 * it's the chip that tells us where packets begin and end.) 924 * We also keep track of the end of the ring and set the 925 * end-of-ring bits as needed, and we set the ownership bits 926 * in all except the very first descriptor. (The caller will 927 * set this descriptor later when it start transmission or 928 * reception.) 929 */ 930 idx = ctx->rl_idx; 931 while(1) { 932 u_int32_t cmdstat; 933 d = &ctx->rl_ring[idx]; 934 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 935 ctx->rl_maxsegs = 0; 936 return; 937 } 938 cmdstat = segs[i].ds_len; 939 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 940 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 941 if (i == 0) 942 cmdstat |= RL_TDESC_CMD_SOF; 943 else 944 cmdstat |= RL_TDESC_CMD_OWN; 945 if (idx == (RL_RX_DESC_CNT - 1)) 946 cmdstat |= RL_TDESC_CMD_EOR; 947 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 948 i++; 949 if (i == nseg) 950 break; 951 RL_DESC_INC(idx); 952 } 953 954 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 955 ctx->rl_maxsegs = nseg; 956 ctx->rl_idx = idx; 957 958 return; 959} 960 961/* 962 * Map a single buffer address. 963 */ 964 965static void 966re_dma_map_addr(arg, segs, nseg, error) 967 void *arg; 968 bus_dma_segment_t *segs; 969 int nseg; 970 int error; 971{ 972 u_int32_t *addr; 973 974 if (error) 975 return; 976 977 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 978 addr = arg; 979 *addr = segs->ds_addr; 980 981 return; 982} 983 984static int 985re_allocmem(dev, sc) 986 device_t dev; 987 struct rl_softc *sc; 988{ 989 int error; 990 int nseg; 991 int i; 992 993 /* 994 * Allocate map for RX mbufs. 995 */ 996 nseg = 32; 997 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 998 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 999 NULL, MCLBYTES * nseg, nseg, RL_JLEN, BUS_DMA_ALLOCNOW, 1000 NULL, NULL, &sc->rl_ldata.rl_mtag); 1001 if (error) { 1002 device_printf(dev, "could not allocate dma tag\n"); 1003 return (ENOMEM); 1004 } 1005 1006 /* 1007 * Allocate map for TX descriptor list. 1008 */ 1009 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1010 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1011 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1012 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1013 if (error) { 1014 device_printf(dev, "could not allocate dma tag\n"); 1015 return (ENOMEM); 1016 } 1017 1018 /* Allocate DMA'able memory for the TX ring */ 1019 1020 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1021 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1022 &sc->rl_ldata.rl_tx_list_map); 1023 if (error) 1024 return (ENOMEM); 1025 1026 /* Load the map for the TX ring. */ 1027 1028 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1029 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1030 RL_TX_LIST_SZ, re_dma_map_addr, 1031 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1032 1033 /* Create DMA maps for TX buffers */ 1034 1035 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1036 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1037 &sc->rl_ldata.rl_tx_dmamap[i]); 1038 if (error) { 1039 device_printf(dev, "can't create DMA map for TX\n"); 1040 return(ENOMEM); 1041 } 1042 } 1043 1044 /* 1045 * Allocate map for RX descriptor list. 1046 */ 1047 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1048 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1049 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1050 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1051 if (error) { 1052 device_printf(dev, "could not allocate dma tag\n"); 1053 return (ENOMEM); 1054 } 1055 1056 /* Allocate DMA'able memory for the RX ring */ 1057 1058 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1059 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1060 &sc->rl_ldata.rl_rx_list_map); 1061 if (error) 1062 return (ENOMEM); 1063 1064 /* Load the map for the RX ring. */ 1065 1066 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1067 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1068 RL_TX_LIST_SZ, re_dma_map_addr, 1069 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1070 1071 /* Create DMA maps for RX buffers */ 1072 1073 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1074 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1075 &sc->rl_ldata.rl_rx_dmamap[i]); 1076 if (error) { 1077 device_printf(dev, "can't create DMA map for RX\n"); 1078 return(ENOMEM); 1079 } 1080 } 1081 1082 return(0); 1083} 1084 1085/* 1086 * Attach the interface. Allocate softc structures, do ifmedia 1087 * setup and ethernet/BPF attach. 1088 */ 1089static int 1090re_attach(dev) 1091 device_t dev; 1092{ 1093 u_char eaddr[ETHER_ADDR_LEN]; 1094 u_int16_t as[3]; 1095 struct rl_softc *sc; 1096 struct ifnet *ifp; 1097 struct rl_hwrev *hw_rev; 1098 int hwrev; 1099 u_int16_t re_did = 0; 1100 int unit, error = 0, rid, i; 1101 1102 sc = device_get_softc(dev); 1103 unit = device_get_unit(dev); 1104 1105 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1106 MTX_DEF | MTX_RECURSE); 1107#ifndef BURN_BRIDGES 1108 /* 1109 * Handle power management nonsense. 1110 */ 1111 1112 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1113 u_int32_t iobase, membase, irq; 1114 1115 /* Save important PCI config data. */ 1116 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 1117 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 1118 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 1119 1120 /* Reset the power state. */ 1121 printf("re%d: chip is is in D%d power mode " 1122 "-- setting to D0\n", unit, 1123 pci_get_powerstate(dev)); 1124 1125 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1126 1127 /* Restore PCI config data. */ 1128 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 1129 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 1130 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 1131 } 1132#endif 1133 /* 1134 * Map control/status registers. 1135 */ 1136 pci_enable_busmaster(dev); 1137 1138 rid = RL_RID; 1139 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 1140 0, ~0, 1, RF_ACTIVE); 1141 1142 if (sc->rl_res == NULL) { 1143 printf ("re%d: couldn't map ports/memory\n", unit); 1144 error = ENXIO; 1145 goto fail; 1146 } 1147 1148 sc->rl_btag = rman_get_bustag(sc->rl_res); 1149 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1150 1151 /* Allocate interrupt */ 1152 rid = 0; 1153 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1154 RF_SHAREABLE | RF_ACTIVE); 1155 1156 if (sc->rl_irq == NULL) { 1157 printf("re%d: couldn't map interrupt\n", unit); 1158 error = ENXIO; 1159 goto fail; 1160 } 1161 1162 /* Reset the adapter. */ 1163 re_reset(sc); 1164 1165 hw_rev = re_hwrevs; 1166 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1167 while (hw_rev->rl_desc != NULL) { 1168 if (hw_rev->rl_rev == hwrev) { 1169 sc->rl_type = hw_rev->rl_type; 1170 break; 1171 } 1172 hw_rev++; 1173 } 1174 1175 if (sc->rl_type == RL_8169) { 1176 1177 /* Set RX length mask */ 1178 1179 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1180 1181 /* Force station address autoload from the EEPROM */ 1182 1183 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1184 for (i = 0; i < RL_TIMEOUT; i++) { 1185 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1186 break; 1187 DELAY(100); 1188 } 1189 if (i == RL_TIMEOUT) 1190 printf ("re%d: eeprom autoload timed out\n", unit); 1191 1192 for (i = 0; i < ETHER_ADDR_LEN; i++) 1193 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1194 } else { 1195 1196 /* Set RX length mask */ 1197 1198 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1199 1200 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1201 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1202 if (re_did != 0x8129) 1203 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1204 1205 /* 1206 * Get station address from the EEPROM. 1207 */ 1208 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1209 for (i = 0; i < 3; i++) { 1210 eaddr[(i * 2) + 0] = as[i] & 0xff; 1211 eaddr[(i * 2) + 1] = as[i] >> 8; 1212 } 1213 } 1214 1215 /* 1216 * A RealTek chip was detected. Inform the world. 1217 */ 1218 printf("re%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1219 1220 sc->rl_unit = unit; 1221 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1222 1223 /* 1224 * Allocate the parent bus DMA tag appropriate for PCI. 1225 */ 1226#define RL_NSEG_NEW 32 1227 error = bus_dma_tag_create(NULL, /* parent */ 1228 1, 0, /* alignment, boundary */ 1229 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1230 BUS_SPACE_MAXADDR, /* highaddr */ 1231 NULL, NULL, /* filter, filterarg */ 1232 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1233 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1234 BUS_DMA_ALLOCNOW, /* flags */ 1235 NULL, NULL, /* lockfunc, lockarg */ 1236 &sc->rl_parent_tag); 1237 if (error) 1238 goto fail; 1239 1240 error = re_allocmem(dev, sc); 1241 1242 if (error) 1243 goto fail; 1244 1245 /* Do MII setup */ 1246 if (mii_phy_probe(dev, &sc->rl_miibus, 1247 re_ifmedia_upd, re_ifmedia_sts)) { 1248 printf("re%d: MII without any phy!\n", sc->rl_unit); 1249 error = ENXIO; 1250 goto fail; 1251 } 1252 1253 ifp = &sc->arpcom.ac_if; 1254 ifp->if_softc = sc; 1255 ifp->if_unit = unit; 1256 ifp->if_name = "re"; 1257 ifp->if_mtu = ETHERMTU; 1258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1259 ifp->if_ioctl = re_ioctl; 1260 ifp->if_output = ether_output; 1261 ifp->if_capabilities = IFCAP_VLAN_MTU; 1262 ifp->if_start = re_start; 1263 ifp->if_hwassist = RE_CSUM_FEATURES; 1264 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1265 ifp->if_watchdog = re_watchdog; 1266 ifp->if_init = re_init; 1267 if (sc->rl_type == RL_8169) 1268 ifp->if_baudrate = 1000000000; 1269 else 1270 ifp->if_baudrate = 100000000; 1271 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; 1272 ifp->if_capenable = ifp->if_capabilities; 1273 1274 callout_handle_init(&sc->rl_stat_ch); 1275 1276 /* 1277 * Call MI attach routine. 1278 */ 1279 ether_ifattach(ifp, eaddr); 1280 1281 /* Perform hardware diagnostic. */ 1282 error = re_diag(sc); 1283 1284 if (error) { 1285 printf("re%d: attach aborted due to hardware diag failure\n", 1286 unit); 1287 ether_ifdetach(ifp); 1288 goto fail; 1289 } 1290 1291 /* Hook interrupt last to avoid having to lock softc */ 1292 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1293 re_intr, sc, &sc->rl_intrhand); 1294 1295 if (error) { 1296 printf("re%d: couldn't set up irq\n", unit); 1297 ether_ifdetach(ifp); 1298 goto fail; 1299 } 1300 1301fail: 1302 if (error) 1303 re_detach(dev); 1304 1305 return (error); 1306} 1307 1308/* 1309 * Shutdown hardware and free up resources. This can be called any 1310 * time after the mutex has been initialized. It is called in both 1311 * the error case in attach and the normal detach case so it needs 1312 * to be careful about only freeing resources that have actually been 1313 * allocated. 1314 */ 1315static int 1316re_detach(dev) 1317 device_t dev; 1318{ 1319 struct rl_softc *sc; 1320 struct ifnet *ifp; 1321 int i; 1322 1323 sc = device_get_softc(dev); 1324 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1325 RL_LOCK(sc); 1326 ifp = &sc->arpcom.ac_if; 1327 1328 /* These should only be active if attach succeeded */ 1329 if (device_is_attached(dev)) { 1330 re_stop(sc); 1331 /* 1332 * Force off the IFF_UP flag here, in case someone 1333 * still had a BPF descriptor attached to this 1334 * interface. If they do, ether_ifattach() will cause 1335 * the BPF code to try and clear the promisc mode 1336 * flag, which will bubble down to re_ioctl(), 1337 * which will try to call re_init() again. This will 1338 * turn the NIC back on and restart the MII ticker, 1339 * which will panic the system when the kernel tries 1340 * to invoke the re_tick() function that isn't there 1341 * anymore. 1342 */ 1343 ifp->if_flags &= ~IFF_UP; 1344 ether_ifdetach(ifp); 1345 } 1346 if (sc->rl_miibus) 1347 device_delete_child(dev, sc->rl_miibus); 1348 bus_generic_detach(dev); 1349 1350 if (sc->rl_intrhand) 1351 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1352 if (sc->rl_irq) 1353 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1354 if (sc->rl_res) 1355 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1356 1357 1358 /* Unload and free the RX DMA ring memory and map */ 1359 1360 if (sc->rl_ldata.rl_rx_list_tag) { 1361 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1362 sc->rl_ldata.rl_rx_list_map); 1363 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1364 sc->rl_ldata.rl_rx_list, 1365 sc->rl_ldata.rl_rx_list_map); 1366 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1367 } 1368 1369 /* Unload and free the TX DMA ring memory and map */ 1370 1371 if (sc->rl_ldata.rl_tx_list_tag) { 1372 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1373 sc->rl_ldata.rl_tx_list_map); 1374 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1375 sc->rl_ldata.rl_tx_list, 1376 sc->rl_ldata.rl_tx_list_map); 1377 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1378 } 1379 1380 /* Destroy all the RX and TX buffer maps */ 1381 1382 if (sc->rl_ldata.rl_mtag) { 1383 for (i = 0; i < RL_TX_DESC_CNT; i++) 1384 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1385 sc->rl_ldata.rl_tx_dmamap[i]); 1386 for (i = 0; i < RL_RX_DESC_CNT; i++) 1387 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1388 sc->rl_ldata.rl_rx_dmamap[i]); 1389 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1390 } 1391 1392 /* Unload and free the stats buffer and map */ 1393 1394 if (sc->rl_ldata.rl_stag) { 1395 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1396 sc->rl_ldata.rl_rx_list_map); 1397 bus_dmamem_free(sc->rl_ldata.rl_stag, 1398 sc->rl_ldata.rl_stats, 1399 sc->rl_ldata.rl_smap); 1400 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1401 } 1402 1403 if (sc->rl_parent_tag) 1404 bus_dma_tag_destroy(sc->rl_parent_tag); 1405 1406 RL_UNLOCK(sc); 1407 mtx_destroy(&sc->rl_mtx); 1408 1409 return(0); 1410} 1411 1412static int 1413re_newbuf(sc, idx, m) 1414 struct rl_softc *sc; 1415 int idx; 1416 struct mbuf *m; 1417{ 1418 struct rl_dmaload_arg arg; 1419 struct mbuf *n = NULL; 1420 int error; 1421 1422 if (m == NULL) { 1423 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1424 if (n == NULL) 1425 return(ENOBUFS); 1426 m = n; 1427 } else 1428 m->m_data = m->m_ext.ext_buf; 1429 1430 /* 1431 * Initialize mbuf length fields and fixup 1432 * alignment so that the frame payload is 1433 * longword aligned. 1434 */ 1435 m->m_len = m->m_pkthdr.len = MCLBYTES; 1436 m_adj(m, ETHER_ALIGN); 1437 1438 arg.sc = sc; 1439 arg.rl_idx = idx; 1440 arg.rl_maxsegs = 1; 1441 arg.rl_flags = 0; 1442 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1443 1444 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1445 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1446 &arg, BUS_DMA_NOWAIT); 1447 if (error || arg.rl_maxsegs != 1) { 1448 if (n != NULL) 1449 m_freem(n); 1450 return (ENOMEM); 1451 } 1452 1453 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1454 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1455 1456 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1457 sc->rl_ldata.rl_rx_dmamap[idx], 1458 BUS_DMASYNC_PREREAD); 1459 1460 return(0); 1461} 1462 1463static int 1464re_tx_list_init(sc) 1465 struct rl_softc *sc; 1466{ 1467 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1468 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1469 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1470 1471 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1472 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1473 sc->rl_ldata.rl_tx_prodidx = 0; 1474 sc->rl_ldata.rl_tx_considx = 0; 1475 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1476 1477 return(0); 1478} 1479 1480static int 1481re_rx_list_init(sc) 1482 struct rl_softc *sc; 1483{ 1484 int i; 1485 1486 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1487 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1488 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1489 1490 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1491 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1492 return(ENOBUFS); 1493 } 1494 1495 /* Flush the RX descriptors */ 1496 1497 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1498 sc->rl_ldata.rl_rx_list_map, 1499 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1500 1501 sc->rl_ldata.rl_rx_prodidx = 0; 1502 sc->rl_head = sc->rl_tail = NULL; 1503 1504 return(0); 1505} 1506 1507/* 1508 * RX handler for C+ and 8169. For the gigE chips, we support 1509 * the reception of jumbo frames that have been fragmented 1510 * across multiple 2K mbuf cluster buffers. 1511 */ 1512static void 1513re_rxeof(sc) 1514 struct rl_softc *sc; 1515{ 1516 struct mbuf *m; 1517 struct ifnet *ifp; 1518 int i, total_len; 1519 struct rl_desc *cur_rx; 1520 u_int32_t rxstat, rxvlan; 1521 1522 ifp = &sc->arpcom.ac_if; 1523 i = sc->rl_ldata.rl_rx_prodidx; 1524 1525 /* Invalidate the descriptor memory */ 1526 1527 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1528 sc->rl_ldata.rl_rx_list_map, 1529 BUS_DMASYNC_POSTREAD); 1530 1531 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1532 1533 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1534 m = sc->rl_ldata.rl_rx_mbuf[i]; 1535 total_len = RL_RXBYTES(cur_rx); 1536 rxstat = le32toh(cur_rx->rl_cmdstat); 1537 rxvlan = le32toh(cur_rx->rl_vlanctl); 1538 1539 /* Invalidate the RX mbuf and unload its map */ 1540 1541 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1542 sc->rl_ldata.rl_rx_dmamap[i], 1543 BUS_DMASYNC_POSTWRITE); 1544 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1545 sc->rl_ldata.rl_rx_dmamap[i]); 1546 1547 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1548 m->m_len = MCLBYTES - ETHER_ALIGN; 1549 if (sc->rl_head == NULL) 1550 sc->rl_head = sc->rl_tail = m; 1551 else { 1552 m->m_flags &= ~M_PKTHDR; 1553 sc->rl_tail->m_next = m; 1554 sc->rl_tail = m; 1555 } 1556 re_newbuf(sc, i, NULL); 1557 RL_DESC_INC(i); 1558 continue; 1559 } 1560 1561 /* 1562 * NOTE: for the 8139C+, the frame length field 1563 * is always 12 bits in size, but for the gigE chips, 1564 * it is 13 bits (since the max RX frame length is 16K). 1565 * Unfortunately, all 32 bits in the status word 1566 * were already used, so to make room for the extra 1567 * length bit, RealTek took out the 'frame alignment 1568 * error' bit and shifted the other status bits 1569 * over one slot. The OWN, EOR, FS and LS bits are 1570 * still in the same places. We have already extracted 1571 * the frame length and checked the OWN bit, so rather 1572 * than using an alternate bit mapping, we shift the 1573 * status bits one space to the right so we can evaluate 1574 * them using the 8169 status as though it was in the 1575 * same format as that of the 8139C+. 1576 */ 1577 if (sc->rl_type == RL_8169) 1578 rxstat >>= 1; 1579 1580 if (rxstat & RL_RDESC_STAT_RXERRSUM) { 1581 ifp->if_ierrors++; 1582 /* 1583 * If this is part of a multi-fragment packet, 1584 * discard all the pieces. 1585 */ 1586 if (sc->rl_head != NULL) { 1587 m_freem(sc->rl_head); 1588 sc->rl_head = sc->rl_tail = NULL; 1589 } 1590 re_newbuf(sc, i, m); 1591 RL_DESC_INC(i); 1592 continue; 1593 } 1594 1595 /* 1596 * If allocating a replacement mbuf fails, 1597 * reload the current one. 1598 */ 1599 1600 if (re_newbuf(sc, i, NULL)) { 1601 ifp->if_ierrors++; 1602 if (sc->rl_head != NULL) { 1603 m_freem(sc->rl_head); 1604 sc->rl_head = sc->rl_tail = NULL; 1605 } 1606 re_newbuf(sc, i, m); 1607 RL_DESC_INC(i); 1608 continue; 1609 } 1610 1611 RL_DESC_INC(i); 1612 1613 if (sc->rl_head != NULL) { 1614 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1615 /* 1616 * Special case: if there's 4 bytes or less 1617 * in this buffer, the mbuf can be discarded: 1618 * the last 4 bytes is the CRC, which we don't 1619 * care about anyway. 1620 */ 1621 if (m->m_len <= ETHER_CRC_LEN) { 1622 sc->rl_tail->m_len -= 1623 (ETHER_CRC_LEN - m->m_len); 1624 m_freem(m); 1625 } else { 1626 m->m_len -= ETHER_CRC_LEN; 1627 m->m_flags &= ~M_PKTHDR; 1628 sc->rl_tail->m_next = m; 1629 } 1630 m = sc->rl_head; 1631 sc->rl_head = sc->rl_tail = NULL; 1632 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1633 } else 1634 m->m_pkthdr.len = m->m_len = 1635 (total_len - ETHER_CRC_LEN); 1636 1637 ifp->if_ipackets++; 1638 m->m_pkthdr.rcvif = ifp; 1639 1640 /* Do RX checksumming if enabled */ 1641 1642 if (ifp->if_capenable & IFCAP_RXCSUM) { 1643 1644 /* Check IP header checksum */ 1645 if (rxstat & RL_RDESC_STAT_PROTOID) 1646 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1647 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1648 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1649 1650 /* Check TCP/UDP checksum */ 1651 if ((RL_TCPPKT(rxstat) && 1652 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1653 (RL_UDPPKT(rxstat) && 1654 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1655 m->m_pkthdr.csum_flags |= 1656 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1657 m->m_pkthdr.csum_data = 0xffff; 1658 } 1659 } 1660 1661 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1662 VLAN_INPUT_TAG(ifp, m, 1663 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1664 (*ifp->if_input)(ifp, m); 1665 } 1666 1667 /* Flush the RX DMA ring */ 1668 1669 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1670 sc->rl_ldata.rl_rx_list_map, 1671 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1672 1673 sc->rl_ldata.rl_rx_prodidx = i; 1674 1675 return; 1676} 1677 1678static void 1679re_txeof(sc) 1680 struct rl_softc *sc; 1681{ 1682 struct ifnet *ifp; 1683 u_int32_t txstat; 1684 int idx; 1685 1686 ifp = &sc->arpcom.ac_if; 1687 idx = sc->rl_ldata.rl_tx_considx; 1688 1689 /* Invalidate the TX descriptor list */ 1690 1691 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1692 sc->rl_ldata.rl_tx_list_map, 1693 BUS_DMASYNC_POSTREAD); 1694 1695 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1696 1697 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1698 if (txstat & RL_TDESC_CMD_OWN) 1699 break; 1700 1701 /* 1702 * We only stash mbufs in the last descriptor 1703 * in a fragment chain, which also happens to 1704 * be the only place where the TX status bits 1705 * are valid. 1706 */ 1707 1708 if (txstat & RL_TDESC_CMD_EOF) { 1709 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1710 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1711 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1712 sc->rl_ldata.rl_tx_dmamap[idx]); 1713 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1714 RL_TDESC_STAT_COLCNT)) 1715 ifp->if_collisions++; 1716 if (txstat & RL_TDESC_STAT_TXERRSUM) 1717 ifp->if_oerrors++; 1718 else 1719 ifp->if_opackets++; 1720 } 1721 sc->rl_ldata.rl_tx_free++; 1722 RL_DESC_INC(idx); 1723 } 1724 1725 /* No changes made to the TX ring, so no flush needed */ 1726 1727 if (idx != sc->rl_ldata.rl_tx_considx) { 1728 sc->rl_ldata.rl_tx_considx = idx; 1729 ifp->if_flags &= ~IFF_OACTIVE; 1730 ifp->if_timer = 0; 1731 } 1732 1733 /* 1734 * If not all descriptors have been released reaped yet, 1735 * reload the timer so that we will eventually get another 1736 * interrupt that will cause us to re-enter this routine. 1737 * This is done in case the transmitter has gone idle. 1738 */ 1739 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1740 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1741 1742 return; 1743} 1744 1745static void 1746re_tick(xsc) 1747 void *xsc; 1748{ 1749 struct rl_softc *sc; 1750 struct mii_data *mii; 1751 1752 sc = xsc; 1753 RL_LOCK(sc); 1754 mii = device_get_softc(sc->rl_miibus); 1755 1756 mii_tick(mii); 1757 1758 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1759 RL_UNLOCK(sc); 1760 1761 return; 1762} 1763 1764#ifdef DEVICE_POLLING 1765static void 1766re_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1767{ 1768 struct rl_softc *sc = ifp->if_softc; 1769 1770 RL_LOCK(sc); 1771 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1772 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1773 goto done; 1774 } 1775 1776 sc->rxcycles = count; 1777 re_rxeof(sc); 1778 re_txeof(sc); 1779 1780 if (ifp->if_snd.ifq_head != NULL) 1781 (*ifp->if_start)(ifp); 1782 1783 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1784 u_int16_t status; 1785 1786 status = CSR_READ_2(sc, RL_ISR); 1787 if (status == 0xffff) 1788 goto done; 1789 if (status) 1790 CSR_WRITE_2(sc, RL_ISR, status); 1791 1792 /* 1793 * XXX check behaviour on receiver stalls. 1794 */ 1795 1796 if (status & RL_ISR_SYSTEM_ERR) { 1797 re_reset(sc); 1798 re_init(sc); 1799 } 1800 } 1801done: 1802 RL_UNLOCK(sc); 1803} 1804#endif /* DEVICE_POLLING */ 1805 1806static void 1807re_intr(arg) 1808 void *arg; 1809{ 1810 struct rl_softc *sc; 1811 struct ifnet *ifp; 1812 u_int16_t status; 1813 1814 sc = arg; 1815 1816 if (sc->suspended) { 1817 return; 1818 } 1819 1820 RL_LOCK(sc); 1821 ifp = &sc->arpcom.ac_if; 1822 1823 if (!(ifp->if_flags & IFF_UP)) { 1824 RL_UNLOCK(sc); 1825 return; 1826 } 1827 1828#ifdef DEVICE_POLLING 1829 if (ifp->if_flags & IFF_POLLING) 1830 goto done; 1831 if (ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1832 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1833 re_poll(ifp, 0, 1); 1834 goto done; 1835 } 1836#endif /* DEVICE_POLLING */ 1837 1838 for (;;) { 1839 1840 status = CSR_READ_2(sc, RL_ISR); 1841 /* If the card has gone away the read returns 0xffff. */ 1842 if (status == 0xffff) 1843 break; 1844 if (status) 1845 CSR_WRITE_2(sc, RL_ISR, status); 1846 1847 if ((status & RL_INTRS_CPLUS) == 0) 1848 break; 1849 1850 if (status & RL_ISR_RX_OK) 1851 re_rxeof(sc); 1852 1853 if (status & RL_ISR_RX_ERR) 1854 re_rxeof(sc); 1855 1856 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1857 (status & RL_ISR_TX_ERR) || 1858 (status & RL_ISR_TX_DESC_UNAVAIL)) 1859 re_txeof(sc); 1860 1861 if (status & RL_ISR_SYSTEM_ERR) { 1862 re_reset(sc); 1863 re_init(sc); 1864 } 1865 1866 if (status & RL_ISR_LINKCHG) { 1867 untimeout(re_tick, sc, sc->rl_stat_ch); 1868 re_tick(sc); 1869 } 1870 } 1871 1872 if (ifp->if_snd.ifq_head != NULL) 1873 (*ifp->if_start)(ifp); 1874 1875#ifdef DEVICE_POLLING 1876done: 1877#endif 1878 RL_UNLOCK(sc); 1879 1880 return; 1881} 1882 1883static int 1884re_encap(sc, m_head, idx) 1885 struct rl_softc *sc; 1886 struct mbuf *m_head; 1887 int *idx; 1888{ 1889 struct mbuf *m_new = NULL; 1890 struct rl_dmaload_arg arg; 1891 bus_dmamap_t map; 1892 int error; 1893 struct m_tag *mtag; 1894 1895 if (sc->rl_ldata.rl_tx_free < 4) 1896 return(EFBIG); 1897 1898 /* 1899 * Set up checksum offload. Note: checksum offload bits must 1900 * appear in all descriptors of a multi-descriptor transmit 1901 * attempt. (This is according to testing done with an 8169 1902 * chip. I'm not sure if this is a requirement or a bug.) 1903 */ 1904 1905 arg.rl_flags = 0; 1906 1907 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1908 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1909 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1910 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1911 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1912 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1913 1914 arg.sc = sc; 1915 arg.rl_idx = *idx; 1916 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1917 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1918 1919 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1920 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1921 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1922 1923 if (error && error != EFBIG) { 1924 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1925 return(ENOBUFS); 1926 } 1927 1928 /* Too many segments to map, coalesce into a single mbuf */ 1929 1930 if (error || arg.rl_maxsegs == 0) { 1931 m_new = m_defrag(m_head, M_DONTWAIT); 1932 if (m_new == NULL) 1933 return(1); 1934 else 1935 m_head = m_new; 1936 1937 arg.sc = sc; 1938 arg.rl_idx = *idx; 1939 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1940 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1941 1942 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1943 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1944 if (error) { 1945 printf("re%d: can't map mbuf (error %d)\n", 1946 sc->rl_unit, error); 1947 return(EFBIG); 1948 } 1949 } 1950 1951 /* 1952 * Insure that the map for this transmission 1953 * is placed at the array index of the last descriptor 1954 * in this chain. 1955 */ 1956 sc->rl_ldata.rl_tx_dmamap[*idx] = 1957 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1958 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1959 1960 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head; 1961 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1962 1963 /* 1964 * Set up hardware VLAN tagging. Note: vlan tag info must 1965 * appear in the first descriptor of a multi-descriptor 1966 * transmission attempt. 1967 */ 1968 1969 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1970 if (mtag != NULL) 1971 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1972 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1973 1974 /* Transfer ownership of packet to the chip. */ 1975 1976 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1977 htole32(RL_TDESC_CMD_OWN); 1978 if (*idx != arg.rl_idx) 1979 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1980 htole32(RL_TDESC_CMD_OWN); 1981 1982 RL_DESC_INC(arg.rl_idx); 1983 *idx = arg.rl_idx; 1984 1985 return(0); 1986} 1987 1988/* 1989 * Main transmit routine for C+ and gigE NICs. 1990 */ 1991 1992static void 1993re_start(ifp) 1994 struct ifnet *ifp; 1995{ 1996 struct rl_softc *sc; 1997 struct mbuf *m_head = NULL; 1998 int idx; 1999 2000 sc = ifp->if_softc; 2001 RL_LOCK(sc); 2002 2003 idx = sc->rl_ldata.rl_tx_prodidx; 2004 2005 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2006 IF_DEQUEUE(&ifp->if_snd, m_head); 2007 if (m_head == NULL) 2008 break; 2009 2010 if (re_encap(sc, m_head, &idx)) { 2011 IF_PREPEND(&ifp->if_snd, m_head); 2012 ifp->if_flags |= IFF_OACTIVE; 2013 break; 2014 } 2015 2016 /* 2017 * If there's a BPF listener, bounce a copy of this frame 2018 * to him. 2019 */ 2020 BPF_MTAP(ifp, m_head); 2021 } 2022 2023 /* Flush the TX descriptors */ 2024 2025 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2026 sc->rl_ldata.rl_tx_list_map, 2027 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2028 2029 sc->rl_ldata.rl_tx_prodidx = idx; 2030 2031 /* 2032 * RealTek put the TX poll request register in a different 2033 * location on the 8169 gigE chip. I don't know why. 2034 */ 2035 2036 if (sc->rl_type == RL_8169) 2037 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2038 else 2039 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2040 2041 /* 2042 * Use the countdown timer for interrupt moderation. 2043 * 'TX done' interrupts are disabled. Instead, we reset the 2044 * countdown timer, which will begin counting until it hits 2045 * the value in the TIMERINT register, and then trigger an 2046 * interrupt. Each time we write to the TIMERCNT register, 2047 * the timer count is reset to 0. 2048 */ 2049 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2050 2051 RL_UNLOCK(sc); 2052 2053 /* 2054 * Set a timeout in case the chip goes out to lunch. 2055 */ 2056 ifp->if_timer = 5; 2057 2058 return; 2059} 2060 2061static void 2062re_init(xsc) 2063 void *xsc; 2064{ 2065 struct rl_softc *sc = xsc; 2066 struct ifnet *ifp = &sc->arpcom.ac_if; 2067 struct mii_data *mii; 2068 u_int32_t rxcfg = 0; 2069 2070 RL_LOCK(sc); 2071 mii = device_get_softc(sc->rl_miibus); 2072 2073 /* 2074 * Cancel pending I/O and free all RX/TX buffers. 2075 */ 2076 re_stop(sc); 2077 2078 /* 2079 * Init our MAC address. Even though the chipset 2080 * documentation doesn't mention it, we need to enter "Config 2081 * register write enable" mode to modify the ID registers. 2082 */ 2083 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2084 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2085 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2086 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2087 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2088 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2089 2090 /* 2091 * For C+ mode, initialize the RX descriptors and mbufs. 2092 */ 2093 re_rx_list_init(sc); 2094 re_tx_list_init(sc); 2095 2096 /* 2097 * Enable transmit and receive. 2098 */ 2099 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2100 2101 /* 2102 * Set the initial TX and RX configuration. 2103 */ 2104 if (sc->rl_testmode) { 2105 if (sc->rl_type == RL_8169) 2106 CSR_WRITE_4(sc, RL_TXCFG, 2107 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2108 else 2109 CSR_WRITE_4(sc, RL_TXCFG, 2110 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2111 } else 2112 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2113 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2114 2115 /* Set the individual bit to receive frames for this host only. */ 2116 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2117 rxcfg |= RL_RXCFG_RX_INDIV; 2118 2119 /* If we want promiscuous mode, set the allframes bit. */ 2120 if (ifp->if_flags & IFF_PROMISC) { 2121 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2122 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2123 } else { 2124 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2125 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2126 } 2127 2128 /* 2129 * Set capture broadcast bit to capture broadcast frames. 2130 */ 2131 if (ifp->if_flags & IFF_BROADCAST) { 2132 rxcfg |= RL_RXCFG_RX_BROAD; 2133 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2134 } else { 2135 rxcfg &= ~RL_RXCFG_RX_BROAD; 2136 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2137 } 2138 2139 /* 2140 * Program the multicast filter, if necessary. 2141 */ 2142 re_setmulti(sc); 2143 2144#ifdef DEVICE_POLLING 2145 /* 2146 * Disable interrupts if we are polling. 2147 */ 2148 if (ifp->if_flags & IFF_POLLING) 2149 CSR_WRITE_2(sc, RL_IMR, 0); 2150 else /* otherwise ... */ 2151#endif /* DEVICE_POLLING */ 2152 /* 2153 * Enable interrupts. 2154 */ 2155 if (sc->rl_testmode) 2156 CSR_WRITE_2(sc, RL_IMR, 0); 2157 else 2158 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2159 2160 /* Set initial TX threshold */ 2161 sc->rl_txthresh = RL_TX_THRESH_INIT; 2162 2163 /* Start RX/TX process. */ 2164 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2165#ifdef notdef 2166 /* Enable receiver and transmitter. */ 2167 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2168#endif 2169 /* 2170 * If this is a C+ capable chip, enable C+ RX and TX mode, 2171 * and load the addresses of the RX and TX lists into the chip. 2172 */ 2173 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2174 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2175 RL_CPLUSCMD_VLANSTRIP| 2176 (ifp->if_capenable & IFCAP_RXCSUM ? 2177 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2178 2179 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2180 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2181 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2182 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2183 2184 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2185 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2186 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2187 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2188 2189 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2190 2191 /* 2192 * Initialize the timer interrupt register so that 2193 * a timer interrupt will be generated once the timer 2194 * reaches a certain number of ticks. The timer is 2195 * reloaded on each transmit. This gives us TX interrupt 2196 * moderation, which dramatically improves TX frame rate. 2197 */ 2198 2199 if (sc->rl_type == RL_8169) 2200 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2201 else 2202 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2203 2204 /* 2205 * For 8169 gigE NICs, set the max allowed RX packet 2206 * size so we can receive jumbo frames. 2207 */ 2208 if (sc->rl_type == RL_8169) 2209 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2210 2211 if (sc->rl_testmode) { 2212 RL_UNLOCK(sc); 2213 return; 2214 } 2215 2216 mii_mediachg(mii); 2217 2218 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2219 2220 ifp->if_flags |= IFF_RUNNING; 2221 ifp->if_flags &= ~IFF_OACTIVE; 2222 2223 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2224 RL_UNLOCK(sc); 2225 2226 return; 2227} 2228 2229/* 2230 * Set media options. 2231 */ 2232static int 2233re_ifmedia_upd(ifp) 2234 struct ifnet *ifp; 2235{ 2236 struct rl_softc *sc; 2237 struct mii_data *mii; 2238 2239 sc = ifp->if_softc; 2240 mii = device_get_softc(sc->rl_miibus); 2241 mii_mediachg(mii); 2242 2243 return(0); 2244} 2245 2246/* 2247 * Report current media status. 2248 */ 2249static void 2250re_ifmedia_sts(ifp, ifmr) 2251 struct ifnet *ifp; 2252 struct ifmediareq *ifmr; 2253{ 2254 struct rl_softc *sc; 2255 struct mii_data *mii; 2256 2257 sc = ifp->if_softc; 2258 mii = device_get_softc(sc->rl_miibus); 2259 2260 mii_pollstat(mii); 2261 ifmr->ifm_active = mii->mii_media_active; 2262 ifmr->ifm_status = mii->mii_media_status; 2263 2264 return; 2265} 2266 2267static int 2268re_ioctl(ifp, command, data) 2269 struct ifnet *ifp; 2270 u_long command; 2271 caddr_t data; 2272{ 2273 struct rl_softc *sc = ifp->if_softc; 2274 struct ifreq *ifr = (struct ifreq *) data; 2275 struct mii_data *mii; 2276 int error = 0; 2277 2278 RL_LOCK(sc); 2279 2280 switch(command) { 2281 case SIOCSIFMTU: 2282 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2283 error = EINVAL; 2284 ifp->if_mtu = ifr->ifr_mtu; 2285 break; 2286 case SIOCSIFFLAGS: 2287 if (ifp->if_flags & IFF_UP) { 2288 re_init(sc); 2289 } else { 2290 if (ifp->if_flags & IFF_RUNNING) 2291 re_stop(sc); 2292 } 2293 error = 0; 2294 break; 2295 case SIOCADDMULTI: 2296 case SIOCDELMULTI: 2297 re_setmulti(sc); 2298 error = 0; 2299 break; 2300 case SIOCGIFMEDIA: 2301 case SIOCSIFMEDIA: 2302 mii = device_get_softc(sc->rl_miibus); 2303 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2304 break; 2305 case SIOCSIFCAP: 2306 ifp->if_capenable = ifr->ifr_reqcap; 2307 if (ifp->if_capenable & IFCAP_TXCSUM) 2308 ifp->if_hwassist = RE_CSUM_FEATURES; 2309 else 2310 ifp->if_hwassist = 0; 2311 if (ifp->if_flags & IFF_RUNNING) 2312 re_init(sc); 2313 break; 2314 default: 2315 error = ether_ioctl(ifp, command, data); 2316 break; 2317 } 2318 2319 RL_UNLOCK(sc); 2320 2321 return(error); 2322} 2323 2324static void 2325re_watchdog(ifp) 2326 struct ifnet *ifp; 2327{ 2328 struct rl_softc *sc; 2329 2330 sc = ifp->if_softc; 2331 RL_LOCK(sc); 2332 printf("re%d: watchdog timeout\n", sc->rl_unit); 2333 ifp->if_oerrors++; 2334 2335 re_txeof(sc); 2336 re_rxeof(sc); 2337 2338 re_init(sc); 2339 2340 RL_UNLOCK(sc); 2341 2342 return; 2343} 2344 2345/* 2346 * Stop the adapter and free any mbufs allocated to the 2347 * RX and TX lists. 2348 */ 2349static void 2350re_stop(sc) 2351 struct rl_softc *sc; 2352{ 2353 register int i; 2354 struct ifnet *ifp; 2355 2356 RL_LOCK(sc); 2357 ifp = &sc->arpcom.ac_if; 2358 ifp->if_timer = 0; 2359 2360 untimeout(re_tick, sc, sc->rl_stat_ch); 2361 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2362#ifdef DEVICE_POLLING 2363 ether_poll_deregister(ifp); 2364#endif /* DEVICE_POLLING */ 2365 2366 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2367 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2368 2369 if (sc->rl_head != NULL) { 2370 m_freem(sc->rl_head); 2371 sc->rl_head = sc->rl_tail = NULL; 2372 } 2373 2374 /* Free the TX list buffers. */ 2375 2376 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2377 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2378 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2379 sc->rl_ldata.rl_tx_dmamap[i]); 2380 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2381 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2382 } 2383 } 2384 2385 /* Free the RX list buffers. */ 2386 2387 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2388 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2389 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2390 sc->rl_ldata.rl_rx_dmamap[i]); 2391 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2392 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2393 } 2394 } 2395 2396 RL_UNLOCK(sc); 2397 return; 2398} 2399 2400/* 2401 * Device suspend routine. Stop the interface and save some PCI 2402 * settings in case the BIOS doesn't restore them properly on 2403 * resume. 2404 */ 2405static int 2406re_suspend(dev) 2407 device_t dev; 2408{ 2409 register int i; 2410 struct rl_softc *sc; 2411 2412 sc = device_get_softc(dev); 2413 2414 re_stop(sc); 2415 2416 for (i = 0; i < 5; i++) 2417 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2418 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2419 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2420 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2421 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2422 2423 sc->suspended = 1; 2424 2425 return (0); 2426} 2427 2428/* 2429 * Device resume routine. Restore some PCI settings in case the BIOS 2430 * doesn't, re-enable busmastering, and restart the interface if 2431 * appropriate. 2432 */ 2433static int 2434re_resume(dev) 2435 device_t dev; 2436{ 2437 register int i; 2438 struct rl_softc *sc; 2439 struct ifnet *ifp; 2440 2441 sc = device_get_softc(dev); 2442 ifp = &sc->arpcom.ac_if; 2443 2444 /* better way to do this? */ 2445 for (i = 0; i < 5; i++) 2446 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2447 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2448 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2449 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2450 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2451 2452 /* reenable busmastering */ 2453 pci_enable_busmaster(dev); 2454 pci_enable_io(dev, RL_RES); 2455 2456 /* reinitialize interface if necessary */ 2457 if (ifp->if_flags & IFF_UP) 2458 re_init(sc); 2459 2460 sc->suspended = 0; 2461 2462 return (0); 2463} 2464 2465/* 2466 * Stop all chip I/O so that the kernel's probe routines don't 2467 * get confused by errant DMAs when rebooting. 2468 */ 2469static void 2470re_shutdown(dev) 2471 device_t dev; 2472{ 2473 struct rl_softc *sc; 2474 2475 sc = device_get_softc(dev); 2476 2477 re_stop(sc); 2478 2479 return; 2480} 2481