if_re.c revision 119955
1/* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 35 * 36 * Written by Bill Paul <wpaul@windriver.com> 37 * Senior Networking Software Engineer 38 * Wind River Systems 39 */ 40 41/* 42 * This driver is designed to support RealTek's next generation of 43 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 44 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 45 * and the RTL8110S. 46 * 47 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 48 * with the older 8139 family, however it also supports a special 49 * C+ mode of operation that provides several new performance enhancing 50 * features. These include: 51 * 52 * o Descriptor based DMA mechanism. Each descriptor represents 53 * a single packet fragment. Data buffers may be aligned on 54 * any byte boundary. 55 * 56 * o 64-bit DMA 57 * 58 * o TCP/IP checksum offload for both RX and TX 59 * 60 * o High and normal priority transmit DMA rings 61 * 62 * o VLAN tag insertion and extraction 63 * 64 * o TCP large send (segmentation offload) 65 * 66 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 67 * programming API is fairly straightforward. The RX filtering, EEPROM 68 * access and PHY access is the same as it is on the older 8139 series 69 * chips. 70 * 71 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 72 * same programming API and feature set as the 8139C+ with the following 73 * differences and additions: 74 * 75 * o 1000Mbps mode 76 * 77 * o Jumbo frames 78 * 79 * o GMII and TBI ports/registers for interfacing with copper 80 * or fiber PHYs 81 * 82 * o RX and TX DMA rings can have up to 1024 descriptors 83 * (the 8139C+ allows a maximum of 64) 84 * 85 * o Slight differences in register layout from the 8139C+ 86 * 87 * The TX start and timer interrupt registers are at different locations 88 * on the 8169 than they are on the 8139C+. Also, the status word in the 89 * RX descriptor has a slightly different bit layout. The 8169 does not 90 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 91 * copper gigE PHY. 92 * 93 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 94 * (the 'S' stands for 'single-chip'). These devices have the same 95 * programming API as the older 8169, but also have some vendor-specific 96 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 97 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 98 * 99 * This driver takes advantage of the RX and TX checksum offload and 100 * VLAN tag insertion/extraction features. It also implements TX 101 * interrupt moderation using the timer interrupt registers, which 102 * significantly reduces TX interrupt load. There is also support 103 * for jumbo frames, however the 8169/8169S/8110S can not transmit 104 * jumbo frames larger than 7.5K, so the max MTU possible with this 105 * driver is 7500 bytes. 106 */ 107 108#include <sys/cdefs.h> 109__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 119955 2003-09-10 15:14:46Z wpaul $"); 110 111#include <sys/param.h> 112#include <sys/endian.h> 113#include <sys/systm.h> 114#include <sys/sockio.h> 115#include <sys/mbuf.h> 116#include <sys/malloc.h> 117#include <sys/kernel.h> 118#include <sys/socket.h> 119 120#include <net/if.h> 121#include <net/if_arp.h> 122#include <net/ethernet.h> 123#include <net/if_dl.h> 124#include <net/if_media.h> 125#include <net/if_vlan_var.h> 126 127#include <net/bpf.h> 128 129#include <machine/bus_pio.h> 130#include <machine/bus_memio.h> 131#include <machine/bus.h> 132#include <machine/resource.h> 133#include <sys/bus.h> 134#include <sys/rman.h> 135 136#include <dev/mii/mii.h> 137#include <dev/mii/miivar.h> 138 139#include <dev/pci/pcireg.h> 140#include <dev/pci/pcivar.h> 141 142MODULE_DEPEND(re, pci, 1, 1, 1); 143MODULE_DEPEND(re, ether, 1, 1, 1); 144MODULE_DEPEND(re, miibus, 1, 1, 1); 145 146/* "controller miibus0" required. See GENERIC if you get errors here. */ 147#include "miibus_if.h" 148 149/* 150 * Default to using PIO access for this driver. 151 */ 152#define RE_USEIOSPACE 153 154#include <pci/if_rlreg.h> 155 156#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 157 158/* 159 * Various supported device vendors/types and their names. 160 */ 161static struct rl_type re_devs[] = { 162 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 163 "RealTek 8139C+ 10/100BaseTX" }, 164 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 165 "RealTek 8169 Gigabit Ethernet" }, 166 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 167 "RealTek 8169S Single-chip Gigabit Ethernet" }, 168 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 169 "RealTek 8110S Single-chip Gigabit Ethernet" }, 170 { 0, 0, 0, NULL } 171}; 172 173static struct rl_hwrev re_hwrevs[] = { 174 { RL_HWREV_8139, RL_8139, "" }, 175 { RL_HWREV_8139A, RL_8139, "A" }, 176 { RL_HWREV_8139AG, RL_8139, "A-G" }, 177 { RL_HWREV_8139B, RL_8139, "B" }, 178 { RL_HWREV_8130, RL_8139, "8130" }, 179 { RL_HWREV_8139C, RL_8139, "C" }, 180 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 181 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 182 { RL_HWREV_8169, RL_8169, "8169"}, 183 { RL_HWREV_8169S, RL_8169, "8169S"}, 184 { RL_HWREV_8110S, RL_8169, "8110S"}, 185 { RL_HWREV_8100, RL_8139, "8100"}, 186 { RL_HWREV_8101, RL_8139, "8101"}, 187 { 0, 0, NULL } 188}; 189 190static int re_probe (device_t); 191static int re_attach (device_t); 192static int re_detach (device_t); 193 194static int re_encap (struct rl_softc *, struct mbuf *, int *); 195 196static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 197static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 198 bus_size_t, int); 199static int re_allocmem (device_t, struct rl_softc *); 200static int re_newbuf (struct rl_softc *, int, struct mbuf *); 201static int re_rx_list_init (struct rl_softc *); 202static int re_tx_list_init (struct rl_softc *); 203static void re_rxeof (struct rl_softc *); 204static void re_txeof (struct rl_softc *); 205static void re_intr (void *); 206static void re_tick (void *); 207static void re_start (struct ifnet *); 208static int re_ioctl (struct ifnet *, u_long, caddr_t); 209static void re_init (void *); 210static void re_stop (struct rl_softc *); 211static void re_watchdog (struct ifnet *); 212static int re_suspend (device_t); 213static int re_resume (device_t); 214static void re_shutdown (device_t); 215static int re_ifmedia_upd (struct ifnet *); 216static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 217 218static void re_eeprom_putbyte (struct rl_softc *, int); 219static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 220static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 221static int re_gmii_readreg (device_t, int, int); 222static int re_gmii_writereg (device_t, int, int, int); 223 224static int re_miibus_readreg (device_t, int, int); 225static int re_miibus_writereg (device_t, int, int, int); 226static void re_miibus_statchg (device_t); 227 228static u_int8_t re_calchash (caddr_t); 229static void re_setmulti (struct rl_softc *); 230static void re_reset (struct rl_softc *); 231 232static int re_diag (struct rl_softc *); 233 234#ifdef RE_USEIOSPACE 235#define RL_RES SYS_RES_IOPORT 236#define RL_RID RL_PCI_LOIO 237#else 238#define RL_RES SYS_RES_MEMORY 239#define RL_RID RL_PCI_LOMEM 240#endif 241 242static device_method_t re_methods[] = { 243 /* Device interface */ 244 DEVMETHOD(device_probe, re_probe), 245 DEVMETHOD(device_attach, re_attach), 246 DEVMETHOD(device_detach, re_detach), 247 DEVMETHOD(device_suspend, re_suspend), 248 DEVMETHOD(device_resume, re_resume), 249 DEVMETHOD(device_shutdown, re_shutdown), 250 251 /* bus interface */ 252 DEVMETHOD(bus_print_child, bus_generic_print_child), 253 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 254 255 /* MII interface */ 256 DEVMETHOD(miibus_readreg, re_miibus_readreg), 257 DEVMETHOD(miibus_writereg, re_miibus_writereg), 258 DEVMETHOD(miibus_statchg, re_miibus_statchg), 259 260 { 0, 0 } 261}; 262 263static driver_t re_driver = { 264 "re", 265 re_methods, 266 sizeof(struct rl_softc) 267}; 268 269static devclass_t re_devclass; 270 271DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 272DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 273DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 274 275#define EE_SET(x) \ 276 CSR_WRITE_1(sc, RL_EECMD, \ 277 CSR_READ_1(sc, RL_EECMD) | x) 278 279#define EE_CLR(x) \ 280 CSR_WRITE_1(sc, RL_EECMD, \ 281 CSR_READ_1(sc, RL_EECMD) & ~x) 282 283/* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286static void 287re_eeprom_putbyte(sc, addr) 288 struct rl_softc *sc; 289 int addr; 290{ 291 register int d, i; 292 293 d = addr | sc->rl_eecmd_read; 294 295 /* 296 * Feed in each bit and strobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 EE_SET(RL_EE_DATAIN); 301 } else { 302 EE_CLR(RL_EE_DATAIN); 303 } 304 DELAY(100); 305 EE_SET(RL_EE_CLK); 306 DELAY(150); 307 EE_CLR(RL_EE_CLK); 308 DELAY(100); 309 } 310 311 return; 312} 313 314/* 315 * Read a word of data stored in the EEPROM at address 'addr.' 316 */ 317static void 318re_eeprom_getword(sc, addr, dest) 319 struct rl_softc *sc; 320 int addr; 321 u_int16_t *dest; 322{ 323 register int i; 324 u_int16_t word = 0; 325 326 /* Enter EEPROM access mode. */ 327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 328 329 /* 330 * Send address of word we want to read. 331 */ 332 re_eeprom_putbyte(sc, addr); 333 334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 335 336 /* 337 * Start reading bits from EEPROM. 338 */ 339 for (i = 0x8000; i; i >>= 1) { 340 EE_SET(RL_EE_CLK); 341 DELAY(100); 342 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 343 word |= i; 344 EE_CLR(RL_EE_CLK); 345 DELAY(100); 346 } 347 348 /* Turn off EEPROM access mode. */ 349 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 350 351 *dest = word; 352 353 return; 354} 355 356/* 357 * Read a sequence of words from the EEPROM. 358 */ 359static void 360re_read_eeprom(sc, dest, off, cnt, swap) 361 struct rl_softc *sc; 362 caddr_t dest; 363 int off; 364 int cnt; 365 int swap; 366{ 367 int i; 368 u_int16_t word = 0, *ptr; 369 370 for (i = 0; i < cnt; i++) { 371 re_eeprom_getword(sc, off + i, &word); 372 ptr = (u_int16_t *)(dest + (i * 2)); 373 if (swap) 374 *ptr = ntohs(word); 375 else 376 *ptr = word; 377 } 378 379 return; 380} 381 382static int 383re_gmii_readreg(dev, phy, reg) 384 device_t dev; 385 int phy, reg; 386{ 387 struct rl_softc *sc; 388 u_int32_t rval; 389 int i; 390 391 if (phy != 1) 392 return(0); 393 394 sc = device_get_softc(dev); 395 396 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 397 DELAY(1000); 398 399 for (i = 0; i < RL_TIMEOUT; i++) { 400 rval = CSR_READ_4(sc, RL_PHYAR); 401 if (rval & RL_PHYAR_BUSY) 402 break; 403 DELAY(100); 404 } 405 406 if (i == RL_TIMEOUT) { 407 printf ("re%d: PHY read failed\n", sc->rl_unit); 408 return (0); 409 } 410 411 return (rval & RL_PHYAR_PHYDATA); 412} 413 414static int 415re_gmii_writereg(dev, phy, reg, data) 416 device_t dev; 417 int phy, reg, data; 418{ 419 struct rl_softc *sc; 420 u_int32_t rval; 421 int i; 422 423 sc = device_get_softc(dev); 424 425 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 426 (data | RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 427 DELAY(1000); 428 429 for (i = 0; i < RL_TIMEOUT; i++) { 430 rval = CSR_READ_4(sc, RL_PHYAR); 431 if (!(rval & RL_PHYAR_BUSY)) 432 break; 433 DELAY(100); 434 } 435 436 if (i == RL_TIMEOUT) { 437 printf ("re%d: PHY write failed\n", sc->rl_unit); 438 return (0); 439 } 440 441 return (0); 442} 443 444static int 445re_miibus_readreg(dev, phy, reg) 446 device_t dev; 447 int phy, reg; 448{ 449 struct rl_softc *sc; 450 u_int16_t rval = 0; 451 u_int16_t re8139_reg = 0; 452 453 sc = device_get_softc(dev); 454 RL_LOCK(sc); 455 456 if (sc->rl_type == RL_8169) { 457 rval = re_gmii_readreg(dev, phy, reg); 458 RL_UNLOCK(sc); 459 return (rval); 460 } 461 462 /* Pretend the internal PHY is only at address 0 */ 463 if (phy) { 464 RL_UNLOCK(sc); 465 return(0); 466 } 467 switch(reg) { 468 case MII_BMCR: 469 re8139_reg = RL_BMCR; 470 break; 471 case MII_BMSR: 472 re8139_reg = RL_BMSR; 473 break; 474 case MII_ANAR: 475 re8139_reg = RL_ANAR; 476 break; 477 case MII_ANER: 478 re8139_reg = RL_ANER; 479 break; 480 case MII_ANLPAR: 481 re8139_reg = RL_LPAR; 482 break; 483 case MII_PHYIDR1: 484 case MII_PHYIDR2: 485 RL_UNLOCK(sc); 486 return(0); 487 /* 488 * Allow the rlphy driver to read the media status 489 * register. If we have a link partner which does not 490 * support NWAY, this is the register which will tell 491 * us the results of parallel detection. 492 */ 493 case RL_MEDIASTAT: 494 rval = CSR_READ_1(sc, RL_MEDIASTAT); 495 RL_UNLOCK(sc); 496 return(rval); 497 default: 498 printf("re%d: bad phy register\n", sc->rl_unit); 499 RL_UNLOCK(sc); 500 return(0); 501 } 502 rval = CSR_READ_2(sc, re8139_reg); 503 RL_UNLOCK(sc); 504 return(rval); 505} 506 507static int 508re_miibus_writereg(dev, phy, reg, data) 509 device_t dev; 510 int phy, reg, data; 511{ 512 struct rl_softc *sc; 513 u_int16_t re8139_reg = 0; 514 int rval = 0; 515 516 sc = device_get_softc(dev); 517 RL_LOCK(sc); 518 519 if (sc->rl_type == RL_8169) { 520 rval = re_gmii_writereg(dev, phy, reg, data); 521 RL_UNLOCK(sc); 522 return (rval); 523 } 524 525 /* Pretend the internal PHY is only at address 0 */ 526 if (phy) { 527 RL_UNLOCK(sc); 528 return(0); 529 } 530 switch(reg) { 531 case MII_BMCR: 532 re8139_reg = RL_BMCR; 533 break; 534 case MII_BMSR: 535 re8139_reg = RL_BMSR; 536 break; 537 case MII_ANAR: 538 re8139_reg = RL_ANAR; 539 break; 540 case MII_ANER: 541 re8139_reg = RL_ANER; 542 break; 543 case MII_ANLPAR: 544 re8139_reg = RL_LPAR; 545 break; 546 case MII_PHYIDR1: 547 case MII_PHYIDR2: 548 RL_UNLOCK(sc); 549 return(0); 550 break; 551 default: 552 printf("re%d: bad phy register\n", sc->rl_unit); 553 RL_UNLOCK(sc); 554 return(0); 555 } 556 CSR_WRITE_2(sc, re8139_reg, data); 557 RL_UNLOCK(sc); 558 return(0); 559} 560 561static void 562re_miibus_statchg(dev) 563 device_t dev; 564{ 565 return; 566} 567 568/* 569 * Calculate CRC of a multicast group address, return the upper 6 bits. 570 */ 571static u_int8_t 572re_calchash(addr) 573 caddr_t addr; 574{ 575 u_int32_t crc, carry; 576 int i, j; 577 u_int8_t c; 578 579 /* Compute CRC for the address value. */ 580 crc = 0xFFFFFFFF; /* initial value */ 581 582 for (i = 0; i < 6; i++) { 583 c = *(addr + i); 584 for (j = 0; j < 8; j++) { 585 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 586 crc <<= 1; 587 c >>= 1; 588 if (carry) 589 crc = (crc ^ 0x04c11db6) | carry; 590 } 591 } 592 593 /* return the filter bit position */ 594 return(crc >> 26); 595} 596 597/* 598 * Program the 64-bit multicast hash filter. 599 */ 600static void 601re_setmulti(sc) 602 struct rl_softc *sc; 603{ 604 struct ifnet *ifp; 605 int h = 0; 606 u_int32_t hashes[2] = { 0, 0 }; 607 struct ifmultiaddr *ifma; 608 u_int32_t rxfilt; 609 int mcnt = 0; 610 611 ifp = &sc->arpcom.ac_if; 612 613 rxfilt = CSR_READ_4(sc, RL_RXCFG); 614 615 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 616 rxfilt |= RL_RXCFG_RX_MULTI; 617 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 618 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 619 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 620 return; 621 } 622 623 /* first, zot all the existing hash bits */ 624 CSR_WRITE_4(sc, RL_MAR0, 0); 625 CSR_WRITE_4(sc, RL_MAR4, 0); 626 627 /* now program new ones */ 628 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 629 if (ifma->ifma_addr->sa_family != AF_LINK) 630 continue; 631 h = re_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 632 if (h < 32) 633 hashes[0] |= (1 << h); 634 else 635 hashes[1] |= (1 << (h - 32)); 636 mcnt++; 637 } 638 639 if (mcnt) 640 rxfilt |= RL_RXCFG_RX_MULTI; 641 else 642 rxfilt &= ~RL_RXCFG_RX_MULTI; 643 644 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 645 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 646 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 647 648 return; 649} 650 651static void 652re_reset(sc) 653 struct rl_softc *sc; 654{ 655 register int i; 656 657 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 658 659 for (i = 0; i < RL_TIMEOUT; i++) { 660 DELAY(10); 661 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 662 break; 663 } 664 if (i == RL_TIMEOUT) 665 printf("re%d: reset never completed!\n", sc->rl_unit); 666 667 CSR_WRITE_1(sc, 0x82, 1); 668 669 return; 670} 671 672/* 673 * The following routine is designed to test for a defect on some 674 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 675 * lines connected to the bus, however for a 32-bit only card, they 676 * should be pulled high. The result of this defect is that the 677 * NIC will not work right if you plug it into a 64-bit slot: DMA 678 * operations will be done with 64-bit transfers, which will fail 679 * because the 64-bit data lines aren't connected. 680 * 681 * There's no way to work around this (short of talking a soldering 682 * iron to the board), however we can detect it. The method we use 683 * here is to put the NIC into digital loopback mode, set the receiver 684 * to promiscuous mode, and then try to send a frame. We then compare 685 * the frame data we sent to what was received. If the data matches, 686 * then the NIC is working correctly, otherwise we know the user has 687 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 688 * slot. In the latter case, there's no way the NIC can work correctly, 689 * so we print out a message on the console and abort the device attach. 690 */ 691 692static int 693re_diag(sc) 694 struct rl_softc *sc; 695{ 696 struct ifnet *ifp = &sc->arpcom.ac_if; 697 struct mbuf *m0; 698 struct ether_header *eh; 699 struct rl_desc *cur_rx; 700 u_int16_t status; 701 u_int32_t rxstat; 702 int total_len, i, error = 0; 703 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 704 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 705 706 /* Allocate a single mbuf */ 707 708 MGETHDR(m0, M_DONTWAIT, MT_DATA); 709 if (m0 == NULL) 710 return(ENOBUFS); 711 712 /* 713 * Initialize the NIC in test mode. This sets the chip up 714 * so that it can send and receive frames, but performs the 715 * following special functions: 716 * - Puts receiver in promiscuous mode 717 * - Enables digital loopback mode 718 * - Leaves interrupts turned off 719 */ 720 721 ifp->if_flags |= IFF_PROMISC; 722 sc->rl_testmode = 1; 723 re_init(sc); 724 725 /* Put some data in the mbuf */ 726 727 eh = mtod(m0, struct ether_header *); 728 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 729 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 730 eh->ether_type = htons(ETHERTYPE_IP); 731 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 732 733 /* Queue the packet, start transmission */ 734 735 IF_HANDOFF(&ifp->if_snd, m0, ifp); 736 re_start(ifp); 737 m0 = NULL; 738 739 /* Wait for it to propagate through the chip */ 740 741 for (i = 0; i < RL_TIMEOUT; i++) { 742 status = CSR_READ_2(sc, RL_ISR); 743 if (status & RL_ISR_RX_OK) 744 break; 745 DELAY(10); 746 } 747 748 if (i == RL_TIMEOUT) { 749 printf("re%d: diagnostic failed, failed to receive packet " 750 "in loopback mode\n", sc->rl_unit); 751 error = EIO; 752 goto done; 753 } 754 755 /* 756 * The packet should have been dumped into the first 757 * entry in the RX DMA ring. Grab it from there. 758 */ 759 760 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 761 sc->rl_ldata.rl_rx_list_map, 762 BUS_DMASYNC_POSTREAD); 763 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 764 sc->rl_ldata.rl_rx_dmamap[0], 765 BUS_DMASYNC_POSTWRITE); 766 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 767 sc->rl_ldata.rl_rx_dmamap[0]); 768 769 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 770 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 771 eh = mtod(m0, struct ether_header *); 772 773 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 774 total_len = RL_RXBYTES(cur_rx); 775 rxstat = le32toh(cur_rx->rl_cmdstat); 776 777 if (total_len != ETHER_MIN_LEN) { 778 printf("re%d: diagnostic failed, received short packet\n", 779 sc->rl_unit); 780 error = EIO; 781 goto done; 782 } 783 784 /* Test that the received packet data matches what we sent. */ 785 786 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 787 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 788 ntohs(eh->ether_type) != ETHERTYPE_IP) { 789 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 790 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 791 dst, ":", src, ":", ETHERTYPE_IP); 792 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 793 eh->ether_dhost, ":", eh->ether_shost, ":", 794 ntohs(eh->ether_type)); 795 printf("re%d: You may have a defective 32-bit NIC plugged " 796 "into a 64-bit PCI slot.\n", sc->rl_unit); 797 printf("re%d: Please re-install the NIC in a 32-bit slot " 798 "for proper operation.\n", sc->rl_unit); 799 printf("re%d: Read the re(4) man page for more details.\n", 800 sc->rl_unit); 801 error = EIO; 802 } 803 804done: 805 /* Turn interface off, release resources */ 806 807 sc->rl_testmode = 0; 808 ifp->if_flags &= ~IFF_PROMISC; 809 re_stop(sc); 810 if (m0 != NULL) 811 m_freem(m0); 812 813 return (error); 814} 815 816/* 817 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 818 * IDs against our list and return a device name if we find a match. 819 */ 820static int 821re_probe(dev) 822 device_t dev; 823{ 824 struct rl_type *t; 825 struct rl_softc *sc; 826 int rid; 827 u_int32_t hwrev; 828 829 t = re_devs; 830 sc = device_get_softc(dev); 831 832 while(t->rl_name != NULL) { 833 if ((pci_get_vendor(dev) == t->rl_vid) && 834 (pci_get_device(dev) == t->rl_did)) { 835 836 /* 837 * Temporarily map the I/O space 838 * so we can read the chip ID register. 839 */ 840 rid = RL_RID; 841 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 842 0, ~0, 1, RF_ACTIVE); 843 if (sc->rl_res == NULL) { 844 device_printf(dev, 845 "couldn't map ports/memory\n"); 846 return(ENXIO); 847 } 848 sc->rl_btag = rman_get_bustag(sc->rl_res); 849 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 850 mtx_init(&sc->rl_mtx, 851 device_get_nameunit(dev), 852 MTX_NETWORK_LOCK, MTX_DEF); 853 RL_LOCK(sc); 854 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 855 bus_release_resource(dev, RL_RES, 856 RL_RID, sc->rl_res); 857 RL_UNLOCK(sc); 858 mtx_destroy(&sc->rl_mtx); 859 if (t->rl_basetype == hwrev) { 860 device_set_desc(dev, t->rl_name); 861 return(0); 862 } 863 } 864 t++; 865 } 866 867 return(ENXIO); 868} 869 870/* 871 * This routine takes the segment list provided as the result of 872 * a bus_dma_map_load() operation and assigns the addresses/lengths 873 * to RealTek DMA descriptors. This can be called either by the RX 874 * code or the TX code. In the RX case, we'll probably wind up mapping 875 * at most one segment. For the TX case, there could be any number of 876 * segments since TX packets may span multiple mbufs. In either case, 877 * if the number of segments is larger than the rl_maxsegs limit 878 * specified by the caller, we abort the mapping operation. Sadly, 879 * whoever designed the buffer mapping API did not provide a way to 880 * return an error from here, so we have to fake it a bit. 881 */ 882 883static void 884re_dma_map_desc(arg, segs, nseg, mapsize, error) 885 void *arg; 886 bus_dma_segment_t *segs; 887 int nseg; 888 bus_size_t mapsize; 889 int error; 890{ 891 struct rl_dmaload_arg *ctx; 892 struct rl_desc *d = NULL; 893 int i = 0, idx; 894 895 if (error) 896 return; 897 898 ctx = arg; 899 900 /* Signal error to caller if there's too many segments */ 901 if (nseg > ctx->rl_maxsegs) { 902 ctx->rl_maxsegs = 0; 903 return; 904 } 905 906 /* 907 * Map the segment array into descriptors. Note that we set the 908 * start-of-frame and end-of-frame markers for either TX or RX, but 909 * they really only have meaning in the TX case. (In the RX case, 910 * it's the chip that tells us where packets begin and end.) 911 * We also keep track of the end of the ring and set the 912 * end-of-ring bits as needed, and we set the ownership bits 913 * in all except the very first descriptor. (The caller will 914 * set this descriptor later when it start transmission or 915 * reception.) 916 */ 917 idx = ctx->rl_idx; 918 while(1) { 919 u_int32_t cmdstat; 920 d = &ctx->rl_ring[idx]; 921 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 922 ctx->rl_maxsegs = 0; 923 return; 924 } 925 cmdstat = segs[i].ds_len; 926 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 927 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 928 if (i == 0) 929 cmdstat |= RL_TDESC_CMD_SOF; 930 else 931 cmdstat |= RL_TDESC_CMD_OWN; 932 if (idx == (RL_RX_DESC_CNT - 1)) 933 cmdstat |= RL_TDESC_CMD_EOR; 934 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 935 i++; 936 if (i == nseg) 937 break; 938 RL_DESC_INC(idx); 939 } 940 941 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 942 ctx->rl_maxsegs = nseg; 943 ctx->rl_idx = idx; 944 945 return; 946} 947 948/* 949 * Map a single buffer address. 950 */ 951 952static void 953re_dma_map_addr(arg, segs, nseg, error) 954 void *arg; 955 bus_dma_segment_t *segs; 956 int nseg; 957 int error; 958{ 959 u_int32_t *addr; 960 961 if (error) 962 return; 963 964 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 965 addr = arg; 966 *addr = segs->ds_addr; 967 968 return; 969} 970 971static int 972re_allocmem(dev, sc) 973 device_t dev; 974 struct rl_softc *sc; 975{ 976 int error; 977 int nseg; 978 int i; 979 980 /* 981 * Allocate map for RX mbufs. 982 */ 983 nseg = 32; 984 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 985 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 986 NULL, MCLBYTES * nseg, nseg, RL_JLEN, BUS_DMA_ALLOCNOW, 987 NULL, NULL, &sc->rl_ldata.rl_mtag); 988 if (error) { 989 device_printf(dev, "could not allocate dma tag\n"); 990 return (ENOMEM); 991 } 992 993 /* 994 * Allocate map for TX descriptor list. 995 */ 996 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 997 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 998 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 999 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1000 if (error) { 1001 device_printf(dev, "could not allocate dma tag\n"); 1002 return (ENOMEM); 1003 } 1004 1005 /* Allocate DMA'able memory for the TX ring */ 1006 1007 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1008 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1009 &sc->rl_ldata.rl_tx_list_map); 1010 if (error) 1011 return (ENOMEM); 1012 1013 /* Load the map for the TX ring. */ 1014 1015 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1016 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1017 RL_TX_LIST_SZ, re_dma_map_addr, 1018 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1019 1020 /* Create DMA maps for TX buffers */ 1021 1022 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1023 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1024 &sc->rl_ldata.rl_tx_dmamap[i]); 1025 if (error) { 1026 device_printf(dev, "can't create DMA map for TX\n"); 1027 return(ENOMEM); 1028 } 1029 } 1030 1031 /* 1032 * Allocate map for RX descriptor list. 1033 */ 1034 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1035 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1036 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1037 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1038 if (error) { 1039 device_printf(dev, "could not allocate dma tag\n"); 1040 return (ENOMEM); 1041 } 1042 1043 /* Allocate DMA'able memory for the RX ring */ 1044 1045 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1046 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1047 &sc->rl_ldata.rl_rx_list_map); 1048 if (error) 1049 return (ENOMEM); 1050 1051 /* Load the map for the RX ring. */ 1052 1053 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1054 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1055 RL_TX_LIST_SZ, re_dma_map_addr, 1056 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1057 1058 /* Create DMA maps for RX buffers */ 1059 1060 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1061 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1062 &sc->rl_ldata.rl_rx_dmamap[i]); 1063 if (error) { 1064 device_printf(dev, "can't create DMA map for RX\n"); 1065 return(ENOMEM); 1066 } 1067 } 1068 1069 return(0); 1070} 1071 1072/* 1073 * Attach the interface. Allocate softc structures, do ifmedia 1074 * setup and ethernet/BPF attach. 1075 */ 1076static int 1077re_attach(dev) 1078 device_t dev; 1079{ 1080 u_char eaddr[ETHER_ADDR_LEN]; 1081 u_int16_t as[3]; 1082 struct rl_softc *sc; 1083 struct ifnet *ifp; 1084 struct rl_hwrev *hw_rev; 1085 int hwrev; 1086 u_int16_t re_did = 0; 1087 int unit, error = 0, rid, i; 1088 1089 sc = device_get_softc(dev); 1090 unit = device_get_unit(dev); 1091 1092 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1093 MTX_DEF | MTX_RECURSE); 1094#ifndef BURN_BRIDGES 1095 /* 1096 * Handle power management nonsense. 1097 */ 1098 1099 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1100 u_int32_t iobase, membase, irq; 1101 1102 /* Save important PCI config data. */ 1103 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 1104 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 1105 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 1106 1107 /* Reset the power state. */ 1108 printf("re%d: chip is is in D%d power mode " 1109 "-- setting to D0\n", unit, 1110 pci_get_powerstate(dev)); 1111 1112 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1113 1114 /* Restore PCI config data. */ 1115 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 1116 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 1117 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 1118 } 1119#endif 1120 /* 1121 * Map control/status registers. 1122 */ 1123 pci_enable_busmaster(dev); 1124 1125 rid = RL_RID; 1126 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 1127 0, ~0, 1, RF_ACTIVE); 1128 1129 if (sc->rl_res == NULL) { 1130 printf ("re%d: couldn't map ports/memory\n", unit); 1131 error = ENXIO; 1132 goto fail; 1133 } 1134 1135 sc->rl_btag = rman_get_bustag(sc->rl_res); 1136 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1137 1138 /* Allocate interrupt */ 1139 rid = 0; 1140 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1141 RF_SHAREABLE | RF_ACTIVE); 1142 1143 if (sc->rl_irq == NULL) { 1144 printf("re%d: couldn't map interrupt\n", unit); 1145 error = ENXIO; 1146 goto fail; 1147 } 1148 1149 /* Reset the adapter. */ 1150 re_reset(sc); 1151 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1152 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1153 if (re_did != 0x8129) 1154 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1155 1156 /* 1157 * Get station address from the EEPROM. 1158 */ 1159 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1160 for (i = 0; i < 3; i++) { 1161 eaddr[(i * 2) + 0] = as[i] & 0xff; 1162 eaddr[(i * 2) + 1] = as[i] >> 8; 1163 } 1164 1165 /* 1166 * A RealTek chip was detected. Inform the world. 1167 */ 1168 printf("re%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1169 1170 sc->rl_unit = unit; 1171 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1172 1173 hw_rev = re_hwrevs; 1174 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1175 while (hw_rev->rl_desc != NULL) { 1176 if (hw_rev->rl_rev == hwrev) { 1177 sc->rl_type = hw_rev->rl_type; 1178 break; 1179 } 1180 hw_rev++; 1181 } 1182 1183 /* 1184 * Allocate the parent bus DMA tag appropriate for PCI. 1185 */ 1186#define RL_NSEG_NEW 32 1187 error = bus_dma_tag_create(NULL, /* parent */ 1188 1, 0, /* alignment, boundary */ 1189 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1190 BUS_SPACE_MAXADDR, /* highaddr */ 1191 NULL, NULL, /* filter, filterarg */ 1192 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1193 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1194 BUS_DMA_ALLOCNOW, /* flags */ 1195 NULL, NULL, /* lockfunc, lockarg */ 1196 &sc->rl_parent_tag); 1197 if (error) 1198 goto fail; 1199 1200 error = re_allocmem(dev, sc); 1201 1202 if (error) 1203 goto fail; 1204 1205 /* Do MII setup */ 1206 if (mii_phy_probe(dev, &sc->rl_miibus, 1207 re_ifmedia_upd, re_ifmedia_sts)) { 1208 printf("re%d: MII without any phy!\n", sc->rl_unit); 1209 error = ENXIO; 1210 goto fail; 1211 } 1212 1213 ifp = &sc->arpcom.ac_if; 1214 ifp->if_softc = sc; 1215 ifp->if_unit = unit; 1216 ifp->if_name = "re"; 1217 ifp->if_mtu = ETHERMTU; 1218 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1219 ifp->if_ioctl = re_ioctl; 1220 ifp->if_output = ether_output; 1221 ifp->if_capabilities = IFCAP_VLAN_MTU; 1222 ifp->if_start = re_start; 1223 ifp->if_hwassist = RE_CSUM_FEATURES; 1224 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1225 ifp->if_watchdog = re_watchdog; 1226 ifp->if_init = re_init; 1227 if (sc->rl_type == RL_8169) 1228 ifp->if_baudrate = 1000000000; 1229 else 1230 ifp->if_baudrate = 100000000; 1231 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; 1232 ifp->if_capenable = ifp->if_capabilities; 1233 1234 callout_handle_init(&sc->rl_stat_ch); 1235 1236 /* 1237 * Call MI attach routine. 1238 */ 1239 ether_ifattach(ifp, eaddr); 1240 1241 /* Perform hardware diagnostic. */ 1242 error = re_diag(sc); 1243 1244 if (error) { 1245 printf("re%d: attach aborted due to hardware diag failure\n", 1246 unit); 1247 ether_ifdetach(ifp); 1248 goto fail; 1249 } 1250 1251 /* Hook interrupt last to avoid having to lock softc */ 1252 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1253 re_intr, sc, &sc->rl_intrhand); 1254 1255 if (error) { 1256 printf("re%d: couldn't set up irq\n", unit); 1257 ether_ifdetach(ifp); 1258 goto fail; 1259 } 1260 1261fail: 1262 if (error) 1263 re_detach(dev); 1264 1265 return (error); 1266} 1267 1268/* 1269 * Shutdown hardware and free up resources. This can be called any 1270 * time after the mutex has been initialized. It is called in both 1271 * the error case in attach and the normal detach case so it needs 1272 * to be careful about only freeing resources that have actually been 1273 * allocated. 1274 */ 1275static int 1276re_detach(dev) 1277 device_t dev; 1278{ 1279 struct rl_softc *sc; 1280 struct ifnet *ifp; 1281 int i; 1282 1283 sc = device_get_softc(dev); 1284 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1285 RL_LOCK(sc); 1286 ifp = &sc->arpcom.ac_if; 1287 1288 /* These should only be active if attach succeeded */ 1289 if (device_is_attached(dev)) { 1290 re_stop(sc); 1291 /* 1292 * Force off the IFF_UP flag here, in case someone 1293 * still had a BPF descriptor attached to this 1294 * interface. If they do, ether_ifattach() will cause 1295 * the BPF code to try and clear the promisc mode 1296 * flag, which will bubble down to re_ioctl(), 1297 * which will try to call re_init() again. This will 1298 * turn the NIC back on and restart the MII ticker, 1299 * which will panic the system when the kernel tries 1300 * to invoke the re_tick() function that isn't there 1301 * anymore. 1302 */ 1303 ifp->if_flags &= ~IFF_UP; 1304 ether_ifdetach(ifp); 1305 } 1306 if (sc->rl_miibus) 1307 device_delete_child(dev, sc->rl_miibus); 1308 bus_generic_detach(dev); 1309 1310 if (sc->rl_intrhand) 1311 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1312 if (sc->rl_irq) 1313 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1314 if (sc->rl_res) 1315 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1316 1317 1318 /* Unload and free the RX DMA ring memory and map */ 1319 1320 if (sc->rl_ldata.rl_rx_list_tag) { 1321 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1322 sc->rl_ldata.rl_rx_list_map); 1323 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1324 sc->rl_ldata.rl_rx_list, 1325 sc->rl_ldata.rl_rx_list_map); 1326 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1327 } 1328 1329 /* Unload and free the TX DMA ring memory and map */ 1330 1331 if (sc->rl_ldata.rl_tx_list_tag) { 1332 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1333 sc->rl_ldata.rl_tx_list_map); 1334 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1335 sc->rl_ldata.rl_tx_list, 1336 sc->rl_ldata.rl_tx_list_map); 1337 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1338 } 1339 1340 /* Destroy all the RX and TX buffer maps */ 1341 1342 if (sc->rl_ldata.rl_mtag) { 1343 for (i = 0; i < RL_TX_DESC_CNT; i++) 1344 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1345 sc->rl_ldata.rl_tx_dmamap[i]); 1346 for (i = 0; i < RL_RX_DESC_CNT; i++) 1347 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1348 sc->rl_ldata.rl_rx_dmamap[i]); 1349 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1350 } 1351 1352 /* Unload and free the stats buffer and map */ 1353 1354 if (sc->rl_ldata.rl_stag) { 1355 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1356 sc->rl_ldata.rl_rx_list_map); 1357 bus_dmamem_free(sc->rl_ldata.rl_stag, 1358 sc->rl_ldata.rl_stats, 1359 sc->rl_ldata.rl_smap); 1360 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1361 } 1362 1363 if (sc->rl_parent_tag) 1364 bus_dma_tag_destroy(sc->rl_parent_tag); 1365 1366 RL_UNLOCK(sc); 1367 mtx_destroy(&sc->rl_mtx); 1368 1369 return(0); 1370} 1371 1372static int 1373re_newbuf(sc, idx, m) 1374 struct rl_softc *sc; 1375 int idx; 1376 struct mbuf *m; 1377{ 1378 struct rl_dmaload_arg arg; 1379 struct mbuf *n = NULL; 1380 int error; 1381 1382 if (m == NULL) { 1383 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1384 if (n == NULL) 1385 return(ENOBUFS); 1386 m = n; 1387 } else 1388 m->m_data = m->m_ext.ext_buf; 1389 1390 /* 1391 * Initialize mbuf length fields and fixup 1392 * alignment so that the frame payload is 1393 * longword aligned. 1394 */ 1395 m->m_len = m->m_pkthdr.len = MCLBYTES; 1396 m_adj(m, ETHER_ALIGN); 1397 1398 arg.sc = sc; 1399 arg.rl_idx = idx; 1400 arg.rl_maxsegs = 1; 1401 arg.rl_flags = 0; 1402 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1403 1404 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1405 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1406 &arg, BUS_DMA_NOWAIT); 1407 if (error || arg.rl_maxsegs != 1) { 1408 if (n != NULL) 1409 m_freem(n); 1410 return (ENOMEM); 1411 } 1412 1413 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1414 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1415 1416 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1417 sc->rl_ldata.rl_rx_dmamap[idx], 1418 BUS_DMASYNC_PREREAD); 1419 1420 return(0); 1421} 1422 1423static int 1424re_tx_list_init(sc) 1425 struct rl_softc *sc; 1426{ 1427 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1428 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1429 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1430 1431 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1432 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1433 sc->rl_ldata.rl_tx_prodidx = 0; 1434 sc->rl_ldata.rl_tx_considx = 0; 1435 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1436 1437 return(0); 1438} 1439 1440static int 1441re_rx_list_init(sc) 1442 struct rl_softc *sc; 1443{ 1444 int i; 1445 1446 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1447 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1448 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1449 1450 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1451 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1452 return(ENOBUFS); 1453 } 1454 1455 /* Flush the RX descriptors */ 1456 1457 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1458 sc->rl_ldata.rl_rx_list_map, 1459 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1460 1461 sc->rl_ldata.rl_rx_prodidx = 0; 1462 sc->rl_head = sc->rl_tail = NULL; 1463 1464 return(0); 1465} 1466 1467/* 1468 * RX handler for C+ and 8169. For the gigE chips, we support 1469 * the reception of jumbo frames that have been fragmented 1470 * across multiple 2K mbuf cluster buffers. 1471 */ 1472static void 1473re_rxeof(sc) 1474 struct rl_softc *sc; 1475{ 1476 struct mbuf *m; 1477 struct ifnet *ifp; 1478 int i, total_len; 1479 struct rl_desc *cur_rx; 1480 u_int32_t rxstat, rxvlan; 1481 1482 ifp = &sc->arpcom.ac_if; 1483 i = sc->rl_ldata.rl_rx_prodidx; 1484 1485 /* Invalidate the descriptor memory */ 1486 1487 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1488 sc->rl_ldata.rl_rx_list_map, 1489 BUS_DMASYNC_POSTREAD); 1490 1491 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1492 1493 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1494 m = sc->rl_ldata.rl_rx_mbuf[i]; 1495 total_len = RL_RXBYTES(cur_rx); 1496 rxstat = le32toh(cur_rx->rl_cmdstat); 1497 rxvlan = le32toh(cur_rx->rl_vlanctl); 1498 1499 /* Invalidate the RX mbuf and unload its map */ 1500 1501 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1502 sc->rl_ldata.rl_rx_dmamap[i], 1503 BUS_DMASYNC_POSTWRITE); 1504 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1505 sc->rl_ldata.rl_rx_dmamap[i]); 1506 1507 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1508 m->m_len = MCLBYTES - ETHER_ALIGN; 1509 if (sc->rl_head == NULL) 1510 sc->rl_head = sc->rl_tail = m; 1511 else { 1512 m->m_flags &= ~M_PKTHDR; 1513 sc->rl_tail->m_next = m; 1514 sc->rl_tail = m; 1515 } 1516 re_newbuf(sc, i, NULL); 1517 RL_DESC_INC(i); 1518 continue; 1519 } 1520 1521 /* 1522 * NOTE: for the 8139C+, the frame length field 1523 * is always 12 bits in size, but for the gigE chips, 1524 * it is 13 bits (since the max RX frame length is 16K). 1525 * Unfortunately, all 32 bits in the status word 1526 * were already used, so to make room for the extra 1527 * length bit, RealTek took out the 'frame alignment 1528 * error' bit and shifted the other status bits 1529 * over one slot. The OWN, EOR, FS and LS bits are 1530 * still in the same places. We have already extracted 1531 * the frame length and checked the OWN bit, so rather 1532 * than using an alternate bit mapping, we shift the 1533 * status bits one space to the right so we can evaluate 1534 * them using the 8169 status as though it was in the 1535 * same format as that of the 8139C+. 1536 */ 1537 if (sc->rl_type == RL_8169) 1538 rxstat >>= 1; 1539 1540 if (rxstat & RL_RDESC_STAT_RXERRSUM) { 1541 ifp->if_ierrors++; 1542 /* 1543 * If this is part of a multi-fragment packet, 1544 * discard all the pieces. 1545 */ 1546 if (sc->rl_head != NULL) { 1547 m_freem(sc->rl_head); 1548 sc->rl_head = sc->rl_tail = NULL; 1549 } 1550 re_newbuf(sc, i, m); 1551 RL_DESC_INC(i); 1552 continue; 1553 } 1554 1555 /* 1556 * If allocating a replacement mbuf fails, 1557 * reload the current one. 1558 */ 1559 1560 if (re_newbuf(sc, i, NULL)) { 1561 ifp->if_ierrors++; 1562 if (sc->rl_head != NULL) { 1563 m_freem(sc->rl_head); 1564 sc->rl_head = sc->rl_tail = NULL; 1565 } 1566 re_newbuf(sc, i, m); 1567 RL_DESC_INC(i); 1568 continue; 1569 } 1570 1571 RL_DESC_INC(i); 1572 1573 if (sc->rl_head != NULL) { 1574 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1575 /* 1576 * Special case: if there's 4 bytes or less 1577 * in this buffer, the mbuf can be discarded: 1578 * the last 4 bytes is the CRC, which we don't 1579 * care about anyway. 1580 */ 1581 if (m->m_len <= ETHER_CRC_LEN) { 1582 sc->rl_tail->m_len -= 1583 (ETHER_CRC_LEN - m->m_len); 1584 m_freem(m); 1585 } else { 1586 m->m_len -= ETHER_CRC_LEN; 1587 m->m_flags &= ~M_PKTHDR; 1588 sc->rl_tail->m_next = m; 1589 } 1590 m = sc->rl_head; 1591 sc->rl_head = sc->rl_tail = NULL; 1592 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1593 } else 1594 m->m_pkthdr.len = m->m_len = 1595 (total_len - ETHER_CRC_LEN); 1596 1597 ifp->if_ipackets++; 1598 m->m_pkthdr.rcvif = ifp; 1599 1600 /* Do RX checksumming if enabled */ 1601 1602 if (ifp->if_capenable & IFCAP_RXCSUM) { 1603 1604 /* Check IP header checksum */ 1605 if (rxstat & RL_RDESC_STAT_PROTOID) 1606 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1607 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1608 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1609 1610 /* Check TCP/UDP checksum */ 1611 if ((RL_TCPPKT(rxstat) && 1612 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1613 (RL_UDPPKT(rxstat) && 1614 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1615 m->m_pkthdr.csum_flags |= 1616 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1617 m->m_pkthdr.csum_data = 0xffff; 1618 } 1619 } 1620 1621 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1622 VLAN_INPUT_TAG(ifp, m, 1623 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1624 (*ifp->if_input)(ifp, m); 1625 } 1626 1627 /* Flush the RX DMA ring */ 1628 1629 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1630 sc->rl_ldata.rl_rx_list_map, 1631 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1632 1633 sc->rl_ldata.rl_rx_prodidx = i; 1634 1635 return; 1636} 1637 1638static void 1639re_txeof(sc) 1640 struct rl_softc *sc; 1641{ 1642 struct ifnet *ifp; 1643 u_int32_t txstat; 1644 int idx; 1645 1646 ifp = &sc->arpcom.ac_if; 1647 idx = sc->rl_ldata.rl_tx_considx; 1648 1649 /* Invalidate the TX descriptor list */ 1650 1651 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1652 sc->rl_ldata.rl_tx_list_map, 1653 BUS_DMASYNC_POSTREAD); 1654 1655 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1656 1657 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1658 if (txstat & RL_TDESC_CMD_OWN) 1659 break; 1660 1661 /* 1662 * We only stash mbufs in the last descriptor 1663 * in a fragment chain, which also happens to 1664 * be the only place where the TX status bits 1665 * are valid. 1666 */ 1667 1668 if (txstat & RL_TDESC_CMD_EOF) { 1669 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1670 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1671 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1672 sc->rl_ldata.rl_tx_dmamap[idx]); 1673 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1674 RL_TDESC_STAT_COLCNT)) 1675 ifp->if_collisions++; 1676 if (txstat & RL_TDESC_STAT_TXERRSUM) 1677 ifp->if_oerrors++; 1678 else 1679 ifp->if_opackets++; 1680 } 1681 sc->rl_ldata.rl_tx_free++; 1682 RL_DESC_INC(idx); 1683 } 1684 1685 /* No changes made to the TX ring, so no flush needed */ 1686 1687 if (idx != sc->rl_ldata.rl_tx_considx) { 1688 sc->rl_ldata.rl_tx_considx = idx; 1689 ifp->if_flags &= ~IFF_OACTIVE; 1690 ifp->if_timer = 0; 1691 } 1692 1693 /* 1694 * If not all descriptors have been released reaped yet, 1695 * reload the timer so that we will eventually get another 1696 * interrupt that will cause us to re-enter this routine. 1697 * This is done in case the transmitter has gone idle. 1698 */ 1699 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1700 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1701 1702 return; 1703} 1704 1705static void 1706re_tick(xsc) 1707 void *xsc; 1708{ 1709 struct rl_softc *sc; 1710 struct mii_data *mii; 1711 1712 sc = xsc; 1713 RL_LOCK(sc); 1714 mii = device_get_softc(sc->rl_miibus); 1715 1716 mii_tick(mii); 1717 1718 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1719 RL_UNLOCK(sc); 1720 1721 return; 1722} 1723 1724#ifdef DEVICE_POLLING 1725static void 1726re_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1727{ 1728 struct rl_softc *sc = ifp->if_softc; 1729 1730 RL_LOCK(sc); 1731 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1732 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1733 goto done; 1734 } 1735 1736 sc->rxcycles = count; 1737 re_rxeof(sc); 1738 re_txeof(sc); 1739 1740 if (ifp->if_snd.ifq_head != NULL) 1741 (*ifp->if_start)(ifp); 1742 1743 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1744 u_int16_t status; 1745 1746 status = CSR_READ_2(sc, RL_ISR); 1747 if (status == 0xffff) 1748 goto done; 1749 if (status) 1750 CSR_WRITE_2(sc, RL_ISR, status); 1751 1752 /* 1753 * XXX check behaviour on receiver stalls. 1754 */ 1755 1756 if (status & RL_ISR_SYSTEM_ERR) { 1757 re_reset(sc); 1758 re_init(sc); 1759 } 1760 } 1761done: 1762 RL_UNLOCK(sc); 1763} 1764#endif /* DEVICE_POLLING */ 1765 1766static void 1767re_intr(arg) 1768 void *arg; 1769{ 1770 struct rl_softc *sc; 1771 struct ifnet *ifp; 1772 u_int16_t status; 1773 1774 sc = arg; 1775 1776 if (sc->suspended) { 1777 return; 1778 } 1779 1780 RL_LOCK(sc); 1781 ifp = &sc->arpcom.ac_if; 1782 1783#ifdef DEVICE_POLLING 1784 if (ifp->if_flags & IFF_POLLING) 1785 goto done; 1786 if (ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1787 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1788 re_poll(ifp, 0, 1); 1789 goto done; 1790 } 1791#endif /* DEVICE_POLLING */ 1792 1793 for (;;) { 1794 1795 status = CSR_READ_2(sc, RL_ISR); 1796 /* If the card has gone away the read returns 0xffff. */ 1797 if (status == 0xffff) 1798 break; 1799 if (status) 1800 CSR_WRITE_2(sc, RL_ISR, status); 1801 1802 if ((status & RL_INTRS_CPLUS) == 0) 1803 break; 1804 1805 if (status & RL_ISR_RX_OK) 1806 re_rxeof(sc); 1807 1808 if (status & RL_ISR_RX_ERR) 1809 re_rxeof(sc); 1810 1811 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1812 (status & RL_ISR_TX_ERR) || 1813 (status & RL_ISR_TX_DESC_UNAVAIL)) 1814 re_txeof(sc); 1815 1816 if (status & RL_ISR_SYSTEM_ERR) { 1817 re_reset(sc); 1818 re_init(sc); 1819 } 1820 1821 if (status & RL_ISR_LINKCHG) { 1822 untimeout(re_tick, sc, sc->rl_stat_ch); 1823 re_tick(sc); 1824 } 1825 } 1826 1827 if (ifp->if_snd.ifq_head != NULL) 1828 (*ifp->if_start)(ifp); 1829 1830#ifdef DEVICE_POLLING 1831done: 1832#endif 1833 RL_UNLOCK(sc); 1834 1835 return; 1836} 1837 1838static int 1839re_encap(sc, m_head, idx) 1840 struct rl_softc *sc; 1841 struct mbuf *m_head; 1842 int *idx; 1843{ 1844 struct mbuf *m_new = NULL; 1845 struct rl_dmaload_arg arg; 1846 bus_dmamap_t map; 1847 int error; 1848 struct m_tag *mtag; 1849 1850 if (sc->rl_ldata.rl_tx_free < 4) 1851 return(EFBIG); 1852 1853 /* 1854 * Set up checksum offload. Note: checksum offload bits must 1855 * appear in all descriptors of a multi-descriptor transmit 1856 * attempt. (This is according to testing done with an 8169 1857 * chip. I'm not sure if this is a requirement or a bug.) 1858 */ 1859 1860 arg.rl_flags = 0; 1861 1862 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1863 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1864 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1865 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1866 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1867 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1868 1869 arg.sc = sc; 1870 arg.rl_idx = *idx; 1871 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1872 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1873 1874 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1875 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1876 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1877 1878 if (error && error != EFBIG) { 1879 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1880 return(ENOBUFS); 1881 } 1882 1883 /* Too many segments to map, coalesce into a single mbuf */ 1884 1885 if (error || arg.rl_maxsegs == 0) { 1886 m_new = m_defrag(m_head, M_DONTWAIT); 1887 if (m_new == NULL) 1888 return(1); 1889 else 1890 m_head = m_new; 1891 1892 arg.sc = sc; 1893 arg.rl_idx = *idx; 1894 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1895 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1896 1897 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1898 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1899 if (error) { 1900 printf("re%d: can't map mbuf (error %d)\n", 1901 sc->rl_unit, error); 1902 return(EFBIG); 1903 } 1904 } 1905 1906 /* 1907 * Insure that the map for this transmission 1908 * is placed at the array index of the last descriptor 1909 * in this chain. 1910 */ 1911 sc->rl_ldata.rl_tx_dmamap[*idx] = 1912 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1913 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1914 1915 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head; 1916 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1917 1918 /* 1919 * Set up hardware VLAN tagging. Note: vlan tag info must 1920 * appear in the first descriptor of a multi-descriptor 1921 * transmission attempt. 1922 */ 1923 1924 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1925 if (mtag != NULL) 1926 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1927 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1928 1929 /* Transfer ownership of packet to the chip. */ 1930 1931 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1932 htole32(RL_TDESC_CMD_OWN); 1933 if (*idx != arg.rl_idx) 1934 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1935 htole32(RL_TDESC_CMD_OWN); 1936 1937 RL_DESC_INC(arg.rl_idx); 1938 *idx = arg.rl_idx; 1939 1940 return(0); 1941} 1942 1943/* 1944 * Main transmit routine for C+ and gigE NICs. 1945 */ 1946 1947static void 1948re_start(ifp) 1949 struct ifnet *ifp; 1950{ 1951 struct rl_softc *sc; 1952 struct mbuf *m_head = NULL; 1953 int idx; 1954 1955 sc = ifp->if_softc; 1956 RL_LOCK(sc); 1957 1958 idx = sc->rl_ldata.rl_tx_prodidx; 1959 1960 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 1961 IF_DEQUEUE(&ifp->if_snd, m_head); 1962 if (m_head == NULL) 1963 break; 1964 1965 if (re_encap(sc, m_head, &idx)) { 1966 IF_PREPEND(&ifp->if_snd, m_head); 1967 ifp->if_flags |= IFF_OACTIVE; 1968 break; 1969 } 1970 1971 /* 1972 * If there's a BPF listener, bounce a copy of this frame 1973 * to him. 1974 */ 1975 BPF_MTAP(ifp, m_head); 1976 } 1977 1978 /* Flush the TX descriptors */ 1979 1980 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1981 sc->rl_ldata.rl_tx_list_map, 1982 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1983 1984 sc->rl_ldata.rl_tx_prodidx = idx; 1985 1986 /* 1987 * RealTek put the TX poll request register in a different 1988 * location on the 8169 gigE chip. I don't know why. 1989 */ 1990 1991 if (sc->rl_type == RL_8169) 1992 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 1993 else 1994 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 1995 1996 /* 1997 * Use the countdown timer for interrupt moderation. 1998 * 'TX done' interrupts are disabled. Instead, we reset the 1999 * countdown timer, which will begin counting until it hits 2000 * the value in the TIMERINT register, and then trigger an 2001 * interrupt. Each time we write to the TIMERCNT register, 2002 * the timer count is reset to 0. 2003 */ 2004 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2005 2006 RL_UNLOCK(sc); 2007 2008 /* 2009 * Set a timeout in case the chip goes out to lunch. 2010 */ 2011 ifp->if_timer = 5; 2012 2013 return; 2014} 2015 2016static void 2017re_init(xsc) 2018 void *xsc; 2019{ 2020 struct rl_softc *sc = xsc; 2021 struct ifnet *ifp = &sc->arpcom.ac_if; 2022 struct mii_data *mii; 2023 u_int32_t rxcfg = 0; 2024 2025 RL_LOCK(sc); 2026 mii = device_get_softc(sc->rl_miibus); 2027 2028 /* 2029 * Cancel pending I/O and free all RX/TX buffers. 2030 */ 2031 re_stop(sc); 2032 2033 /* 2034 * Init our MAC address. Even though the chipset 2035 * documentation doesn't mention it, we need to enter "Config 2036 * register write enable" mode to modify the ID registers. 2037 */ 2038 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2039 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2040 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2041 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2042 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2043 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2044 2045 /* 2046 * For C+ mode, initialize the RX descriptors and mbufs. 2047 */ 2048 re_rx_list_init(sc); 2049 re_tx_list_init(sc); 2050 2051 /* 2052 * Enable transmit and receive. 2053 */ 2054 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2055 2056 /* 2057 * Set the initial TX and RX configuration. 2058 */ 2059 if (sc->rl_testmode) 2060 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2061 else 2062 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2063 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2064 2065 /* Set the individual bit to receive frames for this host only. */ 2066 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2067 rxcfg |= RL_RXCFG_RX_INDIV; 2068 2069 /* If we want promiscuous mode, set the allframes bit. */ 2070 if (ifp->if_flags & IFF_PROMISC) { 2071 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2072 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2073 } else { 2074 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2075 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2076 } 2077 2078 /* 2079 * Set capture broadcast bit to capture broadcast frames. 2080 */ 2081 if (ifp->if_flags & IFF_BROADCAST) { 2082 rxcfg |= RL_RXCFG_RX_BROAD; 2083 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2084 } else { 2085 rxcfg &= ~RL_RXCFG_RX_BROAD; 2086 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2087 } 2088 2089 /* 2090 * Program the multicast filter, if necessary. 2091 */ 2092 re_setmulti(sc); 2093 2094#ifdef DEVICE_POLLING 2095 /* 2096 * Disable interrupts if we are polling. 2097 */ 2098 if (ifp->if_flags & IFF_POLLING) 2099 CSR_WRITE_2(sc, RL_IMR, 0); 2100 else /* otherwise ... */ 2101#endif /* DEVICE_POLLING */ 2102 /* 2103 * Enable interrupts. 2104 */ 2105 if (sc->rl_testmode) 2106 CSR_WRITE_2(sc, RL_IMR, 0); 2107 else 2108 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2109 2110 /* Set initial TX threshold */ 2111 sc->rl_txthresh = RL_TX_THRESH_INIT; 2112 2113 /* Start RX/TX process. */ 2114 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2115#ifdef notdef 2116 /* Enable receiver and transmitter. */ 2117 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2118#endif 2119 /* 2120 * If this is a C+ capable chip, enable C+ RX and TX mode, 2121 * and load the addresses of the RX and TX lists into the chip. 2122 */ 2123 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2124 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2125 RL_CPLUSCMD_VLANSTRIP| 2126 (ifp->if_capenable & IFCAP_RXCSUM ? 2127 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2128 2129 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2130 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2131 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2132 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2133 2134 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2135 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2136 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2137 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2138 2139 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2140 2141 /* 2142 * Initialize the timer interrupt register so that 2143 * a timer interrupt will be generated once the timer 2144 * reaches a certain number of ticks. The timer is 2145 * reloaded on each transmit. This gives us TX interrupt 2146 * moderation, which dramatically improves TX frame rate. 2147 */ 2148 2149 if (sc->rl_type == RL_8169) 2150 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2151 else 2152 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2153 2154 /* 2155 * For 8169 gigE NICs, set the max allowed RX packet 2156 * size so we can receive jumbo frames. 2157 */ 2158 if (sc->rl_type == RL_8169) 2159 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2160 2161 if (sc->rl_testmode) { 2162 RL_UNLOCK(sc); 2163 return; 2164 } 2165 2166 mii_mediachg(mii); 2167 2168 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2169 2170 ifp->if_flags |= IFF_RUNNING; 2171 ifp->if_flags &= ~IFF_OACTIVE; 2172 2173 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2174 RL_UNLOCK(sc); 2175 2176 return; 2177} 2178 2179/* 2180 * Set media options. 2181 */ 2182static int 2183re_ifmedia_upd(ifp) 2184 struct ifnet *ifp; 2185{ 2186 struct rl_softc *sc; 2187 struct mii_data *mii; 2188 2189 sc = ifp->if_softc; 2190 mii = device_get_softc(sc->rl_miibus); 2191 mii_mediachg(mii); 2192 2193 return(0); 2194} 2195 2196/* 2197 * Report current media status. 2198 */ 2199static void 2200re_ifmedia_sts(ifp, ifmr) 2201 struct ifnet *ifp; 2202 struct ifmediareq *ifmr; 2203{ 2204 struct rl_softc *sc; 2205 struct mii_data *mii; 2206 2207 sc = ifp->if_softc; 2208 mii = device_get_softc(sc->rl_miibus); 2209 2210 mii_pollstat(mii); 2211 ifmr->ifm_active = mii->mii_media_active; 2212 ifmr->ifm_status = mii->mii_media_status; 2213 2214 return; 2215} 2216 2217static int 2218re_ioctl(ifp, command, data) 2219 struct ifnet *ifp; 2220 u_long command; 2221 caddr_t data; 2222{ 2223 struct rl_softc *sc = ifp->if_softc; 2224 struct ifreq *ifr = (struct ifreq *) data; 2225 struct mii_data *mii; 2226 int error = 0; 2227 2228 RL_LOCK(sc); 2229 2230 switch(command) { 2231 case SIOCSIFMTU: 2232 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2233 error = EINVAL; 2234 ifp->if_mtu = ifr->ifr_mtu; 2235 break; 2236 case SIOCSIFFLAGS: 2237 if (ifp->if_flags & IFF_UP) { 2238 re_init(sc); 2239 } else { 2240 if (ifp->if_flags & IFF_RUNNING) 2241 re_stop(sc); 2242 } 2243 error = 0; 2244 break; 2245 case SIOCADDMULTI: 2246 case SIOCDELMULTI: 2247 re_setmulti(sc); 2248 error = 0; 2249 break; 2250 case SIOCGIFMEDIA: 2251 case SIOCSIFMEDIA: 2252 mii = device_get_softc(sc->rl_miibus); 2253 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2254 break; 2255 case SIOCSIFCAP: 2256 ifp->if_capenable = ifr->ifr_reqcap; 2257 if (ifp->if_capenable & IFCAP_TXCSUM) 2258 ifp->if_hwassist = RE_CSUM_FEATURES; 2259 else 2260 ifp->if_hwassist = 0; 2261 if (ifp->if_flags & IFF_RUNNING) 2262 re_init(sc); 2263 break; 2264 default: 2265 error = ether_ioctl(ifp, command, data); 2266 break; 2267 } 2268 2269 RL_UNLOCK(sc); 2270 2271 return(error); 2272} 2273 2274static void 2275re_watchdog(ifp) 2276 struct ifnet *ifp; 2277{ 2278 struct rl_softc *sc; 2279 2280 sc = ifp->if_softc; 2281 RL_LOCK(sc); 2282 printf("re%d: watchdog timeout\n", sc->rl_unit); 2283 ifp->if_oerrors++; 2284 2285 re_txeof(sc); 2286 re_rxeof(sc); 2287 2288 re_init(sc); 2289 2290 RL_UNLOCK(sc); 2291 2292 return; 2293} 2294 2295/* 2296 * Stop the adapter and free any mbufs allocated to the 2297 * RX and TX lists. 2298 */ 2299static void 2300re_stop(sc) 2301 struct rl_softc *sc; 2302{ 2303 register int i; 2304 struct ifnet *ifp; 2305 2306 RL_LOCK(sc); 2307 ifp = &sc->arpcom.ac_if; 2308 ifp->if_timer = 0; 2309 2310 untimeout(re_tick, sc, sc->rl_stat_ch); 2311 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2312#ifdef DEVICE_POLLING 2313 ether_poll_deregister(ifp); 2314#endif /* DEVICE_POLLING */ 2315 2316 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2317 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2318 2319 if (sc->rl_head != NULL) { 2320 m_freem(sc->rl_head); 2321 sc->rl_head = sc->rl_tail = NULL; 2322 } 2323 2324 /* Free the TX list buffers. */ 2325 2326 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2327 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2328 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2329 sc->rl_ldata.rl_tx_dmamap[i]); 2330 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2331 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2332 } 2333 } 2334 2335 /* Free the RX list buffers. */ 2336 2337 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2338 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2339 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2340 sc->rl_ldata.rl_rx_dmamap[i]); 2341 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2342 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2343 } 2344 } 2345 2346 RL_UNLOCK(sc); 2347 return; 2348} 2349 2350/* 2351 * Device suspend routine. Stop the interface and save some PCI 2352 * settings in case the BIOS doesn't restore them properly on 2353 * resume. 2354 */ 2355static int 2356re_suspend(dev) 2357 device_t dev; 2358{ 2359 register int i; 2360 struct rl_softc *sc; 2361 2362 sc = device_get_softc(dev); 2363 2364 re_stop(sc); 2365 2366 for (i = 0; i < 5; i++) 2367 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2368 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2369 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2370 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2371 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2372 2373 sc->suspended = 1; 2374 2375 return (0); 2376} 2377 2378/* 2379 * Device resume routine. Restore some PCI settings in case the BIOS 2380 * doesn't, re-enable busmastering, and restart the interface if 2381 * appropriate. 2382 */ 2383static int 2384re_resume(dev) 2385 device_t dev; 2386{ 2387 register int i; 2388 struct rl_softc *sc; 2389 struct ifnet *ifp; 2390 2391 sc = device_get_softc(dev); 2392 ifp = &sc->arpcom.ac_if; 2393 2394 /* better way to do this? */ 2395 for (i = 0; i < 5; i++) 2396 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2397 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2398 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2399 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2400 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2401 2402 /* reenable busmastering */ 2403 pci_enable_busmaster(dev); 2404 pci_enable_io(dev, RL_RES); 2405 2406 /* reinitialize interface if necessary */ 2407 if (ifp->if_flags & IFF_UP) 2408 re_init(sc); 2409 2410 sc->suspended = 0; 2411 2412 return (0); 2413} 2414 2415/* 2416 * Stop all chip I/O so that the kernel's probe routines don't 2417 * get confused by errant DMAs when rebooting. 2418 */ 2419static void 2420re_shutdown(dev) 2421 device_t dev; 2422{ 2423 struct rl_softc *sc; 2424 2425 sc = device_get_softc(dev); 2426 2427 re_stop(sc); 2428 2429 return; 2430} 2431