rt2661.c revision 211314
1/* $FreeBSD: head/sys/dev/ral/rt2661.c 211314 2010-08-14 20:12:10Z bschmidt $ */ 2 3/*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2661.c 211314 2010-08-14 20:12:10Z bschmidt $"); 22 23/*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_arp.h> 50#include <net/ethernet.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54 55#include <net80211/ieee80211_var.h> 56#include <net80211/ieee80211_radiotap.h> 57#include <net80211/ieee80211_regdomain.h> 58#include <net80211/ieee80211_ratectl.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/in_var.h> 63#include <netinet/ip.h> 64#include <netinet/if_ether.h> 65 66#include <dev/ral/rt2661reg.h> 67#include <dev/ral/rt2661var.h> 68 69#define RAL_DEBUG 70#ifdef RAL_DEBUG 71#define DPRINTF(sc, fmt, ...) do { \ 72 if (sc->sc_debug > 0) \ 73 printf(fmt, __VA_ARGS__); \ 74} while (0) 75#define DPRINTFN(sc, n, fmt, ...) do { \ 76 if (sc->sc_debug >= (n)) \ 77 printf(fmt, __VA_ARGS__); \ 78} while (0) 79#else 80#define DPRINTF(sc, fmt, ...) 81#define DPRINTFN(sc, n, fmt, ...) 82#endif 83 84static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 85 const char name[IFNAMSIZ], int unit, int opmode, 86 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 87 const uint8_t mac[IEEE80211_ADDR_LEN]); 88static void rt2661_vap_delete(struct ieee80211vap *); 89static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 90 int); 91static int rt2661_alloc_tx_ring(struct rt2661_softc *, 92 struct rt2661_tx_ring *, int); 93static void rt2661_reset_tx_ring(struct rt2661_softc *, 94 struct rt2661_tx_ring *); 95static void rt2661_free_tx_ring(struct rt2661_softc *, 96 struct rt2661_tx_ring *); 97static int rt2661_alloc_rx_ring(struct rt2661_softc *, 98 struct rt2661_rx_ring *, int); 99static void rt2661_reset_rx_ring(struct rt2661_softc *, 100 struct rt2661_rx_ring *); 101static void rt2661_free_rx_ring(struct rt2661_softc *, 102 struct rt2661_rx_ring *); 103static void rt2661_newassoc(struct ieee80211_node *, int); 104static int rt2661_newstate(struct ieee80211vap *, 105 enum ieee80211_state, int); 106static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 107static void rt2661_rx_intr(struct rt2661_softc *); 108static void rt2661_tx_intr(struct rt2661_softc *); 109static void rt2661_tx_dma_intr(struct rt2661_softc *, 110 struct rt2661_tx_ring *); 111static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 112static void rt2661_mcu_wakeup(struct rt2661_softc *); 113static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 114static void rt2661_scan_start(struct ieee80211com *); 115static void rt2661_scan_end(struct ieee80211com *); 116static void rt2661_set_channel(struct ieee80211com *); 117static void rt2661_setup_tx_desc(struct rt2661_softc *, 118 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 119 int, const bus_dma_segment_t *, int, int); 120static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 121 struct ieee80211_node *, int); 122static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 123 struct ieee80211_node *); 124static void rt2661_start_locked(struct ifnet *); 125static void rt2661_start(struct ifnet *); 126static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 127 const struct ieee80211_bpf_params *); 128static void rt2661_watchdog(void *); 129static int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 130static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 131 uint8_t); 132static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 133static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 134 uint32_t); 135static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 136 uint16_t); 137static void rt2661_select_antenna(struct rt2661_softc *); 138static void rt2661_enable_mrr(struct rt2661_softc *); 139static void rt2661_set_txpreamble(struct rt2661_softc *); 140static void rt2661_set_basicrates(struct rt2661_softc *, 141 const struct ieee80211_rateset *); 142static void rt2661_select_band(struct rt2661_softc *, 143 struct ieee80211_channel *); 144static void rt2661_set_chan(struct rt2661_softc *, 145 struct ieee80211_channel *); 146static void rt2661_set_bssid(struct rt2661_softc *, 147 const uint8_t *); 148static void rt2661_set_macaddr(struct rt2661_softc *, 149 const uint8_t *); 150static void rt2661_update_promisc(struct ifnet *); 151static int rt2661_wme_update(struct ieee80211com *) __unused; 152static void rt2661_update_slot(struct ifnet *); 153static const char *rt2661_get_rf(int); 154static void rt2661_read_eeprom(struct rt2661_softc *, 155 uint8_t macaddr[IEEE80211_ADDR_LEN]); 156static int rt2661_bbp_init(struct rt2661_softc *); 157static void rt2661_init_locked(struct rt2661_softc *); 158static void rt2661_init(void *); 159static void rt2661_stop_locked(struct rt2661_softc *); 160static void rt2661_stop(void *); 161static int rt2661_load_microcode(struct rt2661_softc *); 162#ifdef notyet 163static void rt2661_rx_tune(struct rt2661_softc *); 164static void rt2661_radar_start(struct rt2661_softc *); 165static int rt2661_radar_stop(struct rt2661_softc *); 166#endif 167static int rt2661_prepare_beacon(struct rt2661_softc *, 168 struct ieee80211vap *); 169static void rt2661_enable_tsf_sync(struct rt2661_softc *); 170static void rt2661_enable_tsf(struct rt2661_softc *); 171static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 172 173static const struct { 174 uint32_t reg; 175 uint32_t val; 176} rt2661_def_mac[] = { 177 RT2661_DEF_MAC 178}; 179 180static const struct { 181 uint8_t reg; 182 uint8_t val; 183} rt2661_def_bbp[] = { 184 RT2661_DEF_BBP 185}; 186 187static const struct rfprog { 188 uint8_t chan; 189 uint32_t r1, r2, r3, r4; 190} rt2661_rf5225_1[] = { 191 RT2661_RF5225_1 192}, rt2661_rf5225_2[] = { 193 RT2661_RF5225_2 194}; 195 196int 197rt2661_attach(device_t dev, int id) 198{ 199 struct rt2661_softc *sc = device_get_softc(dev); 200 struct ieee80211com *ic; 201 struct ifnet *ifp; 202 uint32_t val; 203 int error, ac, ntries; 204 uint8_t bands; 205 uint8_t macaddr[IEEE80211_ADDR_LEN]; 206 207 sc->sc_id = id; 208 sc->sc_dev = dev; 209 210 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 211 if (ifp == NULL) { 212 device_printf(sc->sc_dev, "can not if_alloc()\n"); 213 return ENOMEM; 214 } 215 ic = ifp->if_l2com; 216 217 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 218 MTX_DEF | MTX_RECURSE); 219 220 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 221 222 /* wait for NIC to initialize */ 223 for (ntries = 0; ntries < 1000; ntries++) { 224 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 225 break; 226 DELAY(1000); 227 } 228 if (ntries == 1000) { 229 device_printf(sc->sc_dev, 230 "timeout waiting for NIC to initialize\n"); 231 error = EIO; 232 goto fail1; 233 } 234 235 /* retrieve RF rev. no and various other things from EEPROM */ 236 rt2661_read_eeprom(sc, macaddr); 237 238 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 239 rt2661_get_rf(sc->rf_rev)); 240 241 /* 242 * Allocate Tx and Rx rings. 243 */ 244 for (ac = 0; ac < 4; ac++) { 245 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 246 RT2661_TX_RING_COUNT); 247 if (error != 0) { 248 device_printf(sc->sc_dev, 249 "could not allocate Tx ring %d\n", ac); 250 goto fail2; 251 } 252 } 253 254 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 255 if (error != 0) { 256 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 257 goto fail2; 258 } 259 260 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 261 if (error != 0) { 262 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 263 goto fail3; 264 } 265 266 ifp->if_softc = sc; 267 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 268 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 269 ifp->if_init = rt2661_init; 270 ifp->if_ioctl = rt2661_ioctl; 271 ifp->if_start = rt2661_start; 272 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 273 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 274 IFQ_SET_READY(&ifp->if_snd); 275 276 ic->ic_ifp = ifp; 277 ic->ic_opmode = IEEE80211_M_STA; 278 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 279 280 /* set device capabilities */ 281 ic->ic_caps = 282 IEEE80211_C_STA /* station mode */ 283 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 284 | IEEE80211_C_HOSTAP /* hostap mode */ 285 | IEEE80211_C_MONITOR /* monitor mode */ 286 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 287 | IEEE80211_C_WDS /* 4-address traffic works */ 288 | IEEE80211_C_MBSS /* mesh point link mode */ 289 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 290 | IEEE80211_C_SHSLOT /* short slot time supported */ 291 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 292 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 293#ifdef notyet 294 | IEEE80211_C_TXFRAG /* handle tx frags */ 295 | IEEE80211_C_WME /* 802.11e */ 296#endif 297 | IEEE80211_C_RATECTL /* use ratectl */ 298 ; 299 300 bands = 0; 301 setbit(&bands, IEEE80211_MODE_11B); 302 setbit(&bands, IEEE80211_MODE_11G); 303 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) 304 setbit(&bands, IEEE80211_MODE_11A); 305 ieee80211_init_channels(ic, NULL, &bands); 306 307 ieee80211_ifattach(ic, macaddr); 308 ic->ic_newassoc = rt2661_newassoc; 309#if 0 310 ic->ic_wme.wme_update = rt2661_wme_update; 311#endif 312 ic->ic_scan_start = rt2661_scan_start; 313 ic->ic_scan_end = rt2661_scan_end; 314 ic->ic_set_channel = rt2661_set_channel; 315 ic->ic_updateslot = rt2661_update_slot; 316 ic->ic_update_promisc = rt2661_update_promisc; 317 ic->ic_raw_xmit = rt2661_raw_xmit; 318 319 ic->ic_vap_create = rt2661_vap_create; 320 ic->ic_vap_delete = rt2661_vap_delete; 321 322 ieee80211_radiotap_attach(ic, 323 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 324 RT2661_TX_RADIOTAP_PRESENT, 325 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 326 RT2661_RX_RADIOTAP_PRESENT); 327 328#ifdef RAL_DEBUG 329 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 330 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 331 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 332#endif 333 if (bootverbose) 334 ieee80211_announce(ic); 335 336 return 0; 337 338fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 339fail2: while (--ac >= 0) 340 rt2661_free_tx_ring(sc, &sc->txq[ac]); 341fail1: mtx_destroy(&sc->sc_mtx); 342 if_free(ifp); 343 return error; 344} 345 346int 347rt2661_detach(void *xsc) 348{ 349 struct rt2661_softc *sc = xsc; 350 struct ifnet *ifp = sc->sc_ifp; 351 struct ieee80211com *ic = ifp->if_l2com; 352 353 RAL_LOCK(sc); 354 rt2661_stop_locked(sc); 355 RAL_UNLOCK(sc); 356 357 ieee80211_ifdetach(ic); 358 359 rt2661_free_tx_ring(sc, &sc->txq[0]); 360 rt2661_free_tx_ring(sc, &sc->txq[1]); 361 rt2661_free_tx_ring(sc, &sc->txq[2]); 362 rt2661_free_tx_ring(sc, &sc->txq[3]); 363 rt2661_free_tx_ring(sc, &sc->mgtq); 364 rt2661_free_rx_ring(sc, &sc->rxq); 365 366 if_free(ifp); 367 368 mtx_destroy(&sc->sc_mtx); 369 370 return 0; 371} 372 373static struct ieee80211vap * 374rt2661_vap_create(struct ieee80211com *ic, 375 const char name[IFNAMSIZ], int unit, int opmode, int flags, 376 const uint8_t bssid[IEEE80211_ADDR_LEN], 377 const uint8_t mac[IEEE80211_ADDR_LEN]) 378{ 379 struct ifnet *ifp = ic->ic_ifp; 380 struct rt2661_vap *rvp; 381 struct ieee80211vap *vap; 382 383 switch (opmode) { 384 case IEEE80211_M_STA: 385 case IEEE80211_M_IBSS: 386 case IEEE80211_M_AHDEMO: 387 case IEEE80211_M_MONITOR: 388 case IEEE80211_M_HOSTAP: 389 case IEEE80211_M_MBSS: 390 /* XXXRP: TBD */ 391 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 392 if_printf(ifp, "only 1 vap supported\n"); 393 return NULL; 394 } 395 if (opmode == IEEE80211_M_STA) 396 flags |= IEEE80211_CLONE_NOBEACONS; 397 break; 398 case IEEE80211_M_WDS: 399 if (TAILQ_EMPTY(&ic->ic_vaps) || 400 ic->ic_opmode != IEEE80211_M_HOSTAP) { 401 if_printf(ifp, "wds only supported in ap mode\n"); 402 return NULL; 403 } 404 /* 405 * Silently remove any request for a unique 406 * bssid; WDS vap's always share the local 407 * mac address. 408 */ 409 flags &= ~IEEE80211_CLONE_BSSID; 410 break; 411 default: 412 if_printf(ifp, "unknown opmode %d\n", opmode); 413 return NULL; 414 } 415 rvp = (struct rt2661_vap *) malloc(sizeof(struct rt2661_vap), 416 M_80211_VAP, M_NOWAIT | M_ZERO); 417 if (rvp == NULL) 418 return NULL; 419 vap = &rvp->ral_vap; 420 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 421 422 /* override state transition machine */ 423 rvp->ral_newstate = vap->iv_newstate; 424 vap->iv_newstate = rt2661_newstate; 425#if 0 426 vap->iv_update_beacon = rt2661_beacon_update; 427#endif 428 429 ieee80211_ratectl_init(vap); 430 /* complete setup */ 431 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 432 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 433 ic->ic_opmode = opmode; 434 return vap; 435} 436 437static void 438rt2661_vap_delete(struct ieee80211vap *vap) 439{ 440 struct rt2661_vap *rvp = RT2661_VAP(vap); 441 442 ieee80211_ratectl_deinit(vap); 443 ieee80211_vap_detach(vap); 444 free(rvp, M_80211_VAP); 445} 446 447void 448rt2661_shutdown(void *xsc) 449{ 450 struct rt2661_softc *sc = xsc; 451 452 rt2661_stop(sc); 453} 454 455void 456rt2661_suspend(void *xsc) 457{ 458 struct rt2661_softc *sc = xsc; 459 460 rt2661_stop(sc); 461} 462 463void 464rt2661_resume(void *xsc) 465{ 466 struct rt2661_softc *sc = xsc; 467 struct ifnet *ifp = sc->sc_ifp; 468 469 if (ifp->if_flags & IFF_UP) 470 rt2661_init(sc); 471} 472 473static void 474rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 475{ 476 if (error != 0) 477 return; 478 479 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 480 481 *(bus_addr_t *)arg = segs[0].ds_addr; 482} 483 484static int 485rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 486 int count) 487{ 488 int i, error; 489 490 ring->count = count; 491 ring->queued = 0; 492 ring->cur = ring->next = ring->stat = 0; 493 494 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 495 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 496 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 497 0, NULL, NULL, &ring->desc_dmat); 498 if (error != 0) { 499 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 500 goto fail; 501 } 502 503 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 504 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 505 if (error != 0) { 506 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 507 goto fail; 508 } 509 510 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 511 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 512 0); 513 if (error != 0) { 514 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 515 goto fail; 516 } 517 518 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 519 M_NOWAIT | M_ZERO); 520 if (ring->data == NULL) { 521 device_printf(sc->sc_dev, "could not allocate soft data\n"); 522 error = ENOMEM; 523 goto fail; 524 } 525 526 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 527 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 528 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 529 if (error != 0) { 530 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 531 goto fail; 532 } 533 534 for (i = 0; i < count; i++) { 535 error = bus_dmamap_create(ring->data_dmat, 0, 536 &ring->data[i].map); 537 if (error != 0) { 538 device_printf(sc->sc_dev, "could not create DMA map\n"); 539 goto fail; 540 } 541 } 542 543 return 0; 544 545fail: rt2661_free_tx_ring(sc, ring); 546 return error; 547} 548 549static void 550rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 551{ 552 struct rt2661_tx_desc *desc; 553 struct rt2661_tx_data *data; 554 int i; 555 556 for (i = 0; i < ring->count; i++) { 557 desc = &ring->desc[i]; 558 data = &ring->data[i]; 559 560 if (data->m != NULL) { 561 bus_dmamap_sync(ring->data_dmat, data->map, 562 BUS_DMASYNC_POSTWRITE); 563 bus_dmamap_unload(ring->data_dmat, data->map); 564 m_freem(data->m); 565 data->m = NULL; 566 } 567 568 if (data->ni != NULL) { 569 ieee80211_free_node(data->ni); 570 data->ni = NULL; 571 } 572 573 desc->flags = 0; 574 } 575 576 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 577 578 ring->queued = 0; 579 ring->cur = ring->next = ring->stat = 0; 580} 581 582static void 583rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 584{ 585 struct rt2661_tx_data *data; 586 int i; 587 588 if (ring->desc != NULL) { 589 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 590 BUS_DMASYNC_POSTWRITE); 591 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 592 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 593 } 594 595 if (ring->desc_dmat != NULL) 596 bus_dma_tag_destroy(ring->desc_dmat); 597 598 if (ring->data != NULL) { 599 for (i = 0; i < ring->count; i++) { 600 data = &ring->data[i]; 601 602 if (data->m != NULL) { 603 bus_dmamap_sync(ring->data_dmat, data->map, 604 BUS_DMASYNC_POSTWRITE); 605 bus_dmamap_unload(ring->data_dmat, data->map); 606 m_freem(data->m); 607 } 608 609 if (data->ni != NULL) 610 ieee80211_free_node(data->ni); 611 612 if (data->map != NULL) 613 bus_dmamap_destroy(ring->data_dmat, data->map); 614 } 615 616 free(ring->data, M_DEVBUF); 617 } 618 619 if (ring->data_dmat != NULL) 620 bus_dma_tag_destroy(ring->data_dmat); 621} 622 623static int 624rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 625 int count) 626{ 627 struct rt2661_rx_desc *desc; 628 struct rt2661_rx_data *data; 629 bus_addr_t physaddr; 630 int i, error; 631 632 ring->count = count; 633 ring->cur = ring->next = 0; 634 635 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 636 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 637 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 638 0, NULL, NULL, &ring->desc_dmat); 639 if (error != 0) { 640 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 641 goto fail; 642 } 643 644 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 645 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 646 if (error != 0) { 647 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 648 goto fail; 649 } 650 651 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 652 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 653 0); 654 if (error != 0) { 655 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 656 goto fail; 657 } 658 659 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 660 M_NOWAIT | M_ZERO); 661 if (ring->data == NULL) { 662 device_printf(sc->sc_dev, "could not allocate soft data\n"); 663 error = ENOMEM; 664 goto fail; 665 } 666 667 /* 668 * Pre-allocate Rx buffers and populate Rx ring. 669 */ 670 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 671 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 672 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 673 if (error != 0) { 674 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 675 goto fail; 676 } 677 678 for (i = 0; i < count; i++) { 679 desc = &sc->rxq.desc[i]; 680 data = &sc->rxq.data[i]; 681 682 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 683 if (error != 0) { 684 device_printf(sc->sc_dev, "could not create DMA map\n"); 685 goto fail; 686 } 687 688 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 689 if (data->m == NULL) { 690 device_printf(sc->sc_dev, 691 "could not allocate rx mbuf\n"); 692 error = ENOMEM; 693 goto fail; 694 } 695 696 error = bus_dmamap_load(ring->data_dmat, data->map, 697 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 698 &physaddr, 0); 699 if (error != 0) { 700 device_printf(sc->sc_dev, 701 "could not load rx buf DMA map"); 702 goto fail; 703 } 704 705 desc->flags = htole32(RT2661_RX_BUSY); 706 desc->physaddr = htole32(physaddr); 707 } 708 709 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 710 711 return 0; 712 713fail: rt2661_free_rx_ring(sc, ring); 714 return error; 715} 716 717static void 718rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 719{ 720 int i; 721 722 for (i = 0; i < ring->count; i++) 723 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 724 725 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 726 727 ring->cur = ring->next = 0; 728} 729 730static void 731rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 732{ 733 struct rt2661_rx_data *data; 734 int i; 735 736 if (ring->desc != NULL) { 737 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 738 BUS_DMASYNC_POSTWRITE); 739 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 740 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 741 } 742 743 if (ring->desc_dmat != NULL) 744 bus_dma_tag_destroy(ring->desc_dmat); 745 746 if (ring->data != NULL) { 747 for (i = 0; i < ring->count; i++) { 748 data = &ring->data[i]; 749 750 if (data->m != NULL) { 751 bus_dmamap_sync(ring->data_dmat, data->map, 752 BUS_DMASYNC_POSTREAD); 753 bus_dmamap_unload(ring->data_dmat, data->map); 754 m_freem(data->m); 755 } 756 757 if (data->map != NULL) 758 bus_dmamap_destroy(ring->data_dmat, data->map); 759 } 760 761 free(ring->data, M_DEVBUF); 762 } 763 764 if (ring->data_dmat != NULL) 765 bus_dma_tag_destroy(ring->data_dmat); 766} 767 768static void 769rt2661_newassoc(struct ieee80211_node *ni, int isnew) 770{ 771 /* XXX move */ 772 ieee80211_ratectl_node_init(ni); 773} 774 775static int 776rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 777{ 778 struct rt2661_vap *rvp = RT2661_VAP(vap); 779 struct ieee80211com *ic = vap->iv_ic; 780 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 781 int error; 782 783 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 784 uint32_t tmp; 785 786 /* abort TSF synchronization */ 787 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 788 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 789 } 790 791 error = rvp->ral_newstate(vap, nstate, arg); 792 793 if (error == 0 && nstate == IEEE80211_S_RUN) { 794 struct ieee80211_node *ni = vap->iv_bss; 795 796 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 797 rt2661_enable_mrr(sc); 798 rt2661_set_txpreamble(sc); 799 rt2661_set_basicrates(sc, &ni->ni_rates); 800 rt2661_set_bssid(sc, ni->ni_bssid); 801 } 802 803 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 804 vap->iv_opmode == IEEE80211_M_IBSS || 805 vap->iv_opmode == IEEE80211_M_MBSS) { 806 error = rt2661_prepare_beacon(sc, vap); 807 if (error != 0) 808 return error; 809 } 810 if (vap->iv_opmode != IEEE80211_M_MONITOR) 811 rt2661_enable_tsf_sync(sc); 812 else 813 rt2661_enable_tsf(sc); 814 } 815 return error; 816} 817 818/* 819 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 820 * 93C66). 821 */ 822static uint16_t 823rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 824{ 825 uint32_t tmp; 826 uint16_t val; 827 int n; 828 829 /* clock C once before the first command */ 830 RT2661_EEPROM_CTL(sc, 0); 831 832 RT2661_EEPROM_CTL(sc, RT2661_S); 833 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 834 RT2661_EEPROM_CTL(sc, RT2661_S); 835 836 /* write start bit (1) */ 837 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 838 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 839 840 /* write READ opcode (10) */ 841 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 842 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 843 RT2661_EEPROM_CTL(sc, RT2661_S); 844 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 845 846 /* write address (A5-A0 or A7-A0) */ 847 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 848 for (; n >= 0; n--) { 849 RT2661_EEPROM_CTL(sc, RT2661_S | 850 (((addr >> n) & 1) << RT2661_SHIFT_D)); 851 RT2661_EEPROM_CTL(sc, RT2661_S | 852 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 853 } 854 855 RT2661_EEPROM_CTL(sc, RT2661_S); 856 857 /* read data Q15-Q0 */ 858 val = 0; 859 for (n = 15; n >= 0; n--) { 860 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 861 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 862 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 863 RT2661_EEPROM_CTL(sc, RT2661_S); 864 } 865 866 RT2661_EEPROM_CTL(sc, 0); 867 868 /* clear Chip Select and clock C */ 869 RT2661_EEPROM_CTL(sc, RT2661_S); 870 RT2661_EEPROM_CTL(sc, 0); 871 RT2661_EEPROM_CTL(sc, RT2661_C); 872 873 return val; 874} 875 876static void 877rt2661_tx_intr(struct rt2661_softc *sc) 878{ 879 struct ifnet *ifp = sc->sc_ifp; 880 struct rt2661_tx_ring *txq; 881 struct rt2661_tx_data *data; 882 uint32_t val; 883 int qid, retrycnt; 884 struct ieee80211vap *vap; 885 886 for (;;) { 887 struct ieee80211_node *ni; 888 struct mbuf *m; 889 890 val = RAL_READ(sc, RT2661_STA_CSR4); 891 if (!(val & RT2661_TX_STAT_VALID)) 892 break; 893 894 /* retrieve the queue in which this frame was sent */ 895 qid = RT2661_TX_QID(val); 896 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 897 898 /* retrieve rate control algorithm context */ 899 data = &txq->data[txq->stat]; 900 m = data->m; 901 data->m = NULL; 902 ni = data->ni; 903 data->ni = NULL; 904 905 /* if no frame has been sent, ignore */ 906 if (ni == NULL) 907 continue; 908 else 909 vap = ni->ni_vap; 910 911 switch (RT2661_TX_RESULT(val)) { 912 case RT2661_TX_SUCCESS: 913 retrycnt = RT2661_TX_RETRYCNT(val); 914 915 DPRINTFN(sc, 10, "data frame sent successfully after " 916 "%d retries\n", retrycnt); 917 if (data->rix != IEEE80211_FIXED_RATE_NONE) 918 ieee80211_ratectl_tx_complete(vap, ni, 919 IEEE80211_RATECTL_TX_SUCCESS, 920 &retrycnt, NULL); 921 ifp->if_opackets++; 922 break; 923 924 case RT2661_TX_RETRY_FAIL: 925 retrycnt = RT2661_TX_RETRYCNT(val); 926 927 DPRINTFN(sc, 9, "%s\n", 928 "sending data frame failed (too much retries)"); 929 if (data->rix != IEEE80211_FIXED_RATE_NONE) 930 ieee80211_ratectl_tx_complete(vap, ni, 931 IEEE80211_RATECTL_TX_FAILURE, 932 &retrycnt, NULL); 933 ifp->if_oerrors++; 934 break; 935 936 default: 937 /* other failure */ 938 device_printf(sc->sc_dev, 939 "sending data frame failed 0x%08x\n", val); 940 ifp->if_oerrors++; 941 } 942 943 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 944 945 txq->queued--; 946 if (++txq->stat >= txq->count) /* faster than % count */ 947 txq->stat = 0; 948 949 if (m->m_flags & M_TXCB) 950 ieee80211_process_callback(ni, m, 951 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS); 952 m_freem(m); 953 ieee80211_free_node(ni); 954 } 955 956 sc->sc_tx_timer = 0; 957 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 958 959 rt2661_start_locked(ifp); 960} 961 962static void 963rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 964{ 965 struct rt2661_tx_desc *desc; 966 struct rt2661_tx_data *data; 967 968 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 969 970 for (;;) { 971 desc = &txq->desc[txq->next]; 972 data = &txq->data[txq->next]; 973 974 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 975 !(le32toh(desc->flags) & RT2661_TX_VALID)) 976 break; 977 978 bus_dmamap_sync(txq->data_dmat, data->map, 979 BUS_DMASYNC_POSTWRITE); 980 bus_dmamap_unload(txq->data_dmat, data->map); 981 982 /* descriptor is no longer valid */ 983 desc->flags &= ~htole32(RT2661_TX_VALID); 984 985 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 986 987 if (++txq->next >= txq->count) /* faster than % count */ 988 txq->next = 0; 989 } 990 991 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 992} 993 994static void 995rt2661_rx_intr(struct rt2661_softc *sc) 996{ 997 struct ifnet *ifp = sc->sc_ifp; 998 struct ieee80211com *ic = ifp->if_l2com; 999 struct rt2661_rx_desc *desc; 1000 struct rt2661_rx_data *data; 1001 bus_addr_t physaddr; 1002 struct ieee80211_frame *wh; 1003 struct ieee80211_node *ni; 1004 struct mbuf *mnew, *m; 1005 int error; 1006 1007 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1008 BUS_DMASYNC_POSTREAD); 1009 1010 for (;;) { 1011 int8_t rssi, nf; 1012 1013 desc = &sc->rxq.desc[sc->rxq.cur]; 1014 data = &sc->rxq.data[sc->rxq.cur]; 1015 1016 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1017 break; 1018 1019 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1020 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1021 /* 1022 * This should not happen since we did not request 1023 * to receive those frames when we filled TXRX_CSR0. 1024 */ 1025 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 1026 le32toh(desc->flags)); 1027 ifp->if_ierrors++; 1028 goto skip; 1029 } 1030 1031 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1032 ifp->if_ierrors++; 1033 goto skip; 1034 } 1035 1036 /* 1037 * Try to allocate a new mbuf for this ring element and load it 1038 * before processing the current mbuf. If the ring element 1039 * cannot be loaded, drop the received packet and reuse the old 1040 * mbuf. In the unlikely case that the old mbuf can't be 1041 * reloaded either, explicitly panic. 1042 */ 1043 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1044 if (mnew == NULL) { 1045 ifp->if_ierrors++; 1046 goto skip; 1047 } 1048 1049 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1050 BUS_DMASYNC_POSTREAD); 1051 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1052 1053 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1054 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1055 &physaddr, 0); 1056 if (error != 0) { 1057 m_freem(mnew); 1058 1059 /* try to reload the old mbuf */ 1060 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1061 mtod(data->m, void *), MCLBYTES, 1062 rt2661_dma_map_addr, &physaddr, 0); 1063 if (error != 0) { 1064 /* very unlikely that it will fail... */ 1065 panic("%s: could not load old rx mbuf", 1066 device_get_name(sc->sc_dev)); 1067 } 1068 ifp->if_ierrors++; 1069 goto skip; 1070 } 1071 1072 /* 1073 * New mbuf successfully loaded, update Rx ring and continue 1074 * processing. 1075 */ 1076 m = data->m; 1077 data->m = mnew; 1078 desc->physaddr = htole32(physaddr); 1079 1080 /* finalize mbuf */ 1081 m->m_pkthdr.rcvif = ifp; 1082 m->m_pkthdr.len = m->m_len = 1083 (le32toh(desc->flags) >> 16) & 0xfff; 1084 1085 rssi = rt2661_get_rssi(sc, desc->rssi); 1086 /* Error happened during RSSI conversion. */ 1087 if (rssi < 0) 1088 rssi = -30; /* XXX ignored by net80211 */ 1089 nf = RT2661_NOISE_FLOOR; 1090 1091 if (ieee80211_radiotap_active(ic)) { 1092 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1093 uint32_t tsf_lo, tsf_hi; 1094 1095 /* get timestamp (low and high 32 bits) */ 1096 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1097 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1098 1099 tap->wr_tsf = 1100 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1101 tap->wr_flags = 0; 1102 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1103 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1104 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1105 tap->wr_antsignal = nf + rssi; 1106 tap->wr_antnoise = nf; 1107 } 1108 sc->sc_flags |= RAL_INPUT_RUNNING; 1109 RAL_UNLOCK(sc); 1110 wh = mtod(m, struct ieee80211_frame *); 1111 1112 /* send the frame to the 802.11 layer */ 1113 ni = ieee80211_find_rxnode(ic, 1114 (struct ieee80211_frame_min *)wh); 1115 if (ni != NULL) { 1116 (void) ieee80211_input(ni, m, rssi, nf); 1117 ieee80211_free_node(ni); 1118 } else 1119 (void) ieee80211_input_all(ic, m, rssi, nf); 1120 1121 RAL_LOCK(sc); 1122 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1123 1124skip: desc->flags |= htole32(RT2661_RX_BUSY); 1125 1126 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1127 1128 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1129 } 1130 1131 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1132 BUS_DMASYNC_PREWRITE); 1133} 1134 1135/* ARGSUSED */ 1136static void 1137rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1138{ 1139 /* do nothing */ 1140} 1141 1142static void 1143rt2661_mcu_wakeup(struct rt2661_softc *sc) 1144{ 1145 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1146 1147 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1148 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1149 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1150 1151 /* send wakeup command to MCU */ 1152 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1153} 1154 1155static void 1156rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1157{ 1158 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1159 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1160} 1161 1162void 1163rt2661_intr(void *arg) 1164{ 1165 struct rt2661_softc *sc = arg; 1166 struct ifnet *ifp = sc->sc_ifp; 1167 uint32_t r1, r2; 1168 1169 RAL_LOCK(sc); 1170 1171 /* disable MAC and MCU interrupts */ 1172 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1173 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1174 1175 /* don't re-enable interrupts if we're shutting down */ 1176 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1177 RAL_UNLOCK(sc); 1178 return; 1179 } 1180 1181 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1182 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1183 1184 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1185 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1186 1187 if (r1 & RT2661_MGT_DONE) 1188 rt2661_tx_dma_intr(sc, &sc->mgtq); 1189 1190 if (r1 & RT2661_RX_DONE) 1191 rt2661_rx_intr(sc); 1192 1193 if (r1 & RT2661_TX0_DMA_DONE) 1194 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1195 1196 if (r1 & RT2661_TX1_DMA_DONE) 1197 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1198 1199 if (r1 & RT2661_TX2_DMA_DONE) 1200 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1201 1202 if (r1 & RT2661_TX3_DMA_DONE) 1203 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1204 1205 if (r1 & RT2661_TX_DONE) 1206 rt2661_tx_intr(sc); 1207 1208 if (r2 & RT2661_MCU_CMD_DONE) 1209 rt2661_mcu_cmd_intr(sc); 1210 1211 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1212 rt2661_mcu_beacon_expire(sc); 1213 1214 if (r2 & RT2661_MCU_WAKEUP) 1215 rt2661_mcu_wakeup(sc); 1216 1217 /* re-enable MAC and MCU interrupts */ 1218 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1219 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1220 1221 RAL_UNLOCK(sc); 1222} 1223 1224static uint8_t 1225rt2661_plcp_signal(int rate) 1226{ 1227 switch (rate) { 1228 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1229 case 12: return 0xb; 1230 case 18: return 0xf; 1231 case 24: return 0xa; 1232 case 36: return 0xe; 1233 case 48: return 0x9; 1234 case 72: return 0xd; 1235 case 96: return 0x8; 1236 case 108: return 0xc; 1237 1238 /* CCK rates (NB: not IEEE std, device-specific) */ 1239 case 2: return 0x0; 1240 case 4: return 0x1; 1241 case 11: return 0x2; 1242 case 22: return 0x3; 1243 } 1244 return 0xff; /* XXX unsupported/unknown rate */ 1245} 1246 1247static void 1248rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1249 uint32_t flags, uint16_t xflags, int len, int rate, 1250 const bus_dma_segment_t *segs, int nsegs, int ac) 1251{ 1252 struct ifnet *ifp = sc->sc_ifp; 1253 struct ieee80211com *ic = ifp->if_l2com; 1254 uint16_t plcp_length; 1255 int i, remainder; 1256 1257 desc->flags = htole32(flags); 1258 desc->flags |= htole32(len << 16); 1259 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1260 1261 desc->xflags = htole16(xflags); 1262 desc->xflags |= htole16(nsegs << 13); 1263 1264 desc->wme = htole16( 1265 RT2661_QID(ac) | 1266 RT2661_AIFSN(2) | 1267 RT2661_LOGCWMIN(4) | 1268 RT2661_LOGCWMAX(10)); 1269 1270 /* 1271 * Remember in which queue this frame was sent. This field is driver 1272 * private data only. It will be made available by the NIC in STA_CSR4 1273 * on Tx interrupts. 1274 */ 1275 desc->qid = ac; 1276 1277 /* setup PLCP fields */ 1278 desc->plcp_signal = rt2661_plcp_signal(rate); 1279 desc->plcp_service = 4; 1280 1281 len += IEEE80211_CRC_LEN; 1282 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1283 desc->flags |= htole32(RT2661_TX_OFDM); 1284 1285 plcp_length = len & 0xfff; 1286 desc->plcp_length_hi = plcp_length >> 6; 1287 desc->plcp_length_lo = plcp_length & 0x3f; 1288 } else { 1289 plcp_length = (16 * len + rate - 1) / rate; 1290 if (rate == 22) { 1291 remainder = (16 * len) % 22; 1292 if (remainder != 0 && remainder < 7) 1293 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1294 } 1295 desc->plcp_length_hi = plcp_length >> 8; 1296 desc->plcp_length_lo = plcp_length & 0xff; 1297 1298 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1299 desc->plcp_signal |= 0x08; 1300 } 1301 1302 /* RT2x61 supports scatter with up to 5 segments */ 1303 for (i = 0; i < nsegs; i++) { 1304 desc->addr[i] = htole32(segs[i].ds_addr); 1305 desc->len [i] = htole16(segs[i].ds_len); 1306 } 1307} 1308 1309static int 1310rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1311 struct ieee80211_node *ni) 1312{ 1313 struct ieee80211vap *vap = ni->ni_vap; 1314 struct ieee80211com *ic = ni->ni_ic; 1315 struct rt2661_tx_desc *desc; 1316 struct rt2661_tx_data *data; 1317 struct ieee80211_frame *wh; 1318 struct ieee80211_key *k; 1319 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1320 uint16_t dur; 1321 uint32_t flags = 0; /* XXX HWSEQ */ 1322 int nsegs, rate, error; 1323 1324 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1325 data = &sc->mgtq.data[sc->mgtq.cur]; 1326 1327 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1328 1329 wh = mtod(m0, struct ieee80211_frame *); 1330 1331 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1332 k = ieee80211_crypto_encap(ni, m0); 1333 if (k == NULL) { 1334 m_freem(m0); 1335 return ENOBUFS; 1336 } 1337 } 1338 1339 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1340 segs, &nsegs, 0); 1341 if (error != 0) { 1342 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1343 error); 1344 m_freem(m0); 1345 return error; 1346 } 1347 1348 if (ieee80211_radiotap_active_vap(vap)) { 1349 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1350 1351 tap->wt_flags = 0; 1352 tap->wt_rate = rate; 1353 1354 ieee80211_radiotap_tx(vap, m0); 1355 } 1356 1357 data->m = m0; 1358 data->ni = ni; 1359 /* management frames are not taken into account for amrr */ 1360 data->rix = IEEE80211_FIXED_RATE_NONE; 1361 1362 wh = mtod(m0, struct ieee80211_frame *); 1363 1364 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1365 flags |= RT2661_TX_NEED_ACK; 1366 1367 dur = ieee80211_ack_duration(ic->ic_rt, 1368 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1369 *(uint16_t *)wh->i_dur = htole16(dur); 1370 1371 /* tell hardware to add timestamp in probe responses */ 1372 if ((wh->i_fc[0] & 1373 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1374 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1375 flags |= RT2661_TX_TIMESTAMP; 1376 } 1377 1378 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1379 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1380 1381 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1382 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1383 BUS_DMASYNC_PREWRITE); 1384 1385 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1386 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1387 1388 /* kick mgt */ 1389 sc->mgtq.queued++; 1390 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1391 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1392 1393 return 0; 1394} 1395 1396static int 1397rt2661_sendprot(struct rt2661_softc *sc, int ac, 1398 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1399{ 1400 struct ieee80211com *ic = ni->ni_ic; 1401 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1402 const struct ieee80211_frame *wh; 1403 struct rt2661_tx_desc *desc; 1404 struct rt2661_tx_data *data; 1405 struct mbuf *mprot; 1406 int protrate, ackrate, pktlen, flags, isshort, error; 1407 uint16_t dur; 1408 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1409 int nsegs; 1410 1411 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1412 ("protection %d", prot)); 1413 1414 wh = mtod(m, const struct ieee80211_frame *); 1415 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1416 1417 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1418 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1419 1420 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1421 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1422 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1423 flags = RT2661_TX_MORE_FRAG; 1424 if (prot == IEEE80211_PROT_RTSCTS) { 1425 /* NB: CTS is the same size as an ACK */ 1426 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1427 flags |= RT2661_TX_NEED_ACK; 1428 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1429 } else { 1430 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1431 } 1432 if (mprot == NULL) { 1433 /* XXX stat + msg */ 1434 return ENOBUFS; 1435 } 1436 1437 data = &txq->data[txq->cur]; 1438 desc = &txq->desc[txq->cur]; 1439 1440 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, 1441 &nsegs, 0); 1442 if (error != 0) { 1443 device_printf(sc->sc_dev, 1444 "could not map mbuf (error %d)\n", error); 1445 m_freem(mprot); 1446 return error; 1447 } 1448 1449 data->m = mprot; 1450 data->ni = ieee80211_ref_node(ni); 1451 /* ctl frames are not taken into account for amrr */ 1452 data->rix = IEEE80211_FIXED_RATE_NONE; 1453 1454 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1455 protrate, segs, 1, ac); 1456 1457 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1458 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1459 1460 txq->queued++; 1461 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1462 1463 return 0; 1464} 1465 1466static int 1467rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1468 struct ieee80211_node *ni, int ac) 1469{ 1470 struct ieee80211vap *vap = ni->ni_vap; 1471 struct ifnet *ifp = sc->sc_ifp; 1472 struct ieee80211com *ic = ifp->if_l2com; 1473 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1474 struct rt2661_tx_desc *desc; 1475 struct rt2661_tx_data *data; 1476 struct ieee80211_frame *wh; 1477 const struct ieee80211_txparam *tp; 1478 struct ieee80211_key *k; 1479 const struct chanAccParams *cap; 1480 struct mbuf *mnew; 1481 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1482 uint16_t dur; 1483 uint32_t flags; 1484 int error, nsegs, rate, noack = 0; 1485 1486 wh = mtod(m0, struct ieee80211_frame *); 1487 1488 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1489 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1490 rate = tp->mcastrate; 1491 } else if (m0->m_flags & M_EAPOL) { 1492 rate = tp->mgmtrate; 1493 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1494 rate = tp->ucastrate; 1495 } else { 1496 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1497 rate = ni->ni_txrate; 1498 } 1499 rate &= IEEE80211_RATE_VAL; 1500 1501 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1502 cap = &ic->ic_wme.wme_chanParams; 1503 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1504 } 1505 1506 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1507 k = ieee80211_crypto_encap(ni, m0); 1508 if (k == NULL) { 1509 m_freem(m0); 1510 return ENOBUFS; 1511 } 1512 1513 /* packet header may have moved, reset our local pointer */ 1514 wh = mtod(m0, struct ieee80211_frame *); 1515 } 1516 1517 flags = 0; 1518 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1519 int prot = IEEE80211_PROT_NONE; 1520 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1521 prot = IEEE80211_PROT_RTSCTS; 1522 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1523 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1524 prot = ic->ic_protmode; 1525 if (prot != IEEE80211_PROT_NONE) { 1526 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1527 if (error) { 1528 m_freem(m0); 1529 return error; 1530 } 1531 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1532 } 1533 } 1534 1535 data = &txq->data[txq->cur]; 1536 desc = &txq->desc[txq->cur]; 1537 1538 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1539 &nsegs, 0); 1540 if (error != 0 && error != EFBIG) { 1541 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1542 error); 1543 m_freem(m0); 1544 return error; 1545 } 1546 if (error != 0) { 1547 mnew = m_defrag(m0, M_DONTWAIT); 1548 if (mnew == NULL) { 1549 device_printf(sc->sc_dev, 1550 "could not defragment mbuf\n"); 1551 m_freem(m0); 1552 return ENOBUFS; 1553 } 1554 m0 = mnew; 1555 1556 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1557 segs, &nsegs, 0); 1558 if (error != 0) { 1559 device_printf(sc->sc_dev, 1560 "could not map mbuf (error %d)\n", error); 1561 m_freem(m0); 1562 return error; 1563 } 1564 1565 /* packet header have moved, reset our local pointer */ 1566 wh = mtod(m0, struct ieee80211_frame *); 1567 } 1568 1569 if (ieee80211_radiotap_active_vap(vap)) { 1570 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1571 1572 tap->wt_flags = 0; 1573 tap->wt_rate = rate; 1574 1575 ieee80211_radiotap_tx(vap, m0); 1576 } 1577 1578 data->m = m0; 1579 data->ni = ni; 1580 1581 /* remember link conditions for rate adaptation algorithm */ 1582 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1583 data->rix = ni->ni_txrate; 1584 /* XXX probably need last rssi value and not avg */ 1585 data->rssi = ic->ic_node_getrssi(ni); 1586 } else 1587 data->rix = IEEE80211_FIXED_RATE_NONE; 1588 1589 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1590 flags |= RT2661_TX_NEED_ACK; 1591 1592 dur = ieee80211_ack_duration(ic->ic_rt, 1593 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1594 *(uint16_t *)wh->i_dur = htole16(dur); 1595 } 1596 1597 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1598 nsegs, ac); 1599 1600 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1601 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1602 1603 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1604 m0->m_pkthdr.len, txq->cur, rate); 1605 1606 /* kick Tx */ 1607 txq->queued++; 1608 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1609 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1610 1611 return 0; 1612} 1613 1614static void 1615rt2661_start_locked(struct ifnet *ifp) 1616{ 1617 struct rt2661_softc *sc = ifp->if_softc; 1618 struct mbuf *m; 1619 struct ieee80211_node *ni; 1620 int ac; 1621 1622 RAL_LOCK_ASSERT(sc); 1623 1624 /* prevent management frames from being sent if we're not ready */ 1625 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || sc->sc_invalid) 1626 return; 1627 1628 for (;;) { 1629 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1630 if (m == NULL) 1631 break; 1632 1633 ac = M_WME_GETAC(m); 1634 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1635 /* there is no place left in this ring */ 1636 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1637 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1638 break; 1639 } 1640 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1641 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1642 ieee80211_free_node(ni); 1643 ifp->if_oerrors++; 1644 break; 1645 } 1646 1647 sc->sc_tx_timer = 5; 1648 } 1649} 1650 1651static void 1652rt2661_start(struct ifnet *ifp) 1653{ 1654 struct rt2661_softc *sc = ifp->if_softc; 1655 1656 RAL_LOCK(sc); 1657 rt2661_start_locked(ifp); 1658 RAL_UNLOCK(sc); 1659} 1660 1661static int 1662rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1663 const struct ieee80211_bpf_params *params) 1664{ 1665 struct ieee80211com *ic = ni->ni_ic; 1666 struct ifnet *ifp = ic->ic_ifp; 1667 struct rt2661_softc *sc = ifp->if_softc; 1668 1669 RAL_LOCK(sc); 1670 1671 /* prevent management frames from being sent if we're not ready */ 1672 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1673 RAL_UNLOCK(sc); 1674 m_freem(m); 1675 ieee80211_free_node(ni); 1676 return ENETDOWN; 1677 } 1678 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1679 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1680 RAL_UNLOCK(sc); 1681 m_freem(m); 1682 ieee80211_free_node(ni); 1683 return ENOBUFS; /* XXX */ 1684 } 1685 1686 ifp->if_opackets++; 1687 1688 /* 1689 * Legacy path; interpret frame contents to decide 1690 * precisely how to send the frame. 1691 * XXX raw path 1692 */ 1693 if (rt2661_tx_mgt(sc, m, ni) != 0) 1694 goto bad; 1695 sc->sc_tx_timer = 5; 1696 1697 RAL_UNLOCK(sc); 1698 1699 return 0; 1700bad: 1701 ifp->if_oerrors++; 1702 ieee80211_free_node(ni); 1703 RAL_UNLOCK(sc); 1704 return EIO; /* XXX */ 1705} 1706 1707static void 1708rt2661_watchdog(void *arg) 1709{ 1710 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1711 struct ifnet *ifp = sc->sc_ifp; 1712 1713 RAL_LOCK_ASSERT(sc); 1714 1715 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 1716 1717 if (sc->sc_invalid) /* card ejected */ 1718 return; 1719 1720 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1721 if_printf(ifp, "device timeout\n"); 1722 rt2661_init_locked(sc); 1723 ifp->if_oerrors++; 1724 /* NB: callout is reset in rt2661_init() */ 1725 return; 1726 } 1727 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1728} 1729 1730static int 1731rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1732{ 1733 struct rt2661_softc *sc = ifp->if_softc; 1734 struct ieee80211com *ic = ifp->if_l2com; 1735 struct ifreq *ifr = (struct ifreq *) data; 1736 int error = 0, startall = 0; 1737 1738 switch (cmd) { 1739 case SIOCSIFFLAGS: 1740 RAL_LOCK(sc); 1741 if (ifp->if_flags & IFF_UP) { 1742 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1743 rt2661_init_locked(sc); 1744 startall = 1; 1745 } else 1746 rt2661_update_promisc(ifp); 1747 } else { 1748 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1749 rt2661_stop_locked(sc); 1750 } 1751 RAL_UNLOCK(sc); 1752 if (startall) 1753 ieee80211_start_all(ic); 1754 break; 1755 case SIOCGIFMEDIA: 1756 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1757 break; 1758 case SIOCGIFADDR: 1759 error = ether_ioctl(ifp, cmd, data); 1760 break; 1761 default: 1762 error = EINVAL; 1763 break; 1764 } 1765 return error; 1766} 1767 1768static void 1769rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1770{ 1771 uint32_t tmp; 1772 int ntries; 1773 1774 for (ntries = 0; ntries < 100; ntries++) { 1775 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1776 break; 1777 DELAY(1); 1778 } 1779 if (ntries == 100) { 1780 device_printf(sc->sc_dev, "could not write to BBP\n"); 1781 return; 1782 } 1783 1784 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1785 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1786 1787 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1788} 1789 1790static uint8_t 1791rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1792{ 1793 uint32_t val; 1794 int ntries; 1795 1796 for (ntries = 0; ntries < 100; ntries++) { 1797 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1798 break; 1799 DELAY(1); 1800 } 1801 if (ntries == 100) { 1802 device_printf(sc->sc_dev, "could not read from BBP\n"); 1803 return 0; 1804 } 1805 1806 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1807 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1808 1809 for (ntries = 0; ntries < 100; ntries++) { 1810 val = RAL_READ(sc, RT2661_PHY_CSR3); 1811 if (!(val & RT2661_BBP_BUSY)) 1812 return val & 0xff; 1813 DELAY(1); 1814 } 1815 1816 device_printf(sc->sc_dev, "could not read from BBP\n"); 1817 return 0; 1818} 1819 1820static void 1821rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1822{ 1823 uint32_t tmp; 1824 int ntries; 1825 1826 for (ntries = 0; ntries < 100; ntries++) { 1827 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1828 break; 1829 DELAY(1); 1830 } 1831 if (ntries == 100) { 1832 device_printf(sc->sc_dev, "could not write to RF\n"); 1833 return; 1834 } 1835 1836 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1837 (reg & 3); 1838 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1839 1840 /* remember last written value in sc */ 1841 sc->rf_regs[reg] = val; 1842 1843 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1844} 1845 1846static int 1847rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1848{ 1849 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1850 return EIO; /* there is already a command pending */ 1851 1852 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1853 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1854 1855 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1856 1857 return 0; 1858} 1859 1860static void 1861rt2661_select_antenna(struct rt2661_softc *sc) 1862{ 1863 uint8_t bbp4, bbp77; 1864 uint32_t tmp; 1865 1866 bbp4 = rt2661_bbp_read(sc, 4); 1867 bbp77 = rt2661_bbp_read(sc, 77); 1868 1869 /* TBD */ 1870 1871 /* make sure Rx is disabled before switching antenna */ 1872 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1873 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1874 1875 rt2661_bbp_write(sc, 4, bbp4); 1876 rt2661_bbp_write(sc, 77, bbp77); 1877 1878 /* restore Rx filter */ 1879 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1880} 1881 1882/* 1883 * Enable multi-rate retries for frames sent at OFDM rates. 1884 * In 802.11b/g mode, allow fallback to CCK rates. 1885 */ 1886static void 1887rt2661_enable_mrr(struct rt2661_softc *sc) 1888{ 1889 struct ifnet *ifp = sc->sc_ifp; 1890 struct ieee80211com *ic = ifp->if_l2com; 1891 uint32_t tmp; 1892 1893 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1894 1895 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1896 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1897 tmp |= RT2661_MRR_CCK_FALLBACK; 1898 tmp |= RT2661_MRR_ENABLED; 1899 1900 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1901} 1902 1903static void 1904rt2661_set_txpreamble(struct rt2661_softc *sc) 1905{ 1906 struct ifnet *ifp = sc->sc_ifp; 1907 struct ieee80211com *ic = ifp->if_l2com; 1908 uint32_t tmp; 1909 1910 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1911 1912 tmp &= ~RT2661_SHORT_PREAMBLE; 1913 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1914 tmp |= RT2661_SHORT_PREAMBLE; 1915 1916 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1917} 1918 1919static void 1920rt2661_set_basicrates(struct rt2661_softc *sc, 1921 const struct ieee80211_rateset *rs) 1922{ 1923#define RV(r) ((r) & IEEE80211_RATE_VAL) 1924 struct ifnet *ifp = sc->sc_ifp; 1925 struct ieee80211com *ic = ifp->if_l2com; 1926 uint32_t mask = 0; 1927 uint8_t rate; 1928 int i, j; 1929 1930 for (i = 0; i < rs->rs_nrates; i++) { 1931 rate = rs->rs_rates[i]; 1932 1933 if (!(rate & IEEE80211_RATE_BASIC)) 1934 continue; 1935 1936 /* 1937 * Find h/w rate index. We know it exists because the rate 1938 * set has already been negotiated. 1939 */ 1940 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); 1941 1942 mask |= 1 << j; 1943 } 1944 1945 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1946 1947 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1948#undef RV 1949} 1950 1951/* 1952 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1953 * driver. 1954 */ 1955static void 1956rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1957{ 1958 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1959 uint32_t tmp; 1960 1961 /* update all BBP registers that depend on the band */ 1962 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1963 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1964 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1965 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1966 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1967 } 1968 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1969 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1970 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1971 } 1972 1973 rt2661_bbp_write(sc, 17, bbp17); 1974 rt2661_bbp_write(sc, 96, bbp96); 1975 rt2661_bbp_write(sc, 104, bbp104); 1976 1977 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1978 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1979 rt2661_bbp_write(sc, 75, 0x80); 1980 rt2661_bbp_write(sc, 86, 0x80); 1981 rt2661_bbp_write(sc, 88, 0x80); 1982 } 1983 1984 rt2661_bbp_write(sc, 35, bbp35); 1985 rt2661_bbp_write(sc, 97, bbp97); 1986 rt2661_bbp_write(sc, 98, bbp98); 1987 1988 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 1989 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 1990 if (IEEE80211_IS_CHAN_2GHZ(c)) 1991 tmp |= RT2661_PA_PE_2GHZ; 1992 else 1993 tmp |= RT2661_PA_PE_5GHZ; 1994 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 1995} 1996 1997static void 1998rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 1999{ 2000 struct ifnet *ifp = sc->sc_ifp; 2001 struct ieee80211com *ic = ifp->if_l2com; 2002 const struct rfprog *rfprog; 2003 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2004 int8_t power; 2005 u_int i, chan; 2006 2007 chan = ieee80211_chan2ieee(ic, c); 2008 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 2009 2010 /* select the appropriate RF settings based on what EEPROM says */ 2011 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2012 2013 /* find the settings for this channel (we know it exists) */ 2014 for (i = 0; rfprog[i].chan != chan; i++); 2015 2016 power = sc->txpow[i]; 2017 if (power < 0) { 2018 bbp94 += power; 2019 power = 0; 2020 } else if (power > 31) { 2021 bbp94 += power - 31; 2022 power = 31; 2023 } 2024 2025 /* 2026 * If we are switching from the 2GHz band to the 5GHz band or 2027 * vice-versa, BBP registers need to be reprogrammed. 2028 */ 2029 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2030 rt2661_select_band(sc, c); 2031 rt2661_select_antenna(sc); 2032 } 2033 sc->sc_curchan = c; 2034 2035 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2036 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2037 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2038 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2039 2040 DELAY(200); 2041 2042 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2043 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2044 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2045 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2046 2047 DELAY(200); 2048 2049 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2050 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2051 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2052 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2053 2054 /* enable smart mode for MIMO-capable RFs */ 2055 bbp3 = rt2661_bbp_read(sc, 3); 2056 2057 bbp3 &= ~RT2661_SMART_MODE; 2058 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2059 bbp3 |= RT2661_SMART_MODE; 2060 2061 rt2661_bbp_write(sc, 3, bbp3); 2062 2063 if (bbp94 != RT2661_BBPR94_DEFAULT) 2064 rt2661_bbp_write(sc, 94, bbp94); 2065 2066 /* 5GHz radio needs a 1ms delay here */ 2067 if (IEEE80211_IS_CHAN_5GHZ(c)) 2068 DELAY(1000); 2069} 2070 2071static void 2072rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2073{ 2074 uint32_t tmp; 2075 2076 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2077 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2078 2079 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2080 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2081} 2082 2083static void 2084rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2085{ 2086 uint32_t tmp; 2087 2088 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2089 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2090 2091 tmp = addr[4] | addr[5] << 8; 2092 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2093} 2094 2095static void 2096rt2661_update_promisc(struct ifnet *ifp) 2097{ 2098 struct rt2661_softc *sc = ifp->if_softc; 2099 uint32_t tmp; 2100 2101 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2102 2103 tmp &= ~RT2661_DROP_NOT_TO_ME; 2104 if (!(ifp->if_flags & IFF_PROMISC)) 2105 tmp |= RT2661_DROP_NOT_TO_ME; 2106 2107 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2108 2109 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2110 "entering" : "leaving"); 2111} 2112 2113/* 2114 * Update QoS (802.11e) settings for each h/w Tx ring. 2115 */ 2116static int 2117rt2661_wme_update(struct ieee80211com *ic) 2118{ 2119 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2120 const struct wmeParams *wmep; 2121 2122 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2123 2124 /* XXX: not sure about shifts. */ 2125 /* XXX: the reference driver plays with AC_VI settings too. */ 2126 2127 /* update TxOp */ 2128 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2129 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2130 wmep[WME_AC_BK].wmep_txopLimit); 2131 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2132 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2133 wmep[WME_AC_VO].wmep_txopLimit); 2134 2135 /* update CWmin */ 2136 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2137 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2138 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2139 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2140 wmep[WME_AC_VO].wmep_logcwmin); 2141 2142 /* update CWmax */ 2143 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2144 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2145 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2146 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2147 wmep[WME_AC_VO].wmep_logcwmax); 2148 2149 /* update Aifsn */ 2150 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2151 wmep[WME_AC_BE].wmep_aifsn << 12 | 2152 wmep[WME_AC_BK].wmep_aifsn << 8 | 2153 wmep[WME_AC_VI].wmep_aifsn << 4 | 2154 wmep[WME_AC_VO].wmep_aifsn); 2155 2156 return 0; 2157} 2158 2159static void 2160rt2661_update_slot(struct ifnet *ifp) 2161{ 2162 struct rt2661_softc *sc = ifp->if_softc; 2163 struct ieee80211com *ic = ifp->if_l2com; 2164 uint8_t slottime; 2165 uint32_t tmp; 2166 2167 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2168 2169 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2170 tmp = (tmp & ~0xff) | slottime; 2171 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2172} 2173 2174static const char * 2175rt2661_get_rf(int rev) 2176{ 2177 switch (rev) { 2178 case RT2661_RF_5225: return "RT5225"; 2179 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2180 case RT2661_RF_2527: return "RT2527"; 2181 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2182 default: return "unknown"; 2183 } 2184} 2185 2186static void 2187rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2188{ 2189 uint16_t val; 2190 int i; 2191 2192 /* read MAC address */ 2193 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2194 macaddr[0] = val & 0xff; 2195 macaddr[1] = val >> 8; 2196 2197 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2198 macaddr[2] = val & 0xff; 2199 macaddr[3] = val >> 8; 2200 2201 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2202 macaddr[4] = val & 0xff; 2203 macaddr[5] = val >> 8; 2204 2205 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2206 /* XXX: test if different from 0xffff? */ 2207 sc->rf_rev = (val >> 11) & 0x1f; 2208 sc->hw_radio = (val >> 10) & 0x1; 2209 sc->rx_ant = (val >> 4) & 0x3; 2210 sc->tx_ant = (val >> 2) & 0x3; 2211 sc->nb_ant = val & 0x3; 2212 2213 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2214 2215 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2216 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2217 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2218 2219 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2220 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2221 2222 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2223 if ((val & 0xff) != 0xff) 2224 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2225 2226 /* Only [-10, 10] is valid */ 2227 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2228 sc->rssi_2ghz_corr = 0; 2229 2230 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2231 if ((val & 0xff) != 0xff) 2232 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2233 2234 /* Only [-10, 10] is valid */ 2235 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2236 sc->rssi_5ghz_corr = 0; 2237 2238 /* adjust RSSI correction for external low-noise amplifier */ 2239 if (sc->ext_2ghz_lna) 2240 sc->rssi_2ghz_corr -= 14; 2241 if (sc->ext_5ghz_lna) 2242 sc->rssi_5ghz_corr -= 14; 2243 2244 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2245 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2246 2247 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2248 if ((val >> 8) != 0xff) 2249 sc->rfprog = (val >> 8) & 0x3; 2250 if ((val & 0xff) != 0xff) 2251 sc->rffreq = val & 0xff; 2252 2253 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2254 2255 /* read Tx power for all a/b/g channels */ 2256 for (i = 0; i < 19; i++) { 2257 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2258 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2259 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2260 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2261 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2262 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2263 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2264 } 2265 2266 /* read vendor-specific BBP values */ 2267 for (i = 0; i < 16; i++) { 2268 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2269 if (val == 0 || val == 0xffff) 2270 continue; /* skip invalid entries */ 2271 sc->bbp_prom[i].reg = val >> 8; 2272 sc->bbp_prom[i].val = val & 0xff; 2273 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2274 sc->bbp_prom[i].val); 2275 } 2276} 2277 2278static int 2279rt2661_bbp_init(struct rt2661_softc *sc) 2280{ 2281#define N(a) (sizeof (a) / sizeof ((a)[0])) 2282 int i, ntries; 2283 uint8_t val; 2284 2285 /* wait for BBP to be ready */ 2286 for (ntries = 0; ntries < 100; ntries++) { 2287 val = rt2661_bbp_read(sc, 0); 2288 if (val != 0 && val != 0xff) 2289 break; 2290 DELAY(100); 2291 } 2292 if (ntries == 100) { 2293 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2294 return EIO; 2295 } 2296 2297 /* initialize BBP registers to default values */ 2298 for (i = 0; i < N(rt2661_def_bbp); i++) { 2299 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2300 rt2661_def_bbp[i].val); 2301 } 2302 2303 /* write vendor-specific BBP values (from EEPROM) */ 2304 for (i = 0; i < 16; i++) { 2305 if (sc->bbp_prom[i].reg == 0) 2306 continue; 2307 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2308 } 2309 2310 return 0; 2311#undef N 2312} 2313 2314static void 2315rt2661_init_locked(struct rt2661_softc *sc) 2316{ 2317#define N(a) (sizeof (a) / sizeof ((a)[0])) 2318 struct ifnet *ifp = sc->sc_ifp; 2319 struct ieee80211com *ic = ifp->if_l2com; 2320 uint32_t tmp, sta[3]; 2321 int i, error, ntries; 2322 2323 RAL_LOCK_ASSERT(sc); 2324 2325 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2326 error = rt2661_load_microcode(sc); 2327 if (error != 0) { 2328 if_printf(ifp, 2329 "%s: could not load 8051 microcode, error %d\n", 2330 __func__, error); 2331 return; 2332 } 2333 sc->sc_flags |= RAL_FW_LOADED; 2334 } 2335 2336 rt2661_stop_locked(sc); 2337 2338 /* initialize Tx rings */ 2339 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2340 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2341 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2342 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2343 2344 /* initialize Mgt ring */ 2345 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2346 2347 /* initialize Rx ring */ 2348 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2349 2350 /* initialize Tx rings sizes */ 2351 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2352 RT2661_TX_RING_COUNT << 24 | 2353 RT2661_TX_RING_COUNT << 16 | 2354 RT2661_TX_RING_COUNT << 8 | 2355 RT2661_TX_RING_COUNT); 2356 2357 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2358 RT2661_TX_DESC_WSIZE << 16 | 2359 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2360 RT2661_MGT_RING_COUNT); 2361 2362 /* initialize Rx rings */ 2363 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2364 RT2661_RX_DESC_BACK << 16 | 2365 RT2661_RX_DESC_WSIZE << 8 | 2366 RT2661_RX_RING_COUNT); 2367 2368 /* XXX: some magic here */ 2369 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2370 2371 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2372 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2373 2374 /* load base address of Rx ring */ 2375 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2376 2377 /* initialize MAC registers to default values */ 2378 for (i = 0; i < N(rt2661_def_mac); i++) 2379 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2380 2381 rt2661_set_macaddr(sc, IF_LLADDR(ifp)); 2382 2383 /* set host ready */ 2384 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2385 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2386 2387 /* wait for BBP/RF to wakeup */ 2388 for (ntries = 0; ntries < 1000; ntries++) { 2389 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2390 break; 2391 DELAY(1000); 2392 } 2393 if (ntries == 1000) { 2394 printf("timeout waiting for BBP/RF to wakeup\n"); 2395 rt2661_stop_locked(sc); 2396 return; 2397 } 2398 2399 if (rt2661_bbp_init(sc) != 0) { 2400 rt2661_stop_locked(sc); 2401 return; 2402 } 2403 2404 /* select default channel */ 2405 sc->sc_curchan = ic->ic_curchan; 2406 rt2661_select_band(sc, sc->sc_curchan); 2407 rt2661_select_antenna(sc); 2408 rt2661_set_chan(sc, sc->sc_curchan); 2409 2410 /* update Rx filter */ 2411 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2412 2413 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2414 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2415 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2416 RT2661_DROP_ACKCTS; 2417 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2418 ic->ic_opmode != IEEE80211_M_MBSS) 2419 tmp |= RT2661_DROP_TODS; 2420 if (!(ifp->if_flags & IFF_PROMISC)) 2421 tmp |= RT2661_DROP_NOT_TO_ME; 2422 } 2423 2424 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2425 2426 /* clear STA registers */ 2427 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2428 2429 /* initialize ASIC */ 2430 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2431 2432 /* clear any pending interrupt */ 2433 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2434 2435 /* enable interrupts */ 2436 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2437 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2438 2439 /* kick Rx */ 2440 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2441 2442 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2443 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2444 2445 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2446#undef N 2447} 2448 2449static void 2450rt2661_init(void *priv) 2451{ 2452 struct rt2661_softc *sc = priv; 2453 struct ifnet *ifp = sc->sc_ifp; 2454 struct ieee80211com *ic = ifp->if_l2com; 2455 2456 RAL_LOCK(sc); 2457 rt2661_init_locked(sc); 2458 RAL_UNLOCK(sc); 2459 2460 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2461 ieee80211_start_all(ic); /* start all vap's */ 2462} 2463 2464void 2465rt2661_stop_locked(struct rt2661_softc *sc) 2466{ 2467 struct ifnet *ifp = sc->sc_ifp; 2468 uint32_t tmp; 2469 volatile int *flags = &sc->sc_flags; 2470 2471 while (*flags & RAL_INPUT_RUNNING) 2472 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2473 2474 callout_stop(&sc->watchdog_ch); 2475 sc->sc_tx_timer = 0; 2476 2477 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2478 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2479 2480 /* abort Tx (for all 5 Tx rings) */ 2481 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2482 2483 /* disable Rx (value remains after reset!) */ 2484 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2485 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2486 2487 /* reset ASIC */ 2488 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2489 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2490 2491 /* disable interrupts */ 2492 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2493 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2494 2495 /* clear any pending interrupt */ 2496 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2497 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2498 2499 /* reset Tx and Rx rings */ 2500 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2501 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2502 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2503 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2504 rt2661_reset_tx_ring(sc, &sc->mgtq); 2505 rt2661_reset_rx_ring(sc, &sc->rxq); 2506 } 2507} 2508 2509void 2510rt2661_stop(void *priv) 2511{ 2512 struct rt2661_softc *sc = priv; 2513 2514 RAL_LOCK(sc); 2515 rt2661_stop_locked(sc); 2516 RAL_UNLOCK(sc); 2517} 2518 2519static int 2520rt2661_load_microcode(struct rt2661_softc *sc) 2521{ 2522 struct ifnet *ifp = sc->sc_ifp; 2523 const struct firmware *fp; 2524 const char *imagename; 2525 int ntries, error; 2526 2527 RAL_LOCK_ASSERT(sc); 2528 2529 switch (sc->sc_id) { 2530 case 0x0301: imagename = "rt2561sfw"; break; 2531 case 0x0302: imagename = "rt2561fw"; break; 2532 case 0x0401: imagename = "rt2661fw"; break; 2533 default: 2534 if_printf(ifp, "%s: unexpected pci device id 0x%x, " 2535 "don't know how to retrieve firmware\n", 2536 __func__, sc->sc_id); 2537 return EINVAL; 2538 } 2539 RAL_UNLOCK(sc); 2540 fp = firmware_get(imagename); 2541 RAL_LOCK(sc); 2542 if (fp == NULL) { 2543 if_printf(ifp, "%s: unable to retrieve firmware image %s\n", 2544 __func__, imagename); 2545 return EINVAL; 2546 } 2547 2548 /* 2549 * Load 8051 microcode into NIC. 2550 */ 2551 /* reset 8051 */ 2552 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2553 2554 /* cancel any pending Host to MCU command */ 2555 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2556 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2557 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2558 2559 /* write 8051's microcode */ 2560 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2561 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2562 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2563 2564 /* kick 8051's ass */ 2565 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2566 2567 /* wait for 8051 to initialize */ 2568 for (ntries = 0; ntries < 500; ntries++) { 2569 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2570 break; 2571 DELAY(100); 2572 } 2573 if (ntries == 500) { 2574 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n", 2575 __func__); 2576 error = EIO; 2577 } else 2578 error = 0; 2579 2580 firmware_put(fp, FIRMWARE_UNLOAD); 2581 return error; 2582} 2583 2584#ifdef notyet 2585/* 2586 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2587 * false CCA count. This function is called periodically (every seconds) when 2588 * in the RUN state. Values taken from the reference driver. 2589 */ 2590static void 2591rt2661_rx_tune(struct rt2661_softc *sc) 2592{ 2593 uint8_t bbp17; 2594 uint16_t cca; 2595 int lo, hi, dbm; 2596 2597 /* 2598 * Tuning range depends on operating band and on the presence of an 2599 * external low-noise amplifier. 2600 */ 2601 lo = 0x20; 2602 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2603 lo += 0x08; 2604 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2605 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2606 lo += 0x10; 2607 hi = lo + 0x20; 2608 2609 /* retrieve false CCA count since last call (clear on read) */ 2610 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2611 2612 if (dbm >= -35) { 2613 bbp17 = 0x60; 2614 } else if (dbm >= -58) { 2615 bbp17 = hi; 2616 } else if (dbm >= -66) { 2617 bbp17 = lo + 0x10; 2618 } else if (dbm >= -74) { 2619 bbp17 = lo + 0x08; 2620 } else { 2621 /* RSSI < -74dBm, tune using false CCA count */ 2622 2623 bbp17 = sc->bbp17; /* current value */ 2624 2625 hi -= 2 * (-74 - dbm); 2626 if (hi < lo) 2627 hi = lo; 2628 2629 if (bbp17 > hi) { 2630 bbp17 = hi; 2631 2632 } else if (cca > 512) { 2633 if (++bbp17 > hi) 2634 bbp17 = hi; 2635 } else if (cca < 100) { 2636 if (--bbp17 < lo) 2637 bbp17 = lo; 2638 } 2639 } 2640 2641 if (bbp17 != sc->bbp17) { 2642 rt2661_bbp_write(sc, 17, bbp17); 2643 sc->bbp17 = bbp17; 2644 } 2645} 2646 2647/* 2648 * Enter/Leave radar detection mode. 2649 * This is for 802.11h additional regulatory domains. 2650 */ 2651static void 2652rt2661_radar_start(struct rt2661_softc *sc) 2653{ 2654 uint32_t tmp; 2655 2656 /* disable Rx */ 2657 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2658 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2659 2660 rt2661_bbp_write(sc, 82, 0x20); 2661 rt2661_bbp_write(sc, 83, 0x00); 2662 rt2661_bbp_write(sc, 84, 0x40); 2663 2664 /* save current BBP registers values */ 2665 sc->bbp18 = rt2661_bbp_read(sc, 18); 2666 sc->bbp21 = rt2661_bbp_read(sc, 21); 2667 sc->bbp22 = rt2661_bbp_read(sc, 22); 2668 sc->bbp16 = rt2661_bbp_read(sc, 16); 2669 sc->bbp17 = rt2661_bbp_read(sc, 17); 2670 sc->bbp64 = rt2661_bbp_read(sc, 64); 2671 2672 rt2661_bbp_write(sc, 18, 0xff); 2673 rt2661_bbp_write(sc, 21, 0x3f); 2674 rt2661_bbp_write(sc, 22, 0x3f); 2675 rt2661_bbp_write(sc, 16, 0xbd); 2676 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2677 rt2661_bbp_write(sc, 64, 0x21); 2678 2679 /* restore Rx filter */ 2680 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2681} 2682 2683static int 2684rt2661_radar_stop(struct rt2661_softc *sc) 2685{ 2686 uint8_t bbp66; 2687 2688 /* read radar detection result */ 2689 bbp66 = rt2661_bbp_read(sc, 66); 2690 2691 /* restore BBP registers values */ 2692 rt2661_bbp_write(sc, 16, sc->bbp16); 2693 rt2661_bbp_write(sc, 17, sc->bbp17); 2694 rt2661_bbp_write(sc, 18, sc->bbp18); 2695 rt2661_bbp_write(sc, 21, sc->bbp21); 2696 rt2661_bbp_write(sc, 22, sc->bbp22); 2697 rt2661_bbp_write(sc, 64, sc->bbp64); 2698 2699 return bbp66 == 1; 2700} 2701#endif 2702 2703static int 2704rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2705{ 2706 struct ieee80211com *ic = vap->iv_ic; 2707 struct ieee80211_beacon_offsets bo; 2708 struct rt2661_tx_desc desc; 2709 struct mbuf *m0; 2710 int rate; 2711 2712 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo); 2713 if (m0 == NULL) { 2714 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2715 return ENOBUFS; 2716 } 2717 2718 /* send beacons at the lowest available rate */ 2719 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2720 2721 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2722 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2723 2724 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2725 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2726 2727 /* copy beacon header and payload into NIC memory */ 2728 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2729 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2730 2731 m_freem(m0); 2732 2733 return 0; 2734} 2735 2736/* 2737 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2738 * and HostAP operating modes. 2739 */ 2740static void 2741rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2742{ 2743 struct ifnet *ifp = sc->sc_ifp; 2744 struct ieee80211com *ic = ifp->if_l2com; 2745 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2746 uint32_t tmp; 2747 2748 if (vap->iv_opmode != IEEE80211_M_STA) { 2749 /* 2750 * Change default 16ms TBTT adjustment to 8ms. 2751 * Must be done before enabling beacon generation. 2752 */ 2753 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2754 } 2755 2756 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2757 2758 /* set beacon interval (in 1/16ms unit) */ 2759 tmp |= vap->iv_bss->ni_intval * 16; 2760 2761 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2762 if (vap->iv_opmode == IEEE80211_M_STA) 2763 tmp |= RT2661_TSF_MODE(1); 2764 else 2765 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2766 2767 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2768} 2769 2770static void 2771rt2661_enable_tsf(struct rt2661_softc *sc) 2772{ 2773 RAL_WRITE(sc, RT2661_TXRX_CSR9, 2774 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000) 2775 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2)); 2776} 2777 2778/* 2779 * Retrieve the "Received Signal Strength Indicator" from the raw values 2780 * contained in Rx descriptors. The computation depends on which band the 2781 * frame was received. Correction values taken from the reference driver. 2782 */ 2783static int 2784rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2785{ 2786 int lna, agc, rssi; 2787 2788 lna = (raw >> 5) & 0x3; 2789 agc = raw & 0x1f; 2790 2791 if (lna == 0) { 2792 /* 2793 * No mapping available. 2794 * 2795 * NB: Since RSSI is relative to noise floor, -1 is 2796 * adequate for caller to know error happened. 2797 */ 2798 return -1; 2799 } 2800 2801 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2802 2803 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2804 rssi += sc->rssi_2ghz_corr; 2805 2806 if (lna == 1) 2807 rssi -= 64; 2808 else if (lna == 2) 2809 rssi -= 74; 2810 else if (lna == 3) 2811 rssi -= 90; 2812 } else { 2813 rssi += sc->rssi_5ghz_corr; 2814 2815 if (lna == 1) 2816 rssi -= 64; 2817 else if (lna == 2) 2818 rssi -= 86; 2819 else if (lna == 3) 2820 rssi -= 100; 2821 } 2822 return rssi; 2823} 2824 2825static void 2826rt2661_scan_start(struct ieee80211com *ic) 2827{ 2828 struct ifnet *ifp = ic->ic_ifp; 2829 struct rt2661_softc *sc = ifp->if_softc; 2830 uint32_t tmp; 2831 2832 /* abort TSF synchronization */ 2833 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2834 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2835 rt2661_set_bssid(sc, ifp->if_broadcastaddr); 2836} 2837 2838static void 2839rt2661_scan_end(struct ieee80211com *ic) 2840{ 2841 struct ifnet *ifp = ic->ic_ifp; 2842 struct rt2661_softc *sc = ifp->if_softc; 2843 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2844 2845 rt2661_enable_tsf_sync(sc); 2846 /* XXX keep local copy */ 2847 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2848} 2849 2850static void 2851rt2661_set_channel(struct ieee80211com *ic) 2852{ 2853 struct ifnet *ifp = ic->ic_ifp; 2854 struct rt2661_softc *sc = ifp->if_softc; 2855 2856 RAL_LOCK(sc); 2857 rt2661_set_chan(sc, ic->ic_curchan); 2858 RAL_UNLOCK(sc); 2859 2860} 2861