rt2661.c revision 207554
1/* $FreeBSD: head/sys/dev/ral/rt2661.c 207554 2010-05-03 07:32:50Z sobomax $ */ 2 3/*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2661.c 207554 2010-05-03 07:32:50Z sobomax $"); 22 23/*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_arp.h> 50#include <net/ethernet.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54 55#include <net80211/ieee80211_var.h> 56#include <net80211/ieee80211_radiotap.h> 57#include <net80211/ieee80211_regdomain.h> 58#include <net80211/ieee80211_ratectl.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/in_var.h> 63#include <netinet/ip.h> 64#include <netinet/if_ether.h> 65 66#include <dev/ral/rt2661reg.h> 67#include <dev/ral/rt2661var.h> 68 69#define RAL_DEBUG 70#ifdef RAL_DEBUG 71#define DPRINTF(sc, fmt, ...) do { \ 72 if (sc->sc_debug > 0) \ 73 printf(fmt, __VA_ARGS__); \ 74} while (0) 75#define DPRINTFN(sc, n, fmt, ...) do { \ 76 if (sc->sc_debug >= (n)) \ 77 printf(fmt, __VA_ARGS__); \ 78} while (0) 79#else 80#define DPRINTF(sc, fmt, ...) 81#define DPRINTFN(sc, n, fmt, ...) 82#endif 83 84static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 85 const char name[IFNAMSIZ], int unit, int opmode, 86 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 87 const uint8_t mac[IEEE80211_ADDR_LEN]); 88static void rt2661_vap_delete(struct ieee80211vap *); 89static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 90 int); 91static int rt2661_alloc_tx_ring(struct rt2661_softc *, 92 struct rt2661_tx_ring *, int); 93static void rt2661_reset_tx_ring(struct rt2661_softc *, 94 struct rt2661_tx_ring *); 95static void rt2661_free_tx_ring(struct rt2661_softc *, 96 struct rt2661_tx_ring *); 97static int rt2661_alloc_rx_ring(struct rt2661_softc *, 98 struct rt2661_rx_ring *, int); 99static void rt2661_reset_rx_ring(struct rt2661_softc *, 100 struct rt2661_rx_ring *); 101static void rt2661_free_rx_ring(struct rt2661_softc *, 102 struct rt2661_rx_ring *); 103static void rt2661_newassoc(struct ieee80211_node *, int); 104static int rt2661_newstate(struct ieee80211vap *, 105 enum ieee80211_state, int); 106static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 107static void rt2661_rx_intr(struct rt2661_softc *); 108static void rt2661_tx_intr(struct rt2661_softc *); 109static void rt2661_tx_dma_intr(struct rt2661_softc *, 110 struct rt2661_tx_ring *); 111static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 112static void rt2661_mcu_wakeup(struct rt2661_softc *); 113static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 114static void rt2661_scan_start(struct ieee80211com *); 115static void rt2661_scan_end(struct ieee80211com *); 116static void rt2661_set_channel(struct ieee80211com *); 117static void rt2661_setup_tx_desc(struct rt2661_softc *, 118 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 119 int, const bus_dma_segment_t *, int, int); 120static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 121 struct ieee80211_node *, int); 122static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 123 struct ieee80211_node *); 124static void rt2661_start_locked(struct ifnet *); 125static void rt2661_start(struct ifnet *); 126static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 127 const struct ieee80211_bpf_params *); 128static void rt2661_watchdog(void *); 129static int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 130static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 131 uint8_t); 132static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 133static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 134 uint32_t); 135static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 136 uint16_t); 137static void rt2661_select_antenna(struct rt2661_softc *); 138static void rt2661_enable_mrr(struct rt2661_softc *); 139static void rt2661_set_txpreamble(struct rt2661_softc *); 140static void rt2661_set_basicrates(struct rt2661_softc *, 141 const struct ieee80211_rateset *); 142static void rt2661_select_band(struct rt2661_softc *, 143 struct ieee80211_channel *); 144static void rt2661_set_chan(struct rt2661_softc *, 145 struct ieee80211_channel *); 146static void rt2661_set_bssid(struct rt2661_softc *, 147 const uint8_t *); 148static void rt2661_set_macaddr(struct rt2661_softc *, 149 const uint8_t *); 150static void rt2661_update_promisc(struct ifnet *); 151static int rt2661_wme_update(struct ieee80211com *) __unused; 152static void rt2661_update_slot(struct ifnet *); 153static const char *rt2661_get_rf(int); 154static void rt2661_read_eeprom(struct rt2661_softc *, 155 uint8_t macaddr[IEEE80211_ADDR_LEN]); 156static int rt2661_bbp_init(struct rt2661_softc *); 157static void rt2661_init_locked(struct rt2661_softc *); 158static void rt2661_init(void *); 159static void rt2661_stop_locked(struct rt2661_softc *); 160static void rt2661_stop(void *); 161static int rt2661_load_microcode(struct rt2661_softc *); 162#ifdef notyet 163static void rt2661_rx_tune(struct rt2661_softc *); 164static void rt2661_radar_start(struct rt2661_softc *); 165static int rt2661_radar_stop(struct rt2661_softc *); 166#endif 167static int rt2661_prepare_beacon(struct rt2661_softc *, 168 struct ieee80211vap *); 169static void rt2661_enable_tsf_sync(struct rt2661_softc *); 170static void rt2661_enable_tsf(struct rt2661_softc *); 171static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 172 173static const struct { 174 uint32_t reg; 175 uint32_t val; 176} rt2661_def_mac[] = { 177 RT2661_DEF_MAC 178}; 179 180static const struct { 181 uint8_t reg; 182 uint8_t val; 183} rt2661_def_bbp[] = { 184 RT2661_DEF_BBP 185}; 186 187static const struct rfprog { 188 uint8_t chan; 189 uint32_t r1, r2, r3, r4; 190} rt2661_rf5225_1[] = { 191 RT2661_RF5225_1 192}, rt2661_rf5225_2[] = { 193 RT2661_RF5225_2 194}; 195 196int 197rt2661_attach(device_t dev, int id) 198{ 199 struct rt2661_softc *sc = device_get_softc(dev); 200 struct ieee80211com *ic; 201 struct ifnet *ifp; 202 uint32_t val; 203 int error, ac, ntries; 204 uint8_t bands; 205 uint8_t macaddr[IEEE80211_ADDR_LEN]; 206 207 sc->sc_id = id; 208 sc->sc_dev = dev; 209 210 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 211 if (ifp == NULL) { 212 device_printf(sc->sc_dev, "can not if_alloc()\n"); 213 return ENOMEM; 214 } 215 ic = ifp->if_l2com; 216 217 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 218 MTX_DEF | MTX_RECURSE); 219 220 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 221 222 /* wait for NIC to initialize */ 223 for (ntries = 0; ntries < 1000; ntries++) { 224 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 225 break; 226 DELAY(1000); 227 } 228 if (ntries == 1000) { 229 device_printf(sc->sc_dev, 230 "timeout waiting for NIC to initialize\n"); 231 error = EIO; 232 goto fail1; 233 } 234 235 /* retrieve RF rev. no and various other things from EEPROM */ 236 rt2661_read_eeprom(sc, macaddr); 237 238 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 239 rt2661_get_rf(sc->rf_rev)); 240 241 /* 242 * Allocate Tx and Rx rings. 243 */ 244 for (ac = 0; ac < 4; ac++) { 245 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 246 RT2661_TX_RING_COUNT); 247 if (error != 0) { 248 device_printf(sc->sc_dev, 249 "could not allocate Tx ring %d\n", ac); 250 goto fail2; 251 } 252 } 253 254 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 255 if (error != 0) { 256 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 257 goto fail2; 258 } 259 260 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 261 if (error != 0) { 262 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 263 goto fail3; 264 } 265 266 ifp->if_softc = sc; 267 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 268 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 269 ifp->if_init = rt2661_init; 270 ifp->if_ioctl = rt2661_ioctl; 271 ifp->if_start = rt2661_start; 272 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 273 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 274 IFQ_SET_READY(&ifp->if_snd); 275 276 ic->ic_ifp = ifp; 277 ic->ic_opmode = IEEE80211_M_STA; 278 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 279 280 /* set device capabilities */ 281 ic->ic_caps = 282 IEEE80211_C_STA /* station mode */ 283 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 284 | IEEE80211_C_HOSTAP /* hostap mode */ 285 | IEEE80211_C_MONITOR /* monitor mode */ 286 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 287 | IEEE80211_C_WDS /* 4-address traffic works */ 288 | IEEE80211_C_MBSS /* mesh point link mode */ 289 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 290 | IEEE80211_C_SHSLOT /* short slot time supported */ 291 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 292 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 293#ifdef notyet 294 | IEEE80211_C_TXFRAG /* handle tx frags */ 295 | IEEE80211_C_WME /* 802.11e */ 296#endif 297 ; 298 299 bands = 0; 300 setbit(&bands, IEEE80211_MODE_11B); 301 setbit(&bands, IEEE80211_MODE_11G); 302 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) 303 setbit(&bands, IEEE80211_MODE_11A); 304 ieee80211_init_channels(ic, NULL, &bands); 305 306 ieee80211_ifattach(ic, macaddr); 307 ic->ic_newassoc = rt2661_newassoc; 308#if 0 309 ic->ic_wme.wme_update = rt2661_wme_update; 310#endif 311 ic->ic_scan_start = rt2661_scan_start; 312 ic->ic_scan_end = rt2661_scan_end; 313 ic->ic_set_channel = rt2661_set_channel; 314 ic->ic_updateslot = rt2661_update_slot; 315 ic->ic_update_promisc = rt2661_update_promisc; 316 ic->ic_raw_xmit = rt2661_raw_xmit; 317 318 ic->ic_vap_create = rt2661_vap_create; 319 ic->ic_vap_delete = rt2661_vap_delete; 320 321 ieee80211_radiotap_attach(ic, 322 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 323 RT2661_TX_RADIOTAP_PRESENT, 324 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 325 RT2661_RX_RADIOTAP_PRESENT); 326 327#ifdef RAL_DEBUG 328 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 329 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 330 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 331#endif 332 if (bootverbose) 333 ieee80211_announce(ic); 334 335 return 0; 336 337fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 338fail2: while (--ac >= 0) 339 rt2661_free_tx_ring(sc, &sc->txq[ac]); 340fail1: mtx_destroy(&sc->sc_mtx); 341 if_free(ifp); 342 return error; 343} 344 345int 346rt2661_detach(void *xsc) 347{ 348 struct rt2661_softc *sc = xsc; 349 struct ifnet *ifp = sc->sc_ifp; 350 struct ieee80211com *ic = ifp->if_l2com; 351 352 RAL_LOCK(sc); 353 rt2661_stop_locked(sc); 354 RAL_UNLOCK(sc); 355 356 ieee80211_ifdetach(ic); 357 358 rt2661_free_tx_ring(sc, &sc->txq[0]); 359 rt2661_free_tx_ring(sc, &sc->txq[1]); 360 rt2661_free_tx_ring(sc, &sc->txq[2]); 361 rt2661_free_tx_ring(sc, &sc->txq[3]); 362 rt2661_free_tx_ring(sc, &sc->mgtq); 363 rt2661_free_rx_ring(sc, &sc->rxq); 364 365 if_free(ifp); 366 367 mtx_destroy(&sc->sc_mtx); 368 369 return 0; 370} 371 372static struct ieee80211vap * 373rt2661_vap_create(struct ieee80211com *ic, 374 const char name[IFNAMSIZ], int unit, int opmode, int flags, 375 const uint8_t bssid[IEEE80211_ADDR_LEN], 376 const uint8_t mac[IEEE80211_ADDR_LEN]) 377{ 378 struct ifnet *ifp = ic->ic_ifp; 379 struct rt2661_vap *rvp; 380 struct ieee80211vap *vap; 381 382 switch (opmode) { 383 case IEEE80211_M_STA: 384 case IEEE80211_M_IBSS: 385 case IEEE80211_M_AHDEMO: 386 case IEEE80211_M_MONITOR: 387 case IEEE80211_M_HOSTAP: 388 case IEEE80211_M_MBSS: 389 /* XXXRP: TBD */ 390 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 391 if_printf(ifp, "only 1 vap supported\n"); 392 return NULL; 393 } 394 if (opmode == IEEE80211_M_STA) 395 flags |= IEEE80211_CLONE_NOBEACONS; 396 break; 397 case IEEE80211_M_WDS: 398 if (TAILQ_EMPTY(&ic->ic_vaps) || 399 ic->ic_opmode != IEEE80211_M_HOSTAP) { 400 if_printf(ifp, "wds only supported in ap mode\n"); 401 return NULL; 402 } 403 /* 404 * Silently remove any request for a unique 405 * bssid; WDS vap's always share the local 406 * mac address. 407 */ 408 flags &= ~IEEE80211_CLONE_BSSID; 409 break; 410 default: 411 if_printf(ifp, "unknown opmode %d\n", opmode); 412 return NULL; 413 } 414 rvp = (struct rt2661_vap *) malloc(sizeof(struct rt2661_vap), 415 M_80211_VAP, M_NOWAIT | M_ZERO); 416 if (rvp == NULL) 417 return NULL; 418 vap = &rvp->ral_vap; 419 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 420 421 /* override state transition machine */ 422 rvp->ral_newstate = vap->iv_newstate; 423 vap->iv_newstate = rt2661_newstate; 424#if 0 425 vap->iv_update_beacon = rt2661_beacon_update; 426#endif 427 428 ieee80211_ratectl_init(vap); 429 /* complete setup */ 430 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 431 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 432 ic->ic_opmode = opmode; 433 return vap; 434} 435 436static void 437rt2661_vap_delete(struct ieee80211vap *vap) 438{ 439 struct rt2661_vap *rvp = RT2661_VAP(vap); 440 441 ieee80211_ratectl_deinit(vap); 442 ieee80211_vap_detach(vap); 443 free(rvp, M_80211_VAP); 444} 445 446void 447rt2661_shutdown(void *xsc) 448{ 449 struct rt2661_softc *sc = xsc; 450 451 rt2661_stop(sc); 452} 453 454void 455rt2661_suspend(void *xsc) 456{ 457 struct rt2661_softc *sc = xsc; 458 459 rt2661_stop(sc); 460} 461 462void 463rt2661_resume(void *xsc) 464{ 465 struct rt2661_softc *sc = xsc; 466 struct ifnet *ifp = sc->sc_ifp; 467 468 if (ifp->if_flags & IFF_UP) 469 rt2661_init(sc); 470} 471 472static void 473rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 474{ 475 if (error != 0) 476 return; 477 478 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 479 480 *(bus_addr_t *)arg = segs[0].ds_addr; 481} 482 483static int 484rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 485 int count) 486{ 487 int i, error; 488 489 ring->count = count; 490 ring->queued = 0; 491 ring->cur = ring->next = ring->stat = 0; 492 493 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 494 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 495 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 496 0, NULL, NULL, &ring->desc_dmat); 497 if (error != 0) { 498 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 499 goto fail; 500 } 501 502 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 503 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 504 if (error != 0) { 505 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 506 goto fail; 507 } 508 509 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 510 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 511 0); 512 if (error != 0) { 513 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 514 goto fail; 515 } 516 517 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 518 M_NOWAIT | M_ZERO); 519 if (ring->data == NULL) { 520 device_printf(sc->sc_dev, "could not allocate soft data\n"); 521 error = ENOMEM; 522 goto fail; 523 } 524 525 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 526 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 527 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 528 if (error != 0) { 529 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 530 goto fail; 531 } 532 533 for (i = 0; i < count; i++) { 534 error = bus_dmamap_create(ring->data_dmat, 0, 535 &ring->data[i].map); 536 if (error != 0) { 537 device_printf(sc->sc_dev, "could not create DMA map\n"); 538 goto fail; 539 } 540 } 541 542 return 0; 543 544fail: rt2661_free_tx_ring(sc, ring); 545 return error; 546} 547 548static void 549rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 550{ 551 struct rt2661_tx_desc *desc; 552 struct rt2661_tx_data *data; 553 int i; 554 555 for (i = 0; i < ring->count; i++) { 556 desc = &ring->desc[i]; 557 data = &ring->data[i]; 558 559 if (data->m != NULL) { 560 bus_dmamap_sync(ring->data_dmat, data->map, 561 BUS_DMASYNC_POSTWRITE); 562 bus_dmamap_unload(ring->data_dmat, data->map); 563 m_freem(data->m); 564 data->m = NULL; 565 } 566 567 if (data->ni != NULL) { 568 ieee80211_free_node(data->ni); 569 data->ni = NULL; 570 } 571 572 desc->flags = 0; 573 } 574 575 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 576 577 ring->queued = 0; 578 ring->cur = ring->next = ring->stat = 0; 579} 580 581static void 582rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 583{ 584 struct rt2661_tx_data *data; 585 int i; 586 587 if (ring->desc != NULL) { 588 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 589 BUS_DMASYNC_POSTWRITE); 590 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 591 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 592 } 593 594 if (ring->desc_dmat != NULL) 595 bus_dma_tag_destroy(ring->desc_dmat); 596 597 if (ring->data != NULL) { 598 for (i = 0; i < ring->count; i++) { 599 data = &ring->data[i]; 600 601 if (data->m != NULL) { 602 bus_dmamap_sync(ring->data_dmat, data->map, 603 BUS_DMASYNC_POSTWRITE); 604 bus_dmamap_unload(ring->data_dmat, data->map); 605 m_freem(data->m); 606 } 607 608 if (data->ni != NULL) 609 ieee80211_free_node(data->ni); 610 611 if (data->map != NULL) 612 bus_dmamap_destroy(ring->data_dmat, data->map); 613 } 614 615 free(ring->data, M_DEVBUF); 616 } 617 618 if (ring->data_dmat != NULL) 619 bus_dma_tag_destroy(ring->data_dmat); 620} 621 622static int 623rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 624 int count) 625{ 626 struct rt2661_rx_desc *desc; 627 struct rt2661_rx_data *data; 628 bus_addr_t physaddr; 629 int i, error; 630 631 ring->count = count; 632 ring->cur = ring->next = 0; 633 634 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 635 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 636 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 637 0, NULL, NULL, &ring->desc_dmat); 638 if (error != 0) { 639 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 640 goto fail; 641 } 642 643 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 644 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 645 if (error != 0) { 646 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 647 goto fail; 648 } 649 650 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 651 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 652 0); 653 if (error != 0) { 654 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 655 goto fail; 656 } 657 658 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 659 M_NOWAIT | M_ZERO); 660 if (ring->data == NULL) { 661 device_printf(sc->sc_dev, "could not allocate soft data\n"); 662 error = ENOMEM; 663 goto fail; 664 } 665 666 /* 667 * Pre-allocate Rx buffers and populate Rx ring. 668 */ 669 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 670 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 671 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 672 if (error != 0) { 673 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 674 goto fail; 675 } 676 677 for (i = 0; i < count; i++) { 678 desc = &sc->rxq.desc[i]; 679 data = &sc->rxq.data[i]; 680 681 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 682 if (error != 0) { 683 device_printf(sc->sc_dev, "could not create DMA map\n"); 684 goto fail; 685 } 686 687 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 688 if (data->m == NULL) { 689 device_printf(sc->sc_dev, 690 "could not allocate rx mbuf\n"); 691 error = ENOMEM; 692 goto fail; 693 } 694 695 error = bus_dmamap_load(ring->data_dmat, data->map, 696 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 697 &physaddr, 0); 698 if (error != 0) { 699 device_printf(sc->sc_dev, 700 "could not load rx buf DMA map"); 701 goto fail; 702 } 703 704 desc->flags = htole32(RT2661_RX_BUSY); 705 desc->physaddr = htole32(physaddr); 706 } 707 708 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 709 710 return 0; 711 712fail: rt2661_free_rx_ring(sc, ring); 713 return error; 714} 715 716static void 717rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 718{ 719 int i; 720 721 for (i = 0; i < ring->count; i++) 722 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 723 724 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 725 726 ring->cur = ring->next = 0; 727} 728 729static void 730rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 731{ 732 struct rt2661_rx_data *data; 733 int i; 734 735 if (ring->desc != NULL) { 736 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 737 BUS_DMASYNC_POSTWRITE); 738 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 739 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 740 } 741 742 if (ring->desc_dmat != NULL) 743 bus_dma_tag_destroy(ring->desc_dmat); 744 745 if (ring->data != NULL) { 746 for (i = 0; i < ring->count; i++) { 747 data = &ring->data[i]; 748 749 if (data->m != NULL) { 750 bus_dmamap_sync(ring->data_dmat, data->map, 751 BUS_DMASYNC_POSTREAD); 752 bus_dmamap_unload(ring->data_dmat, data->map); 753 m_freem(data->m); 754 } 755 756 if (data->map != NULL) 757 bus_dmamap_destroy(ring->data_dmat, data->map); 758 } 759 760 free(ring->data, M_DEVBUF); 761 } 762 763 if (ring->data_dmat != NULL) 764 bus_dma_tag_destroy(ring->data_dmat); 765} 766 767static void 768rt2661_newassoc(struct ieee80211_node *ni, int isnew) 769{ 770 /* XXX move */ 771 ieee80211_ratectl_node_init(ni); 772} 773 774static int 775rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 776{ 777 struct rt2661_vap *rvp = RT2661_VAP(vap); 778 struct ieee80211com *ic = vap->iv_ic; 779 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 780 int error; 781 782 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 783 uint32_t tmp; 784 785 /* abort TSF synchronization */ 786 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 787 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 788 } 789 790 error = rvp->ral_newstate(vap, nstate, arg); 791 792 if (error == 0 && nstate == IEEE80211_S_RUN) { 793 struct ieee80211_node *ni = vap->iv_bss; 794 795 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 796 rt2661_enable_mrr(sc); 797 rt2661_set_txpreamble(sc); 798 rt2661_set_basicrates(sc, &ni->ni_rates); 799 rt2661_set_bssid(sc, ni->ni_bssid); 800 } 801 802 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 803 vap->iv_opmode == IEEE80211_M_IBSS || 804 vap->iv_opmode == IEEE80211_M_MBSS) { 805 error = rt2661_prepare_beacon(sc, vap); 806 if (error != 0) 807 return error; 808 } 809 if (vap->iv_opmode != IEEE80211_M_MONITOR) 810 rt2661_enable_tsf_sync(sc); 811 else 812 rt2661_enable_tsf(sc); 813 } 814 return error; 815} 816 817/* 818 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 819 * 93C66). 820 */ 821static uint16_t 822rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 823{ 824 uint32_t tmp; 825 uint16_t val; 826 int n; 827 828 /* clock C once before the first command */ 829 RT2661_EEPROM_CTL(sc, 0); 830 831 RT2661_EEPROM_CTL(sc, RT2661_S); 832 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 833 RT2661_EEPROM_CTL(sc, RT2661_S); 834 835 /* write start bit (1) */ 836 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 837 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 838 839 /* write READ opcode (10) */ 840 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 841 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 842 RT2661_EEPROM_CTL(sc, RT2661_S); 843 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 844 845 /* write address (A5-A0 or A7-A0) */ 846 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 847 for (; n >= 0; n--) { 848 RT2661_EEPROM_CTL(sc, RT2661_S | 849 (((addr >> n) & 1) << RT2661_SHIFT_D)); 850 RT2661_EEPROM_CTL(sc, RT2661_S | 851 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 852 } 853 854 RT2661_EEPROM_CTL(sc, RT2661_S); 855 856 /* read data Q15-Q0 */ 857 val = 0; 858 for (n = 15; n >= 0; n--) { 859 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 860 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 861 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 862 RT2661_EEPROM_CTL(sc, RT2661_S); 863 } 864 865 RT2661_EEPROM_CTL(sc, 0); 866 867 /* clear Chip Select and clock C */ 868 RT2661_EEPROM_CTL(sc, RT2661_S); 869 RT2661_EEPROM_CTL(sc, 0); 870 RT2661_EEPROM_CTL(sc, RT2661_C); 871 872 return val; 873} 874 875static void 876rt2661_tx_intr(struct rt2661_softc *sc) 877{ 878 struct ifnet *ifp = sc->sc_ifp; 879 struct rt2661_tx_ring *txq; 880 struct rt2661_tx_data *data; 881 uint32_t val; 882 int qid, retrycnt; 883 struct ieee80211vap *vap; 884 885 for (;;) { 886 struct ieee80211_node *ni; 887 struct mbuf *m; 888 889 val = RAL_READ(sc, RT2661_STA_CSR4); 890 if (!(val & RT2661_TX_STAT_VALID)) 891 break; 892 893 /* retrieve the queue in which this frame was sent */ 894 qid = RT2661_TX_QID(val); 895 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 896 897 /* retrieve rate control algorithm context */ 898 data = &txq->data[txq->stat]; 899 m = data->m; 900 data->m = NULL; 901 ni = data->ni; 902 data->ni = NULL; 903 904 /* if no frame has been sent, ignore */ 905 if (ni == NULL) 906 continue; 907 else 908 vap = ni->ni_vap; 909 910 switch (RT2661_TX_RESULT(val)) { 911 case RT2661_TX_SUCCESS: 912 retrycnt = RT2661_TX_RETRYCNT(val); 913 914 DPRINTFN(sc, 10, "data frame sent successfully after " 915 "%d retries\n", retrycnt); 916 if (data->rix != IEEE80211_FIXED_RATE_NONE) 917 ieee80211_ratectl_tx_complete(vap, ni, 918 IEEE80211_RATECTL_TX_SUCCESS, 919 &retrycnt, NULL); 920 ifp->if_opackets++; 921 break; 922 923 case RT2661_TX_RETRY_FAIL: 924 retrycnt = RT2661_TX_RETRYCNT(val); 925 926 DPRINTFN(sc, 9, "%s\n", 927 "sending data frame failed (too much retries)"); 928 if (data->rix != IEEE80211_FIXED_RATE_NONE) 929 ieee80211_ratectl_tx_complete(vap, ni, 930 IEEE80211_RATECTL_TX_FAILURE, 931 &retrycnt, NULL); 932 ifp->if_oerrors++; 933 break; 934 935 default: 936 /* other failure */ 937 device_printf(sc->sc_dev, 938 "sending data frame failed 0x%08x\n", val); 939 ifp->if_oerrors++; 940 } 941 942 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 943 944 txq->queued--; 945 if (++txq->stat >= txq->count) /* faster than % count */ 946 txq->stat = 0; 947 948 if (m->m_flags & M_TXCB) 949 ieee80211_process_callback(ni, m, 950 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS); 951 m_freem(m); 952 ieee80211_free_node(ni); 953 } 954 955 sc->sc_tx_timer = 0; 956 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 957 958 rt2661_start_locked(ifp); 959} 960 961static void 962rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 963{ 964 struct rt2661_tx_desc *desc; 965 struct rt2661_tx_data *data; 966 967 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 968 969 for (;;) { 970 desc = &txq->desc[txq->next]; 971 data = &txq->data[txq->next]; 972 973 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 974 !(le32toh(desc->flags) & RT2661_TX_VALID)) 975 break; 976 977 bus_dmamap_sync(txq->data_dmat, data->map, 978 BUS_DMASYNC_POSTWRITE); 979 bus_dmamap_unload(txq->data_dmat, data->map); 980 981 /* descriptor is no longer valid */ 982 desc->flags &= ~htole32(RT2661_TX_VALID); 983 984 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 985 986 if (++txq->next >= txq->count) /* faster than % count */ 987 txq->next = 0; 988 } 989 990 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 991} 992 993static void 994rt2661_rx_intr(struct rt2661_softc *sc) 995{ 996 struct ifnet *ifp = sc->sc_ifp; 997 struct ieee80211com *ic = ifp->if_l2com; 998 struct rt2661_rx_desc *desc; 999 struct rt2661_rx_data *data; 1000 bus_addr_t physaddr; 1001 struct ieee80211_frame *wh; 1002 struct ieee80211_node *ni; 1003 struct mbuf *mnew, *m; 1004 int error; 1005 1006 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1007 BUS_DMASYNC_POSTREAD); 1008 1009 for (;;) { 1010 int8_t rssi, nf; 1011 1012 desc = &sc->rxq.desc[sc->rxq.cur]; 1013 data = &sc->rxq.data[sc->rxq.cur]; 1014 1015 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1016 break; 1017 1018 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1019 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1020 /* 1021 * This should not happen since we did not request 1022 * to receive those frames when we filled TXRX_CSR0. 1023 */ 1024 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 1025 le32toh(desc->flags)); 1026 ifp->if_ierrors++; 1027 goto skip; 1028 } 1029 1030 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1031 ifp->if_ierrors++; 1032 goto skip; 1033 } 1034 1035 /* 1036 * Try to allocate a new mbuf for this ring element and load it 1037 * before processing the current mbuf. If the ring element 1038 * cannot be loaded, drop the received packet and reuse the old 1039 * mbuf. In the unlikely case that the old mbuf can't be 1040 * reloaded either, explicitly panic. 1041 */ 1042 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1043 if (mnew == NULL) { 1044 ifp->if_ierrors++; 1045 goto skip; 1046 } 1047 1048 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1049 BUS_DMASYNC_POSTREAD); 1050 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1051 1052 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1053 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1054 &physaddr, 0); 1055 if (error != 0) { 1056 m_freem(mnew); 1057 1058 /* try to reload the old mbuf */ 1059 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1060 mtod(data->m, void *), MCLBYTES, 1061 rt2661_dma_map_addr, &physaddr, 0); 1062 if (error != 0) { 1063 /* very unlikely that it will fail... */ 1064 panic("%s: could not load old rx mbuf", 1065 device_get_name(sc->sc_dev)); 1066 } 1067 ifp->if_ierrors++; 1068 goto skip; 1069 } 1070 1071 /* 1072 * New mbuf successfully loaded, update Rx ring and continue 1073 * processing. 1074 */ 1075 m = data->m; 1076 data->m = mnew; 1077 desc->physaddr = htole32(physaddr); 1078 1079 /* finalize mbuf */ 1080 m->m_pkthdr.rcvif = ifp; 1081 m->m_pkthdr.len = m->m_len = 1082 (le32toh(desc->flags) >> 16) & 0xfff; 1083 1084 rssi = rt2661_get_rssi(sc, desc->rssi); 1085 /* Error happened during RSSI conversion. */ 1086 if (rssi < 0) 1087 rssi = -30; /* XXX ignored by net80211 */ 1088 nf = RT2661_NOISE_FLOOR; 1089 1090 if (ieee80211_radiotap_active(ic)) { 1091 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1092 uint32_t tsf_lo, tsf_hi; 1093 1094 /* get timestamp (low and high 32 bits) */ 1095 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1096 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1097 1098 tap->wr_tsf = 1099 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1100 tap->wr_flags = 0; 1101 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1102 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1103 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1104 tap->wr_antsignal = nf + rssi; 1105 tap->wr_antnoise = nf; 1106 } 1107 sc->sc_flags |= RAL_INPUT_RUNNING; 1108 RAL_UNLOCK(sc); 1109 wh = mtod(m, struct ieee80211_frame *); 1110 1111 /* send the frame to the 802.11 layer */ 1112 ni = ieee80211_find_rxnode(ic, 1113 (struct ieee80211_frame_min *)wh); 1114 if (ni != NULL) { 1115 (void) ieee80211_input(ni, m, rssi, nf); 1116 ieee80211_free_node(ni); 1117 } else 1118 (void) ieee80211_input_all(ic, m, rssi, nf); 1119 1120 RAL_LOCK(sc); 1121 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1122 1123skip: desc->flags |= htole32(RT2661_RX_BUSY); 1124 1125 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1126 1127 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1128 } 1129 1130 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1131 BUS_DMASYNC_PREWRITE); 1132} 1133 1134/* ARGSUSED */ 1135static void 1136rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1137{ 1138 /* do nothing */ 1139} 1140 1141static void 1142rt2661_mcu_wakeup(struct rt2661_softc *sc) 1143{ 1144 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1145 1146 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1147 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1148 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1149 1150 /* send wakeup command to MCU */ 1151 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1152} 1153 1154static void 1155rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1156{ 1157 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1158 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1159} 1160 1161void 1162rt2661_intr(void *arg) 1163{ 1164 struct rt2661_softc *sc = arg; 1165 struct ifnet *ifp = sc->sc_ifp; 1166 uint32_t r1, r2; 1167 1168 RAL_LOCK(sc); 1169 1170 /* disable MAC and MCU interrupts */ 1171 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1172 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1173 1174 /* don't re-enable interrupts if we're shutting down */ 1175 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1176 RAL_UNLOCK(sc); 1177 return; 1178 } 1179 1180 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1181 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1182 1183 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1184 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1185 1186 if (r1 & RT2661_MGT_DONE) 1187 rt2661_tx_dma_intr(sc, &sc->mgtq); 1188 1189 if (r1 & RT2661_RX_DONE) 1190 rt2661_rx_intr(sc); 1191 1192 if (r1 & RT2661_TX0_DMA_DONE) 1193 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1194 1195 if (r1 & RT2661_TX1_DMA_DONE) 1196 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1197 1198 if (r1 & RT2661_TX2_DMA_DONE) 1199 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1200 1201 if (r1 & RT2661_TX3_DMA_DONE) 1202 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1203 1204 if (r1 & RT2661_TX_DONE) 1205 rt2661_tx_intr(sc); 1206 1207 if (r2 & RT2661_MCU_CMD_DONE) 1208 rt2661_mcu_cmd_intr(sc); 1209 1210 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1211 rt2661_mcu_beacon_expire(sc); 1212 1213 if (r2 & RT2661_MCU_WAKEUP) 1214 rt2661_mcu_wakeup(sc); 1215 1216 /* re-enable MAC and MCU interrupts */ 1217 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1218 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1219 1220 RAL_UNLOCK(sc); 1221} 1222 1223static uint8_t 1224rt2661_plcp_signal(int rate) 1225{ 1226 switch (rate) { 1227 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1228 case 12: return 0xb; 1229 case 18: return 0xf; 1230 case 24: return 0xa; 1231 case 36: return 0xe; 1232 case 48: return 0x9; 1233 case 72: return 0xd; 1234 case 96: return 0x8; 1235 case 108: return 0xc; 1236 1237 /* CCK rates (NB: not IEEE std, device-specific) */ 1238 case 2: return 0x0; 1239 case 4: return 0x1; 1240 case 11: return 0x2; 1241 case 22: return 0x3; 1242 } 1243 return 0xff; /* XXX unsupported/unknown rate */ 1244} 1245 1246static void 1247rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1248 uint32_t flags, uint16_t xflags, int len, int rate, 1249 const bus_dma_segment_t *segs, int nsegs, int ac) 1250{ 1251 struct ifnet *ifp = sc->sc_ifp; 1252 struct ieee80211com *ic = ifp->if_l2com; 1253 uint16_t plcp_length; 1254 int i, remainder; 1255 1256 desc->flags = htole32(flags); 1257 desc->flags |= htole32(len << 16); 1258 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1259 1260 desc->xflags = htole16(xflags); 1261 desc->xflags |= htole16(nsegs << 13); 1262 1263 desc->wme = htole16( 1264 RT2661_QID(ac) | 1265 RT2661_AIFSN(2) | 1266 RT2661_LOGCWMIN(4) | 1267 RT2661_LOGCWMAX(10)); 1268 1269 /* 1270 * Remember in which queue this frame was sent. This field is driver 1271 * private data only. It will be made available by the NIC in STA_CSR4 1272 * on Tx interrupts. 1273 */ 1274 desc->qid = ac; 1275 1276 /* setup PLCP fields */ 1277 desc->plcp_signal = rt2661_plcp_signal(rate); 1278 desc->plcp_service = 4; 1279 1280 len += IEEE80211_CRC_LEN; 1281 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1282 desc->flags |= htole32(RT2661_TX_OFDM); 1283 1284 plcp_length = len & 0xfff; 1285 desc->plcp_length_hi = plcp_length >> 6; 1286 desc->plcp_length_lo = plcp_length & 0x3f; 1287 } else { 1288 plcp_length = (16 * len + rate - 1) / rate; 1289 if (rate == 22) { 1290 remainder = (16 * len) % 22; 1291 if (remainder != 0 && remainder < 7) 1292 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1293 } 1294 desc->plcp_length_hi = plcp_length >> 8; 1295 desc->plcp_length_lo = plcp_length & 0xff; 1296 1297 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1298 desc->plcp_signal |= 0x08; 1299 } 1300 1301 /* RT2x61 supports scatter with up to 5 segments */ 1302 for (i = 0; i < nsegs; i++) { 1303 desc->addr[i] = htole32(segs[i].ds_addr); 1304 desc->len [i] = htole16(segs[i].ds_len); 1305 } 1306} 1307 1308static int 1309rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1310 struct ieee80211_node *ni) 1311{ 1312 struct ieee80211vap *vap = ni->ni_vap; 1313 struct ieee80211com *ic = ni->ni_ic; 1314 struct rt2661_tx_desc *desc; 1315 struct rt2661_tx_data *data; 1316 struct ieee80211_frame *wh; 1317 struct ieee80211_key *k; 1318 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1319 uint16_t dur; 1320 uint32_t flags = 0; /* XXX HWSEQ */ 1321 int nsegs, rate, error; 1322 1323 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1324 data = &sc->mgtq.data[sc->mgtq.cur]; 1325 1326 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1327 1328 wh = mtod(m0, struct ieee80211_frame *); 1329 1330 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1331 k = ieee80211_crypto_encap(ni, m0); 1332 if (k == NULL) { 1333 m_freem(m0); 1334 return ENOBUFS; 1335 } 1336 } 1337 1338 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1339 segs, &nsegs, 0); 1340 if (error != 0) { 1341 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1342 error); 1343 m_freem(m0); 1344 return error; 1345 } 1346 1347 if (ieee80211_radiotap_active_vap(vap)) { 1348 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1349 1350 tap->wt_flags = 0; 1351 tap->wt_rate = rate; 1352 1353 ieee80211_radiotap_tx(vap, m0); 1354 } 1355 1356 data->m = m0; 1357 data->ni = ni; 1358 /* management frames are not taken into account for amrr */ 1359 data->rix = IEEE80211_FIXED_RATE_NONE; 1360 1361 wh = mtod(m0, struct ieee80211_frame *); 1362 1363 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1364 flags |= RT2661_TX_NEED_ACK; 1365 1366 dur = ieee80211_ack_duration(ic->ic_rt, 1367 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1368 *(uint16_t *)wh->i_dur = htole16(dur); 1369 1370 /* tell hardware to add timestamp in probe responses */ 1371 if ((wh->i_fc[0] & 1372 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1373 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1374 flags |= RT2661_TX_TIMESTAMP; 1375 } 1376 1377 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1378 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1379 1380 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1381 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1382 BUS_DMASYNC_PREWRITE); 1383 1384 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1385 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1386 1387 /* kick mgt */ 1388 sc->mgtq.queued++; 1389 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1390 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1391 1392 return 0; 1393} 1394 1395static int 1396rt2661_sendprot(struct rt2661_softc *sc, int ac, 1397 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1398{ 1399 struct ieee80211com *ic = ni->ni_ic; 1400 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1401 const struct ieee80211_frame *wh; 1402 struct rt2661_tx_desc *desc; 1403 struct rt2661_tx_data *data; 1404 struct mbuf *mprot; 1405 int protrate, ackrate, pktlen, flags, isshort, error; 1406 uint16_t dur; 1407 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1408 int nsegs; 1409 1410 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1411 ("protection %d", prot)); 1412 1413 wh = mtod(m, const struct ieee80211_frame *); 1414 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1415 1416 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1417 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1418 1419 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1420 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1421 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1422 flags = RT2661_TX_MORE_FRAG; 1423 if (prot == IEEE80211_PROT_RTSCTS) { 1424 /* NB: CTS is the same size as an ACK */ 1425 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1426 flags |= RT2661_TX_NEED_ACK; 1427 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1428 } else { 1429 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1430 } 1431 if (mprot == NULL) { 1432 /* XXX stat + msg */ 1433 return ENOBUFS; 1434 } 1435 1436 data = &txq->data[txq->cur]; 1437 desc = &txq->desc[txq->cur]; 1438 1439 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, 1440 &nsegs, 0); 1441 if (error != 0) { 1442 device_printf(sc->sc_dev, 1443 "could not map mbuf (error %d)\n", error); 1444 m_freem(mprot); 1445 return error; 1446 } 1447 1448 data->m = mprot; 1449 data->ni = ieee80211_ref_node(ni); 1450 /* ctl frames are not taken into account for amrr */ 1451 data->rix = IEEE80211_FIXED_RATE_NONE; 1452 1453 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1454 protrate, segs, 1, ac); 1455 1456 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1457 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1458 1459 txq->queued++; 1460 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1461 1462 return 0; 1463} 1464 1465static int 1466rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1467 struct ieee80211_node *ni, int ac) 1468{ 1469 struct ieee80211vap *vap = ni->ni_vap; 1470 struct ifnet *ifp = sc->sc_ifp; 1471 struct ieee80211com *ic = ifp->if_l2com; 1472 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1473 struct rt2661_tx_desc *desc; 1474 struct rt2661_tx_data *data; 1475 struct ieee80211_frame *wh; 1476 const struct ieee80211_txparam *tp; 1477 struct ieee80211_key *k; 1478 const struct chanAccParams *cap; 1479 struct mbuf *mnew; 1480 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1481 uint16_t dur; 1482 uint32_t flags; 1483 int error, nsegs, rate, noack = 0; 1484 1485 wh = mtod(m0, struct ieee80211_frame *); 1486 1487 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1488 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1489 rate = tp->mcastrate; 1490 } else if (m0->m_flags & M_EAPOL) { 1491 rate = tp->mgmtrate; 1492 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1493 rate = tp->ucastrate; 1494 } else { 1495 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1496 rate = ni->ni_txrate; 1497 } 1498 rate &= IEEE80211_RATE_VAL; 1499 1500 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1501 cap = &ic->ic_wme.wme_chanParams; 1502 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1503 } 1504 1505 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1506 k = ieee80211_crypto_encap(ni, m0); 1507 if (k == NULL) { 1508 m_freem(m0); 1509 return ENOBUFS; 1510 } 1511 1512 /* packet header may have moved, reset our local pointer */ 1513 wh = mtod(m0, struct ieee80211_frame *); 1514 } 1515 1516 flags = 0; 1517 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1518 int prot = IEEE80211_PROT_NONE; 1519 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1520 prot = IEEE80211_PROT_RTSCTS; 1521 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1522 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1523 prot = ic->ic_protmode; 1524 if (prot != IEEE80211_PROT_NONE) { 1525 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1526 if (error) { 1527 m_freem(m0); 1528 return error; 1529 } 1530 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1531 } 1532 } 1533 1534 data = &txq->data[txq->cur]; 1535 desc = &txq->desc[txq->cur]; 1536 1537 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1538 &nsegs, 0); 1539 if (error != 0 && error != EFBIG) { 1540 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1541 error); 1542 m_freem(m0); 1543 return error; 1544 } 1545 if (error != 0) { 1546 mnew = m_defrag(m0, M_DONTWAIT); 1547 if (mnew == NULL) { 1548 device_printf(sc->sc_dev, 1549 "could not defragment mbuf\n"); 1550 m_freem(m0); 1551 return ENOBUFS; 1552 } 1553 m0 = mnew; 1554 1555 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1556 segs, &nsegs, 0); 1557 if (error != 0) { 1558 device_printf(sc->sc_dev, 1559 "could not map mbuf (error %d)\n", error); 1560 m_freem(m0); 1561 return error; 1562 } 1563 1564 /* packet header have moved, reset our local pointer */ 1565 wh = mtod(m0, struct ieee80211_frame *); 1566 } 1567 1568 if (ieee80211_radiotap_active_vap(vap)) { 1569 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1570 1571 tap->wt_flags = 0; 1572 tap->wt_rate = rate; 1573 1574 ieee80211_radiotap_tx(vap, m0); 1575 } 1576 1577 data->m = m0; 1578 data->ni = ni; 1579 1580 /* remember link conditions for rate adaptation algorithm */ 1581 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1582 data->rix = ni->ni_txrate; 1583 /* XXX probably need last rssi value and not avg */ 1584 data->rssi = ic->ic_node_getrssi(ni); 1585 } else 1586 data->rix = IEEE80211_FIXED_RATE_NONE; 1587 1588 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1589 flags |= RT2661_TX_NEED_ACK; 1590 1591 dur = ieee80211_ack_duration(ic->ic_rt, 1592 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1593 *(uint16_t *)wh->i_dur = htole16(dur); 1594 } 1595 1596 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1597 nsegs, ac); 1598 1599 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1600 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1601 1602 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1603 m0->m_pkthdr.len, txq->cur, rate); 1604 1605 /* kick Tx */ 1606 txq->queued++; 1607 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1608 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1609 1610 return 0; 1611} 1612 1613static void 1614rt2661_start_locked(struct ifnet *ifp) 1615{ 1616 struct rt2661_softc *sc = ifp->if_softc; 1617 struct mbuf *m; 1618 struct ieee80211_node *ni; 1619 int ac; 1620 1621 RAL_LOCK_ASSERT(sc); 1622 1623 /* prevent management frames from being sent if we're not ready */ 1624 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || sc->sc_invalid) 1625 return; 1626 1627 for (;;) { 1628 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1629 if (m == NULL) 1630 break; 1631 1632 ac = M_WME_GETAC(m); 1633 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1634 /* there is no place left in this ring */ 1635 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1636 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1637 break; 1638 } 1639 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1640 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1641 ieee80211_free_node(ni); 1642 ifp->if_oerrors++; 1643 break; 1644 } 1645 1646 sc->sc_tx_timer = 5; 1647 } 1648} 1649 1650static void 1651rt2661_start(struct ifnet *ifp) 1652{ 1653 struct rt2661_softc *sc = ifp->if_softc; 1654 1655 RAL_LOCK(sc); 1656 rt2661_start_locked(ifp); 1657 RAL_UNLOCK(sc); 1658} 1659 1660static int 1661rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1662 const struct ieee80211_bpf_params *params) 1663{ 1664 struct ieee80211com *ic = ni->ni_ic; 1665 struct ifnet *ifp = ic->ic_ifp; 1666 struct rt2661_softc *sc = ifp->if_softc; 1667 1668 RAL_LOCK(sc); 1669 1670 /* prevent management frames from being sent if we're not ready */ 1671 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1672 RAL_UNLOCK(sc); 1673 m_freem(m); 1674 ieee80211_free_node(ni); 1675 return ENETDOWN; 1676 } 1677 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1678 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1679 RAL_UNLOCK(sc); 1680 m_freem(m); 1681 ieee80211_free_node(ni); 1682 return ENOBUFS; /* XXX */ 1683 } 1684 1685 ifp->if_opackets++; 1686 1687 /* 1688 * Legacy path; interpret frame contents to decide 1689 * precisely how to send the frame. 1690 * XXX raw path 1691 */ 1692 if (rt2661_tx_mgt(sc, m, ni) != 0) 1693 goto bad; 1694 sc->sc_tx_timer = 5; 1695 1696 RAL_UNLOCK(sc); 1697 1698 return 0; 1699bad: 1700 ifp->if_oerrors++; 1701 ieee80211_free_node(ni); 1702 RAL_UNLOCK(sc); 1703 return EIO; /* XXX */ 1704} 1705 1706static void 1707rt2661_watchdog(void *arg) 1708{ 1709 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1710 struct ifnet *ifp = sc->sc_ifp; 1711 1712 RAL_LOCK_ASSERT(sc); 1713 1714 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 1715 1716 if (sc->sc_invalid) /* card ejected */ 1717 return; 1718 1719 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1720 if_printf(ifp, "device timeout\n"); 1721 rt2661_init_locked(sc); 1722 ifp->if_oerrors++; 1723 /* NB: callout is reset in rt2661_init() */ 1724 return; 1725 } 1726 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1727} 1728 1729static int 1730rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1731{ 1732 struct rt2661_softc *sc = ifp->if_softc; 1733 struct ieee80211com *ic = ifp->if_l2com; 1734 struct ifreq *ifr = (struct ifreq *) data; 1735 int error = 0, startall = 0; 1736 1737 switch (cmd) { 1738 case SIOCSIFFLAGS: 1739 RAL_LOCK(sc); 1740 if (ifp->if_flags & IFF_UP) { 1741 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1742 rt2661_init_locked(sc); 1743 startall = 1; 1744 } else 1745 rt2661_update_promisc(ifp); 1746 } else { 1747 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1748 rt2661_stop_locked(sc); 1749 } 1750 RAL_UNLOCK(sc); 1751 if (startall) 1752 ieee80211_start_all(ic); 1753 break; 1754 case SIOCGIFMEDIA: 1755 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1756 break; 1757 case SIOCGIFADDR: 1758 error = ether_ioctl(ifp, cmd, data); 1759 break; 1760 default: 1761 error = EINVAL; 1762 break; 1763 } 1764 return error; 1765} 1766 1767static void 1768rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1769{ 1770 uint32_t tmp; 1771 int ntries; 1772 1773 for (ntries = 0; ntries < 100; ntries++) { 1774 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1775 break; 1776 DELAY(1); 1777 } 1778 if (ntries == 100) { 1779 device_printf(sc->sc_dev, "could not write to BBP\n"); 1780 return; 1781 } 1782 1783 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1784 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1785 1786 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1787} 1788 1789static uint8_t 1790rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1791{ 1792 uint32_t val; 1793 int ntries; 1794 1795 for (ntries = 0; ntries < 100; ntries++) { 1796 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1797 break; 1798 DELAY(1); 1799 } 1800 if (ntries == 100) { 1801 device_printf(sc->sc_dev, "could not read from BBP\n"); 1802 return 0; 1803 } 1804 1805 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1806 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1807 1808 for (ntries = 0; ntries < 100; ntries++) { 1809 val = RAL_READ(sc, RT2661_PHY_CSR3); 1810 if (!(val & RT2661_BBP_BUSY)) 1811 return val & 0xff; 1812 DELAY(1); 1813 } 1814 1815 device_printf(sc->sc_dev, "could not read from BBP\n"); 1816 return 0; 1817} 1818 1819static void 1820rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1821{ 1822 uint32_t tmp; 1823 int ntries; 1824 1825 for (ntries = 0; ntries < 100; ntries++) { 1826 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1827 break; 1828 DELAY(1); 1829 } 1830 if (ntries == 100) { 1831 device_printf(sc->sc_dev, "could not write to RF\n"); 1832 return; 1833 } 1834 1835 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1836 (reg & 3); 1837 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1838 1839 /* remember last written value in sc */ 1840 sc->rf_regs[reg] = val; 1841 1842 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1843} 1844 1845static int 1846rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1847{ 1848 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1849 return EIO; /* there is already a command pending */ 1850 1851 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1852 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1853 1854 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1855 1856 return 0; 1857} 1858 1859static void 1860rt2661_select_antenna(struct rt2661_softc *sc) 1861{ 1862 uint8_t bbp4, bbp77; 1863 uint32_t tmp; 1864 1865 bbp4 = rt2661_bbp_read(sc, 4); 1866 bbp77 = rt2661_bbp_read(sc, 77); 1867 1868 /* TBD */ 1869 1870 /* make sure Rx is disabled before switching antenna */ 1871 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1872 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1873 1874 rt2661_bbp_write(sc, 4, bbp4); 1875 rt2661_bbp_write(sc, 77, bbp77); 1876 1877 /* restore Rx filter */ 1878 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1879} 1880 1881/* 1882 * Enable multi-rate retries for frames sent at OFDM rates. 1883 * In 802.11b/g mode, allow fallback to CCK rates. 1884 */ 1885static void 1886rt2661_enable_mrr(struct rt2661_softc *sc) 1887{ 1888 struct ifnet *ifp = sc->sc_ifp; 1889 struct ieee80211com *ic = ifp->if_l2com; 1890 uint32_t tmp; 1891 1892 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1893 1894 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1895 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1896 tmp |= RT2661_MRR_CCK_FALLBACK; 1897 tmp |= RT2661_MRR_ENABLED; 1898 1899 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1900} 1901 1902static void 1903rt2661_set_txpreamble(struct rt2661_softc *sc) 1904{ 1905 struct ifnet *ifp = sc->sc_ifp; 1906 struct ieee80211com *ic = ifp->if_l2com; 1907 uint32_t tmp; 1908 1909 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1910 1911 tmp &= ~RT2661_SHORT_PREAMBLE; 1912 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1913 tmp |= RT2661_SHORT_PREAMBLE; 1914 1915 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1916} 1917 1918static void 1919rt2661_set_basicrates(struct rt2661_softc *sc, 1920 const struct ieee80211_rateset *rs) 1921{ 1922#define RV(r) ((r) & IEEE80211_RATE_VAL) 1923 struct ifnet *ifp = sc->sc_ifp; 1924 struct ieee80211com *ic = ifp->if_l2com; 1925 uint32_t mask = 0; 1926 uint8_t rate; 1927 int i, j; 1928 1929 for (i = 0; i < rs->rs_nrates; i++) { 1930 rate = rs->rs_rates[i]; 1931 1932 if (!(rate & IEEE80211_RATE_BASIC)) 1933 continue; 1934 1935 /* 1936 * Find h/w rate index. We know it exists because the rate 1937 * set has already been negotiated. 1938 */ 1939 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); 1940 1941 mask |= 1 << j; 1942 } 1943 1944 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1945 1946 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1947#undef RV 1948} 1949 1950/* 1951 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1952 * driver. 1953 */ 1954static void 1955rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1956{ 1957 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1958 uint32_t tmp; 1959 1960 /* update all BBP registers that depend on the band */ 1961 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1962 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1963 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1964 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1965 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1966 } 1967 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1968 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1969 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1970 } 1971 1972 rt2661_bbp_write(sc, 17, bbp17); 1973 rt2661_bbp_write(sc, 96, bbp96); 1974 rt2661_bbp_write(sc, 104, bbp104); 1975 1976 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1977 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1978 rt2661_bbp_write(sc, 75, 0x80); 1979 rt2661_bbp_write(sc, 86, 0x80); 1980 rt2661_bbp_write(sc, 88, 0x80); 1981 } 1982 1983 rt2661_bbp_write(sc, 35, bbp35); 1984 rt2661_bbp_write(sc, 97, bbp97); 1985 rt2661_bbp_write(sc, 98, bbp98); 1986 1987 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 1988 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 1989 if (IEEE80211_IS_CHAN_2GHZ(c)) 1990 tmp |= RT2661_PA_PE_2GHZ; 1991 else 1992 tmp |= RT2661_PA_PE_5GHZ; 1993 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 1994} 1995 1996static void 1997rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 1998{ 1999 struct ifnet *ifp = sc->sc_ifp; 2000 struct ieee80211com *ic = ifp->if_l2com; 2001 const struct rfprog *rfprog; 2002 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2003 int8_t power; 2004 u_int i, chan; 2005 2006 chan = ieee80211_chan2ieee(ic, c); 2007 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 2008 2009 /* select the appropriate RF settings based on what EEPROM says */ 2010 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2011 2012 /* find the settings for this channel (we know it exists) */ 2013 for (i = 0; rfprog[i].chan != chan; i++); 2014 2015 power = sc->txpow[i]; 2016 if (power < 0) { 2017 bbp94 += power; 2018 power = 0; 2019 } else if (power > 31) { 2020 bbp94 += power - 31; 2021 power = 31; 2022 } 2023 2024 /* 2025 * If we are switching from the 2GHz band to the 5GHz band or 2026 * vice-versa, BBP registers need to be reprogrammed. 2027 */ 2028 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2029 rt2661_select_band(sc, c); 2030 rt2661_select_antenna(sc); 2031 } 2032 sc->sc_curchan = c; 2033 2034 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2035 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2036 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2037 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2038 2039 DELAY(200); 2040 2041 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2042 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2043 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2044 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2045 2046 DELAY(200); 2047 2048 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2049 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2050 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2051 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2052 2053 /* enable smart mode for MIMO-capable RFs */ 2054 bbp3 = rt2661_bbp_read(sc, 3); 2055 2056 bbp3 &= ~RT2661_SMART_MODE; 2057 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2058 bbp3 |= RT2661_SMART_MODE; 2059 2060 rt2661_bbp_write(sc, 3, bbp3); 2061 2062 if (bbp94 != RT2661_BBPR94_DEFAULT) 2063 rt2661_bbp_write(sc, 94, bbp94); 2064 2065 /* 5GHz radio needs a 1ms delay here */ 2066 if (IEEE80211_IS_CHAN_5GHZ(c)) 2067 DELAY(1000); 2068} 2069 2070static void 2071rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2072{ 2073 uint32_t tmp; 2074 2075 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2076 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2077 2078 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2079 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2080} 2081 2082static void 2083rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2084{ 2085 uint32_t tmp; 2086 2087 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2088 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2089 2090 tmp = addr[4] | addr[5] << 8; 2091 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2092} 2093 2094static void 2095rt2661_update_promisc(struct ifnet *ifp) 2096{ 2097 struct rt2661_softc *sc = ifp->if_softc; 2098 uint32_t tmp; 2099 2100 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2101 2102 tmp &= ~RT2661_DROP_NOT_TO_ME; 2103 if (!(ifp->if_flags & IFF_PROMISC)) 2104 tmp |= RT2661_DROP_NOT_TO_ME; 2105 2106 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2107 2108 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2109 "entering" : "leaving"); 2110} 2111 2112/* 2113 * Update QoS (802.11e) settings for each h/w Tx ring. 2114 */ 2115static int 2116rt2661_wme_update(struct ieee80211com *ic) 2117{ 2118 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2119 const struct wmeParams *wmep; 2120 2121 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2122 2123 /* XXX: not sure about shifts. */ 2124 /* XXX: the reference driver plays with AC_VI settings too. */ 2125 2126 /* update TxOp */ 2127 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2128 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2129 wmep[WME_AC_BK].wmep_txopLimit); 2130 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2131 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2132 wmep[WME_AC_VO].wmep_txopLimit); 2133 2134 /* update CWmin */ 2135 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2136 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2137 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2138 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2139 wmep[WME_AC_VO].wmep_logcwmin); 2140 2141 /* update CWmax */ 2142 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2143 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2144 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2145 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2146 wmep[WME_AC_VO].wmep_logcwmax); 2147 2148 /* update Aifsn */ 2149 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2150 wmep[WME_AC_BE].wmep_aifsn << 12 | 2151 wmep[WME_AC_BK].wmep_aifsn << 8 | 2152 wmep[WME_AC_VI].wmep_aifsn << 4 | 2153 wmep[WME_AC_VO].wmep_aifsn); 2154 2155 return 0; 2156} 2157 2158static void 2159rt2661_update_slot(struct ifnet *ifp) 2160{ 2161 struct rt2661_softc *sc = ifp->if_softc; 2162 struct ieee80211com *ic = ifp->if_l2com; 2163 uint8_t slottime; 2164 uint32_t tmp; 2165 2166 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2167 2168 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2169 tmp = (tmp & ~0xff) | slottime; 2170 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2171} 2172 2173static const char * 2174rt2661_get_rf(int rev) 2175{ 2176 switch (rev) { 2177 case RT2661_RF_5225: return "RT5225"; 2178 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2179 case RT2661_RF_2527: return "RT2527"; 2180 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2181 default: return "unknown"; 2182 } 2183} 2184 2185static void 2186rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2187{ 2188 uint16_t val; 2189 int i; 2190 2191 /* read MAC address */ 2192 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2193 macaddr[0] = val & 0xff; 2194 macaddr[1] = val >> 8; 2195 2196 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2197 macaddr[2] = val & 0xff; 2198 macaddr[3] = val >> 8; 2199 2200 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2201 macaddr[4] = val & 0xff; 2202 macaddr[5] = val >> 8; 2203 2204 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2205 /* XXX: test if different from 0xffff? */ 2206 sc->rf_rev = (val >> 11) & 0x1f; 2207 sc->hw_radio = (val >> 10) & 0x1; 2208 sc->rx_ant = (val >> 4) & 0x3; 2209 sc->tx_ant = (val >> 2) & 0x3; 2210 sc->nb_ant = val & 0x3; 2211 2212 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2213 2214 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2215 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2216 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2217 2218 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2219 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2220 2221 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2222 if ((val & 0xff) != 0xff) 2223 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2224 2225 /* Only [-10, 10] is valid */ 2226 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2227 sc->rssi_2ghz_corr = 0; 2228 2229 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2230 if ((val & 0xff) != 0xff) 2231 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2232 2233 /* Only [-10, 10] is valid */ 2234 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2235 sc->rssi_5ghz_corr = 0; 2236 2237 /* adjust RSSI correction for external low-noise amplifier */ 2238 if (sc->ext_2ghz_lna) 2239 sc->rssi_2ghz_corr -= 14; 2240 if (sc->ext_5ghz_lna) 2241 sc->rssi_5ghz_corr -= 14; 2242 2243 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2244 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2245 2246 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2247 if ((val >> 8) != 0xff) 2248 sc->rfprog = (val >> 8) & 0x3; 2249 if ((val & 0xff) != 0xff) 2250 sc->rffreq = val & 0xff; 2251 2252 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2253 2254 /* read Tx power for all a/b/g channels */ 2255 for (i = 0; i < 19; i++) { 2256 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2257 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2258 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2259 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2260 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2261 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2262 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2263 } 2264 2265 /* read vendor-specific BBP values */ 2266 for (i = 0; i < 16; i++) { 2267 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2268 if (val == 0 || val == 0xffff) 2269 continue; /* skip invalid entries */ 2270 sc->bbp_prom[i].reg = val >> 8; 2271 sc->bbp_prom[i].val = val & 0xff; 2272 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2273 sc->bbp_prom[i].val); 2274 } 2275} 2276 2277static int 2278rt2661_bbp_init(struct rt2661_softc *sc) 2279{ 2280#define N(a) (sizeof (a) / sizeof ((a)[0])) 2281 int i, ntries; 2282 uint8_t val; 2283 2284 /* wait for BBP to be ready */ 2285 for (ntries = 0; ntries < 100; ntries++) { 2286 val = rt2661_bbp_read(sc, 0); 2287 if (val != 0 && val != 0xff) 2288 break; 2289 DELAY(100); 2290 } 2291 if (ntries == 100) { 2292 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2293 return EIO; 2294 } 2295 2296 /* initialize BBP registers to default values */ 2297 for (i = 0; i < N(rt2661_def_bbp); i++) { 2298 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2299 rt2661_def_bbp[i].val); 2300 } 2301 2302 /* write vendor-specific BBP values (from EEPROM) */ 2303 for (i = 0; i < 16; i++) { 2304 if (sc->bbp_prom[i].reg == 0) 2305 continue; 2306 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2307 } 2308 2309 return 0; 2310#undef N 2311} 2312 2313static void 2314rt2661_init_locked(struct rt2661_softc *sc) 2315{ 2316#define N(a) (sizeof (a) / sizeof ((a)[0])) 2317 struct ifnet *ifp = sc->sc_ifp; 2318 struct ieee80211com *ic = ifp->if_l2com; 2319 uint32_t tmp, sta[3]; 2320 int i, error, ntries; 2321 2322 RAL_LOCK_ASSERT(sc); 2323 2324 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2325 error = rt2661_load_microcode(sc); 2326 if (error != 0) { 2327 if_printf(ifp, 2328 "%s: could not load 8051 microcode, error %d\n", 2329 __func__, error); 2330 return; 2331 } 2332 sc->sc_flags |= RAL_FW_LOADED; 2333 } 2334 2335 rt2661_stop_locked(sc); 2336 2337 /* initialize Tx rings */ 2338 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2339 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2340 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2341 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2342 2343 /* initialize Mgt ring */ 2344 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2345 2346 /* initialize Rx ring */ 2347 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2348 2349 /* initialize Tx rings sizes */ 2350 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2351 RT2661_TX_RING_COUNT << 24 | 2352 RT2661_TX_RING_COUNT << 16 | 2353 RT2661_TX_RING_COUNT << 8 | 2354 RT2661_TX_RING_COUNT); 2355 2356 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2357 RT2661_TX_DESC_WSIZE << 16 | 2358 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2359 RT2661_MGT_RING_COUNT); 2360 2361 /* initialize Rx rings */ 2362 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2363 RT2661_RX_DESC_BACK << 16 | 2364 RT2661_RX_DESC_WSIZE << 8 | 2365 RT2661_RX_RING_COUNT); 2366 2367 /* XXX: some magic here */ 2368 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2369 2370 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2371 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2372 2373 /* load base address of Rx ring */ 2374 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2375 2376 /* initialize MAC registers to default values */ 2377 for (i = 0; i < N(rt2661_def_mac); i++) 2378 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2379 2380 rt2661_set_macaddr(sc, IF_LLADDR(ifp)); 2381 2382 /* set host ready */ 2383 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2384 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2385 2386 /* wait for BBP/RF to wakeup */ 2387 for (ntries = 0; ntries < 1000; ntries++) { 2388 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2389 break; 2390 DELAY(1000); 2391 } 2392 if (ntries == 1000) { 2393 printf("timeout waiting for BBP/RF to wakeup\n"); 2394 rt2661_stop_locked(sc); 2395 return; 2396 } 2397 2398 if (rt2661_bbp_init(sc) != 0) { 2399 rt2661_stop_locked(sc); 2400 return; 2401 } 2402 2403 /* select default channel */ 2404 sc->sc_curchan = ic->ic_curchan; 2405 rt2661_select_band(sc, sc->sc_curchan); 2406 rt2661_select_antenna(sc); 2407 rt2661_set_chan(sc, sc->sc_curchan); 2408 2409 /* update Rx filter */ 2410 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2411 2412 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2413 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2414 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2415 RT2661_DROP_ACKCTS; 2416 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2417 ic->ic_opmode != IEEE80211_M_MBSS) 2418 tmp |= RT2661_DROP_TODS; 2419 if (!(ifp->if_flags & IFF_PROMISC)) 2420 tmp |= RT2661_DROP_NOT_TO_ME; 2421 } 2422 2423 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2424 2425 /* clear STA registers */ 2426 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2427 2428 /* initialize ASIC */ 2429 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2430 2431 /* clear any pending interrupt */ 2432 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2433 2434 /* enable interrupts */ 2435 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2436 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2437 2438 /* kick Rx */ 2439 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2440 2441 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2442 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2443 2444 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2445#undef N 2446} 2447 2448static void 2449rt2661_init(void *priv) 2450{ 2451 struct rt2661_softc *sc = priv; 2452 struct ifnet *ifp = sc->sc_ifp; 2453 struct ieee80211com *ic = ifp->if_l2com; 2454 2455 RAL_LOCK(sc); 2456 rt2661_init_locked(sc); 2457 RAL_UNLOCK(sc); 2458 2459 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2460 ieee80211_start_all(ic); /* start all vap's */ 2461} 2462 2463void 2464rt2661_stop_locked(struct rt2661_softc *sc) 2465{ 2466 struct ifnet *ifp = sc->sc_ifp; 2467 uint32_t tmp; 2468 volatile int *flags = &sc->sc_flags; 2469 2470 while (*flags & RAL_INPUT_RUNNING) 2471 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2472 2473 callout_stop(&sc->watchdog_ch); 2474 sc->sc_tx_timer = 0; 2475 2476 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2477 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2478 2479 /* abort Tx (for all 5 Tx rings) */ 2480 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2481 2482 /* disable Rx (value remains after reset!) */ 2483 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2484 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2485 2486 /* reset ASIC */ 2487 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2488 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2489 2490 /* disable interrupts */ 2491 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2492 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2493 2494 /* clear any pending interrupt */ 2495 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2496 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2497 2498 /* reset Tx and Rx rings */ 2499 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2500 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2501 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2502 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2503 rt2661_reset_tx_ring(sc, &sc->mgtq); 2504 rt2661_reset_rx_ring(sc, &sc->rxq); 2505 } 2506} 2507 2508void 2509rt2661_stop(void *priv) 2510{ 2511 struct rt2661_softc *sc = priv; 2512 2513 RAL_LOCK(sc); 2514 rt2661_stop_locked(sc); 2515 RAL_UNLOCK(sc); 2516} 2517 2518static int 2519rt2661_load_microcode(struct rt2661_softc *sc) 2520{ 2521 struct ifnet *ifp = sc->sc_ifp; 2522 const struct firmware *fp; 2523 const char *imagename; 2524 int ntries, error; 2525 2526 RAL_LOCK_ASSERT(sc); 2527 2528 switch (sc->sc_id) { 2529 case 0x0301: imagename = "rt2561sfw"; break; 2530 case 0x0302: imagename = "rt2561fw"; break; 2531 case 0x0401: imagename = "rt2661fw"; break; 2532 default: 2533 if_printf(ifp, "%s: unexpected pci device id 0x%x, " 2534 "don't know how to retrieve firmware\n", 2535 __func__, sc->sc_id); 2536 return EINVAL; 2537 } 2538 RAL_UNLOCK(sc); 2539 fp = firmware_get(imagename); 2540 RAL_LOCK(sc); 2541 if (fp == NULL) { 2542 if_printf(ifp, "%s: unable to retrieve firmware image %s\n", 2543 __func__, imagename); 2544 return EINVAL; 2545 } 2546 2547 /* 2548 * Load 8051 microcode into NIC. 2549 */ 2550 /* reset 8051 */ 2551 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2552 2553 /* cancel any pending Host to MCU command */ 2554 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2555 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2556 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2557 2558 /* write 8051's microcode */ 2559 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2560 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2561 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2562 2563 /* kick 8051's ass */ 2564 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2565 2566 /* wait for 8051 to initialize */ 2567 for (ntries = 0; ntries < 500; ntries++) { 2568 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2569 break; 2570 DELAY(100); 2571 } 2572 if (ntries == 500) { 2573 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n", 2574 __func__); 2575 error = EIO; 2576 } else 2577 error = 0; 2578 2579 firmware_put(fp, FIRMWARE_UNLOAD); 2580 return error; 2581} 2582 2583#ifdef notyet 2584/* 2585 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2586 * false CCA count. This function is called periodically (every seconds) when 2587 * in the RUN state. Values taken from the reference driver. 2588 */ 2589static void 2590rt2661_rx_tune(struct rt2661_softc *sc) 2591{ 2592 uint8_t bbp17; 2593 uint16_t cca; 2594 int lo, hi, dbm; 2595 2596 /* 2597 * Tuning range depends on operating band and on the presence of an 2598 * external low-noise amplifier. 2599 */ 2600 lo = 0x20; 2601 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2602 lo += 0x08; 2603 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2604 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2605 lo += 0x10; 2606 hi = lo + 0x20; 2607 2608 /* retrieve false CCA count since last call (clear on read) */ 2609 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2610 2611 if (dbm >= -35) { 2612 bbp17 = 0x60; 2613 } else if (dbm >= -58) { 2614 bbp17 = hi; 2615 } else if (dbm >= -66) { 2616 bbp17 = lo + 0x10; 2617 } else if (dbm >= -74) { 2618 bbp17 = lo + 0x08; 2619 } else { 2620 /* RSSI < -74dBm, tune using false CCA count */ 2621 2622 bbp17 = sc->bbp17; /* current value */ 2623 2624 hi -= 2 * (-74 - dbm); 2625 if (hi < lo) 2626 hi = lo; 2627 2628 if (bbp17 > hi) { 2629 bbp17 = hi; 2630 2631 } else if (cca > 512) { 2632 if (++bbp17 > hi) 2633 bbp17 = hi; 2634 } else if (cca < 100) { 2635 if (--bbp17 < lo) 2636 bbp17 = lo; 2637 } 2638 } 2639 2640 if (bbp17 != sc->bbp17) { 2641 rt2661_bbp_write(sc, 17, bbp17); 2642 sc->bbp17 = bbp17; 2643 } 2644} 2645 2646/* 2647 * Enter/Leave radar detection mode. 2648 * This is for 802.11h additional regulatory domains. 2649 */ 2650static void 2651rt2661_radar_start(struct rt2661_softc *sc) 2652{ 2653 uint32_t tmp; 2654 2655 /* disable Rx */ 2656 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2657 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2658 2659 rt2661_bbp_write(sc, 82, 0x20); 2660 rt2661_bbp_write(sc, 83, 0x00); 2661 rt2661_bbp_write(sc, 84, 0x40); 2662 2663 /* save current BBP registers values */ 2664 sc->bbp18 = rt2661_bbp_read(sc, 18); 2665 sc->bbp21 = rt2661_bbp_read(sc, 21); 2666 sc->bbp22 = rt2661_bbp_read(sc, 22); 2667 sc->bbp16 = rt2661_bbp_read(sc, 16); 2668 sc->bbp17 = rt2661_bbp_read(sc, 17); 2669 sc->bbp64 = rt2661_bbp_read(sc, 64); 2670 2671 rt2661_bbp_write(sc, 18, 0xff); 2672 rt2661_bbp_write(sc, 21, 0x3f); 2673 rt2661_bbp_write(sc, 22, 0x3f); 2674 rt2661_bbp_write(sc, 16, 0xbd); 2675 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2676 rt2661_bbp_write(sc, 64, 0x21); 2677 2678 /* restore Rx filter */ 2679 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2680} 2681 2682static int 2683rt2661_radar_stop(struct rt2661_softc *sc) 2684{ 2685 uint8_t bbp66; 2686 2687 /* read radar detection result */ 2688 bbp66 = rt2661_bbp_read(sc, 66); 2689 2690 /* restore BBP registers values */ 2691 rt2661_bbp_write(sc, 16, sc->bbp16); 2692 rt2661_bbp_write(sc, 17, sc->bbp17); 2693 rt2661_bbp_write(sc, 18, sc->bbp18); 2694 rt2661_bbp_write(sc, 21, sc->bbp21); 2695 rt2661_bbp_write(sc, 22, sc->bbp22); 2696 rt2661_bbp_write(sc, 64, sc->bbp64); 2697 2698 return bbp66 == 1; 2699} 2700#endif 2701 2702static int 2703rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2704{ 2705 struct ieee80211com *ic = vap->iv_ic; 2706 struct ieee80211_beacon_offsets bo; 2707 struct rt2661_tx_desc desc; 2708 struct mbuf *m0; 2709 int rate; 2710 2711 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo); 2712 if (m0 == NULL) { 2713 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2714 return ENOBUFS; 2715 } 2716 2717 /* send beacons at the lowest available rate */ 2718 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2719 2720 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2721 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2722 2723 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2724 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2725 2726 /* copy beacon header and payload into NIC memory */ 2727 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2728 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2729 2730 m_freem(m0); 2731 2732 return 0; 2733} 2734 2735/* 2736 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2737 * and HostAP operating modes. 2738 */ 2739static void 2740rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2741{ 2742 struct ifnet *ifp = sc->sc_ifp; 2743 struct ieee80211com *ic = ifp->if_l2com; 2744 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2745 uint32_t tmp; 2746 2747 if (vap->iv_opmode != IEEE80211_M_STA) { 2748 /* 2749 * Change default 16ms TBTT adjustment to 8ms. 2750 * Must be done before enabling beacon generation. 2751 */ 2752 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2753 } 2754 2755 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2756 2757 /* set beacon interval (in 1/16ms unit) */ 2758 tmp |= vap->iv_bss->ni_intval * 16; 2759 2760 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2761 if (vap->iv_opmode == IEEE80211_M_STA) 2762 tmp |= RT2661_TSF_MODE(1); 2763 else 2764 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2765 2766 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2767} 2768 2769static void 2770rt2661_enable_tsf(struct rt2661_softc *sc) 2771{ 2772 RAL_WRITE(sc, RT2661_TXRX_CSR9, 2773 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000) 2774 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2)); 2775} 2776 2777/* 2778 * Retrieve the "Received Signal Strength Indicator" from the raw values 2779 * contained in Rx descriptors. The computation depends on which band the 2780 * frame was received. Correction values taken from the reference driver. 2781 */ 2782static int 2783rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2784{ 2785 int lna, agc, rssi; 2786 2787 lna = (raw >> 5) & 0x3; 2788 agc = raw & 0x1f; 2789 2790 if (lna == 0) { 2791 /* 2792 * No mapping available. 2793 * 2794 * NB: Since RSSI is relative to noise floor, -1 is 2795 * adequate for caller to know error happened. 2796 */ 2797 return -1; 2798 } 2799 2800 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2801 2802 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2803 rssi += sc->rssi_2ghz_corr; 2804 2805 if (lna == 1) 2806 rssi -= 64; 2807 else if (lna == 2) 2808 rssi -= 74; 2809 else if (lna == 3) 2810 rssi -= 90; 2811 } else { 2812 rssi += sc->rssi_5ghz_corr; 2813 2814 if (lna == 1) 2815 rssi -= 64; 2816 else if (lna == 2) 2817 rssi -= 86; 2818 else if (lna == 3) 2819 rssi -= 100; 2820 } 2821 return rssi; 2822} 2823 2824static void 2825rt2661_scan_start(struct ieee80211com *ic) 2826{ 2827 struct ifnet *ifp = ic->ic_ifp; 2828 struct rt2661_softc *sc = ifp->if_softc; 2829 uint32_t tmp; 2830 2831 /* abort TSF synchronization */ 2832 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2833 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2834 rt2661_set_bssid(sc, ifp->if_broadcastaddr); 2835} 2836 2837static void 2838rt2661_scan_end(struct ieee80211com *ic) 2839{ 2840 struct ifnet *ifp = ic->ic_ifp; 2841 struct rt2661_softc *sc = ifp->if_softc; 2842 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2843 2844 rt2661_enable_tsf_sync(sc); 2845 /* XXX keep local copy */ 2846 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2847} 2848 2849static void 2850rt2661_set_channel(struct ieee80211com *ic) 2851{ 2852 struct ifnet *ifp = ic->ic_ifp; 2853 struct rt2661_softc *sc = ifp->if_softc; 2854 2855 RAL_LOCK(sc); 2856 rt2661_set_chan(sc, ic->ic_curchan); 2857 RAL_UNLOCK(sc); 2858 2859} 2860