rt2661.c revision 179643
1/* $FreeBSD: head/sys/dev/ral/rt2661.c 179643 2008-06-07 18:38:02Z sam $ */ 2 3/*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2661.c 179643 2008-06-07 18:38:02Z sam $"); 22 23/*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_arp.h> 50#include <net/ethernet.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54 55#include <net80211/ieee80211_var.h> 56#include <net80211/ieee80211_phy.h> 57#include <net80211/ieee80211_radiotap.h> 58#include <net80211/ieee80211_regdomain.h> 59#include <net80211/ieee80211_amrr.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/ip.h> 65#include <netinet/if_ether.h> 66 67#include <dev/ral/rt2661reg.h> 68#include <dev/ral/rt2661var.h> 69 70#define RAL_DEBUG 71#ifdef RAL_DEBUG 72#define DPRINTF(sc, fmt, ...) do { \ 73 if (sc->sc_debug > 0) \ 74 printf(fmt, __VA_ARGS__); \ 75} while (0) 76#define DPRINTFN(sc, n, fmt, ...) do { \ 77 if (sc->sc_debug >= (n)) \ 78 printf(fmt, __VA_ARGS__); \ 79} while (0) 80#else 81#define DPRINTF(sc, fmt, ...) 82#define DPRINTFN(sc, n, fmt, ...) 83#endif 84 85static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 86 const char name[IFNAMSIZ], int unit, int opmode, 87 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 88 const uint8_t mac[IEEE80211_ADDR_LEN]); 89static void rt2661_vap_delete(struct ieee80211vap *); 90static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 91 int); 92static int rt2661_alloc_tx_ring(struct rt2661_softc *, 93 struct rt2661_tx_ring *, int); 94static void rt2661_reset_tx_ring(struct rt2661_softc *, 95 struct rt2661_tx_ring *); 96static void rt2661_free_tx_ring(struct rt2661_softc *, 97 struct rt2661_tx_ring *); 98static int rt2661_alloc_rx_ring(struct rt2661_softc *, 99 struct rt2661_rx_ring *, int); 100static void rt2661_reset_rx_ring(struct rt2661_softc *, 101 struct rt2661_rx_ring *); 102static void rt2661_free_rx_ring(struct rt2661_softc *, 103 struct rt2661_rx_ring *); 104static struct ieee80211_node *rt2661_node_alloc(struct ieee80211vap *, 105 const uint8_t [IEEE80211_ADDR_LEN]); 106static void rt2661_newassoc(struct ieee80211_node *, int); 107static int rt2661_newstate(struct ieee80211vap *, 108 enum ieee80211_state, int); 109static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 110static void rt2661_rx_intr(struct rt2661_softc *); 111static void rt2661_tx_intr(struct rt2661_softc *); 112static void rt2661_tx_dma_intr(struct rt2661_softc *, 113 struct rt2661_tx_ring *); 114static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 115static void rt2661_mcu_wakeup(struct rt2661_softc *); 116static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 117static void rt2661_scan_start(struct ieee80211com *); 118static void rt2661_scan_end(struct ieee80211com *); 119static void rt2661_set_channel(struct ieee80211com *); 120static void rt2661_setup_tx_desc(struct rt2661_softc *, 121 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 122 int, const bus_dma_segment_t *, int, int); 123static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 124 struct ieee80211_node *, int); 125static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 126 struct ieee80211_node *); 127static void rt2661_start_locked(struct ifnet *); 128static void rt2661_start(struct ifnet *); 129static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 130 const struct ieee80211_bpf_params *); 131static void rt2661_watchdog(void *); 132static int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 133static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 134 uint8_t); 135static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 136static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 137 uint32_t); 138static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 139 uint16_t); 140static void rt2661_select_antenna(struct rt2661_softc *); 141static void rt2661_enable_mrr(struct rt2661_softc *); 142static void rt2661_set_txpreamble(struct rt2661_softc *); 143static void rt2661_set_basicrates(struct rt2661_softc *, 144 const struct ieee80211_rateset *); 145static void rt2661_select_band(struct rt2661_softc *, 146 struct ieee80211_channel *); 147static void rt2661_set_chan(struct rt2661_softc *, 148 struct ieee80211_channel *); 149static void rt2661_set_bssid(struct rt2661_softc *, 150 const uint8_t *); 151static void rt2661_set_macaddr(struct rt2661_softc *, 152 const uint8_t *); 153static void rt2661_update_promisc(struct ifnet *); 154static int rt2661_wme_update(struct ieee80211com *) __unused; 155static void rt2661_update_slot(struct ifnet *); 156static const char *rt2661_get_rf(int); 157static void rt2661_read_eeprom(struct rt2661_softc *, 158 struct ieee80211com *); 159static int rt2661_bbp_init(struct rt2661_softc *); 160static void rt2661_init_locked(struct rt2661_softc *); 161static void rt2661_init(void *); 162static void rt2661_stop_locked(struct rt2661_softc *); 163static void rt2661_stop(void *); 164static int rt2661_load_microcode(struct rt2661_softc *); 165#ifdef notyet 166static void rt2661_rx_tune(struct rt2661_softc *); 167static void rt2661_radar_start(struct rt2661_softc *); 168static int rt2661_radar_stop(struct rt2661_softc *); 169#endif 170static int rt2661_prepare_beacon(struct rt2661_softc *, 171 struct ieee80211vap *); 172static void rt2661_enable_tsf_sync(struct rt2661_softc *); 173static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 174 175static const struct { 176 uint32_t reg; 177 uint32_t val; 178} rt2661_def_mac[] = { 179 RT2661_DEF_MAC 180}; 181 182static const struct { 183 uint8_t reg; 184 uint8_t val; 185} rt2661_def_bbp[] = { 186 RT2661_DEF_BBP 187}; 188 189static const struct rfprog { 190 uint8_t chan; 191 uint32_t r1, r2, r3, r4; 192} rt2661_rf5225_1[] = { 193 RT2661_RF5225_1 194}, rt2661_rf5225_2[] = { 195 RT2661_RF5225_2 196}; 197 198int 199rt2661_attach(device_t dev, int id) 200{ 201 struct rt2661_softc *sc = device_get_softc(dev); 202 struct ieee80211com *ic; 203 struct ifnet *ifp; 204 uint32_t val; 205 int error, ac, ntries; 206 uint8_t bands; 207 208 sc->sc_id = id; 209 sc->sc_dev = dev; 210 211 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 212 if (ifp == NULL) { 213 device_printf(sc->sc_dev, "can not if_alloc()\n"); 214 return ENOMEM; 215 } 216 ic = ifp->if_l2com; 217 218 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 219 MTX_DEF | MTX_RECURSE); 220 221 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 222 223 /* wait for NIC to initialize */ 224 for (ntries = 0; ntries < 1000; ntries++) { 225 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 226 break; 227 DELAY(1000); 228 } 229 if (ntries == 1000) { 230 device_printf(sc->sc_dev, 231 "timeout waiting for NIC to initialize\n"); 232 error = EIO; 233 goto fail1; 234 } 235 236 /* retrieve RF rev. no and various other things from EEPROM */ 237 rt2661_read_eeprom(sc, ic); 238 239 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 240 rt2661_get_rf(sc->rf_rev)); 241 242 /* 243 * Allocate Tx and Rx rings. 244 */ 245 for (ac = 0; ac < 4; ac++) { 246 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 247 RT2661_TX_RING_COUNT); 248 if (error != 0) { 249 device_printf(sc->sc_dev, 250 "could not allocate Tx ring %d\n", ac); 251 goto fail2; 252 } 253 } 254 255 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 256 if (error != 0) { 257 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 258 goto fail2; 259 } 260 261 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 262 if (error != 0) { 263 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 264 goto fail3; 265 } 266 267 ifp->if_softc = sc; 268 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 270 ifp->if_init = rt2661_init; 271 ifp->if_ioctl = rt2661_ioctl; 272 ifp->if_start = rt2661_start; 273 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 274 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 275 IFQ_SET_READY(&ifp->if_snd); 276 277 ic->ic_ifp = ifp; 278 ic->ic_opmode = IEEE80211_M_STA; 279 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 280 281 /* set device capabilities */ 282 ic->ic_caps = 283 IEEE80211_C_STA /* station mode */ 284 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 285 | IEEE80211_C_HOSTAP /* hostap mode */ 286 | IEEE80211_C_MONITOR /* monitor mode */ 287 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 288 | IEEE80211_C_WDS /* 4-address traffic works */ 289 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 290 | IEEE80211_C_SHSLOT /* short slot time supported */ 291 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 292 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 293#ifdef notyet 294 | IEEE80211_C_TXFRAG /* handle tx frags */ 295 | IEEE80211_C_WME /* 802.11e */ 296#endif 297 ; 298 299 bands = 0; 300 setbit(&bands, IEEE80211_MODE_11B); 301 setbit(&bands, IEEE80211_MODE_11G); 302 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) 303 setbit(&bands, IEEE80211_MODE_11A); 304 ieee80211_init_channels(ic, NULL, &bands); 305 306 ieee80211_ifattach(ic); 307 ic->ic_newassoc = rt2661_newassoc; 308 ic->ic_node_alloc = rt2661_node_alloc; 309#if 0 310 ic->ic_wme.wme_update = rt2661_wme_update; 311#endif 312 ic->ic_scan_start = rt2661_scan_start; 313 ic->ic_scan_end = rt2661_scan_end; 314 ic->ic_set_channel = rt2661_set_channel; 315 ic->ic_updateslot = rt2661_update_slot; 316 ic->ic_update_promisc = rt2661_update_promisc; 317 ic->ic_raw_xmit = rt2661_raw_xmit; 318 319 ic->ic_vap_create = rt2661_vap_create; 320 ic->ic_vap_delete = rt2661_vap_delete; 321 322 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 323 324 bpfattach(ifp, DLT_IEEE802_11_RADIO, 325 sizeof (struct ieee80211_frame) + sizeof (sc->sc_txtap)); 326 327 sc->sc_rxtap_len = sizeof sc->sc_rxtap; 328 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 329 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 330 331 sc->sc_txtap_len = sizeof sc->sc_txtap; 332 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 333 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 334 335#ifdef RAL_DEBUG 336 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 337 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 338 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 339#endif 340 if (bootverbose) 341 ieee80211_announce(ic); 342 343 return 0; 344 345fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 346fail2: while (--ac >= 0) 347 rt2661_free_tx_ring(sc, &sc->txq[ac]); 348fail1: mtx_destroy(&sc->sc_mtx); 349 if_free(ifp); 350 return error; 351} 352 353int 354rt2661_detach(void *xsc) 355{ 356 struct rt2661_softc *sc = xsc; 357 struct ifnet *ifp = sc->sc_ifp; 358 struct ieee80211com *ic = ifp->if_l2com; 359 360 RAL_LOCK(sc); 361 rt2661_stop_locked(sc); 362 RAL_UNLOCK(sc); 363 364 bpfdetach(ifp); 365 ieee80211_ifdetach(ic); 366 367 rt2661_free_tx_ring(sc, &sc->txq[0]); 368 rt2661_free_tx_ring(sc, &sc->txq[1]); 369 rt2661_free_tx_ring(sc, &sc->txq[2]); 370 rt2661_free_tx_ring(sc, &sc->txq[3]); 371 rt2661_free_tx_ring(sc, &sc->mgtq); 372 rt2661_free_rx_ring(sc, &sc->rxq); 373 374 if_free(ifp); 375 376 mtx_destroy(&sc->sc_mtx); 377 378 return 0; 379} 380 381static struct ieee80211vap * 382rt2661_vap_create(struct ieee80211com *ic, 383 const char name[IFNAMSIZ], int unit, int opmode, int flags, 384 const uint8_t bssid[IEEE80211_ADDR_LEN], 385 const uint8_t mac[IEEE80211_ADDR_LEN]) 386{ 387 struct ifnet *ifp = ic->ic_ifp; 388 struct rt2661_vap *rvp; 389 struct ieee80211vap *vap; 390 391 switch (opmode) { 392 case IEEE80211_M_STA: 393 case IEEE80211_M_IBSS: 394 case IEEE80211_M_AHDEMO: 395 case IEEE80211_M_MONITOR: 396 case IEEE80211_M_HOSTAP: 397 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 398 if_printf(ifp, "only 1 vap supported\n"); 399 return NULL; 400 } 401 if (opmode == IEEE80211_M_STA) 402 flags |= IEEE80211_CLONE_NOBEACONS; 403 break; 404 case IEEE80211_M_WDS: 405 if (TAILQ_EMPTY(&ic->ic_vaps) || 406 ic->ic_opmode != IEEE80211_M_HOSTAP) { 407 if_printf(ifp, "wds only supported in ap mode\n"); 408 return NULL; 409 } 410 /* 411 * Silently remove any request for a unique 412 * bssid; WDS vap's always share the local 413 * mac address. 414 */ 415 flags &= ~IEEE80211_CLONE_BSSID; 416 break; 417 default: 418 if_printf(ifp, "unknown opmode %d\n", opmode); 419 return NULL; 420 } 421 rvp = (struct rt2661_vap *) malloc(sizeof(struct rt2661_vap), 422 M_80211_VAP, M_NOWAIT | M_ZERO); 423 if (rvp == NULL) 424 return NULL; 425 vap = &rvp->ral_vap; 426 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 427 428 /* override state transition machine */ 429 rvp->ral_newstate = vap->iv_newstate; 430 vap->iv_newstate = rt2661_newstate; 431#if 0 432 vap->iv_update_beacon = rt2661_beacon_update; 433#endif 434 435 ieee80211_amrr_init(&rvp->amrr, vap, 436 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 437 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 438 500 /* ms */); 439 440 /* complete setup */ 441 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 442 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 443 ic->ic_opmode = opmode; 444 return vap; 445} 446 447static void 448rt2661_vap_delete(struct ieee80211vap *vap) 449{ 450 struct rt2661_vap *rvp = RT2661_VAP(vap); 451 452 ieee80211_amrr_cleanup(&rvp->amrr); 453 ieee80211_vap_detach(vap); 454 free(rvp, M_80211_VAP); 455} 456 457void 458rt2661_shutdown(void *xsc) 459{ 460 struct rt2661_softc *sc = xsc; 461 462 rt2661_stop(sc); 463} 464 465void 466rt2661_suspend(void *xsc) 467{ 468 struct rt2661_softc *sc = xsc; 469 470 rt2661_stop(sc); 471} 472 473void 474rt2661_resume(void *xsc) 475{ 476 struct rt2661_softc *sc = xsc; 477 struct ifnet *ifp = sc->sc_ifp; 478 479 if (ifp->if_flags & IFF_UP) 480 rt2661_init(sc); 481} 482 483static void 484rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 485{ 486 if (error != 0) 487 return; 488 489 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 490 491 *(bus_addr_t *)arg = segs[0].ds_addr; 492} 493 494static int 495rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 496 int count) 497{ 498 int i, error; 499 500 ring->count = count; 501 ring->queued = 0; 502 ring->cur = ring->next = ring->stat = 0; 503 504 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 505 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 506 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 507 0, NULL, NULL, &ring->desc_dmat); 508 if (error != 0) { 509 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 510 goto fail; 511 } 512 513 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 514 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 515 if (error != 0) { 516 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 517 goto fail; 518 } 519 520 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 521 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 522 0); 523 if (error != 0) { 524 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 525 goto fail; 526 } 527 528 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 529 M_NOWAIT | M_ZERO); 530 if (ring->data == NULL) { 531 device_printf(sc->sc_dev, "could not allocate soft data\n"); 532 error = ENOMEM; 533 goto fail; 534 } 535 536 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 537 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 538 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 539 if (error != 0) { 540 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 541 goto fail; 542 } 543 544 for (i = 0; i < count; i++) { 545 error = bus_dmamap_create(ring->data_dmat, 0, 546 &ring->data[i].map); 547 if (error != 0) { 548 device_printf(sc->sc_dev, "could not create DMA map\n"); 549 goto fail; 550 } 551 } 552 553 return 0; 554 555fail: rt2661_free_tx_ring(sc, ring); 556 return error; 557} 558 559static void 560rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 561{ 562 struct rt2661_tx_desc *desc; 563 struct rt2661_tx_data *data; 564 int i; 565 566 for (i = 0; i < ring->count; i++) { 567 desc = &ring->desc[i]; 568 data = &ring->data[i]; 569 570 if (data->m != NULL) { 571 bus_dmamap_sync(ring->data_dmat, data->map, 572 BUS_DMASYNC_POSTWRITE); 573 bus_dmamap_unload(ring->data_dmat, data->map); 574 m_freem(data->m); 575 data->m = NULL; 576 } 577 578 if (data->ni != NULL) { 579 ieee80211_free_node(data->ni); 580 data->ni = NULL; 581 } 582 583 desc->flags = 0; 584 } 585 586 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 587 588 ring->queued = 0; 589 ring->cur = ring->next = ring->stat = 0; 590} 591 592static void 593rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 594{ 595 struct rt2661_tx_data *data; 596 int i; 597 598 if (ring->desc != NULL) { 599 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 600 BUS_DMASYNC_POSTWRITE); 601 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 602 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 603 } 604 605 if (ring->desc_dmat != NULL) 606 bus_dma_tag_destroy(ring->desc_dmat); 607 608 if (ring->data != NULL) { 609 for (i = 0; i < ring->count; i++) { 610 data = &ring->data[i]; 611 612 if (data->m != NULL) { 613 bus_dmamap_sync(ring->data_dmat, data->map, 614 BUS_DMASYNC_POSTWRITE); 615 bus_dmamap_unload(ring->data_dmat, data->map); 616 m_freem(data->m); 617 } 618 619 if (data->ni != NULL) 620 ieee80211_free_node(data->ni); 621 622 if (data->map != NULL) 623 bus_dmamap_destroy(ring->data_dmat, data->map); 624 } 625 626 free(ring->data, M_DEVBUF); 627 } 628 629 if (ring->data_dmat != NULL) 630 bus_dma_tag_destroy(ring->data_dmat); 631} 632 633static int 634rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 635 int count) 636{ 637 struct rt2661_rx_desc *desc; 638 struct rt2661_rx_data *data; 639 bus_addr_t physaddr; 640 int i, error; 641 642 ring->count = count; 643 ring->cur = ring->next = 0; 644 645 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 646 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 647 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 648 0, NULL, NULL, &ring->desc_dmat); 649 if (error != 0) { 650 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 651 goto fail; 652 } 653 654 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 655 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 656 if (error != 0) { 657 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 658 goto fail; 659 } 660 661 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 662 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 663 0); 664 if (error != 0) { 665 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 666 goto fail; 667 } 668 669 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 670 M_NOWAIT | M_ZERO); 671 if (ring->data == NULL) { 672 device_printf(sc->sc_dev, "could not allocate soft data\n"); 673 error = ENOMEM; 674 goto fail; 675 } 676 677 /* 678 * Pre-allocate Rx buffers and populate Rx ring. 679 */ 680 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 681 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 682 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 683 if (error != 0) { 684 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 685 goto fail; 686 } 687 688 for (i = 0; i < count; i++) { 689 desc = &sc->rxq.desc[i]; 690 data = &sc->rxq.data[i]; 691 692 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 693 if (error != 0) { 694 device_printf(sc->sc_dev, "could not create DMA map\n"); 695 goto fail; 696 } 697 698 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 699 if (data->m == NULL) { 700 device_printf(sc->sc_dev, 701 "could not allocate rx mbuf\n"); 702 error = ENOMEM; 703 goto fail; 704 } 705 706 error = bus_dmamap_load(ring->data_dmat, data->map, 707 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 708 &physaddr, 0); 709 if (error != 0) { 710 device_printf(sc->sc_dev, 711 "could not load rx buf DMA map"); 712 goto fail; 713 } 714 715 desc->flags = htole32(RT2661_RX_BUSY); 716 desc->physaddr = htole32(physaddr); 717 } 718 719 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 720 721 return 0; 722 723fail: rt2661_free_rx_ring(sc, ring); 724 return error; 725} 726 727static void 728rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 729{ 730 int i; 731 732 for (i = 0; i < ring->count; i++) 733 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 734 735 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 736 737 ring->cur = ring->next = 0; 738} 739 740static void 741rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 742{ 743 struct rt2661_rx_data *data; 744 int i; 745 746 if (ring->desc != NULL) { 747 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 748 BUS_DMASYNC_POSTWRITE); 749 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 750 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 751 } 752 753 if (ring->desc_dmat != NULL) 754 bus_dma_tag_destroy(ring->desc_dmat); 755 756 if (ring->data != NULL) { 757 for (i = 0; i < ring->count; i++) { 758 data = &ring->data[i]; 759 760 if (data->m != NULL) { 761 bus_dmamap_sync(ring->data_dmat, data->map, 762 BUS_DMASYNC_POSTREAD); 763 bus_dmamap_unload(ring->data_dmat, data->map); 764 m_freem(data->m); 765 } 766 767 if (data->map != NULL) 768 bus_dmamap_destroy(ring->data_dmat, data->map); 769 } 770 771 free(ring->data, M_DEVBUF); 772 } 773 774 if (ring->data_dmat != NULL) 775 bus_dma_tag_destroy(ring->data_dmat); 776} 777 778static struct ieee80211_node * 779rt2661_node_alloc(struct ieee80211vap *vap, 780 const uint8_t mac[IEEE80211_ADDR_LEN]) 781{ 782 struct rt2661_node *rn; 783 784 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 785 M_NOWAIT | M_ZERO); 786 787 return (rn != NULL) ? &rn->ni : NULL; 788} 789 790static void 791rt2661_newassoc(struct ieee80211_node *ni, int isnew) 792{ 793 struct ieee80211vap *vap = ni->ni_vap; 794 795 ieee80211_amrr_node_init(&RT2661_VAP(vap)->amrr, 796 &RT2661_NODE(ni)->amrr, ni); 797} 798 799static int 800rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 801{ 802 struct rt2661_vap *rvp = RT2661_VAP(vap); 803 struct ieee80211com *ic = vap->iv_ic; 804 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 805 int error; 806 807 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 808 uint32_t tmp; 809 810 /* abort TSF synchronization */ 811 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 812 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 813 } 814 815 error = rvp->ral_newstate(vap, nstate, arg); 816 817 if (error == 0 && nstate == IEEE80211_S_RUN) { 818 struct ieee80211_node *ni = vap->iv_bss; 819 820 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 821 rt2661_enable_mrr(sc); 822 rt2661_set_txpreamble(sc); 823 rt2661_set_basicrates(sc, &ni->ni_rates); 824 rt2661_set_bssid(sc, ni->ni_bssid); 825 } 826 827 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 828 vap->iv_opmode == IEEE80211_M_IBSS) { 829 error = rt2661_prepare_beacon(sc, vap); 830 if (error != 0) 831 return error; 832 } 833 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 834 if (vap->iv_opmode == IEEE80211_M_STA) { 835 /* fake a join to init the tx rate */ 836 rt2661_newassoc(ni, 1); 837 } 838 rt2661_enable_tsf_sync(sc); 839 } 840 } 841 return error; 842} 843 844/* 845 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 846 * 93C66). 847 */ 848static uint16_t 849rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 850{ 851 uint32_t tmp; 852 uint16_t val; 853 int n; 854 855 /* clock C once before the first command */ 856 RT2661_EEPROM_CTL(sc, 0); 857 858 RT2661_EEPROM_CTL(sc, RT2661_S); 859 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 860 RT2661_EEPROM_CTL(sc, RT2661_S); 861 862 /* write start bit (1) */ 863 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 864 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 865 866 /* write READ opcode (10) */ 867 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 868 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 869 RT2661_EEPROM_CTL(sc, RT2661_S); 870 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 871 872 /* write address (A5-A0 or A7-A0) */ 873 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 874 for (; n >= 0; n--) { 875 RT2661_EEPROM_CTL(sc, RT2661_S | 876 (((addr >> n) & 1) << RT2661_SHIFT_D)); 877 RT2661_EEPROM_CTL(sc, RT2661_S | 878 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 879 } 880 881 RT2661_EEPROM_CTL(sc, RT2661_S); 882 883 /* read data Q15-Q0 */ 884 val = 0; 885 for (n = 15; n >= 0; n--) { 886 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 887 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 888 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 889 RT2661_EEPROM_CTL(sc, RT2661_S); 890 } 891 892 RT2661_EEPROM_CTL(sc, 0); 893 894 /* clear Chip Select and clock C */ 895 RT2661_EEPROM_CTL(sc, RT2661_S); 896 RT2661_EEPROM_CTL(sc, 0); 897 RT2661_EEPROM_CTL(sc, RT2661_C); 898 899 return val; 900} 901 902static void 903rt2661_tx_intr(struct rt2661_softc *sc) 904{ 905 struct ifnet *ifp = sc->sc_ifp; 906 struct rt2661_tx_ring *txq; 907 struct rt2661_tx_data *data; 908 struct rt2661_node *rn; 909 uint32_t val; 910 int qid, retrycnt; 911 912 for (;;) { 913 struct ieee80211_node *ni; 914 struct mbuf *m; 915 916 val = RAL_READ(sc, RT2661_STA_CSR4); 917 if (!(val & RT2661_TX_STAT_VALID)) 918 break; 919 920 /* retrieve the queue in which this frame was sent */ 921 qid = RT2661_TX_QID(val); 922 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 923 924 /* retrieve rate control algorithm context */ 925 data = &txq->data[txq->stat]; 926 m = data->m; 927 data->m = NULL; 928 ni = data->ni; 929 data->ni = NULL; 930 931 /* if no frame has been sent, ignore */ 932 if (ni == NULL) 933 continue; 934 935 rn = RT2661_NODE(ni); 936 937 switch (RT2661_TX_RESULT(val)) { 938 case RT2661_TX_SUCCESS: 939 retrycnt = RT2661_TX_RETRYCNT(val); 940 941 DPRINTFN(sc, 10, "data frame sent successfully after " 942 "%d retries\n", retrycnt); 943 if (data->rix != IEEE80211_FIXED_RATE_NONE) 944 ieee80211_amrr_tx_complete(&rn->amrr, 945 IEEE80211_AMRR_SUCCESS, retrycnt); 946 ifp->if_opackets++; 947 break; 948 949 case RT2661_TX_RETRY_FAIL: 950 retrycnt = RT2661_TX_RETRYCNT(val); 951 952 DPRINTFN(sc, 9, "%s\n", 953 "sending data frame failed (too much retries)"); 954 if (data->rix != IEEE80211_FIXED_RATE_NONE) 955 ieee80211_amrr_tx_complete(&rn->amrr, 956 IEEE80211_AMRR_FAILURE, retrycnt); 957 ifp->if_oerrors++; 958 break; 959 960 default: 961 /* other failure */ 962 device_printf(sc->sc_dev, 963 "sending data frame failed 0x%08x\n", val); 964 ifp->if_oerrors++; 965 } 966 967 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 968 969 txq->queued--; 970 if (++txq->stat >= txq->count) /* faster than % count */ 971 txq->stat = 0; 972 973 if (m->m_flags & M_TXCB) 974 ieee80211_process_callback(ni, m, 975 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS); 976 m_freem(m); 977 ieee80211_free_node(ni); 978 } 979 980 sc->sc_tx_timer = 0; 981 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 982 983 rt2661_start_locked(ifp); 984} 985 986static void 987rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 988{ 989 struct rt2661_tx_desc *desc; 990 struct rt2661_tx_data *data; 991 992 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 993 994 for (;;) { 995 desc = &txq->desc[txq->next]; 996 data = &txq->data[txq->next]; 997 998 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 999 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1000 break; 1001 1002 bus_dmamap_sync(txq->data_dmat, data->map, 1003 BUS_DMASYNC_POSTWRITE); 1004 bus_dmamap_unload(txq->data_dmat, data->map); 1005 1006 /* descriptor is no longer valid */ 1007 desc->flags &= ~htole32(RT2661_TX_VALID); 1008 1009 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 1010 1011 if (++txq->next >= txq->count) /* faster than % count */ 1012 txq->next = 0; 1013 } 1014 1015 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1016} 1017 1018static void 1019rt2661_rx_intr(struct rt2661_softc *sc) 1020{ 1021 struct ifnet *ifp = sc->sc_ifp; 1022 struct ieee80211com *ic = ifp->if_l2com; 1023 struct rt2661_rx_desc *desc; 1024 struct rt2661_rx_data *data; 1025 bus_addr_t physaddr; 1026 struct ieee80211_frame *wh; 1027 struct ieee80211_node *ni; 1028 struct mbuf *mnew, *m; 1029 int error; 1030 1031 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1032 BUS_DMASYNC_POSTREAD); 1033 1034 for (;;) { 1035 int rssi; 1036 1037 desc = &sc->rxq.desc[sc->rxq.cur]; 1038 data = &sc->rxq.data[sc->rxq.cur]; 1039 1040 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1041 break; 1042 1043 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1044 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1045 /* 1046 * This should not happen since we did not request 1047 * to receive those frames when we filled TXRX_CSR0. 1048 */ 1049 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 1050 le32toh(desc->flags)); 1051 ifp->if_ierrors++; 1052 goto skip; 1053 } 1054 1055 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1056 ifp->if_ierrors++; 1057 goto skip; 1058 } 1059 1060 /* 1061 * Try to allocate a new mbuf for this ring element and load it 1062 * before processing the current mbuf. If the ring element 1063 * cannot be loaded, drop the received packet and reuse the old 1064 * mbuf. In the unlikely case that the old mbuf can't be 1065 * reloaded either, explicitly panic. 1066 */ 1067 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1068 if (mnew == NULL) { 1069 ifp->if_ierrors++; 1070 goto skip; 1071 } 1072 1073 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1074 BUS_DMASYNC_POSTREAD); 1075 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1076 1077 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1078 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1079 &physaddr, 0); 1080 if (error != 0) { 1081 m_freem(mnew); 1082 1083 /* try to reload the old mbuf */ 1084 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1085 mtod(data->m, void *), MCLBYTES, 1086 rt2661_dma_map_addr, &physaddr, 0); 1087 if (error != 0) { 1088 /* very unlikely that it will fail... */ 1089 panic("%s: could not load old rx mbuf", 1090 device_get_name(sc->sc_dev)); 1091 } 1092 ifp->if_ierrors++; 1093 goto skip; 1094 } 1095 1096 /* 1097 * New mbuf successfully loaded, update Rx ring and continue 1098 * processing. 1099 */ 1100 m = data->m; 1101 data->m = mnew; 1102 desc->physaddr = htole32(physaddr); 1103 1104 /* finalize mbuf */ 1105 m->m_pkthdr.rcvif = ifp; 1106 m->m_pkthdr.len = m->m_len = 1107 (le32toh(desc->flags) >> 16) & 0xfff; 1108 1109 rssi = rt2661_get_rssi(sc, desc->rssi); 1110 1111 if (bpf_peers_present(ifp->if_bpf)) { 1112 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1113 uint32_t tsf_lo, tsf_hi; 1114 1115 /* get timestamp (low and high 32 bits) */ 1116 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1117 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1118 1119 tap->wr_tsf = 1120 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1121 tap->wr_flags = 0; 1122 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1123 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1124 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1125 tap->wr_antsignal = rssi < 0 ? 0 : rssi; 1126 1127 bpf_mtap2(ifp->if_bpf, tap, sc->sc_rxtap_len, m); 1128 } 1129 sc->sc_flags |= RAL_INPUT_RUNNING; 1130 RAL_UNLOCK(sc); 1131 wh = mtod(m, struct ieee80211_frame *); 1132 1133 /* send the frame to the 802.11 layer */ 1134 ni = ieee80211_find_rxnode(ic, 1135 (struct ieee80211_frame_min *)wh); 1136 if (ni != NULL) { 1137 /* Error happened during RSSI conversion. */ 1138 if (rssi < 0) 1139 rssi = -30; /* XXX ignored by net80211 */ 1140 1141 (void) ieee80211_input(ni, m, rssi, 1142 RT2661_NOISE_FLOOR, 0); 1143 ieee80211_free_node(ni); 1144 } else 1145 (void) ieee80211_input_all(ic, m, rssi, 1146 RT2661_NOISE_FLOOR, 0); 1147 1148 RAL_LOCK(sc); 1149 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1150 1151skip: desc->flags |= htole32(RT2661_RX_BUSY); 1152 1153 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1154 1155 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1156 } 1157 1158 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1159 BUS_DMASYNC_PREWRITE); 1160} 1161 1162/* ARGSUSED */ 1163static void 1164rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1165{ 1166 /* do nothing */ 1167} 1168 1169static void 1170rt2661_mcu_wakeup(struct rt2661_softc *sc) 1171{ 1172 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1173 1174 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1175 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1176 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1177 1178 /* send wakeup command to MCU */ 1179 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1180} 1181 1182static void 1183rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1184{ 1185 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1186 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1187} 1188 1189void 1190rt2661_intr(void *arg) 1191{ 1192 struct rt2661_softc *sc = arg; 1193 struct ifnet *ifp = sc->sc_ifp; 1194 uint32_t r1, r2; 1195 1196 RAL_LOCK(sc); 1197 1198 /* disable MAC and MCU interrupts */ 1199 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1200 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1201 1202 /* don't re-enable interrupts if we're shutting down */ 1203 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1204 RAL_UNLOCK(sc); 1205 return; 1206 } 1207 1208 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1209 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1210 1211 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1212 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1213 1214 if (r1 & RT2661_MGT_DONE) 1215 rt2661_tx_dma_intr(sc, &sc->mgtq); 1216 1217 if (r1 & RT2661_RX_DONE) 1218 rt2661_rx_intr(sc); 1219 1220 if (r1 & RT2661_TX0_DMA_DONE) 1221 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1222 1223 if (r1 & RT2661_TX1_DMA_DONE) 1224 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1225 1226 if (r1 & RT2661_TX2_DMA_DONE) 1227 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1228 1229 if (r1 & RT2661_TX3_DMA_DONE) 1230 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1231 1232 if (r1 & RT2661_TX_DONE) 1233 rt2661_tx_intr(sc); 1234 1235 if (r2 & RT2661_MCU_CMD_DONE) 1236 rt2661_mcu_cmd_intr(sc); 1237 1238 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1239 rt2661_mcu_beacon_expire(sc); 1240 1241 if (r2 & RT2661_MCU_WAKEUP) 1242 rt2661_mcu_wakeup(sc); 1243 1244 /* re-enable MAC and MCU interrupts */ 1245 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1246 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1247 1248 RAL_UNLOCK(sc); 1249} 1250 1251static uint8_t 1252rt2661_plcp_signal(int rate) 1253{ 1254 switch (rate) { 1255 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1256 case 12: return 0xb; 1257 case 18: return 0xf; 1258 case 24: return 0xa; 1259 case 36: return 0xe; 1260 case 48: return 0x9; 1261 case 72: return 0xd; 1262 case 96: return 0x8; 1263 case 108: return 0xc; 1264 1265 /* CCK rates (NB: not IEEE std, device-specific) */ 1266 case 2: return 0x0; 1267 case 4: return 0x1; 1268 case 11: return 0x2; 1269 case 22: return 0x3; 1270 } 1271 return 0xff; /* XXX unsupported/unknown rate */ 1272} 1273 1274static void 1275rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1276 uint32_t flags, uint16_t xflags, int len, int rate, 1277 const bus_dma_segment_t *segs, int nsegs, int ac) 1278{ 1279 struct ifnet *ifp = sc->sc_ifp; 1280 struct ieee80211com *ic = ifp->if_l2com; 1281 uint16_t plcp_length; 1282 int i, remainder; 1283 1284 desc->flags = htole32(flags); 1285 desc->flags |= htole32(len << 16); 1286 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1287 1288 desc->xflags = htole16(xflags); 1289 desc->xflags |= htole16(nsegs << 13); 1290 1291 desc->wme = htole16( 1292 RT2661_QID(ac) | 1293 RT2661_AIFSN(2) | 1294 RT2661_LOGCWMIN(4) | 1295 RT2661_LOGCWMAX(10)); 1296 1297 /* 1298 * Remember in which queue this frame was sent. This field is driver 1299 * private data only. It will be made available by the NIC in STA_CSR4 1300 * on Tx interrupts. 1301 */ 1302 desc->qid = ac; 1303 1304 /* setup PLCP fields */ 1305 desc->plcp_signal = rt2661_plcp_signal(rate); 1306 desc->plcp_service = 4; 1307 1308 len += IEEE80211_CRC_LEN; 1309 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 1310 desc->flags |= htole32(RT2661_TX_OFDM); 1311 1312 plcp_length = len & 0xfff; 1313 desc->plcp_length_hi = plcp_length >> 6; 1314 desc->plcp_length_lo = plcp_length & 0x3f; 1315 } else { 1316 plcp_length = (16 * len + rate - 1) / rate; 1317 if (rate == 22) { 1318 remainder = (16 * len) % 22; 1319 if (remainder != 0 && remainder < 7) 1320 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1321 } 1322 desc->plcp_length_hi = plcp_length >> 8; 1323 desc->plcp_length_lo = plcp_length & 0xff; 1324 1325 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1326 desc->plcp_signal |= 0x08; 1327 } 1328 1329 /* RT2x61 supports scatter with up to 5 segments */ 1330 for (i = 0; i < nsegs; i++) { 1331 desc->addr[i] = htole32(segs[i].ds_addr); 1332 desc->len [i] = htole16(segs[i].ds_len); 1333 } 1334} 1335 1336static int 1337rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1338 struct ieee80211_node *ni) 1339{ 1340 struct ieee80211vap *vap = ni->ni_vap; 1341 struct ieee80211com *ic = ni->ni_ic; 1342 struct ifnet *ifp = sc->sc_ifp; 1343 struct rt2661_tx_desc *desc; 1344 struct rt2661_tx_data *data; 1345 struct ieee80211_frame *wh; 1346 struct ieee80211_key *k; 1347 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1348 uint16_t dur; 1349 uint32_t flags = 0; /* XXX HWSEQ */ 1350 int nsegs, rate, error; 1351 1352 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1353 data = &sc->mgtq.data[sc->mgtq.cur]; 1354 1355 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1356 1357 wh = mtod(m0, struct ieee80211_frame *); 1358 1359 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1360 k = ieee80211_crypto_encap(ni, m0); 1361 if (k == NULL) { 1362 m_freem(m0); 1363 return ENOBUFS; 1364 } 1365 } 1366 1367 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1368 segs, &nsegs, 0); 1369 if (error != 0) { 1370 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1371 error); 1372 m_freem(m0); 1373 return error; 1374 } 1375 1376 if (bpf_peers_present(ifp->if_bpf)) { 1377 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1378 1379 tap->wt_flags = 0; 1380 tap->wt_rate = rate; 1381 1382 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0); 1383 } 1384 1385 data->m = m0; 1386 data->ni = ni; 1387 /* management frames are not taken into account for amrr */ 1388 data->rix = IEEE80211_FIXED_RATE_NONE; 1389 1390 wh = mtod(m0, struct ieee80211_frame *); 1391 1392 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1393 flags |= RT2661_TX_NEED_ACK; 1394 1395 dur = ieee80211_ack_duration(sc->sc_rates, 1396 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1397 *(uint16_t *)wh->i_dur = htole16(dur); 1398 1399 /* tell hardware to add timestamp in probe responses */ 1400 if ((wh->i_fc[0] & 1401 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1402 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1403 flags |= RT2661_TX_TIMESTAMP; 1404 } 1405 1406 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1407 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1408 1409 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1410 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1411 BUS_DMASYNC_PREWRITE); 1412 1413 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1414 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1415 1416 /* kick mgt */ 1417 sc->mgtq.queued++; 1418 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1419 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1420 1421 return 0; 1422} 1423 1424static int 1425rt2661_sendprot(struct rt2661_softc *sc, int ac, 1426 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1427{ 1428 struct ieee80211com *ic = ni->ni_ic; 1429 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1430 const struct ieee80211_frame *wh; 1431 struct rt2661_tx_desc *desc; 1432 struct rt2661_tx_data *data; 1433 struct mbuf *mprot; 1434 int protrate, ackrate, pktlen, flags, isshort, error; 1435 uint16_t dur; 1436 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1437 int nsegs; 1438 1439 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1440 ("protection %d", prot)); 1441 1442 wh = mtod(m, const struct ieee80211_frame *); 1443 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1444 1445 protrate = ieee80211_ctl_rate(sc->sc_rates, rate); 1446 ackrate = ieee80211_ack_rate(sc->sc_rates, rate); 1447 1448 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1449 dur = ieee80211_compute_duration(sc->sc_rates, pktlen, rate, isshort) 1450 + ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1451 flags = RT2661_TX_MORE_FRAG; 1452 if (prot == IEEE80211_PROT_RTSCTS) { 1453 /* NB: CTS is the same size as an ACK */ 1454 dur += ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1455 flags |= RT2661_TX_NEED_ACK; 1456 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1457 } else { 1458 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1459 } 1460 if (mprot == NULL) { 1461 /* XXX stat + msg */ 1462 return ENOBUFS; 1463 } 1464 1465 data = &txq->data[txq->cur]; 1466 desc = &txq->desc[txq->cur]; 1467 1468 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, 1469 &nsegs, 0); 1470 if (error != 0) { 1471 device_printf(sc->sc_dev, 1472 "could not map mbuf (error %d)\n", error); 1473 m_freem(mprot); 1474 return error; 1475 } 1476 1477 data->m = mprot; 1478 data->ni = ieee80211_ref_node(ni); 1479 /* ctl frames are not taken into account for amrr */ 1480 data->rix = IEEE80211_FIXED_RATE_NONE; 1481 1482 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1483 protrate, segs, 1, ac); 1484 1485 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1486 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1487 1488 txq->queued++; 1489 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1490 1491 return 0; 1492} 1493 1494static int 1495rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1496 struct ieee80211_node *ni, int ac) 1497{ 1498 struct ieee80211vap *vap = ni->ni_vap; 1499 struct ifnet *ifp = sc->sc_ifp; 1500 struct ieee80211com *ic = ifp->if_l2com; 1501 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1502 struct rt2661_tx_desc *desc; 1503 struct rt2661_tx_data *data; 1504 struct ieee80211_frame *wh; 1505 const struct ieee80211_txparam *tp; 1506 struct ieee80211_key *k; 1507 const struct chanAccParams *cap; 1508 struct mbuf *mnew; 1509 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1510 uint16_t dur; 1511 uint32_t flags; 1512 int error, nsegs, rate, noack = 0; 1513 1514 wh = mtod(m0, struct ieee80211_frame *); 1515 1516 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1517 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1518 rate = tp->mcastrate; 1519 } else if (m0->m_flags & M_EAPOL) { 1520 rate = tp->mgmtrate; 1521 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1522 rate = tp->ucastrate; 1523 } else { 1524 (void) ieee80211_amrr_choose(ni, &RT2661_NODE(ni)->amrr); 1525 rate = ni->ni_txrate; 1526 } 1527 rate &= IEEE80211_RATE_VAL; 1528 1529 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1530 cap = &ic->ic_wme.wme_chanParams; 1531 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1532 } 1533 1534 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1535 k = ieee80211_crypto_encap(ni, m0); 1536 if (k == NULL) { 1537 m_freem(m0); 1538 return ENOBUFS; 1539 } 1540 1541 /* packet header may have moved, reset our local pointer */ 1542 wh = mtod(m0, struct ieee80211_frame *); 1543 } 1544 1545 flags = 0; 1546 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1547 int prot = IEEE80211_PROT_NONE; 1548 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1549 prot = IEEE80211_PROT_RTSCTS; 1550 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1551 ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 1552 prot = ic->ic_protmode; 1553 if (prot != IEEE80211_PROT_NONE) { 1554 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1555 if (error) { 1556 m_freem(m0); 1557 return error; 1558 } 1559 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1560 } 1561 } 1562 1563 data = &txq->data[txq->cur]; 1564 desc = &txq->desc[txq->cur]; 1565 1566 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1567 &nsegs, 0); 1568 if (error != 0 && error != EFBIG) { 1569 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1570 error); 1571 m_freem(m0); 1572 return error; 1573 } 1574 if (error != 0) { 1575 mnew = m_defrag(m0, M_DONTWAIT); 1576 if (mnew == NULL) { 1577 device_printf(sc->sc_dev, 1578 "could not defragment mbuf\n"); 1579 m_freem(m0); 1580 return ENOBUFS; 1581 } 1582 m0 = mnew; 1583 1584 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1585 segs, &nsegs, 0); 1586 if (error != 0) { 1587 device_printf(sc->sc_dev, 1588 "could not map mbuf (error %d)\n", error); 1589 m_freem(m0); 1590 return error; 1591 } 1592 1593 /* packet header have moved, reset our local pointer */ 1594 wh = mtod(m0, struct ieee80211_frame *); 1595 } 1596 1597 if (bpf_peers_present(ifp->if_bpf)) { 1598 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1599 1600 tap->wt_flags = 0; 1601 tap->wt_rate = rate; 1602 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1603 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1604 1605 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0); 1606 } 1607 1608 data->m = m0; 1609 data->ni = ni; 1610 1611 /* remember link conditions for rate adaptation algorithm */ 1612 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1613 data->rix = ni->ni_txrate; 1614 /* XXX probably need last rssi value and not avg */ 1615 data->rssi = ic->ic_node_getrssi(ni); 1616 } else 1617 data->rix = IEEE80211_FIXED_RATE_NONE; 1618 1619 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1620 flags |= RT2661_TX_NEED_ACK; 1621 1622 dur = ieee80211_ack_duration(sc->sc_rates, 1623 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1624 *(uint16_t *)wh->i_dur = htole16(dur); 1625 } 1626 1627 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1628 nsegs, ac); 1629 1630 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1631 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1632 1633 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1634 m0->m_pkthdr.len, txq->cur, rate); 1635 1636 /* kick Tx */ 1637 txq->queued++; 1638 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1639 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1640 1641 return 0; 1642} 1643 1644static void 1645rt2661_start_locked(struct ifnet *ifp) 1646{ 1647 struct rt2661_softc *sc = ifp->if_softc; 1648 struct mbuf *m; 1649 struct ieee80211_node *ni; 1650 int ac; 1651 1652 RAL_LOCK_ASSERT(sc); 1653 1654 /* prevent management frames from being sent if we're not ready */ 1655 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || sc->sc_invalid) 1656 return; 1657 1658 for (;;) { 1659 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1660 if (m == NULL) 1661 break; 1662 1663 ac = M_WME_GETAC(m); 1664 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1665 /* there is no place left in this ring */ 1666 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1667 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1668 break; 1669 } 1670 1671 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1672 m = ieee80211_encap(ni, m); 1673 if (m == NULL) { 1674 ieee80211_free_node(ni); 1675 ifp->if_oerrors++; 1676 continue; 1677 } 1678 1679 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1680 ieee80211_free_node(ni); 1681 ifp->if_oerrors++; 1682 break; 1683 } 1684 1685 sc->sc_tx_timer = 5; 1686 } 1687} 1688 1689static void 1690rt2661_start(struct ifnet *ifp) 1691{ 1692 struct rt2661_softc *sc = ifp->if_softc; 1693 1694 RAL_LOCK(sc); 1695 rt2661_start_locked(ifp); 1696 RAL_UNLOCK(sc); 1697} 1698 1699static int 1700rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1701 const struct ieee80211_bpf_params *params) 1702{ 1703 struct ieee80211com *ic = ni->ni_ic; 1704 struct ifnet *ifp = ic->ic_ifp; 1705 struct rt2661_softc *sc = ifp->if_softc; 1706 1707 RAL_LOCK(sc); 1708 1709 /* prevent management frames from being sent if we're not ready */ 1710 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1711 RAL_UNLOCK(sc); 1712 m_freem(m); 1713 ieee80211_free_node(ni); 1714 return ENETDOWN; 1715 } 1716 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1717 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1718 RAL_UNLOCK(sc); 1719 m_freem(m); 1720 ieee80211_free_node(ni); 1721 return ENOBUFS; /* XXX */ 1722 } 1723 1724 ifp->if_opackets++; 1725 1726 /* 1727 * Legacy path; interpret frame contents to decide 1728 * precisely how to send the frame. 1729 * XXX raw path 1730 */ 1731 if (rt2661_tx_mgt(sc, m, ni) != 0) 1732 goto bad; 1733 sc->sc_tx_timer = 5; 1734 1735 RAL_UNLOCK(sc); 1736 1737 return 0; 1738bad: 1739 ifp->if_oerrors++; 1740 ieee80211_free_node(ni); 1741 RAL_UNLOCK(sc); 1742 return EIO; /* XXX */ 1743} 1744 1745static void 1746rt2661_watchdog(void *arg) 1747{ 1748 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1749 struct ifnet *ifp = sc->sc_ifp; 1750 1751 RAL_LOCK_ASSERT(sc); 1752 1753 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 1754 1755 if (sc->sc_invalid) /* card ejected */ 1756 return; 1757 1758 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1759 if_printf(ifp, "device timeout\n"); 1760 rt2661_init_locked(sc); 1761 ifp->if_oerrors++; 1762 /* NB: callout is reset in rt2661_init() */ 1763 return; 1764 } 1765 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1766} 1767 1768static int 1769rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1770{ 1771 struct rt2661_softc *sc = ifp->if_softc; 1772 struct ieee80211com *ic = ifp->if_l2com; 1773 struct ifreq *ifr = (struct ifreq *) data; 1774 int error = 0, startall = 0; 1775 1776 switch (cmd) { 1777 case SIOCSIFFLAGS: 1778 RAL_LOCK(sc); 1779 if (ifp->if_flags & IFF_UP) { 1780 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1781 rt2661_init_locked(sc); 1782 startall = 1; 1783 } else 1784 rt2661_update_promisc(ifp); 1785 } else { 1786 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1787 rt2661_stop_locked(sc); 1788 } 1789 RAL_UNLOCK(sc); 1790 if (startall) 1791 ieee80211_start_all(ic); 1792 break; 1793 case SIOCGIFMEDIA: 1794 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1795 break; 1796 case SIOCGIFADDR: 1797 error = ether_ioctl(ifp, cmd, data); 1798 break; 1799 default: 1800 error = EINVAL; 1801 break; 1802 } 1803 return error; 1804} 1805 1806static void 1807rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1808{ 1809 uint32_t tmp; 1810 int ntries; 1811 1812 for (ntries = 0; ntries < 100; ntries++) { 1813 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1814 break; 1815 DELAY(1); 1816 } 1817 if (ntries == 100) { 1818 device_printf(sc->sc_dev, "could not write to BBP\n"); 1819 return; 1820 } 1821 1822 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1823 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1824 1825 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1826} 1827 1828static uint8_t 1829rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1830{ 1831 uint32_t val; 1832 int ntries; 1833 1834 for (ntries = 0; ntries < 100; ntries++) { 1835 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1836 break; 1837 DELAY(1); 1838 } 1839 if (ntries == 100) { 1840 device_printf(sc->sc_dev, "could not read from BBP\n"); 1841 return 0; 1842 } 1843 1844 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1845 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1846 1847 for (ntries = 0; ntries < 100; ntries++) { 1848 val = RAL_READ(sc, RT2661_PHY_CSR3); 1849 if (!(val & RT2661_BBP_BUSY)) 1850 return val & 0xff; 1851 DELAY(1); 1852 } 1853 1854 device_printf(sc->sc_dev, "could not read from BBP\n"); 1855 return 0; 1856} 1857 1858static void 1859rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1860{ 1861 uint32_t tmp; 1862 int ntries; 1863 1864 for (ntries = 0; ntries < 100; ntries++) { 1865 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1866 break; 1867 DELAY(1); 1868 } 1869 if (ntries == 100) { 1870 device_printf(sc->sc_dev, "could not write to RF\n"); 1871 return; 1872 } 1873 1874 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1875 (reg & 3); 1876 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1877 1878 /* remember last written value in sc */ 1879 sc->rf_regs[reg] = val; 1880 1881 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1882} 1883 1884static int 1885rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1886{ 1887 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1888 return EIO; /* there is already a command pending */ 1889 1890 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1891 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1892 1893 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1894 1895 return 0; 1896} 1897 1898static void 1899rt2661_select_antenna(struct rt2661_softc *sc) 1900{ 1901 uint8_t bbp4, bbp77; 1902 uint32_t tmp; 1903 1904 bbp4 = rt2661_bbp_read(sc, 4); 1905 bbp77 = rt2661_bbp_read(sc, 77); 1906 1907 /* TBD */ 1908 1909 /* make sure Rx is disabled before switching antenna */ 1910 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1911 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1912 1913 rt2661_bbp_write(sc, 4, bbp4); 1914 rt2661_bbp_write(sc, 77, bbp77); 1915 1916 /* restore Rx filter */ 1917 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1918} 1919 1920/* 1921 * Enable multi-rate retries for frames sent at OFDM rates. 1922 * In 802.11b/g mode, allow fallback to CCK rates. 1923 */ 1924static void 1925rt2661_enable_mrr(struct rt2661_softc *sc) 1926{ 1927 struct ifnet *ifp = sc->sc_ifp; 1928 struct ieee80211com *ic = ifp->if_l2com; 1929 uint32_t tmp; 1930 1931 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1932 1933 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1934 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1935 tmp |= RT2661_MRR_CCK_FALLBACK; 1936 tmp |= RT2661_MRR_ENABLED; 1937 1938 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1939} 1940 1941static void 1942rt2661_set_txpreamble(struct rt2661_softc *sc) 1943{ 1944 struct ifnet *ifp = sc->sc_ifp; 1945 struct ieee80211com *ic = ifp->if_l2com; 1946 uint32_t tmp; 1947 1948 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1949 1950 tmp &= ~RT2661_SHORT_PREAMBLE; 1951 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1952 tmp |= RT2661_SHORT_PREAMBLE; 1953 1954 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1955} 1956 1957static void 1958rt2661_set_basicrates(struct rt2661_softc *sc, 1959 const struct ieee80211_rateset *rs) 1960{ 1961#define RV(r) ((r) & IEEE80211_RATE_VAL) 1962 struct ifnet *ifp = sc->sc_ifp; 1963 struct ieee80211com *ic = ifp->if_l2com; 1964 uint32_t mask = 0; 1965 uint8_t rate; 1966 int i, j; 1967 1968 for (i = 0; i < rs->rs_nrates; i++) { 1969 rate = rs->rs_rates[i]; 1970 1971 if (!(rate & IEEE80211_RATE_BASIC)) 1972 continue; 1973 1974 /* 1975 * Find h/w rate index. We know it exists because the rate 1976 * set has already been negotiated. 1977 */ 1978 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); 1979 1980 mask |= 1 << j; 1981 } 1982 1983 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1984 1985 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1986#undef RV 1987} 1988 1989/* 1990 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1991 * driver. 1992 */ 1993static void 1994rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1995{ 1996 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1997 uint32_t tmp; 1998 1999 /* update all BBP registers that depend on the band */ 2000 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2001 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2002 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2003 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2004 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2005 } 2006 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2007 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2008 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2009 } 2010 2011 rt2661_bbp_write(sc, 17, bbp17); 2012 rt2661_bbp_write(sc, 96, bbp96); 2013 rt2661_bbp_write(sc, 104, bbp104); 2014 2015 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2016 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2017 rt2661_bbp_write(sc, 75, 0x80); 2018 rt2661_bbp_write(sc, 86, 0x80); 2019 rt2661_bbp_write(sc, 88, 0x80); 2020 } 2021 2022 rt2661_bbp_write(sc, 35, bbp35); 2023 rt2661_bbp_write(sc, 97, bbp97); 2024 rt2661_bbp_write(sc, 98, bbp98); 2025 2026 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2027 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2028 if (IEEE80211_IS_CHAN_2GHZ(c)) 2029 tmp |= RT2661_PA_PE_2GHZ; 2030 else 2031 tmp |= RT2661_PA_PE_5GHZ; 2032 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2033} 2034 2035static void 2036rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2037{ 2038 struct ifnet *ifp = sc->sc_ifp; 2039 struct ieee80211com *ic = ifp->if_l2com; 2040 const struct rfprog *rfprog; 2041 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2042 int8_t power; 2043 u_int i, chan; 2044 2045 chan = ieee80211_chan2ieee(ic, c); 2046 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 2047 2048 sc->sc_rates = ieee80211_get_ratetable(c); 2049 2050 /* select the appropriate RF settings based on what EEPROM says */ 2051 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2052 2053 /* find the settings for this channel (we know it exists) */ 2054 for (i = 0; rfprog[i].chan != chan; i++); 2055 2056 power = sc->txpow[i]; 2057 if (power < 0) { 2058 bbp94 += power; 2059 power = 0; 2060 } else if (power > 31) { 2061 bbp94 += power - 31; 2062 power = 31; 2063 } 2064 2065 /* 2066 * If we are switching from the 2GHz band to the 5GHz band or 2067 * vice-versa, BBP registers need to be reprogrammed. 2068 */ 2069 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2070 rt2661_select_band(sc, c); 2071 rt2661_select_antenna(sc); 2072 } 2073 sc->sc_curchan = c; 2074 2075 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2076 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2077 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2078 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2079 2080 DELAY(200); 2081 2082 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2083 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2084 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2085 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2086 2087 DELAY(200); 2088 2089 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2090 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2091 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2092 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2093 2094 /* enable smart mode for MIMO-capable RFs */ 2095 bbp3 = rt2661_bbp_read(sc, 3); 2096 2097 bbp3 &= ~RT2661_SMART_MODE; 2098 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2099 bbp3 |= RT2661_SMART_MODE; 2100 2101 rt2661_bbp_write(sc, 3, bbp3); 2102 2103 if (bbp94 != RT2661_BBPR94_DEFAULT) 2104 rt2661_bbp_write(sc, 94, bbp94); 2105 2106 /* 5GHz radio needs a 1ms delay here */ 2107 if (IEEE80211_IS_CHAN_5GHZ(c)) 2108 DELAY(1000); 2109} 2110 2111static void 2112rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2113{ 2114 uint32_t tmp; 2115 2116 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2117 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2118 2119 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2120 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2121} 2122 2123static void 2124rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2125{ 2126 uint32_t tmp; 2127 2128 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2129 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2130 2131 tmp = addr[4] | addr[5] << 8; 2132 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2133} 2134 2135static void 2136rt2661_update_promisc(struct ifnet *ifp) 2137{ 2138 struct rt2661_softc *sc = ifp->if_softc; 2139 uint32_t tmp; 2140 2141 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2142 2143 tmp &= ~RT2661_DROP_NOT_TO_ME; 2144 if (!(ifp->if_flags & IFF_PROMISC)) 2145 tmp |= RT2661_DROP_NOT_TO_ME; 2146 2147 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2148 2149 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2150 "entering" : "leaving"); 2151} 2152 2153/* 2154 * Update QoS (802.11e) settings for each h/w Tx ring. 2155 */ 2156static int 2157rt2661_wme_update(struct ieee80211com *ic) 2158{ 2159 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2160 const struct wmeParams *wmep; 2161 2162 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2163 2164 /* XXX: not sure about shifts. */ 2165 /* XXX: the reference driver plays with AC_VI settings too. */ 2166 2167 /* update TxOp */ 2168 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2169 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2170 wmep[WME_AC_BK].wmep_txopLimit); 2171 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2172 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2173 wmep[WME_AC_VO].wmep_txopLimit); 2174 2175 /* update CWmin */ 2176 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2177 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2178 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2179 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2180 wmep[WME_AC_VO].wmep_logcwmin); 2181 2182 /* update CWmax */ 2183 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2184 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2185 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2186 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2187 wmep[WME_AC_VO].wmep_logcwmax); 2188 2189 /* update Aifsn */ 2190 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2191 wmep[WME_AC_BE].wmep_aifsn << 12 | 2192 wmep[WME_AC_BK].wmep_aifsn << 8 | 2193 wmep[WME_AC_VI].wmep_aifsn << 4 | 2194 wmep[WME_AC_VO].wmep_aifsn); 2195 2196 return 0; 2197} 2198 2199static void 2200rt2661_update_slot(struct ifnet *ifp) 2201{ 2202 struct rt2661_softc *sc = ifp->if_softc; 2203 struct ieee80211com *ic = ifp->if_l2com; 2204 uint8_t slottime; 2205 uint32_t tmp; 2206 2207 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2208 2209 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2210 tmp = (tmp & ~0xff) | slottime; 2211 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2212} 2213 2214static const char * 2215rt2661_get_rf(int rev) 2216{ 2217 switch (rev) { 2218 case RT2661_RF_5225: return "RT5225"; 2219 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2220 case RT2661_RF_2527: return "RT2527"; 2221 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2222 default: return "unknown"; 2223 } 2224} 2225 2226static void 2227rt2661_read_eeprom(struct rt2661_softc *sc, struct ieee80211com *ic) 2228{ 2229 uint16_t val; 2230 int i; 2231 2232 /* read MAC address */ 2233 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2234 ic->ic_myaddr[0] = val & 0xff; 2235 ic->ic_myaddr[1] = val >> 8; 2236 2237 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2238 ic->ic_myaddr[2] = val & 0xff; 2239 ic->ic_myaddr[3] = val >> 8; 2240 2241 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2242 ic->ic_myaddr[4] = val & 0xff; 2243 ic->ic_myaddr[5] = val >> 8; 2244 2245 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2246 /* XXX: test if different from 0xffff? */ 2247 sc->rf_rev = (val >> 11) & 0x1f; 2248 sc->hw_radio = (val >> 10) & 0x1; 2249 sc->rx_ant = (val >> 4) & 0x3; 2250 sc->tx_ant = (val >> 2) & 0x3; 2251 sc->nb_ant = val & 0x3; 2252 2253 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2254 2255 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2256 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2257 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2258 2259 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2260 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2261 2262 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2263 if ((val & 0xff) != 0xff) 2264 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2265 2266 /* Only [-10, 10] is valid */ 2267 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2268 sc->rssi_2ghz_corr = 0; 2269 2270 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2271 if ((val & 0xff) != 0xff) 2272 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2273 2274 /* Only [-10, 10] is valid */ 2275 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2276 sc->rssi_5ghz_corr = 0; 2277 2278 /* adjust RSSI correction for external low-noise amplifier */ 2279 if (sc->ext_2ghz_lna) 2280 sc->rssi_2ghz_corr -= 14; 2281 if (sc->ext_5ghz_lna) 2282 sc->rssi_5ghz_corr -= 14; 2283 2284 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2285 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2286 2287 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2288 if ((val >> 8) != 0xff) 2289 sc->rfprog = (val >> 8) & 0x3; 2290 if ((val & 0xff) != 0xff) 2291 sc->rffreq = val & 0xff; 2292 2293 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2294 2295 /* read Tx power for all a/b/g channels */ 2296 for (i = 0; i < 19; i++) { 2297 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2298 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2299 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2300 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2301 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2302 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2303 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2304 } 2305 2306 /* read vendor-specific BBP values */ 2307 for (i = 0; i < 16; i++) { 2308 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2309 if (val == 0 || val == 0xffff) 2310 continue; /* skip invalid entries */ 2311 sc->bbp_prom[i].reg = val >> 8; 2312 sc->bbp_prom[i].val = val & 0xff; 2313 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2314 sc->bbp_prom[i].val); 2315 } 2316} 2317 2318static int 2319rt2661_bbp_init(struct rt2661_softc *sc) 2320{ 2321#define N(a) (sizeof (a) / sizeof ((a)[0])) 2322 int i, ntries; 2323 uint8_t val; 2324 2325 /* wait for BBP to be ready */ 2326 for (ntries = 0; ntries < 100; ntries++) { 2327 val = rt2661_bbp_read(sc, 0); 2328 if (val != 0 && val != 0xff) 2329 break; 2330 DELAY(100); 2331 } 2332 if (ntries == 100) { 2333 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2334 return EIO; 2335 } 2336 2337 /* initialize BBP registers to default values */ 2338 for (i = 0; i < N(rt2661_def_bbp); i++) { 2339 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2340 rt2661_def_bbp[i].val); 2341 } 2342 2343 /* write vendor-specific BBP values (from EEPROM) */ 2344 for (i = 0; i < 16; i++) { 2345 if (sc->bbp_prom[i].reg == 0) 2346 continue; 2347 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2348 } 2349 2350 return 0; 2351#undef N 2352} 2353 2354static void 2355rt2661_init_locked(struct rt2661_softc *sc) 2356{ 2357#define N(a) (sizeof (a) / sizeof ((a)[0])) 2358 struct ifnet *ifp = sc->sc_ifp; 2359 struct ieee80211com *ic = ifp->if_l2com; 2360 uint32_t tmp, sta[3]; 2361 int i, error, ntries; 2362 2363 RAL_LOCK_ASSERT(sc); 2364 2365 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2366 error = rt2661_load_microcode(sc); 2367 if (error != 0) { 2368 if_printf(ifp, 2369 "%s: could not load 8051 microcode, error %d\n", 2370 __func__, error); 2371 return; 2372 } 2373 sc->sc_flags |= RAL_FW_LOADED; 2374 } 2375 2376 rt2661_stop_locked(sc); 2377 2378 /* initialize Tx rings */ 2379 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2380 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2381 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2382 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2383 2384 /* initialize Mgt ring */ 2385 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2386 2387 /* initialize Rx ring */ 2388 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2389 2390 /* initialize Tx rings sizes */ 2391 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2392 RT2661_TX_RING_COUNT << 24 | 2393 RT2661_TX_RING_COUNT << 16 | 2394 RT2661_TX_RING_COUNT << 8 | 2395 RT2661_TX_RING_COUNT); 2396 2397 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2398 RT2661_TX_DESC_WSIZE << 16 | 2399 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2400 RT2661_MGT_RING_COUNT); 2401 2402 /* initialize Rx rings */ 2403 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2404 RT2661_RX_DESC_BACK << 16 | 2405 RT2661_RX_DESC_WSIZE << 8 | 2406 RT2661_RX_RING_COUNT); 2407 2408 /* XXX: some magic here */ 2409 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2410 2411 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2412 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2413 2414 /* load base address of Rx ring */ 2415 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2416 2417 /* initialize MAC registers to default values */ 2418 for (i = 0; i < N(rt2661_def_mac); i++) 2419 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2420 2421 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2422 rt2661_set_macaddr(sc, ic->ic_myaddr); 2423 2424 /* set host ready */ 2425 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2426 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2427 2428 /* wait for BBP/RF to wakeup */ 2429 for (ntries = 0; ntries < 1000; ntries++) { 2430 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2431 break; 2432 DELAY(1000); 2433 } 2434 if (ntries == 1000) { 2435 printf("timeout waiting for BBP/RF to wakeup\n"); 2436 rt2661_stop_locked(sc); 2437 return; 2438 } 2439 2440 if (rt2661_bbp_init(sc) != 0) { 2441 rt2661_stop_locked(sc); 2442 return; 2443 } 2444 2445 /* select default channel */ 2446 sc->sc_curchan = ic->ic_curchan; 2447 rt2661_select_band(sc, sc->sc_curchan); 2448 rt2661_select_antenna(sc); 2449 rt2661_set_chan(sc, sc->sc_curchan); 2450 2451 /* update Rx filter */ 2452 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2453 2454 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2455 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2456 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2457 RT2661_DROP_ACKCTS; 2458 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2459 tmp |= RT2661_DROP_TODS; 2460 if (!(ifp->if_flags & IFF_PROMISC)) 2461 tmp |= RT2661_DROP_NOT_TO_ME; 2462 } 2463 2464 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2465 2466 /* clear STA registers */ 2467 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2468 2469 /* initialize ASIC */ 2470 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2471 2472 /* clear any pending interrupt */ 2473 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2474 2475 /* enable interrupts */ 2476 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2477 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2478 2479 /* kick Rx */ 2480 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2481 2482 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2483 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2484 2485 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2486#undef N 2487} 2488 2489static void 2490rt2661_init(void *priv) 2491{ 2492 struct rt2661_softc *sc = priv; 2493 struct ifnet *ifp = sc->sc_ifp; 2494 struct ieee80211com *ic = ifp->if_l2com; 2495 2496 RAL_LOCK(sc); 2497 rt2661_init_locked(sc); 2498 RAL_UNLOCK(sc); 2499 2500 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2501 ieee80211_start_all(ic); /* start all vap's */ 2502} 2503 2504void 2505rt2661_stop_locked(struct rt2661_softc *sc) 2506{ 2507 struct ifnet *ifp = sc->sc_ifp; 2508 uint32_t tmp; 2509 volatile int *flags = &sc->sc_flags; 2510 2511 while (*flags & RAL_INPUT_RUNNING) 2512 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2513 2514 callout_stop(&sc->watchdog_ch); 2515 sc->sc_tx_timer = 0; 2516 2517 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2518 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2519 2520 /* abort Tx (for all 5 Tx rings) */ 2521 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2522 2523 /* disable Rx (value remains after reset!) */ 2524 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2525 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2526 2527 /* reset ASIC */ 2528 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2529 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2530 2531 /* disable interrupts */ 2532 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2533 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2534 2535 /* clear any pending interrupt */ 2536 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2537 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2538 2539 /* reset Tx and Rx rings */ 2540 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2541 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2542 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2543 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2544 rt2661_reset_tx_ring(sc, &sc->mgtq); 2545 rt2661_reset_rx_ring(sc, &sc->rxq); 2546 } 2547} 2548 2549void 2550rt2661_stop(void *priv) 2551{ 2552 struct rt2661_softc *sc = priv; 2553 2554 RAL_LOCK(sc); 2555 rt2661_stop_locked(sc); 2556 RAL_UNLOCK(sc); 2557} 2558 2559static int 2560rt2661_load_microcode(struct rt2661_softc *sc) 2561{ 2562 struct ifnet *ifp = sc->sc_ifp; 2563 const struct firmware *fp; 2564 const char *imagename; 2565 int ntries, error; 2566 2567 RAL_LOCK_ASSERT(sc); 2568 2569 switch (sc->sc_id) { 2570 case 0x0301: imagename = "rt2561sfw"; break; 2571 case 0x0302: imagename = "rt2561fw"; break; 2572 case 0x0401: imagename = "rt2661fw"; break; 2573 default: 2574 if_printf(ifp, "%s: unexpected pci device id 0x%x, " 2575 "don't know how to retrieve firmware\n", 2576 __func__, sc->sc_id); 2577 return EINVAL; 2578 } 2579 RAL_UNLOCK(sc); 2580 fp = firmware_get(imagename); 2581 RAL_LOCK(sc); 2582 if (fp == NULL) { 2583 if_printf(ifp, "%s: unable to retrieve firmware image %s\n", 2584 __func__, imagename); 2585 return EINVAL; 2586 } 2587 2588 /* 2589 * Load 8051 microcode into NIC. 2590 */ 2591 /* reset 8051 */ 2592 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2593 2594 /* cancel any pending Host to MCU command */ 2595 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2596 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2597 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2598 2599 /* write 8051's microcode */ 2600 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2601 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2602 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2603 2604 /* kick 8051's ass */ 2605 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2606 2607 /* wait for 8051 to initialize */ 2608 for (ntries = 0; ntries < 500; ntries++) { 2609 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2610 break; 2611 DELAY(100); 2612 } 2613 if (ntries == 500) { 2614 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n", 2615 __func__); 2616 error = EIO; 2617 } else 2618 error = 0; 2619 2620 firmware_put(fp, FIRMWARE_UNLOAD); 2621 return error; 2622} 2623 2624#ifdef notyet 2625/* 2626 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2627 * false CCA count. This function is called periodically (every seconds) when 2628 * in the RUN state. Values taken from the reference driver. 2629 */ 2630static void 2631rt2661_rx_tune(struct rt2661_softc *sc) 2632{ 2633 uint8_t bbp17; 2634 uint16_t cca; 2635 int lo, hi, dbm; 2636 2637 /* 2638 * Tuning range depends on operating band and on the presence of an 2639 * external low-noise amplifier. 2640 */ 2641 lo = 0x20; 2642 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2643 lo += 0x08; 2644 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2645 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2646 lo += 0x10; 2647 hi = lo + 0x20; 2648 2649 /* retrieve false CCA count since last call (clear on read) */ 2650 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2651 2652 if (dbm >= -35) { 2653 bbp17 = 0x60; 2654 } else if (dbm >= -58) { 2655 bbp17 = hi; 2656 } else if (dbm >= -66) { 2657 bbp17 = lo + 0x10; 2658 } else if (dbm >= -74) { 2659 bbp17 = lo + 0x08; 2660 } else { 2661 /* RSSI < -74dBm, tune using false CCA count */ 2662 2663 bbp17 = sc->bbp17; /* current value */ 2664 2665 hi -= 2 * (-74 - dbm); 2666 if (hi < lo) 2667 hi = lo; 2668 2669 if (bbp17 > hi) { 2670 bbp17 = hi; 2671 2672 } else if (cca > 512) { 2673 if (++bbp17 > hi) 2674 bbp17 = hi; 2675 } else if (cca < 100) { 2676 if (--bbp17 < lo) 2677 bbp17 = lo; 2678 } 2679 } 2680 2681 if (bbp17 != sc->bbp17) { 2682 rt2661_bbp_write(sc, 17, bbp17); 2683 sc->bbp17 = bbp17; 2684 } 2685} 2686 2687/* 2688 * Enter/Leave radar detection mode. 2689 * This is for 802.11h additional regulatory domains. 2690 */ 2691static void 2692rt2661_radar_start(struct rt2661_softc *sc) 2693{ 2694 uint32_t tmp; 2695 2696 /* disable Rx */ 2697 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2698 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2699 2700 rt2661_bbp_write(sc, 82, 0x20); 2701 rt2661_bbp_write(sc, 83, 0x00); 2702 rt2661_bbp_write(sc, 84, 0x40); 2703 2704 /* save current BBP registers values */ 2705 sc->bbp18 = rt2661_bbp_read(sc, 18); 2706 sc->bbp21 = rt2661_bbp_read(sc, 21); 2707 sc->bbp22 = rt2661_bbp_read(sc, 22); 2708 sc->bbp16 = rt2661_bbp_read(sc, 16); 2709 sc->bbp17 = rt2661_bbp_read(sc, 17); 2710 sc->bbp64 = rt2661_bbp_read(sc, 64); 2711 2712 rt2661_bbp_write(sc, 18, 0xff); 2713 rt2661_bbp_write(sc, 21, 0x3f); 2714 rt2661_bbp_write(sc, 22, 0x3f); 2715 rt2661_bbp_write(sc, 16, 0xbd); 2716 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2717 rt2661_bbp_write(sc, 64, 0x21); 2718 2719 /* restore Rx filter */ 2720 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2721} 2722 2723static int 2724rt2661_radar_stop(struct rt2661_softc *sc) 2725{ 2726 uint8_t bbp66; 2727 2728 /* read radar detection result */ 2729 bbp66 = rt2661_bbp_read(sc, 66); 2730 2731 /* restore BBP registers values */ 2732 rt2661_bbp_write(sc, 16, sc->bbp16); 2733 rt2661_bbp_write(sc, 17, sc->bbp17); 2734 rt2661_bbp_write(sc, 18, sc->bbp18); 2735 rt2661_bbp_write(sc, 21, sc->bbp21); 2736 rt2661_bbp_write(sc, 22, sc->bbp22); 2737 rt2661_bbp_write(sc, 64, sc->bbp64); 2738 2739 return bbp66 == 1; 2740} 2741#endif 2742 2743static int 2744rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2745{ 2746 struct ieee80211com *ic = vap->iv_ic; 2747 struct ieee80211_beacon_offsets bo; 2748 struct rt2661_tx_desc desc; 2749 struct mbuf *m0; 2750 int rate; 2751 2752 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo); 2753 if (m0 == NULL) { 2754 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2755 return ENOBUFS; 2756 } 2757 2758 /* send beacons at the lowest available rate */ 2759 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2760 2761 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2762 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2763 2764 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2765 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2766 2767 /* copy beacon header and payload into NIC memory */ 2768 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2769 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2770 2771 m_freem(m0); 2772 2773 return 0; 2774} 2775 2776/* 2777 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2778 * and HostAP operating modes. 2779 */ 2780static void 2781rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2782{ 2783 struct ifnet *ifp = sc->sc_ifp; 2784 struct ieee80211com *ic = ifp->if_l2com; 2785 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2786 uint32_t tmp; 2787 2788 if (vap->iv_opmode != IEEE80211_M_STA) { 2789 /* 2790 * Change default 16ms TBTT adjustment to 8ms. 2791 * Must be done before enabling beacon generation. 2792 */ 2793 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2794 } 2795 2796 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2797 2798 /* set beacon interval (in 1/16ms unit) */ 2799 tmp |= vap->iv_bss->ni_intval * 16; 2800 2801 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2802 if (vap->iv_opmode == IEEE80211_M_STA) 2803 tmp |= RT2661_TSF_MODE(1); 2804 else 2805 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2806 2807 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2808} 2809 2810/* 2811 * Retrieve the "Received Signal Strength Indicator" from the raw values 2812 * contained in Rx descriptors. The computation depends on which band the 2813 * frame was received. Correction values taken from the reference driver. 2814 */ 2815static int 2816rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2817{ 2818 int lna, agc, rssi; 2819 2820 lna = (raw >> 5) & 0x3; 2821 agc = raw & 0x1f; 2822 2823 if (lna == 0) { 2824 /* 2825 * No mapping available. 2826 * 2827 * NB: Since RSSI is relative to noise floor, -1 is 2828 * adequate for caller to know error happened. 2829 */ 2830 return -1; 2831 } 2832 2833 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2834 2835 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2836 rssi += sc->rssi_2ghz_corr; 2837 2838 if (lna == 1) 2839 rssi -= 64; 2840 else if (lna == 2) 2841 rssi -= 74; 2842 else if (lna == 3) 2843 rssi -= 90; 2844 } else { 2845 rssi += sc->rssi_5ghz_corr; 2846 2847 if (lna == 1) 2848 rssi -= 64; 2849 else if (lna == 2) 2850 rssi -= 86; 2851 else if (lna == 3) 2852 rssi -= 100; 2853 } 2854 return rssi; 2855} 2856 2857static void 2858rt2661_scan_start(struct ieee80211com *ic) 2859{ 2860 struct ifnet *ifp = ic->ic_ifp; 2861 struct rt2661_softc *sc = ifp->if_softc; 2862 uint32_t tmp; 2863 2864 /* abort TSF synchronization */ 2865 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2866 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2867 rt2661_set_bssid(sc, ifp->if_broadcastaddr); 2868} 2869 2870static void 2871rt2661_scan_end(struct ieee80211com *ic) 2872{ 2873 struct ifnet *ifp = ic->ic_ifp; 2874 struct rt2661_softc *sc = ifp->if_softc; 2875 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2876 2877 rt2661_enable_tsf_sync(sc); 2878 /* XXX keep local copy */ 2879 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2880} 2881 2882static void 2883rt2661_set_channel(struct ieee80211com *ic) 2884{ 2885 struct ifnet *ifp = ic->ic_ifp; 2886 struct rt2661_softc *sc = ifp->if_softc; 2887 2888 RAL_LOCK(sc); 2889 rt2661_set_chan(sc, ic->ic_curchan); 2890 2891 sc->sc_txtap.wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2892 sc->sc_txtap.wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2893 sc->sc_rxtap.wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2894 sc->sc_rxtap.wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2895 RAL_UNLOCK(sc); 2896 2897} 2898