rt2661.c revision 158651
1/* $FreeBSD: head/sys/dev/ral/rt2661.c 158651 2006-05-16 14:37:58Z phk $ */ 2 3/*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2661.c 158651 2006-05-16 14:37:58Z phk $"); 22 23/*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39 40#include <machine/bus.h> 41#include <machine/resource.h> 42#include <sys/rman.h> 43 44#include <net/bpf.h> 45#include <net/if.h> 46#include <net/if_arp.h> 47#include <net/ethernet.h> 48#include <net/if_dl.h> 49#include <net/if_media.h> 50#include <net/if_types.h> 51 52#include <net80211/ieee80211_var.h> 53#include <net80211/ieee80211_radiotap.h> 54 55#include <netinet/in.h> 56#include <netinet/in_systm.h> 57#include <netinet/in_var.h> 58#include <netinet/ip.h> 59#include <netinet/if_ether.h> 60 61#include <dev/ral/if_ralrate.h> 62#include <dev/ral/rt2661reg.h> 63#include <dev/ral/rt2661var.h> 64#include <dev/ral/rt2661_ucode.h> 65 66#ifdef RAL_DEBUG 67#define DPRINTF(x) do { if (ral_debug > 0) printf x; } while (0) 68#define DPRINTFN(n, x) do { if (ral_debug >= (n)) printf x; } while (0) 69int ral_debug = 0; 70SYSCTL_INT(_debug, OID_AUTO, ral, CTLFLAG_RW, &ral_debug, 0, "ral debug level"); 71#else 72#define DPRINTF(x) 73#define DPRINTFN(n, x) 74#endif 75 76static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 77 int); 78static int rt2661_alloc_tx_ring(struct rt2661_softc *, 79 struct rt2661_tx_ring *, int); 80static void rt2661_reset_tx_ring(struct rt2661_softc *, 81 struct rt2661_tx_ring *); 82static void rt2661_free_tx_ring(struct rt2661_softc *, 83 struct rt2661_tx_ring *); 84static int rt2661_alloc_rx_ring(struct rt2661_softc *, 85 struct rt2661_rx_ring *, int); 86static void rt2661_reset_rx_ring(struct rt2661_softc *, 87 struct rt2661_rx_ring *); 88static void rt2661_free_rx_ring(struct rt2661_softc *, 89 struct rt2661_rx_ring *); 90static struct ieee80211_node *rt2661_node_alloc( 91 struct ieee80211_node_table *); 92static int rt2661_media_change(struct ifnet *); 93static void rt2661_next_scan(void *); 94static int rt2661_newstate(struct ieee80211com *, 95 enum ieee80211_state, int); 96static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 97static void rt2661_rx_intr(struct rt2661_softc *); 98static void rt2661_tx_intr(struct rt2661_softc *); 99static void rt2661_tx_dma_intr(struct rt2661_softc *, 100 struct rt2661_tx_ring *); 101static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 102static void rt2661_mcu_wakeup(struct rt2661_softc *); 103static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 104static int rt2661_ack_rate(struct ieee80211com *, int); 105static uint16_t rt2661_txtime(int, int, uint32_t); 106static uint8_t rt2661_rxrate(struct rt2661_rx_desc *); 107static uint8_t rt2661_plcp_signal(int); 108static void rt2661_setup_tx_desc(struct rt2661_softc *, 109 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 110 int, const bus_dma_segment_t *, int, int); 111static struct mbuf * rt2661_get_rts(struct rt2661_softc *, 112 struct ieee80211_frame *, uint16_t); 113static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 114 struct ieee80211_node *, int); 115static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 116 struct ieee80211_node *); 117static void rt2661_start(struct ifnet *); 118static void rt2661_watchdog(struct ifnet *); 119static int rt2661_reset(struct ifnet *); 120static int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 121static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 122 uint8_t); 123static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 124static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 125 uint32_t); 126static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 127 uint16_t); 128static void rt2661_select_antenna(struct rt2661_softc *); 129static void rt2661_enable_mrr(struct rt2661_softc *); 130static void rt2661_set_txpreamble(struct rt2661_softc *); 131static void rt2661_set_basicrates(struct rt2661_softc *, 132 const struct ieee80211_rateset *); 133static void rt2661_select_band(struct rt2661_softc *, 134 struct ieee80211_channel *); 135static void rt2661_set_chan(struct rt2661_softc *, 136 struct ieee80211_channel *); 137static void rt2661_set_bssid(struct rt2661_softc *, 138 const uint8_t *); 139static void rt2661_set_macaddr(struct rt2661_softc *, 140 const uint8_t *); 141static void rt2661_update_promisc(struct rt2661_softc *); 142static int rt2661_wme_update(struct ieee80211com *) __unused; 143static void rt2661_update_slot(struct ifnet *); 144static const char *rt2661_get_rf(int); 145static void rt2661_read_eeprom(struct rt2661_softc *); 146static int rt2661_bbp_init(struct rt2661_softc *); 147static void rt2661_init(void *); 148static void rt2661_stop(void *); 149static int rt2661_load_microcode(struct rt2661_softc *, 150 const uint8_t *, int); 151#ifdef notyet 152static void rt2661_rx_tune(struct rt2661_softc *); 153static void rt2661_radar_start(struct rt2661_softc *); 154static int rt2661_radar_stop(struct rt2661_softc *); 155#endif 156static int rt2661_prepare_beacon(struct rt2661_softc *); 157static void rt2661_enable_tsf_sync(struct rt2661_softc *); 158static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 159 160/* 161 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 162 */ 163static const struct ieee80211_rateset rt2661_rateset_11a = 164 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 165 166static const struct ieee80211_rateset rt2661_rateset_11b = 167 { 4, { 2, 4, 11, 22 } }; 168 169static const struct ieee80211_rateset rt2661_rateset_11g = 170 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 171 172static const struct { 173 uint32_t reg; 174 uint32_t val; 175} rt2661_def_mac[] = { 176 RT2661_DEF_MAC 177}; 178 179static const struct { 180 uint8_t reg; 181 uint8_t val; 182} rt2661_def_bbp[] = { 183 RT2661_DEF_BBP 184}; 185 186static const struct rfprog { 187 uint8_t chan; 188 uint32_t r1, r2, r3, r4; 189} rt2661_rf5225_1[] = { 190 RT2661_RF5225_1 191}, rt2661_rf5225_2[] = { 192 RT2661_RF5225_2 193}; 194 195int 196rt2661_attach(device_t dev, int id) 197{ 198 struct rt2661_softc *sc = device_get_softc(dev); 199 struct ieee80211com *ic = &sc->sc_ic; 200 struct ifnet *ifp; 201 uint32_t val; 202 const uint8_t *ucode = NULL; 203 int error, i, ac, ntries, size = 0; 204 205 sc->sc_dev = dev; 206 207 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 208 MTX_DEF | MTX_RECURSE); 209 210 callout_init(&sc->scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 211 callout_init(&sc->rssadapt_ch, CALLOUT_MPSAFE); 212 213 /* wait for NIC to initialize */ 214 for (ntries = 0; ntries < 1000; ntries++) { 215 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 216 break; 217 DELAY(1000); 218 } 219 if (ntries == 1000) { 220 device_printf(sc->sc_dev, 221 "timeout waiting for NIC to initialize\n"); 222 error = EIO; 223 goto fail1; 224 } 225 226 /* retrieve RF rev. no and various other things from EEPROM */ 227 rt2661_read_eeprom(sc); 228 229 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 230 rt2661_get_rf(sc->rf_rev)); 231 232 /* 233 * Load 8051 microcode into NIC. 234 */ 235 switch (id) { 236 case 0x0301: 237 ucode = rt2561s_ucode; 238 size = sizeof rt2561s_ucode; 239 break; 240 case 0x0302: 241 ucode = rt2561_ucode; 242 size = sizeof rt2561_ucode; 243 break; 244 case 0x0401: 245 ucode = rt2661_ucode; 246 size = sizeof rt2661_ucode; 247 break; 248 } 249 250 error = rt2661_load_microcode(sc, ucode, size); 251 if (error != 0) { 252 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 253 goto fail1; 254 } 255 256 /* 257 * Allocate Tx and Rx rings. 258 */ 259 for (ac = 0; ac < 4; ac++) { 260 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 261 RT2661_TX_RING_COUNT); 262 if (error != 0) { 263 device_printf(sc->sc_dev, 264 "could not allocate Tx ring %d\n", ac); 265 goto fail2; 266 } 267 } 268 269 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 270 if (error != 0) { 271 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 272 goto fail2; 273 } 274 275 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 276 if (error != 0) { 277 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 278 goto fail3; 279 } 280 281 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 282 if (ifp == NULL) { 283 device_printf(sc->sc_dev, "can not if_alloc()\n"); 284 error = ENOMEM; 285 goto fail4; 286 } 287 288 ifp->if_softc = sc; 289 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 290 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 291 ifp->if_init = rt2661_init; 292 ifp->if_ioctl = rt2661_ioctl; 293 ifp->if_start = rt2661_start; 294 ifp->if_watchdog = rt2661_watchdog; 295 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 296 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 297 IFQ_SET_READY(&ifp->if_snd); 298 299 ic->ic_ifp = ifp; 300 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 301 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 302 ic->ic_state = IEEE80211_S_INIT; 303 304 /* set device capabilities */ 305 ic->ic_caps = 306 IEEE80211_C_IBSS | /* IBSS mode supported */ 307 IEEE80211_C_MONITOR | /* monitor mode supported */ 308 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 309 IEEE80211_C_TXPMGT | /* tx power management */ 310 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 311 IEEE80211_C_SHSLOT | /* short slot time supported */ 312#ifdef notyet 313 IEEE80211_C_WME | /* 802.11e */ 314#endif 315 IEEE80211_C_WPA; /* 802.11i */ 316 317 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 318 /* set supported .11a rates */ 319 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2661_rateset_11a; 320 321 /* set supported .11a channels */ 322 for (i = 36; i <= 64; i += 4) { 323 ic->ic_channels[i].ic_freq = 324 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 325 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 326 } 327 for (i = 100; i <= 140; i += 4) { 328 ic->ic_channels[i].ic_freq = 329 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 330 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 331 } 332 for (i = 149; i <= 165; i += 4) { 333 ic->ic_channels[i].ic_freq = 334 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 335 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; 336 } 337 } 338 339 /* set supported .11b and .11g rates */ 340 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2661_rateset_11b; 341 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2661_rateset_11g; 342 343 /* set supported .11b and .11g channels (1 through 14) */ 344 for (i = 1; i <= 14; i++) { 345 ic->ic_channels[i].ic_freq = 346 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 347 ic->ic_channels[i].ic_flags = 348 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 349 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 350 } 351 352 ieee80211_ifattach(ic); 353 ic->ic_node_alloc = rt2661_node_alloc; 354/* ic->ic_wme.wme_update = rt2661_wme_update;*/ 355 ic->ic_updateslot = rt2661_update_slot; 356 ic->ic_reset = rt2661_reset; 357 /* enable s/w bmiss handling in sta mode */ 358 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; 359 360 /* override state transition machine */ 361 sc->sc_newstate = ic->ic_newstate; 362 ic->ic_newstate = rt2661_newstate; 363 ieee80211_media_init(ic, rt2661_media_change, ieee80211_media_status); 364 365 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 366 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 367 368 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 369 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 370 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 371 372 sc->sc_txtap_len = sizeof sc->sc_txtapu; 373 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 374 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 375 376 /* 377 * Add a few sysctl knobs. 378 */ 379 sc->dwelltime = 200; 380 381 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 382 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", 383 CTLFLAG_RW, &sc->dwelltime, 0, 384 "channel dwell time (ms) for AP/station scanning"); 385 386 if (bootverbose) 387 ieee80211_announce(ic); 388 389 return 0; 390 391fail4: rt2661_free_rx_ring(sc, &sc->rxq); 392fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 393fail2: while (--ac >= 0) 394 rt2661_free_tx_ring(sc, &sc->txq[ac]); 395fail1: mtx_destroy(&sc->sc_mtx); 396 397 return error; 398} 399 400int 401rt2661_detach(void *xsc) 402{ 403 struct rt2661_softc *sc = xsc; 404 struct ieee80211com *ic = &sc->sc_ic; 405 struct ifnet *ifp = ic->ic_ifp; 406 407 rt2661_stop(sc); 408 callout_stop(&sc->scan_ch); 409 callout_stop(&sc->rssadapt_ch); 410 411 bpfdetach(ifp); 412 ieee80211_ifdetach(ic); 413 414 rt2661_free_tx_ring(sc, &sc->txq[0]); 415 rt2661_free_tx_ring(sc, &sc->txq[1]); 416 rt2661_free_tx_ring(sc, &sc->txq[2]); 417 rt2661_free_tx_ring(sc, &sc->txq[3]); 418 rt2661_free_tx_ring(sc, &sc->mgtq); 419 rt2661_free_rx_ring(sc, &sc->rxq); 420 421 if_free(ifp); 422 423 mtx_destroy(&sc->sc_mtx); 424 425 return 0; 426} 427 428void 429rt2661_shutdown(void *xsc) 430{ 431 struct rt2661_softc *sc = xsc; 432 433 rt2661_stop(sc); 434} 435 436void 437rt2661_suspend(void *xsc) 438{ 439 struct rt2661_softc *sc = xsc; 440 441 rt2661_stop(sc); 442} 443 444void 445rt2661_resume(void *xsc) 446{ 447 struct rt2661_softc *sc = xsc; 448 struct ifnet *ifp = sc->sc_ic.ic_ifp; 449 450 if (ifp->if_flags & IFF_UP) { 451 ifp->if_init(ifp->if_softc); 452 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 453 ifp->if_start(ifp); 454 } 455} 456 457static void 458rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 459{ 460 if (error != 0) 461 return; 462 463 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 464 465 *(bus_addr_t *)arg = segs[0].ds_addr; 466} 467 468static int 469rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 470 int count) 471{ 472 int i, error; 473 474 ring->count = count; 475 ring->queued = 0; 476 ring->cur = ring->next = ring->stat = 0; 477 478 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 479 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_TX_DESC_SIZE, 1, 480 count * RT2661_TX_DESC_SIZE, 0, NULL, NULL, &ring->desc_dmat); 481 if (error != 0) { 482 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 483 goto fail; 484 } 485 486 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 487 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 488 if (error != 0) { 489 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 490 goto fail; 491 } 492 493 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 494 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 495 0); 496 if (error != 0) { 497 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 498 goto fail; 499 } 500 501 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 502 M_NOWAIT | M_ZERO); 503 if (ring->data == NULL) { 504 device_printf(sc->sc_dev, "could not allocate soft data\n"); 505 error = ENOMEM; 506 goto fail; 507 } 508 509 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 510 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, RT2661_MAX_SCATTER, 511 MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 512 if (error != 0) { 513 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 514 goto fail; 515 } 516 517 for (i = 0; i < count; i++) { 518 error = bus_dmamap_create(ring->data_dmat, 0, 519 &ring->data[i].map); 520 if (error != 0) { 521 device_printf(sc->sc_dev, "could not create DMA map\n"); 522 goto fail; 523 } 524 } 525 526 return 0; 527 528fail: rt2661_free_tx_ring(sc, ring); 529 return error; 530} 531 532static void 533rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 534{ 535 struct rt2661_tx_desc *desc; 536 struct rt2661_tx_data *data; 537 int i; 538 539 for (i = 0; i < ring->count; i++) { 540 desc = &ring->desc[i]; 541 data = &ring->data[i]; 542 543 if (data->m != NULL) { 544 bus_dmamap_sync(ring->data_dmat, data->map, 545 BUS_DMASYNC_POSTWRITE); 546 bus_dmamap_unload(ring->data_dmat, data->map); 547 m_freem(data->m); 548 data->m = NULL; 549 } 550 551 if (data->ni != NULL) { 552 ieee80211_free_node(data->ni); 553 data->ni = NULL; 554 } 555 556 desc->flags = 0; 557 } 558 559 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 560 561 ring->queued = 0; 562 ring->cur = ring->next = ring->stat = 0; 563} 564 565static void 566rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 567{ 568 struct rt2661_tx_data *data; 569 int i; 570 571 if (ring->desc != NULL) { 572 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 573 BUS_DMASYNC_POSTWRITE); 574 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 575 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 576 } 577 578 if (ring->desc_dmat != NULL) 579 bus_dma_tag_destroy(ring->desc_dmat); 580 581 if (ring->data != NULL) { 582 for (i = 0; i < ring->count; i++) { 583 data = &ring->data[i]; 584 585 if (data->m != NULL) { 586 bus_dmamap_sync(ring->data_dmat, data->map, 587 BUS_DMASYNC_POSTWRITE); 588 bus_dmamap_unload(ring->data_dmat, data->map); 589 m_freem(data->m); 590 } 591 592 if (data->ni != NULL) 593 ieee80211_free_node(data->ni); 594 595 if (data->map != NULL) 596 bus_dmamap_destroy(ring->data_dmat, data->map); 597 } 598 599 free(ring->data, M_DEVBUF); 600 } 601 602 if (ring->data_dmat != NULL) 603 bus_dma_tag_destroy(ring->data_dmat); 604} 605 606static int 607rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 608 int count) 609{ 610 struct rt2661_rx_desc *desc; 611 struct rt2661_rx_data *data; 612 bus_addr_t physaddr; 613 int i, error; 614 615 ring->count = count; 616 ring->cur = ring->next = 0; 617 618 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 619 BUS_SPACE_MAXADDR, NULL, NULL, count * RT2661_RX_DESC_SIZE, 1, 620 count * RT2661_RX_DESC_SIZE, 0, NULL, NULL, &ring->desc_dmat); 621 if (error != 0) { 622 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 623 goto fail; 624 } 625 626 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 627 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 628 if (error != 0) { 629 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 630 goto fail; 631 } 632 633 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 634 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 635 0); 636 if (error != 0) { 637 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 638 goto fail; 639 } 640 641 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 642 M_NOWAIT | M_ZERO); 643 if (ring->data == NULL) { 644 device_printf(sc->sc_dev, "could not allocate soft data\n"); 645 error = ENOMEM; 646 goto fail; 647 } 648 649 /* 650 * Pre-allocate Rx buffers and populate Rx ring. 651 */ 652 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 653 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, 654 NULL, &ring->data_dmat); 655 if (error != 0) { 656 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 657 goto fail; 658 } 659 660 for (i = 0; i < count; i++) { 661 desc = &sc->rxq.desc[i]; 662 data = &sc->rxq.data[i]; 663 664 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 665 if (error != 0) { 666 device_printf(sc->sc_dev, "could not create DMA map\n"); 667 goto fail; 668 } 669 670 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 671 if (data->m == NULL) { 672 device_printf(sc->sc_dev, 673 "could not allocate rx mbuf\n"); 674 error = ENOMEM; 675 goto fail; 676 } 677 678 error = bus_dmamap_load(ring->data_dmat, data->map, 679 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 680 &physaddr, 0); 681 if (error != 0) { 682 device_printf(sc->sc_dev, 683 "could not load rx buf DMA map"); 684 goto fail; 685 } 686 687 desc->flags = htole32(RT2661_RX_BUSY); 688 desc->physaddr = htole32(physaddr); 689 } 690 691 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 692 693 return 0; 694 695fail: rt2661_free_rx_ring(sc, ring); 696 return error; 697} 698 699static void 700rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 701{ 702 int i; 703 704 for (i = 0; i < ring->count; i++) 705 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 706 707 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 708 709 ring->cur = ring->next = 0; 710} 711 712static void 713rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 714{ 715 struct rt2661_rx_data *data; 716 int i; 717 718 if (ring->desc != NULL) { 719 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 720 BUS_DMASYNC_POSTWRITE); 721 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 722 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 723 } 724 725 if (ring->desc_dmat != NULL) 726 bus_dma_tag_destroy(ring->desc_dmat); 727 728 if (ring->data != NULL) { 729 for (i = 0; i < ring->count; i++) { 730 data = &ring->data[i]; 731 732 if (data->m != NULL) { 733 bus_dmamap_sync(ring->data_dmat, data->map, 734 BUS_DMASYNC_POSTREAD); 735 bus_dmamap_unload(ring->data_dmat, data->map); 736 m_freem(data->m); 737 } 738 739 if (data->map != NULL) 740 bus_dmamap_destroy(ring->data_dmat, data->map); 741 } 742 743 free(ring->data, M_DEVBUF); 744 } 745 746 if (ring->data_dmat != NULL) 747 bus_dma_tag_destroy(ring->data_dmat); 748} 749 750static struct ieee80211_node * 751rt2661_node_alloc(struct ieee80211_node_table *nt) 752{ 753 struct rt2661_node *rn; 754 755 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 756 M_NOWAIT | M_ZERO); 757 758 return (rn != NULL) ? &rn->ni : NULL; 759} 760 761static int 762rt2661_media_change(struct ifnet *ifp) 763{ 764 struct rt2661_softc *sc = ifp->if_softc; 765 int error; 766 767 error = ieee80211_media_change(ifp); 768 if (error != ENETRESET) 769 return error; 770 771 if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 772 rt2661_init(sc); 773 774 return 0; 775} 776 777/* 778 * This function is called periodically (every 200ms) during scanning to 779 * switch from one channel to another. 780 */ 781static void 782rt2661_next_scan(void *arg) 783{ 784 struct rt2661_softc *sc = arg; 785 struct ieee80211com *ic = &sc->sc_ic; 786 787 if (ic->ic_state == IEEE80211_S_SCAN) 788 ieee80211_next_scan(ic); 789} 790 791/* 792 * This function is called for each node present in the node station table. 793 */ 794static void 795rt2661_iter_func(void *arg, struct ieee80211_node *ni) 796{ 797 struct rt2661_node *rn = (struct rt2661_node *)ni; 798 799 ral_rssadapt_updatestats(&rn->rssadapt); 800} 801 802/* 803 * This function is called periodically (every 100ms) in RUN state to update 804 * the rate adaptation statistics. 805 */ 806static void 807rt2661_update_rssadapt(void *arg) 808{ 809 struct rt2661_softc *sc = arg; 810 struct ieee80211com *ic = &sc->sc_ic; 811 812 RAL_LOCK(sc); 813 814 ieee80211_iterate_nodes(&ic->ic_sta, rt2661_iter_func, arg); 815 callout_reset(&sc->rssadapt_ch, hz / 10, rt2661_update_rssadapt, sc); 816 817 RAL_UNLOCK(sc); 818} 819 820static int 821rt2661_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 822{ 823 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 824 enum ieee80211_state ostate; 825 struct ieee80211_node *ni; 826 uint32_t tmp; 827 int error = 0; 828 829 ostate = ic->ic_state; 830 callout_stop(&sc->scan_ch); 831 832 switch (nstate) { 833 case IEEE80211_S_INIT: 834 callout_stop(&sc->rssadapt_ch); 835 836 if (ostate == IEEE80211_S_RUN) { 837 /* abort TSF synchronization */ 838 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 839 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 840 } 841 break; 842 843 case IEEE80211_S_SCAN: 844 rt2661_set_chan(sc, ic->ic_curchan); 845 callout_reset(&sc->scan_ch, (sc->dwelltime * hz) / 1000, 846 rt2661_next_scan, sc); 847 break; 848 849 case IEEE80211_S_AUTH: 850 case IEEE80211_S_ASSOC: 851 rt2661_set_chan(sc, ic->ic_curchan); 852 break; 853 854 case IEEE80211_S_RUN: 855 rt2661_set_chan(sc, ic->ic_curchan); 856 857 ni = ic->ic_bss; 858 859 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 860 rt2661_enable_mrr(sc); 861 rt2661_set_txpreamble(sc); 862 rt2661_set_basicrates(sc, &ni->ni_rates); 863 rt2661_set_bssid(sc, ni->ni_bssid); 864 } 865 866 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 867 ic->ic_opmode == IEEE80211_M_IBSS) { 868 if ((error = rt2661_prepare_beacon(sc)) != 0) 869 break; 870 } 871 872 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 873 callout_reset(&sc->rssadapt_ch, hz / 10, 874 rt2661_update_rssadapt, sc); 875 rt2661_enable_tsf_sync(sc); 876 } 877 break; 878 } 879 880 return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); 881} 882 883/* 884 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 885 * 93C66). 886 */ 887static uint16_t 888rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 889{ 890 uint32_t tmp; 891 uint16_t val; 892 int n; 893 894 /* clock C once before the first command */ 895 RT2661_EEPROM_CTL(sc, 0); 896 897 RT2661_EEPROM_CTL(sc, RT2661_S); 898 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 899 RT2661_EEPROM_CTL(sc, RT2661_S); 900 901 /* write start bit (1) */ 902 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 903 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 904 905 /* write READ opcode (10) */ 906 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 907 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 908 RT2661_EEPROM_CTL(sc, RT2661_S); 909 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 910 911 /* write address (A5-A0 or A7-A0) */ 912 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 913 for (; n >= 0; n--) { 914 RT2661_EEPROM_CTL(sc, RT2661_S | 915 (((addr >> n) & 1) << RT2661_SHIFT_D)); 916 RT2661_EEPROM_CTL(sc, RT2661_S | 917 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 918 } 919 920 RT2661_EEPROM_CTL(sc, RT2661_S); 921 922 /* read data Q15-Q0 */ 923 val = 0; 924 for (n = 15; n >= 0; n--) { 925 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 926 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 927 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 928 RT2661_EEPROM_CTL(sc, RT2661_S); 929 } 930 931 RT2661_EEPROM_CTL(sc, 0); 932 933 /* clear Chip Select and clock C */ 934 RT2661_EEPROM_CTL(sc, RT2661_S); 935 RT2661_EEPROM_CTL(sc, 0); 936 RT2661_EEPROM_CTL(sc, RT2661_C); 937 938 return val; 939} 940 941static void 942rt2661_tx_intr(struct rt2661_softc *sc) 943{ 944 struct ieee80211com *ic = &sc->sc_ic; 945 struct ifnet *ifp = ic->ic_ifp; 946 struct rt2661_tx_ring *txq; 947 struct rt2661_tx_data *data; 948 struct rt2661_node *rn; 949 uint32_t val; 950 int qid, retrycnt; 951 952 for (;;) { 953 val = RAL_READ(sc, RT2661_STA_CSR4); 954 if (!(val & RT2661_TX_STAT_VALID)) 955 break; 956 957 /* retrieve the queue in which this frame was sent */ 958 qid = RT2661_TX_QID(val); 959 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 960 961 /* retrieve rate control algorithm context */ 962 data = &txq->data[txq->stat]; 963 rn = (struct rt2661_node *)data->ni; 964 965 switch (RT2661_TX_RESULT(val)) { 966 case RT2661_TX_SUCCESS: 967 retrycnt = RT2661_TX_RETRYCNT(val); 968 969 DPRINTFN(10, ("data frame sent successfully after " 970 "%d retries\n", retrycnt)); 971 if (retrycnt == 0 && data->id.id_node != NULL) { 972 ral_rssadapt_raise_rate(ic, &rn->rssadapt, 973 &data->id); 974 } 975 ifp->if_opackets++; 976 break; 977 978 case RT2661_TX_RETRY_FAIL: 979 DPRINTFN(9, ("sending data frame failed (too much " 980 "retries)\n")); 981 if (data->id.id_node != NULL) { 982 ral_rssadapt_lower_rate(ic, data->ni, 983 &rn->rssadapt, &data->id); 984 } 985 ifp->if_oerrors++; 986 break; 987 988 default: 989 /* other failure */ 990 device_printf(sc->sc_dev, 991 "sending data frame failed 0x%08x\n", val); 992 ifp->if_oerrors++; 993 } 994 995 ieee80211_free_node(data->ni); 996 data->ni = NULL; 997 998 DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat)); 999 1000 txq->queued--; 1001 if (++txq->stat >= txq->count) /* faster than % count */ 1002 txq->stat = 0; 1003 } 1004 1005 sc->sc_tx_timer = 0; 1006 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1007 rt2661_start(ifp); 1008} 1009 1010static void 1011rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 1012{ 1013 struct rt2661_tx_desc *desc; 1014 struct rt2661_tx_data *data; 1015 1016 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 1017 1018 for (;;) { 1019 desc = &txq->desc[txq->next]; 1020 data = &txq->data[txq->next]; 1021 1022 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 1023 !(le32toh(desc->flags) & RT2661_TX_VALID)) 1024 break; 1025 1026 bus_dmamap_sync(txq->data_dmat, data->map, 1027 BUS_DMASYNC_POSTWRITE); 1028 bus_dmamap_unload(txq->data_dmat, data->map); 1029 m_freem(data->m); 1030 data->m = NULL; 1031 /* node reference is released in rt2661_tx_intr() */ 1032 1033 /* descriptor is no longer valid */ 1034 desc->flags &= ~htole32(RT2661_TX_VALID); 1035 1036 DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next)); 1037 1038 if (++txq->next >= txq->count) /* faster than % count */ 1039 txq->next = 0; 1040 } 1041 1042 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1043} 1044 1045static void 1046rt2661_rx_intr(struct rt2661_softc *sc) 1047{ 1048 struct ieee80211com *ic = &sc->sc_ic; 1049 struct ifnet *ifp = ic->ic_ifp; 1050 struct rt2661_rx_desc *desc; 1051 struct rt2661_rx_data *data; 1052 bus_addr_t physaddr; 1053 struct ieee80211_frame *wh; 1054 struct ieee80211_node *ni; 1055 struct rt2661_node *rn; 1056 struct mbuf *mnew, *m; 1057 int error; 1058 1059 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1060 BUS_DMASYNC_POSTREAD); 1061 1062 for (;;) { 1063 desc = &sc->rxq.desc[sc->rxq.cur]; 1064 data = &sc->rxq.data[sc->rxq.cur]; 1065 1066 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1067 break; 1068 1069 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1070 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1071 /* 1072 * This should not happen since we did not request 1073 * to receive those frames when we filled TXRX_CSR0. 1074 */ 1075 DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", 1076 le32toh(desc->flags))); 1077 ifp->if_ierrors++; 1078 goto skip; 1079 } 1080 1081 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1082 ifp->if_ierrors++; 1083 goto skip; 1084 } 1085 1086 /* 1087 * Try to allocate a new mbuf for this ring element and load it 1088 * before processing the current mbuf. If the ring element 1089 * cannot be loaded, drop the received packet and reuse the old 1090 * mbuf. In the unlikely case that the old mbuf can't be 1091 * reloaded either, explicitly panic. 1092 */ 1093 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1094 if (mnew == NULL) { 1095 ifp->if_ierrors++; 1096 goto skip; 1097 } 1098 1099 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1100 BUS_DMASYNC_POSTREAD); 1101 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1102 1103 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1104 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1105 &physaddr, 0); 1106 if (error != 0) { 1107 m_freem(mnew); 1108 1109 /* try to reload the old mbuf */ 1110 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1111 mtod(data->m, void *), MCLBYTES, 1112 rt2661_dma_map_addr, &physaddr, 0); 1113 if (error != 0) { 1114 /* very unlikely that it will fail... */ 1115 panic("%s: could not load old rx mbuf", 1116 device_get_name(sc->sc_dev)); 1117 } 1118 ifp->if_ierrors++; 1119 goto skip; 1120 } 1121 1122 /* 1123 * New mbuf successfully loaded, update Rx ring and continue 1124 * processing. 1125 */ 1126 m = data->m; 1127 data->m = mnew; 1128 desc->physaddr = htole32(physaddr); 1129 1130 /* finalize mbuf */ 1131 m->m_pkthdr.rcvif = ifp; 1132 m->m_pkthdr.len = m->m_len = 1133 (le32toh(desc->flags) >> 16) & 0xfff; 1134 1135 if (sc->sc_drvbpf != NULL) { 1136 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1137 uint32_t tsf_lo, tsf_hi; 1138 1139 /* get timestamp (low and high 32 bits) */ 1140 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1141 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1142 1143 tap->wr_tsf = 1144 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1145 tap->wr_flags = 0; 1146 tap->wr_rate = rt2661_rxrate(desc); 1147 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1148 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1149 tap->wr_antsignal = desc->rssi; 1150 1151 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1152 } 1153 1154 wh = mtod(m, struct ieee80211_frame *); 1155 ni = ieee80211_find_rxnode(ic, 1156 (struct ieee80211_frame_min *)wh); 1157 1158 /* send the frame to the 802.11 layer */ 1159 ieee80211_input(ic, m, ni, desc->rssi, 0); 1160 1161 /* give rssi to the rate adatation algorithm */ 1162 rn = (struct rt2661_node *)ni; 1163 ral_rssadapt_input(ic, ni, &rn->rssadapt, 1164 rt2661_get_rssi(sc, desc->rssi)); 1165 1166 /* node is no longer needed */ 1167 ieee80211_free_node(ni); 1168 1169skip: desc->flags |= htole32(RT2661_RX_BUSY); 1170 1171 DPRINTFN(15, ("rx intr idx=%u\n", sc->rxq.cur)); 1172 1173 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1174 } 1175 1176 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1177 BUS_DMASYNC_PREWRITE); 1178} 1179 1180/* ARGSUSED */ 1181static void 1182rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1183{ 1184 /* do nothing */ 1185} 1186 1187static void 1188rt2661_mcu_wakeup(struct rt2661_softc *sc) 1189{ 1190 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1191 1192 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1193 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1194 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1195 1196 /* send wakeup command to MCU */ 1197 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1198} 1199 1200static void 1201rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1202{ 1203 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1204 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1205} 1206 1207void 1208rt2661_intr(void *arg) 1209{ 1210 struct rt2661_softc *sc = arg; 1211 struct ifnet *ifp = sc->sc_ifp; 1212 uint32_t r1, r2; 1213 1214 RAL_LOCK(sc); 1215 1216 /* disable MAC and MCU interrupts */ 1217 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1218 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1219 1220 /* don't re-enable interrupts if we're shutting down */ 1221 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1222 RAL_UNLOCK(sc); 1223 return; 1224 } 1225 1226 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1227 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1228 1229 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1230 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1231 1232 if (r1 & RT2661_MGT_DONE) 1233 rt2661_tx_dma_intr(sc, &sc->mgtq); 1234 1235 if (r1 & RT2661_RX_DONE) 1236 rt2661_rx_intr(sc); 1237 1238 if (r1 & RT2661_TX0_DMA_DONE) 1239 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1240 1241 if (r1 & RT2661_TX1_DMA_DONE) 1242 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1243 1244 if (r1 & RT2661_TX2_DMA_DONE) 1245 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1246 1247 if (r1 & RT2661_TX3_DMA_DONE) 1248 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1249 1250 if (r1 & RT2661_TX_DONE) 1251 rt2661_tx_intr(sc); 1252 1253 if (r2 & RT2661_MCU_CMD_DONE) 1254 rt2661_mcu_cmd_intr(sc); 1255 1256 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1257 rt2661_mcu_beacon_expire(sc); 1258 1259 if (r2 & RT2661_MCU_WAKEUP) 1260 rt2661_mcu_wakeup(sc); 1261 1262 /* re-enable MAC and MCU interrupts */ 1263 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1264 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1265 1266 RAL_UNLOCK(sc); 1267} 1268 1269/* quickly determine if a given rate is CCK or OFDM */ 1270#define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 1271 1272#define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 1273#define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 1274 1275#define RAL_SIFS 10 /* us */ 1276 1277/* 1278 * This function is only used by the Rx radiotap code. It returns the rate at 1279 * which a given frame was received. 1280 */ 1281static uint8_t 1282rt2661_rxrate(struct rt2661_rx_desc *desc) 1283{ 1284 if (le32toh(desc->flags) & RT2661_RX_OFDM) { 1285 /* reverse function of rt2661_plcp_signal */ 1286 switch (desc->rate & 0xf) { 1287 case 0xb: return 12; 1288 case 0xf: return 18; 1289 case 0xa: return 24; 1290 case 0xe: return 36; 1291 case 0x9: return 48; 1292 case 0xd: return 72; 1293 case 0x8: return 96; 1294 case 0xc: return 108; 1295 } 1296 } else { 1297 if (desc->rate == 10) 1298 return 2; 1299 if (desc->rate == 20) 1300 return 4; 1301 if (desc->rate == 55) 1302 return 11; 1303 if (desc->rate == 110) 1304 return 22; 1305 } 1306 return 2; /* should not get there */ 1307} 1308 1309/* 1310 * Return the expected ack rate for a frame transmitted at rate `rate'. 1311 * XXX: this should depend on the destination node basic rate set. 1312 */ 1313static int 1314rt2661_ack_rate(struct ieee80211com *ic, int rate) 1315{ 1316 switch (rate) { 1317 /* CCK rates */ 1318 case 2: 1319 return 2; 1320 case 4: 1321 case 11: 1322 case 22: 1323 return (ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate; 1324 1325 /* OFDM rates */ 1326 case 12: 1327 case 18: 1328 return 12; 1329 case 24: 1330 case 36: 1331 return 24; 1332 case 48: 1333 case 72: 1334 case 96: 1335 case 108: 1336 return 48; 1337 } 1338 1339 /* default to 1Mbps */ 1340 return 2; 1341} 1342 1343/* 1344 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1345 * The function automatically determines the operating mode depending on the 1346 * given rate. `flags' indicates whether short preamble is in use or not. 1347 */ 1348static uint16_t 1349rt2661_txtime(int len, int rate, uint32_t flags) 1350{ 1351 uint16_t txtime; 1352 1353 if (RAL_RATE_IS_OFDM(rate)) { 1354 /* IEEE Std 802.11a-1999, pp. 37 */ 1355 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1356 txtime = 16 + 4 + 4 * txtime + 6; 1357 } else { 1358 /* IEEE Std 802.11b-1999, pp. 28 */ 1359 txtime = (16 * len + rate - 1) / rate; 1360 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1361 txtime += 72 + 24; 1362 else 1363 txtime += 144 + 48; 1364 } 1365 1366 return txtime; 1367} 1368 1369static uint8_t 1370rt2661_plcp_signal(int rate) 1371{ 1372 switch (rate) { 1373 /* CCK rates (returned values are device-dependent) */ 1374 case 2: return 0x0; 1375 case 4: return 0x1; 1376 case 11: return 0x2; 1377 case 22: return 0x3; 1378 1379 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1380 case 12: return 0xb; 1381 case 18: return 0xf; 1382 case 24: return 0xa; 1383 case 36: return 0xe; 1384 case 48: return 0x9; 1385 case 72: return 0xd; 1386 case 96: return 0x8; 1387 case 108: return 0xc; 1388 1389 /* unsupported rates (should not get there) */ 1390 default: return 0xff; 1391 } 1392} 1393 1394static void 1395rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1396 uint32_t flags, uint16_t xflags, int len, int rate, 1397 const bus_dma_segment_t *segs, int nsegs, int ac) 1398{ 1399 struct ieee80211com *ic = &sc->sc_ic; 1400 uint16_t plcp_length; 1401 int i, remainder; 1402 1403 desc->flags = htole32(flags); 1404 desc->flags |= htole32(len << 16); 1405 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1406 1407 desc->xflags = htole16(xflags); 1408 desc->xflags |= htole16(nsegs << 13); 1409 1410 desc->wme = htole16( 1411 RT2661_QID(ac) | 1412 RT2661_AIFSN(2) | 1413 RT2661_LOGCWMIN(4) | 1414 RT2661_LOGCWMAX(10)); 1415 1416 /* 1417 * Remember in which queue this frame was sent. This field is driver 1418 * private data only. It will be made available by the NIC in STA_CSR4 1419 * on Tx interrupts. 1420 */ 1421 desc->qid = ac; 1422 1423 /* setup PLCP fields */ 1424 desc->plcp_signal = rt2661_plcp_signal(rate); 1425 desc->plcp_service = 4; 1426 1427 len += IEEE80211_CRC_LEN; 1428 if (RAL_RATE_IS_OFDM(rate)) { 1429 desc->flags |= htole32(RT2661_TX_OFDM); 1430 1431 plcp_length = len & 0xfff; 1432 desc->plcp_length_hi = plcp_length >> 6; 1433 desc->plcp_length_lo = plcp_length & 0x3f; 1434 } else { 1435 plcp_length = (16 * len + rate - 1) / rate; 1436 if (rate == 22) { 1437 remainder = (16 * len) % 22; 1438 if (remainder != 0 && remainder < 7) 1439 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1440 } 1441 desc->plcp_length_hi = plcp_length >> 8; 1442 desc->plcp_length_lo = plcp_length & 0xff; 1443 1444 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1445 desc->plcp_signal |= 0x08; 1446 } 1447 1448 /* RT2x61 supports scatter with up to 5 segments */ 1449 for (i = 0; i < nsegs; i++) { 1450 desc->addr[i] = htole32(segs[i].ds_addr); 1451 desc->len [i] = htole16(segs[i].ds_len); 1452 } 1453} 1454 1455static int 1456rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1457 struct ieee80211_node *ni) 1458{ 1459 struct ieee80211com *ic = &sc->sc_ic; 1460 struct rt2661_tx_desc *desc; 1461 struct rt2661_tx_data *data; 1462 struct ieee80211_frame *wh; 1463 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1464 uint16_t dur; 1465 uint32_t flags = 0; /* XXX HWSEQ */ 1466 int nsegs, rate, error; 1467 1468 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1469 data = &sc->mgtq.data[sc->mgtq.cur]; 1470 1471 /* send mgt frames at the lowest available rate */ 1472 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1473 1474 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1475 segs, &nsegs, 0); 1476 if (error != 0) { 1477 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1478 error); 1479 m_freem(m0); 1480 return error; 1481 } 1482 1483 if (sc->sc_drvbpf != NULL) { 1484 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1485 1486 tap->wt_flags = 0; 1487 tap->wt_rate = rate; 1488 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1489 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1490 1491 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1492 } 1493 1494 data->m = m0; 1495 data->ni = ni; 1496 1497 wh = mtod(m0, struct ieee80211_frame *); 1498 1499 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1500 flags |= RT2661_TX_NEED_ACK; 1501 1502 dur = rt2661_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1503 RAL_SIFS; 1504 *(uint16_t *)wh->i_dur = htole16(dur); 1505 1506 /* tell hardware to add timestamp in probe responses */ 1507 if ((wh->i_fc[0] & 1508 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1509 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1510 flags |= RT2661_TX_TIMESTAMP; 1511 } 1512 1513 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1514 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1515 1516 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1517 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1518 BUS_DMASYNC_PREWRITE); 1519 1520 DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", 1521 m0->m_pkthdr.len, sc->mgtq.cur, rate)); 1522 1523 /* kick mgt */ 1524 sc->mgtq.queued++; 1525 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1526 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1527 1528 return 0; 1529} 1530 1531/* 1532 * Build a RTS control frame. 1533 */ 1534static struct mbuf * 1535rt2661_get_rts(struct rt2661_softc *sc, struct ieee80211_frame *wh, 1536 uint16_t dur) 1537{ 1538 struct ieee80211_frame_rts *rts; 1539 struct mbuf *m; 1540 1541 MGETHDR(m, M_DONTWAIT, MT_DATA); 1542 if (m == NULL) { 1543 sc->sc_ic.ic_stats.is_tx_nobuf++; 1544 device_printf(sc->sc_dev, "could not allocate RTS frame\n"); 1545 return NULL; 1546 } 1547 1548 rts = mtod(m, struct ieee80211_frame_rts *); 1549 1550 rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | 1551 IEEE80211_FC0_SUBTYPE_RTS; 1552 rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1553 *(uint16_t *)rts->i_dur = htole16(dur); 1554 IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); 1555 IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); 1556 1557 m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); 1558 1559 return m; 1560} 1561 1562static int 1563rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1564 struct ieee80211_node *ni, int ac) 1565{ 1566 struct ieee80211com *ic = &sc->sc_ic; 1567 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1568 struct rt2661_tx_desc *desc; 1569 struct rt2661_tx_data *data; 1570 struct rt2661_node *rn; 1571 struct ieee80211_rateset *rs; 1572 struct ieee80211_frame *wh; 1573 struct ieee80211_key *k; 1574 const struct chanAccParams *cap; 1575 struct mbuf *mnew; 1576 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1577 uint16_t dur; 1578 uint32_t flags = 0; 1579 int error, nsegs, rate, noack = 0; 1580 1581 wh = mtod(m0, struct ieee80211_frame *); 1582 1583 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1584 rs = &ic->ic_sup_rates[ic->ic_curmode]; 1585 rate = rs->rs_rates[ic->ic_fixed_rate]; 1586 } else { 1587 rs = &ni->ni_rates; 1588 rn = (struct rt2661_node *)ni; 1589 ni->ni_txrate = ral_rssadapt_choose(&rn->rssadapt, rs, 1590 wh, m0->m_pkthdr.len, NULL, 0); 1591 rate = rs->rs_rates[ni->ni_txrate]; 1592 } 1593 rate &= IEEE80211_RATE_VAL; 1594 1595 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1596 cap = &ic->ic_wme.wme_chanParams; 1597 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1598 } 1599 1600 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1601 k = ieee80211_crypto_encap(ic, ni, m0); 1602 if (k == NULL) { 1603 m_freem(m0); 1604 return ENOBUFS; 1605 } 1606 1607 /* packet header may have moved, reset our local pointer */ 1608 wh = mtod(m0, struct ieee80211_frame *); 1609 } 1610 1611 /* 1612 * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange 1613 * for directed frames only when the length of the MPDU is greater 1614 * than the length threshold indicated by [...]" ic_rtsthreshold. 1615 */ 1616 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1617 m0->m_pkthdr.len > ic->ic_rtsthreshold) { 1618 struct mbuf *m; 1619 uint16_t dur; 1620 int rtsrate, ackrate; 1621 1622 rtsrate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1623 ackrate = rt2661_ack_rate(ic, rate); 1624 1625 dur = rt2661_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + 1626 rt2661_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + 1627 /* XXX: noack (QoS)? */ 1628 rt2661_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + 1629 3 * RAL_SIFS; 1630 1631 m = rt2661_get_rts(sc, wh, dur); 1632 1633 desc = &txq->desc[txq->cur]; 1634 data = &txq->data[txq->cur]; 1635 1636 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m, 1637 segs, &nsegs, 0); 1638 if (error != 0) { 1639 device_printf(sc->sc_dev, 1640 "could not map mbuf (error %d)\n", error); 1641 m_freem(m); 1642 m_freem(m0); 1643 return error; 1644 } 1645 1646 /* avoid multiple free() of the same node for each fragment */ 1647 ieee80211_ref_node(ni); 1648 1649 data->m = m; 1650 data->ni = ni; 1651 1652 /* RTS frames are not taken into account for rssadapt */ 1653 data->id.id_node = NULL; 1654 1655 rt2661_setup_tx_desc(sc, desc, RT2661_TX_NEED_ACK | 1656 RT2661_TX_MORE_FRAG, 0, m->m_pkthdr.len, rtsrate, segs, 1657 nsegs, ac); 1658 1659 bus_dmamap_sync(txq->data_dmat, data->map, 1660 BUS_DMASYNC_PREWRITE); 1661 1662 txq->queued++; 1663 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1664 1665 /* 1666 * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the 1667 * asynchronous data frame shall be transmitted after the CTS 1668 * frame and a SIFS period. 1669 */ 1670 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1671 } 1672 1673 data = &txq->data[txq->cur]; 1674 desc = &txq->desc[txq->cur]; 1675 1676 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1677 &nsegs, 0); 1678 if (error != 0 && error != EFBIG) { 1679 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1680 error); 1681 m_freem(m0); 1682 return error; 1683 } 1684 if (error != 0) { 1685 mnew = m_defrag(m0, M_DONTWAIT); 1686 if (mnew == NULL) { 1687 device_printf(sc->sc_dev, 1688 "could not defragment mbuf\n"); 1689 m_freem(m0); 1690 return ENOBUFS; 1691 } 1692 m0 = mnew; 1693 1694 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1695 segs, &nsegs, 0); 1696 if (error != 0) { 1697 device_printf(sc->sc_dev, 1698 "could not map mbuf (error %d)\n", error); 1699 m_freem(m0); 1700 return error; 1701 } 1702 1703 /* packet header have moved, reset our local pointer */ 1704 wh = mtod(m0, struct ieee80211_frame *); 1705 } 1706 1707 if (sc->sc_drvbpf != NULL) { 1708 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1709 1710 tap->wt_flags = 0; 1711 tap->wt_rate = rate; 1712 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1713 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1714 1715 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1716 } 1717 1718 data->m = m0; 1719 data->ni = ni; 1720 1721 /* remember link conditions for rate adaptation algorithm */ 1722 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1723 data->id.id_len = m0->m_pkthdr.len; 1724 data->id.id_rateidx = ni->ni_txrate; 1725 data->id.id_node = ni; 1726 data->id.id_rssi = ni->ni_rssi; 1727 } else 1728 data->id.id_node = NULL; 1729 1730 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1731 flags |= RT2661_TX_NEED_ACK; 1732 1733 dur = rt2661_txtime(RAL_ACK_SIZE, rt2661_ack_rate(ic, rate), 1734 ic->ic_flags) + RAL_SIFS; 1735 *(uint16_t *)wh->i_dur = htole16(dur); 1736 } 1737 1738 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1739 nsegs, ac); 1740 1741 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1742 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1743 1744 DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", 1745 m0->m_pkthdr.len, txq->cur, rate)); 1746 1747 /* kick Tx */ 1748 txq->queued++; 1749 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1750 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1751 1752 return 0; 1753} 1754 1755static void 1756rt2661_start(struct ifnet *ifp) 1757{ 1758 struct rt2661_softc *sc = ifp->if_softc; 1759 struct ieee80211com *ic = &sc->sc_ic; 1760 struct mbuf *m0; 1761 struct ether_header *eh; 1762 struct ieee80211_node *ni; 1763 int ac; 1764 1765 RAL_LOCK(sc); 1766 1767 /* prevent management frames from being sent if we're not ready */ 1768 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1769 RAL_UNLOCK(sc); 1770 return; 1771 } 1772 1773 for (;;) { 1774 IF_POLL(&ic->ic_mgtq, m0); 1775 if (m0 != NULL) { 1776 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1777 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1778 break; 1779 } 1780 IF_DEQUEUE(&ic->ic_mgtq, m0); 1781 1782 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; 1783 m0->m_pkthdr.rcvif = NULL; 1784 1785 if (ic->ic_rawbpf != NULL) 1786 bpf_mtap(ic->ic_rawbpf, m0); 1787 1788 if (rt2661_tx_mgt(sc, m0, ni) != 0) 1789 break; 1790 1791 } else { 1792 if (ic->ic_state != IEEE80211_S_RUN) 1793 break; 1794 1795 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1796 if (m0 == NULL) 1797 break; 1798 1799 if (m0->m_len < sizeof (struct ether_header) && 1800 !(m0 = m_pullup(m0, sizeof (struct ether_header)))) 1801 continue; 1802 1803 eh = mtod(m0, struct ether_header *); 1804 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1805 if (ni == NULL) { 1806 m_freem(m0); 1807 ifp->if_oerrors++; 1808 continue; 1809 } 1810 1811 /* classify mbuf so we can find which tx ring to use */ 1812 if (ieee80211_classify(ic, m0, ni) != 0) { 1813 m_freem(m0); 1814 ieee80211_free_node(ni); 1815 ifp->if_oerrors++; 1816 continue; 1817 } 1818 1819 /* no QoS encapsulation for EAPOL frames */ 1820 ac = (eh->ether_type != htons(ETHERTYPE_PAE)) ? 1821 M_WME_GETAC(m0) : WME_AC_BE; 1822 1823 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1824 /* there is no place left in this ring */ 1825 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1826 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1827 break; 1828 } 1829 1830 BPF_MTAP(ifp, m0); 1831 1832 m0 = ieee80211_encap(ic, m0, ni); 1833 if (m0 == NULL) { 1834 ieee80211_free_node(ni); 1835 ifp->if_oerrors++; 1836 continue; 1837 } 1838 1839 if (ic->ic_rawbpf != NULL) 1840 bpf_mtap(ic->ic_rawbpf, m0); 1841 1842 if (rt2661_tx_data(sc, m0, ni, ac) != 0) { 1843 ieee80211_free_node(ni); 1844 ifp->if_oerrors++; 1845 break; 1846 } 1847 } 1848 1849 sc->sc_tx_timer = 5; 1850 ifp->if_timer = 1; 1851 } 1852 1853 RAL_UNLOCK(sc); 1854} 1855 1856static void 1857rt2661_watchdog(struct ifnet *ifp) 1858{ 1859 struct rt2661_softc *sc = ifp->if_softc; 1860 struct ieee80211com *ic = &sc->sc_ic; 1861 1862 RAL_LOCK(sc); 1863 1864 ifp->if_timer = 0; 1865 1866 if (sc->sc_tx_timer > 0) { 1867 if (--sc->sc_tx_timer == 0) { 1868 device_printf(sc->sc_dev, "device timeout\n"); 1869 rt2661_init(sc); 1870 ifp->if_oerrors++; 1871 RAL_UNLOCK(sc); 1872 return; 1873 } 1874 ifp->if_timer = 1; 1875 } 1876 1877 ieee80211_watchdog(ic); 1878 1879 RAL_UNLOCK(sc); 1880} 1881 1882/* 1883 * This function allows for fast channel switching in monitor mode (used by 1884 * net-mgmt/kismet). In IBSS mode, we must explicitly reset the interface to 1885 * generate a new beacon frame. 1886 */ 1887static int 1888rt2661_reset(struct ifnet *ifp) 1889{ 1890 struct rt2661_softc *sc = ifp->if_softc; 1891 struct ieee80211com *ic = &sc->sc_ic; 1892 1893 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1894 return ENETRESET; 1895 1896 rt2661_set_chan(sc, ic->ic_curchan); 1897 1898 return 0; 1899} 1900 1901static int 1902rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1903{ 1904 struct rt2661_softc *sc = ifp->if_softc; 1905 struct ieee80211com *ic = &sc->sc_ic; 1906 int error = 0; 1907 1908 RAL_LOCK(sc); 1909 1910 switch (cmd) { 1911 case SIOCSIFFLAGS: 1912 if (ifp->if_flags & IFF_UP) { 1913 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1914 rt2661_update_promisc(sc); 1915 else 1916 rt2661_init(sc); 1917 } else { 1918 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1919 rt2661_stop(sc); 1920 } 1921 break; 1922 1923 default: 1924 error = ieee80211_ioctl(ic, cmd, data); 1925 } 1926 1927 if (error == ENETRESET) { 1928 if ((ifp->if_flags & IFF_UP) && 1929 (ifp->if_drv_flags & IFF_DRV_RUNNING) && 1930 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 1931 rt2661_init(sc); 1932 error = 0; 1933 } 1934 1935 RAL_UNLOCK(sc); 1936 1937 return error; 1938} 1939 1940static void 1941rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1942{ 1943 uint32_t tmp; 1944 int ntries; 1945 1946 for (ntries = 0; ntries < 100; ntries++) { 1947 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1948 break; 1949 DELAY(1); 1950 } 1951 if (ntries == 100) { 1952 device_printf(sc->sc_dev, "could not write to BBP\n"); 1953 return; 1954 } 1955 1956 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1957 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1958 1959 DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); 1960} 1961 1962static uint8_t 1963rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1964{ 1965 uint32_t val; 1966 int ntries; 1967 1968 for (ntries = 0; ntries < 100; ntries++) { 1969 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1970 break; 1971 DELAY(1); 1972 } 1973 if (ntries == 100) { 1974 device_printf(sc->sc_dev, "could not read from BBP\n"); 1975 return 0; 1976 } 1977 1978 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1979 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1980 1981 for (ntries = 0; ntries < 100; ntries++) { 1982 val = RAL_READ(sc, RT2661_PHY_CSR3); 1983 if (!(val & RT2661_BBP_BUSY)) 1984 return val & 0xff; 1985 DELAY(1); 1986 } 1987 1988 device_printf(sc->sc_dev, "could not read from BBP\n"); 1989 return 0; 1990} 1991 1992static void 1993rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1994{ 1995 uint32_t tmp; 1996 int ntries; 1997 1998 for (ntries = 0; ntries < 100; ntries++) { 1999 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 2000 break; 2001 DELAY(1); 2002 } 2003 if (ntries == 100) { 2004 device_printf(sc->sc_dev, "could not write to RF\n"); 2005 return; 2006 } 2007 2008 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 2009 (reg & 3); 2010 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 2011 2012 /* remember last written value in sc */ 2013 sc->rf_regs[reg] = val; 2014 2015 DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff)); 2016} 2017 2018static int 2019rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 2020{ 2021 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 2022 return EIO; /* there is already a command pending */ 2023 2024 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 2025 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 2026 2027 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 2028 2029 return 0; 2030} 2031 2032static void 2033rt2661_select_antenna(struct rt2661_softc *sc) 2034{ 2035 uint8_t bbp4, bbp77; 2036 uint32_t tmp; 2037 2038 bbp4 = rt2661_bbp_read(sc, 4); 2039 bbp77 = rt2661_bbp_read(sc, 77); 2040 2041 /* TBD */ 2042 2043 /* make sure Rx is disabled before switching antenna */ 2044 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2045 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2046 2047 rt2661_bbp_write(sc, 4, bbp4); 2048 rt2661_bbp_write(sc, 77, bbp77); 2049 2050 /* restore Rx filter */ 2051 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2052} 2053 2054/* 2055 * Enable multi-rate retries for frames sent at OFDM rates. 2056 * In 802.11b/g mode, allow fallback to CCK rates. 2057 */ 2058static void 2059rt2661_enable_mrr(struct rt2661_softc *sc) 2060{ 2061 struct ieee80211com *ic = &sc->sc_ic; 2062 uint32_t tmp; 2063 2064 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2065 2066 tmp &= ~RT2661_MRR_CCK_FALLBACK; 2067 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) 2068 tmp |= RT2661_MRR_CCK_FALLBACK; 2069 tmp |= RT2661_MRR_ENABLED; 2070 2071 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2072} 2073 2074static void 2075rt2661_set_txpreamble(struct rt2661_softc *sc) 2076{ 2077 uint32_t tmp; 2078 2079 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 2080 2081 tmp &= ~RT2661_SHORT_PREAMBLE; 2082 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 2083 tmp |= RT2661_SHORT_PREAMBLE; 2084 2085 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 2086} 2087 2088static void 2089rt2661_set_basicrates(struct rt2661_softc *sc, 2090 const struct ieee80211_rateset *rs) 2091{ 2092#define RV(r) ((r) & IEEE80211_RATE_VAL) 2093 uint32_t mask = 0; 2094 uint8_t rate; 2095 int i, j; 2096 2097 for (i = 0; i < rs->rs_nrates; i++) { 2098 rate = rs->rs_rates[i]; 2099 2100 if (!(rate & IEEE80211_RATE_BASIC)) 2101 continue; 2102 2103 /* 2104 * Find h/w rate index. We know it exists because the rate 2105 * set has already been negotiated. 2106 */ 2107 for (j = 0; rt2661_rateset_11g.rs_rates[j] != RV(rate); j++); 2108 2109 mask |= 1 << j; 2110 } 2111 2112 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 2113 2114 DPRINTF(("Setting basic rate mask to 0x%x\n", mask)); 2115#undef RV 2116} 2117 2118/* 2119 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 2120 * driver. 2121 */ 2122static void 2123rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 2124{ 2125 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 2126 uint32_t tmp; 2127 2128 /* update all BBP registers that depend on the band */ 2129 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2130 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2131 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2132 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2133 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2134 } 2135 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2136 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2137 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2138 } 2139 2140 rt2661_bbp_write(sc, 17, bbp17); 2141 rt2661_bbp_write(sc, 96, bbp96); 2142 rt2661_bbp_write(sc, 104, bbp104); 2143 2144 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2145 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2146 rt2661_bbp_write(sc, 75, 0x80); 2147 rt2661_bbp_write(sc, 86, 0x80); 2148 rt2661_bbp_write(sc, 88, 0x80); 2149 } 2150 2151 rt2661_bbp_write(sc, 35, bbp35); 2152 rt2661_bbp_write(sc, 97, bbp97); 2153 rt2661_bbp_write(sc, 98, bbp98); 2154 2155 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2156 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2157 if (IEEE80211_IS_CHAN_2GHZ(c)) 2158 tmp |= RT2661_PA_PE_2GHZ; 2159 else 2160 tmp |= RT2661_PA_PE_5GHZ; 2161 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2162} 2163 2164static void 2165rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2166{ 2167 struct ieee80211com *ic = &sc->sc_ic; 2168 const struct rfprog *rfprog; 2169 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2170 int8_t power; 2171 u_int i, chan; 2172 2173 chan = ieee80211_chan2ieee(ic, c); 2174 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 2175 return; 2176 2177 /* select the appropriate RF settings based on what EEPROM says */ 2178 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2179 2180 /* find the settings for this channel (we know it exists) */ 2181 for (i = 0; rfprog[i].chan != chan; i++); 2182 2183 power = sc->txpow[i]; 2184 if (power < 0) { 2185 bbp94 += power; 2186 power = 0; 2187 } else if (power > 31) { 2188 bbp94 += power - 31; 2189 power = 31; 2190 } 2191 2192 /* 2193 * If we are switching from the 2GHz band to the 5GHz band or 2194 * vice-versa, BBP registers need to be reprogrammed. 2195 */ 2196 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2197 rt2661_select_band(sc, c); 2198 rt2661_select_antenna(sc); 2199 } 2200 sc->sc_curchan = c; 2201 2202 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2203 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2204 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2205 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2206 2207 DELAY(200); 2208 2209 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2210 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2211 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2212 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2213 2214 DELAY(200); 2215 2216 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2217 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2218 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2219 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2220 2221 /* enable smart mode for MIMO-capable RFs */ 2222 bbp3 = rt2661_bbp_read(sc, 3); 2223 2224 bbp3 &= ~RT2661_SMART_MODE; 2225 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2226 bbp3 |= RT2661_SMART_MODE; 2227 2228 rt2661_bbp_write(sc, 3, bbp3); 2229 2230 if (bbp94 != RT2661_BBPR94_DEFAULT) 2231 rt2661_bbp_write(sc, 94, bbp94); 2232 2233 /* 5GHz radio needs a 1ms delay here */ 2234 if (IEEE80211_IS_CHAN_5GHZ(c)) 2235 DELAY(1000); 2236} 2237 2238static void 2239rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2240{ 2241 uint32_t tmp; 2242 2243 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2244 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2245 2246 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2247 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2248} 2249 2250static void 2251rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2252{ 2253 uint32_t tmp; 2254 2255 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2256 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2257 2258 tmp = addr[4] | addr[5] << 8; 2259 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2260} 2261 2262static void 2263rt2661_update_promisc(struct rt2661_softc *sc) 2264{ 2265 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2266 uint32_t tmp; 2267 2268 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2269 2270 tmp &= ~RT2661_DROP_NOT_TO_ME; 2271 if (!(ifp->if_flags & IFF_PROMISC)) 2272 tmp |= RT2661_DROP_NOT_TO_ME; 2273 2274 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2275 2276 DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2277 "entering" : "leaving")); 2278} 2279 2280/* 2281 * Update QoS (802.11e) settings for each h/w Tx ring. 2282 */ 2283static int 2284rt2661_wme_update(struct ieee80211com *ic) 2285{ 2286 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2287 const struct wmeParams *wmep; 2288 2289 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2290 2291 /* XXX: not sure about shifts. */ 2292 /* XXX: the reference driver plays with AC_VI settings too. */ 2293 2294 /* update TxOp */ 2295 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2296 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2297 wmep[WME_AC_BK].wmep_txopLimit); 2298 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2299 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2300 wmep[WME_AC_VO].wmep_txopLimit); 2301 2302 /* update CWmin */ 2303 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2304 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2305 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2306 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2307 wmep[WME_AC_VO].wmep_logcwmin); 2308 2309 /* update CWmax */ 2310 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2311 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2312 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2313 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2314 wmep[WME_AC_VO].wmep_logcwmax); 2315 2316 /* update Aifsn */ 2317 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2318 wmep[WME_AC_BE].wmep_aifsn << 12 | 2319 wmep[WME_AC_BK].wmep_aifsn << 8 | 2320 wmep[WME_AC_VI].wmep_aifsn << 4 | 2321 wmep[WME_AC_VO].wmep_aifsn); 2322 2323 return 0; 2324} 2325 2326static void 2327rt2661_update_slot(struct ifnet *ifp) 2328{ 2329 struct rt2661_softc *sc = ifp->if_softc; 2330 struct ieee80211com *ic = &sc->sc_ic; 2331 uint8_t slottime; 2332 uint32_t tmp; 2333 2334 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2335 2336 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2337 tmp = (tmp & ~0xff) | slottime; 2338 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2339} 2340 2341static const char * 2342rt2661_get_rf(int rev) 2343{ 2344 switch (rev) { 2345 case RT2661_RF_5225: return "RT5225"; 2346 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2347 case RT2661_RF_2527: return "RT2527"; 2348 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2349 default: return "unknown"; 2350 } 2351} 2352 2353static void 2354rt2661_read_eeprom(struct rt2661_softc *sc) 2355{ 2356 struct ieee80211com *ic = &sc->sc_ic; 2357 uint16_t val; 2358 int i; 2359 2360 /* read MAC address */ 2361 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2362 ic->ic_myaddr[0] = val & 0xff; 2363 ic->ic_myaddr[1] = val >> 8; 2364 2365 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2366 ic->ic_myaddr[2] = val & 0xff; 2367 ic->ic_myaddr[3] = val >> 8; 2368 2369 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2370 ic->ic_myaddr[4] = val & 0xff; 2371 ic->ic_myaddr[5] = val >> 8; 2372 2373 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2374 /* XXX: test if different from 0xffff? */ 2375 sc->rf_rev = (val >> 11) & 0x1f; 2376 sc->hw_radio = (val >> 10) & 0x1; 2377 sc->rx_ant = (val >> 4) & 0x3; 2378 sc->tx_ant = (val >> 2) & 0x3; 2379 sc->nb_ant = val & 0x3; 2380 2381 DPRINTF(("RF revision=%d\n", sc->rf_rev)); 2382 2383 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2384 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2385 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2386 2387 DPRINTF(("External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2388 sc->ext_2ghz_lna, sc->ext_5ghz_lna)); 2389 2390 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2391 if ((val & 0xff) != 0xff) 2392 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2393 2394 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2395 if ((val & 0xff) != 0xff) 2396 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2397 2398 /* adjust RSSI correction for external low-noise amplifier */ 2399 if (sc->ext_2ghz_lna) 2400 sc->rssi_2ghz_corr -= 14; 2401 if (sc->ext_5ghz_lna) 2402 sc->rssi_5ghz_corr -= 14; 2403 2404 DPRINTF(("RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2405 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr)); 2406 2407 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2408 if ((val >> 8) != 0xff) 2409 sc->rfprog = (val >> 8) & 0x3; 2410 if ((val & 0xff) != 0xff) 2411 sc->rffreq = val & 0xff; 2412 2413 DPRINTF(("RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq)); 2414 2415 /* read Tx power for all a/b/g channels */ 2416 for (i = 0; i < 19; i++) { 2417 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2418 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2419 DPRINTF(("Channel=%d Tx power=%d\n", 2420 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2])); 2421 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2422 DPRINTF(("Channel=%d Tx power=%d\n", 2423 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1])); 2424 } 2425 2426 /* read vendor-specific BBP values */ 2427 for (i = 0; i < 16; i++) { 2428 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2429 if (val == 0 || val == 0xffff) 2430 continue; /* skip invalid entries */ 2431 sc->bbp_prom[i].reg = val >> 8; 2432 sc->bbp_prom[i].val = val & 0xff; 2433 DPRINTF(("BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2434 sc->bbp_prom[i].val)); 2435 } 2436} 2437 2438static int 2439rt2661_bbp_init(struct rt2661_softc *sc) 2440{ 2441#define N(a) (sizeof (a) / sizeof ((a)[0])) 2442 int i, ntries; 2443 uint8_t val; 2444 2445 /* wait for BBP to be ready */ 2446 for (ntries = 0; ntries < 100; ntries++) { 2447 val = rt2661_bbp_read(sc, 0); 2448 if (val != 0 && val != 0xff) 2449 break; 2450 DELAY(100); 2451 } 2452 if (ntries == 100) { 2453 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2454 return EIO; 2455 } 2456 2457 /* initialize BBP registers to default values */ 2458 for (i = 0; i < N(rt2661_def_bbp); i++) { 2459 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2460 rt2661_def_bbp[i].val); 2461 } 2462 2463 /* write vendor-specific BBP values (from EEPROM) */ 2464 for (i = 0; i < 16; i++) { 2465 if (sc->bbp_prom[i].reg == 0) 2466 continue; 2467 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2468 } 2469 2470 return 0; 2471#undef N 2472} 2473 2474static void 2475rt2661_init(void *priv) 2476{ 2477#define N(a) (sizeof (a) / sizeof ((a)[0])) 2478 struct rt2661_softc *sc = priv; 2479 struct ieee80211com *ic = &sc->sc_ic; 2480 struct ifnet *ifp = ic->ic_ifp; 2481 uint32_t tmp, sta[3]; 2482 int i, ntries; 2483 2484 RAL_LOCK(sc); 2485 2486 rt2661_stop(sc); 2487 2488 /* initialize Tx rings */ 2489 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2490 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2491 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2492 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2493 2494 /* initialize Mgt ring */ 2495 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2496 2497 /* initialize Rx ring */ 2498 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2499 2500 /* initialize Tx rings sizes */ 2501 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2502 RT2661_TX_RING_COUNT << 24 | 2503 RT2661_TX_RING_COUNT << 16 | 2504 RT2661_TX_RING_COUNT << 8 | 2505 RT2661_TX_RING_COUNT); 2506 2507 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2508 RT2661_TX_DESC_WSIZE << 16 | 2509 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2510 RT2661_MGT_RING_COUNT); 2511 2512 /* initialize Rx rings */ 2513 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2514 RT2661_RX_DESC_BACK << 16 | 2515 RT2661_RX_DESC_WSIZE << 8 | 2516 RT2661_RX_RING_COUNT); 2517 2518 /* XXX: some magic here */ 2519 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2520 2521 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2522 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2523 2524 /* load base address of Rx ring */ 2525 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2526 2527 /* initialize MAC registers to default values */ 2528 for (i = 0; i < N(rt2661_def_mac); i++) 2529 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2530 2531 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2532 rt2661_set_macaddr(sc, ic->ic_myaddr); 2533 2534 /* set host ready */ 2535 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2536 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2537 2538 /* wait for BBP/RF to wakeup */ 2539 for (ntries = 0; ntries < 1000; ntries++) { 2540 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2541 break; 2542 DELAY(1000); 2543 } 2544 if (ntries == 1000) { 2545 printf("timeout waiting for BBP/RF to wakeup\n"); 2546 rt2661_stop(sc); 2547 RAL_UNLOCK(sc); 2548 return; 2549 } 2550 2551 if (rt2661_bbp_init(sc) != 0) { 2552 rt2661_stop(sc); 2553 RAL_UNLOCK(sc); 2554 return; 2555 } 2556 2557 /* select default channel */ 2558 sc->sc_curchan = ic->ic_curchan; 2559 rt2661_select_band(sc, sc->sc_curchan); 2560 rt2661_select_antenna(sc); 2561 rt2661_set_chan(sc, sc->sc_curchan); 2562 2563 /* update Rx filter */ 2564 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2565 2566 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2567 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2568 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2569 RT2661_DROP_ACKCTS; 2570 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2571 tmp |= RT2661_DROP_TODS; 2572 if (!(ifp->if_flags & IFF_PROMISC)) 2573 tmp |= RT2661_DROP_NOT_TO_ME; 2574 } 2575 2576 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2577 2578 /* clear STA registers */ 2579 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2580 2581 /* initialize ASIC */ 2582 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2583 2584 /* clear any pending interrupt */ 2585 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2586 2587 /* enable interrupts */ 2588 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2589 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2590 2591 /* kick Rx */ 2592 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2593 2594 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2595 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2596 2597 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2598 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 2599 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2600 } else 2601 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2602 2603 RAL_UNLOCK(sc); 2604#undef N 2605} 2606 2607void 2608rt2661_stop(void *priv) 2609{ 2610 struct rt2661_softc *sc = priv; 2611 struct ieee80211com *ic = &sc->sc_ic; 2612 struct ifnet *ifp = ic->ic_ifp; 2613 uint32_t tmp; 2614 2615 sc->sc_tx_timer = 0; 2616 ifp->if_timer = 0; 2617 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2618 2619 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2620 2621 /* abort Tx (for all 5 Tx rings) */ 2622 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2623 2624 /* disable Rx (value remains after reset!) */ 2625 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2626 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2627 2628 /* reset ASIC */ 2629 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2630 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2631 2632 /* disable interrupts */ 2633 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2634 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2635 2636 /* clear any pending interrupt */ 2637 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2638 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2639 2640 /* reset Tx and Rx rings */ 2641 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2642 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2643 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2644 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2645 rt2661_reset_tx_ring(sc, &sc->mgtq); 2646 rt2661_reset_rx_ring(sc, &sc->rxq); 2647} 2648 2649static int 2650rt2661_load_microcode(struct rt2661_softc *sc, const uint8_t *ucode, int size) 2651{ 2652 int ntries; 2653 2654 /* reset 8051 */ 2655 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2656 2657 /* cancel any pending Host to MCU command */ 2658 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2659 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2660 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2661 2662 /* write 8051's microcode */ 2663 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2664 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, ucode, size); 2665 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2666 2667 /* kick 8051's ass */ 2668 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2669 2670 /* wait for 8051 to initialize */ 2671 for (ntries = 0; ntries < 500; ntries++) { 2672 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2673 break; 2674 DELAY(100); 2675 } 2676 if (ntries == 500) { 2677 printf("timeout waiting for MCU to initialize\n"); 2678 return EIO; 2679 } 2680 return 0; 2681} 2682 2683#ifdef notyet 2684/* 2685 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2686 * false CCA count. This function is called periodically (every seconds) when 2687 * in the RUN state. Values taken from the reference driver. 2688 */ 2689static void 2690rt2661_rx_tune(struct rt2661_softc *sc) 2691{ 2692 uint8_t bbp17; 2693 uint16_t cca; 2694 int lo, hi, dbm; 2695 2696 /* 2697 * Tuning range depends on operating band and on the presence of an 2698 * external low-noise amplifier. 2699 */ 2700 lo = 0x20; 2701 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2702 lo += 0x08; 2703 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2704 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2705 lo += 0x10; 2706 hi = lo + 0x20; 2707 2708 /* retrieve false CCA count since last call (clear on read) */ 2709 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2710 2711 if (dbm >= -35) { 2712 bbp17 = 0x60; 2713 } else if (dbm >= -58) { 2714 bbp17 = hi; 2715 } else if (dbm >= -66) { 2716 bbp17 = lo + 0x10; 2717 } else if (dbm >= -74) { 2718 bbp17 = lo + 0x08; 2719 } else { 2720 /* RSSI < -74dBm, tune using false CCA count */ 2721 2722 bbp17 = sc->bbp17; /* current value */ 2723 2724 hi -= 2 * (-74 - dbm); 2725 if (hi < lo) 2726 hi = lo; 2727 2728 if (bbp17 > hi) { 2729 bbp17 = hi; 2730 2731 } else if (cca > 512) { 2732 if (++bbp17 > hi) 2733 bbp17 = hi; 2734 } else if (cca < 100) { 2735 if (--bbp17 < lo) 2736 bbp17 = lo; 2737 } 2738 } 2739 2740 if (bbp17 != sc->bbp17) { 2741 rt2661_bbp_write(sc, 17, bbp17); 2742 sc->bbp17 = bbp17; 2743 } 2744} 2745 2746/* 2747 * Enter/Leave radar detection mode. 2748 * This is for 802.11h additional regulatory domains. 2749 */ 2750static void 2751rt2661_radar_start(struct rt2661_softc *sc) 2752{ 2753 uint32_t tmp; 2754 2755 /* disable Rx */ 2756 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2757 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2758 2759 rt2661_bbp_write(sc, 82, 0x20); 2760 rt2661_bbp_write(sc, 83, 0x00); 2761 rt2661_bbp_write(sc, 84, 0x40); 2762 2763 /* save current BBP registers values */ 2764 sc->bbp18 = rt2661_bbp_read(sc, 18); 2765 sc->bbp21 = rt2661_bbp_read(sc, 21); 2766 sc->bbp22 = rt2661_bbp_read(sc, 22); 2767 sc->bbp16 = rt2661_bbp_read(sc, 16); 2768 sc->bbp17 = rt2661_bbp_read(sc, 17); 2769 sc->bbp64 = rt2661_bbp_read(sc, 64); 2770 2771 rt2661_bbp_write(sc, 18, 0xff); 2772 rt2661_bbp_write(sc, 21, 0x3f); 2773 rt2661_bbp_write(sc, 22, 0x3f); 2774 rt2661_bbp_write(sc, 16, 0xbd); 2775 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2776 rt2661_bbp_write(sc, 64, 0x21); 2777 2778 /* restore Rx filter */ 2779 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2780} 2781 2782static int 2783rt2661_radar_stop(struct rt2661_softc *sc) 2784{ 2785 uint8_t bbp66; 2786 2787 /* read radar detection result */ 2788 bbp66 = rt2661_bbp_read(sc, 66); 2789 2790 /* restore BBP registers values */ 2791 rt2661_bbp_write(sc, 16, sc->bbp16); 2792 rt2661_bbp_write(sc, 17, sc->bbp17); 2793 rt2661_bbp_write(sc, 18, sc->bbp18); 2794 rt2661_bbp_write(sc, 21, sc->bbp21); 2795 rt2661_bbp_write(sc, 22, sc->bbp22); 2796 rt2661_bbp_write(sc, 64, sc->bbp64); 2797 2798 return bbp66 == 1; 2799} 2800#endif 2801 2802static int 2803rt2661_prepare_beacon(struct rt2661_softc *sc) 2804{ 2805 struct ieee80211com *ic = &sc->sc_ic; 2806 struct ieee80211_beacon_offsets bo; 2807 struct rt2661_tx_desc desc; 2808 struct mbuf *m0; 2809 int rate; 2810 2811 m0 = ieee80211_beacon_alloc(ic, ic->ic_bss, &bo); 2812 if (m0 == NULL) { 2813 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2814 return ENOBUFS; 2815 } 2816 2817 /* send beacons at the lowest available rate */ 2818 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan) ? 12 : 2; 2819 2820 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2821 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2822 2823 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2824 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2825 2826 /* copy beacon header and payload into NIC memory */ 2827 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2828 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2829 2830 m_freem(m0); 2831 2832 return 0; 2833} 2834 2835/* 2836 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2837 * and HostAP operating modes. 2838 */ 2839static void 2840rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2841{ 2842 struct ieee80211com *ic = &sc->sc_ic; 2843 uint32_t tmp; 2844 2845 if (ic->ic_opmode != IEEE80211_M_STA) { 2846 /* 2847 * Change default 16ms TBTT adjustment to 8ms. 2848 * Must be done before enabling beacon generation. 2849 */ 2850 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2851 } 2852 2853 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2854 2855 /* set beacon interval (in 1/16ms unit) */ 2856 tmp |= ic->ic_bss->ni_intval * 16; 2857 2858 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2859 if (ic->ic_opmode == IEEE80211_M_STA) 2860 tmp |= RT2661_TSF_MODE(1); 2861 else 2862 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2863 2864 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2865} 2866 2867/* 2868 * Retrieve the "Received Signal Strength Indicator" from the raw values 2869 * contained in Rx descriptors. The computation depends on which band the 2870 * frame was received. Correction values taken from the reference driver. 2871 */ 2872static int 2873rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2874{ 2875 int lna, agc, rssi; 2876 2877 lna = (raw >> 5) & 0x3; 2878 agc = raw & 0x1f; 2879 2880 rssi = 2 * agc; 2881 2882 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2883 rssi += sc->rssi_2ghz_corr; 2884 2885 if (lna == 1) 2886 rssi -= 64; 2887 else if (lna == 2) 2888 rssi -= 74; 2889 else if (lna == 3) 2890 rssi -= 90; 2891 } else { 2892 rssi += sc->rssi_5ghz_corr; 2893 2894 if (lna == 1) 2895 rssi -= 64; 2896 else if (lna == 2) 2897 rssi -= 86; 2898 else if (lna == 3) 2899 rssi -= 100; 2900 } 2901 return rssi; 2902} 2903