rt2661.c revision 178704
1/* $FreeBSD: head/sys/dev/ral/rt2661.c 178704 2008-05-01 04:55:00Z thompsa $ */ 2 3/*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2661.c 178704 2008-05-01 04:55:00Z thompsa $"); 22 23/*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28#include <sys/param.h> 29#include <sys/sysctl.h> 30#include <sys/sockio.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/lock.h> 37#include <sys/mutex.h> 38#include <sys/module.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/firmware.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_arp.h> 50#include <net/ethernet.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54 55#include <net80211/ieee80211_var.h> 56#include <net80211/ieee80211_phy.h> 57#include <net80211/ieee80211_radiotap.h> 58#include <net80211/ieee80211_regdomain.h> 59#include <net80211/ieee80211_amrr.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/ip.h> 65#include <netinet/if_ether.h> 66 67#include <dev/ral/rt2661reg.h> 68#include <dev/ral/rt2661var.h> 69 70#define RAL_DEBUG 71#ifdef RAL_DEBUG 72#define DPRINTF(sc, fmt, ...) do { \ 73 if (sc->sc_debug > 0) \ 74 printf(fmt, __VA_ARGS__); \ 75} while (0) 76#define DPRINTFN(sc, n, fmt, ...) do { \ 77 if (sc->sc_debug >= (n)) \ 78 printf(fmt, __VA_ARGS__); \ 79} while (0) 80#else 81#define DPRINTF(sc, fmt, ...) 82#define DPRINTFN(sc, n, fmt, ...) 83#endif 84 85static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 86 const char name[IFNAMSIZ], int unit, int opmode, 87 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 88 const uint8_t mac[IEEE80211_ADDR_LEN]); 89static void rt2661_vap_delete(struct ieee80211vap *); 90static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 91 int); 92static int rt2661_alloc_tx_ring(struct rt2661_softc *, 93 struct rt2661_tx_ring *, int); 94static void rt2661_reset_tx_ring(struct rt2661_softc *, 95 struct rt2661_tx_ring *); 96static void rt2661_free_tx_ring(struct rt2661_softc *, 97 struct rt2661_tx_ring *); 98static int rt2661_alloc_rx_ring(struct rt2661_softc *, 99 struct rt2661_rx_ring *, int); 100static void rt2661_reset_rx_ring(struct rt2661_softc *, 101 struct rt2661_rx_ring *); 102static void rt2661_free_rx_ring(struct rt2661_softc *, 103 struct rt2661_rx_ring *); 104static struct ieee80211_node *rt2661_node_alloc( 105 struct ieee80211_node_table *); 106static void rt2661_newassoc(struct ieee80211_node *, int); 107static int rt2661_newstate(struct ieee80211vap *, 108 enum ieee80211_state, int); 109static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 110static void rt2661_rx_intr(struct rt2661_softc *); 111static void rt2661_tx_intr(struct rt2661_softc *); 112static void rt2661_tx_dma_intr(struct rt2661_softc *, 113 struct rt2661_tx_ring *); 114static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 115static void rt2661_mcu_wakeup(struct rt2661_softc *); 116static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 117static void rt2661_scan_start(struct ieee80211com *); 118static void rt2661_scan_end(struct ieee80211com *); 119static void rt2661_set_channel(struct ieee80211com *); 120static void rt2661_setup_tx_desc(struct rt2661_softc *, 121 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 122 int, const bus_dma_segment_t *, int, int); 123static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 124 struct ieee80211_node *, int); 125static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 126 struct ieee80211_node *); 127static void rt2661_start_locked(struct ifnet *); 128static void rt2661_start(struct ifnet *); 129static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 130 const struct ieee80211_bpf_params *); 131static void rt2661_watchdog(void *); 132static int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 133static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 134 uint8_t); 135static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 136static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 137 uint32_t); 138static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 139 uint16_t); 140static void rt2661_select_antenna(struct rt2661_softc *); 141static void rt2661_enable_mrr(struct rt2661_softc *); 142static void rt2661_set_txpreamble(struct rt2661_softc *); 143static void rt2661_set_basicrates(struct rt2661_softc *, 144 const struct ieee80211_rateset *); 145static void rt2661_select_band(struct rt2661_softc *, 146 struct ieee80211_channel *); 147static void rt2661_set_chan(struct rt2661_softc *, 148 struct ieee80211_channel *); 149static void rt2661_set_bssid(struct rt2661_softc *, 150 const uint8_t *); 151static void rt2661_set_macaddr(struct rt2661_softc *, 152 const uint8_t *); 153static void rt2661_update_promisc(struct ifnet *); 154static int rt2661_wme_update(struct ieee80211com *) __unused; 155static void rt2661_update_slot(struct ifnet *); 156static const char *rt2661_get_rf(int); 157static void rt2661_read_eeprom(struct rt2661_softc *, 158 struct ieee80211com *); 159static int rt2661_bbp_init(struct rt2661_softc *); 160static void rt2661_init_locked(struct rt2661_softc *); 161static void rt2661_init(void *); 162static void rt2661_stop_locked(struct rt2661_softc *); 163static void rt2661_stop(void *); 164static int rt2661_load_microcode(struct rt2661_softc *); 165#ifdef notyet 166static void rt2661_rx_tune(struct rt2661_softc *); 167static void rt2661_radar_start(struct rt2661_softc *); 168static int rt2661_radar_stop(struct rt2661_softc *); 169#endif 170static int rt2661_prepare_beacon(struct rt2661_softc *, 171 struct ieee80211vap *); 172static void rt2661_enable_tsf_sync(struct rt2661_softc *); 173static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 174 175static const struct { 176 uint32_t reg; 177 uint32_t val; 178} rt2661_def_mac[] = { 179 RT2661_DEF_MAC 180}; 181 182static const struct { 183 uint8_t reg; 184 uint8_t val; 185} rt2661_def_bbp[] = { 186 RT2661_DEF_BBP 187}; 188 189static const struct rfprog { 190 uint8_t chan; 191 uint32_t r1, r2, r3, r4; 192} rt2661_rf5225_1[] = { 193 RT2661_RF5225_1 194}, rt2661_rf5225_2[] = { 195 RT2661_RF5225_2 196}; 197 198int 199rt2661_attach(device_t dev, int id) 200{ 201 struct rt2661_softc *sc = device_get_softc(dev); 202 struct ieee80211com *ic; 203 struct ifnet *ifp; 204 uint32_t val; 205 int error, ac, ntries; 206 uint8_t bands; 207 208 sc->sc_id = id; 209 sc->sc_dev = dev; 210 211 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 212 if (ifp == NULL) { 213 device_printf(sc->sc_dev, "can not if_alloc()\n"); 214 return ENOMEM; 215 } 216 ic = ifp->if_l2com; 217 218 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 219 MTX_DEF | MTX_RECURSE); 220 221 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 222 223 /* wait for NIC to initialize */ 224 for (ntries = 0; ntries < 1000; ntries++) { 225 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 226 break; 227 DELAY(1000); 228 } 229 if (ntries == 1000) { 230 device_printf(sc->sc_dev, 231 "timeout waiting for NIC to initialize\n"); 232 error = EIO; 233 goto fail1; 234 } 235 236 /* retrieve RF rev. no and various other things from EEPROM */ 237 rt2661_read_eeprom(sc, ic); 238 239 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 240 rt2661_get_rf(sc->rf_rev)); 241 242 /* 243 * Allocate Tx and Rx rings. 244 */ 245 for (ac = 0; ac < 4; ac++) { 246 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 247 RT2661_TX_RING_COUNT); 248 if (error != 0) { 249 device_printf(sc->sc_dev, 250 "could not allocate Tx ring %d\n", ac); 251 goto fail2; 252 } 253 } 254 255 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 256 if (error != 0) { 257 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 258 goto fail2; 259 } 260 261 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 262 if (error != 0) { 263 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 264 goto fail3; 265 } 266 267 ifp->if_softc = sc; 268 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 270 ifp->if_init = rt2661_init; 271 ifp->if_ioctl = rt2661_ioctl; 272 ifp->if_start = rt2661_start; 273 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 274 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 275 IFQ_SET_READY(&ifp->if_snd); 276 277 ic->ic_ifp = ifp; 278 ic->ic_opmode = IEEE80211_M_STA; 279 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 280 281 /* set device capabilities */ 282 ic->ic_caps = 283 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 284 | IEEE80211_C_HOSTAP /* hostap mode */ 285 | IEEE80211_C_MONITOR /* monitor mode */ 286 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 287 | IEEE80211_C_WDS /* 4-address traffic works */ 288 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 289 | IEEE80211_C_SHSLOT /* short slot time supported */ 290 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 291 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 292#ifdef notyet 293 | IEEE80211_C_TXFRAG /* handle tx frags */ 294 | IEEE80211_C_WME /* 802.11e */ 295#endif 296 ; 297 298 bands = 0; 299 setbit(&bands, IEEE80211_MODE_11B); 300 setbit(&bands, IEEE80211_MODE_11G); 301 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) 302 setbit(&bands, IEEE80211_MODE_11A); 303 ieee80211_init_channels(ic, NULL, &bands); 304 305 ieee80211_ifattach(ic); 306 ic->ic_newassoc = rt2661_newassoc; 307 ic->ic_node_alloc = rt2661_node_alloc; 308#if 0 309 ic->ic_wme.wme_update = rt2661_wme_update; 310#endif 311 ic->ic_scan_start = rt2661_scan_start; 312 ic->ic_scan_end = rt2661_scan_end; 313 ic->ic_set_channel = rt2661_set_channel; 314 ic->ic_updateslot = rt2661_update_slot; 315 ic->ic_update_promisc = rt2661_update_promisc; 316 ic->ic_raw_xmit = rt2661_raw_xmit; 317 318 ic->ic_vap_create = rt2661_vap_create; 319 ic->ic_vap_delete = rt2661_vap_delete; 320 321 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 322 323 bpfattach(ifp, DLT_IEEE802_11_RADIO, 324 sizeof (struct ieee80211_frame) + sizeof (sc->sc_txtap)); 325 326 sc->sc_rxtap_len = sizeof sc->sc_rxtap; 327 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 328 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 329 330 sc->sc_txtap_len = sizeof sc->sc_txtap; 331 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 332 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 333 334#ifdef RAL_DEBUG 335 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 336 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 337 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 338#endif 339 if (bootverbose) 340 ieee80211_announce(ic); 341 342 return 0; 343 344fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 345fail2: while (--ac >= 0) 346 rt2661_free_tx_ring(sc, &sc->txq[ac]); 347fail1: mtx_destroy(&sc->sc_mtx); 348 if_free(ifp); 349 return error; 350} 351 352int 353rt2661_detach(void *xsc) 354{ 355 struct rt2661_softc *sc = xsc; 356 struct ifnet *ifp = sc->sc_ifp; 357 struct ieee80211com *ic = ifp->if_l2com; 358 359 RAL_LOCK(sc); 360 rt2661_stop_locked(sc); 361 RAL_UNLOCK(sc); 362 363 bpfdetach(ifp); 364 ieee80211_ifdetach(ic); 365 366 rt2661_free_tx_ring(sc, &sc->txq[0]); 367 rt2661_free_tx_ring(sc, &sc->txq[1]); 368 rt2661_free_tx_ring(sc, &sc->txq[2]); 369 rt2661_free_tx_ring(sc, &sc->txq[3]); 370 rt2661_free_tx_ring(sc, &sc->mgtq); 371 rt2661_free_rx_ring(sc, &sc->rxq); 372 373 if_free(ifp); 374 375 mtx_destroy(&sc->sc_mtx); 376 377 return 0; 378} 379 380static struct ieee80211vap * 381rt2661_vap_create(struct ieee80211com *ic, 382 const char name[IFNAMSIZ], int unit, int opmode, int flags, 383 const uint8_t bssid[IEEE80211_ADDR_LEN], 384 const uint8_t mac[IEEE80211_ADDR_LEN]) 385{ 386 struct ifnet *ifp = ic->ic_ifp; 387 struct rt2661_vap *rvp; 388 struct ieee80211vap *vap; 389 390 switch (opmode) { 391 case IEEE80211_M_STA: 392 case IEEE80211_M_IBSS: 393 case IEEE80211_M_AHDEMO: 394 case IEEE80211_M_MONITOR: 395 case IEEE80211_M_HOSTAP: 396 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 397 if_printf(ifp, "only 1 vap supported\n"); 398 return NULL; 399 } 400 if (opmode == IEEE80211_M_STA) 401 flags |= IEEE80211_CLONE_NOBEACONS; 402 break; 403 case IEEE80211_M_WDS: 404 if (TAILQ_EMPTY(&ic->ic_vaps) || 405 ic->ic_opmode != IEEE80211_M_HOSTAP) { 406 if_printf(ifp, "wds only supported in ap mode\n"); 407 return NULL; 408 } 409 /* 410 * Silently remove any request for a unique 411 * bssid; WDS vap's always share the local 412 * mac address. 413 */ 414 flags &= ~IEEE80211_CLONE_BSSID; 415 break; 416 default: 417 if_printf(ifp, "unknown opmode %d\n", opmode); 418 return NULL; 419 } 420 rvp = (struct rt2661_vap *) malloc(sizeof(struct rt2661_vap), 421 M_80211_VAP, M_NOWAIT | M_ZERO); 422 if (rvp == NULL) 423 return NULL; 424 vap = &rvp->ral_vap; 425 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 426 427 /* override state transition machine */ 428 rvp->ral_newstate = vap->iv_newstate; 429 vap->iv_newstate = rt2661_newstate; 430#if 0 431 vap->iv_update_beacon = rt2661_beacon_update; 432#endif 433 434 ieee80211_amrr_init(&rvp->amrr, vap, 435 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 436 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 437 500 /* ms */); 438 439 /* complete setup */ 440 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 441 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 442 ic->ic_opmode = opmode; 443 return vap; 444} 445 446static void 447rt2661_vap_delete(struct ieee80211vap *vap) 448{ 449 struct rt2661_vap *rvp = RT2661_VAP(vap); 450 451 ieee80211_amrr_cleanup(&rvp->amrr); 452 ieee80211_vap_detach(vap); 453 free(rvp, M_80211_VAP); 454} 455 456void 457rt2661_shutdown(void *xsc) 458{ 459 struct rt2661_softc *sc = xsc; 460 461 rt2661_stop(sc); 462} 463 464void 465rt2661_suspend(void *xsc) 466{ 467 struct rt2661_softc *sc = xsc; 468 469 rt2661_stop(sc); 470} 471 472void 473rt2661_resume(void *xsc) 474{ 475 struct rt2661_softc *sc = xsc; 476 struct ifnet *ifp = sc->sc_ifp; 477 478 if (ifp->if_flags & IFF_UP) 479 rt2661_init(sc); 480} 481 482static void 483rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 484{ 485 if (error != 0) 486 return; 487 488 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 489 490 *(bus_addr_t *)arg = segs[0].ds_addr; 491} 492 493static int 494rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 495 int count) 496{ 497 int i, error; 498 499 ring->count = count; 500 ring->queued = 0; 501 ring->cur = ring->next = ring->stat = 0; 502 503 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 504 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 505 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 506 0, NULL, NULL, &ring->desc_dmat); 507 if (error != 0) { 508 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 509 goto fail; 510 } 511 512 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 513 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 514 if (error != 0) { 515 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 516 goto fail; 517 } 518 519 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 520 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 521 0); 522 if (error != 0) { 523 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 524 goto fail; 525 } 526 527 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 528 M_NOWAIT | M_ZERO); 529 if (ring->data == NULL) { 530 device_printf(sc->sc_dev, "could not allocate soft data\n"); 531 error = ENOMEM; 532 goto fail; 533 } 534 535 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 536 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 537 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 538 if (error != 0) { 539 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 540 goto fail; 541 } 542 543 for (i = 0; i < count; i++) { 544 error = bus_dmamap_create(ring->data_dmat, 0, 545 &ring->data[i].map); 546 if (error != 0) { 547 device_printf(sc->sc_dev, "could not create DMA map\n"); 548 goto fail; 549 } 550 } 551 552 return 0; 553 554fail: rt2661_free_tx_ring(sc, ring); 555 return error; 556} 557 558static void 559rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 560{ 561 struct rt2661_tx_desc *desc; 562 struct rt2661_tx_data *data; 563 int i; 564 565 for (i = 0; i < ring->count; i++) { 566 desc = &ring->desc[i]; 567 data = &ring->data[i]; 568 569 if (data->m != NULL) { 570 bus_dmamap_sync(ring->data_dmat, data->map, 571 BUS_DMASYNC_POSTWRITE); 572 bus_dmamap_unload(ring->data_dmat, data->map); 573 m_freem(data->m); 574 data->m = NULL; 575 } 576 577 if (data->ni != NULL) { 578 ieee80211_free_node(data->ni); 579 data->ni = NULL; 580 } 581 582 desc->flags = 0; 583 } 584 585 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 586 587 ring->queued = 0; 588 ring->cur = ring->next = ring->stat = 0; 589} 590 591static void 592rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 593{ 594 struct rt2661_tx_data *data; 595 int i; 596 597 if (ring->desc != NULL) { 598 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 599 BUS_DMASYNC_POSTWRITE); 600 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 601 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 602 } 603 604 if (ring->desc_dmat != NULL) 605 bus_dma_tag_destroy(ring->desc_dmat); 606 607 if (ring->data != NULL) { 608 for (i = 0; i < ring->count; i++) { 609 data = &ring->data[i]; 610 611 if (data->m != NULL) { 612 bus_dmamap_sync(ring->data_dmat, data->map, 613 BUS_DMASYNC_POSTWRITE); 614 bus_dmamap_unload(ring->data_dmat, data->map); 615 m_freem(data->m); 616 } 617 618 if (data->ni != NULL) 619 ieee80211_free_node(data->ni); 620 621 if (data->map != NULL) 622 bus_dmamap_destroy(ring->data_dmat, data->map); 623 } 624 625 free(ring->data, M_DEVBUF); 626 } 627 628 if (ring->data_dmat != NULL) 629 bus_dma_tag_destroy(ring->data_dmat); 630} 631 632static int 633rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 634 int count) 635{ 636 struct rt2661_rx_desc *desc; 637 struct rt2661_rx_data *data; 638 bus_addr_t physaddr; 639 int i, error; 640 641 ring->count = count; 642 ring->cur = ring->next = 0; 643 644 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 645 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 646 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 647 0, NULL, NULL, &ring->desc_dmat); 648 if (error != 0) { 649 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 650 goto fail; 651 } 652 653 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 654 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 655 if (error != 0) { 656 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 657 goto fail; 658 } 659 660 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 661 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 662 0); 663 if (error != 0) { 664 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 665 goto fail; 666 } 667 668 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 669 M_NOWAIT | M_ZERO); 670 if (ring->data == NULL) { 671 device_printf(sc->sc_dev, "could not allocate soft data\n"); 672 error = ENOMEM; 673 goto fail; 674 } 675 676 /* 677 * Pre-allocate Rx buffers and populate Rx ring. 678 */ 679 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 680 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 681 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 682 if (error != 0) { 683 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 684 goto fail; 685 } 686 687 for (i = 0; i < count; i++) { 688 desc = &sc->rxq.desc[i]; 689 data = &sc->rxq.data[i]; 690 691 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 692 if (error != 0) { 693 device_printf(sc->sc_dev, "could not create DMA map\n"); 694 goto fail; 695 } 696 697 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 698 if (data->m == NULL) { 699 device_printf(sc->sc_dev, 700 "could not allocate rx mbuf\n"); 701 error = ENOMEM; 702 goto fail; 703 } 704 705 error = bus_dmamap_load(ring->data_dmat, data->map, 706 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 707 &physaddr, 0); 708 if (error != 0) { 709 device_printf(sc->sc_dev, 710 "could not load rx buf DMA map"); 711 goto fail; 712 } 713 714 desc->flags = htole32(RT2661_RX_BUSY); 715 desc->physaddr = htole32(physaddr); 716 } 717 718 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 719 720 return 0; 721 722fail: rt2661_free_rx_ring(sc, ring); 723 return error; 724} 725 726static void 727rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 728{ 729 int i; 730 731 for (i = 0; i < ring->count; i++) 732 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 733 734 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 735 736 ring->cur = ring->next = 0; 737} 738 739static void 740rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 741{ 742 struct rt2661_rx_data *data; 743 int i; 744 745 if (ring->desc != NULL) { 746 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 747 BUS_DMASYNC_POSTWRITE); 748 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 749 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 750 } 751 752 if (ring->desc_dmat != NULL) 753 bus_dma_tag_destroy(ring->desc_dmat); 754 755 if (ring->data != NULL) { 756 for (i = 0; i < ring->count; i++) { 757 data = &ring->data[i]; 758 759 if (data->m != NULL) { 760 bus_dmamap_sync(ring->data_dmat, data->map, 761 BUS_DMASYNC_POSTREAD); 762 bus_dmamap_unload(ring->data_dmat, data->map); 763 m_freem(data->m); 764 } 765 766 if (data->map != NULL) 767 bus_dmamap_destroy(ring->data_dmat, data->map); 768 } 769 770 free(ring->data, M_DEVBUF); 771 } 772 773 if (ring->data_dmat != NULL) 774 bus_dma_tag_destroy(ring->data_dmat); 775} 776 777static struct ieee80211_node * 778rt2661_node_alloc(struct ieee80211_node_table *nt) 779{ 780 struct rt2661_node *rn; 781 782 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 783 M_NOWAIT | M_ZERO); 784 785 return (rn != NULL) ? &rn->ni : NULL; 786} 787 788static void 789rt2661_newassoc(struct ieee80211_node *ni, int isnew) 790{ 791 struct ieee80211vap *vap = ni->ni_vap; 792 793 ieee80211_amrr_node_init(&RT2661_VAP(vap)->amrr, 794 &RT2661_NODE(ni)->amrr, ni); 795} 796 797static int 798rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 799{ 800 struct rt2661_vap *rvp = RT2661_VAP(vap); 801 struct ieee80211com *ic = vap->iv_ic; 802 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 803 int error; 804 805 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 806 uint32_t tmp; 807 808 /* abort TSF synchronization */ 809 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 810 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 811 } 812 813 error = rvp->ral_newstate(vap, nstate, arg); 814 815 if (error == 0 && nstate == IEEE80211_S_RUN) { 816 struct ieee80211_node *ni = vap->iv_bss; 817 818 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 819 rt2661_enable_mrr(sc); 820 rt2661_set_txpreamble(sc); 821 rt2661_set_basicrates(sc, &ni->ni_rates); 822 rt2661_set_bssid(sc, ni->ni_bssid); 823 } 824 825 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 826 vap->iv_opmode == IEEE80211_M_IBSS) { 827 error = rt2661_prepare_beacon(sc, vap); 828 if (error != 0) 829 return error; 830 } 831 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 832 if (vap->iv_opmode == IEEE80211_M_STA) { 833 /* fake a join to init the tx rate */ 834 rt2661_newassoc(ni, 1); 835 } 836 rt2661_enable_tsf_sync(sc); 837 } 838 } 839 return error; 840} 841 842/* 843 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 844 * 93C66). 845 */ 846static uint16_t 847rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 848{ 849 uint32_t tmp; 850 uint16_t val; 851 int n; 852 853 /* clock C once before the first command */ 854 RT2661_EEPROM_CTL(sc, 0); 855 856 RT2661_EEPROM_CTL(sc, RT2661_S); 857 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 858 RT2661_EEPROM_CTL(sc, RT2661_S); 859 860 /* write start bit (1) */ 861 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 862 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 863 864 /* write READ opcode (10) */ 865 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 866 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 867 RT2661_EEPROM_CTL(sc, RT2661_S); 868 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 869 870 /* write address (A5-A0 or A7-A0) */ 871 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 872 for (; n >= 0; n--) { 873 RT2661_EEPROM_CTL(sc, RT2661_S | 874 (((addr >> n) & 1) << RT2661_SHIFT_D)); 875 RT2661_EEPROM_CTL(sc, RT2661_S | 876 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 877 } 878 879 RT2661_EEPROM_CTL(sc, RT2661_S); 880 881 /* read data Q15-Q0 */ 882 val = 0; 883 for (n = 15; n >= 0; n--) { 884 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 885 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 886 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 887 RT2661_EEPROM_CTL(sc, RT2661_S); 888 } 889 890 RT2661_EEPROM_CTL(sc, 0); 891 892 /* clear Chip Select and clock C */ 893 RT2661_EEPROM_CTL(sc, RT2661_S); 894 RT2661_EEPROM_CTL(sc, 0); 895 RT2661_EEPROM_CTL(sc, RT2661_C); 896 897 return val; 898} 899 900static void 901rt2661_tx_intr(struct rt2661_softc *sc) 902{ 903 struct ifnet *ifp = sc->sc_ifp; 904 struct rt2661_tx_ring *txq; 905 struct rt2661_tx_data *data; 906 struct rt2661_node *rn; 907 uint32_t val; 908 int qid, retrycnt; 909 910 for (;;) { 911 struct ieee80211_node *ni; 912 struct mbuf *m; 913 914 val = RAL_READ(sc, RT2661_STA_CSR4); 915 if (!(val & RT2661_TX_STAT_VALID)) 916 break; 917 918 /* retrieve the queue in which this frame was sent */ 919 qid = RT2661_TX_QID(val); 920 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 921 922 /* retrieve rate control algorithm context */ 923 data = &txq->data[txq->stat]; 924 m = data->m; 925 data->m = NULL; 926 ni = data->ni; 927 data->ni = NULL; 928 929 /* if no frame has been sent, ignore */ 930 if (ni == NULL) 931 continue; 932 933 rn = RT2661_NODE(ni); 934 935 switch (RT2661_TX_RESULT(val)) { 936 case RT2661_TX_SUCCESS: 937 retrycnt = RT2661_TX_RETRYCNT(val); 938 939 DPRINTFN(sc, 10, "data frame sent successfully after " 940 "%d retries\n", retrycnt); 941 if (data->rix != IEEE80211_FIXED_RATE_NONE) 942 ieee80211_amrr_tx_complete(&rn->amrr, 943 IEEE80211_AMRR_SUCCESS, retrycnt); 944 ifp->if_opackets++; 945 break; 946 947 case RT2661_TX_RETRY_FAIL: 948 retrycnt = RT2661_TX_RETRYCNT(val); 949 950 DPRINTFN(sc, 9, "%s\n", 951 "sending data frame failed (too much retries)"); 952 if (data->rix != IEEE80211_FIXED_RATE_NONE) 953 ieee80211_amrr_tx_complete(&rn->amrr, 954 IEEE80211_AMRR_FAILURE, retrycnt); 955 ifp->if_oerrors++; 956 break; 957 958 default: 959 /* other failure */ 960 device_printf(sc->sc_dev, 961 "sending data frame failed 0x%08x\n", val); 962 ifp->if_oerrors++; 963 } 964 965 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 966 967 txq->queued--; 968 if (++txq->stat >= txq->count) /* faster than % count */ 969 txq->stat = 0; 970 971 if (m->m_flags & M_TXCB) 972 ieee80211_process_callback(ni, m, 973 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS); 974 m_freem(m); 975 ieee80211_free_node(ni); 976 } 977 978 sc->sc_tx_timer = 0; 979 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 980 981 rt2661_start_locked(ifp); 982} 983 984static void 985rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 986{ 987 struct rt2661_tx_desc *desc; 988 struct rt2661_tx_data *data; 989 990 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 991 992 for (;;) { 993 desc = &txq->desc[txq->next]; 994 data = &txq->data[txq->next]; 995 996 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 997 !(le32toh(desc->flags) & RT2661_TX_VALID)) 998 break; 999 1000 bus_dmamap_sync(txq->data_dmat, data->map, 1001 BUS_DMASYNC_POSTWRITE); 1002 bus_dmamap_unload(txq->data_dmat, data->map); 1003 1004 /* descriptor is no longer valid */ 1005 desc->flags &= ~htole32(RT2661_TX_VALID); 1006 1007 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 1008 1009 if (++txq->next >= txq->count) /* faster than % count */ 1010 txq->next = 0; 1011 } 1012 1013 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1014} 1015 1016static void 1017rt2661_rx_intr(struct rt2661_softc *sc) 1018{ 1019 struct ifnet *ifp = sc->sc_ifp; 1020 struct ieee80211com *ic = ifp->if_l2com; 1021 struct rt2661_rx_desc *desc; 1022 struct rt2661_rx_data *data; 1023 bus_addr_t physaddr; 1024 struct ieee80211_frame *wh; 1025 struct ieee80211_node *ni; 1026 struct mbuf *mnew, *m; 1027 int error; 1028 1029 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1030 BUS_DMASYNC_POSTREAD); 1031 1032 for (;;) { 1033 int rssi; 1034 1035 desc = &sc->rxq.desc[sc->rxq.cur]; 1036 data = &sc->rxq.data[sc->rxq.cur]; 1037 1038 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1039 break; 1040 1041 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1042 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1043 /* 1044 * This should not happen since we did not request 1045 * to receive those frames when we filled TXRX_CSR0. 1046 */ 1047 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 1048 le32toh(desc->flags)); 1049 ifp->if_ierrors++; 1050 goto skip; 1051 } 1052 1053 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1054 ifp->if_ierrors++; 1055 goto skip; 1056 } 1057 1058 /* 1059 * Try to allocate a new mbuf for this ring element and load it 1060 * before processing the current mbuf. If the ring element 1061 * cannot be loaded, drop the received packet and reuse the old 1062 * mbuf. In the unlikely case that the old mbuf can't be 1063 * reloaded either, explicitly panic. 1064 */ 1065 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1066 if (mnew == NULL) { 1067 ifp->if_ierrors++; 1068 goto skip; 1069 } 1070 1071 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1072 BUS_DMASYNC_POSTREAD); 1073 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1074 1075 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1076 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1077 &physaddr, 0); 1078 if (error != 0) { 1079 m_freem(mnew); 1080 1081 /* try to reload the old mbuf */ 1082 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1083 mtod(data->m, void *), MCLBYTES, 1084 rt2661_dma_map_addr, &physaddr, 0); 1085 if (error != 0) { 1086 /* very unlikely that it will fail... */ 1087 panic("%s: could not load old rx mbuf", 1088 device_get_name(sc->sc_dev)); 1089 } 1090 ifp->if_ierrors++; 1091 goto skip; 1092 } 1093 1094 /* 1095 * New mbuf successfully loaded, update Rx ring and continue 1096 * processing. 1097 */ 1098 m = data->m; 1099 data->m = mnew; 1100 desc->physaddr = htole32(physaddr); 1101 1102 /* finalize mbuf */ 1103 m->m_pkthdr.rcvif = ifp; 1104 m->m_pkthdr.len = m->m_len = 1105 (le32toh(desc->flags) >> 16) & 0xfff; 1106 1107 rssi = rt2661_get_rssi(sc, desc->rssi); 1108 1109 if (bpf_peers_present(ifp->if_bpf)) { 1110 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1111 uint32_t tsf_lo, tsf_hi; 1112 1113 /* get timestamp (low and high 32 bits) */ 1114 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1115 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1116 1117 tap->wr_tsf = 1118 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1119 tap->wr_flags = 0; 1120 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1121 le32toh(desc->flags) & RT2661_RX_OFDM); 1122 tap->wr_antsignal = rssi < 0 ? 0 : rssi; 1123 1124 bpf_mtap2(ifp->if_bpf, tap, sc->sc_rxtap_len, m); 1125 } 1126 sc->sc_flags |= RAL_INPUT_RUNNING; 1127 RAL_UNLOCK(sc); 1128 wh = mtod(m, struct ieee80211_frame *); 1129 1130 /* send the frame to the 802.11 layer */ 1131 ni = ieee80211_find_rxnode(ic, 1132 (struct ieee80211_frame_min *)wh); 1133 if (ni != NULL) { 1134 /* Error happened during RSSI conversion. */ 1135 if (rssi < 0) 1136 rssi = -30; /* XXX ignored by net80211 */ 1137 1138 (void) ieee80211_input(ni, m, rssi, 1139 RT2661_NOISE_FLOOR, 0); 1140 ieee80211_free_node(ni); 1141 } else 1142 (void) ieee80211_input_all(ic, m, rssi, 1143 RT2661_NOISE_FLOOR, 0); 1144 1145 RAL_LOCK(sc); 1146 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1147 1148skip: desc->flags |= htole32(RT2661_RX_BUSY); 1149 1150 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1151 1152 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1153 } 1154 1155 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1156 BUS_DMASYNC_PREWRITE); 1157} 1158 1159/* ARGSUSED */ 1160static void 1161rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1162{ 1163 /* do nothing */ 1164} 1165 1166static void 1167rt2661_mcu_wakeup(struct rt2661_softc *sc) 1168{ 1169 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1170 1171 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1172 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1173 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1174 1175 /* send wakeup command to MCU */ 1176 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1177} 1178 1179static void 1180rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1181{ 1182 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1183 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1184} 1185 1186void 1187rt2661_intr(void *arg) 1188{ 1189 struct rt2661_softc *sc = arg; 1190 struct ifnet *ifp = sc->sc_ifp; 1191 uint32_t r1, r2; 1192 1193 RAL_LOCK(sc); 1194 1195 /* disable MAC and MCU interrupts */ 1196 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1197 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1198 1199 /* don't re-enable interrupts if we're shutting down */ 1200 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1201 RAL_UNLOCK(sc); 1202 return; 1203 } 1204 1205 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1206 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1207 1208 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1209 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1210 1211 if (r1 & RT2661_MGT_DONE) 1212 rt2661_tx_dma_intr(sc, &sc->mgtq); 1213 1214 if (r1 & RT2661_RX_DONE) 1215 rt2661_rx_intr(sc); 1216 1217 if (r1 & RT2661_TX0_DMA_DONE) 1218 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1219 1220 if (r1 & RT2661_TX1_DMA_DONE) 1221 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1222 1223 if (r1 & RT2661_TX2_DMA_DONE) 1224 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1225 1226 if (r1 & RT2661_TX3_DMA_DONE) 1227 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1228 1229 if (r1 & RT2661_TX_DONE) 1230 rt2661_tx_intr(sc); 1231 1232 if (r2 & RT2661_MCU_CMD_DONE) 1233 rt2661_mcu_cmd_intr(sc); 1234 1235 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1236 rt2661_mcu_beacon_expire(sc); 1237 1238 if (r2 & RT2661_MCU_WAKEUP) 1239 rt2661_mcu_wakeup(sc); 1240 1241 /* re-enable MAC and MCU interrupts */ 1242 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1243 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1244 1245 RAL_UNLOCK(sc); 1246} 1247 1248static void 1249rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1250 uint32_t flags, uint16_t xflags, int len, int rate, 1251 const bus_dma_segment_t *segs, int nsegs, int ac) 1252{ 1253 struct ifnet *ifp = sc->sc_ifp; 1254 struct ieee80211com *ic = ifp->if_l2com; 1255 uint16_t plcp_length; 1256 int i, remainder; 1257 1258 desc->flags = htole32(flags); 1259 desc->flags |= htole32(len << 16); 1260 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1261 1262 desc->xflags = htole16(xflags); 1263 desc->xflags |= htole16(nsegs << 13); 1264 1265 desc->wme = htole16( 1266 RT2661_QID(ac) | 1267 RT2661_AIFSN(2) | 1268 RT2661_LOGCWMIN(4) | 1269 RT2661_LOGCWMAX(10)); 1270 1271 /* 1272 * Remember in which queue this frame was sent. This field is driver 1273 * private data only. It will be made available by the NIC in STA_CSR4 1274 * on Tx interrupts. 1275 */ 1276 desc->qid = ac; 1277 1278 /* setup PLCP fields */ 1279 desc->plcp_signal = ieee80211_rate2plcp(rate); 1280 desc->plcp_service = 4; 1281 1282 len += IEEE80211_CRC_LEN; 1283 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 1284 desc->flags |= htole32(RT2661_TX_OFDM); 1285 1286 plcp_length = len & 0xfff; 1287 desc->plcp_length_hi = plcp_length >> 6; 1288 desc->plcp_length_lo = plcp_length & 0x3f; 1289 } else { 1290 plcp_length = (16 * len + rate - 1) / rate; 1291 if (rate == 22) { 1292 remainder = (16 * len) % 22; 1293 if (remainder != 0 && remainder < 7) 1294 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1295 } 1296 desc->plcp_length_hi = plcp_length >> 8; 1297 desc->plcp_length_lo = plcp_length & 0xff; 1298 1299 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1300 desc->plcp_signal |= 0x08; 1301 } 1302 1303 /* RT2x61 supports scatter with up to 5 segments */ 1304 for (i = 0; i < nsegs; i++) { 1305 desc->addr[i] = htole32(segs[i].ds_addr); 1306 desc->len [i] = htole16(segs[i].ds_len); 1307 } 1308} 1309 1310static int 1311rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1312 struct ieee80211_node *ni) 1313{ 1314 struct ieee80211vap *vap = ni->ni_vap; 1315 struct ieee80211com *ic = ni->ni_ic; 1316 struct ifnet *ifp = sc->sc_ifp; 1317 struct rt2661_tx_desc *desc; 1318 struct rt2661_tx_data *data; 1319 struct ieee80211_frame *wh; 1320 struct ieee80211_key *k; 1321 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1322 uint16_t dur; 1323 uint32_t flags = 0; /* XXX HWSEQ */ 1324 int nsegs, rate, error; 1325 1326 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1327 data = &sc->mgtq.data[sc->mgtq.cur]; 1328 1329 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1330 1331 wh = mtod(m0, struct ieee80211_frame *); 1332 1333 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1334 k = ieee80211_crypto_encap(ni, m0); 1335 if (k == NULL) { 1336 m_freem(m0); 1337 return ENOBUFS; 1338 } 1339 } 1340 1341 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1342 segs, &nsegs, 0); 1343 if (error != 0) { 1344 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1345 error); 1346 m_freem(m0); 1347 return error; 1348 } 1349 1350 if (bpf_peers_present(ifp->if_bpf)) { 1351 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1352 1353 tap->wt_flags = 0; 1354 tap->wt_rate = rate; 1355 1356 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0); 1357 } 1358 1359 data->m = m0; 1360 data->ni = ni; 1361 /* management frames are not taken into account for amrr */ 1362 data->rix = IEEE80211_FIXED_RATE_NONE; 1363 1364 wh = mtod(m0, struct ieee80211_frame *); 1365 1366 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1367 flags |= RT2661_TX_NEED_ACK; 1368 1369 dur = ieee80211_ack_duration(sc->sc_rates, 1370 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1371 *(uint16_t *)wh->i_dur = htole16(dur); 1372 1373 /* tell hardware to add timestamp in probe responses */ 1374 if ((wh->i_fc[0] & 1375 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1376 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1377 flags |= RT2661_TX_TIMESTAMP; 1378 } 1379 1380 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1381 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1382 1383 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1384 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1385 BUS_DMASYNC_PREWRITE); 1386 1387 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1388 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1389 1390 /* kick mgt */ 1391 sc->mgtq.queued++; 1392 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1393 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1394 1395 return 0; 1396} 1397 1398static int 1399rt2661_sendprot(struct rt2661_softc *sc, int ac, 1400 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1401{ 1402 struct ieee80211com *ic = ni->ni_ic; 1403 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1404 const struct ieee80211_frame *wh; 1405 struct rt2661_tx_desc *desc; 1406 struct rt2661_tx_data *data; 1407 struct mbuf *mprot; 1408 int protrate, ackrate, pktlen, flags, isshort, error; 1409 uint16_t dur; 1410 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1411 int nsegs; 1412 1413 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1414 ("protection %d", prot)); 1415 1416 wh = mtod(m, const struct ieee80211_frame *); 1417 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1418 1419 protrate = ieee80211_ctl_rate(sc->sc_rates, rate); 1420 ackrate = ieee80211_ack_rate(sc->sc_rates, rate); 1421 1422 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1423 dur = ieee80211_compute_duration(sc->sc_rates, pktlen, rate, isshort); 1424 + ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1425 flags = RT2661_TX_MORE_FRAG; 1426 if (prot == IEEE80211_PROT_RTSCTS) { 1427 /* NB: CTS is the same size as an ACK */ 1428 dur += ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1429 flags |= RT2661_TX_NEED_ACK; 1430 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1431 } else { 1432 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1433 } 1434 if (mprot == NULL) { 1435 /* XXX stat + msg */ 1436 return ENOBUFS; 1437 } 1438 1439 data = &txq->data[txq->cur]; 1440 desc = &txq->desc[txq->cur]; 1441 1442 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, 1443 &nsegs, 0); 1444 if (error != 0) { 1445 device_printf(sc->sc_dev, 1446 "could not map mbuf (error %d)\n", error); 1447 m_freem(mprot); 1448 return error; 1449 } 1450 1451 data->m = mprot; 1452 data->ni = ieee80211_ref_node(ni); 1453 /* ctl frames are not taken into account for amrr */ 1454 data->rix = IEEE80211_FIXED_RATE_NONE; 1455 1456 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1457 protrate, segs, 1, ac); 1458 1459 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1460 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1461 1462 txq->queued++; 1463 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1464 1465 return 0; 1466} 1467 1468static int 1469rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1470 struct ieee80211_node *ni, int ac) 1471{ 1472 struct ieee80211vap *vap = ni->ni_vap; 1473 struct ifnet *ifp = sc->sc_ifp; 1474 struct ieee80211com *ic = ifp->if_l2com; 1475 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1476 struct rt2661_tx_desc *desc; 1477 struct rt2661_tx_data *data; 1478 struct ieee80211_frame *wh; 1479 const struct ieee80211_txparam *tp; 1480 struct ieee80211_key *k; 1481 const struct chanAccParams *cap; 1482 struct mbuf *mnew; 1483 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1484 uint16_t dur; 1485 uint32_t flags; 1486 int error, nsegs, rate, noack = 0; 1487 1488 wh = mtod(m0, struct ieee80211_frame *); 1489 1490 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1491 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1492 rate = tp->mcastrate; 1493 } else if (m0->m_flags & M_EAPOL) { 1494 rate = tp->mgmtrate; 1495 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1496 rate = tp->ucastrate; 1497 } else { 1498 (void) ieee80211_amrr_choose(ni, &RT2661_NODE(ni)->amrr); 1499 rate = ni->ni_txrate; 1500 } 1501 rate &= IEEE80211_RATE_VAL; 1502 1503 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1504 cap = &ic->ic_wme.wme_chanParams; 1505 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1506 } 1507 1508 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1509 k = ieee80211_crypto_encap(ni, m0); 1510 if (k == NULL) { 1511 m_freem(m0); 1512 return ENOBUFS; 1513 } 1514 1515 /* packet header may have moved, reset our local pointer */ 1516 wh = mtod(m0, struct ieee80211_frame *); 1517 } 1518 1519 flags = 0; 1520 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1521 int prot = IEEE80211_PROT_NONE; 1522 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1523 prot = IEEE80211_PROT_RTSCTS; 1524 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1525 ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 1526 prot = ic->ic_protmode; 1527 if (prot != IEEE80211_PROT_NONE) { 1528 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1529 if (error) { 1530 m_freem(m0); 1531 return error; 1532 } 1533 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1534 } 1535 } 1536 1537 data = &txq->data[txq->cur]; 1538 desc = &txq->desc[txq->cur]; 1539 1540 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1541 &nsegs, 0); 1542 if (error != 0 && error != EFBIG) { 1543 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1544 error); 1545 m_freem(m0); 1546 return error; 1547 } 1548 if (error != 0) { 1549 mnew = m_defrag(m0, M_DONTWAIT); 1550 if (mnew == NULL) { 1551 device_printf(sc->sc_dev, 1552 "could not defragment mbuf\n"); 1553 m_freem(m0); 1554 return ENOBUFS; 1555 } 1556 m0 = mnew; 1557 1558 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1559 segs, &nsegs, 0); 1560 if (error != 0) { 1561 device_printf(sc->sc_dev, 1562 "could not map mbuf (error %d)\n", error); 1563 m_freem(m0); 1564 return error; 1565 } 1566 1567 /* packet header have moved, reset our local pointer */ 1568 wh = mtod(m0, struct ieee80211_frame *); 1569 } 1570 1571 if (bpf_peers_present(ifp->if_bpf)) { 1572 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1573 1574 tap->wt_flags = 0; 1575 tap->wt_rate = rate; 1576 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1577 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1578 1579 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0); 1580 } 1581 1582 data->m = m0; 1583 data->ni = ni; 1584 1585 /* remember link conditions for rate adaptation algorithm */ 1586 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1587 data->rix = ni->ni_txrate; 1588 /* XXX probably need last rssi value and not avg */ 1589 data->rssi = ic->ic_node_getrssi(ni); 1590 } else 1591 data->rix = IEEE80211_FIXED_RATE_NONE; 1592 1593 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1594 flags |= RT2661_TX_NEED_ACK; 1595 1596 dur = ieee80211_ack_duration(sc->sc_rates, 1597 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1598 *(uint16_t *)wh->i_dur = htole16(dur); 1599 } 1600 1601 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1602 nsegs, ac); 1603 1604 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1605 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1606 1607 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1608 m0->m_pkthdr.len, txq->cur, rate); 1609 1610 /* kick Tx */ 1611 txq->queued++; 1612 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1613 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1614 1615 return 0; 1616} 1617 1618static void 1619rt2661_start_locked(struct ifnet *ifp) 1620{ 1621 struct rt2661_softc *sc = ifp->if_softc; 1622 struct mbuf *m; 1623 struct ieee80211_node *ni; 1624 int ac; 1625 1626 RAL_LOCK_ASSERT(sc); 1627 1628 /* prevent management frames from being sent if we're not ready */ 1629 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || sc->sc_invalid) 1630 return; 1631 1632 for (;;) { 1633 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1634 if (m == NULL) 1635 break; 1636 1637 ac = M_WME_GETAC(m); 1638 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1639 /* there is no place left in this ring */ 1640 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1641 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1642 break; 1643 } 1644 1645 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1646 m = ieee80211_encap(ni, m); 1647 if (m == NULL) { 1648 ieee80211_free_node(ni); 1649 ifp->if_oerrors++; 1650 continue; 1651 } 1652 1653 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1654 ieee80211_free_node(ni); 1655 ifp->if_oerrors++; 1656 break; 1657 } 1658 1659 sc->sc_tx_timer = 5; 1660 } 1661} 1662 1663static void 1664rt2661_start(struct ifnet *ifp) 1665{ 1666 struct rt2661_softc *sc = ifp->if_softc; 1667 1668 RAL_LOCK(sc); 1669 rt2661_start_locked(ifp); 1670 RAL_UNLOCK(sc); 1671} 1672 1673static int 1674rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1675 const struct ieee80211_bpf_params *params) 1676{ 1677 struct ieee80211com *ic = ni->ni_ic; 1678 struct ifnet *ifp = ic->ic_ifp; 1679 struct rt2661_softc *sc = ifp->if_softc; 1680 1681 RAL_LOCK(sc); 1682 1683 /* prevent management frames from being sent if we're not ready */ 1684 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1685 RAL_UNLOCK(sc); 1686 m_freem(m); 1687 ieee80211_free_node(ni); 1688 return ENETDOWN; 1689 } 1690 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1691 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1692 RAL_UNLOCK(sc); 1693 m_freem(m); 1694 ieee80211_free_node(ni); 1695 return ENOBUFS; /* XXX */ 1696 } 1697 1698 ifp->if_opackets++; 1699 1700 /* 1701 * Legacy path; interpret frame contents to decide 1702 * precisely how to send the frame. 1703 * XXX raw path 1704 */ 1705 if (rt2661_tx_mgt(sc, m, ni) != 0) 1706 goto bad; 1707 sc->sc_tx_timer = 5; 1708 1709 RAL_UNLOCK(sc); 1710 1711 return 0; 1712bad: 1713 ifp->if_oerrors++; 1714 ieee80211_free_node(ni); 1715 RAL_UNLOCK(sc); 1716 return EIO; /* XXX */ 1717} 1718 1719static void 1720rt2661_watchdog(void *arg) 1721{ 1722 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1723 struct ifnet *ifp = sc->sc_ifp; 1724 1725 RAL_LOCK_ASSERT(sc); 1726 1727 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 1728 1729 if (sc->sc_invalid) /* card ejected */ 1730 return; 1731 1732 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1733 if_printf(ifp, "device timeout\n"); 1734 rt2661_init_locked(sc); 1735 ifp->if_oerrors++; 1736 /* NB: callout is reset in rt2661_init() */ 1737 return; 1738 } 1739 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1740} 1741 1742static int 1743rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1744{ 1745 struct rt2661_softc *sc = ifp->if_softc; 1746 struct ieee80211com *ic = ifp->if_l2com; 1747 struct ifreq *ifr = (struct ifreq *) data; 1748 int error = 0, startall = 0; 1749 1750 switch (cmd) { 1751 case SIOCSIFFLAGS: 1752 RAL_LOCK(sc); 1753 if (ifp->if_flags & IFF_UP) { 1754 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1755 rt2661_init_locked(sc); 1756 startall = 1; 1757 } else 1758 rt2661_update_promisc(ifp); 1759 } else { 1760 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1761 rt2661_stop_locked(sc); 1762 } 1763 RAL_UNLOCK(sc); 1764 if (startall) 1765 ieee80211_start_all(ic); 1766 break; 1767 case SIOCGIFMEDIA: 1768 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1769 break; 1770 case SIOCGIFADDR: 1771 error = ether_ioctl(ifp, cmd, data); 1772 break; 1773 default: 1774 error = EINVAL; 1775 break; 1776 } 1777 return error; 1778} 1779 1780static void 1781rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1782{ 1783 uint32_t tmp; 1784 int ntries; 1785 1786 for (ntries = 0; ntries < 100; ntries++) { 1787 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1788 break; 1789 DELAY(1); 1790 } 1791 if (ntries == 100) { 1792 device_printf(sc->sc_dev, "could not write to BBP\n"); 1793 return; 1794 } 1795 1796 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1797 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1798 1799 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1800} 1801 1802static uint8_t 1803rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1804{ 1805 uint32_t val; 1806 int ntries; 1807 1808 for (ntries = 0; ntries < 100; ntries++) { 1809 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1810 break; 1811 DELAY(1); 1812 } 1813 if (ntries == 100) { 1814 device_printf(sc->sc_dev, "could not read from BBP\n"); 1815 return 0; 1816 } 1817 1818 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1819 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1820 1821 for (ntries = 0; ntries < 100; ntries++) { 1822 val = RAL_READ(sc, RT2661_PHY_CSR3); 1823 if (!(val & RT2661_BBP_BUSY)) 1824 return val & 0xff; 1825 DELAY(1); 1826 } 1827 1828 device_printf(sc->sc_dev, "could not read from BBP\n"); 1829 return 0; 1830} 1831 1832static void 1833rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1834{ 1835 uint32_t tmp; 1836 int ntries; 1837 1838 for (ntries = 0; ntries < 100; ntries++) { 1839 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1840 break; 1841 DELAY(1); 1842 } 1843 if (ntries == 100) { 1844 device_printf(sc->sc_dev, "could not write to RF\n"); 1845 return; 1846 } 1847 1848 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1849 (reg & 3); 1850 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1851 1852 /* remember last written value in sc */ 1853 sc->rf_regs[reg] = val; 1854 1855 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1856} 1857 1858static int 1859rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1860{ 1861 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1862 return EIO; /* there is already a command pending */ 1863 1864 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1865 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1866 1867 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1868 1869 return 0; 1870} 1871 1872static void 1873rt2661_select_antenna(struct rt2661_softc *sc) 1874{ 1875 uint8_t bbp4, bbp77; 1876 uint32_t tmp; 1877 1878 bbp4 = rt2661_bbp_read(sc, 4); 1879 bbp77 = rt2661_bbp_read(sc, 77); 1880 1881 /* TBD */ 1882 1883 /* make sure Rx is disabled before switching antenna */ 1884 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1885 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1886 1887 rt2661_bbp_write(sc, 4, bbp4); 1888 rt2661_bbp_write(sc, 77, bbp77); 1889 1890 /* restore Rx filter */ 1891 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1892} 1893 1894/* 1895 * Enable multi-rate retries for frames sent at OFDM rates. 1896 * In 802.11b/g mode, allow fallback to CCK rates. 1897 */ 1898static void 1899rt2661_enable_mrr(struct rt2661_softc *sc) 1900{ 1901 struct ifnet *ifp = sc->sc_ifp; 1902 struct ieee80211com *ic = ifp->if_l2com; 1903 uint32_t tmp; 1904 1905 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1906 1907 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1908 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1909 tmp |= RT2661_MRR_CCK_FALLBACK; 1910 tmp |= RT2661_MRR_ENABLED; 1911 1912 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1913} 1914 1915static void 1916rt2661_set_txpreamble(struct rt2661_softc *sc) 1917{ 1918 struct ifnet *ifp = sc->sc_ifp; 1919 struct ieee80211com *ic = ifp->if_l2com; 1920 uint32_t tmp; 1921 1922 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1923 1924 tmp &= ~RT2661_SHORT_PREAMBLE; 1925 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1926 tmp |= RT2661_SHORT_PREAMBLE; 1927 1928 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1929} 1930 1931static void 1932rt2661_set_basicrates(struct rt2661_softc *sc, 1933 const struct ieee80211_rateset *rs) 1934{ 1935#define RV(r) ((r) & IEEE80211_RATE_VAL) 1936 struct ifnet *ifp = sc->sc_ifp; 1937 struct ieee80211com *ic = ifp->if_l2com; 1938 uint32_t mask = 0; 1939 uint8_t rate; 1940 int i, j; 1941 1942 for (i = 0; i < rs->rs_nrates; i++) { 1943 rate = rs->rs_rates[i]; 1944 1945 if (!(rate & IEEE80211_RATE_BASIC)) 1946 continue; 1947 1948 /* 1949 * Find h/w rate index. We know it exists because the rate 1950 * set has already been negotiated. 1951 */ 1952 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); 1953 1954 mask |= 1 << j; 1955 } 1956 1957 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1958 1959 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1960#undef RV 1961} 1962 1963/* 1964 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1965 * driver. 1966 */ 1967static void 1968rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1969{ 1970 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1971 uint32_t tmp; 1972 1973 /* update all BBP registers that depend on the band */ 1974 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1975 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1976 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1977 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1978 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1979 } 1980 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1981 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1982 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1983 } 1984 1985 rt2661_bbp_write(sc, 17, bbp17); 1986 rt2661_bbp_write(sc, 96, bbp96); 1987 rt2661_bbp_write(sc, 104, bbp104); 1988 1989 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1990 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1991 rt2661_bbp_write(sc, 75, 0x80); 1992 rt2661_bbp_write(sc, 86, 0x80); 1993 rt2661_bbp_write(sc, 88, 0x80); 1994 } 1995 1996 rt2661_bbp_write(sc, 35, bbp35); 1997 rt2661_bbp_write(sc, 97, bbp97); 1998 rt2661_bbp_write(sc, 98, bbp98); 1999 2000 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2001 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2002 if (IEEE80211_IS_CHAN_2GHZ(c)) 2003 tmp |= RT2661_PA_PE_2GHZ; 2004 else 2005 tmp |= RT2661_PA_PE_5GHZ; 2006 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2007} 2008 2009static void 2010rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2011{ 2012 struct ifnet *ifp = sc->sc_ifp; 2013 struct ieee80211com *ic = ifp->if_l2com; 2014 const struct rfprog *rfprog; 2015 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2016 int8_t power; 2017 u_int i, chan; 2018 2019 chan = ieee80211_chan2ieee(ic, c); 2020 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 2021 2022 sc->sc_rates = ieee80211_get_ratetable(c); 2023 2024 /* select the appropriate RF settings based on what EEPROM says */ 2025 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2026 2027 /* find the settings for this channel (we know it exists) */ 2028 for (i = 0; rfprog[i].chan != chan; i++); 2029 2030 power = sc->txpow[i]; 2031 if (power < 0) { 2032 bbp94 += power; 2033 power = 0; 2034 } else if (power > 31) { 2035 bbp94 += power - 31; 2036 power = 31; 2037 } 2038 2039 /* 2040 * If we are switching from the 2GHz band to the 5GHz band or 2041 * vice-versa, BBP registers need to be reprogrammed. 2042 */ 2043 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2044 rt2661_select_band(sc, c); 2045 rt2661_select_antenna(sc); 2046 } 2047 sc->sc_curchan = c; 2048 2049 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2050 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2051 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2052 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2053 2054 DELAY(200); 2055 2056 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2057 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2058 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2059 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2060 2061 DELAY(200); 2062 2063 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2064 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2065 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2066 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2067 2068 /* enable smart mode for MIMO-capable RFs */ 2069 bbp3 = rt2661_bbp_read(sc, 3); 2070 2071 bbp3 &= ~RT2661_SMART_MODE; 2072 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2073 bbp3 |= RT2661_SMART_MODE; 2074 2075 rt2661_bbp_write(sc, 3, bbp3); 2076 2077 if (bbp94 != RT2661_BBPR94_DEFAULT) 2078 rt2661_bbp_write(sc, 94, bbp94); 2079 2080 /* 5GHz radio needs a 1ms delay here */ 2081 if (IEEE80211_IS_CHAN_5GHZ(c)) 2082 DELAY(1000); 2083} 2084 2085static void 2086rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2087{ 2088 uint32_t tmp; 2089 2090 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2091 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2092 2093 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2094 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2095} 2096 2097static void 2098rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2099{ 2100 uint32_t tmp; 2101 2102 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2103 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2104 2105 tmp = addr[4] | addr[5] << 8; 2106 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2107} 2108 2109static void 2110rt2661_update_promisc(struct ifnet *ifp) 2111{ 2112 struct rt2661_softc *sc = ifp->if_softc; 2113 uint32_t tmp; 2114 2115 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2116 2117 tmp &= ~RT2661_DROP_NOT_TO_ME; 2118 if (!(ifp->if_flags & IFF_PROMISC)) 2119 tmp |= RT2661_DROP_NOT_TO_ME; 2120 2121 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2122 2123 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2124 "entering" : "leaving"); 2125} 2126 2127/* 2128 * Update QoS (802.11e) settings for each h/w Tx ring. 2129 */ 2130static int 2131rt2661_wme_update(struct ieee80211com *ic) 2132{ 2133 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2134 const struct wmeParams *wmep; 2135 2136 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2137 2138 /* XXX: not sure about shifts. */ 2139 /* XXX: the reference driver plays with AC_VI settings too. */ 2140 2141 /* update TxOp */ 2142 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2143 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2144 wmep[WME_AC_BK].wmep_txopLimit); 2145 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2146 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2147 wmep[WME_AC_VO].wmep_txopLimit); 2148 2149 /* update CWmin */ 2150 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2151 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2152 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2153 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2154 wmep[WME_AC_VO].wmep_logcwmin); 2155 2156 /* update CWmax */ 2157 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2158 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2159 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2160 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2161 wmep[WME_AC_VO].wmep_logcwmax); 2162 2163 /* update Aifsn */ 2164 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2165 wmep[WME_AC_BE].wmep_aifsn << 12 | 2166 wmep[WME_AC_BK].wmep_aifsn << 8 | 2167 wmep[WME_AC_VI].wmep_aifsn << 4 | 2168 wmep[WME_AC_VO].wmep_aifsn); 2169 2170 return 0; 2171} 2172 2173static void 2174rt2661_update_slot(struct ifnet *ifp) 2175{ 2176 struct rt2661_softc *sc = ifp->if_softc; 2177 struct ieee80211com *ic = ifp->if_l2com; 2178 uint8_t slottime; 2179 uint32_t tmp; 2180 2181 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2182 2183 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2184 tmp = (tmp & ~0xff) | slottime; 2185 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2186} 2187 2188static const char * 2189rt2661_get_rf(int rev) 2190{ 2191 switch (rev) { 2192 case RT2661_RF_5225: return "RT5225"; 2193 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2194 case RT2661_RF_2527: return "RT2527"; 2195 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2196 default: return "unknown"; 2197 } 2198} 2199 2200static void 2201rt2661_read_eeprom(struct rt2661_softc *sc, struct ieee80211com *ic) 2202{ 2203 uint16_t val; 2204 int i; 2205 2206 /* read MAC address */ 2207 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2208 ic->ic_myaddr[0] = val & 0xff; 2209 ic->ic_myaddr[1] = val >> 8; 2210 2211 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2212 ic->ic_myaddr[2] = val & 0xff; 2213 ic->ic_myaddr[3] = val >> 8; 2214 2215 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2216 ic->ic_myaddr[4] = val & 0xff; 2217 ic->ic_myaddr[5] = val >> 8; 2218 2219 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2220 /* XXX: test if different from 0xffff? */ 2221 sc->rf_rev = (val >> 11) & 0x1f; 2222 sc->hw_radio = (val >> 10) & 0x1; 2223 sc->rx_ant = (val >> 4) & 0x3; 2224 sc->tx_ant = (val >> 2) & 0x3; 2225 sc->nb_ant = val & 0x3; 2226 2227 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2228 2229 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2230 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2231 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2232 2233 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2234 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2235 2236 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2237 if ((val & 0xff) != 0xff) 2238 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2239 2240 /* Only [-10, 10] is valid */ 2241 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2242 sc->rssi_2ghz_corr = 0; 2243 2244 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2245 if ((val & 0xff) != 0xff) 2246 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2247 2248 /* Only [-10, 10] is valid */ 2249 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2250 sc->rssi_5ghz_corr = 0; 2251 2252 /* adjust RSSI correction for external low-noise amplifier */ 2253 if (sc->ext_2ghz_lna) 2254 sc->rssi_2ghz_corr -= 14; 2255 if (sc->ext_5ghz_lna) 2256 sc->rssi_5ghz_corr -= 14; 2257 2258 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2259 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2260 2261 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2262 if ((val >> 8) != 0xff) 2263 sc->rfprog = (val >> 8) & 0x3; 2264 if ((val & 0xff) != 0xff) 2265 sc->rffreq = val & 0xff; 2266 2267 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2268 2269 /* read Tx power for all a/b/g channels */ 2270 for (i = 0; i < 19; i++) { 2271 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2272 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2273 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2274 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2275 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2276 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2277 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2278 } 2279 2280 /* read vendor-specific BBP values */ 2281 for (i = 0; i < 16; i++) { 2282 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2283 if (val == 0 || val == 0xffff) 2284 continue; /* skip invalid entries */ 2285 sc->bbp_prom[i].reg = val >> 8; 2286 sc->bbp_prom[i].val = val & 0xff; 2287 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2288 sc->bbp_prom[i].val); 2289 } 2290} 2291 2292static int 2293rt2661_bbp_init(struct rt2661_softc *sc) 2294{ 2295#define N(a) (sizeof (a) / sizeof ((a)[0])) 2296 int i, ntries; 2297 uint8_t val; 2298 2299 /* wait for BBP to be ready */ 2300 for (ntries = 0; ntries < 100; ntries++) { 2301 val = rt2661_bbp_read(sc, 0); 2302 if (val != 0 && val != 0xff) 2303 break; 2304 DELAY(100); 2305 } 2306 if (ntries == 100) { 2307 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2308 return EIO; 2309 } 2310 2311 /* initialize BBP registers to default values */ 2312 for (i = 0; i < N(rt2661_def_bbp); i++) { 2313 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2314 rt2661_def_bbp[i].val); 2315 } 2316 2317 /* write vendor-specific BBP values (from EEPROM) */ 2318 for (i = 0; i < 16; i++) { 2319 if (sc->bbp_prom[i].reg == 0) 2320 continue; 2321 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2322 } 2323 2324 return 0; 2325#undef N 2326} 2327 2328static void 2329rt2661_init_locked(struct rt2661_softc *sc) 2330{ 2331#define N(a) (sizeof (a) / sizeof ((a)[0])) 2332 struct ifnet *ifp = sc->sc_ifp; 2333 struct ieee80211com *ic = ifp->if_l2com; 2334 uint32_t tmp, sta[3]; 2335 int i, error, ntries; 2336 2337 RAL_LOCK_ASSERT(sc); 2338 2339 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2340 error = rt2661_load_microcode(sc); 2341 if (error != 0) { 2342 if_printf(ifp, 2343 "%s: could not load 8051 microcode, error %d\n", 2344 __func__, error); 2345 return; 2346 } 2347 sc->sc_flags |= RAL_FW_LOADED; 2348 } 2349 2350 rt2661_stop_locked(sc); 2351 2352 /* initialize Tx rings */ 2353 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2354 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2355 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2356 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2357 2358 /* initialize Mgt ring */ 2359 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2360 2361 /* initialize Rx ring */ 2362 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2363 2364 /* initialize Tx rings sizes */ 2365 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2366 RT2661_TX_RING_COUNT << 24 | 2367 RT2661_TX_RING_COUNT << 16 | 2368 RT2661_TX_RING_COUNT << 8 | 2369 RT2661_TX_RING_COUNT); 2370 2371 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2372 RT2661_TX_DESC_WSIZE << 16 | 2373 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2374 RT2661_MGT_RING_COUNT); 2375 2376 /* initialize Rx rings */ 2377 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2378 RT2661_RX_DESC_BACK << 16 | 2379 RT2661_RX_DESC_WSIZE << 8 | 2380 RT2661_RX_RING_COUNT); 2381 2382 /* XXX: some magic here */ 2383 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2384 2385 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2386 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2387 2388 /* load base address of Rx ring */ 2389 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2390 2391 /* initialize MAC registers to default values */ 2392 for (i = 0; i < N(rt2661_def_mac); i++) 2393 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2394 2395 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2396 rt2661_set_macaddr(sc, ic->ic_myaddr); 2397 2398 /* set host ready */ 2399 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2400 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2401 2402 /* wait for BBP/RF to wakeup */ 2403 for (ntries = 0; ntries < 1000; ntries++) { 2404 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2405 break; 2406 DELAY(1000); 2407 } 2408 if (ntries == 1000) { 2409 printf("timeout waiting for BBP/RF to wakeup\n"); 2410 rt2661_stop_locked(sc); 2411 return; 2412 } 2413 2414 if (rt2661_bbp_init(sc) != 0) { 2415 rt2661_stop_locked(sc); 2416 return; 2417 } 2418 2419 /* select default channel */ 2420 sc->sc_curchan = ic->ic_curchan; 2421 rt2661_select_band(sc, sc->sc_curchan); 2422 rt2661_select_antenna(sc); 2423 rt2661_set_chan(sc, sc->sc_curchan); 2424 2425 /* update Rx filter */ 2426 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2427 2428 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2429 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2430 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2431 RT2661_DROP_ACKCTS; 2432 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2433 tmp |= RT2661_DROP_TODS; 2434 if (!(ifp->if_flags & IFF_PROMISC)) 2435 tmp |= RT2661_DROP_NOT_TO_ME; 2436 } 2437 2438 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2439 2440 /* clear STA registers */ 2441 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2442 2443 /* initialize ASIC */ 2444 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2445 2446 /* clear any pending interrupt */ 2447 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2448 2449 /* enable interrupts */ 2450 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2451 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2452 2453 /* kick Rx */ 2454 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2455 2456 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2457 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2458 2459 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2460#undef N 2461} 2462 2463static void 2464rt2661_init(void *priv) 2465{ 2466 struct rt2661_softc *sc = priv; 2467 struct ifnet *ifp = sc->sc_ifp; 2468 struct ieee80211com *ic = ifp->if_l2com; 2469 2470 RAL_LOCK(sc); 2471 rt2661_init_locked(sc); 2472 RAL_UNLOCK(sc); 2473 2474 ieee80211_start_all(ic); 2475} 2476 2477void 2478rt2661_stop_locked(struct rt2661_softc *sc) 2479{ 2480 struct ifnet *ifp = sc->sc_ifp; 2481 uint32_t tmp; 2482 volatile int *flags = &sc->sc_flags; 2483 2484 while (*flags & RAL_INPUT_RUNNING) 2485 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2486 2487 callout_stop(&sc->watchdog_ch); 2488 sc->sc_tx_timer = 0; 2489 2490 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2491 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2492 2493 /* abort Tx (for all 5 Tx rings) */ 2494 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2495 2496 /* disable Rx (value remains after reset!) */ 2497 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2498 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2499 2500 /* reset ASIC */ 2501 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2502 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2503 2504 /* disable interrupts */ 2505 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2506 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2507 2508 /* clear any pending interrupt */ 2509 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2510 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2511 2512 /* reset Tx and Rx rings */ 2513 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2514 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2515 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2516 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2517 rt2661_reset_tx_ring(sc, &sc->mgtq); 2518 rt2661_reset_rx_ring(sc, &sc->rxq); 2519 } 2520} 2521 2522void 2523rt2661_stop(void *priv) 2524{ 2525 struct rt2661_softc *sc = priv; 2526 2527 RAL_LOCK(sc); 2528 rt2661_stop_locked(sc); 2529 RAL_UNLOCK(sc); 2530} 2531 2532static int 2533rt2661_load_microcode(struct rt2661_softc *sc) 2534{ 2535 struct ifnet *ifp = sc->sc_ifp; 2536 const struct firmware *fp; 2537 const char *imagename; 2538 int ntries, error; 2539 2540 RAL_LOCK_ASSERT(sc); 2541 2542 switch (sc->sc_id) { 2543 case 0x0301: imagename = "rt2561sfw"; break; 2544 case 0x0302: imagename = "rt2561fw"; break; 2545 case 0x0401: imagename = "rt2661fw"; break; 2546 default: 2547 if_printf(ifp, "%s: unexpected pci device id 0x%x, " 2548 "don't know how to retrieve firmware\n", 2549 __func__, sc->sc_id); 2550 return EINVAL; 2551 } 2552 RAL_UNLOCK(sc); 2553 fp = firmware_get(imagename); 2554 RAL_LOCK(sc); 2555 if (fp == NULL) { 2556 if_printf(ifp, "%s: unable to retrieve firmware image %s\n", 2557 __func__, imagename); 2558 return EINVAL; 2559 } 2560 2561 /* 2562 * Load 8051 microcode into NIC. 2563 */ 2564 /* reset 8051 */ 2565 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2566 2567 /* cancel any pending Host to MCU command */ 2568 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2569 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2570 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2571 2572 /* write 8051's microcode */ 2573 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2574 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2575 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2576 2577 /* kick 8051's ass */ 2578 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2579 2580 /* wait for 8051 to initialize */ 2581 for (ntries = 0; ntries < 500; ntries++) { 2582 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2583 break; 2584 DELAY(100); 2585 } 2586 if (ntries == 500) { 2587 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n", 2588 __func__); 2589 error = EIO; 2590 } else 2591 error = 0; 2592 2593 firmware_put(fp, FIRMWARE_UNLOAD); 2594 return error; 2595} 2596 2597#ifdef notyet 2598/* 2599 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2600 * false CCA count. This function is called periodically (every seconds) when 2601 * in the RUN state. Values taken from the reference driver. 2602 */ 2603static void 2604rt2661_rx_tune(struct rt2661_softc *sc) 2605{ 2606 uint8_t bbp17; 2607 uint16_t cca; 2608 int lo, hi, dbm; 2609 2610 /* 2611 * Tuning range depends on operating band and on the presence of an 2612 * external low-noise amplifier. 2613 */ 2614 lo = 0x20; 2615 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2616 lo += 0x08; 2617 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2618 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2619 lo += 0x10; 2620 hi = lo + 0x20; 2621 2622 /* retrieve false CCA count since last call (clear on read) */ 2623 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2624 2625 if (dbm >= -35) { 2626 bbp17 = 0x60; 2627 } else if (dbm >= -58) { 2628 bbp17 = hi; 2629 } else if (dbm >= -66) { 2630 bbp17 = lo + 0x10; 2631 } else if (dbm >= -74) { 2632 bbp17 = lo + 0x08; 2633 } else { 2634 /* RSSI < -74dBm, tune using false CCA count */ 2635 2636 bbp17 = sc->bbp17; /* current value */ 2637 2638 hi -= 2 * (-74 - dbm); 2639 if (hi < lo) 2640 hi = lo; 2641 2642 if (bbp17 > hi) { 2643 bbp17 = hi; 2644 2645 } else if (cca > 512) { 2646 if (++bbp17 > hi) 2647 bbp17 = hi; 2648 } else if (cca < 100) { 2649 if (--bbp17 < lo) 2650 bbp17 = lo; 2651 } 2652 } 2653 2654 if (bbp17 != sc->bbp17) { 2655 rt2661_bbp_write(sc, 17, bbp17); 2656 sc->bbp17 = bbp17; 2657 } 2658} 2659 2660/* 2661 * Enter/Leave radar detection mode. 2662 * This is for 802.11h additional regulatory domains. 2663 */ 2664static void 2665rt2661_radar_start(struct rt2661_softc *sc) 2666{ 2667 uint32_t tmp; 2668 2669 /* disable Rx */ 2670 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2671 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2672 2673 rt2661_bbp_write(sc, 82, 0x20); 2674 rt2661_bbp_write(sc, 83, 0x00); 2675 rt2661_bbp_write(sc, 84, 0x40); 2676 2677 /* save current BBP registers values */ 2678 sc->bbp18 = rt2661_bbp_read(sc, 18); 2679 sc->bbp21 = rt2661_bbp_read(sc, 21); 2680 sc->bbp22 = rt2661_bbp_read(sc, 22); 2681 sc->bbp16 = rt2661_bbp_read(sc, 16); 2682 sc->bbp17 = rt2661_bbp_read(sc, 17); 2683 sc->bbp64 = rt2661_bbp_read(sc, 64); 2684 2685 rt2661_bbp_write(sc, 18, 0xff); 2686 rt2661_bbp_write(sc, 21, 0x3f); 2687 rt2661_bbp_write(sc, 22, 0x3f); 2688 rt2661_bbp_write(sc, 16, 0xbd); 2689 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2690 rt2661_bbp_write(sc, 64, 0x21); 2691 2692 /* restore Rx filter */ 2693 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2694} 2695 2696static int 2697rt2661_radar_stop(struct rt2661_softc *sc) 2698{ 2699 uint8_t bbp66; 2700 2701 /* read radar detection result */ 2702 bbp66 = rt2661_bbp_read(sc, 66); 2703 2704 /* restore BBP registers values */ 2705 rt2661_bbp_write(sc, 16, sc->bbp16); 2706 rt2661_bbp_write(sc, 17, sc->bbp17); 2707 rt2661_bbp_write(sc, 18, sc->bbp18); 2708 rt2661_bbp_write(sc, 21, sc->bbp21); 2709 rt2661_bbp_write(sc, 22, sc->bbp22); 2710 rt2661_bbp_write(sc, 64, sc->bbp64); 2711 2712 return bbp66 == 1; 2713} 2714#endif 2715 2716static int 2717rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2718{ 2719 struct ieee80211com *ic = vap->iv_ic; 2720 struct ieee80211_beacon_offsets bo; 2721 struct rt2661_tx_desc desc; 2722 struct mbuf *m0; 2723 int rate; 2724 2725 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo); 2726 if (m0 == NULL) { 2727 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2728 return ENOBUFS; 2729 } 2730 2731 /* send beacons at the lowest available rate */ 2732 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2733 2734 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2735 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2736 2737 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2738 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2739 2740 /* copy beacon header and payload into NIC memory */ 2741 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2742 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2743 2744 m_freem(m0); 2745 2746 return 0; 2747} 2748 2749/* 2750 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2751 * and HostAP operating modes. 2752 */ 2753static void 2754rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2755{ 2756 struct ifnet *ifp = sc->sc_ifp; 2757 struct ieee80211com *ic = ifp->if_l2com; 2758 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2759 uint32_t tmp; 2760 2761 if (vap->iv_opmode != IEEE80211_M_STA) { 2762 /* 2763 * Change default 16ms TBTT adjustment to 8ms. 2764 * Must be done before enabling beacon generation. 2765 */ 2766 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2767 } 2768 2769 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2770 2771 /* set beacon interval (in 1/16ms unit) */ 2772 tmp |= vap->iv_bss->ni_intval * 16; 2773 2774 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2775 if (vap->iv_opmode == IEEE80211_M_STA) 2776 tmp |= RT2661_TSF_MODE(1); 2777 else 2778 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2779 2780 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2781} 2782 2783/* 2784 * Retrieve the "Received Signal Strength Indicator" from the raw values 2785 * contained in Rx descriptors. The computation depends on which band the 2786 * frame was received. Correction values taken from the reference driver. 2787 */ 2788static int 2789rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2790{ 2791 int lna, agc, rssi; 2792 2793 lna = (raw >> 5) & 0x3; 2794 agc = raw & 0x1f; 2795 2796 if (lna == 0) { 2797 /* 2798 * No mapping available. 2799 * 2800 * NB: Since RSSI is relative to noise floor, -1 is 2801 * adequate for caller to know error happened. 2802 */ 2803 return -1; 2804 } 2805 2806 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2807 2808 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2809 rssi += sc->rssi_2ghz_corr; 2810 2811 if (lna == 1) 2812 rssi -= 64; 2813 else if (lna == 2) 2814 rssi -= 74; 2815 else if (lna == 3) 2816 rssi -= 90; 2817 } else { 2818 rssi += sc->rssi_5ghz_corr; 2819 2820 if (lna == 1) 2821 rssi -= 64; 2822 else if (lna == 2) 2823 rssi -= 86; 2824 else if (lna == 3) 2825 rssi -= 100; 2826 } 2827 return rssi; 2828} 2829 2830static void 2831rt2661_scan_start(struct ieee80211com *ic) 2832{ 2833 struct ifnet *ifp = ic->ic_ifp; 2834 struct rt2661_softc *sc = ifp->if_softc; 2835 uint32_t tmp; 2836 2837 /* abort TSF synchronization */ 2838 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2839 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2840 rt2661_set_bssid(sc, ifp->if_broadcastaddr); 2841} 2842 2843static void 2844rt2661_scan_end(struct ieee80211com *ic) 2845{ 2846 struct ifnet *ifp = ic->ic_ifp; 2847 struct rt2661_softc *sc = ifp->if_softc; 2848 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2849 2850 rt2661_enable_tsf_sync(sc); 2851 /* XXX keep local copy */ 2852 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2853} 2854 2855static void 2856rt2661_set_channel(struct ieee80211com *ic) 2857{ 2858 struct ifnet *ifp = ic->ic_ifp; 2859 struct rt2661_softc *sc = ifp->if_softc; 2860 2861 RAL_LOCK(sc); 2862 rt2661_set_chan(sc, ic->ic_curchan); 2863 2864 sc->sc_txtap.wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2865 sc->sc_txtap.wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2866 sc->sc_rxtap.wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2867 sc->sc_rxtap.wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2868 RAL_UNLOCK(sc); 2869 2870} 2871