1250661Sdavidcs/* 2250661Sdavidcs * Copyright (c) 2013-2014 Qlogic Corporation 3250661Sdavidcs * All rights reserved. 4250661Sdavidcs * 5250661Sdavidcs * Redistribution and use in source and binary forms, with or without 6250661Sdavidcs * modification, are permitted provided that the following conditions 7250661Sdavidcs * are met: 8250661Sdavidcs * 9250661Sdavidcs * 1. Redistributions of source code must retain the above copyright 10250661Sdavidcs * notice, this list of conditions and the following disclaimer. 11250661Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12250661Sdavidcs * notice, this list of conditions and the following disclaimer in the 13250661Sdavidcs * documentation and/or other materials provided with the distribution. 14250661Sdavidcs * 15250661Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16250661Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17250661Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18250661Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19250661Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20250661Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21250661Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22250661Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23250661Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24250661Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25250661Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26250661Sdavidcs * 27250661Sdavidcs * $FreeBSD$ 28250661Sdavidcs */ 29250661Sdavidcs/* 30250661Sdavidcs * File: ql_hw.h 31250661Sdavidcs * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32250661Sdavidcs */ 33250661Sdavidcs#ifndef _QL_HW_H_ 34250661Sdavidcs#define _QL_HW_H_ 35250661Sdavidcs 36250661Sdavidcs/* 37250661Sdavidcs * PCIe Registers; Direct Mapped; Offsets from BAR0 38250661Sdavidcs */ 39250661Sdavidcs 40250661Sdavidcs/* 41250661Sdavidcs * Register offsets for QLE8030 42250661Sdavidcs */ 43250661Sdavidcs 44250661Sdavidcs/* 45250661Sdavidcs * Firmware Mailbox Registers 46250661Sdavidcs * 0 thru 511; offsets 0x800 thru 0xFFC; 32bits each 47250661Sdavidcs */ 48250661Sdavidcs#define Q8_FW_MBOX0 0x00000800 49250661Sdavidcs#define Q8_FW_MBOX511 0x00000FFC 50250661Sdavidcs 51250661Sdavidcs/* 52250661Sdavidcs * Host Mailbox Registers 53250661Sdavidcs * 0 thru 511; offsets 0x000 thru 0x7FC; 32bits each 54250661Sdavidcs */ 55250661Sdavidcs#define Q8_HOST_MBOX0 0x00000000 56250661Sdavidcs#define Q8_HOST_MBOX511 0x000007FC 57250661Sdavidcs 58250661Sdavidcs#define Q8_MBOX_INT_ENABLE 0x00001000 59250661Sdavidcs#define Q8_MBOX_INT_MASK_MSIX 0x00001200 60250661Sdavidcs#define Q8_MBOX_INT_LEGACY 0x00003010 61250661Sdavidcs 62250661Sdavidcs#define Q8_HOST_MBOX_CNTRL 0x00003038 63250661Sdavidcs#define Q8_FW_MBOX_CNTRL 0x0000303C 64250661Sdavidcs 65250661Sdavidcs#define Q8_PEG_HALT_STATUS1 0x000034A8 66250661Sdavidcs#define Q8_PEG_HALT_STATUS2 0x000034AC 67250661Sdavidcs#define Q8_FIRMWARE_HEARTBEAT 0x000034B0 68250661Sdavidcs 69250661Sdavidcs#define Q8_FLASH_LOCK_ID 0x00003500 70250661Sdavidcs#define Q8_DRIVER_LOCK_ID 0x00003504 71250661Sdavidcs#define Q8_FW_CAPABILITIES 0x00003528 72250661Sdavidcs 73250661Sdavidcs#define Q8_FW_VER_MAJOR 0x00003550 74250661Sdavidcs#define Q8_FW_VER_MINOR 0x00003554 75250661Sdavidcs#define Q8_FW_VER_SUB 0x00003558 76250661Sdavidcs 77250661Sdavidcs#define Q8_BOOTLD_ADDR 0x0000355C 78250661Sdavidcs#define Q8_BOOTLD_SIZE 0x00003560 79250661Sdavidcs 80250661Sdavidcs#define Q8_FW_IMAGE_ADDR 0x00003564 81250661Sdavidcs#define Q8_FW_BUILD_NUMBER 0x00003568 82250661Sdavidcs#define Q8_FW_IMAGE_VALID 0x000035FC 83250661Sdavidcs 84250661Sdavidcs#define Q8_CMDPEG_STATE 0x00003650 85250661Sdavidcs 86250661Sdavidcs#define Q8_LINK_STATE 0x00003698 87250661Sdavidcs#define Q8_LINK_STATE_2 0x0000369C 88250661Sdavidcs 89250661Sdavidcs#define Q8_LINK_SPEED_0 0x000036E0 90250661Sdavidcs#define Q8_LINK_SPEED_1 0x000036E4 91250661Sdavidcs#define Q8_LINK_SPEED_2 0x000036E8 92250661Sdavidcs#define Q8_LINK_SPEED_3 0x000036EC 93250661Sdavidcs 94250661Sdavidcs#define Q8_MAX_LINK_SPEED_0 0x000036F0 95250661Sdavidcs#define Q8_MAX_LINK_SPEED_1 0x000036F4 96250661Sdavidcs#define Q8_MAX_LINK_SPEED_2 0x000036F8 97250661Sdavidcs#define Q8_MAX_LINK_SPEED_3 0x000036FC 98250661Sdavidcs 99250661Sdavidcs#define Q8_ASIC_TEMPERATURE 0x000037B4 100250661Sdavidcs 101250661Sdavidcs/* 102250661Sdavidcs * CRB Window Registers 103250661Sdavidcs * 0 thru 15; offsets 0x3800 thru 0x383C; 32bits each 104250661Sdavidcs */ 105250661Sdavidcs#define Q8_CRB_WINDOW_PF0 0x00003800 106250661Sdavidcs#define Q8_CRB_WINDOW_PF15 0x0000383C 107250661Sdavidcs 108250661Sdavidcs#define Q8_FLASH_LOCK 0x00003850 109250661Sdavidcs#define Q8_FLASH_UNLOCK 0x00003854 110250661Sdavidcs 111250661Sdavidcs#define Q8_DRIVER_LOCK 0x00003868 112250661Sdavidcs#define Q8_DRIVER_UNLOCK 0x0000386C 113250661Sdavidcs 114250661Sdavidcs#define Q8_LEGACY_INT_PTR 0x000038C0 115250661Sdavidcs#define Q8_LEGACY_INT_TRIG 0x000038C4 116250661Sdavidcs#define Q8_LEGACY_INT_MASK 0x000038C8 117250661Sdavidcs 118250661Sdavidcs#define Q8_WILD_CARD 0x000038F0 119250661Sdavidcs#define Q8_INFORMANT 0x000038FC 120250661Sdavidcs 121250661Sdavidcs/* 122250661Sdavidcs * Ethernet Interface Specific Registers 123250661Sdavidcs */ 124250661Sdavidcs#define Q8_DRIVER_OP_MODE 0x00003570 125250661Sdavidcs#define Q8_API_VERSION 0x0000356C 126250661Sdavidcs#define Q8_NPAR_STATE 0x0000359C 127250661Sdavidcs 128250661Sdavidcs/* 129250661Sdavidcs * End of PCIe Registers; Direct Mapped; Offsets from BAR0 130250661Sdavidcs */ 131250661Sdavidcs 132250661Sdavidcs/* 133250661Sdavidcs * Indirect Registers 134250661Sdavidcs */ 135250661Sdavidcs#define Q8_LED_DUAL_0 0x28084C80 136250661Sdavidcs#define Q8_LED_SINGLE_0 0x28084C90 137250661Sdavidcs 138250661Sdavidcs#define Q8_LED_DUAL_1 0x28084CA0 139250661Sdavidcs#define Q8_LED_SINGLE_1 0x28084CB0 140250661Sdavidcs 141250661Sdavidcs#define Q8_LED_DUAL_2 0x28084CC0 142250661Sdavidcs#define Q8_LED_SINGLE_2 0x28084CD0 143250661Sdavidcs 144250661Sdavidcs#define Q8_LED_DUAL_3 0x28084CE0 145250661Sdavidcs#define Q8_LED_SINGLE_3 0x28084CF0 146250661Sdavidcs 147250661Sdavidcs#define Q8_GPIO_1 0x28084D00 148250661Sdavidcs#define Q8_GPIO_2 0x28084D10 149250661Sdavidcs#define Q8_GPIO_3 0x28084D20 150250661Sdavidcs#define Q8_GPIO_4 0x28084D40 151250661Sdavidcs#define Q8_GPIO_5 0x28084D50 152250661Sdavidcs#define Q8_GPIO_6 0x28084D60 153250661Sdavidcs#define Q8_GPIO_7 0x42100060 154250661Sdavidcs#define Q8_GPIO_8 0x42100064 155250661Sdavidcs 156250661Sdavidcs#define Q8_FLASH_SPI_STATUS 0x2808E010 157250661Sdavidcs#define Q8_FLASH_SPI_CONTROL 0x2808E014 158250661Sdavidcs 159250661Sdavidcs#define Q8_FLASH_STATUS 0x42100004 160250661Sdavidcs#define Q8_FLASH_CONTROL 0x42110004 161250661Sdavidcs#define Q8_FLASH_ADDRESS 0x42110008 162250661Sdavidcs#define Q8_FLASH_WR_DATA 0x4211000C 163250661Sdavidcs#define Q8_FLASH_RD_DATA 0x42110018 164250661Sdavidcs 165250661Sdavidcs#define Q8_FLASH_DIRECT_WINDOW 0x42110030 166250661Sdavidcs#define Q8_FLASH_DIRECT_DATA 0x42150000 167250661Sdavidcs 168250661Sdavidcs#define Q8_MS_CNTRL 0x41000090 169250661Sdavidcs 170250661Sdavidcs#define Q8_MS_ADDR_LO 0x41000094 171250661Sdavidcs#define Q8_MS_ADDR_HI 0x41000098 172250661Sdavidcs 173250661Sdavidcs#define Q8_MS_WR_DATA_0_31 0x410000A0 174250661Sdavidcs#define Q8_MS_WR_DATA_32_63 0x410000A4 175250661Sdavidcs#define Q8_MS_WR_DATA_64_95 0x410000B0 176250661Sdavidcs#define Q8_MS_WR_DATA_96_127 0x410000B4 177250661Sdavidcs 178250661Sdavidcs#define Q8_MS_RD_DATA_0_31 0x410000A8 179250661Sdavidcs#define Q8_MS_RD_DATA_32_63 0x410000AC 180250661Sdavidcs#define Q8_MS_RD_DATA_64_95 0x410000B8 181250661Sdavidcs#define Q8_MS_RD_DATA_96_127 0x410000BC 182250661Sdavidcs 183250661Sdavidcs#define Q8_CRB_PEG_0 0x3400003c 184250661Sdavidcs#define Q8_CRB_PEG_1 0x3410003c 185250661Sdavidcs#define Q8_CRB_PEG_2 0x3420003c 186250661Sdavidcs#define Q8_CRB_PEG_3 0x3430003c 187250661Sdavidcs#define Q8_CRB_PEG_4 0x34B0003c 188250661Sdavidcs 189250661Sdavidcs/* 190250661Sdavidcs * Macros for reading and writing registers 191250661Sdavidcs */ 192250661Sdavidcs 193250661Sdavidcs#if defined(__i386__) || defined(__amd64__) 194250661Sdavidcs#define Q8_MB() __asm volatile("mfence" ::: "memory") 195250661Sdavidcs#define Q8_WMB() __asm volatile("sfence" ::: "memory") 196250661Sdavidcs#define Q8_RMB() __asm volatile("lfence" ::: "memory") 197250661Sdavidcs#else 198250661Sdavidcs#define Q8_MB() 199250661Sdavidcs#define Q8_WMB() 200250661Sdavidcs#define Q8_RMB() 201250661Sdavidcs#endif 202250661Sdavidcs 203250661Sdavidcs#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) 204250661Sdavidcs 205250661Sdavidcs#define WRITE_REG32(ha, reg, val) \ 206250661Sdavidcs {\ 207250661Sdavidcs bus_write_4((ha->pci_reg), reg, val);\ 208250661Sdavidcs bus_read_4((ha->pci_reg), reg);\ 209250661Sdavidcs } 210250661Sdavidcs 211250661Sdavidcs#define Q8_NUM_MBOX 512 212250661Sdavidcs 213250661Sdavidcs#define Q8_MAX_NUM_MULTICAST_ADDRS 1023 214250661Sdavidcs#define Q8_MAC_ADDR_LEN 6 215250661Sdavidcs 216250661Sdavidcs/* 217250661Sdavidcs * Firmware Interface 218250661Sdavidcs */ 219250661Sdavidcs 220250661Sdavidcs/* 221250661Sdavidcs * Command Response Interface - Commands 222250661Sdavidcs */ 223250661Sdavidcs 224250661Sdavidcs#define Q8_MBX_CONFIG_IP_ADDRESS 0x0001 225250661Sdavidcs#define Q8_MBX_CONFIG_INTR 0x0002 226250661Sdavidcs#define Q8_MBX_MAP_INTR_SRC 0x0003 227250661Sdavidcs#define Q8_MBX_MAP_SDS_TO_RDS 0x0006 228250661Sdavidcs#define Q8_MBX_CREATE_RX_CNTXT 0x0007 229250661Sdavidcs#define Q8_MBX_DESTROY_RX_CNTXT 0x0008 230250661Sdavidcs#define Q8_MBX_CREATE_TX_CNTXT 0x0009 231250661Sdavidcs#define Q8_MBX_DESTROY_TX_CNTXT 0x000A 232250661Sdavidcs#define Q8_MBX_ADD_RX_RINGS 0x000B 233250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW 0x000C 234250661Sdavidcs#define Q8_MBX_CONFIG_MAC_LEARNING 0x000D 235250661Sdavidcs#define Q8_MBX_GET_STATS 0x000F 236250661Sdavidcs#define Q8_MBX_GENERATE_INTR 0x0011 237250661Sdavidcs#define Q8_MBX_SET_MAX_MTU 0x0012 238250661Sdavidcs#define Q8_MBX_MAC_ADDR_CNTRL 0x001F 239250661Sdavidcs#define Q8_MBX_GET_PCI_CONFIG 0x0020 240250661Sdavidcs#define Q8_MBX_GET_NIC_PARTITION 0x0021 241250661Sdavidcs#define Q8_MBX_SET_NIC_PARTITION 0x0022 242250661Sdavidcs#define Q8_MBX_QUERY_WOL_CAP 0x002C 243250661Sdavidcs#define Q8_MBX_SET_WOL_CONFIG 0x002D 244250661Sdavidcs#define Q8_MBX_GET_MINIDUMP_TMPLT_SIZE 0x002F 245250661Sdavidcs#define Q8_MBX_GET_MINIDUMP_TMPLT 0x0030 246250661Sdavidcs#define Q8_MBX_GET_FW_DCBX_CAPS 0x0034 247250661Sdavidcs#define Q8_MBX_QUERY_DCBX_SETTINGS 0x0035 248250661Sdavidcs#define Q8_MBX_CONFIG_RSS 0x0041 249250661Sdavidcs#define Q8_MBX_CONFIG_RSS_TABLE 0x0042 250250661Sdavidcs#define Q8_MBX_CONFIG_INTR_COALESCE 0x0043 251250661Sdavidcs#define Q8_MBX_CONFIG_LED 0x0044 252250661Sdavidcs#define Q8_MBX_CONFIG_MAC_ADDR 0x0045 253250661Sdavidcs#define Q8_MBX_CONFIG_STATISTICS 0x0046 254250661Sdavidcs#define Q8_MBX_CONFIG_LOOPBACK 0x0047 255250661Sdavidcs#define Q8_MBX_LINK_EVENT_REQ 0x0048 256250661Sdavidcs#define Q8_MBX_CONFIG_MAC_RX_MODE 0x0049 257250661Sdavidcs#define Q8_MBX_CONFIG_FW_LRO 0x004A 258250661Sdavidcs#define Q8_MBX_INIT_NIC_FUNC 0x0060 259250661Sdavidcs#define Q8_MBX_STOP_NIC_FUNC 0x0061 260250661Sdavidcs#define Q8_MBX_SET_PORT_CONFIG 0x0066 261250661Sdavidcs#define Q8_MBX_GET_PORT_CONFIG 0x0067 262250661Sdavidcs#define Q8_MBX_GET_LINK_STATUS 0x0068 263250661Sdavidcs 264250661Sdavidcs 265250661Sdavidcs 266250661Sdavidcs/* 267250661Sdavidcs * Mailbox Command Response 268250661Sdavidcs */ 269250661Sdavidcs#define Q8_MBX_RSP_SUCCESS 0x0001 270250661Sdavidcs#define Q8_MBX_RSP_RESPONSE_FAILURE 0x0002 271250661Sdavidcs#define Q8_MBX_RSP_NO_CARD_CRB 0x0003 272250661Sdavidcs#define Q8_MBX_RSP_NO_CARD_MEM 0x0004 273250661Sdavidcs#define Q8_MBX_RSP_NO_CARD_RSRC 0x0005 274250661Sdavidcs#define Q8_MBX_RSP_INVALID_ARGS 0x0006 275250661Sdavidcs#define Q8_MBX_RSP_INVALID_ACTION 0x0007 276250661Sdavidcs#define Q8_MBX_RSP_INVALID_STATE 0x0008 277250661Sdavidcs#define Q8_MBX_RSP_NOT_SUPPORTED 0x0009 278250661Sdavidcs#define Q8_MBX_RSP_NOT_PERMITTED 0x000A 279250661Sdavidcs#define Q8_MBX_RSP_NOT_READY 0x000B 280250661Sdavidcs#define Q8_MBX_RSP_DOES_NOT_EXIST 0x000C 281250661Sdavidcs#define Q8_MBX_RSP_ALREADY_EXISTS 0x000D 282250661Sdavidcs#define Q8_MBX_RSP_BAD_SIGNATURE 0x000E 283250661Sdavidcs#define Q8_MBX_RSP_CMD_NOT_IMPLEMENTED 0x000F 284250661Sdavidcs#define Q8_MBX_RSP_CMD_INVALID 0x0010 285250661Sdavidcs#define Q8_MBX_RSP_TIMEOUT 0x0011 286250661Sdavidcs#define Q8_MBX_RSP_CMD_FAILED 0x0012 287250661Sdavidcs#define Q8_MBX_RSP_FATAL_TEMP 0x0013 288250661Sdavidcs#define Q8_MBX_RSP_MAX_EXCEEDED 0x0014 289250661Sdavidcs#define Q8_MBX_RSP_UNSPECIFIED 0x0015 290250661Sdavidcs#define Q8_MBX_RSP_INTR_CREATE_FAILED 0x0017 291250661Sdavidcs#define Q8_MBX_RSP_INTR_DELETE_FAILED 0x0018 292250661Sdavidcs#define Q8_MBX_RSP_INTR_INVALID_OP 0x0019 293250661Sdavidcs#define Q8_MBX_RSP_IDC_INTRMD_RSP 0x001A 294250661Sdavidcs 295250661Sdavidcs#define Q8_MBX_CMD_VERSION (0x2 << 13) 296250661Sdavidcs#define Q8_MBX_RSP_STATUS(x) (((!(x >> 9)) || ((x >> 9) == 1)) ? 0: (x >> 9)) 297250661Sdavidcs/* 298250661Sdavidcs * Configure IP Address 299250661Sdavidcs */ 300250661Sdavidcstypedef struct _q80_config_ip_addr { 301250661Sdavidcs uint16_t opcode; 302250661Sdavidcs uint16_t count_version; 303250661Sdavidcs 304250661Sdavidcs uint8_t cmd; 305250661Sdavidcs#define Q8_MBX_CONFIG_IP_ADD_IP 0x1 306250661Sdavidcs#define Q8_MBX_CONFIG_IP_DEL_IP 0x2 307250661Sdavidcs 308250661Sdavidcs uint8_t ip_type; 309250661Sdavidcs#define Q8_MBX_CONFIG_IP_V4 0x0 310250661Sdavidcs#define Q8_MBX_CONFIG_IP_V6 0x1 311250661Sdavidcs 312250661Sdavidcs uint16_t rsrvd; 313250661Sdavidcs union { 314250661Sdavidcs struct { 315250661Sdavidcs uint32_t addr; 316250661Sdavidcs uint32_t rsrvd[3]; 317250661Sdavidcs } ipv4; 318250661Sdavidcs uint8_t ipv6_addr[16]; 319250661Sdavidcs } u; 320250661Sdavidcs} __packed q80_config_ip_addr_t; 321250661Sdavidcs 322250661Sdavidcstypedef struct _q80_config_ip_addr_rsp { 323250661Sdavidcs uint16_t opcode; 324250661Sdavidcs uint16_t regcnt_status; 325250661Sdavidcs} __packed q80_config_ip_addr_rsp_t; 326250661Sdavidcs 327250661Sdavidcs/* 328250661Sdavidcs * Configure Interrupt Command 329250661Sdavidcs */ 330250661Sdavidcstypedef struct _q80_intr { 331250661Sdavidcs uint8_t cmd_type; 332250661Sdavidcs#define Q8_MBX_CONFIG_INTR_CREATE 0x1 333250661Sdavidcs#define Q8_MBX_CONFIG_INTR_DELETE 0x2 334250661Sdavidcs#define Q8_MBX_CONFIG_INTR_TYPE_LINE (0x1 << 4) 335250661Sdavidcs#define Q8_MBX_CONFIG_INTR_TYPE_MSI_X (0x3 << 4) 336250661Sdavidcs 337250661Sdavidcs uint8_t rsrvd; 338250661Sdavidcs uint16_t msix_index; 339250661Sdavidcs} __packed q80_intr_t; 340250661Sdavidcs 341250661Sdavidcs#define Q8_MAX_INTR_VECTORS 16 342250661Sdavidcstypedef struct _q80_config_intr { 343250661Sdavidcs uint16_t opcode; 344250661Sdavidcs uint16_t count_version; 345250661Sdavidcs uint8_t nentries; 346250661Sdavidcs uint8_t rsrvd[3]; 347250661Sdavidcs q80_intr_t intr[Q8_MAX_INTR_VECTORS]; 348250661Sdavidcs} __packed q80_config_intr_t; 349250661Sdavidcs 350250661Sdavidcstypedef struct _q80_intr_rsp { 351250661Sdavidcs uint8_t status; 352250661Sdavidcs uint8_t cmd; 353250661Sdavidcs uint16_t intr_id; 354250661Sdavidcs uint32_t intr_src; 355250661Sdavidcs} q80_intr_rsp_t; 356250661Sdavidcs 357250661Sdavidcstypedef struct _q80_config_intr_rsp { 358250661Sdavidcs uint16_t opcode; 359250661Sdavidcs uint16_t regcnt_status; 360250661Sdavidcs uint8_t nentries; 361250661Sdavidcs uint8_t rsrvd[3]; 362250661Sdavidcs q80_intr_rsp_t intr[Q8_MAX_INTR_VECTORS]; 363250661Sdavidcs} __packed q80_config_intr_rsp_t; 364250661Sdavidcs 365250661Sdavidcs/* 366250661Sdavidcs * Configure LRO Flow Command 367250661Sdavidcs */ 368250661Sdavidcstypedef struct _q80_config_lro_flow { 369250661Sdavidcs uint16_t opcode; 370250661Sdavidcs uint16_t count_version; 371250661Sdavidcs 372250661Sdavidcs uint8_t cmd; 373250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_ADD 0x01 374250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_DELETE 0x02 375250661Sdavidcs 376250661Sdavidcs uint8_t type_ts; 377250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_IPV4 0x00 378250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_IPV6 0x01 379250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_TS_ABSENT 0x00 380250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_TS_PRESENT 0x02 381250661Sdavidcs 382250661Sdavidcs uint16_t rsrvd; 383250661Sdavidcs union { 384250661Sdavidcs struct { 385250661Sdavidcs uint32_t addr; 386250661Sdavidcs uint32_t rsrvd[3]; 387250661Sdavidcs } ipv4; 388250661Sdavidcs uint8_t ipv6_addr[16]; 389250661Sdavidcs } dst; 390250661Sdavidcs union { 391250661Sdavidcs struct { 392250661Sdavidcs uint32_t addr; 393250661Sdavidcs uint32_t rsrvd[3]; 394250661Sdavidcs } ipv4; 395250661Sdavidcs uint8_t ipv6_addr[16]; 396250661Sdavidcs } src; 397250661Sdavidcs uint16_t dst_port; 398250661Sdavidcs uint16_t src_port; 399250661Sdavidcs} __packed q80_config_lro_flow_t; 400250661Sdavidcs 401250661Sdavidcstypedef struct _q80_config_lro_flow_rsp { 402250661Sdavidcs uint16_t opcode; 403250661Sdavidcs uint16_t regcnt_status; 404250661Sdavidcs} __packed q80_config_lro_flow_rsp_t; 405250661Sdavidcs 406250661Sdavidcstypedef struct _q80_set_max_mtu { 407250661Sdavidcs uint16_t opcode; 408250661Sdavidcs uint16_t count_version; 409250661Sdavidcs uint32_t cntxt_id; 410250661Sdavidcs uint32_t mtu; 411250661Sdavidcs} __packed q80_set_max_mtu_t; 412250661Sdavidcs 413250661Sdavidcstypedef struct _q80_set_max_mtu_rsp { 414250661Sdavidcs uint16_t opcode; 415250661Sdavidcs uint16_t regcnt_status; 416250661Sdavidcs} __packed q80_set_max_mtu_rsp_t; 417250661Sdavidcs 418250661Sdavidcs/* 419250661Sdavidcs * Configure RSS 420250661Sdavidcs */ 421250661Sdavidcstypedef struct _q80_config_rss { 422250661Sdavidcs uint16_t opcode; 423250661Sdavidcs uint16_t count_version; 424250661Sdavidcs 425250661Sdavidcs uint16_t cntxt_id; 426250661Sdavidcs uint16_t rsrvd; 427250661Sdavidcs 428250661Sdavidcs uint8_t hash_type; 429250661Sdavidcs#define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP (0x3 << 4) 430250661Sdavidcs#define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP (0x3 << 6) 431250661Sdavidcs 432250661Sdavidcs uint8_t flags; 433250661Sdavidcs#define Q8_MBX_RSS_FLAGS_ENABLE_RSS (0x1) 434250661Sdavidcs#define Q8_MBX_RSS_FLAGS_USE_IND_TABLE (0x2) 435250661Sdavidcs#define Q8_MBX_RSS_FLAGS_TYPE_CRSS (0x4) 436250661Sdavidcs 437250661Sdavidcs uint16_t indtbl_mask; 438250661Sdavidcs#define Q8_MBX_RSS_INDTBL_MASK 0x7F 439250661Sdavidcs#define Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID 0x8000 440250661Sdavidcs 441250661Sdavidcs uint32_t multi_rss; 442250661Sdavidcs#define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN BIT_30 443250661Sdavidcs#define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES BIT_31 444250661Sdavidcs 445250661Sdavidcs uint64_t rss_key[5]; 446250661Sdavidcs} __packed q80_config_rss_t; 447250661Sdavidcs 448250661Sdavidcstypedef struct _q80_config_rss_rsp { 449250661Sdavidcs uint16_t opcode; 450250661Sdavidcs uint16_t regcnt_status; 451250661Sdavidcs} __packed q80_config_rss_rsp_t; 452250661Sdavidcs 453250661Sdavidcs/* 454250661Sdavidcs * Configure RSS Indirection Table 455250661Sdavidcs */ 456250661Sdavidcs#define Q8_RSS_IND_TBL_SIZE 40 457250661Sdavidcs#define Q8_RSS_IND_TBL_MIN_IDX 0 458250661Sdavidcs#define Q8_RSS_IND_TBL_MAX_IDX 127 459250661Sdavidcs 460250661Sdavidcstypedef struct _q80_config_rss_ind_table { 461250661Sdavidcs uint16_t opcode; 462250661Sdavidcs uint16_t count_version; 463250661Sdavidcs uint8_t start_idx; 464250661Sdavidcs uint8_t end_idx; 465250661Sdavidcs uint16_t cntxt_id; 466250661Sdavidcs uint8_t ind_table[40]; 467250661Sdavidcs} __packed q80_config_rss_ind_table_t; 468250661Sdavidcs 469250661Sdavidcstypedef struct _q80_config_rss_ind_table_rsp { 470250661Sdavidcs uint16_t opcode; 471250661Sdavidcs uint16_t regcnt_status; 472250661Sdavidcs} __packed q80_config_rss_ind_table_rsp_t; 473250661Sdavidcs 474250661Sdavidcs/* 475250661Sdavidcs * Configure Interrupt Coalescing and Generation 476250661Sdavidcs */ 477250661Sdavidcstypedef struct _q80_config_intr_coalesc { 478250661Sdavidcs uint16_t opcode; 479250661Sdavidcs uint16_t count_version; 480250661Sdavidcs uint16_t flags; 481250661Sdavidcs#define Q8_MBX_INTRC_FLAGS_RCV 1 482250661Sdavidcs#define Q8_MBX_INTRC_FLAGS_XMT 2 483250661Sdavidcs#define Q8_MBX_INTRC_FLAGS_PERIODIC (1 << 3) 484250661Sdavidcs 485250661Sdavidcs uint16_t cntxt_id; 486250661Sdavidcs uint16_t max_pkts; 487250661Sdavidcs uint16_t max_mswait; 488250661Sdavidcs uint8_t timer_type; 489250661Sdavidcs#define Q8_MBX_INTRC_TIMER_NONE 0 490250661Sdavidcs#define Q8_MBX_INTRC_TIMER_SINGLE 1 491250661Sdavidcs#define Q8_MBX_INTRC_TIMER_PERIODIC 2 492250661Sdavidcs 493250661Sdavidcs uint16_t sds_ring_mask; 494250661Sdavidcs 495250661Sdavidcs uint8_t rsrvd; 496250661Sdavidcs uint32_t ms_timeout; 497250661Sdavidcs} __packed q80_config_intr_coalesc_t; 498250661Sdavidcs 499250661Sdavidcstypedef struct _q80_config_intr_coalesc_rsp { 500250661Sdavidcs uint16_t opcode; 501250661Sdavidcs uint16_t regcnt_status; 502250661Sdavidcs} __packed q80_config_intr_coalesc_rsp_t; 503250661Sdavidcs 504250661Sdavidcs/* 505250661Sdavidcs * Configure MAC Address 506250661Sdavidcs */ 507250661Sdavidcstypedef struct _q80_mac_addr { 508250661Sdavidcs uint8_t addr[6]; 509250661Sdavidcs uint16_t vlan_tci; 510250661Sdavidcs} __packed q80_mac_addr_t; 511250661Sdavidcs 512250661Sdavidcs#define Q8_MAX_MAC_ADDRS 64 513250661Sdavidcs 514250661Sdavidcstypedef struct _q80_config_mac_addr { 515250661Sdavidcs uint16_t opcode; 516250661Sdavidcs uint16_t count_version; 517250661Sdavidcs uint8_t cmd; 518250661Sdavidcs#define Q8_MBX_CMAC_CMD_ADD_MAC_ADDR 1 519250661Sdavidcs#define Q8_MBX_CMAC_CMD_DEL_MAC_ADDR 2 520250661Sdavidcs 521250661Sdavidcs#define Q8_MBX_CMAC_CMD_CAM_BOTH (0x0 << 6) 522250661Sdavidcs#define Q8_MBX_CMAC_CMD_CAM_INGRESS (0x1 << 6) 523250661Sdavidcs#define Q8_MBX_CMAC_CMD_CAM_EGRESS (0x2 << 6) 524250661Sdavidcs 525250661Sdavidcs uint8_t nmac_entries; 526250661Sdavidcs uint16_t cntxt_id; 527250661Sdavidcs q80_mac_addr_t mac_addr[Q8_MAX_MAC_ADDRS]; 528250661Sdavidcs} __packed q80_config_mac_addr_t; 529250661Sdavidcs 530250661Sdavidcstypedef struct _q80_config_mac_addr_rsp { 531250661Sdavidcs uint16_t opcode; 532250661Sdavidcs uint16_t regcnt_status; 533250661Sdavidcs uint8_t cmd; 534250661Sdavidcs uint8_t nmac_entries; 535250661Sdavidcs uint16_t cntxt_id; 536250661Sdavidcs uint32_t status[Q8_MAX_MAC_ADDRS]; 537250661Sdavidcs} __packed q80_config_mac_addr_rsp_t; 538250661Sdavidcs 539250661Sdavidcs/* 540250661Sdavidcs * Configure MAC Receive Mode 541250661Sdavidcs */ 542250661Sdavidcstypedef struct _q80_config_mac_rcv_mode { 543250661Sdavidcs uint16_t opcode; 544250661Sdavidcs uint16_t count_version; 545250661Sdavidcs 546250661Sdavidcs uint8_t mode; 547250661Sdavidcs#define Q8_MBX_MAC_RCV_PROMISC_ENABLE 0x1 548250661Sdavidcs#define Q8_MBX_MAC_ALL_MULTI_ENABLE 0x2 549250661Sdavidcs 550250661Sdavidcs uint8_t rsrvd; 551250661Sdavidcs uint16_t cntxt_id; 552250661Sdavidcs} __packed q80_config_mac_rcv_mode_t; 553250661Sdavidcs 554250661Sdavidcstypedef struct _q80_config_mac_rcv_mode_rsp { 555250661Sdavidcs uint16_t opcode; 556250661Sdavidcs uint16_t regcnt_status; 557250661Sdavidcs} __packed q80_config_mac_rcv_mode_rsp_t; 558250661Sdavidcs 559250661Sdavidcs/* 560250661Sdavidcs * Configure Firmware Controlled LRO 561250661Sdavidcs */ 562250661Sdavidcstypedef struct _q80_config_fw_lro { 563250661Sdavidcs uint16_t opcode; 564250661Sdavidcs uint16_t count_version; 565250661Sdavidcs 566250661Sdavidcs uint8_t flags; 567250661Sdavidcs#define Q8_MBX_FW_LRO_IPV4 0x1 568250661Sdavidcs#define Q8_MBX_FW_LRO_IPV6 0x2 569250661Sdavidcs#define Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK 0x4 570250661Sdavidcs#define Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK 0x8 571258898Sdavidcs#define Q8_MBX_FW_LRO_LOW_THRESHOLD 0x10 572250661Sdavidcs 573250661Sdavidcs uint8_t rsrvd; 574250661Sdavidcs uint16_t cntxt_id; 575258898Sdavidcs 576258898Sdavidcs uint16_t low_threshold; 577258898Sdavidcs uint16_t rsrvd0; 578250661Sdavidcs} __packed q80_config_fw_lro_t; 579250661Sdavidcs 580250661Sdavidcstypedef struct _q80_config_fw_lro_rsp { 581250661Sdavidcs uint16_t opcode; 582250661Sdavidcs uint16_t regcnt_status; 583250661Sdavidcs} __packed q80_config_fw_lro_rsp_t; 584250661Sdavidcs 585250661Sdavidcs/* 586250661Sdavidcs * Minidump mailbox commands 587250661Sdavidcs */ 588250661Sdavidcstypedef struct _q80_config_md_templ_size { 589250661Sdavidcs uint16_t opcode; 590250661Sdavidcs uint16_t count_version; 591250661Sdavidcs} __packed q80_config_md_templ_size_t; 592250661Sdavidcs 593250661Sdavidcstypedef struct _q80_config_md_templ_size_rsp { 594250661Sdavidcs uint16_t opcode; 595250661Sdavidcs uint16_t regcnt_status; 596250661Sdavidcs uint32_t rsrvd; 597250661Sdavidcs uint32_t templ_size; 598250661Sdavidcs uint32_t templ_version; 599250661Sdavidcs} __packed q80_config_md_templ_size_rsp_t; 600250661Sdavidcs 601250661Sdavidcstypedef struct _q80_config_md_templ_cmd { 602250661Sdavidcs uint16_t opcode; 603250661Sdavidcs uint16_t count_version; 604250661Sdavidcs uint64_t buf_addr; /* physical address of buffer */ 605250661Sdavidcs uint32_t buff_size; 606250661Sdavidcs uint32_t offset; 607250661Sdavidcs} __packed q80_config_md_templ_cmd_t; 608250661Sdavidcs 609250661Sdavidcstypedef struct _q80_config_md_templ_cmd_rsp { 610250661Sdavidcs uint16_t opcode; 611250661Sdavidcs uint16_t regcnt_status; 612250661Sdavidcs uint32_t rsrvd; 613250661Sdavidcs uint32_t templ_size; 614250661Sdavidcs uint32_t buff_size; 615250661Sdavidcs uint32_t offset; 616250661Sdavidcs} __packed q80_config_md_templ_cmd_rsp_t; 617250661Sdavidcs 618250661Sdavidcs/* 619250661Sdavidcs * Link Event Request Command 620250661Sdavidcs */ 621250661Sdavidcstypedef struct _q80_link_event { 622250661Sdavidcs uint16_t opcode; 623250661Sdavidcs uint16_t count_version; 624250661Sdavidcs uint8_t cmd; 625250661Sdavidcs#define Q8_LINK_EVENT_CMD_STOP_PERIODIC 0 626250661Sdavidcs#define Q8_LINK_EVENT_CMD_ENABLE_ASYNC 1 627250661Sdavidcs 628250661Sdavidcs uint8_t flags; 629250661Sdavidcs#define Q8_LINK_EVENT_FLAGS_SEND_RSP 1 630250661Sdavidcs 631250661Sdavidcs uint16_t cntxt_id; 632250661Sdavidcs} __packed q80_link_event_t; 633250661Sdavidcs 634250661Sdavidcstypedef struct _q80_link_event_rsp { 635250661Sdavidcs uint16_t opcode; 636250661Sdavidcs uint16_t regcnt_status; 637250661Sdavidcs} __packed q80_link_event_rsp_t; 638250661Sdavidcs 639250661Sdavidcs/* 640250661Sdavidcs * Get Statistics Command 641250661Sdavidcs */ 642250661Sdavidcstypedef struct _q80_rcv_stats { 643250661Sdavidcs uint64_t total_bytes; 644250661Sdavidcs uint64_t total_pkts; 645250661Sdavidcs uint64_t lro_pkt_count; 646250661Sdavidcs uint64_t sw_pkt_count; 647250661Sdavidcs uint64_t ip_chksum_err; 648250661Sdavidcs uint64_t pkts_wo_acntxts; 649250661Sdavidcs uint64_t pkts_dropped_no_sds_card; 650250661Sdavidcs uint64_t pkts_dropped_no_sds_host; 651250661Sdavidcs uint64_t oversized_pkts; 652250661Sdavidcs uint64_t pkts_dropped_no_rds; 653250661Sdavidcs uint64_t unxpctd_mcast_pkts; 654250661Sdavidcs uint64_t re1_fbq_error; 655250661Sdavidcs uint64_t invalid_mac_addr; 656250661Sdavidcs uint64_t rds_prime_trys; 657250661Sdavidcs uint64_t rds_prime_success; 658250661Sdavidcs uint64_t lro_flows_added; 659250661Sdavidcs uint64_t lro_flows_deleted; 660250661Sdavidcs uint64_t lro_flows_active; 661250661Sdavidcs uint64_t pkts_droped_unknown; 662250661Sdavidcs} __packed q80_rcv_stats_t; 663250661Sdavidcs 664250661Sdavidcstypedef struct _q80_xmt_stats { 665250661Sdavidcs uint64_t total_bytes; 666250661Sdavidcs uint64_t total_pkts; 667250661Sdavidcs uint64_t errors; 668250661Sdavidcs uint64_t pkts_dropped; 669250661Sdavidcs uint64_t switch_pkts; 670250661Sdavidcs uint64_t num_buffers; 671250661Sdavidcs} __packed q80_xmt_stats_t; 672250661Sdavidcs 673250661Sdavidcstypedef struct _q80_mac_stats { 674250661Sdavidcs uint64_t xmt_frames; 675250661Sdavidcs uint64_t xmt_bytes; 676250661Sdavidcs uint64_t xmt_mcast_pkts; 677250661Sdavidcs uint64_t xmt_bcast_pkts; 678250661Sdavidcs uint64_t xmt_pause_frames; 679250661Sdavidcs uint64_t xmt_cntrl_pkts; 680250661Sdavidcs uint64_t xmt_pkt_lt_64bytes; 681250661Sdavidcs uint64_t xmt_pkt_lt_127bytes; 682250661Sdavidcs uint64_t xmt_pkt_lt_255bytes; 683250661Sdavidcs uint64_t xmt_pkt_lt_511bytes; 684250661Sdavidcs uint64_t xmt_pkt_lt_1023bytes; 685250661Sdavidcs uint64_t xmt_pkt_lt_1518bytes; 686250661Sdavidcs uint64_t xmt_pkt_gt_1518bytes; 687250661Sdavidcs uint64_t rsrvd0[3]; 688250661Sdavidcs uint64_t rcv_frames; 689250661Sdavidcs uint64_t rcv_bytes; 690250661Sdavidcs uint64_t rcv_mcast_pkts; 691250661Sdavidcs uint64_t rcv_bcast_pkts; 692250661Sdavidcs uint64_t rcv_pause_frames; 693250661Sdavidcs uint64_t rcv_cntrl_pkts; 694250661Sdavidcs uint64_t rcv_pkt_lt_64bytes; 695250661Sdavidcs uint64_t rcv_pkt_lt_127bytes; 696250661Sdavidcs uint64_t rcv_pkt_lt_255bytes; 697250661Sdavidcs uint64_t rcv_pkt_lt_511bytes; 698250661Sdavidcs uint64_t rcv_pkt_lt_1023bytes; 699250661Sdavidcs uint64_t rcv_pkt_lt_1518bytes; 700250661Sdavidcs uint64_t rcv_pkt_gt_1518bytes; 701250661Sdavidcs uint64_t rsrvd1[3]; 702250661Sdavidcs uint64_t rcv_len_error; 703250661Sdavidcs uint64_t rcv_len_small; 704250661Sdavidcs uint64_t rcv_len_large; 705250661Sdavidcs uint64_t rcv_jabber; 706250661Sdavidcs uint64_t rcv_dropped; 707250661Sdavidcs uint64_t fcs_error; 708250661Sdavidcs uint64_t align_error; 709250661Sdavidcs} __packed q80_mac_stats_t; 710250661Sdavidcs 711250661Sdavidcstypedef struct _q80_get_stats { 712250661Sdavidcs uint16_t opcode; 713250661Sdavidcs uint16_t count_version; 714250661Sdavidcs 715250661Sdavidcs uint32_t cmd; 716250661Sdavidcs#define Q8_GET_STATS_CMD_CLEAR 0x01 717250661Sdavidcs#define Q8_GET_STATS_CMD_RCV 0x00 718250661Sdavidcs#define Q8_GET_STATS_CMD_XMT 0x02 719250661Sdavidcs#define Q8_GET_STATS_CMD_TYPE_CNTXT 0x00 720250661Sdavidcs#define Q8_GET_STATS_CMD_TYPE_MAC 0x04 721250661Sdavidcs#define Q8_GET_STATS_CMD_TYPE_FUNC 0x08 722250661Sdavidcs#define Q8_GET_STATS_CMD_TYPE_VPORT 0x0C 723250661Sdavidcs 724250661Sdavidcs} __packed q80_get_stats_t; 725250661Sdavidcs 726250661Sdavidcstypedef struct _q80_get_stats_rsp { 727250661Sdavidcs uint16_t opcode; 728250661Sdavidcs uint16_t regcnt_status; 729250661Sdavidcs uint32_t cmd; 730250661Sdavidcs union { 731250661Sdavidcs q80_rcv_stats_t rcv; 732250661Sdavidcs q80_xmt_stats_t xmt; 733250661Sdavidcs q80_mac_stats_t mac; 734250661Sdavidcs } u; 735250661Sdavidcs} __packed q80_get_stats_rsp_t; 736250661Sdavidcs 737250661Sdavidcs/* 738250661Sdavidcs * Init NIC Function 739250661Sdavidcs * Used to Register DCBX Configuration Change AEN 740250661Sdavidcs */ 741250661Sdavidcstypedef struct _q80_init_nic_func { 742250661Sdavidcs uint16_t opcode; 743250661Sdavidcs uint16_t count_version; 744250661Sdavidcs 745250661Sdavidcs uint32_t options; 746250661Sdavidcs#define Q8_INIT_NIC_REG_DCBX_CHNG_AEN 0x02 747250661Sdavidcs#define Q8_INIT_NIC_REG_SFP_CHNG_AEN 0x04 748250661Sdavidcs 749250661Sdavidcs} __packed q80_init_nic_func_t; 750250661Sdavidcs 751250661Sdavidcstypedef struct _q80_init_nic_func_rsp { 752250661Sdavidcs uint16_t opcode; 753250661Sdavidcs uint16_t regcnt_status; 754250661Sdavidcs} __packed q80_init_nic_func_rsp_t; 755250661Sdavidcs 756250661Sdavidcs/* 757250661Sdavidcs * Stop NIC Function 758250661Sdavidcs * Used to DeRegister DCBX Configuration Change AEN 759250661Sdavidcs */ 760250661Sdavidcstypedef struct _q80_stop_nic_func { 761250661Sdavidcs uint16_t opcode; 762250661Sdavidcs uint16_t count_version; 763250661Sdavidcs 764250661Sdavidcs uint32_t options; 765250661Sdavidcs#define Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN 0x02 766250661Sdavidcs#define Q8_STOP_NIC_DEREG_SFP_CHNG_AEN 0x04 767250661Sdavidcs 768250661Sdavidcs} __packed q80_stop_nic_func_t; 769250661Sdavidcs 770250661Sdavidcstypedef struct _q80_stop_nic_func_rsp { 771250661Sdavidcs uint16_t opcode; 772250661Sdavidcs uint16_t regcnt_status; 773250661Sdavidcs} __packed q80_stop_nic_func_rsp_t; 774250661Sdavidcs 775250661Sdavidcs/* 776250661Sdavidcs * Query Firmware DCBX Capabilities 777250661Sdavidcs */ 778250661Sdavidcstypedef struct _q80_query_fw_dcbx_caps { 779250661Sdavidcs uint16_t opcode; 780250661Sdavidcs uint16_t count_version; 781250661Sdavidcs} __packed q80_query_fw_dcbx_caps_t; 782250661Sdavidcs 783250661Sdavidcstypedef struct _q80_query_fw_dcbx_caps_rsp { 784250661Sdavidcs uint16_t opcode; 785250661Sdavidcs uint16_t regcnt_status; 786250661Sdavidcs 787250661Sdavidcs uint32_t dcbx_caps; 788250661Sdavidcs#define Q8_QUERY_FW_DCBX_CAPS_TSA 0x00000001 789250661Sdavidcs#define Q8_QUERY_FW_DCBX_CAPS_ETS 0x00000002 790250661Sdavidcs#define Q8_QUERY_FW_DCBX_CAPS_DCBX_CEE_1_01 0x00000004 791250661Sdavidcs#define Q8_QUERY_FW_DCBX_CAPS_DCBX_IEEE_1_0 0x00000008 792250661Sdavidcs#define Q8_QUERY_FW_DCBX_MAX_TC_MASK 0x00F00000 793250661Sdavidcs#define Q8_QUERY_FW_DCBX_MAX_ETS_TC_MASK 0x0F000000 794250661Sdavidcs#define Q8_QUERY_FW_DCBX_MAX_PFC_TC_MASK 0xF0000000 795250661Sdavidcs 796250661Sdavidcs} __packed q80_query_fw_dcbx_caps_rsp_t; 797250661Sdavidcs 798250661Sdavidcs/* 799250661Sdavidcs * Set Port Configuration command 800250661Sdavidcs * Used to set Ethernet Standard Pause values 801250661Sdavidcs */ 802250661Sdavidcs 803250661Sdavidcstypedef struct _q80_set_port_cfg { 804250661Sdavidcs uint16_t opcode; 805250661Sdavidcs uint16_t count_version; 806250661Sdavidcs 807250661Sdavidcs uint32_t cfg_bits; 808250661Sdavidcs 809250661Sdavidcs#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_MASK (0x7 << 1) 810250661Sdavidcs#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE (0x0 << 1) 811250661Sdavidcs#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS (0x2 << 1) 812250661Sdavidcs#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_PHY (0x3 << 1) 813250661Sdavidcs#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT (0x4 << 1) 814250661Sdavidcs 815250661Sdavidcs#define Q8_VALID_LOOPBACK_MODE(mode) \ 816250661Sdavidcs (((mode) == Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE) || \ 817250661Sdavidcs (((mode) >= Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS) && \ 818250661Sdavidcs ((mode) <= Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT))) 819250661Sdavidcs 820250661Sdavidcs#define Q8_PORT_CFG_BITS_DCBX_ENABLE BIT_4 821250661Sdavidcs 822250661Sdavidcs#define Q8_PORT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 5) 823250661Sdavidcs#define Q8_PORT_CFG_BITS_PAUSE_DISABLED (0x0 << 5) 824250661Sdavidcs#define Q8_PORT_CFG_BITS_PAUSE_STD (0x1 << 5) 825250661Sdavidcs#define Q8_PORT_CFG_BITS_PAUSE_PPM (0x2 << 5) 826250661Sdavidcs 827250661Sdavidcs#define Q8_PORT_CFG_BITS_LNKCAP_10MB BIT_8 828250661Sdavidcs#define Q8_PORT_CFG_BITS_LNKCAP_100MB BIT_9 829250661Sdavidcs#define Q8_PORT_CFG_BITS_LNKCAP_1GB BIT_10 830250661Sdavidcs#define Q8_PORT_CFG_BITS_LNKCAP_10GB BIT_11 831250661Sdavidcs 832250661Sdavidcs#define Q8_PORT_CFG_BITS_AUTONEG BIT_15 833250661Sdavidcs#define Q8_PORT_CFG_BITS_XMT_DISABLE BIT_17 834250661Sdavidcs#define Q8_PORT_CFG_BITS_FEC_RQSTD BIT_18 835250661Sdavidcs#define Q8_PORT_CFG_BITS_EEE_RQSTD BIT_19 836250661Sdavidcs 837250661Sdavidcs#define Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20) 838250661Sdavidcs#define Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV (0x0 << 20) 839250661Sdavidcs#define Q8_PORT_CFG_BITS_STDPAUSE_XMT (0x1 << 20) 840250661Sdavidcs#define Q8_PORT_CFG_BITS_STDPAUSE_RCV (0x2 << 20) 841250661Sdavidcs 842250661Sdavidcs} __packed q80_set_port_cfg_t; 843250661Sdavidcs 844250661Sdavidcstypedef struct _q80_set_port_cfg_rsp { 845250661Sdavidcs uint16_t opcode; 846250661Sdavidcs uint16_t regcnt_status; 847250661Sdavidcs} __packed q80_set_port_cfg_rsp_t; 848250661Sdavidcs 849250661Sdavidcs/* 850250661Sdavidcs * Get Port Configuration Command 851250661Sdavidcs */ 852250661Sdavidcs 853250661Sdavidcstypedef struct _q80_get_port_cfg { 854250661Sdavidcs uint16_t opcode; 855250661Sdavidcs uint16_t count_version; 856250661Sdavidcs} __packed q80_get_port_cfg_t; 857250661Sdavidcs 858250661Sdavidcstypedef struct _q80_get_port_cfg_rsp { 859250661Sdavidcs uint16_t opcode; 860250661Sdavidcs uint16_t regcnt_status; 861250661Sdavidcs 862250661Sdavidcs uint32_t cfg_bits; /* same as in q80_set_port_cfg_t */ 863250661Sdavidcs 864250661Sdavidcs uint8_t phys_port_type; 865250661Sdavidcs uint8_t rsvd[3]; 866250661Sdavidcs} __packed q80_get_port_cfg_rsp_t; 867250661Sdavidcs 868250661Sdavidcs/* 869250661Sdavidcs * Get Link Status Command 870250661Sdavidcs * Used to get current PAUSE values for the port 871250661Sdavidcs */ 872250661Sdavidcs 873250661Sdavidcstypedef struct _q80_get_link_status { 874250661Sdavidcs uint16_t opcode; 875250661Sdavidcs uint16_t count_version; 876250661Sdavidcs} __packed q80_get_link_status_t; 877250661Sdavidcs 878250661Sdavidcstypedef struct _q80_get_link_status_rsp { 879250661Sdavidcs uint16_t opcode; 880250661Sdavidcs uint16_t regcnt_status; 881250661Sdavidcs 882250661Sdavidcs uint32_t cfg_bits; 883250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_UP BIT_0 884250661Sdavidcs 885250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_MASK (0x7 << 3) 886250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_UNKNOWN (0x0 << 3) 887250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10MB (0x1 << 3) 888250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_100MB (0x2 << 3) 889250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_1GB (0x3 << 3) 890250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10GB (0x4 << 3) 891250661Sdavidcs 892250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 6) 893250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_DISABLE (0x0 << 6) 894250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_STD (0x1 << 6) 895250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_PPM (0x2 << 6) 896250661Sdavidcs 897250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_MASK (0x7 << 8) 898250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_NONE (0x0 << 6) 899250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_HSS (0x2 << 6) 900250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_PHY (0x3 << 6) 901250661Sdavidcs 902250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED BIT_12 903250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED BIT_13 904250661Sdavidcs 905250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20) 906250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_NONE (0x0 << 20) 907250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT (0x1 << 20) 908250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_RCV (0x2 << 20) 909250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT_RCV (0x3 << 20) 910250661Sdavidcs 911250661Sdavidcs uint32_t link_state; 912250661Sdavidcs#define Q8_GET_LINK_STAT_LOSS_OF_SIGNAL BIT_0 913250661Sdavidcs#define Q8_GET_LINK_STAT_PORT_RST_DONE BIT_3 914250661Sdavidcs#define Q8_GET_LINK_STAT_PHY_LINK_DOWN BIT_4 915250661Sdavidcs#define Q8_GET_LINK_STAT_PCS_LINK_DOWN BIT_5 916250661Sdavidcs#define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT BIT_6 917250661Sdavidcs#define Q8_GET_LINK_STAT_MAC_REMOTE_FAULT BIT_7 918250661Sdavidcs#define Q8_GET_LINK_STAT_XMT_DISABLED BIT_9 919250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10 920250661Sdavidcs 921250661Sdavidcs uint32_t sfp_info; 922250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_TRNCVR_MASK 0x3 923250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_TRNCVR_NOT_EXPECTED 0x0 924250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_TRNCVR_NONE 0x1 925250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_TRNCVR_INVALID 0x2 926250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_TRNCVR_VALID 0x3 927250661Sdavidcs 928250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_MASK (0x3 << 2) 929250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_UNREC_TRSVR (0x0 << 2) 930250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_NOT_QLOGIC (0x1 << 2) 931250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_SPEED_FAILED (0x2 << 2) 932250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_ACCESS_ERROR (0x3 << 2) 933250661Sdavidcs 934250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_TYPE_MASK (0x1F << 4) 935250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_NONE (0x00 << 4) 936250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBLRM (0x01 << 4) 937250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBLR (0x02 << 4) 938250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBSR (0x03 << 4) 939250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBC_P (0x04 << 4) 940250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBC_AL (0x05 << 4) 941250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBC_PL (0x06 << 4) 942250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_1GBSX (0x07 << 4) 943250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_1GBLX (0x08 << 4) 944250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_1GBCX (0x09 << 4) 945250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_1GBT (0x0A << 4) 946250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_1GBC_PL (0x0B << 4) 947250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_UNKNOWN (0x0F << 4) 948250661Sdavidcs 949250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD BIT_9 950250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10 951250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_COPPER_CBL_LENGTH_MASK (0xFF << 16) 952250661Sdavidcs 953250661Sdavidcs} __packed q80_get_link_status_rsp_t; 954250661Sdavidcs 955250661Sdavidcs 956250661Sdavidcs/* 957250661Sdavidcs * Transmit Related Definitions 958250661Sdavidcs */ 959250661Sdavidcs/* Max# of TX Rings per Tx Create Cntxt Mbx Cmd*/ 960250661Sdavidcs#define MAX_TCNTXT_RINGS 8 961250661Sdavidcs 962250661Sdavidcs/* 963250661Sdavidcs * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data 964250661Sdavidcs */ 965250661Sdavidcs 966250661Sdavidcstypedef struct _q80_rq_tx_ring { 967250661Sdavidcs uint64_t paddr; 968250661Sdavidcs uint64_t tx_consumer; 969250661Sdavidcs uint16_t nentries; 970250661Sdavidcs uint16_t intr_id; 971250661Sdavidcs uint8_t intr_src_bit; 972250661Sdavidcs uint8_t rsrvd[3]; 973250661Sdavidcs} __packed q80_rq_tx_ring_t; 974250661Sdavidcs 975250661Sdavidcstypedef struct _q80_rq_tx_cntxt { 976250661Sdavidcs uint16_t opcode; 977250661Sdavidcs uint16_t count_version; 978250661Sdavidcs 979250661Sdavidcs uint32_t cap0; 980250661Sdavidcs#define Q8_TX_CNTXT_CAP0_BASEFW (1 << 0) 981250661Sdavidcs#define Q8_TX_CNTXT_CAP0_LSO (1 << 6) 982250661Sdavidcs#define Q8_TX_CNTXT_CAP0_TC (1 << 25) 983250661Sdavidcs 984250661Sdavidcs uint32_t cap1; 985250661Sdavidcs uint32_t cap2; 986250661Sdavidcs uint32_t cap3; 987250661Sdavidcs uint8_t ntx_rings; 988250661Sdavidcs uint8_t traffic_class; /* bits 8-10; others reserved */ 989250661Sdavidcs uint16_t tx_vpid; 990250661Sdavidcs q80_rq_tx_ring_t tx_ring[MAX_TCNTXT_RINGS]; 991250661Sdavidcs} __packed q80_rq_tx_cntxt_t; 992250661Sdavidcs 993250661Sdavidcstypedef struct _q80_rsp_tx_ring { 994250661Sdavidcs uint32_t prod_index; 995250661Sdavidcs uint16_t cntxt_id; 996250661Sdavidcs uint8_t state; 997250661Sdavidcs uint8_t rsrvd; 998250661Sdavidcs} q80_rsp_tx_ring_t; 999250661Sdavidcs 1000250661Sdavidcstypedef struct _q80_rsp_tx_cntxt { 1001250661Sdavidcs uint16_t opcode; 1002250661Sdavidcs uint16_t regcnt_status; 1003250661Sdavidcs uint8_t ntx_rings; 1004250661Sdavidcs uint8_t phy_port; 1005250661Sdavidcs uint8_t virt_port; 1006250661Sdavidcs uint8_t rsrvd; 1007250661Sdavidcs q80_rsp_tx_ring_t tx_ring[MAX_TCNTXT_RINGS]; 1008250661Sdavidcs} __packed q80_rsp_tx_cntxt_t; 1009250661Sdavidcs 1010250661Sdavidcstypedef struct _q80_tx_cntxt_destroy { 1011250661Sdavidcs uint16_t opcode; 1012250661Sdavidcs uint16_t count_version; 1013250661Sdavidcs uint32_t cntxt_id; 1014250661Sdavidcs} __packed q80_tx_cntxt_destroy_t; 1015250661Sdavidcs 1016250661Sdavidcstypedef struct _q80_tx_cntxt_destroy_rsp { 1017250661Sdavidcs uint16_t opcode; 1018250661Sdavidcs uint16_t regcnt_status; 1019250661Sdavidcs} __packed q80_tx_cntxt_destroy_rsp_t; 1020250661Sdavidcs 1021250661Sdavidcs/* 1022250661Sdavidcs * Transmit Command Descriptor 1023250661Sdavidcs * These commands are issued on the Transmit Ring associated with a Transmit 1024250661Sdavidcs * context 1025250661Sdavidcs */ 1026250661Sdavidcstypedef struct _q80_tx_cmd { 1027250661Sdavidcs uint8_t tcp_hdr_off; /* TCP Header Offset */ 1028250661Sdavidcs uint8_t ip_hdr_off; /* IP Header Offset */ 1029250661Sdavidcs uint16_t flags_opcode; /* Bits 0-6: flags; 7-12: opcode */ 1030250661Sdavidcs 1031250661Sdavidcs /* flags field */ 1032250661Sdavidcs#define Q8_TX_CMD_FLAGS_MULTICAST 0x01 1033250661Sdavidcs#define Q8_TX_CMD_FLAGS_LSO_TSO 0x02 1034250661Sdavidcs#define Q8_TX_CMD_FLAGS_VLAN_TAGGED 0x10 1035250661Sdavidcs#define Q8_TX_CMD_FLAGS_HW_VLAN_ID 0x40 1036250661Sdavidcs 1037250661Sdavidcs /* opcode field */ 1038250661Sdavidcs#define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6 (0xC << 7) 1039250661Sdavidcs#define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6 (0xB << 7) 1040250661Sdavidcs#define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6 (0x6 << 7) 1041250661Sdavidcs#define Q8_TX_CMD_OP_XMT_TCP_LSO (0x5 << 7) 1042250661Sdavidcs#define Q8_TX_CMD_OP_XMT_UDP_CHKSUM (0x3 << 7) 1043250661Sdavidcs#define Q8_TX_CMD_OP_XMT_TCP_CHKSUM (0x2 << 7) 1044250661Sdavidcs#define Q8_TX_CMD_OP_XMT_ETHER (0x1 << 7) 1045250661Sdavidcs 1046250661Sdavidcs uint8_t n_bufs; /* # of data segs in data buffer */ 1047250661Sdavidcs uint8_t data_len_lo; /* data length lower 8 bits */ 1048250661Sdavidcs uint16_t data_len_hi; /* data length upper 16 bits */ 1049250661Sdavidcs 1050250661Sdavidcs uint64_t buf2_addr; /* buffer 2 address */ 1051250661Sdavidcs 1052250661Sdavidcs uint16_t rsrvd0; 1053250661Sdavidcs uint16_t mss; /* MSS for this packet */ 1054250661Sdavidcs uint8_t cntxtid; /* Bits 7-4: ContextId; 3-0: reserved */ 1055250661Sdavidcs 1056250661Sdavidcs#define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4) 1057250661Sdavidcs 1058250661Sdavidcs uint8_t total_hdr_len; /* MAC+IP+TCP Header Length for LSO */ 1059250661Sdavidcs uint16_t rsrvd1; 1060250661Sdavidcs 1061250661Sdavidcs uint64_t buf3_addr; /* buffer 3 address */ 1062250661Sdavidcs uint64_t buf1_addr; /* buffer 1 address */ 1063250661Sdavidcs 1064250661Sdavidcs uint16_t buf1_len; /* length of buffer 1 */ 1065250661Sdavidcs uint16_t buf2_len; /* length of buffer 2 */ 1066250661Sdavidcs uint16_t buf3_len; /* length of buffer 3 */ 1067250661Sdavidcs uint16_t buf4_len; /* length of buffer 4 */ 1068250661Sdavidcs 1069250661Sdavidcs uint64_t buf4_addr; /* buffer 4 address */ 1070250661Sdavidcs 1071250661Sdavidcs uint32_t rsrvd2; 1072250661Sdavidcs uint16_t rsrvd3; 1073250661Sdavidcs uint16_t vlan_tci; /* VLAN TCI when hw tagging is enabled*/ 1074250661Sdavidcs 1075250661Sdavidcs} __packed q80_tx_cmd_t; /* 64 bytes */ 1076250661Sdavidcs 1077250661Sdavidcs#define Q8_TX_CMD_MAX_SEGMENTS 4 1078250661Sdavidcs#define Q8_TX_CMD_TSO_ALIGN 2 1079250661Sdavidcs#define Q8_TX_MAX_NON_TSO_SEGS 62 1080250661Sdavidcs 1081250661Sdavidcs 1082250661Sdavidcs/* 1083250661Sdavidcs * Receive Related Definitions 1084250661Sdavidcs */ 1085250661Sdavidcs#define MAX_RDS_RING_SETS 8 /* Max# of Receive Descriptor Rings */ 1086250661Sdavidcs#define MAX_SDS_RINGS 4 /* Max# of Status Descriptor Rings */ 1087250661Sdavidcs 1088250661Sdavidcstypedef struct _q80_rq_sds_ring { 1089250661Sdavidcs uint64_t paddr; /* physical addr of status ring in system memory */ 1090250661Sdavidcs uint64_t hdr_split1; 1091250661Sdavidcs uint64_t hdr_split2; 1092250661Sdavidcs uint16_t size; /* number of entries in status ring */ 1093250661Sdavidcs uint16_t hdr_split1_size; 1094250661Sdavidcs uint16_t hdr_split2_size; 1095250661Sdavidcs uint16_t hdr_split_count; 1096250661Sdavidcs uint16_t intr_id; 1097250661Sdavidcs uint8_t intr_src_bit; 1098250661Sdavidcs uint8_t rsrvd[5]; 1099250661Sdavidcs} __packed q80_rq_sds_ring_t; /* 10 32bit words */ 1100250661Sdavidcs 1101250661Sdavidcstypedef struct _q80_rq_rds_ring { 1102250661Sdavidcs uint64_t paddr_std; /* physical addr of rcv ring in system memory */ 1103250661Sdavidcs uint64_t paddr_jumbo; /* physical addr of rcv ring in system memory */ 1104250661Sdavidcs uint16_t std_bsize; 1105250661Sdavidcs uint16_t std_nentries; 1106250661Sdavidcs uint16_t jumbo_bsize; 1107250661Sdavidcs uint16_t jumbo_nentries; 1108250661Sdavidcs} __packed q80_rq_rds_ring_t; /* 6 32bit words */ 1109250661Sdavidcs 1110250661Sdavidcs#define MAX_RCNTXT_SDS_RINGS 8 1111250661Sdavidcs 1112250661Sdavidcstypedef struct _q80_rq_rcv_cntxt { 1113250661Sdavidcs uint16_t opcode; 1114250661Sdavidcs uint16_t count_version; 1115250661Sdavidcs uint32_t cap0; 1116250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_BASEFW (1 << 0) 1117250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_MULTI_RDS (1 << 1) 1118250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_LRO (1 << 5) 1119250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_HW_LRO (1 << 10) 1120250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_VLAN_ALIGN (1 << 14) 1121250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_RSS (1 << 15) 1122250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_MSFT_RSS (1 << 16) 1123250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_SGL_JUMBO (1 << 18) 1124250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_SGL_LRO (1 << 19) 1125250661Sdavidcs 1126250661Sdavidcs uint32_t cap1; 1127250661Sdavidcs uint32_t cap2; 1128250661Sdavidcs uint32_t cap3; 1129250661Sdavidcs uint8_t nrds_sets_rings; 1130250661Sdavidcs uint8_t nsds_rings; 1131250661Sdavidcs uint16_t rds_producer_mode; 1132250661Sdavidcs#define Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE 0 1133250661Sdavidcs#define Q8_RCV_CNTXT_RDS_PROD_MODE_SHARED 1 1134250661Sdavidcs 1135250661Sdavidcs uint16_t rcv_vpid; 1136250661Sdavidcs uint16_t rsrvd0; 1137250661Sdavidcs uint32_t rsrvd1; 1138250661Sdavidcs q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS]; 1139250661Sdavidcs q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS]; 1140250661Sdavidcs} __packed q80_rq_rcv_cntxt_t; 1141250661Sdavidcs 1142250661Sdavidcstypedef struct _q80_rsp_rds_ring { 1143250661Sdavidcs uint32_t prod_std; 1144250661Sdavidcs uint32_t prod_jumbo; 1145250661Sdavidcs} __packed q80_rsp_rds_ring_t; /* 8 bytes */ 1146250661Sdavidcs 1147250661Sdavidcstypedef struct _q80_rsp_rcv_cntxt { 1148250661Sdavidcs uint16_t opcode; 1149250661Sdavidcs uint16_t regcnt_status; 1150250661Sdavidcs uint8_t nrds_sets_rings; 1151250661Sdavidcs uint8_t nsds_rings; 1152250661Sdavidcs uint16_t cntxt_id; 1153250661Sdavidcs uint8_t state; 1154250661Sdavidcs uint8_t num_funcs; 1155250661Sdavidcs uint8_t phy_port; 1156250661Sdavidcs uint8_t virt_port; 1157250661Sdavidcs uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS]; 1158250661Sdavidcs q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS]; 1159250661Sdavidcs} __packed q80_rsp_rcv_cntxt_t; 1160250661Sdavidcs 1161250661Sdavidcstypedef struct _q80_rcv_cntxt_destroy { 1162250661Sdavidcs uint16_t opcode; 1163250661Sdavidcs uint16_t count_version; 1164250661Sdavidcs uint32_t cntxt_id; 1165250661Sdavidcs} __packed q80_rcv_cntxt_destroy_t; 1166250661Sdavidcs 1167250661Sdavidcstypedef struct _q80_rcv_cntxt_destroy_rsp { 1168250661Sdavidcs uint16_t opcode; 1169250661Sdavidcs uint16_t regcnt_status; 1170250661Sdavidcs} __packed q80_rcv_cntxt_destroy_rsp_t; 1171250661Sdavidcs 1172250661Sdavidcs 1173250661Sdavidcs/* 1174250661Sdavidcs * Add Receive Rings 1175250661Sdavidcs */ 1176250661Sdavidcstypedef struct _q80_rq_add_rcv_rings { 1177250661Sdavidcs uint16_t opcode; 1178250661Sdavidcs uint16_t count_version; 1179250661Sdavidcs uint8_t nrds_sets_rings; 1180250661Sdavidcs uint8_t nsds_rings; 1181250661Sdavidcs uint16_t cntxt_id; 1182250661Sdavidcs q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS]; 1183250661Sdavidcs q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS]; 1184250661Sdavidcs} __packed q80_rq_add_rcv_rings_t; 1185250661Sdavidcs 1186250661Sdavidcstypedef struct _q80_rsp_add_rcv_rings { 1187250661Sdavidcs uint16_t opcode; 1188250661Sdavidcs uint16_t regcnt_status; 1189250661Sdavidcs uint8_t nrds_sets_rings; 1190250661Sdavidcs uint8_t nsds_rings; 1191250661Sdavidcs uint16_t cntxt_id; 1192250661Sdavidcs uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS]; 1193250661Sdavidcs q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS]; 1194250661Sdavidcs} __packed q80_rsp_add_rcv_rings_t; 1195250661Sdavidcs 1196250661Sdavidcs/* 1197250661Sdavidcs * Map Status Ring to Receive Descriptor Set 1198250661Sdavidcs */ 1199250661Sdavidcs 1200250661Sdavidcs#define MAX_SDS_TO_RDS_MAP 16 1201250661Sdavidcs 1202250661Sdavidcstypedef struct _q80_sds_rds_map_e { 1203250661Sdavidcs uint8_t sds_ring; 1204250661Sdavidcs uint8_t rsrvd0; 1205250661Sdavidcs uint8_t rds_ring; 1206250661Sdavidcs uint8_t rsrvd1; 1207250661Sdavidcs} __packed q80_sds_rds_map_e_t; 1208250661Sdavidcs 1209250661Sdavidcstypedef struct _q80_rq_map_sds_to_rds { 1210250661Sdavidcs uint16_t opcode; 1211250661Sdavidcs uint16_t count_version; 1212250661Sdavidcs uint16_t cntxt_id; 1213250661Sdavidcs uint16_t num_rings; 1214250661Sdavidcs q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP]; 1215250661Sdavidcs} __packed q80_rq_map_sds_to_rds_t; 1216250661Sdavidcs 1217250661Sdavidcs 1218250661Sdavidcstypedef struct _q80_rsp_map_sds_to_rds { 1219250661Sdavidcs uint16_t opcode; 1220250661Sdavidcs uint16_t regcnt_status; 1221250661Sdavidcs uint16_t cntxt_id; 1222250661Sdavidcs uint16_t num_rings; 1223250661Sdavidcs q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP]; 1224250661Sdavidcs} __packed q80_rsp_map_sds_to_rds_t; 1225250661Sdavidcs 1226250661Sdavidcs 1227250661Sdavidcs/* 1228250661Sdavidcs * Receive Descriptor corresponding to each entry in the receive ring 1229250661Sdavidcs */ 1230250661Sdavidcstypedef struct _q80_rcv_desc { 1231250661Sdavidcs uint16_t handle; 1232250661Sdavidcs uint16_t rsrvd; 1233250661Sdavidcs uint32_t buf_size; /* buffer size in bytes */ 1234250661Sdavidcs uint64_t buf_addr; /* physical address of buffer */ 1235250661Sdavidcs} __packed q80_recv_desc_t; 1236250661Sdavidcs 1237250661Sdavidcs/* 1238250661Sdavidcs * Status Descriptor corresponding to each entry in the Status ring 1239250661Sdavidcs */ 1240250661Sdavidcstypedef struct _q80_stat_desc { 1241250661Sdavidcs uint64_t data[2]; 1242250661Sdavidcs} __packed q80_stat_desc_t; 1243250661Sdavidcs 1244250661Sdavidcs/* 1245250661Sdavidcs * definitions for data[0] field of Status Descriptor 1246250661Sdavidcs */ 1247250661Sdavidcs#define Q8_STAT_DESC_RSS_HASH(data) (data & 0xFFFFFFFF) 1248250661Sdavidcs#define Q8_STAT_DESC_TOTAL_LENGTH(data) ((data >> 32) & 0x3FFF) 1249250661Sdavidcs#define Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(data) ((data >> 32) & 0xFFFF) 1250250661Sdavidcs#define Q8_STAT_DESC_HANDLE(data) ((data >> 48) & 0xFFFF) 1251250661Sdavidcs/* 1252250661Sdavidcs * definitions for data[1] field of Status Descriptor 1253250661Sdavidcs */ 1254250661Sdavidcs 1255250661Sdavidcs#define Q8_STAT_DESC_OPCODE(data) ((data >> 42) & 0xF) 1256250661Sdavidcs#define Q8_STAT_DESC_OPCODE_RCV_PKT 0x01 1257250661Sdavidcs#define Q8_STAT_DESC_OPCODE_LRO_PKT 0x02 1258250661Sdavidcs#define Q8_STAT_DESC_OPCODE_SGL_LRO 0x04 1259250661Sdavidcs#define Q8_STAT_DESC_OPCODE_SGL_RCV 0x05 1260250661Sdavidcs#define Q8_STAT_DESC_OPCODE_CONT 0x06 1261250661Sdavidcs 1262250661Sdavidcs/* 1263250661Sdavidcs * definitions for data[1] field of Status Descriptor for standard frames 1264250661Sdavidcs * status descriptor opcode equals 0x04 1265250661Sdavidcs */ 1266250661Sdavidcs#define Q8_STAT_DESC_STATUS(data) ((data >> 39) & 0x0007) 1267250661Sdavidcs#define Q8_STAT_DESC_STATUS_CHKSUM_NOT_DONE 0x00 1268250661Sdavidcs#define Q8_STAT_DESC_STATUS_NO_CHKSUM 0x01 1269250661Sdavidcs#define Q8_STAT_DESC_STATUS_CHKSUM_OK 0x02 1270250661Sdavidcs#define Q8_STAT_DESC_STATUS_CHKSUM_ERR 0x03 1271250661Sdavidcs 1272250661Sdavidcs#define Q8_STAT_DESC_VLAN(data) ((data >> 47) & 1) 1273250661Sdavidcs#define Q8_STAT_DESC_VLAN_ID(data) ((data >> 48) & 0xFFFF) 1274250661Sdavidcs 1275250661Sdavidcs#define Q8_STAT_DESC_PROTOCOL(data) ((data >> 44) & 0x000F) 1276250661Sdavidcs#define Q8_STAT_DESC_L2_OFFSET(data) ((data >> 48) & 0x001F) 1277250661Sdavidcs#define Q8_STAT_DESC_COUNT(data) ((data >> 37) & 0x0007) 1278250661Sdavidcs 1279250661Sdavidcs/* 1280250661Sdavidcs * definitions for data[0-1] fields of Status Descriptor for LRO 1281250661Sdavidcs * status descriptor opcode equals 0x04 1282250661Sdavidcs */ 1283250661Sdavidcs 1284250661Sdavidcs/* definitions for data[1] field */ 1285250661Sdavidcs#define Q8_LRO_STAT_DESC_SEQ_NUM(data) (uint32_t)(data) 1286250661Sdavidcs 1287250661Sdavidcs/* 1288250661Sdavidcs * definitions specific to opcode 0x04 data[1] 1289250661Sdavidcs */ 1290250661Sdavidcs#define Q8_STAT_DESC_COUNT_SGL_LRO(data) ((data >> 13) & 0x0007) 1291250661Sdavidcs#define Q8_SGL_LRO_STAT_L2_OFFSET(data) ((data >> 16) & 0xFF) 1292250661Sdavidcs#define Q8_SGL_LRO_STAT_L4_OFFSET(data) ((data >> 24) & 0xFF) 1293250661Sdavidcs#define Q8_SGL_LRO_STAT_TS(data) ((data >> 40) & 0x1) 1294250661Sdavidcs#define Q8_SGL_LRO_STAT_PUSH_BIT(data) ((data >> 41) & 0x1) 1295250661Sdavidcs 1296250661Sdavidcs 1297250661Sdavidcs/* 1298250661Sdavidcs * definitions specific to opcode 0x05 data[1] 1299250661Sdavidcs */ 1300250661Sdavidcs#define Q8_STAT_DESC_COUNT_SGL_RCV(data) ((data >> 37) & 0x0003) 1301250661Sdavidcs 1302250661Sdavidcs/* 1303250661Sdavidcs * definitions for opcode 0x06 1304250661Sdavidcs */ 1305250661Sdavidcs/* definitions for data[0] field */ 1306250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE1(data) (data & 0xFFFF) 1307250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE2(data) ((data >> 16) & 0xFFFF) 1308250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE3(data) ((data >> 32) & 0xFFFF) 1309250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE4(data) ((data >> 48) & 0xFFFF) 1310250661Sdavidcs 1311250661Sdavidcs/* definitions for data[1] field */ 1312250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE5(data) (data & 0xFFFF) 1313250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE6(data) ((data >> 16) & 0xFFFF) 1314250661Sdavidcs#define Q8_SGL_STAT_DESC_NUM_HANDLES(data) ((data >> 32) & 0x7) 1315250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE7(data) ((data >> 48) & 0xFFFF) 1316250661Sdavidcs 1317250661Sdavidcs/** Driver Related Definitions Begin **/ 1318250661Sdavidcs 1319250661Sdavidcs#define TX_SMALL_PKT_SIZE 128 /* size in bytes of small packets */ 1320250661Sdavidcs 1321250661Sdavidcs/* The number of descriptors should be a power of 2 */ 1322250661Sdavidcs#define NUM_TX_DESCRIPTORS 1024 1323250661Sdavidcs#define NUM_STATUS_DESCRIPTORS 1024 1324250661Sdavidcs 1325250661Sdavidcs 1326250661Sdavidcs#define NUM_RX_DESCRIPTORS 2048 1327250661Sdavidcs#define MAX_RDS_RINGS MAX_SDS_RINGS /* Max# of Rcv Descriptor Rings */ 1328250661Sdavidcs 1329250661Sdavidcs/* 1330250661Sdavidcs * structure describing various dma buffers 1331250661Sdavidcs */ 1332250661Sdavidcs 1333250661Sdavidcstypedef struct qla_dmabuf { 1334250661Sdavidcs volatile struct { 1335250661Sdavidcs uint32_t tx_ring :1, 1336250661Sdavidcs rds_ring :1, 1337250661Sdavidcs sds_ring :1, 1338250661Sdavidcs minidump :1; 1339250661Sdavidcs } flags; 1340250661Sdavidcs 1341250661Sdavidcs qla_dma_t tx_ring; 1342250661Sdavidcs qla_dma_t rds_ring[MAX_RDS_RINGS]; 1343250661Sdavidcs qla_dma_t sds_ring[MAX_SDS_RINGS]; 1344250661Sdavidcs qla_dma_t minidump; 1345250661Sdavidcs} qla_dmabuf_t; 1346250661Sdavidcs 1347250661Sdavidcstypedef struct _qla_sds { 1348250661Sdavidcs q80_stat_desc_t *sds_ring_base; /* start of sds ring */ 1349250661Sdavidcs uint32_t sdsr_next; /* next entry in SDS ring to process */ 1350250661Sdavidcs struct lro_ctrl lro; 1351250661Sdavidcs void *rxb_free; 1352250661Sdavidcs uint32_t rx_free; 1353250661Sdavidcs volatile uint32_t rcv_active; 1354250661Sdavidcs uint32_t sds_consumer; 1355250661Sdavidcs uint64_t intr_count; 1356250661Sdavidcs} qla_sds_t; 1357250661Sdavidcs 1358250661Sdavidcs#define Q8_MAX_LRO_CONT_DESC 7 1359250661Sdavidcs#define Q8_MAX_HANDLES_LRO (1 + (Q8_MAX_LRO_CONT_DESC * 7)) 1360250661Sdavidcs#define Q8_MAX_HANDLES_NON_LRO 8 1361250661Sdavidcs 1362250661Sdavidcstypedef struct _qla_sgl_rcv { 1363250661Sdavidcs uint16_t pkt_length; 1364250661Sdavidcs uint16_t num_handles; 1365250661Sdavidcs uint16_t chksum_status; 1366250661Sdavidcs uint32_t rss_hash; 1367250661Sdavidcs uint16_t rss_hash_flags; 1368250661Sdavidcs uint16_t vlan_tag; 1369250661Sdavidcs uint16_t handle[Q8_MAX_HANDLES_NON_LRO]; 1370250661Sdavidcs} qla_sgl_rcv_t; 1371250661Sdavidcs 1372250661Sdavidcstypedef struct _qla_sgl_lro { 1373250661Sdavidcs uint16_t flags; 1374250661Sdavidcs#define Q8_LRO_COMP_TS 0x1 1375250661Sdavidcs#define Q8_LRO_COMP_PUSH_BIT 0x2 1376250661Sdavidcs uint16_t l2_offset; 1377250661Sdavidcs uint16_t l4_offset; 1378250661Sdavidcs 1379250661Sdavidcs uint16_t payload_length; 1380250661Sdavidcs uint16_t num_handles; 1381250661Sdavidcs uint32_t rss_hash; 1382250661Sdavidcs uint16_t rss_hash_flags; 1383250661Sdavidcs uint16_t vlan_tag; 1384250661Sdavidcs uint16_t handle[Q8_MAX_HANDLES_LRO]; 1385250661Sdavidcs} qla_sgl_lro_t; 1386250661Sdavidcs 1387250661Sdavidcstypedef union { 1388250661Sdavidcs qla_sgl_rcv_t rcv; 1389250661Sdavidcs qla_sgl_lro_t lro; 1390250661Sdavidcs} qla_sgl_comp_t; 1391250661Sdavidcs 1392250661Sdavidcs#define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\ 1393250661Sdavidcs sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16) 1394250661Sdavidcs 1395250661Sdavidcstypedef struct _qla_hw_tx_cntxt { 1396250661Sdavidcs q80_tx_cmd_t *tx_ring_base; 1397250661Sdavidcs bus_addr_t tx_ring_paddr; 1398250661Sdavidcs 1399250661Sdavidcs volatile uint32_t *tx_cons; /* tx consumer shadow reg */ 1400250661Sdavidcs bus_addr_t tx_cons_paddr; 1401250661Sdavidcs 1402250661Sdavidcs volatile uint32_t txr_free; /* # of free entries in tx ring */ 1403250661Sdavidcs volatile uint32_t txr_next; /* # next available tx ring entry */ 1404250661Sdavidcs volatile uint32_t txr_comp; /* index of last tx entry completed */ 1405250661Sdavidcs 1406250661Sdavidcs uint32_t tx_prod_reg; 1407250661Sdavidcs uint16_t tx_cntxt_id; 1408250661Sdavidcs uint8_t frame_hdr[QL_FRAME_HDR_SIZE]; 1409250661Sdavidcs 1410250661Sdavidcs} qla_hw_tx_cntxt_t; 1411250661Sdavidcs 1412250661Sdavidcstypedef struct _qla_mcast { 1413250661Sdavidcs uint16_t rsrvd; 1414250661Sdavidcs uint8_t addr[6]; 1415250661Sdavidcs} __packed qla_mcast_t; 1416250661Sdavidcs 1417250661Sdavidcstypedef struct _qla_rdesc { 1418250661Sdavidcs volatile uint32_t prod_std; 1419250661Sdavidcs volatile uint32_t prod_jumbo; 1420250661Sdavidcs volatile uint32_t rx_next; /* next standard rcv ring to arm fw */ 1421250661Sdavidcs volatile int32_t rx_in; /* next standard rcv ring to add mbufs */ 1422250661Sdavidcs volatile uint64_t count; 1423250661Sdavidcs} qla_rdesc_t; 1424250661Sdavidcs 1425250661Sdavidcstypedef struct _qla_flash_desc_table { 1426250661Sdavidcs uint32_t flash_valid; 1427250661Sdavidcs uint16_t flash_ver; 1428250661Sdavidcs uint16_t flash_len; 1429250661Sdavidcs uint16_t flash_cksum; 1430250661Sdavidcs uint16_t flash_unused; 1431250661Sdavidcs uint8_t flash_model[16]; 1432250661Sdavidcs uint16_t flash_manuf; 1433250661Sdavidcs uint16_t flash_id; 1434250661Sdavidcs uint8_t flash_flag; 1435250661Sdavidcs uint8_t erase_cmd; 1436250661Sdavidcs uint8_t alt_erase_cmd; 1437250661Sdavidcs uint8_t write_enable_cmd; 1438250661Sdavidcs uint8_t write_enable_bits; 1439250661Sdavidcs uint8_t write_statusreg_cmd; 1440250661Sdavidcs uint8_t unprotected_sec_cmd; 1441250661Sdavidcs uint8_t read_manuf_cmd; 1442250661Sdavidcs uint32_t block_size; 1443250661Sdavidcs uint32_t alt_block_size; 1444250661Sdavidcs uint32_t flash_size; 1445250661Sdavidcs uint32_t write_enable_data; 1446250661Sdavidcs uint8_t readid_addr_len; 1447250661Sdavidcs uint8_t write_disable_bits; 1448250661Sdavidcs uint8_t read_dev_id_len; 1449250661Sdavidcs uint8_t chip_erase_cmd; 1450250661Sdavidcs uint16_t read_timeo; 1451250661Sdavidcs uint8_t protected_sec_cmd; 1452250661Sdavidcs uint8_t resvd[65]; 1453250661Sdavidcs} __packed qla_flash_desc_table_t; 1454250661Sdavidcs 1455250661Sdavidcs#define NUM_TX_RINGS 4 1456250661Sdavidcs 1457250661Sdavidcs/* 1458250661Sdavidcs * struct for storing hardware specific information for a given interface 1459250661Sdavidcs */ 1460250661Sdavidcstypedef struct _qla_hw { 1461250661Sdavidcs struct { 1462250661Sdavidcs uint32_t 1463250661Sdavidcs unicast_mac :1, 1464250661Sdavidcs bcast_mac :1, 1465250661Sdavidcs loopback_mode :2, 1466250661Sdavidcs init_tx_cnxt :1, 1467250661Sdavidcs init_rx_cnxt :1, 1468250661Sdavidcs init_intr_cnxt :1, 1469250661Sdavidcs fduplex :1, 1470250661Sdavidcs autoneg :1, 1471250661Sdavidcs fdt_valid :1; 1472250661Sdavidcs } flags; 1473250661Sdavidcs 1474250661Sdavidcs 1475250661Sdavidcs uint16_t link_speed; 1476250661Sdavidcs uint16_t cable_length; 1477250661Sdavidcs uint32_t cable_oui; 1478250661Sdavidcs uint8_t link_up; 1479250661Sdavidcs uint8_t module_type; 1480250661Sdavidcs uint8_t link_faults; 1481250661Sdavidcs 1482250661Sdavidcs uint8_t mac_rcv_mode; 1483250661Sdavidcs 1484250661Sdavidcs uint32_t max_mtu; 1485250661Sdavidcs 1486250661Sdavidcs uint8_t mac_addr[ETHER_ADDR_LEN]; 1487250661Sdavidcs 1488250661Sdavidcs uint32_t num_sds_rings; 1489250661Sdavidcs uint32_t num_rds_rings; 1490250661Sdavidcs uint32_t num_tx_rings; 1491250661Sdavidcs 1492250661Sdavidcs qla_dmabuf_t dma_buf; 1493250661Sdavidcs 1494250661Sdavidcs /* Transmit Side */ 1495250661Sdavidcs 1496250661Sdavidcs qla_hw_tx_cntxt_t tx_cntxt[NUM_TX_RINGS]; 1497250661Sdavidcs 1498250661Sdavidcs /* Receive Side */ 1499250661Sdavidcs 1500250661Sdavidcs uint16_t rcv_cntxt_id; 1501250661Sdavidcs 1502250661Sdavidcs uint32_t mbx_intr_mask_offset; 1503250661Sdavidcs 1504250661Sdavidcs uint16_t intr_id[MAX_SDS_RINGS]; 1505250661Sdavidcs uint32_t intr_src[MAX_SDS_RINGS]; 1506250661Sdavidcs 1507250661Sdavidcs qla_sds_t sds[MAX_SDS_RINGS]; 1508250661Sdavidcs uint32_t mbox[Q8_NUM_MBOX]; 1509250661Sdavidcs qla_rdesc_t rds[MAX_RDS_RINGS]; 1510250661Sdavidcs 1511250661Sdavidcs uint32_t rds_pidx_thres; 1512250661Sdavidcs uint32_t sds_cidx_thres; 1513250661Sdavidcs 1514250661Sdavidcs /* multicast address list */ 1515250661Sdavidcs uint32_t nmcast; 1516250661Sdavidcs qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS]; 1517250661Sdavidcs 1518250661Sdavidcs /* reset sequence */ 1519250661Sdavidcs#define Q8_MAX_RESET_SEQ_IDX 16 1520250661Sdavidcs uint32_t rst_seq[Q8_MAX_RESET_SEQ_IDX]; 1521250661Sdavidcs uint32_t rst_seq_idx; 1522250661Sdavidcs 1523250661Sdavidcs /* heart beat register value */ 1524250661Sdavidcs uint32_t hbeat_value; 1525250661Sdavidcs uint32_t health_count; 1526250661Sdavidcs 1527250661Sdavidcs uint32_t max_tx_segs; 1528258898Sdavidcs uint32_t min_lro_pkt_size; 1529250661Sdavidcs 1530250661Sdavidcs /* Flash Descriptor Table */ 1531250661Sdavidcs qla_flash_desc_table_t fdt; 1532250661Sdavidcs 1533250661Sdavidcs /* Minidump Related */ 1534250661Sdavidcs uint32_t mdump_init; 1535250661Sdavidcs uint32_t mdump_start; 1536250661Sdavidcs uint32_t mdump_active; 1537250661Sdavidcs uint32_t mdump_start_seq_index; 1538250661Sdavidcs} qla_hw_t; 1539250661Sdavidcs 1540250661Sdavidcs#define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \ 1541258898Sdavidcs bus_write_4((ha->pci_reg), prod_reg, val); 1542250661Sdavidcs 1543250661Sdavidcs#define QL_UPDATE_TX_PRODUCER_INDEX(ha, val, i) \ 1544258898Sdavidcs WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val) 1545250661Sdavidcs 1546250661Sdavidcs#define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \ 1547258898Sdavidcs bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val); 1548250661Sdavidcs 1549258898Sdavidcs#define QL_ENABLE_INTERRUPTS(ha, i) \ 1550258898Sdavidcs bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0); 1551250661Sdavidcs 1552250661Sdavidcs#define QL_BUFFER_ALIGN 16 1553250661Sdavidcs 1554250661Sdavidcs 1555250661Sdavidcs/* 1556250661Sdavidcs * Flash Configuration 1557250661Sdavidcs */ 1558250661Sdavidcs#define Q8_BOARD_CONFIG_OFFSET 0x370000 1559250661Sdavidcs#define Q8_BOARD_CONFIG_LENGTH 0x2000 1560250661Sdavidcs 1561250661Sdavidcs#define Q8_BOARD_CONFIG_MAC0_LO 0x400 1562250661Sdavidcs 1563250661Sdavidcs#define Q8_FDT_LOCK_MAGIC_ID 0x00FD00FD 1564250661Sdavidcs#define Q8_FDT_FLASH_ADDR_VAL 0xFD009F 1565250661Sdavidcs#define Q8_FDT_FLASH_CTRL_VAL 0x3F 1566250661Sdavidcs#define Q8_FDT_MASK_VAL 0xFF 1567250661Sdavidcs 1568250661Sdavidcs#define Q8_WR_ENABLE_FL_ADDR 0xFD0100 1569250661Sdavidcs#define Q8_WR_ENABLE_FL_CTRL 0x5 1570250661Sdavidcs 1571250661Sdavidcs#define Q8_ERASE_LOCK_MAGIC_ID 0x00EF00EF 1572250661Sdavidcs#define Q8_ERASE_FL_ADDR_MASK 0xFD0300 1573250661Sdavidcs#define Q8_ERASE_FL_CTRL_MASK 0x3D 1574250661Sdavidcs 1575250661Sdavidcs#define Q8_WR_FL_LOCK_MAGIC_ID 0xABCDABCD 1576250661Sdavidcs#define Q8_WR_FL_ADDR_MASK 0x800000 1577250661Sdavidcs#define Q8_WR_FL_CTRL_MASK 0x3D 1578250661Sdavidcs 1579250661Sdavidcs#define QL_FDT_OFFSET 0x3F0000 1580250661Sdavidcs#define Q8_FLASH_SECTOR_SIZE 0x10000 1581250661Sdavidcs 1582250661Sdavidcs/* 1583250661Sdavidcs * Off Chip Memory Access 1584250661Sdavidcs */ 1585250661Sdavidcs 1586250661Sdavidcstypedef struct _q80_offchip_mem_val { 1587250661Sdavidcs uint32_t data_lo; 1588250661Sdavidcs uint32_t data_hi; 1589250661Sdavidcs uint32_t data_ulo; 1590250661Sdavidcs uint32_t data_uhi; 1591250661Sdavidcs} q80_offchip_mem_val_t; 1592250661Sdavidcs 1593250661Sdavidcs#endif /* #ifndef _QL_HW_H_ */ 1594