1/* 2 * Copyright (c) 2010-2011 Qlogic Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29/* 30 * File: qla_hw.h 31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32 */ 33#ifndef _QLA_HW_H_ 34#define _QLA_HW_H_ 35 36#define Q8_MAX_NUM_MULTICAST_ADDRS 128 37#define Q8_MAC_ADDR_LEN 6 38 39/* 40 * Firmware Interface 41 */ 42 43/* 44 * Command Response Interface - Commands 45 */ 46typedef struct qla_cdrp { 47 uint32_t cmd; 48 uint32_t cmd_arg1; 49 uint32_t cmd_arg2; 50 uint32_t cmd_arg3; 51 uint32_t rsp; 52 uint32_t rsp_arg1; 53 uint32_t rsp_arg2; 54 uint32_t rsp_arg3; 55} qla_cdrp_t; 56 57#define Q8_CMD_RD_MAX_RDS_PER_CNTXT 0x80000002 58#define Q8_CMD_RD_MAX_SDS_PER_CNTXT 0x80000003 59#define Q8_CMD_RD_MAX_RULES_PER_CNTXT 0x80000004 60#define Q8_CMD_RD_MAX_RX_CNTXT 0x80000005 61#define Q8_CMD_RD_MAX_TX_CNTXT 0x80000006 62#define Q8_CMD_CREATE_RX_CNTXT 0x80000007 63#define Q8_CMD_DESTROY_RX_CNTXT 0x80000008 64#define Q8_CMD_CREATE_TX_CNTXT 0x80000009 65#define Q8_CMD_DESTROY_TX_CNTXT 0x8000000A 66#define Q8_CMD_SETUP_STATS 0x8000000E 67#define Q8_CMD_GET_STATS 0x8000000F 68#define Q8_CMD_DELETE_STATS 0x80000010 69#define Q8_CMD_GEN_INT 0x80000011 70#define Q8_CMD_SET_MTU 0x80000012 71#define Q8_CMD_GET_FLOW_CNTRL 0x80000016 72#define Q8_CMD_SET_FLOW_CNTRL 0x80000017 73#define Q8_CMD_RD_MAX_MTU 0x80000018 74#define Q8_CMD_RD_MAX_LRO 0x80000019 75 76/* 77 * Command Response Interface - Response 78 */ 79#define Q8_RSP_SUCCESS 0x00000000 80#define Q8_RSP_NO_HOST_MEM 0x00000001 81#define Q8_RSP_NO_HOST_RSRC 0x00000002 82#define Q8_RSP_NO_CARD_CRB 0x00000003 83#define Q8_RSP_NO_CARD_MEM 0x00000004 84#define Q8_RSP_NO_CARD_RSRC 0x00000005 85#define Q8_RSP_INVALID_ARGS 0x00000006 86#define Q8_RSP_INVALID_ACTION 0x00000007 87#define Q8_RSP_INVALID_STATE 0x00000008 88#define Q8_RSP_NOT_SUPPORTED 0x00000009 89#define Q8_RSP_NOT_PERMITTED 0x0000000A 90#define Q8_RSP_NOT_READY 0x0000000B 91#define Q8_RSP_DOES_NOT_EXIST 0x0000000C 92#define Q8_RSP_ALREADY_EXISTS 0x0000000D 93#define Q8_RSP_BAD_SIGNATURE 0x0000000E 94#define Q8_RSP_CMD_NOT_IMPLEMENTED 0x0000000F 95#define Q8_RSP_CMD_INVALID 0x00000010 96#define Q8_RSP_TIMEOUT 0x00000011 97 98 99/* 100 * Transmit Related Definitions 101 */ 102 103/* 104 * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data 105 */ 106 107typedef struct _q80_tx_cntxt_req { 108 uint64_t rsp_dma_addr; /* rsp from firmware is DMA'ed here */ 109 uint64_t cmd_cons_dma_addr; 110 uint64_t rsrvd0; 111 112 uint32_t caps[4]; /* capabilities - bit vector*/ 113#define CNTXT_CAP0_BASEFW 0x0001 114#define CNTXT_CAP0_LEGACY_MN 0x0004 115#define CNTXT_CAP0_LSO 0x0040 116 117 uint32_t intr_mode; /* Interrupt Mode */ 118#define CNTXT_INTR_MODE_UNIQUE 0x0000 119#define CNTXT_INTR_MODE_SHARED 0x0001 120 121 uint64_t rsrvd1; 122 uint16_t msi_index; 123 uint16_t rsrvd2; 124 uint64_t phys_addr; /* physical address of transmit ring 125 * in system memory */ 126 uint32_t num_entries; /* number of entries in transmit ring */ 127 uint8_t rsrvd3[128]; 128} __packed q80_tx_cntxt_req_t; /* 188 bytes total */ 129 130 131/* 132 * Transmit Context - Response from Firmware to Q8_CMD_CREATE_TX_CNTXT 133 */ 134 135typedef struct _q80_tx_cntxt_rsp { 136 uint32_t cntxt_state; /* starting state */ 137#define CNTXT_STATE_ALLOCATED_NOT_ACTIVE 0x0001 138#define CNTXT_STATE_ACTIVE 0x0002 139#define CNTXT_STATE_QUIESCED 0x0004 140 141 uint16_t cntxt_id; /* handle for context */ 142 uint8_t phys_port_id; /* physical id of port */ 143 uint8_t virt_port_id; /* virtual or logical id of port */ 144 uint32_t producer_reg; /* producer register for transmit ring */ 145 uint32_t intr_mask_reg; /* interrupt mask register */ 146 uint8_t rsrvd[128]; 147} __packed q80_tx_cntxt_rsp_t; /* 144 bytes */ 148 149/* 150 * Transmit Command Descriptor 151 * These commands are issued on the Transmit Ring associated with a Transmit 152 * context 153 */ 154typedef struct _q80_tx_cmd { 155 uint8_t tcp_hdr_off; /* TCP Header Offset */ 156 uint8_t ip_hdr_off; /* IP Header Offset */ 157 uint16_t flags_opcode; /* Bits 0-6: flags; 7-12: opcode */ 158 159 /* flags field */ 160#define Q8_TX_CMD_FLAGS_MULTICAST 0x01 161#define Q8_TX_CMD_FLAGS_LSO_TSO 0x02 162#define Q8_TX_CMD_FLAGS_VLAN_TAGGED 0x10 163#define Q8_TX_CMD_FLAGS_HW_VLAN_ID 0x40 164 165 /* opcode field */ 166#define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6 (0xC << 7) 167#define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6 (0xB << 7) 168#define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6 (0x6 << 7) 169#define Q8_TX_CMD_OP_XMT_TCP_LSO (0x5 << 7) 170#define Q8_TX_CMD_OP_XMT_UDP_CHKSUM (0x3 << 7) 171#define Q8_TX_CMD_OP_XMT_TCP_CHKSUM (0x2 << 7) 172#define Q8_TX_CMD_OP_XMT_ETHER (0x1 << 7) 173 174 uint8_t n_bufs; /* # of data segs in data buffer */ 175 uint8_t data_len_lo; /* data length lower 8 bits */ 176 uint16_t data_len_hi; /* data length upper 16 bits */ 177 178 uint64_t buf2_addr; /* buffer 2 address */ 179 180 uint16_t rsrvd0; 181 uint16_t mss; /* MSS for this packet */ 182 uint8_t port_cntxtid; /* Bits 7-4: ContextId; 3-0: reserved */ 183 184#define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4) 185 186 uint8_t total_hdr_len; /* MAC+IP+TCP Header Length for LSO */ 187 uint16_t rsrvd1; 188 189 uint64_t buf3_addr; /* buffer 3 address */ 190 uint64_t buf1_addr; /* buffer 1 address */ 191 192 uint16_t buf1_len; /* length of buffer 1 */ 193 uint16_t buf2_len; /* length of buffer 2 */ 194 uint16_t buf3_len; /* length of buffer 3 */ 195 uint16_t buf4_len; /* length of buffer 4 */ 196 197 uint64_t buf4_addr; /* buffer 4 address */ 198 199 uint32_t rsrvd2; 200 uint16_t rsrvd3; 201 uint16_t vlan_tci; /* VLAN TCI when hw tagging is enabled*/ 202 203} __packed q80_tx_cmd_t; /* 64 bytes */ 204 205#define Q8_TX_CMD_MAX_SEGMENTS 4 206#define Q8_TX_CMD_TSO_ALIGN 2 207#define Q8_TX_MAX_SEGMENTS 14 208 209 210/* 211 * Receive Related Definitions 212 */ 213/* 214 * Receive Context - Q8_CMD_CREATE_RX_CNTXT Command Configuration Data 215 */ 216 217typedef struct _q80_rq_sds_ring { 218 uint64_t phys_addr; /* physical addr of status ring in system memory */ 219 uint32_t size; /* number of entries in status ring */ 220 uint16_t msi_index; 221 uint16_t rsrvd; 222} __packed q80_rq_sds_ring_t; /* 16 bytes */ 223 224typedef struct _q80_rq_rds_ring { 225 uint64_t phys_addr; /* physical addr of rcv ring in system memory */ 226 uint64_t buf_size; /* packet buffer size */ 227 uint32_t size; /* number of entries in ring */ 228 uint32_t rsrvd; 229} __packed q80_rq_rds_ring_t; /* 24 bytes */ 230 231typedef struct _q80_rq_rcv_cntxt { 232 uint64_t rsp_dma_addr; /* rsp from firmware is DMA'ed here */ 233 uint32_t caps[4]; /* bit vector */ 234#define CNTXT_CAP0_JUMBO 0x0080 /* Contiguous Jumbo buffers*/ 235#define CNTXT_CAP0_LRO 0x0100 236#define CNTXT_CAP0_HW_LRO 0x0800 /* HW LRO */ 237 238 uint32_t intr_mode; /* same as q80_tx_cntxt_req_t */ 239 uint32_t rds_intr_mode; /* same as q80_tx_cntxt_req_t */ 240 241 uint32_t rds_ring_offset; /* rds configuration relative to data[0] */ 242 uint32_t sds_ring_offset; /* sds configuration relative to data[0] */ 243 244 uint16_t num_rds_rings; 245 uint16_t num_sds_rings; 246 247 uint8_t rsrvd1[132]; 248} __packed q80_rq_rcv_cntxt_t; /* 176 bytes header + rds + sds ring rqsts */ 249 250/* 251 * Receive Context - Response from Firmware to Q8_CMD_CREATE_RX_CNTXT 252 */ 253 254typedef struct _q80_rsp_rds_ring { 255 uint32_t producer_reg; 256 uint32_t rsrvd; 257} __packed q80_rsp_rds_ring_t; /* 8 bytes */ 258 259typedef struct _q80_rsp_sds_ring { 260 uint32_t consumer_reg; 261 uint32_t intr_mask_reg; 262} __packed q80_rsp_sds_ring_t; /* 8 bytes */ 263 264typedef struct _q80_rsp_rcv_cntxt { 265 uint32_t rds_ring_offset; /* rds configuration relative to data[0] */ 266 uint32_t sds_ring_offset; /* sds configuration relative to data[0] */ 267 268 uint32_t cntxt_state; /* starting state */ 269 uint32_t funcs_per_port; /* number of PCI functions sharing each port */ 270 271 uint16_t num_rds_rings; 272 uint16_t num_sds_rings; 273 274 uint16_t cntxt_id; /* handle for context */ 275 276 uint8_t phys_port; /* physical id of port */ 277 uint8_t virt_port; /* virtual or logical id of port */ 278 279 uint8_t rsrvd[128]; 280 uint8_t data[0]; 281} __packed q80_rsp_rcv_cntxt_t; /* 152 bytes header + rds + sds ring rspncs */ 282 283 284/* 285 * Note: 286 * Transmit Context 287 * 188 (rq) + 144 (rsp) = 332 bytes are required 288 * 289 * Receive Context 290 * 1 RDS and 1 SDS rings: (16+24+176)+(8+8+152) = 384 bytes 291 * 292 * 3 RDS and 4 SDS rings: (((16+24)*3)+176) + (((8+8)*4)+152) = 293 * = 296 + 216 = 512 bytes 294 * Clearly this within the minimum PAGE size of most O.S platforms 295 * (typically 4Kbytes). Hence it is simpler to simply allocate one PAGE 296 * and then carve out space for each context. It is also a good idea to 297 * to throw in the shadown register for the consumer index of the transmit 298 * ring in this PAGE. 299 */ 300 301/* 302 * Receive Descriptor corresponding to each entry in the receive ring 303 */ 304typedef struct _q80_rcv_desc { 305 uint16_t handle; 306 uint16_t rsrvd; 307 uint32_t buf_size; /* buffer size in bytes */ 308 uint64_t buf_addr; /* physical address of buffer */ 309} __packed q80_recv_desc_t; 310 311/* 312 * Status Descriptor corresponding to each entry in the Status ring 313 */ 314typedef struct _q80_stat_desc { 315 uint64_t data[2]; 316} __packed q80_stat_desc_t; 317 318/* 319 * definitions for data[0] field of Status Descriptor 320 */ 321#define Q8_STAT_DESC_OWNER(data) ((data >> 56) & 0x3) 322#define Q8_STAT_DESC_OWNER_HOST 0x1 323#define Q8_STAT_DESC_OWNER_FW 0x2 324 325#define Q8_STAT_DESC_OWNER_MASK (((uint64_t)0x3) << 56) 326#define Q8_STAT_DESC_SET_OWNER(owner) (uint64_t)(((uint64_t)owner) << 56) 327 328#define Q8_STAT_DESC_OPCODE(data) ((data >> 58) & 0x003F) 329#define Q8_STAT_DESC_OPCODE_SYN_OFFLOAD 0x03 330#define Q8_STAT_DESC_OPCODE_RCV_PKT 0x04 331#define Q8_STAT_DESC_OPCODE_CTRL_MSG 0x05 332#define Q8_STAT_DESC_OPCODE_LRO_PKT 0x12 333 334/* 335 * definitions for data[0] field of Status Descriptor for standard frames 336 * status descriptor opcode equals 0x04 337 */ 338#define Q8_STAT_DESC_PORT(data) ((data) & 0x000F) 339#define Q8_STAT_DESC_STATUS(data) ((data >> 4) & 0x000F) 340#define Q8_STAT_DESC_STATUS_NO_CHKSUM 0x01 341#define Q8_STAT_DESC_STATUS_CHKSUM_OK 0x02 342#define Q8_STAT_DESC_STATUS_CHKSUM_ERR 0x03 343 344#define Q8_STAT_DESC_TYPE(data) ((data >> 8) & 0x000F) 345#define Q8_STAT_DESC_TOTAL_LENGTH(data) ((data >> 12) & 0xFFFF) 346#define Q8_STAT_DESC_HANDLE(data) ((data >> 28) & 0xFFFF) 347#define Q8_STAT_DESC_PROTOCOL(data) ((data >> 44) & 0x000F) 348#define Q8_STAT_DESC_L2_OFFSET(data) ((data >> 48) & 0x001F) 349#define Q8_STAT_DESC_COUNT(data) ((data >> 53) & 0x0007) 350 351/* 352 * definitions for data[0-1] fields of Status Descriptor for LRO 353 * status descriptor opcode equals 0x05 354 */ 355/* definitions for data[0] field */ 356#define Q8_LRO_STAT_DESC_HANDLE(data) ((data) & 0xFFFF) 357#define Q8_LRO_STAT_DESC_PAYLOAD_LENGTH(data) ((data >> 16) & 0xFFFF) 358#define Q8_LRO_STAT_DESC_L2_OFFSET(data) ((data >> 32) & 0xFF) 359#define Q8_LRO_STAT_DESC_L4_OFFSET(data) ((data >> 40) & 0xFF) 360#define Q8_LRO_STAT_DESC_TS_PRESENT(data) ((data >> 48) & 0x1) 361#define Q8_LRO_STAT_DESC_TYPE(data) ((data >> 49) & 0x7) 362#define Q8_LRO_STAT_DESC_PUSH_BIT(data) ((data >> 52) & 0x1) 363 364/* definitions for data[1] field */ 365#define Q8_LRO_STAT_DESC_SEQ_NUM(data) (uint32_t)(data) 366 367/** Driver Related Definitions Begin **/ 368 369#define MAX_RDS_RINGS 2 /* Max# of Receive Descriptor Rings */ 370#define MAX_SDS_RINGS 4 /* Max# of Status Descriptor Rings */ 371#define TX_SMALL_PKT_SIZE 128 /* size in bytes of small packets */ 372 373/* The number of descriptors should be a power of 2 */ 374#define NUM_TX_DESCRIPTORS 2048 375#define NUM_RX_DESCRIPTORS 8192 376//#define NUM_RX_JUMBO_DESCRIPTORS 1024 377#define NUM_RX_JUMBO_DESCRIPTORS 2048 378//#define NUM_STATUS_DESCRIPTORS 8192 379#define NUM_STATUS_DESCRIPTORS 2048 380 381typedef struct _q80_rcv_cntxt_req { 382 q80_rq_rcv_cntxt_t rx_req; 383 q80_rq_rds_ring_t rds_req[MAX_RDS_RINGS]; 384 q80_rq_sds_ring_t sds_req[MAX_SDS_RINGS]; 385} __packed q80_rcv_cntxt_req_t; 386 387typedef struct _q80_rcv_cntxt_rsp { 388 q80_rsp_rcv_cntxt_t rx_rsp; 389 q80_rsp_rds_ring_t rds_rsp[MAX_RDS_RINGS]; 390 q80_rsp_sds_ring_t sds_rsp[MAX_SDS_RINGS]; 391} __packed q80_rcv_cntxt_rsp_t; 392 393/* 394 * structure describing various dma buffers 395 */ 396#define RDS_RING_INDEX_NORMAL 0 397#define RDS_RING_INDEX_JUMBO 1 398 399typedef struct qla_dmabuf { 400 volatile struct { 401 uint32_t tx_ring :1, 402 rds_ring :1, 403 sds_ring :1, 404 context :1; 405 } flags; 406 407 qla_dma_t tx_ring; 408 qla_dma_t rds_ring[MAX_RDS_RINGS]; 409 qla_dma_t sds_ring[MAX_SDS_RINGS]; 410 qla_dma_t context; 411} qla_dmabuf_t; 412 413/** Driver Related Definitions End **/ 414 415/* 416 * Firmware Control Descriptor 417 */ 418typedef struct _qla_fw_cds_hdr { 419 uint64_t cmd; 420#define Q8_FWCD_CNTRL_REQ (0x13 << 23) 421 uint8_t opcode; 422 uint8_t cookie; 423 uint16_t cntxt_id; 424 uint8_t response; 425#define Q8_FW_CDS_HDR_COMPLETION 0x1 426 uint16_t rsrvd; 427 uint8_t sub_opcode; 428} __packed qla_fw_cds_hdr_t; 429 430/* 431 * definitions for opcode in qla_fw_cds_hdr_t 432 */ 433#define Q8_FWCD_OPCODE_CONFIG_RSS 0x01 434#define Q8_FWCD_OPCODE_CONFIG_RSS_TABLE 0x02 435#define Q8_FWCD_OPCODE_CONFIG_INTR_COALESCING 0x03 436#define Q8_FWCD_OPCODE_CONFIG_LED 0x04 437#define Q8_FWCD_OPCODE_CONFIG_MAC_ADDR 0x06 438#define Q8_FWCD_OPCODE_LRO_FLOW 0x07 439#define Q8_FWCD_OPCODE_GET_SNMP_STATS 0x08 440#define Q8_FWCD_OPCODE_CONFIG_MAC_RCV_MODE 0x0C 441#define Q8_FWCD_OPCODE_STATISTICS 0x10 442#define Q8_FWCD_OPCODE_CONFIG_IPADDR 0x12 443#define Q8_FWCD_OPCODE_CONFIG_LOOPBACK 0x13 444#define Q8_FWCD_OPCODE_LINK_EVENT_REQ 0x15 445#define Q8_FWCD_OPCODE_CONFIG_BRIDGING 0x17 446#define Q8_FWCD_OPCODE_CONFIG_LRO 0x18 447 448/* 449 * Configure RSS 450 */ 451typedef struct _qla_fw_cds_config_rss { 452 qla_fw_cds_hdr_t hdr; 453 uint8_t hash_type; 454#define Q8_FWCD_RSS_HASH_TYPE_IPV4_TCP (0x2 << 4) 455#define Q8_FWCD_RSS_HASH_TYPE_IPV4_IP (0x1 << 4) 456#define Q8_FWCD_RSS_HASH_TYPE_IPV4_TCP_IP (0x3 << 4) 457#define Q8_FWCD_RSS_HASH_TYPE_IPV6_TCP (0x2 << 6) 458#define Q8_FWCD_RSS_HASH_TYPE_IPV6_IP (0x1 << 6) 459#define Q8_FWCD_RSS_HASH_TYPE_IPV6_TCP_IP (0x3 << 6) 460 461 uint8_t flags; 462#define Q8_FWCD_RSS_FLAGS_ENABLE_RSS 0x1 463#define Q8_FWCD_RSS_FLAGS_USE_IND_TABLE 0x2 464 uint8_t rsrvd[4]; 465 uint16_t ind_tbl_mask; 466 uint64_t rss_key[5]; 467} __packed qla_fw_cds_config_rss_t; 468 469/* 470 * Configure RSS Table 471 */ 472typedef struct _qla_fw_cds_config_rss_table { 473 qla_fw_cds_hdr_t hdr; 474 uint64_t index; 475 uint8_t table[40]; 476} __packed qla_fw_cds_config_rss_table_t; 477 478/* 479 * Configure Interrupt Coalescing 480 */ 481typedef struct _qla_fw_cds_config_intr_coalesc { 482 qla_fw_cds_hdr_t hdr; 483 uint16_t rsrvd0; 484 uint16_t rsrvd1; 485 uint16_t flags; 486 uint16_t rsrvd2; 487 uint64_t rsrvd3; 488 uint16_t max_rcv_pkts; 489 uint16_t max_rcv_usecs; 490 uint16_t max_snd_pkts; 491 uint16_t max_snd_usecs; 492 uint64_t rsrvd4; 493 uint64_t rsrvd5; 494 uint32_t usecs_to; 495 uint8_t timer_type; 496#define Q8_FWCMD_INTR_COALESC_TIMER_NONE 0x00 497#define Q8_FWCMD_INTR_COALESC_TIMER_ONCE 0x01 498#define Q8_FWCMD_INTR_COALESC_TIMER_PERIODIC 0x02 499 500 uint8_t sds_ring_bitmask; 501#define Q8_FWCMD_INTR_COALESC_SDS_RING_0 0x01 502#define Q8_FWCMD_INTR_COALESC_SDS_RING_1 0x02 503#define Q8_FWCMD_INTR_COALESC_SDS_RING_2 0x04 504#define Q8_FWCMD_INTR_COALESC_SDS_RING_3 0x08 505 506 uint16_t rsrvd6; 507} __packed qla_fw_cds_config_intr_coalesc_t; 508 509/* 510 * Configure LED Parameters 511 */ 512typedef struct _qla_fw_cds_config_led { 513 qla_fw_cds_hdr_t hdr; 514 uint32_t cntxt_id; 515 uint32_t blink_rate; 516 uint32_t blink_state; 517 uint32_t rsrvd; 518} __packed qla_fw_cds_config_led_t; 519 520/* 521 * Configure MAC Address 522 */ 523typedef struct _qla_fw_cds_config_mac_addr { 524 qla_fw_cds_hdr_t hdr; 525 uint8_t cmd; 526#define Q8_FWCD_ADD_MAC_ADDR 0x1 527#define Q8_FWCD_DEL_MAC_ADDR 0x2 528 uint8_t rsrvd; 529 uint8_t mac_addr[6]; 530} __packed qla_fw_cds_config_mac_addr_t; 531 532/* 533 * Configure Add/Delete LRO 534 */ 535typedef struct _qla_fw_cds_config_lro { 536 qla_fw_cds_hdr_t hdr; 537 uint32_t dst_ip_addr; 538 uint32_t src_ip_addr; 539 uint16_t dst_tcp_port; 540 uint16_t src_tcp_port; 541 uint8_t ipv6; 542 uint8_t time_stamp; 543 uint16_t rsrvd; 544 uint32_t rss_hash; 545 uint32_t host_handle; 546} __packed qla_fw_cds_config_lro_t; 547 548/* 549 * Get SNMP Statistics 550 */ 551typedef struct _qla_fw_cds_get_snmp { 552 qla_fw_cds_hdr_t hdr; 553 uint64_t phys_addr; 554 uint16_t size; 555 uint16_t cntxt_id; 556 uint32_t rsrvd; 557} __packed qla_fw_cds_get_snmp_t; 558 559typedef struct _qla_snmp_stats { 560 uint64_t jabber_state; 561 uint64_t false_carrier; 562 uint64_t rsrvd; 563 uint64_t mac_cntrl; 564 uint64_t align_errors; 565 uint64_t chksum_errors; 566 uint64_t oversize_frames; 567 uint64_t tx_errors; 568 uint64_t mac_rcv_errors; 569 uint64_t phy_rcv_errors; 570 uint64_t rcv_pause; 571 uint64_t tx_pause; 572} __packed qla_snmp_stats_t; 573 574/* 575 * Enable Link Event Requests 576 */ 577typedef struct _qla_link_event_req { 578 qla_fw_cds_hdr_t hdr; 579 uint8_t enable; 580 uint8_t get_clnk_params; 581 uint8_t pad[6]; 582} __packed qla_link_event_req_t; 583 584 585/* 586 * Set MAC Receive Mode 587 */ 588typedef struct _qla_set_mac_rcv_mode { 589 qla_fw_cds_hdr_t hdr; 590 591 uint32_t mode; 592#define Q8_MAC_RCV_RESET_PROMISC_ALLMULTI 0x00 593#define Q8_MAC_RCV_ENABLE_PROMISCUOUS 0x01 594#define Q8_MAC_RCV_ENABLE_ALLMULTI 0x02 595 596 uint8_t pad[4]; 597} __packed qla_set_mac_rcv_mode_t; 598 599/* 600 * Configure IP Address 601 */ 602typedef struct _qla_config_ipv4 { 603 qla_fw_cds_hdr_t hdr; 604 605 uint64_t cmd; 606#define Q8_CONFIG_CMD_IP_ENABLE 0x02 607#define Q8_CONFIG_CMD_IP_DISABLE 0x03 608 609 uint64_t ipv4_addr; 610} __packed qla_config_ipv4_t; 611 612/* 613 * Configure LRO 614 */ 615typedef struct _qla_config_lro { 616 qla_fw_cds_hdr_t hdr; 617 618 uint64_t cmd; 619#define Q8_CONFIG_LRO_ENABLE 0x08 620} __packed qla_config_lro_t; 621 622 623/* 624 * Control Messages Received on SDS Ring 625 */ 626/* Header */ 627typedef struct _qla_cntrl_msg_hdr { 628 uint16_t rsrvd0; 629 uint16_t err_code; 630 uint8_t rsp_type; 631 uint8_t comp_id; 632 uint16_t tag; 633#define Q8_CTRL_MSG_TAG_DESC_COUNT_MASK (0x7 << 5) 634#define Q8_CTRL_MSG_TAG_OWNER_MASK (0x3 << 8) 635#define Q8_CTRL_MSG_TAG_OPCODE_MASK (0x3F << 10) 636} __packed qla_cntrl_msg_hdr_t; 637 638/* 639 * definitions for rsp_type in qla_cntrl_msg_hdr_t 640 */ 641#define Q8_CTRL_CONFIG_MAC_RSP 0x85 642#define Q8_CTRL_LRO_FLOW_DELETE_RSP 0x86 643#define Q8_CTRL_LRO_FLOW_ADD_FAILURE_RSP 0x87 644#define Q8_CTRL_GET_SNMP_STATS_RSP 0x88 645#define Q8_CTRL_GET_NETWORK_STATS_RSP 0x8C 646#define Q8_CTRL_LINK_EVENT_NOTIFICATION 0x8D 647 648/* 649 * Configure MAC Response 650 */ 651typedef struct _qla_config_mac_rsp { 652 uint32_t rval; 653 uint32_t rsrvd; 654} __packed qla_config_mac_rsp_t; 655 656/* 657 * LRO Flow Response (can be LRO Flow Delete and LRO Flow Add Failure) 658 */ 659typedef struct _qla_lro_flow_rsp { 660 uint32_t handle; 661 uint32_t rss_hash; 662 uint32_t dst_ip; 663 uint32_t src_ip; 664 uint16_t dst_tcp_port; 665 uint16_t src_tcp_port; 666 uint8_t ipv6; 667 uint8_t rsrvd0; 668 uint16_t rsrvd1; 669} __packed qla_lro_flow_rsp_t; 670 671/* 672 * Get SNMP Statistics Response 673 */ 674typedef struct _qla_get_snmp_stats_rsp { 675 uint64_t rsrvd; 676} __packed qla_get_snmp_stats_rsp_t; 677 678/* 679 * Get Network Statistics Response 680 */ 681typedef struct _qla_get_net_stats_rsp { 682 uint64_t rsrvd; 683} __packed qla_get_net_stats_rsp_t; 684 685/* 686 * Link Event Notification 687 */ 688typedef struct _qla_link_event { 689 uint32_t cable_oui; 690 uint16_t cable_length; 691 692 uint16_t link_speed; 693#define Q8_LE_SPEED_MASK 0xFFF 694#define Q8_LE_SPEED_10GBPS 0x710 695#define Q8_LE_SPEED_1GBPS 0x3E8 696#define Q8_LE_SPEED_100MBPS 0x064 697#define Q8_LE_SPEED_10MBPS 0x00A 698 699 uint8_t link_up;/* 0 = down; else up */ 700 701 uint8_t mod_info; 702#define Q8_LE_MI_MODULE_NOT_PRESENT 0x01 703#define Q8_LE_MI_UNKNOWN_OPTICAL_MODULE 0x02 704#define Q8_LE_MI_SR_LR_OPTICAL_MODULE 0x03 705#define Q8_LE_MI_LRM_OPTICAL_MODULE 0x04 706#define Q8_LE_MI_SFP_1G_MODULE 0x05 707#define Q8_LE_MI_UNSUPPORTED_TWINAX 0x06 708#define Q8_LE_MI_UNSUPPORTED_TWINAX_LENGTH 0x07 709#define Q8_LE_MI_SUPPORTED_TWINAX 0x08 710 711 uint8_t fduplex; /* 1 = full duplex; 0 = half duplex */ 712 uint8_t autoneg; /* 1 = autoneg enable; 0 = disabled */ 713 uint32_t rsrvd; 714} __packed qla_link_event_t; 715 716typedef struct _qla_sds { 717 q80_stat_desc_t *sds_ring_base; /* start of sds ring */ 718 uint32_t sdsr_next; /* next entry in SDS ring to process */ 719 struct lro_ctrl lro; 720 void *rxb_free; 721 uint32_t rx_free; 722 void *rxjb_free; 723 uint32_t rxj_free; 724 volatile uint32_t rcv_active; 725} qla_sds_t; 726 727/* 728 * struct for storing hardware specific information for a given interface 729 */ 730typedef struct _qla_hw { 731 struct { 732 uint32_t 733 lro :1, 734 init_tx_cnxt :1, 735 init_rx_cnxt :1, 736 fduplex :1, 737 autoneg :1, 738 link_up :1; 739 } flags; 740 741 uint16_t link_speed; 742 uint16_t cable_length; 743 uint16_t cable_oui; 744 uint8_t mod_info; 745 uint8_t rsrvd; 746 747 uint32_t max_rds_per_cntxt; 748 uint32_t max_sds_per_cntxt; 749 uint32_t max_rules_per_cntxt; 750 uint32_t max_rcv_cntxts; 751 uint32_t max_xmt_cntxts; 752 uint32_t max_mtu; 753 uint32_t max_lro; 754 755 uint8_t mac_addr[ETHER_ADDR_LEN]; 756 757 uint16_t num_rds_rings; 758 uint16_t num_sds_rings; 759 760 qla_dmabuf_t dma_buf; 761 762 /* Transmit Side */ 763 764 q80_tx_cmd_t *tx_ring_base; 765 766 q80_tx_cntxt_req_t *tx_cntxt_req; /* TX Context Request */ 767 bus_addr_t tx_cntxt_req_paddr; 768 769 q80_tx_cntxt_rsp_t *tx_cntxt_rsp; /* TX Context Response */ 770 bus_addr_t tx_cntxt_rsp_paddr; 771 772 uint32_t *tx_cons; /* tx consumer shadow reg */ 773 bus_addr_t tx_cons_paddr; 774 775 volatile uint32_t txr_free; /* # of free entries in tx ring */ 776 volatile uint32_t txr_next; /* # next available tx ring entry */ 777 volatile uint32_t txr_comp; /* index of last tx entry completed */ 778 779 uint32_t tx_prod_reg; 780 781 /* Receive Side */ 782 volatile uint32_t rx_next; /* next standard rcv ring to arm fw */ 783 volatile int32_t rxj_next; /* next jumbo rcv ring to arm fw */ 784 785 volatile int32_t rx_in; /* next standard rcv ring to add mbufs */ 786 volatile int32_t rxj_in; /* next jumbo rcv ring to add mbufs */ 787 788 q80_rcv_cntxt_req_t *rx_cntxt_req; /* Rcv Context Request */ 789 bus_addr_t rx_cntxt_req_paddr; 790 q80_rcv_cntxt_rsp_t *rx_cntxt_rsp; /* Rcv Context Response */ 791 bus_addr_t rx_cntxt_rsp_paddr; 792 793 qla_sds_t sds[MAX_SDS_RINGS]; 794} qla_hw_t; 795 796#define QL_UPDATE_RDS_PRODUCER_INDEX(ha, i, val) \ 797 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->rds_rsp[i].producer_reg +\ 798 0x1b2000), val) 799 800#define QL_UPDATE_TX_PRODUCER_INDEX(ha, val) \ 801 WRITE_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000), val) 802 803#define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \ 804 WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->sds_rsp[i].consumer_reg +\ 805 0x1b2000), val) 806 807#define QL_CLEAR_INTERRUPTS(ha) \ 808 if (ha->pci_func == 0) {\ 809 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F0, 0xFFFFFFFF);\ 810 } else {\ 811 WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F1, 0xFFFFFFFF);\ 812 }\ 813 814#define QL_ENABLE_INTERRUPTS(ha, sds_index) \ 815 {\ 816 q80_rsp_sds_ring_t *rsp_sds;\ 817 rsp_sds = &((ha->hw.rx_cntxt_rsp)->sds_rsp[sds_index]);\ 818 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x1);\ 819 } 820 821#define QL_DISABLE_INTERRUPTS(ha, sds_index) \ 822 {\ 823 q80_rsp_sds_ring_t *rsp_sds;\ 824 rsp_sds = &((ha->hw.rx_cntxt_rsp)->sds_rsp[sds_index]);\ 825 WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x0);\ 826 } 827 828 829#define QL_BUFFER_ALIGN 16 830 831#endif /* #ifndef _QLA_HW_H_ */ 832