xgehal-ring.h revision 171095
1/*- 2 * Copyright (c) 2002-2007 Neterion, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nxge/include/xgehal-ring.h 171095 2007-06-29 22:47:18Z sam $ 27 */ 28 29/* 30 * FileName : xgehal-ring.h 31 * 32 * Description: HAL Rx ring object functionality 33 * 34 * Created: 19 May 2004 35 */ 36 37#ifndef XGE_HAL_RING_H 38#define XGE_HAL_RING_H 39 40#include <dev/nxge/include/xgehal-channel.h> 41#include <dev/nxge/include/xgehal-config.h> 42#include <dev/nxge/include/xgehal-mm.h> 43 44__EXTERN_BEGIN_DECLS 45 46/* HW ring configuration */ 47#define XGE_HAL_RING_RXDBLOCK_SIZE 0x1000 48 49#define XGE_HAL_RXD_T_CODE_OK 0x0 50#define XGE_HAL_RXD_T_CODE_PARITY 0x1 51#define XGE_HAL_RXD_T_CODE_ABORT 0x2 52#define XGE_HAL_RXD_T_CODE_PARITY_ABORT 0x3 53#define XGE_HAL_RXD_T_CODE_RDA_FAILURE 0x4 54#define XGE_HAL_RXD_T_CODE_UNKNOWN_PROTO 0x5 55#define XGE_HAL_RXD_T_CODE_BAD_FCS 0x6 56#define XGE_HAL_RXD_T_CODE_BUFF_SIZE 0x7 57#define XGE_HAL_RXD_T_CODE_BAD_ECC 0x8 58#define XGE_HAL_RXD_T_CODE_UNUSED_C 0xC 59#define XGE_HAL_RXD_T_CODE_UNKNOWN 0xF 60 61#define XGE_HAL_RING_USE_MTU -1 62 63/* control_1 and control_2 formatting - same for all buffer modes */ 64#define XGE_HAL_RXD_GET_L3_CKSUM(control_1) ((u16)(control_1>>16) & 0xFFFF) 65#define XGE_HAL_RXD_GET_L4_CKSUM(control_1) ((u16)(control_1 & 0xFFFF)) 66 67#define XGE_HAL_RXD_MASK_VLAN_TAG vBIT(0xFFFF,48,16) 68#define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val 69#define XGE_HAL_RXD_GET_VLAN_TAG(control_2) ((u16)(control_2 & 0xFFFF)) 70 71#define XGE_HAL_RXD_POSTED_4_XFRAME BIT(7) /* control_1 */ 72#define XGE_HAL_RXD_NOT_COMPLETED BIT(0) /* control_2 */ 73#define XGE_HAL_RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 74#define XGE_HAL_RXD_GET_T_CODE(control_1) \ 75 ((control_1 & XGE_HAL_RXD_T_CODE)>>48) 76#define XGE_HAL_RXD_SET_T_CODE(control_1, val) \ 77 (control_1 |= (((u64)val & 0xF) << 48)) 78 79#define XGE_HAL_RXD_MASK_FRAME_TYPE vBIT(0x3,25,2) 80#define XGE_HAL_RXD_MASK_FRAME_PROTO vBIT(0xFFFF,24,8) 81#define XGE_HAL_RXD_GET_FRAME_TYPE(control_1) \ 82 (u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37)) 83#define XGE_HAL_RXD_GET_FRAME_PROTO(control_1) \ 84 (u8)((control_1 & XGE_HAL_RXD_MASK_FRAME_PROTO) >> 32) 85#define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED BIT(24) 86#define XGE_HAL_RXD_FRAME_PROTO_IPV4 BIT(27) 87#define XGE_HAL_RXD_FRAME_PROTO_IPV6 BIT(28) 88#define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED BIT(29) 89#define XGE_HAL_RXD_FRAME_PROTO_TCP BIT(30) 90#define XGE_HAL_RXD_FRAME_PROTO_UDP BIT(31) 91#define XGE_HAL_RXD_FRAME_TCP_OR_UDP (XGE_HAL_RXD_FRAME_PROTO_TCP | \ 92 XGE_HAL_RXD_FRAME_PROTO_UDP) 93 94/** 95 * enum xge_hal_frame_type_e - Ethernet frame format. 96 * @XGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format. 97 * @XGE_HAL_FRAME_TYPE_LLC: LLC format. 98 * @XGE_HAL_FRAME_TYPE_SNAP: SNAP format. 99 * @XGE_HAL_FRAME_TYPE_IPX: IPX format. 100 * 101 * Ethernet frame format. 102 */ 103typedef enum xge_hal_frame_type_e { 104 XGE_HAL_FRAME_TYPE_DIX = 0x0, 105 XGE_HAL_FRAME_TYPE_LLC = 0x1, 106 XGE_HAL_FRAME_TYPE_SNAP = 0x2, 107 XGE_HAL_FRAME_TYPE_IPX = 0x3, 108} xge_hal_frame_type_e; 109 110/** 111 * enum xge_hal_frame_proto_e - Higher-layer ethernet protocols. 112 * @XGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN. 113 * @XGE_HAL_FRAME_PROTO_IPV4: IPv4. 114 * @XGE_HAL_FRAME_PROTO_IPV6: IPv6. 115 * @XGE_HAL_FRAME_PROTO_IP_FRAGMENTED: IP fragmented. 116 * @XGE_HAL_FRAME_PROTO_TCP: TCP. 117 * @XGE_HAL_FRAME_PROTO_UDP: UDP. 118 * @XGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP. 119 * 120 * Higher layer ethernet protocols and options. 121 */ 122typedef enum xge_hal_frame_proto_e { 123 XGE_HAL_FRAME_PROTO_VLAN_TAGGED = 0x80, 124 XGE_HAL_FRAME_PROTO_IPV4 = 0x10, 125 XGE_HAL_FRAME_PROTO_IPV6 = 0x08, 126 XGE_HAL_FRAME_PROTO_IP_FRAGMENTED = 0x04, 127 XGE_HAL_FRAME_PROTO_TCP = 0x02, 128 XGE_HAL_FRAME_PROTO_UDP = 0x01, 129 XGE_HAL_FRAME_PROTO_TCP_OR_UDP = (XGE_HAL_FRAME_PROTO_TCP | \ 130 XGE_HAL_FRAME_PROTO_UDP) 131} xge_hal_frame_proto_e; 132 133/* 134 * xge_hal_ring_rxd_1_t 135 */ 136typedef struct { 137 u64 host_control; 138 u64 control_1; 139 u64 control_2; 140#define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) 141#define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val) vBIT(val,0,16) 142#define XGE_HAL_RXD_1_GET_BUFFER0_SIZE(Control_2) \ 143 (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) 144#define XGE_HAL_RXD_1_GET_RTH_VALUE(Control_2) \ 145 (u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16) 146 u64 buffer0_ptr; 147} xge_hal_ring_rxd_1_t; 148 149/* 150 * xge_hal_ring_rxd_3_t 151 */ 152typedef struct { 153 u64 host_control; 154 u64 control_1; 155 156 u64 control_2; 157#define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE vBIT(0xFF,8,8) 158#define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val) vBIT(val,8,8) 159#define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) 160#define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val) vBIT(val,16,16) 161#define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) 162#define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val) vBIT(val,32,16) 163 164 165#define XGE_HAL_RXD_3_GET_BUFFER0_SIZE(Control_2) \ 166 (int)((Control_2 & vBIT(0xFF,8,8))>>48) 167#define XGE_HAL_RXD_3_GET_BUFFER1_SIZE(Control_2) \ 168 (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) 169#define XGE_HAL_RXD_3_GET_BUFFER2_SIZE(Control_2) \ 170 (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) 171 172 u64 buffer0_ptr; 173 u64 buffer1_ptr; 174 u64 buffer2_ptr; 175} xge_hal_ring_rxd_3_t; 176 177/* 178 * xge_hal_ring_rxd_5_t 179 */ 180typedef struct { 181#ifdef XGE_OS_HOST_BIG_ENDIAN 182 u32 host_control; 183 u32 control_3; 184#else 185 u32 control_3; 186 u32 host_control; 187#endif 188 189 190#define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE vBIT(0xFFFF,32,16) 191#define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val) vBIT(val,32,16) 192#define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE vBIT(0xFFFF,48,16) 193#define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val) vBIT(val,48,16) 194 195#define XGE_HAL_RXD_5_GET_BUFFER3_SIZE(Control_3) \ 196 (int)((Control_3 & vBIT(0xFFFF,32,16))>>16) 197#define XGE_HAL_RXD_5_GET_BUFFER4_SIZE(Control_3) \ 198 (int)((Control_3 & vBIT(0xFFFF,48,16))) 199 200 u64 control_1; 201 u64 control_2; 202 203#define XGE_HAL_RXD_5_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) 204#define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val) vBIT(val,0,16) 205#define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) 206#define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val) vBIT(val,16,16) 207#define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) 208#define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val) vBIT(val,32,16) 209 210 211#define XGE_HAL_RXD_5_GET_BUFFER0_SIZE(Control_2) \ 212 (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) 213#define XGE_HAL_RXD_5_GET_BUFFER1_SIZE(Control_2) \ 214 (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) 215#define XGE_HAL_RXD_5_GET_BUFFER2_SIZE(Control_2) \ 216 (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) 217 u64 buffer0_ptr; 218 u64 buffer1_ptr; 219 u64 buffer2_ptr; 220 u64 buffer3_ptr; 221 u64 buffer4_ptr; 222} xge_hal_ring_rxd_5_t; 223 224#define XGE_HAL_RXD_GET_RTH_SPDM_HIT(Control_1) \ 225 (u8)((Control_1 & BIT(18))>>45) 226#define XGE_HAL_RXD_GET_RTH_IT_HIT(Control_1) \ 227 (u8)((Control_1 & BIT(19))>>44) 228#define XGE_HAL_RXD_GET_RTH_HASH_TYPE(Control_1) \ 229 (u8)((Control_1 & vBIT(0xF,20,4))>>40) 230 231#define XGE_HAL_RXD_HASH_TYPE_NONE 0x0 232#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV4 0x1 233#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV4 0x2 234#define XGE_HAL_RXD_HASH_TYPE_IPV4 0x3 235#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6 0x4 236#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6 0x5 237#define XGE_HAL_RXD_HASH_TYPE_IPV6 0x6 238#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6_EX 0x7 239#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6_EX 0x8 240#define XGE_HAL_RXD_HASH_TYPE_IPV6_EX 0x9 241 242typedef u8 xge_hal_ring_block_t[XGE_HAL_RING_RXDBLOCK_SIZE]; 243 244#define XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET 0xFF8 245#define XGE_HAL_RING_MEMBLOCK_IDX_OFFSET 0xFF0 246 247#define XGE_HAL_RING_RXD_SIZEOF(n) \ 248 (n==1 ? sizeof(xge_hal_ring_rxd_1_t) : \ 249 (n==3 ? sizeof(xge_hal_ring_rxd_3_t) : \ 250 sizeof(xge_hal_ring_rxd_5_t))) 251 252#define XGE_HAL_RING_RXDS_PER_BLOCK(n) \ 253 (n==1 ? 127 : (n==3 ? 85 : 63)) 254 255/** 256 * struct xge_hal_ring_rxd_priv_t - Receive descriptor HAL-private data. 257 * @dma_addr: DMA (mapped) address of _this_ descriptor. 258 * @dma_handle: DMA handle used to map the descriptor onto device. 259 * @dma_offset: Descriptor's offset in the memory block. HAL allocates 260 * descriptors in memory blocks of 261 * %XGE_HAL_RING_RXDBLOCK_SIZE 262 * bytes. Each memblock is contiguous DMA-able memory. Each 263 * memblock contains 1 or more 4KB RxD blocks visible to the 264 * Xframe hardware. 265 * @dma_object: DMA address and handle of the memory block that contains 266 * the descriptor. This member is used only in the "checked" 267 * version of the HAL (to enforce certain assertions); 268 * otherwise it gets compiled out. 269 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. 270 * 271 * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA 272 * information associated with the descriptor. Note that ULD can ask HAL 273 * to allocate additional per-descriptor space for its own (ULD-specific) 274 * purposes. 275 */ 276typedef struct xge_hal_ring_rxd_priv_t { 277 dma_addr_t dma_addr; 278 pci_dma_h dma_handle; 279 ptrdiff_t dma_offset; 280#ifdef XGE_DEBUG_ASSERT 281 xge_hal_mempool_dma_t *dma_object; 282#endif 283#ifdef XGE_OS_MEMORY_CHECK 284 int allocated; 285#endif 286} xge_hal_ring_rxd_priv_t; 287 288/** 289 * struct xge_hal_ring_t - Ring channel. 290 * @channel: Channel "base" of this ring, the common part of all HAL 291 * channels. 292 * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode, 293 * as per Xframe User Guide. 294 * @indicate_max_pkts: Maximum number of packets processed within a single 295 * interrupt. Can be used to limit the time spent inside hw 296 * interrupt. 297 * @config: Ring configuration, part of device configuration 298 * (see xge_hal_device_config_t{}). 299 * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Xframe spec, 300 * 1-buffer mode descriptor is 32 byte long, etc. 301 * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor 302 * data (e.g., DMA handle for Solaris) 303 * @rxds_per_block: Number of descriptors per hardware-defined RxD 304 * block. Depends on the (1-,3-,5-) buffer mode. 305 * @mempool: Memory pool, the pool from which descriptors get allocated. 306 * (See xge_hal_mm.h). 307 * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal 308 * usage. Not to confuse with @rxd_priv_size. 309 * @reserved_rxds_arr: Array of RxD pointers. At any point in time each 310 * entry in this array is available for allocation 311 * (via xge_hal_ring_dtr_reserve()) and posting. 312 * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR. 313 * Used in conjunction with @indicate_max_pkts. 314 * Ring channel. 315 * 316 * Note: The structure is cache line aligned to better utilize 317 * CPU cache performance. 318 */ 319typedef struct xge_hal_ring_t { 320 xge_hal_channel_t channel; 321 int buffer_mode; 322 int indicate_max_pkts; 323 xge_hal_ring_config_t *config; 324 int rxd_size; 325 int rxd_priv_size; 326 int rxds_per_block; 327 xge_hal_mempool_t *mempool; 328 int rxdblock_priv_size; 329 void **reserved_rxds_arr; 330 int cmpl_cnt; 331} __xge_os_attr_cacheline_aligned xge_hal_ring_t; 332 333/** 334 * struct xge_hal_dtr_info_t - Extended information associated with a 335 * completed ring descriptor. 336 * @l3_cksum: Result of IP checksum check (by Xframe hardware). 337 * This field containing XGE_HAL_L3_CKSUM_OK would mean that 338 * the checksum is correct, otherwise - the datagram is 339 * corrupted. 340 * @l4_cksum: Result of TCP/UDP checksum check (by Xframe hardware). 341 * This field containing XGE_HAL_L4_CKSUM_OK would mean that 342 * the checksum is correct. Otherwise - the packet is 343 * corrupted. 344 * @frame: See xge_hal_frame_type_e{}. 345 * @proto: Reporting bits for various higher-layer protocols, including (but 346 * note restricted to) TCP and UDP. See xge_hal_frame_proto_e{}. 347 * @vlan: VLAN tag extracted from the received frame. 348 * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Xframe II 349 * hardware if RTH is enabled. 350 * @rth_it_hit: Set, If RTH hash value calculated by the Xframe II hardware 351 * has a matching entry in the Indirection table. 352 * @rth_spdm_hit: Set, If RTH hash value calculated by the Xframe II hardware 353 * has a matching entry in the Socket Pair Direct Match table. 354 * @rth_hash_type: RTH hash code of the function used to calculate the hash. 355 * @reserved_pad: Unused byte. 356 */ 357typedef struct xge_hal_dtr_info_t { 358 int l3_cksum; 359 int l4_cksum; 360 int frame; /* zero or more of xge_hal_frame_type_e flags */ 361 int proto; /* zero or more of xge_hal_frame_proto_e flags */ 362 int vlan; 363 u32 rth_value; 364 u8 rth_it_hit; 365 u8 rth_spdm_hit; 366 u8 rth_hash_type; 367 u8 reserved_pad; 368} xge_hal_dtr_info_t; 369 370/* ========================== RING PRIVATE API ============================ */ 371 372xge_hal_status_e __hal_ring_open(xge_hal_channel_h channelh, 373 xge_hal_channel_attr_t *attr); 374 375void __hal_ring_close(xge_hal_channel_h channelh); 376 377void __hal_ring_hw_initialize(xge_hal_device_h devh); 378 379void __hal_ring_mtu_set(xge_hal_device_h devh, int new_mtu); 380 381void __hal_ring_prc_enable(xge_hal_channel_h channelh); 382 383void __hal_ring_prc_disable(xge_hal_channel_h channelh); 384 385xge_hal_status_e __hal_ring_initial_replenish(xge_hal_channel_t *channel, 386 xge_hal_channel_reopen_e reopen); 387 388#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_RING) 389#define __HAL_STATIC_RING 390#define __HAL_INLINE_RING 391 392__HAL_STATIC_RING __HAL_INLINE_RING int 393__hal_ring_block_memblock_idx(xge_hal_ring_block_t *block); 394 395__HAL_STATIC_RING __HAL_INLINE_RING void 396__hal_ring_block_memblock_idx_set(xge_hal_ring_block_t*block, int memblock_idx); 397 398__HAL_STATIC_RING __HAL_INLINE_RING dma_addr_t 399__hal_ring_block_next_pointer(xge_hal_ring_block_t *block); 400 401__HAL_STATIC_RING __HAL_INLINE_RING void 402__hal_ring_block_next_pointer_set(xge_hal_ring_block_t*block, 403 dma_addr_t dma_next); 404 405__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_ring_rxd_priv_t* 406__hal_ring_rxd_priv(xge_hal_ring_t *ring, xge_hal_dtr_h dtrh); 407 408/* =========================== RING PUBLIC API ============================ */ 409 410__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 411xge_hal_ring_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh); 412 413__HAL_STATIC_RING __HAL_INLINE_RING void* 414xge_hal_ring_dtr_private(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 415 416__HAL_STATIC_RING __HAL_INLINE_RING void 417xge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int size); 418 419__HAL_STATIC_RING __HAL_INLINE_RING void 420xge_hal_ring_dtr_info_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 421 xge_hal_dtr_info_t *ext_info); 422 423__HAL_STATIC_RING __HAL_INLINE_RING void 424xge_hal_ring_dtr_1b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 425 dma_addr_t *dma_pointer, int *pkt_length); 426 427__HAL_STATIC_RING __HAL_INLINE_RING void 428xge_hal_ring_dtr_3b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], 429 int sizes[]); 430 431__HAL_STATIC_RING __HAL_INLINE_RING void 432xge_hal_ring_dtr_3b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 433 dma_addr_t dma_pointers[], int sizes[]); 434 435__HAL_STATIC_RING __HAL_INLINE_RING void 436xge_hal_ring_dtr_5b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], 437 int sizes[]); 438 439__HAL_STATIC_RING __HAL_INLINE_RING void 440xge_hal_ring_dtr_5b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 441 dma_addr_t dma_pointer[], int sizes[]); 442 443__HAL_STATIC_RING __HAL_INLINE_RING void 444xge_hal_ring_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 445 446__HAL_STATIC_RING __HAL_INLINE_RING void 447xge_hal_ring_dtr_pre_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 448 449__HAL_STATIC_RING __HAL_INLINE_RING void 450xge_hal_ring_dtr_post_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 451 452__HAL_STATIC_RING __HAL_INLINE_RING void 453xge_hal_ring_dtr_post_post_wmb(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 454 455__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 456xge_hal_ring_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, 457 u8 *t_code); 458 459__HAL_STATIC_RING __HAL_INLINE_RING void 460xge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 461 462__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 463xge_hal_ring_is_next_dtr_completed(xge_hal_channel_h channelh); 464 465#else /* XGE_FASTPATH_EXTERN */ 466#define __HAL_STATIC_RING static 467#define __HAL_INLINE_RING inline 468#include <dev/nxge/xgehal/xgehal-ring-fp.c> 469#endif /* XGE_FASTPATH_INLINE */ 470 471__EXTERN_END_DECLS 472 473#endif /* XGE_HAL_RING_H */ 474