1171095Ssam/*- 2171095Ssam * Copyright (c) 2002-2007 Neterion, Inc. 3171095Ssam * All rights reserved. 4171095Ssam * 5171095Ssam * Redistribution and use in source and binary forms, with or without 6171095Ssam * modification, are permitted provided that the following conditions 7171095Ssam * are met: 8171095Ssam * 1. Redistributions of source code must retain the above copyright 9171095Ssam * notice, this list of conditions and the following disclaimer. 10171095Ssam * 2. Redistributions in binary form must reproduce the above copyright 11171095Ssam * notice, this list of conditions and the following disclaimer in the 12171095Ssam * documentation and/or other materials provided with the distribution. 13171095Ssam * 14171095Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15171095Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16171095Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17171095Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18171095Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19171095Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20171095Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21171095Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22171095Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23171095Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24171095Ssam * SUCH DAMAGE. 25171095Ssam * 26171095Ssam * $FreeBSD$ 27171095Ssam */ 28171095Ssam 29171095Ssam#ifndef XGE_HAL_RING_H 30171095Ssam#define XGE_HAL_RING_H 31171095Ssam 32171095Ssam#include <dev/nxge/include/xgehal-channel.h> 33171095Ssam#include <dev/nxge/include/xgehal-config.h> 34171095Ssam#include <dev/nxge/include/xgehal-mm.h> 35171095Ssam 36171095Ssam__EXTERN_BEGIN_DECLS 37171095Ssam 38171095Ssam/* HW ring configuration */ 39173139Srwatson#define XGE_HAL_RING_RXDBLOCK_SIZE 0x1000 40171095Ssam 41173139Srwatson#define XGE_HAL_RXD_T_CODE_OK 0x0 42173139Srwatson#define XGE_HAL_RXD_T_CODE_PARITY 0x1 43173139Srwatson#define XGE_HAL_RXD_T_CODE_ABORT 0x2 44173139Srwatson#define XGE_HAL_RXD_T_CODE_PARITY_ABORT 0x3 45173139Srwatson#define XGE_HAL_RXD_T_CODE_RDA_FAILURE 0x4 46171095Ssam#define XGE_HAL_RXD_T_CODE_UNKNOWN_PROTO 0x5 47173139Srwatson#define XGE_HAL_RXD_T_CODE_BAD_FCS 0x6 48173139Srwatson#define XGE_HAL_RXD_T_CODE_BUFF_SIZE 0x7 49173139Srwatson#define XGE_HAL_RXD_T_CODE_BAD_ECC 0x8 50173139Srwatson#define XGE_HAL_RXD_T_CODE_UNUSED_C 0xC 51173139Srwatson#define XGE_HAL_RXD_T_CODE_UNKNOWN 0xF 52171095Ssam 53173139Srwatson#define XGE_HAL_RING_USE_MTU -1 54171095Ssam 55171095Ssam/* control_1 and control_2 formatting - same for all buffer modes */ 56171095Ssam#define XGE_HAL_RXD_GET_L3_CKSUM(control_1) ((u16)(control_1>>16) & 0xFFFF) 57171095Ssam#define XGE_HAL_RXD_GET_L4_CKSUM(control_1) ((u16)(control_1 & 0xFFFF)) 58171095Ssam 59173139Srwatson#define XGE_HAL_RXD_MASK_VLAN_TAG vBIT(0xFFFF,48,16) 60171095Ssam#define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val 61173139Srwatson#define XGE_HAL_RXD_GET_VLAN_TAG(control_2) ((u16)(control_2 & 0xFFFF)) 62171095Ssam 63173139Srwatson#define XGE_HAL_RXD_POSTED_4_XFRAME BIT(7) /* control_1 */ 64171095Ssam#define XGE_HAL_RXD_NOT_COMPLETED BIT(0) /* control_2 */ 65173139Srwatson#define XGE_HAL_RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 66173139Srwatson#define XGE_HAL_RXD_GET_T_CODE(control_1) \ 67173139Srwatson ((control_1 & XGE_HAL_RXD_T_CODE)>>48) 68171095Ssam#define XGE_HAL_RXD_SET_T_CODE(control_1, val) \ 69173139Srwatson (control_1 |= (((u64)val & 0xF) << 48)) 70171095Ssam 71173139Srwatson#define XGE_HAL_RXD_MASK_FRAME_TYPE vBIT(0x3,25,2) 72173139Srwatson#define XGE_HAL_RXD_MASK_FRAME_PROTO vBIT(0xFFFF,24,8) 73173139Srwatson#define XGE_HAL_RXD_GET_FRAME_TYPE(control_1) \ 74173139Srwatson (u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37)) 75173139Srwatson#define XGE_HAL_RXD_GET_FRAME_PROTO(control_1) \ 76173139Srwatson (u8)((control_1 & XGE_HAL_RXD_MASK_FRAME_PROTO) >> 32) 77173139Srwatson#define XGE_HAL_RXD_FRAME_PROTO_VLAN_TAGGED BIT(24) 78173139Srwatson#define XGE_HAL_RXD_FRAME_PROTO_IPV4 BIT(27) 79173139Srwatson#define XGE_HAL_RXD_FRAME_PROTO_IPV6 BIT(28) 80173139Srwatson#define XGE_HAL_RXD_FRAME_PROTO_IP_FRAGMENTED BIT(29) 81173139Srwatson#define XGE_HAL_RXD_FRAME_PROTO_TCP BIT(30) 82173139Srwatson#define XGE_HAL_RXD_FRAME_PROTO_UDP BIT(31) 83171095Ssam#define XGE_HAL_RXD_FRAME_TCP_OR_UDP (XGE_HAL_RXD_FRAME_PROTO_TCP | \ 84173139Srwatson XGE_HAL_RXD_FRAME_PROTO_UDP) 85171095Ssam 86171095Ssam/** 87171095Ssam * enum xge_hal_frame_type_e - Ethernet frame format. 88171095Ssam * @XGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format. 89171095Ssam * @XGE_HAL_FRAME_TYPE_LLC: LLC format. 90171095Ssam * @XGE_HAL_FRAME_TYPE_SNAP: SNAP format. 91171095Ssam * @XGE_HAL_FRAME_TYPE_IPX: IPX format. 92171095Ssam * 93171095Ssam * Ethernet frame format. 94171095Ssam */ 95171095Ssamtypedef enum xge_hal_frame_type_e { 96173139Srwatson XGE_HAL_FRAME_TYPE_DIX = 0x0, 97173139Srwatson XGE_HAL_FRAME_TYPE_LLC = 0x1, 98173139Srwatson XGE_HAL_FRAME_TYPE_SNAP = 0x2, 99173139Srwatson XGE_HAL_FRAME_TYPE_IPX = 0x3, 100171095Ssam} xge_hal_frame_type_e; 101171095Ssam 102171095Ssam/** 103171095Ssam * enum xge_hal_frame_proto_e - Higher-layer ethernet protocols. 104171095Ssam * @XGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN. 105171095Ssam * @XGE_HAL_FRAME_PROTO_IPV4: IPv4. 106171095Ssam * @XGE_HAL_FRAME_PROTO_IPV6: IPv6. 107171095Ssam * @XGE_HAL_FRAME_PROTO_IP_FRAGMENTED: IP fragmented. 108171095Ssam * @XGE_HAL_FRAME_PROTO_TCP: TCP. 109171095Ssam * @XGE_HAL_FRAME_PROTO_UDP: UDP. 110171095Ssam * @XGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP. 111171095Ssam * 112171095Ssam * Higher layer ethernet protocols and options. 113171095Ssam */ 114171095Ssamtypedef enum xge_hal_frame_proto_e { 115173139Srwatson XGE_HAL_FRAME_PROTO_VLAN_TAGGED = 0x80, 116173139Srwatson XGE_HAL_FRAME_PROTO_IPV4 = 0x10, 117173139Srwatson XGE_HAL_FRAME_PROTO_IPV6 = 0x08, 118173139Srwatson XGE_HAL_FRAME_PROTO_IP_FRAGMENTED = 0x04, 119173139Srwatson XGE_HAL_FRAME_PROTO_TCP = 0x02, 120173139Srwatson XGE_HAL_FRAME_PROTO_UDP = 0x01, 121173139Srwatson XGE_HAL_FRAME_PROTO_TCP_OR_UDP = (XGE_HAL_FRAME_PROTO_TCP | \ 122173139Srwatson XGE_HAL_FRAME_PROTO_UDP) 123171095Ssam} xge_hal_frame_proto_e; 124171095Ssam 125171095Ssam/* 126171095Ssam * xge_hal_ring_rxd_1_t 127171095Ssam */ 128171095Ssamtypedef struct { 129171095Ssam u64 host_control; 130171095Ssam u64 control_1; 131171095Ssam u64 control_2; 132173139Srwatson#define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) 133173139Srwatson#define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val) vBIT(val,0,16) 134171095Ssam#define XGE_HAL_RXD_1_GET_BUFFER0_SIZE(Control_2) \ 135173139Srwatson (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) 136171095Ssam#define XGE_HAL_RXD_1_GET_RTH_VALUE(Control_2) \ 137173139Srwatson (u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16) 138171095Ssam u64 buffer0_ptr; 139171095Ssam} xge_hal_ring_rxd_1_t; 140171095Ssam 141171095Ssam/* 142171095Ssam * xge_hal_ring_rxd_3_t 143171095Ssam */ 144171095Ssamtypedef struct { 145171095Ssam u64 host_control; 146171095Ssam u64 control_1; 147171095Ssam 148171095Ssam u64 control_2; 149173139Srwatson#define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE vBIT(0xFF,8,8) 150173139Srwatson#define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val) vBIT(val,8,8) 151173139Srwatson#define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) 152173139Srwatson#define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val) vBIT(val,16,16) 153173139Srwatson#define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) 154173139Srwatson#define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val) vBIT(val,32,16) 155171095Ssam 156171095Ssam 157171095Ssam#define XGE_HAL_RXD_3_GET_BUFFER0_SIZE(Control_2) \ 158173139Srwatson (int)((Control_2 & vBIT(0xFF,8,8))>>48) 159171095Ssam#define XGE_HAL_RXD_3_GET_BUFFER1_SIZE(Control_2) \ 160173139Srwatson (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) 161171095Ssam#define XGE_HAL_RXD_3_GET_BUFFER2_SIZE(Control_2) \ 162173139Srwatson (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) 163171095Ssam 164171095Ssam u64 buffer0_ptr; 165171095Ssam u64 buffer1_ptr; 166171095Ssam u64 buffer2_ptr; 167171095Ssam} xge_hal_ring_rxd_3_t; 168171095Ssam 169171095Ssam/* 170171095Ssam * xge_hal_ring_rxd_5_t 171171095Ssam */ 172171095Ssamtypedef struct { 173171095Ssam#ifdef XGE_OS_HOST_BIG_ENDIAN 174171095Ssam u32 host_control; 175171095Ssam u32 control_3; 176171095Ssam#else 177171095Ssam u32 control_3; 178171095Ssam u32 host_control; 179171095Ssam#endif 180171095Ssam 181171095Ssam 182173139Srwatson#define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE vBIT(0xFFFF,32,16) 183173139Srwatson#define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val) vBIT(val,32,16) 184173139Srwatson#define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE vBIT(0xFFFF,48,16) 185173139Srwatson#define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val) vBIT(val,48,16) 186171095Ssam 187171095Ssam#define XGE_HAL_RXD_5_GET_BUFFER3_SIZE(Control_3) \ 188173139Srwatson (int)((Control_3 & vBIT(0xFFFF,32,16))>>16) 189171095Ssam#define XGE_HAL_RXD_5_GET_BUFFER4_SIZE(Control_3) \ 190173139Srwatson (int)((Control_3 & vBIT(0xFFFF,48,16))) 191171095Ssam 192171095Ssam u64 control_1; 193171095Ssam u64 control_2; 194171095Ssam 195173139Srwatson#define XGE_HAL_RXD_5_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) 196173139Srwatson#define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val) vBIT(val,0,16) 197173139Srwatson#define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) 198173139Srwatson#define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val) vBIT(val,16,16) 199173139Srwatson#define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) 200173139Srwatson#define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val) vBIT(val,32,16) 201171095Ssam 202171095Ssam 203171095Ssam#define XGE_HAL_RXD_5_GET_BUFFER0_SIZE(Control_2) \ 204173139Srwatson (int)((Control_2 & vBIT(0xFFFF,0,16))>>48) 205171095Ssam#define XGE_HAL_RXD_5_GET_BUFFER1_SIZE(Control_2) \ 206173139Srwatson (int)((Control_2 & vBIT(0xFFFF,16,16))>>32) 207171095Ssam#define XGE_HAL_RXD_5_GET_BUFFER2_SIZE(Control_2) \ 208173139Srwatson (int)((Control_2 & vBIT(0xFFFF,32,16))>>16) 209171095Ssam u64 buffer0_ptr; 210171095Ssam u64 buffer1_ptr; 211171095Ssam u64 buffer2_ptr; 212171095Ssam u64 buffer3_ptr; 213171095Ssam u64 buffer4_ptr; 214171095Ssam} xge_hal_ring_rxd_5_t; 215171095Ssam 216171095Ssam#define XGE_HAL_RXD_GET_RTH_SPDM_HIT(Control_1) \ 217173139Srwatson (u8)((Control_1 & BIT(18))>>45) 218171095Ssam#define XGE_HAL_RXD_GET_RTH_IT_HIT(Control_1) \ 219173139Srwatson (u8)((Control_1 & BIT(19))>>44) 220171095Ssam#define XGE_HAL_RXD_GET_RTH_HASH_TYPE(Control_1) \ 221173139Srwatson (u8)((Control_1 & vBIT(0xF,20,4))>>40) 222171095Ssam 223173139Srwatson#define XGE_HAL_RXD_HASH_TYPE_NONE 0x0 224173139Srwatson#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV4 0x1 225173139Srwatson#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV4 0x2 226173139Srwatson#define XGE_HAL_RXD_HASH_TYPE_IPV4 0x3 227173139Srwatson#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6 0x4 228173139Srwatson#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6 0x5 229173139Srwatson#define XGE_HAL_RXD_HASH_TYPE_IPV6 0x6 230173139Srwatson#define XGE_HAL_RXD_HASH_TYPE_TCP_IPV6_EX 0x7 231173139Srwatson#define XGE_HAL_RXD_HASH_TYPE_UDP_IPV6_EX 0x8 232173139Srwatson#define XGE_HAL_RXD_HASH_TYPE_IPV6_EX 0x9 233171095Ssam 234171095Ssamtypedef u8 xge_hal_ring_block_t[XGE_HAL_RING_RXDBLOCK_SIZE]; 235171095Ssam 236173139Srwatson#define XGE_HAL_RING_NEXT_BLOCK_POINTER_OFFSET 0xFF8 237173139Srwatson#define XGE_HAL_RING_MEMBLOCK_IDX_OFFSET 0xFF0 238171095Ssam 239171095Ssam#define XGE_HAL_RING_RXD_SIZEOF(n) \ 240171095Ssam (n==1 ? sizeof(xge_hal_ring_rxd_1_t) : \ 241173139Srwatson (n==3 ? sizeof(xge_hal_ring_rxd_3_t) : \ 242173139Srwatson sizeof(xge_hal_ring_rxd_5_t))) 243171095Ssam 244171095Ssam#define XGE_HAL_RING_RXDS_PER_BLOCK(n) \ 245171095Ssam (n==1 ? 127 : (n==3 ? 85 : 63)) 246171095Ssam 247171095Ssam/** 248171095Ssam * struct xge_hal_ring_rxd_priv_t - Receive descriptor HAL-private data. 249171095Ssam * @dma_addr: DMA (mapped) address of _this_ descriptor. 250171095Ssam * @dma_handle: DMA handle used to map the descriptor onto device. 251171095Ssam * @dma_offset: Descriptor's offset in the memory block. HAL allocates 252171095Ssam * descriptors in memory blocks of 253171095Ssam * %XGE_HAL_RING_RXDBLOCK_SIZE 254171095Ssam * bytes. Each memblock is contiguous DMA-able memory. Each 255171095Ssam * memblock contains 1 or more 4KB RxD blocks visible to the 256171095Ssam * Xframe hardware. 257171095Ssam * @dma_object: DMA address and handle of the memory block that contains 258171095Ssam * the descriptor. This member is used only in the "checked" 259171095Ssam * version of the HAL (to enforce certain assertions); 260171095Ssam * otherwise it gets compiled out. 261171095Ssam * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. 262171095Ssam * 263171095Ssam * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA 264171095Ssam * information associated with the descriptor. Note that ULD can ask HAL 265171095Ssam * to allocate additional per-descriptor space for its own (ULD-specific) 266171095Ssam * purposes. 267171095Ssam */ 268171095Ssamtypedef struct xge_hal_ring_rxd_priv_t { 269173139Srwatson dma_addr_t dma_addr; 270173139Srwatson pci_dma_h dma_handle; 271173139Srwatson ptrdiff_t dma_offset; 272171095Ssam#ifdef XGE_DEBUG_ASSERT 273173139Srwatson xge_hal_mempool_dma_t *dma_object; 274171095Ssam#endif 275171095Ssam#ifdef XGE_OS_MEMORY_CHECK 276173139Srwatson int allocated; 277171095Ssam#endif 278171095Ssam} xge_hal_ring_rxd_priv_t; 279171095Ssam 280171095Ssam/** 281171095Ssam * struct xge_hal_ring_t - Ring channel. 282171095Ssam * @channel: Channel "base" of this ring, the common part of all HAL 283171095Ssam * channels. 284171095Ssam * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode, 285171095Ssam * as per Xframe User Guide. 286171095Ssam * @indicate_max_pkts: Maximum number of packets processed within a single 287171095Ssam * interrupt. Can be used to limit the time spent inside hw 288171095Ssam * interrupt. 289171095Ssam * @config: Ring configuration, part of device configuration 290171095Ssam * (see xge_hal_device_config_t{}). 291171095Ssam * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Xframe spec, 292171095Ssam * 1-buffer mode descriptor is 32 byte long, etc. 293171095Ssam * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor 294171095Ssam * data (e.g., DMA handle for Solaris) 295171095Ssam * @rxds_per_block: Number of descriptors per hardware-defined RxD 296171095Ssam * block. Depends on the (1-,3-,5-) buffer mode. 297171095Ssam * @mempool: Memory pool, the pool from which descriptors get allocated. 298171095Ssam * (See xge_hal_mm.h). 299171095Ssam * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal 300171095Ssam * usage. Not to confuse with @rxd_priv_size. 301171095Ssam * @reserved_rxds_arr: Array of RxD pointers. At any point in time each 302171095Ssam * entry in this array is available for allocation 303171095Ssam * (via xge_hal_ring_dtr_reserve()) and posting. 304171095Ssam * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR. 305171095Ssam * Used in conjunction with @indicate_max_pkts. 306171095Ssam * Ring channel. 307171095Ssam * 308171095Ssam * Note: The structure is cache line aligned to better utilize 309171095Ssam * CPU cache performance. 310171095Ssam */ 311171095Ssamtypedef struct xge_hal_ring_t { 312173139Srwatson xge_hal_channel_t channel; 313173139Srwatson int buffer_mode; 314173139Srwatson int indicate_max_pkts; 315173139Srwatson xge_hal_ring_config_t *config; 316173139Srwatson int rxd_size; 317173139Srwatson int rxd_priv_size; 318173139Srwatson int rxds_per_block; 319173139Srwatson xge_hal_mempool_t *mempool; 320173139Srwatson int rxdblock_priv_size; 321173139Srwatson void **reserved_rxds_arr; 322173139Srwatson int cmpl_cnt; 323171095Ssam} __xge_os_attr_cacheline_aligned xge_hal_ring_t; 324171095Ssam 325171095Ssam/** 326171095Ssam * struct xge_hal_dtr_info_t - Extended information associated with a 327171095Ssam * completed ring descriptor. 328171095Ssam * @l3_cksum: Result of IP checksum check (by Xframe hardware). 329171095Ssam * This field containing XGE_HAL_L3_CKSUM_OK would mean that 330171095Ssam * the checksum is correct, otherwise - the datagram is 331171095Ssam * corrupted. 332171095Ssam * @l4_cksum: Result of TCP/UDP checksum check (by Xframe hardware). 333171095Ssam * This field containing XGE_HAL_L4_CKSUM_OK would mean that 334171095Ssam * the checksum is correct. Otherwise - the packet is 335171095Ssam * corrupted. 336171095Ssam * @frame: See xge_hal_frame_type_e{}. 337171095Ssam * @proto: Reporting bits for various higher-layer protocols, including (but 338173139Srwatson * note restricted to) TCP and UDP. See xge_hal_frame_proto_e{}. 339171095Ssam * @vlan: VLAN tag extracted from the received frame. 340171095Ssam * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Xframe II 341171095Ssam * hardware if RTH is enabled. 342171095Ssam * @rth_it_hit: Set, If RTH hash value calculated by the Xframe II hardware 343171095Ssam * has a matching entry in the Indirection table. 344171095Ssam * @rth_spdm_hit: Set, If RTH hash value calculated by the Xframe II hardware 345171095Ssam * has a matching entry in the Socket Pair Direct Match table. 346171095Ssam * @rth_hash_type: RTH hash code of the function used to calculate the hash. 347171095Ssam * @reserved_pad: Unused byte. 348171095Ssam */ 349171095Ssamtypedef struct xge_hal_dtr_info_t { 350173139Srwatson int l3_cksum; 351173139Srwatson int l4_cksum; 352173139Srwatson int frame; /* zero or more of xge_hal_frame_type_e flags */ 353173139Srwatson int proto; /* zero or more of xge_hal_frame_proto_e flags */ 354173139Srwatson int vlan; 355173139Srwatson u32 rth_value; 356173139Srwatson u8 rth_it_hit; 357173139Srwatson u8 rth_spdm_hit; 358173139Srwatson u8 rth_hash_type; 359173139Srwatson u8 reserved_pad; 360171095Ssam} xge_hal_dtr_info_t; 361171095Ssam 362171095Ssam/* ========================== RING PRIVATE API ============================ */ 363171095Ssam 364171095Ssamxge_hal_status_e __hal_ring_open(xge_hal_channel_h channelh, 365173139Srwatson xge_hal_channel_attr_t *attr); 366171095Ssam 367171095Ssamvoid __hal_ring_close(xge_hal_channel_h channelh); 368171095Ssam 369171095Ssamvoid __hal_ring_hw_initialize(xge_hal_device_h devh); 370171095Ssam 371171095Ssamvoid __hal_ring_mtu_set(xge_hal_device_h devh, int new_mtu); 372171095Ssam 373171095Ssamvoid __hal_ring_prc_enable(xge_hal_channel_h channelh); 374171095Ssam 375171095Ssamvoid __hal_ring_prc_disable(xge_hal_channel_h channelh); 376171095Ssam 377171095Ssamxge_hal_status_e __hal_ring_initial_replenish(xge_hal_channel_t *channel, 378173139Srwatson xge_hal_channel_reopen_e reopen); 379171095Ssam 380171095Ssam#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_RING) 381171095Ssam#define __HAL_STATIC_RING 382171095Ssam#define __HAL_INLINE_RING 383171095Ssam 384171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING int 385171095Ssam__hal_ring_block_memblock_idx(xge_hal_ring_block_t *block); 386171095Ssam 387171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 388171095Ssam__hal_ring_block_memblock_idx_set(xge_hal_ring_block_t*block, int memblock_idx); 389171095Ssam 390171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING dma_addr_t 391171095Ssam__hal_ring_block_next_pointer(xge_hal_ring_block_t *block); 392171095Ssam 393171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 394171095Ssam__hal_ring_block_next_pointer_set(xge_hal_ring_block_t*block, 395173139Srwatson dma_addr_t dma_next); 396171095Ssam 397171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_ring_rxd_priv_t* 398171095Ssam__hal_ring_rxd_priv(xge_hal_ring_t *ring, xge_hal_dtr_h dtrh); 399171095Ssam 400171095Ssam/* =========================== RING PUBLIC API ============================ */ 401171095Ssam 402171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 403171095Ssamxge_hal_ring_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh); 404171095Ssam 405171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void* 406171095Ssamxge_hal_ring_dtr_private(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 407171095Ssam 408171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 409173139Srwatsonxge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int size); 410171095Ssam 411171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 412171095Ssamxge_hal_ring_dtr_info_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 413173139Srwatson xge_hal_dtr_info_t *ext_info); 414171095Ssam 415171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 416171095Ssamxge_hal_ring_dtr_1b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 417173139Srwatson dma_addr_t *dma_pointer, int *pkt_length); 418171095Ssam 419171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 420171095Ssamxge_hal_ring_dtr_3b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], 421173139Srwatson int sizes[]); 422171095Ssam 423171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 424171095Ssamxge_hal_ring_dtr_3b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 425173139Srwatson dma_addr_t dma_pointers[], int sizes[]); 426171095Ssam 427171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 428171095Ssamxge_hal_ring_dtr_5b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[], 429173139Srwatson int sizes[]); 430171095Ssam 431171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 432171095Ssamxge_hal_ring_dtr_5b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh, 433173139Srwatson dma_addr_t dma_pointer[], int sizes[]); 434171095Ssam 435171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 436171095Ssamxge_hal_ring_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 437171095Ssam 438171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 439171095Ssamxge_hal_ring_dtr_pre_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 440171095Ssam 441171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 442171095Ssamxge_hal_ring_dtr_post_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 443171095Ssam 444171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 445171095Ssamxge_hal_ring_dtr_post_post_wmb(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 446171095Ssam 447171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 448171095Ssamxge_hal_ring_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh, 449173139Srwatson u8 *t_code); 450171095Ssam 451171095Ssam__HAL_STATIC_RING __HAL_INLINE_RING void 452171095Ssamxge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh); 453171095Ssam 454173139Srwatson__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_status_e 455171095Ssamxge_hal_ring_is_next_dtr_completed(xge_hal_channel_h channelh); 456171095Ssam 457171095Ssam#else /* XGE_FASTPATH_EXTERN */ 458171095Ssam#define __HAL_STATIC_RING static 459171095Ssam#define __HAL_INLINE_RING inline 460171095Ssam#include <dev/nxge/xgehal/xgehal-ring-fp.c> 461171095Ssam#endif /* XGE_FASTPATH_INLINE */ 462171095Ssam 463171095Ssam__EXTERN_END_DECLS 464171095Ssam 465171095Ssam#endif /* XGE_HAL_RING_H */ 466