xgehal-device.h revision 171095
1/*- 2 * Copyright (c) 2002-2007 Neterion, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/nxge/include/xgehal-device.h 171095 2007-06-29 22:47:18Z sam $ 27 */ 28 29/* 30 * FileName : xgehal-device.h 31 * 32 * Description: HAL device object functionality 33 * 34 * Created: 14 May 2004 35 */ 36 37#ifndef XGE_HAL_DEVICE_H 38#define XGE_HAL_DEVICE_H 39 40#include <dev/nxge/include/xge-os-pal.h> 41#include <dev/nxge/include/xge-queue.h> 42#include <dev/nxge/include/xgehal-event.h> 43#include <dev/nxge/include/xgehal-config.h> 44#include <dev/nxge/include/xgehal-regs.h> 45#include <dev/nxge/include/xgehal-channel.h> 46#include <dev/nxge/include/xgehal-stats.h> 47#include <dev/nxge/include/xgehal-ring.h> 48#ifdef XGEHAL_RNIC 49#include "xgehal-common-regs.h" 50#include "xgehal-pcicfg-mgmt-regs.h" 51#include "xgehal-mrpcim-regs.h" 52#include "xgehal-srpcim-regs.h" 53#include "xgehal-vpath-regs.h" 54#include "xgehal-bitmap.h" 55#include "xgehal-virtualpath.h" 56#include "xgehal-lbwrapper.h" 57#include "xgehal-blockpool.h" 58#include "xgehal-regpool.h" 59#endif 60 61__EXTERN_BEGIN_DECLS 62 63#define XGE_HAL_VPD_LENGTH 80 64#define XGE_HAL_CARD_XENA_VPD_ADDR 0x50 65#define XGE_HAL_CARD_HERC_VPD_ADDR 0x80 66#define XGE_HAL_VPD_READ_COMPLETE 0x80 67#define XGE_HAL_VPD_BUFFER_SIZE 128 68#define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS 500 69#define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS 500 70#define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS 500 71#define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS 50 72#define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS 250 73#define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS 250 /* TODO */ 74 75#define XGE_HAL_MAGIC 0x12345678 76#define XGE_HAL_DEAD 0xDEADDEAD 77#define XGE_HAL_DUMP_BUF_SIZE 0x4000 78 79#define XGE_HAL_LRO_MAX_BUCKETS 32 80 81/** 82 * enum xge_hal_card_e - Xframe adapter type. 83 * @XGE_HAL_CARD_UNKNOWN: Unknown device. 84 * @XGE_HAL_CARD_XENA: Xframe I device. 85 * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device. 86 * @XGE_HAL_CARD_TITAN: Xframe ER (PCI-266Mhz) device. 87 * 88 * Enumerates Xframe adapter types. The corresponding PCI device 89 * IDs are listed in the file xgehal-defs.h. 90 * (See XGE_PCI_DEVICE_ID_XENA_1, etc.) 91 * 92 * See also: xge_hal_device_check_id(). 93 */ 94typedef enum xge_hal_card_e { 95 XGE_HAL_CARD_UNKNOWN = 0, 96 XGE_HAL_CARD_XENA = 1, 97 XGE_HAL_CARD_HERC = 2, 98 XGE_HAL_CARD_TITAN = 3, 99} xge_hal_card_e; 100 101/** 102 * struct xge_hal_device_attr_t - Device memory spaces. 103 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 104 * (Linux and the rest.) 105 * @regh1: BAR1 mapped memory handle. Same comment as above. 106 * @bar0: BAR0 virtual address. 107 * @bar1: BAR1 virtual address. 108 * @irqh: IRQ handle (Solaris). 109 * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux). 110 * @pdev: PCI device object. 111 * 112 * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device 113 * mapped memories. Also, includes a pointer to OS-specific PCI device object. 114 */ 115typedef struct xge_hal_device_attr_t { 116 pci_reg_h regh0; 117 pci_reg_h regh1; 118 pci_reg_h regh2; 119 char *bar0; 120 char *bar1; 121 char *bar2; 122 pci_irq_h irqh; 123 pci_cfg_h cfgh; 124 pci_dev_h pdev; 125} xge_hal_device_attr_t; 126 127/** 128 * enum xge_hal_device_link_state_e - Link state enumeration. 129 * @XGE_HAL_LINK_NONE: Invalid link state. 130 * @XGE_HAL_LINK_DOWN: Link is down. 131 * @XGE_HAL_LINK_UP: Link is up. 132 * 133 */ 134typedef enum xge_hal_device_link_state_e { 135 XGE_HAL_LINK_NONE, 136 XGE_HAL_LINK_DOWN, 137 XGE_HAL_LINK_UP 138} xge_hal_device_link_state_e; 139 140 141/** 142 * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration. 143 * @XGE_HAL_PCI_33MHZ_MODE: 33 MHZ pci mode. 144 * @XGE_HAL_PCI_66MHZ_MODE: 66 MHZ pci mode. 145 * @XGE_HAL_PCIX_M1_66MHZ_MODE: PCIX M1 66MHZ mode. 146 * @XGE_HAL_PCIX_M1_100MHZ_MODE: PCIX M1 100MHZ mode. 147 * @XGE_HAL_PCIX_M1_133MHZ_MODE: PCIX M1 133MHZ mode. 148 * @XGE_HAL_PCIX_M2_66MHZ_MODE: PCIX M2 66MHZ mode. 149 * @XGE_HAL_PCIX_M2_100MHZ_MODE: PCIX M2 100MHZ mode. 150 * @XGE_HAL_PCIX_M2_133MHZ_MODE: PCIX M3 133MHZ mode. 151 * @XGE_HAL_PCIX_M1_RESERVED: PCIX M1 reserved mode. 152 * @XGE_HAL_PCIX_M1_66MHZ_NS: PCIX M1 66MHZ mode not supported. 153 * @XGE_HAL_PCIX_M1_100MHZ_NS: PCIX M1 100MHZ mode not supported. 154 * @XGE_HAL_PCIX_M1_133MHZ_NS: PCIX M1 133MHZ not supported. 155 * @XGE_HAL_PCIX_M2_RESERVED: PCIX M2 reserved. 156 * @XGE_HAL_PCIX_533_RESERVED: PCIX 533 reserved. 157 * @XGE_HAL_PCI_BASIC_MODE: PCI basic mode, XENA specific value. 158 * @XGE_HAL_PCIX_BASIC_MODE: PCIX basic mode, XENA specific value. 159 * @XGE_HAL_PCI_INVALID_MODE: Invalid PCI or PCIX mode. 160 * 161 */ 162typedef enum xge_hal_pci_mode_e { 163 XGE_HAL_PCI_33MHZ_MODE = 0x0, 164 XGE_HAL_PCI_66MHZ_MODE = 0x1, 165 XGE_HAL_PCIX_M1_66MHZ_MODE = 0x2, 166 XGE_HAL_PCIX_M1_100MHZ_MODE = 0x3, 167 XGE_HAL_PCIX_M1_133MHZ_MODE = 0x4, 168 XGE_HAL_PCIX_M2_66MHZ_MODE = 0x5, 169 XGE_HAL_PCIX_M2_100MHZ_MODE = 0x6, 170 XGE_HAL_PCIX_M2_133MHZ_MODE = 0x7, 171 XGE_HAL_PCIX_M1_RESERVED = 0x8, 172 XGE_HAL_PCIX_M1_66MHZ_NS = 0xA, 173 XGE_HAL_PCIX_M1_100MHZ_NS = 0xB, 174 XGE_HAL_PCIX_M1_133MHZ_NS = 0xC, 175 XGE_HAL_PCIX_M2_RESERVED = 0xD, 176 XGE_HAL_PCIX_533_RESERVED = 0xE, 177 XGE_HAL_PCI_BASIC_MODE = 0x10, 178 XGE_HAL_PCIX_BASIC_MODE = 0x11, 179 XGE_HAL_PCI_INVALID_MODE = 0x12, 180} xge_hal_pci_mode_e; 181 182/** 183 * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration. 184 * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ: PCI bus frequency 33MHZ 185 * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ: PCI bus frequency 66MHZ 186 * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ: PCI bus frequency 100MHZ 187 * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ: PCI bus frequency 133MHZ 188 * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ: PCI bus frequency 200MHZ 189 * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ: PCI bus frequency 250MHZ 190 * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ: PCI bus frequency 266MHZ 191 * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN: Unrecognized PCI bus frequency value. 192 * 193 */ 194typedef enum xge_hal_pci_bus_frequency_e { 195 XGE_HAL_PCI_BUS_FREQUENCY_33MHZ = 33, 196 XGE_HAL_PCI_BUS_FREQUENCY_66MHZ = 66, 197 XGE_HAL_PCI_BUS_FREQUENCY_100MHZ = 100, 198 XGE_HAL_PCI_BUS_FREQUENCY_133MHZ = 133, 199 XGE_HAL_PCI_BUS_FREQUENCY_200MHZ = 200, 200 XGE_HAL_PCI_BUS_FREQUENCY_250MHZ = 250, 201 XGE_HAL_PCI_BUS_FREQUENCY_266MHZ = 266, 202 XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN = 0 203} xge_hal_pci_bus_frequency_e; 204 205/** 206 * enum xge_hal_pci_bus_width_e - PCI bus width enumeration. 207 * @XGE_HAL_PCI_BUS_WIDTH_64BIT: 64 bit bus width. 208 * @XGE_HAL_PCI_BUS_WIDTH_32BIT: 32 bit bus width. 209 * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN: unknown bus width. 210 * 211 */ 212typedef enum xge_hal_pci_bus_width_e { 213 XGE_HAL_PCI_BUS_WIDTH_64BIT = 0, 214 XGE_HAL_PCI_BUS_WIDTH_32BIT = 1, 215 XGE_HAL_PCI_BUS_WIDTH_UNKNOWN = 2, 216} xge_hal_pci_bus_width_e; 217 218#if defined (XGE_HAL_CONFIG_LRO) 219 220#define IP_TOTAL_LENGTH_OFFSET 2 221#define IP_FAST_PATH_HDR_MASK 0x45 222#define TCP_FAST_PATH_HDR_MASK1 0x50 223#define TCP_FAST_PATH_HDR_MASK2 0x10 224#define TCP_FAST_PATH_HDR_MASK3 0x18 225#define IP_SOURCE_ADDRESS_OFFSET 12 226#define IP_DESTINATION_ADDRESS_OFFSET 16 227#define TCP_DESTINATION_PORT_OFFSET 2 228#define TCP_SOURCE_PORT_OFFSET 0 229#define TCP_DATA_OFFSET_OFFSET 12 230#define TCP_WINDOW_OFFSET 14 231#define TCP_SEQUENCE_NUMBER_OFFSET 4 232#define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET 8 233 234typedef struct tcplro { 235 u16 source; 236 u16 dest; 237 u32 seq; 238 u32 ack_seq; 239 u8 doff_res; 240 u8 ctrl; 241 u16 window; 242 u16 check; 243 u16 urg_ptr; 244} tcplro_t; 245 246typedef struct iplro { 247 u8 version_ihl; 248 u8 tos; 249 u16 tot_len; 250 u16 id; 251 u16 frag_off; 252 u8 ttl; 253 u8 protocol; 254 u16 check; 255 u32 saddr; 256 u32 daddr; 257 /*The options start here. */ 258} iplro_t; 259 260/* 261 * LRO object, one per each LRO session. 262*/ 263typedef struct lro { 264 /* non-linear: contains scatter-gather list of 265 xframe-mapped received buffers */ 266 OS_NETSTACK_BUF os_buf; 267 OS_NETSTACK_BUF os_buf_end; 268 269 /* link layer header of the first frame; 270 remains intack throughout the processing */ 271 u8 *ll_hdr; 272 273 /* IP header - gets _collapsed_ */ 274 iplro_t *ip_hdr; 275 276 /* transport header - gets _collapsed_ */ 277 tcplro_t *tcp_hdr; 278 279 /* Next tcp sequence number */ 280 u32 tcp_next_seq_num; 281 /* Current tcp seq & ack */ 282 u32 tcp_seq_num; 283 u32 tcp_ack_num; 284 285 /* total number of accumulated (so far) frames */ 286 int sg_num; 287 288 /* total data length */ 289 int total_length; 290 291 /* receive side hash value, available from Hercules */ 292 u32 rth_value; 293 294 /* In use */ 295 u8 in_use; 296 297 /* Total length of the fragments clubbed with the inital frame */ 298 u32 frags_len; 299 300 /* LRO frame contains time stamp, if (ts_off != -1) */ 301 int ts_off; 302 303} lro_t; 304#endif 305 306/* 307 * xge_hal_spdm_entry_t 308 * 309 * Represents a single spdm entry in the SPDM table. 310 */ 311typedef struct xge_hal_spdm_entry_t { 312 xge_hal_ipaddr_t src_ip; 313 xge_hal_ipaddr_t dst_ip; 314 u32 jhash_value; 315 u16 l4_sp; 316 u16 l4_dp; 317 u16 spdm_entry; 318 u8 in_use; 319 u8 is_tcp; 320 u8 is_ipv4; 321 u8 tgt_queue; 322} xge_hal_spdm_entry_t; 323 324#if defined(XGE_HAL_CONFIG_LRO) 325typedef struct { 326 lro_t lro_pool[XGE_HAL_LRO_MAX_BUCKETS]; 327 int lro_next_idx; 328 lro_t *lro_recent; 329} xge_hal_lro_desc_t; 330#endif 331/* 332 * xge_hal_vpd_data_t 333 * 334 * Represents vpd capabilty structure 335 */ 336typedef struct xge_hal_vpd_data_t { 337 u8 product_name[XGE_HAL_VPD_LENGTH]; 338 u8 serial_num[XGE_HAL_VPD_LENGTH]; 339} xge_hal_vpd_data_t; 340 341/* 342 * xge_hal_device_t 343 * 344 * HAL device object. Represents Xframe. 345 */ 346typedef struct { 347 unsigned int magic; 348 pci_reg_h regh0; 349 pci_reg_h regh1; 350 pci_reg_h regh2; 351 char *bar0; 352 char *isrbar0; 353 char *bar1; 354 char *bar2; 355 pci_irq_h irqh; 356 pci_cfg_h cfgh; 357 pci_dev_h pdev; 358 xge_hal_pci_config_t pci_config_space; 359 xge_hal_pci_config_t pci_config_space_bios; 360 xge_hal_device_config_t config; 361 xge_list_t free_channels; 362 xge_list_t fifo_channels; 363 xge_list_t ring_channels; 364#ifdef XGEHAL_RNIC 365 __hal_bitmap_entry_t bitmap_table[XGE_HAL_MAX_BITMAP_BITS]; 366 __hal_virtualpath_t virtual_paths[XGE_HAL_MAX_VIRTUAL_PATHS]; 367 __hal_blockpool_t block_pool; 368 __hal_regpool_t reg_pool; 369#endif 370 volatile int is_initialized; 371 volatile int terminating; 372 xge_hal_stats_t stats; 373 macaddr_t macaddr[1]; 374 xge_queue_h queueh; 375 volatile int mcast_refcnt; 376 int is_promisc; 377 volatile xge_hal_device_link_state_e link_state; 378 void *upper_layer_info; 379 xge_hal_device_attr_t orig_attr; 380 u16 device_id; 381 u8 revision; 382 int msi_enabled; 383 int hw_is_initialized; 384 u64 inject_serr; 385 u64 inject_ecc; 386 u8 inject_bad_tcode; 387 int inject_bad_tcode_for_chan_type; 388 int reset_needed_after_close; 389 int tti_enabled; 390 xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM]; 391 int bimodal_timer_val_us; 392 int bimodal_urange_a_en; 393 int bimodal_intr_cnt; 394 char *spdm_mem_base; 395 u16 spdm_max_entries; 396 xge_hal_spdm_entry_t **spdm_table; 397 spinlock_t spdm_lock; 398 u32 msi_mask; 399#if defined(XGE_HAL_CONFIG_LRO) 400 xge_hal_lro_desc_t lro_desc[XGE_HAL_MAX_RING_NUM]; 401#endif 402 spinlock_t xena_post_lock; 403 404 /* bimodal workload stats */ 405 int irq_workload_rxd[XGE_HAL_MAX_RING_NUM]; 406 int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM]; 407 int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM]; 408 int irq_workload_txd[XGE_HAL_MAX_FIFO_NUM]; 409 int irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM]; 410 int irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM]; 411 412 int mtu_first_time_set; 413 u64 rxufca_lbolt; 414 u64 rxufca_lbolt_time; 415 u64 rxufca_intr_thres; 416 char* dump_buf; 417 xge_hal_pci_mode_e pci_mode; 418 xge_hal_pci_bus_frequency_e bus_frequency; 419 xge_hal_pci_bus_width_e bus_width; 420 xge_hal_vpd_data_t vpd_data; 421 volatile int in_poll; 422 u64 msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR]; 423} xge_hal_device_t; 424 425 426/* ========================== PRIVATE API ================================= */ 427 428void 429__hal_device_event_queued(void *data, int event_type); 430 431xge_hal_status_e 432__hal_device_set_swapper(xge_hal_device_t *hldev); 433 434xge_hal_status_e 435__hal_device_rth_it_configure(xge_hal_device_t *hldev); 436 437xge_hal_status_e 438__hal_device_rth_spdm_configure(xge_hal_device_t *hldev); 439 440xge_hal_status_e 441__hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status); 442 443xge_hal_status_e 444__hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason); 445 446xge_hal_status_e 447__hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line, 448 u16 spdm_entry, u64 *spdm_line_val); 449 450void __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val, 451 void *addr); 452 453void __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val, 454 void *addr); 455void __hal_device_get_vpd_data(xge_hal_device_t *hldev); 456 457xge_hal_status_e 458__hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason); 459 460xge_hal_status_e 461__hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason); 462 463xge_hal_status_e 464__hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason); 465 466xge_hal_status_e 467__hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason); 468 469xge_hal_status_e 470__hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason); 471 472xge_hal_status_e 473__hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason); 474 475xge_hal_status_e 476__hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason); 477 478xge_hal_status_e 479__hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason); 480 481xge_hal_status_e 482__hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason); 483 484xge_hal_status_e 485__hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask, 486 int max_millis); 487xge_hal_status_e 488__hal_device_rts_mac_configure(xge_hal_device_t *hldev); 489 490xge_hal_status_e 491__hal_device_rts_qos_configure(xge_hal_device_t *hldev); 492 493xge_hal_status_e 494__hal_device_rts_port_configure(xge_hal_device_t *hldev); 495 496xge_hal_status_e 497__hal_device_rti_configure(xge_hal_device_t *hldev, int runtime); 498 499void 500__hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag); 501 502void 503__hal_device_msix_intr_endis(xge_hal_device_t *hldev, 504 xge_hal_channel_t *channel, int flag); 505 506/* =========================== PUBLIC API ================================= */ 507 508unsigned int 509__hal_fix_time_ival_herc(xge_hal_device_t *hldev, 510 unsigned int time_ival); 511xge_hal_status_e 512xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable, 513 u32 itable_size); 514 515void 516xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type, 517 u16 bucket_size); 518 519void 520xge_hal_rts_rth_init(xge_hal_device_t *hldev); 521 522void 523xge_hal_rts_rth_clr(xge_hal_device_t *hldev); 524 525void 526xge_hal_rts_rth_start(xge_hal_device_t *hldev); 527 528void 529xge_hal_rts_rth_stop(xge_hal_device_t *hldev); 530 531void 532xge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key); 533 534xge_hal_status_e 535xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr); 536 537xge_hal_status_e 538xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index); 539 540int xge_hal_reinitialize_hw(xge_hal_device_t * hldev); 541 542/** 543 * xge_hal_device_rti_reconfigure 544 * @hldev: Hal Device 545 */ 546static inline xge_hal_status_e 547xge_hal_device_rti_reconfigure(xge_hal_device_t *hldev) 548{ 549 return __hal_device_rti_configure(hldev, 1); 550} 551 552/** 553 * xge_hal_device_rts_port_reconfigure 554 * @hldev: Hal Device 555 */ 556static inline xge_hal_status_e 557xge_hal_device_rts_port_reconfigure(xge_hal_device_t *hldev) 558{ 559 return __hal_device_rts_port_configure(hldev); 560} 561 562/** 563 * xge_hal_device_is_initialized - Returns 0 if device is not 564 * initialized, non-zero otherwise. 565 * @devh: HAL device handle. 566 * 567 * Returns 0 if device is not initialized, non-zero otherwise. 568 */ 569static inline int 570xge_hal_device_is_initialized(xge_hal_device_h devh) 571{ 572 return ((xge_hal_device_t*)devh)->is_initialized; 573} 574 575 576/** 577 * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing. 578 * @devh: HAL device handle. 579 * 580 * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise. 581 */ 582static inline int 583xge_hal_device_in_poll(xge_hal_device_h devh) 584{ 585 return ((xge_hal_device_t*)devh)->in_poll; 586} 587 588 589/** 590 * xge_hal_device_inject_ecc - Inject ECC error. 591 * @devh: HAL device, pointer to xge_hal_device_t structure. 592 * @err_reg: Contains the error register. 593 * 594 * This function is used to inject ECC error into the driver flow. 595 * This facility can be used to test the driver flow in the 596 * case of ECC error is reported by the firmware. 597 * 598 * Returns: void 599 * See also: xge_hal_device_inject_serr(), 600 * xge_hal_device_inject_bad_tcode() 601 */ 602static inline void 603xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg) 604{ 605 ((xge_hal_device_t*)devh)->inject_ecc = err_reg; 606} 607 608 609/** 610 * xge_hal_device_inject_serr - Inject SERR error. 611 * @devh: HAL device, pointer to xge_hal_device_t structure. 612 * @err_reg: Contains the error register. 613 * 614 * This function is used to inject SERR error into the driver flow. 615 * This facility can be used to test the driver flow in the 616 * case of SERR error is reported by firmware. 617 * 618 * Returns: void 619 * See also: xge_hal_device_inject_ecc(), 620 * xge_hal_device_inject_bad_tcode() 621 */ 622static inline void 623xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg) 624{ 625 ((xge_hal_device_t*)devh)->inject_serr = err_reg; 626} 627 628 629/** 630 * xge_hal_device_inject_bad_tcode - Inject Bad transfer code. 631 * @devh: HAL device, pointer to xge_hal_device_t structure. 632 * @chan_type: Channel type (fifo/ring). 633 * @t_code: Transfer code. 634 * 635 * This function is used to inject bad (Tx/Rx Data)transfer code 636 * into the driver flow. 637 * 638 * This facility can be used to test the driver flow in the 639 * case of bad transfer code reported by firmware for a Tx/Rx data 640 * transfer. 641 * 642 * Returns: void 643 * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr() 644 */ 645static inline void 646xge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code) 647{ 648 ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type; 649 ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code; 650} 651 652void xge_hal_device_msi_enable(xge_hal_device_h devh); 653 654/* 655 * xge_hal_device_msi_mode - Is MSI enabled? 656 * @devh: HAL device handle. 657 * 658 * Returns 0 if MSI is enabled for the specified device, 659 * non-zero otherwise. 660 */ 661static inline int 662xge_hal_device_msi_mode(xge_hal_device_h devh) 663{ 664 return ((xge_hal_device_t*)devh)->msi_enabled; 665} 666 667/** 668 * xge_hal_device_queue - Get per-device event queue. 669 * @devh: HAL device handle. 670 * 671 * Returns: event queue associated with the specified HAL device. 672 */ 673static inline xge_queue_h 674xge_hal_device_queue (xge_hal_device_h devh) 675{ 676 return ((xge_hal_device_t*)devh)->queueh; 677} 678 679/** 680 * xge_hal_device_attr - Get original (user-specified) device 681 * attributes. 682 * @devh: HAL device handle. 683 * 684 * Returns: original (user-specified) device attributes. 685 */ 686static inline xge_hal_device_attr_t* 687xge_hal_device_attr(xge_hal_device_h devh) 688{ 689 return &((xge_hal_device_t*)devh)->orig_attr; 690} 691 692/** 693 * xge_hal_device_private_set - Set ULD context. 694 * @devh: HAL device handle. 695 * @data: pointer to ULD context 696 * 697 * Use HAL device to set upper-layer driver (ULD) context. 698 * 699 * See also: xge_hal_device_from_private(), xge_hal_device_private() 700 */ 701static inline void 702xge_hal_device_private_set(xge_hal_device_h devh, void *data) 703{ 704 ((xge_hal_device_t*)devh)->upper_layer_info = data; 705} 706 707/** 708 * xge_hal_device_private - Get ULD context. 709 * @devh: HAL device handle. 710 * 711 * Use HAL device to get upper-layer driver (ULD) context. 712 * 713 * Returns: ULD context. 714 * 715 * See also: xge_hal_device_from_private(), xge_hal_device_private_set() 716 */ 717static inline void* 718xge_hal_device_private(xge_hal_device_h devh) 719{ 720 return ((xge_hal_device_t*)devh)->upper_layer_info; 721} 722 723/** 724 * xge_hal_device_from_private - Get HAL device object from private. 725 * @info_ptr: ULD context. 726 * 727 * Use ULD context to get HAL device. 728 * 729 * Returns: Device handle. 730 * 731 * See also: xge_hal_device_private(), xge_hal_device_private_set() 732 */ 733static inline xge_hal_device_h 734xge_hal_device_from_private(void *info_ptr) 735{ 736 return xge_container_of((void ** ) info_ptr, xge_hal_device_t, 737 upper_layer_info); 738} 739 740/** 741 * xge_hal_device_mtu_check - check MTU value for ranges 742 * @hldev: the device 743 * @new_mtu: new MTU value to check 744 * 745 * Will do sanity check for new MTU value. 746 * 747 * Returns: XGE_HAL_OK - success. 748 * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid. 749 * 750 * See also: xge_hal_device_mtu_set() 751 */ 752static inline xge_hal_status_e 753xge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu) 754{ 755 if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) { 756 return XGE_HAL_ERR_INVALID_MTU_SIZE; 757 } 758 759 return XGE_HAL_OK; 760} 761 762void xge_hal_device_bcast_enable(xge_hal_device_h devh); 763 764void xge_hal_device_bcast_disable(xge_hal_device_h devh); 765 766void xge_hal_device_terminating(xge_hal_device_h devh); 767 768xge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev, 769 xge_hal_device_attr_t *attr, xge_hal_device_config_t *config); 770 771void xge_hal_device_terminate(xge_hal_device_t *hldev); 772 773xge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev); 774 775xge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev, 776 int index, macaddr_t *macaddr); 777 778xge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev, 779 int index, macaddr_t macaddr); 780 781xge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev, 782 int index); 783 784int xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted); 785 786xge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu); 787 788xge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status); 789 790void xge_hal_device_intr_enable(xge_hal_device_t *hldev); 791 792void xge_hal_device_intr_disable(xge_hal_device_t *hldev); 793 794xge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev); 795 796xge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev); 797 798void xge_hal_device_promisc_enable(xge_hal_device_t *hldev); 799 800void xge_hal_device_promisc_disable(xge_hal_device_t *hldev); 801 802xge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev); 803 804xge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev); 805 806xge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh, 807 xge_hal_dtr_h dtrh, 808 u8 t_code); 809 810xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh, 811 xge_hal_device_link_state_e *ls); 812 813void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us, 814 int one_shot); 815 816void xge_hal_device_poll(xge_hal_device_h devh); 817 818xge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh); 819 820int xge_hal_device_is_slot_freeze(xge_hal_device_h devh); 821 822xge_hal_status_e 823xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode, 824 xge_hal_pci_bus_frequency_e *bus_frequency, 825 xge_hal_pci_bus_width_e *bus_width); 826 827xge_hal_status_e 828xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, 829 xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, 830 u8 is_tcp, u8 is_ipv4, u8 tgt_queue); 831 832xge_hal_status_e 833xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip, 834 xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp, 835 u8 is_tcp, u8 is_ipv4); 836 837xge_hal_status_e 838xge_hal_device_rts_section_enable(xge_hal_device_h devh, int index); 839 840int 841xge_hal_device_is_closed (xge_hal_device_h devh); 842 843/* private functions, don't use them in ULD */ 844 845void __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg); 846 847u64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg); 848 849 850/* Some function protoypes for MSI implementation. */ 851xge_hal_status_e 852xge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi, 853 u32 msg_val); 854void 855xge_hal_mask_msi(xge_hal_device_t *hldev); 856 857void 858xge_hal_unmask_msi(xge_hal_channel_h channelh); 859 860xge_hal_status_e 861xge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx); 862 863xge_hal_status_e 864xge_hal_mask_msix(xge_hal_device_h devh, int msi_id); 865 866xge_hal_status_e 867xge_hal_unmask_msix(xge_hal_device_h devh, int msi_id); 868 869#if defined(XGE_HAL_CONFIG_LRO) 870xge_hal_status_e 871xge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev); 872#endif 873 874#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE) 875#define __HAL_STATIC_DEVICE 876#define __HAL_INLINE_DEVICE 877 878__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int 879xge_hal_device_rev(xge_hal_device_t *hldev); 880 881__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 882xge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason); 883 884__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 885xge_hal_device_clear_rx(xge_hal_device_t *hldev); 886 887__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 888xge_hal_device_clear_tx(xge_hal_device_t *hldev); 889 890__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 891xge_hal_device_continue_irq(xge_hal_device_t *hldev); 892 893__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 894xge_hal_device_handle_irq(xge_hal_device_t *hldev); 895 896__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 897xge_hal_device_bar0(xge_hal_device_t *hldev); 898 899__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 900xge_hal_device_isrbar0(xge_hal_device_t *hldev); 901 902__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char * 903xge_hal_device_bar1(xge_hal_device_t *hldev); 904 905__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 906xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0); 907 908__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 909xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0); 910 911__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 912xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh, 913 char *bar1); 914 915__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 916xge_hal_device_mask_tx(xge_hal_device_t *hldev); 917 918__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 919xge_hal_device_mask_rx(xge_hal_device_t *hldev); 920 921__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 922xge_hal_device_mask_all(xge_hal_device_t *hldev); 923 924__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 925xge_hal_device_unmask_tx(xge_hal_device_t *hldev); 926 927__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 928xge_hal_device_unmask_rx(xge_hal_device_t *hldev); 929 930__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void 931xge_hal_device_unmask_all(xge_hal_device_t *hldev); 932 933__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 934xge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx); 935 936__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 937xge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx); 938 939__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 940xge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx); 941 942__HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e 943xge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx); 944 945#if defined (XGE_HAL_CONFIG_LRO) 946__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8 947__hal_header_parse_token_u8(u8 *string,u16 offset); 948 949__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16 950__hal_header_parse_token_u16(u8 *string,u16 offset); 951 952__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32 953__hal_header_parse_token_u32(u8 *string,u16 offset); 954 955__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 956__hal_header_update_u8(u8 *string, u16 offset, u8 val); 957 958__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 959__hal_header_update_u16(u8 *string, u16 offset, u16 val); 960 961__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 962__hal_header_update_u32(u8 *string, u16 offset, u32 val); 963 964__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16 965__hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp); 966 967__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 968__hal_ip_lro_capable(iplro_t *ip, xge_hal_dtr_info_t *ext_info); 969 970__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 971__hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off); 972 973__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 974__hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp, 975 xge_hal_dtr_info_t *ext_info); 976 977__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 978__hal_get_lro_session(u8 *eth_hdr, iplro_t *ip, tcplro_t *tcp, lro_t **lro, 979 xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, 980 xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3); 981 982__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 983__hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 984 xge_hal_device_t *hldev); 985 986__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 987__hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 988 xge_hal_device_t *hldev); 989 990__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 991__hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro, 992 xge_hal_device_t *hldev); 993 994__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 995__hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro, 996 xge_hal_device_t *hldev); 997 998__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 999xge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp, 1000 u32 *seglen, lro_t **p_lro, 1001 xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev, 1002 lro_t **lro_end3); 1003 1004__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e 1005xge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen, 1006 lro_t **lro, xge_hal_dtr_info_t *ext_info, 1007 xge_hal_device_t *hldev, lro_t **lro_end3); 1008 1009void 1010xge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev); 1011 1012__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * 1013xge_hal_lro_next_session (xge_hal_device_t *hldev, int ring); 1014 1015__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t * 1016xge_hal_lro_get_next_session(xge_hal_device_t *hldev); 1017 1018__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void 1019__hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro, 1020 xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro, 1021 int slot, u32 tcp_seg_len, int ts_off); 1022 1023__HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int 1024__hal_lro_get_free_slot (xge_hal_lro_desc_t *ring_lro); 1025#endif 1026 1027#else /* XGE_FASTPATH_EXTERN */ 1028#define __HAL_STATIC_DEVICE static 1029#define __HAL_INLINE_DEVICE inline 1030#include <dev/nxge/xgehal/xgehal-device-fp.c> 1031#endif /* XGE_FASTPATH_INLINE */ 1032 1033 1034__EXTERN_END_DECLS 1035 1036#endif /* XGE_HAL_DEVICE_H */ 1037