1265555Sambrisko/* 2265555Sambrisko * Copyright (c) 2014, LSI Corp. 3265555Sambrisko * All rights reserved. 4265555Sambrisko * Authors: Marian Choy 5265555Sambrisko * Support: freebsdraid@lsi.com 6265555Sambrisko * 7265555Sambrisko * Redistribution and use in source and binary forms, with or without 8265555Sambrisko * modification, are permitted provided that the following conditions 9265555Sambrisko * are met: 10265555Sambrisko * 11265555Sambrisko * 1. Redistributions of source code must retain the above copyright 12265555Sambrisko * notice, this list of conditions and the following disclaimer. 13265555Sambrisko * 2. Redistributions in binary form must reproduce the above copyright 14265555Sambrisko * notice, this list of conditions and the following disclaimer in 15265555Sambrisko * the documentation and/or other materials provided with the 16265555Sambrisko * distribution. 17265555Sambrisko * 3. Neither the name of the <ORGANIZATION> nor the names of its 18265555Sambrisko * contributors may be used to endorse or promote products derived 19265555Sambrisko * from this software without specific prior written permission. 20265555Sambrisko * 21265555Sambrisko * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22265555Sambrisko * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23265555Sambrisko * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24265555Sambrisko * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25265555Sambrisko * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26265555Sambrisko * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 27265555Sambrisko * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28265555Sambrisko * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29265555Sambrisko * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30265555Sambrisko * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31265555Sambrisko * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32265555Sambrisko * POSSIBILITY OF SUCH DAMAGE. 33265555Sambrisko * 34265555Sambrisko * The views and conclusions contained in the software and documentation 35265555Sambrisko * are those of the authors and should not be interpreted as representing 36265555Sambrisko * official policies,either expressed or implied, of the FreeBSD Project. 37265555Sambrisko * 38265555Sambrisko * Send feedback to: <megaraidfbsd@lsi.com> 39265555Sambrisko * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035 40265555Sambrisko * ATTN: MegaRaid FreeBSD 41265555Sambrisko * 42265555Sambrisko */ 43265555Sambrisko 44265555Sambrisko#include <sys/cdefs.h> 45265555Sambrisko__FBSDID("$FreeBSD$"); 46265555Sambrisko 47265555Sambrisko#ifndef MRSAS_H 48265555Sambrisko#define MRSAS_H 49265555Sambrisko 50265555Sambrisko#include <sys/param.h> /* defines used in kernel.h */ 51265555Sambrisko#include <sys/module.h> 52265555Sambrisko#include <sys/systm.h> 53265555Sambrisko#include <sys/proc.h> 54265555Sambrisko#include <sys/errno.h> 55265555Sambrisko#include <sys/kernel.h> /* types used in module initialization */ 56265555Sambrisko#include <sys/conf.h> /* cdevsw struct */ 57265555Sambrisko#include <sys/uio.h> /* uio struct */ 58265555Sambrisko#include <sys/malloc.h> 59265555Sambrisko#include <sys/bus.h> /* structs, prototypes for pci bus stuff */ 60265555Sambrisko 61265555Sambrisko#include <machine/bus.h> 62265555Sambrisko#include <sys/rman.h> 63265555Sambrisko#include <machine/resource.h> 64265555Sambrisko#include <machine/atomic.h> 65265555Sambrisko 66265555Sambrisko#include <dev/pci/pcivar.h> /* For pci_get macros! */ 67265555Sambrisko#include <dev/pci/pcireg.h> 68265555Sambrisko 69265555Sambrisko#include <sys/types.h> 70265555Sambrisko#include <sys/sysctl.h> 71265555Sambrisko#include <sys/stat.h> 72265555Sambrisko#include <sys/taskqueue.h> 73265555Sambrisko#include <sys/poll.h> 74265555Sambrisko#include <sys/selinfo.h> 75265555Sambrisko 76265555Sambrisko/* 77265555Sambrisko * Device IDs and PCI 78265555Sambrisko */ 79265555Sambrisko#define MRSAS_TBOLT 0x005b 80265555Sambrisko#define MRSAS_INVADER 0x005d 81265555Sambrisko#define MRSAS_FURY 0x005f 82265555Sambrisko#define MRSAS_PCI_BAR0 0x10 83265555Sambrisko#define MRSAS_PCI_BAR1 0x14 84265555Sambrisko#define MRSAS_PCI_BAR2 0x1C 85265555Sambrisko 86265555Sambrisko/* 87265555Sambrisko * Firmware State Defines 88265555Sambrisko */ 89265555Sambrisko#define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 90265555Sambrisko#define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 91265555Sambrisko#define MRSAS_FW_STATE_CHNG_INTERRUPT 1 92265555Sambrisko 93265555Sambrisko/* 94265555Sambrisko * Message Frame Defines 95265555Sambrisko */ 96265555Sambrisko#define MRSAS_SENSE_LEN 96 97265555Sambrisko#define MRSAS_FUSION_MAX_RESET_TRIES 3 98265555Sambrisko 99265555Sambrisko/* 100265555Sambrisko * Miscellaneous Defines 101265555Sambrisko */ 102265555Sambrisko#define BYTE_ALIGNMENT 1 103265555Sambrisko#define MRSAS_MAX_NAME_LENGTH 32 104265555Sambrisko#define MRSAS_VERSION "06.704.01.00-fbsd" 105265555Sambrisko#define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 106265555Sambrisko#define MRSAS_DEFAULT_TIMEOUT 0x14 //temp 107265555Sambrisko#define DONE 0 108265555Sambrisko#define MRSAS_PAGE_SIZE 4096 109265555Sambrisko#define MRSAS_RESET_NOTICE_INTERVAL 5 110265555Sambrisko#define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 111265555Sambrisko#define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 112265555Sambrisko#define THRESHOLD_REPLY_COUNT 50 113265555Sambrisko 114265555Sambrisko/* 115265555Sambrisko Boolean types 116265555Sambrisko*/ 117265555Sambrisko#if (__FreeBSD_version < 901000) 118265555Sambrisko typedef enum _boolean { false, true } boolean; 119265555Sambrisko#endif 120265555Sambriskoenum err { SUCCESS, FAIL }; 121265555Sambrisko 122265555SambriskoMALLOC_DECLARE(M_MRSAS); 123265555SambriskoSYSCTL_DECL(_hw_mrsas); 124265555Sambrisko 125265555Sambrisko#define MRSAS_INFO (1 << 0) 126265555Sambrisko#define MRSAS_TRACE (1 << 1) 127265555Sambrisko#define MRSAS_FAULT (1 << 2) 128265555Sambrisko#define MRSAS_OCR (1 << 3) 129265555Sambrisko#define MRSAS_TOUT MRSAS_OCR 130265555Sambrisko#define MRSAS_AEN (1 << 4) 131265555Sambrisko#define MRSAS_PRL11 (1 << 5) 132265555Sambrisko 133265555Sambrisko#define mrsas_dprint(sc, level, msg, args...) \ 134265555Sambriskodo { \ 135265555Sambrisko if (sc->mrsas_debug & level) \ 136265555Sambrisko device_printf(sc->mrsas_dev, msg, ##args); \ 137265555Sambrisko} while (0) 138265555Sambrisko 139265555Sambrisko 140265555Sambrisko/**************************************************************************** 141265555Sambrisko * Raid Context structure which describes MegaRAID specific IO Paramenters 142265555Sambrisko * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 143265555Sambrisko ****************************************************************************/ 144265555Sambrisko 145265555Sambriskotypedef struct _RAID_CONTEXT { 146265555Sambrisko u_int8_t Type:4; // 0x00 147265555Sambrisko u_int8_t nseg:4; // 0x00 148265555Sambrisko u_int8_t resvd0; // 0x01 149265555Sambrisko u_int16_t timeoutValue; // 0x02 -0x03 150265555Sambrisko u_int8_t regLockFlags; // 0x04 151265555Sambrisko u_int8_t resvd1; // 0x05 152265555Sambrisko u_int16_t VirtualDiskTgtId; // 0x06 -0x07 153265555Sambrisko u_int64_t regLockRowLBA; // 0x08 - 0x0F 154265555Sambrisko u_int32_t regLockLength; // 0x10 - 0x13 155265555Sambrisko u_int16_t nextLMId; // 0x14 - 0x15 156265555Sambrisko u_int8_t exStatus; // 0x16 157265555Sambrisko u_int8_t status; // 0x17 status 158265555Sambrisko u_int8_t RAIDFlags; // 0x18 resvd[7:6],ioSubType[5:4],resvd[3:1],preferredCpu[0] 159265555Sambrisko u_int8_t numSGE; // 0x19 numSge; not including chain entries 160265555Sambrisko u_int16_t configSeqNum; // 0x1A -0x1B 161265555Sambrisko u_int8_t spanArm; // 0x1C span[7:5], arm[4:0] 162265555Sambrisko u_int8_t resvd2[3]; // 0x1D-0x1f 163265555Sambrisko} RAID_CONTEXT; 164265555Sambrisko 165265555Sambrisko 166265555Sambrisko/************************************************************************* 167265555Sambrisko * MPI2 Defines 168265555Sambrisko ************************************************************************/ 169265555Sambrisko 170265555Sambrisko#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 171265555Sambrisko#define MPI2_WHOINIT_HOST_DRIVER (0x04) 172265555Sambrisko#define MPI2_VERSION_MAJOR (0x02) 173265555Sambrisko#define MPI2_VERSION_MINOR (0x00) 174265555Sambrisko#define MPI2_VERSION_MAJOR_MASK (0xFF00) 175265555Sambrisko#define MPI2_VERSION_MAJOR_SHIFT (8) 176265555Sambrisko#define MPI2_VERSION_MINOR_MASK (0x00FF) 177265555Sambrisko#define MPI2_VERSION_MINOR_SHIFT (0) 178265555Sambrisko#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 179265555Sambrisko MPI2_VERSION_MINOR) 180265555Sambrisko#define MPI2_HEADER_VERSION_UNIT (0x10) 181265555Sambrisko#define MPI2_HEADER_VERSION_DEV (0x00) 182265555Sambrisko#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 183265555Sambrisko#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 184265555Sambrisko#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 185265555Sambrisko#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 186265555Sambrisko#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 187265555Sambrisko#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 188265555Sambrisko#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 189265555Sambrisko#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 190265555Sambrisko#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 191265555Sambrisko#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 192265555Sambrisko#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 193265555Sambrisko#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 194265555Sambrisko#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 195265555Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 196265555Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 197265555Sambrisko#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 198265555Sambrisko#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 199265555Sambrisko#define MPI2_SCSIIO_CONTROL_READ (0x02000000) 200265555Sambrisko#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 201265555Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 202265555Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 203265555Sambrisko#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 204265555Sambrisko#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 205265555Sambrisko#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 206265555Sambrisko#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 207265555Sambrisko#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 208265555Sambrisko#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 209265555Sambrisko#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 210265555Sambrisko#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 211265555Sambrisko#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 212265555Sambrisko 213265555Sambrisko#ifndef MPI2_POINTER 214265555Sambrisko#define MPI2_POINTER * 215265555Sambrisko#endif 216265555Sambrisko 217265555Sambrisko 218265555Sambrisko/*************************************** 219265555Sambrisko * MPI2 Structures 220265555Sambrisko ***************************************/ 221265555Sambrisko 222265555Sambriskotypedef struct _MPI25_IEEE_SGE_CHAIN64 223265555Sambrisko{ 224265555Sambrisko u_int64_t Address; 225265555Sambrisko u_int32_t Length; 226265555Sambrisko u_int16_t Reserved1; 227265555Sambrisko u_int8_t NextChainOffset; 228265555Sambrisko u_int8_t Flags; 229265555Sambrisko} MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 230265555Sambrisko Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 231265555Sambrisko 232265555Sambriskotypedef struct _MPI2_SGE_SIMPLE_UNION 233265555Sambrisko{ 234265555Sambrisko u_int32_t FlagsLength; 235265555Sambrisko union 236265555Sambrisko { 237265555Sambrisko u_int32_t Address32; 238265555Sambrisko u_int64_t Address64; 239265555Sambrisko } u; 240265555Sambrisko} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 241265555Sambrisko Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 242265555Sambrisko 243265555Sambriskotypedef struct 244265555Sambrisko{ 245265555Sambrisko u_int8_t CDB[20]; /* 0x00 */ 246265555Sambrisko u_int32_t PrimaryReferenceTag; /* 0x14 */ 247265555Sambrisko u_int16_t PrimaryApplicationTag; /* 0x18 */ 248265555Sambrisko u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 249265555Sambrisko u_int32_t TransferLength; /* 0x1C */ 250265555Sambrisko} MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 251265555Sambrisko Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 252265555Sambrisko 253265555Sambriskotypedef struct _MPI2_SGE_CHAIN_UNION 254265555Sambrisko{ 255265555Sambrisko u_int16_t Length; 256265555Sambrisko u_int8_t NextChainOffset; 257265555Sambrisko u_int8_t Flags; 258265555Sambrisko union 259265555Sambrisko { 260265555Sambrisko u_int32_t Address32; 261265555Sambrisko u_int64_t Address64; 262265555Sambrisko } u; 263265555Sambrisko} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 264265555Sambrisko Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 265265555Sambrisko 266265555Sambriskotypedef struct _MPI2_IEEE_SGE_SIMPLE32 267265555Sambrisko{ 268265555Sambrisko u_int32_t Address; 269265555Sambrisko u_int32_t FlagsLength; 270265555Sambrisko} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 271265555Sambrisko Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 272265555Sambriskotypedef struct _MPI2_IEEE_SGE_SIMPLE64 273265555Sambrisko{ 274265555Sambrisko u_int64_t Address; 275265555Sambrisko u_int32_t Length; 276265555Sambrisko u_int16_t Reserved1; 277265555Sambrisko u_int8_t Reserved2; 278265555Sambrisko u_int8_t Flags; 279265555Sambrisko} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 280265555Sambrisko Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 281265555Sambrisko 282265555Sambriskotypedef union _MPI2_IEEE_SGE_SIMPLE_UNION 283265555Sambrisko{ 284265555Sambrisko MPI2_IEEE_SGE_SIMPLE32 Simple32; 285265555Sambrisko MPI2_IEEE_SGE_SIMPLE64 Simple64; 286265555Sambrisko} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 287265555Sambrisko Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 288265555Sambrisko 289265555Sambriskotypedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 290265555Sambriskotypedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 291265555Sambrisko 292265555Sambriskotypedef union _MPI2_IEEE_SGE_CHAIN_UNION 293265555Sambrisko{ 294265555Sambrisko MPI2_IEEE_SGE_CHAIN32 Chain32; 295265555Sambrisko MPI2_IEEE_SGE_CHAIN64 Chain64; 296265555Sambrisko} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 297265555Sambrisko Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 298265555Sambrisko 299265555Sambriskotypedef union _MPI2_SGE_IO_UNION 300265555Sambrisko{ 301265555Sambrisko MPI2_SGE_SIMPLE_UNION MpiSimple; 302265555Sambrisko MPI2_SGE_CHAIN_UNION MpiChain; 303265555Sambrisko MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 304265555Sambrisko MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 305265555Sambrisko} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 306265555Sambrisko Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 307265555Sambrisko 308265555Sambriskotypedef union 309265555Sambrisko{ 310265555Sambrisko u_int8_t CDB32[32]; 311265555Sambrisko MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 312265555Sambrisko MPI2_SGE_SIMPLE_UNION SGE; 313265555Sambrisko} MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 314265555Sambrisko Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 315265555Sambrisko 316265555Sambrisko/* 317265555Sambrisko * RAID SCSI IO Request Message 318265555Sambrisko * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 319265555Sambrisko */ 320265555Sambriskotypedef struct _MPI2_RAID_SCSI_IO_REQUEST 321265555Sambrisko{ 322265555Sambrisko u_int16_t DevHandle; /* 0x00 */ 323265555Sambrisko u_int8_t ChainOffset; /* 0x02 */ 324265555Sambrisko u_int8_t Function; /* 0x03 */ 325265555Sambrisko u_int16_t Reserved1; /* 0x04 */ 326265555Sambrisko u_int8_t Reserved2; /* 0x06 */ 327265555Sambrisko u_int8_t MsgFlags; /* 0x07 */ 328265555Sambrisko u_int8_t VP_ID; /* 0x08 */ 329265555Sambrisko u_int8_t VF_ID; /* 0x09 */ 330265555Sambrisko u_int16_t Reserved3; /* 0x0A */ 331265555Sambrisko u_int32_t SenseBufferLowAddress; /* 0x0C */ 332265555Sambrisko u_int16_t SGLFlags; /* 0x10 */ 333265555Sambrisko u_int8_t SenseBufferLength; /* 0x12 */ 334265555Sambrisko u_int8_t Reserved4; /* 0x13 */ 335265555Sambrisko u_int8_t SGLOffset0; /* 0x14 */ 336265555Sambrisko u_int8_t SGLOffset1; /* 0x15 */ 337265555Sambrisko u_int8_t SGLOffset2; /* 0x16 */ 338265555Sambrisko u_int8_t SGLOffset3; /* 0x17 */ 339265555Sambrisko u_int32_t SkipCount; /* 0x18 */ 340265555Sambrisko u_int32_t DataLength; /* 0x1C */ 341265555Sambrisko u_int32_t BidirectionalDataLength; /* 0x20 */ 342265555Sambrisko u_int16_t IoFlags; /* 0x24 */ 343265555Sambrisko u_int16_t EEDPFlags; /* 0x26 */ 344265555Sambrisko u_int32_t EEDPBlockSize; /* 0x28 */ 345265555Sambrisko u_int32_t SecondaryReferenceTag; /* 0x2C */ 346265555Sambrisko u_int16_t SecondaryApplicationTag; /* 0x30 */ 347265555Sambrisko u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 348265555Sambrisko u_int8_t LUN[8]; /* 0x34 */ 349265555Sambrisko u_int32_t Control; /* 0x3C */ 350265555Sambrisko MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 351265555Sambrisko RAID_CONTEXT RaidContext; /* 0x60 */ 352265555Sambrisko MPI2_SGE_IO_UNION SGL; /* 0x80 */ 353265555Sambrisko} MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 354265555Sambrisko MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 355265555Sambrisko 356265555Sambrisko/* 357265555Sambrisko * MPT RAID MFA IO Descriptor. 358265555Sambrisko */ 359265555Sambriskotypedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 360265555Sambrisko u_int32_t RequestFlags : 8; 361265555Sambrisko u_int32_t MessageAddress1 : 24; /* bits 31:8*/ 362265555Sambrisko u_int32_t MessageAddress2; /* bits 61:32 */ 363265555Sambrisko} MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR,*PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 364265555Sambrisko 365265555Sambrisko/* Default Request Descriptor */ 366265555Sambriskotypedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 367265555Sambrisko{ 368265555Sambrisko u_int8_t RequestFlags; /* 0x00 */ 369265555Sambrisko u_int8_t MSIxIndex; /* 0x01 */ 370265555Sambrisko u_int16_t SMID; /* 0x02 */ 371265555Sambrisko u_int16_t LMID; /* 0x04 */ 372265555Sambrisko u_int16_t DescriptorTypeDependent; /* 0x06 */ 373265555Sambrisko} MPI2_DEFAULT_REQUEST_DESCRIPTOR, 374265555Sambrisko MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 375265555Sambrisko Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 376265555Sambrisko 377265555Sambrisko/* High Priority Request Descriptor */ 378265555Sambriskotypedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 379265555Sambrisko{ 380265555Sambrisko u_int8_t RequestFlags; /* 0x00 */ 381265555Sambrisko u_int8_t MSIxIndex; /* 0x01 */ 382265555Sambrisko u_int16_t SMID; /* 0x02 */ 383265555Sambrisko u_int16_t LMID; /* 0x04 */ 384265555Sambrisko u_int16_t Reserved1; /* 0x06 */ 385265555Sambrisko} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 386265555Sambrisko MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 387265555Sambrisko Mpi2HighPriorityRequestDescriptor_t, 388265555Sambrisko MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 389265555Sambrisko 390265555Sambrisko/* SCSI IO Request Descriptor */ 391265555Sambriskotypedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 392265555Sambrisko{ 393265555Sambrisko u_int8_t RequestFlags; /* 0x00 */ 394265555Sambrisko u_int8_t MSIxIndex; /* 0x01 */ 395265555Sambrisko u_int16_t SMID; /* 0x02 */ 396265555Sambrisko u_int16_t LMID; /* 0x04 */ 397265555Sambrisko u_int16_t DevHandle; /* 0x06 */ 398265555Sambrisko} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 399265555Sambrisko MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 400265555Sambrisko Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 401265555Sambrisko 402265555Sambrisko/* SCSI Target Request Descriptor */ 403265555Sambriskotypedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 404265555Sambrisko{ 405265555Sambrisko u_int8_t RequestFlags; /* 0x00 */ 406265555Sambrisko u_int8_t MSIxIndex; /* 0x01 */ 407265555Sambrisko u_int16_t SMID; /* 0x02 */ 408265555Sambrisko u_int16_t LMID; /* 0x04 */ 409265555Sambrisko u_int16_t IoIndex; /* 0x06 */ 410265555Sambrisko} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 411265555Sambrisko MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 412265555Sambrisko Mpi2SCSITargetRequestDescriptor_t, 413265555Sambrisko MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 414265555Sambrisko 415265555Sambrisko/* RAID Accelerator Request Descriptor */ 416265555Sambriskotypedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 417265555Sambrisko{ 418265555Sambrisko u_int8_t RequestFlags; /* 0x00 */ 419265555Sambrisko u_int8_t MSIxIndex; /* 0x01 */ 420265555Sambrisko u_int16_t SMID; /* 0x02 */ 421265555Sambrisko u_int16_t LMID; /* 0x04 */ 422265555Sambrisko u_int16_t Reserved; /* 0x06 */ 423265555Sambrisko} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 424265555Sambrisko MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 425265555Sambrisko Mpi2RAIDAcceleratorRequestDescriptor_t, 426265555Sambrisko MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 427265555Sambrisko 428265555Sambrisko/* union of Request Descriptors */ 429265555Sambriskotypedef union _MRSAS_REQUEST_DESCRIPTOR_UNION 430265555Sambrisko{ 431265555Sambrisko MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 432265555Sambrisko MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 433265555Sambrisko MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 434265555Sambrisko MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 435265555Sambrisko MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 436265555Sambrisko MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 437265555Sambrisko union { 438265555Sambrisko struct { 439265555Sambrisko u_int32_t low; 440265555Sambrisko u_int32_t high; 441265555Sambrisko } u; 442265555Sambrisko u_int64_t Words; 443265555Sambrisko } addr; 444265555Sambrisko} MRSAS_REQUEST_DESCRIPTOR_UNION; 445265555Sambrisko 446265555Sambrisko/* Default Reply Descriptor */ 447265555Sambriskotypedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 448265555Sambrisko{ 449265555Sambrisko u_int8_t ReplyFlags; /* 0x00 */ 450265555Sambrisko u_int8_t MSIxIndex; /* 0x01 */ 451265555Sambrisko u_int16_t DescriptorTypeDependent1; /* 0x02 */ 452265555Sambrisko u_int32_t DescriptorTypeDependent2; /* 0x04 */ 453265555Sambrisko} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 454265555Sambrisko Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 455265555Sambrisko 456265555Sambrisko/* Address Reply Descriptor */ 457265555Sambriskotypedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 458265555Sambrisko{ 459265555Sambrisko u_int8_t ReplyFlags; /* 0x00 */ 460265555Sambrisko u_int8_t MSIxIndex; /* 0x01 */ 461265555Sambrisko u_int16_t SMID; /* 0x02 */ 462265555Sambrisko u_int32_t ReplyFrameAddress; /* 0x04 */ 463265555Sambrisko} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 464265555Sambrisko Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 465265555Sambrisko 466265555Sambrisko/* SCSI IO Success Reply Descriptor */ 467265555Sambriskotypedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 468265555Sambrisko{ 469265555Sambrisko u_int8_t ReplyFlags; /* 0x00 */ 470265555Sambrisko u_int8_t MSIxIndex; /* 0x01 */ 471265555Sambrisko u_int16_t SMID; /* 0x02 */ 472265555Sambrisko u_int16_t TaskTag; /* 0x04 */ 473265555Sambrisko u_int16_t Reserved1; /* 0x06 */ 474265555Sambrisko} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 475265555Sambrisko MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 476265555Sambrisko Mpi2SCSIIOSuccessReplyDescriptor_t, 477265555Sambrisko MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 478265555Sambrisko 479265555Sambrisko/* TargetAssist Success Reply Descriptor */ 480265555Sambriskotypedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 481265555Sambrisko{ 482265555Sambrisko u_int8_t ReplyFlags; /* 0x00 */ 483265555Sambrisko u_int8_t MSIxIndex; /* 0x01 */ 484265555Sambrisko u_int16_t SMID; /* 0x02 */ 485265555Sambrisko u_int8_t SequenceNumber; /* 0x04 */ 486265555Sambrisko u_int8_t Reserved1; /* 0x05 */ 487265555Sambrisko u_int16_t IoIndex; /* 0x06 */ 488265555Sambrisko} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 489265555Sambrisko MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 490265555Sambrisko Mpi2TargetAssistSuccessReplyDescriptor_t, 491265555Sambrisko MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 492265555Sambrisko 493265555Sambrisko/* Target Command Buffer Reply Descriptor */ 494265555Sambriskotypedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 495265555Sambrisko{ 496265555Sambrisko u_int8_t ReplyFlags; /* 0x00 */ 497265555Sambrisko u_int8_t MSIxIndex; /* 0x01 */ 498265555Sambrisko u_int8_t VP_ID; /* 0x02 */ 499265555Sambrisko u_int8_t Flags; /* 0x03 */ 500265555Sambrisko u_int16_t InitiatorDevHandle; /* 0x04 */ 501265555Sambrisko u_int16_t IoIndex; /* 0x06 */ 502265555Sambrisko} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 503265555Sambrisko MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 504265555Sambrisko Mpi2TargetCommandBufferReplyDescriptor_t, 505265555Sambrisko MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 506265555Sambrisko 507265555Sambrisko/* RAID Accelerator Success Reply Descriptor */ 508265555Sambriskotypedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 509265555Sambrisko{ 510265555Sambrisko u_int8_t ReplyFlags; /* 0x00 */ 511265555Sambrisko u_int8_t MSIxIndex; /* 0x01 */ 512265555Sambrisko u_int16_t SMID; /* 0x02 */ 513265555Sambrisko u_int32_t Reserved; /* 0x04 */ 514265555Sambrisko} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 515265555Sambrisko MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 516265555Sambrisko Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 517265555Sambrisko MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 518265555Sambrisko 519265555Sambrisko/* union of Reply Descriptors */ 520265555Sambriskotypedef union _MPI2_REPLY_DESCRIPTORS_UNION 521265555Sambrisko{ 522265555Sambrisko MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 523265555Sambrisko MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 524265555Sambrisko MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 525265555Sambrisko MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 526265555Sambrisko MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 527265555Sambrisko MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 528265555Sambrisko u_int64_t Words; 529265555Sambrisko} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 530265555Sambrisko Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 531265555Sambrisko 532265555Sambriskotypedef struct { 533265555Sambrisko volatile unsigned int val; 534265555Sambrisko} atomic_t; 535265555Sambrisko 536265555Sambrisko#define atomic_read(v) atomic_load_acq_int(&(v)->val) 537265555Sambrisko#define atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 538265555Sambrisko#define atomic_dec(v) atomic_fetchadd_int(&(v)->val, -1) 539265555Sambrisko#define atomic_inc(v) atomic_fetchadd_int(&(v)->val, 1) 540265555Sambrisko 541265555Sambrisko/* IOCInit Request message */ 542265555Sambriskotypedef struct _MPI2_IOC_INIT_REQUEST 543265555Sambrisko{ 544265555Sambrisko u_int8_t WhoInit; /* 0x00 */ 545265555Sambrisko u_int8_t Reserved1; /* 0x01 */ 546265555Sambrisko u_int8_t ChainOffset; /* 0x02 */ 547265555Sambrisko u_int8_t Function; /* 0x03 */ 548265555Sambrisko u_int16_t Reserved2; /* 0x04 */ 549265555Sambrisko u_int8_t Reserved3; /* 0x06 */ 550265555Sambrisko u_int8_t MsgFlags; /* 0x07 */ 551265555Sambrisko u_int8_t VP_ID; /* 0x08 */ 552265555Sambrisko u_int8_t VF_ID; /* 0x09 */ 553265555Sambrisko u_int16_t Reserved4; /* 0x0A */ 554265555Sambrisko u_int16_t MsgVersion; /* 0x0C */ 555265555Sambrisko u_int16_t HeaderVersion; /* 0x0E */ 556265555Sambrisko u_int32_t Reserved5; /* 0x10 */ 557265555Sambrisko u_int16_t Reserved6; /* 0x14 */ 558265555Sambrisko u_int8_t Reserved7; /* 0x16 */ 559265555Sambrisko u_int8_t HostMSIxVectors; /* 0x17 */ 560265555Sambrisko u_int16_t Reserved8; /* 0x18 */ 561265555Sambrisko u_int16_t SystemRequestFrameSize; /* 0x1A */ 562265555Sambrisko u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 563265555Sambrisko u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 564265555Sambrisko u_int32_t SenseBufferAddressHigh; /* 0x20 */ 565265555Sambrisko u_int32_t SystemReplyAddressHigh; /* 0x24 */ 566265555Sambrisko u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 567265555Sambrisko u_int64_t ReplyDescriptorPostQueueAddress;/* 0x30 */ 568265555Sambrisko u_int64_t ReplyFreeQueueAddress; /* 0x38 */ 569265555Sambrisko u_int64_t TimeStamp; /* 0x40 */ 570265555Sambrisko} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 571265555Sambrisko Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 572265555Sambrisko 573265555Sambrisko/* 574265555Sambrisko * MR private defines 575265555Sambrisko */ 576265555Sambrisko#define MR_PD_INVALID 0xFFFF 577265555Sambrisko#define MAX_SPAN_DEPTH 8 578265555Sambrisko#define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 579265555Sambrisko#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 580265555Sambrisko#define MAX_ROW_SIZE 32 581265555Sambrisko#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 582265555Sambrisko#define MAX_LOGICAL_DRIVES 64 583265555Sambrisko#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 584265555Sambrisko#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 585265555Sambrisko#define MAX_ARRAYS 128 586265555Sambrisko#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 587265555Sambrisko#define MAX_PHYSICAL_DEVICES 256 588265555Sambrisko#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 589265555Sambrisko#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 // get the mapping information of this LD 590265555Sambrisko 591265555Sambrisko 592265555Sambrisko/******************************************************************* 593265555Sambrisko * RAID map related structures 594265555Sambrisko ********************************************************************/ 595265555Sambrisko 596265555Sambriskotypedef struct _MR_DEV_HANDLE_INFO { 597265555Sambrisko u_int16_t curDevHdl; // the device handle currently used by fw to issue the command. 598265555Sambrisko u_int8_t validHandles; // bitmap of valid device handles. 599265555Sambrisko u_int8_t reserved; 600265555Sambrisko u_int16_t devHandle[2]; // 0x04 dev handles for all the paths. 601265555Sambrisko} MR_DEV_HANDLE_INFO; 602265555Sambrisko 603265555Sambriskotypedef struct _MR_ARRAY_INFO { 604265555Sambrisko u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 605265555Sambrisko} MR_ARRAY_INFO; // 0x40, Total Size 606265555Sambrisko 607265555Sambriskotypedef struct _MR_QUAD_ELEMENT { 608265555Sambrisko u_int64_t logStart; // 0x00 609265555Sambrisko u_int64_t logEnd; // 0x08 610265555Sambrisko u_int64_t offsetInSpan; // 0x10 611265555Sambrisko u_int32_t diff; // 0x18 612265555Sambrisko u_int32_t reserved1; // 0x1C 613265555Sambrisko} MR_QUAD_ELEMENT; // 0x20, Total size 614265555Sambrisko 615265555Sambriskotypedef struct _MR_SPAN_INFO { 616265555Sambrisko u_int32_t noElements; // 0x00 617265555Sambrisko u_int32_t reserved1; // 0x04 618265555Sambrisko MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; // 0x08 619265555Sambrisko} MR_SPAN_INFO; // 0x108, Total size 620265555Sambrisko 621265555Sambriskotypedef struct _MR_LD_SPAN_ { // SPAN structure 622265555Sambrisko u_int64_t startBlk; // 0x00, starting block number in array 623265555Sambrisko u_int64_t numBlks; // 0x08, number of blocks 624265555Sambrisko u_int16_t arrayRef; // 0x10, array reference 625265555Sambrisko u_int8_t spanRowSize; // 0x11, span row size 626265555Sambrisko u_int8_t spanRowDataSize; // 0x12, span row data size 627265555Sambrisko u_int8_t reserved[4]; // 0x13, reserved 628265555Sambrisko} MR_LD_SPAN; // 0x18, Total Size 629265555Sambrisko 630265555Sambriskotypedef struct _MR_SPAN_BLOCK_INFO { 631265555Sambrisko u_int64_t num_rows; // number of rows/span 632265555Sambrisko MR_LD_SPAN span; // 0x08 633265555Sambrisko MR_SPAN_INFO block_span_info; // 0x20 634265555Sambrisko} MR_SPAN_BLOCK_INFO; 635265555Sambrisko 636265555Sambriskotypedef struct _MR_LD_RAID { 637265555Sambrisko struct { 638265555Sambrisko u_int32_t fpCapable :1; 639265555Sambrisko u_int32_t reserved5 :3; 640265555Sambrisko u_int32_t ldPiMode :4; 641265555Sambrisko u_int32_t pdPiMode :4; // Every Pd has to be same. 642265555Sambrisko u_int32_t encryptionType :8; // FDE or ctlr encryption (MR_LD_ENCRYPTION_TYPE) 643265555Sambrisko u_int32_t fpWriteCapable :1; 644265555Sambrisko u_int32_t fpReadCapable :1; 645265555Sambrisko u_int32_t fpWriteAcrossStripe :1; 646265555Sambrisko u_int32_t fpReadAcrossStripe :1; 647265555Sambrisko u_int32_t fpNonRWCapable :1; // TRUE if supporting Non RW IO 648265555Sambrisko u_int32_t reserved4 :7; 649265555Sambrisko } capability; // 0x00 650265555Sambrisko u_int32_t reserved6; 651265555Sambrisko u_int64_t size; // 0x08, LD size in blocks 652265555Sambrisko 653265555Sambrisko u_int8_t spanDepth; // 0x10, Total Number of Spans 654265555Sambrisko u_int8_t level; // 0x11, RAID level 655265555Sambrisko u_int8_t stripeShift; // 0x12, shift-count to get stripe size (0=512, 1=1K, 7=64K, etc.) 656265555Sambrisko u_int8_t rowSize; // 0x13, number of disks in a row 657265555Sambrisko 658265555Sambrisko u_int8_t rowDataSize; // 0x14, number of data disks in a row 659265555Sambrisko u_int8_t writeMode; // 0x15, WRITE_THROUGH or WRITE_BACK 660265555Sambrisko u_int8_t PRL; // 0x16, To differentiate between RAID1 and RAID1E 661265555Sambrisko u_int8_t SRL; // 0x17 662265555Sambrisko 663265555Sambrisko u_int16_t targetId; // 0x18, ld Target Id. 664265555Sambrisko u_int8_t ldState; // 0x1a, state of ld, state corresponds to MR_LD_STATE 665265555Sambrisko u_int8_t regTypeReqOnWrite;// 0x1b, Pre calculate region type requests based on MFC etc.. 666265555Sambrisko u_int8_t modFactor; // 0x1c, same as rowSize, 667265555Sambrisko u_int8_t regTypeReqOnRead; // 0x1d, region lock type used for read, valid only if regTypeOnReadIsValid=1 668265555Sambrisko u_int16_t seqNum; // 0x1e, LD sequence number 669265555Sambrisko 670265555Sambrisko struct { 671265555Sambrisko u_int32_t ldSyncRequired:1; // This LD requires sync command before completing 672265555Sambrisko u_int32_t regTypeReqOnReadLsValid:1; // Qualifier for regTypeOnRead 673265555Sambrisko u_int32_t reserved:30; 674265555Sambrisko } flags; // 0x20 675265555Sambrisko 676265555Sambrisko u_int8_t LUN[8]; // 0x24, 8 byte LUN field used for SCSI 677265555Sambrisko u_int8_t fpIoTimeoutForLd; // 0x2C, timeout value for FP IOs 678265555Sambrisko u_int8_t reserved2[3]; // 0x2D 679265555Sambrisko u_int32_t logicalBlockLength; // 0x30 Logical block size for the LD 680265555Sambrisko struct { 681265555Sambrisko u_int32_t LdPiExp:4; // 0x34, P_I_EXPONENT for ReadCap 16 682265555Sambrisko u_int32_t LdLogicalBlockExp:4; // 0x34, LOGICAL BLOCKS PER PHYS BLOCK 683265555Sambrisko u_int32_t reserved1:24; // 0x34 684265555Sambrisko } exponent; 685265555Sambrisko u_int8_t reserved3[0x80-0x38]; // 0x38 686265555Sambrisko} MR_LD_RAID; // 0x80, Total Size 687265555Sambrisko 688265555Sambriskotypedef struct _MR_LD_SPAN_MAP { 689265555Sambrisko MR_LD_RAID ldRaid; // 0x00 690265555Sambrisko u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; // 0x80, needed for GET_ARM() - R0/1/5 only. 691265555Sambrisko MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; // 0xA0 692265555Sambrisko} MR_LD_SPAN_MAP; // 0x9E0 693265555Sambrisko 694265555Sambriskotypedef struct _MR_FW_RAID_MAP { 695265555Sambrisko u_int32_t totalSize; // total size of this structure, including this field. 696265555Sambrisko union { 697265555Sambrisko struct { // Simple method of version checking variables 698265555Sambrisko u_int32_t maxLd; 699265555Sambrisko u_int32_t maxSpanDepth; 700265555Sambrisko u_int32_t maxRowSize; 701265555Sambrisko u_int32_t maxPdCount; 702265555Sambrisko u_int32_t maxArrays; 703265555Sambrisko } validationInfo; 704265555Sambrisko u_int32_t version[5]; 705265555Sambrisko u_int32_t reserved1[5]; 706265555Sambrisko } raid_desc; 707265555Sambrisko u_int32_t ldCount; // count of lds. 708265555Sambrisko u_int32_t Reserved1; 709265555Sambrisko u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS]; // 0x20 710265555Sambrisko // This doesn't correspond to 711265555Sambrisko // FW Ld Tgt Id to LD, but will purge. For example: if tgt Id is 4 712265555Sambrisko // and FW LD is 2, and there is only one LD, FW will populate the 713265555Sambrisko // array like this. [0xFF, 0xFF, 0xFF, 0xFF, 0x0,.....]. This is to 714265555Sambrisko // help reduce the entire strcture size if there are few LDs or 715265555Sambrisko // driver is looking info for 1 LD only. 716265555Sambrisko u_int8_t fpPdIoTimeoutSec; // timeout value used by driver in FP IOs 717265555Sambrisko u_int8_t reserved2[7]; 718265555Sambrisko MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; // 0x00a8 719265555Sambrisko MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; // 0x20a8 720265555Sambrisko MR_LD_SPAN_MAP ldSpanMap[1]; // 0x28a8-[0-MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS+1]; 721265555Sambrisko} MR_FW_RAID_MAP; // 0x3288, Total Size 722265555Sambrisko 723265555Sambriskotypedef struct _LD_LOAD_BALANCE_INFO 724265555Sambrisko{ 725265555Sambrisko u_int8_t loadBalanceFlag; 726265555Sambrisko u_int8_t reserved1; 727265555Sambrisko u_int16_t raid1DevHandle[2]; 728265555Sambrisko atomic_t scsi_pending_cmds[2]; 729265555Sambrisko u_int64_t last_accessed_block[2]; 730265555Sambrisko} LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 731265555Sambrisko 732265555Sambrisko/* SPAN_SET is info caclulated from span info from Raid map per ld */ 733265555Sambriskotypedef struct _LD_SPAN_SET { 734265555Sambrisko u_int64_t log_start_lba; 735265555Sambrisko u_int64_t log_end_lba; 736265555Sambrisko u_int64_t span_row_start; 737265555Sambrisko u_int64_t span_row_end; 738265555Sambrisko u_int64_t data_strip_start; 739265555Sambrisko u_int64_t data_strip_end; 740265555Sambrisko u_int64_t data_row_start; 741265555Sambrisko u_int64_t data_row_end; 742265555Sambrisko u_int8_t strip_offset[MAX_SPAN_DEPTH]; 743265555Sambrisko u_int32_t span_row_data_width; 744265555Sambrisko u_int32_t diff; 745265555Sambrisko u_int32_t reserved[2]; 746265555Sambrisko}LD_SPAN_SET, *PLD_SPAN_SET; 747265555Sambrisko 748265555Sambriskotypedef struct LOG_BLOCK_SPAN_INFO { 749265555Sambrisko LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 750265555Sambrisko}LD_SPAN_INFO, *PLD_SPAN_INFO; 751265555Sambrisko 752265555Sambrisko#pragma pack(1) 753265555Sambriskotypedef struct _MR_FW_RAID_MAP_ALL { 754265555Sambrisko MR_FW_RAID_MAP raidMap; 755265555Sambrisko MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 756265555Sambrisko} MR_FW_RAID_MAP_ALL; 757265555Sambrisko#pragma pack() 758265555Sambrisko 759265555Sambriskostruct IO_REQUEST_INFO { 760265555Sambrisko u_int64_t ldStartBlock; 761265555Sambrisko u_int32_t numBlocks; 762265555Sambrisko u_int16_t ldTgtId; 763265555Sambrisko u_int8_t isRead; 764265555Sambrisko u_int16_t devHandle; 765265555Sambrisko u_int64_t pdBlock; 766265555Sambrisko u_int8_t fpOkForIo; 767265555Sambrisko u_int8_t IoforUnevenSpan; 768265555Sambrisko u_int8_t start_span; 769265555Sambrisko u_int8_t reserved; 770265555Sambrisko u_int64_t start_row; 771265555Sambrisko}; 772265555Sambrisko 773265555Sambriskotypedef struct _MR_LD_TARGET_SYNC { 774265555Sambrisko u_int8_t targetId; 775265555Sambrisko u_int8_t reserved; 776265555Sambrisko u_int16_t seqNum; 777265555Sambrisko} MR_LD_TARGET_SYNC; 778265555Sambrisko 779265555Sambrisko#define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 780265555Sambrisko#define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 781265555Sambrisko#define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 782265555Sambrisko#define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 783265555Sambrisko#define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 784265555Sambrisko#define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 785265555Sambrisko#define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 786265555Sambrisko 787265555Sambriskounion desc_value { 788265555Sambrisko u_int64_t word; 789265555Sambrisko struct { 790265555Sambrisko u_int32_t low; 791265555Sambrisko u_int32_t high; 792265555Sambrisko } u; 793265555Sambrisko}; 794265555Sambrisko 795265555Sambrisko/******************************************************************* 796265555Sambrisko * Temporary command 797265555Sambrisko ********************************************************************/ 798265555Sambriskostruct mrsas_tmp_dcmd { 799265555Sambrisko bus_dma_tag_t tmp_dcmd_tag; // tag for tmp DMCD cmd 800265555Sambrisko bus_dmamap_t tmp_dcmd_dmamap; // dmamap for tmp DCMD cmd 801265555Sambrisko void *tmp_dcmd_mem; // virtual addr of tmp DCMD cmd 802265555Sambrisko bus_addr_t tmp_dcmd_phys_addr; //physical addr of tmp DCMD 803265555Sambrisko}; 804265555Sambrisko 805265555Sambrisko/******************************************************************* 806265555Sambrisko * Register set, included legacy controllers 1068 and 1078, 807265555Sambrisko * structure extended for 1078 registers 808265555Sambrisko ********************************************************************/ 809265555Sambrisko#pragma pack(1) 810265555Sambriskotypedef struct _mrsas_register_set { 811265555Sambrisko u_int32_t doorbell; /*0000h*/ 812265555Sambrisko u_int32_t fusion_seq_offset; /*0004h*/ 813265555Sambrisko u_int32_t fusion_host_diag; /*0008h*/ 814265555Sambrisko u_int32_t reserved_01; /*000Ch*/ 815265555Sambrisko 816265555Sambrisko u_int32_t inbound_msg_0; /*0010h*/ 817265555Sambrisko u_int32_t inbound_msg_1; /*0014h*/ 818265555Sambrisko u_int32_t outbound_msg_0; /*0018h*/ 819265555Sambrisko u_int32_t outbound_msg_1; /*001Ch*/ 820265555Sambrisko 821265555Sambrisko u_int32_t inbound_doorbell; /*0020h*/ 822265555Sambrisko u_int32_t inbound_intr_status; /*0024h*/ 823265555Sambrisko u_int32_t inbound_intr_mask; /*0028h*/ 824265555Sambrisko 825265555Sambrisko u_int32_t outbound_doorbell; /*002Ch*/ 826265555Sambrisko u_int32_t outbound_intr_status; /*0030h*/ 827265555Sambrisko u_int32_t outbound_intr_mask; /*0034h*/ 828265555Sambrisko 829265555Sambrisko u_int32_t reserved_1[2]; /*0038h*/ 830265555Sambrisko 831265555Sambrisko u_int32_t inbound_queue_port; /*0040h*/ 832265555Sambrisko u_int32_t outbound_queue_port; /*0044h*/ 833265555Sambrisko 834265555Sambrisko u_int32_t reserved_2[9]; /*0048h*/ 835265555Sambrisko u_int32_t reply_post_host_index; /*006Ch*/ 836265555Sambrisko u_int32_t reserved_2_2[12]; /*0070h*/ 837265555Sambrisko 838265555Sambrisko u_int32_t outbound_doorbell_clear; /*00A0h*/ 839265555Sambrisko 840265555Sambrisko u_int32_t reserved_3[3]; /*00A4h*/ 841265555Sambrisko 842265555Sambrisko u_int32_t outbound_scratch_pad ; /*00B0h*/ 843265555Sambrisko u_int32_t outbound_scratch_pad_2; /*00B4h*/ 844265555Sambrisko 845265555Sambrisko u_int32_t reserved_4[2]; /*00B8h*/ 846265555Sambrisko 847265555Sambrisko u_int32_t inbound_low_queue_port ; /*00C0h*/ 848265555Sambrisko 849265555Sambrisko u_int32_t inbound_high_queue_port ; /*00C4h*/ 850265555Sambrisko 851265555Sambrisko u_int32_t reserved_5; /*00C8h*/ 852265555Sambrisko u_int32_t res_6[11]; /*CCh*/ 853265555Sambrisko u_int32_t host_diag; 854265555Sambrisko u_int32_t seq_offset; 855265555Sambrisko u_int32_t index_registers[807]; /*00CCh*/ 856265555Sambrisko 857265555Sambrisko} mrsas_reg_set; 858265555Sambrisko#pragma pack() 859265555Sambrisko 860265555Sambrisko/******************************************************************* 861265555Sambrisko * Firmware Interface Defines 862265555Sambrisko ******************************************************************* 863265555Sambrisko * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 864265555Sambrisko * for protocol between the software and firmware. Commands are 865265555Sambrisko * issued using "message frames". 866265555Sambrisko ******************************************************************/ 867265555Sambrisko/* 868265555Sambrisko * FW posts its state in upper 4 bits of outbound_msg_0 register 869265555Sambrisko */ 870265555Sambrisko#define MFI_STATE_MASK 0xF0000000 871265555Sambrisko#define MFI_STATE_UNDEFINED 0x00000000 872265555Sambrisko#define MFI_STATE_BB_INIT 0x10000000 873265555Sambrisko#define MFI_STATE_FW_INIT 0x40000000 874265555Sambrisko#define MFI_STATE_WAIT_HANDSHAKE 0x60000000 875265555Sambrisko#define MFI_STATE_FW_INIT_2 0x70000000 876265555Sambrisko#define MFI_STATE_DEVICE_SCAN 0x80000000 877265555Sambrisko#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 878265555Sambrisko#define MFI_STATE_FLUSH_CACHE 0xA0000000 879265555Sambrisko#define MFI_STATE_READY 0xB0000000 880265555Sambrisko#define MFI_STATE_OPERATIONAL 0xC0000000 881265555Sambrisko#define MFI_STATE_FAULT 0xF0000000 882265555Sambrisko#define MFI_RESET_REQUIRED 0x00000001 883265555Sambrisko#define MFI_RESET_ADAPTER 0x00000002 884265555Sambrisko#define MEGAMFI_FRAME_SIZE 64 885265555Sambrisko#define MRSAS_MFI_FRAME_SIZE 1024 886265555Sambrisko#define MRSAS_MFI_SENSE_SIZE 128 887265555Sambrisko 888265555Sambrisko/* 889265555Sambrisko * During FW init, clear pending cmds & reset state using inbound_msg_0 890265555Sambrisko * 891265555Sambrisko * ABORT : Abort all pending cmds 892265555Sambrisko * READY : Move from OPERATIONAL to READY state; discard queue info 893265555Sambrisko * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 894265555Sambrisko * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 895265555Sambrisko * HOTPLUG : Resume from Hotplug 896265555Sambrisko * MFI_STOP_ADP : Send signal to FW to stop processing 897265555Sambrisko */ 898265555Sambrisko 899265555Sambrisko#define WRITE_SEQUENCE_OFFSET (0x0000000FC) // I20 900265555Sambrisko#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) // I20 901265555Sambrisko#define DIAG_WRITE_ENABLE (0x00000080) 902265555Sambrisko#define DIAG_RESET_ADAPTER (0x00000004) 903265555Sambrisko 904265555Sambrisko#define MFI_ADP_RESET 0x00000040 905265555Sambrisko#define MFI_INIT_ABORT 0x00000001 906265555Sambrisko#define MFI_INIT_READY 0x00000002 907265555Sambrisko#define MFI_INIT_MFIMODE 0x00000004 908265555Sambrisko#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 909265555Sambrisko#define MFI_INIT_HOTPLUG 0x00000010 910265555Sambrisko#define MFI_STOP_ADP 0x00000020 911265555Sambrisko#define MFI_RESET_FLAGS MFI_INIT_READY| \ 912265555Sambrisko MFI_INIT_MFIMODE| \ 913265555Sambrisko MFI_INIT_ABORT 914265555Sambrisko 915265555Sambrisko/* 916265555Sambrisko * MFI frame flags 917265555Sambrisko */ 918265555Sambrisko#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 919265555Sambrisko#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 920265555Sambrisko#define MFI_FRAME_SGL32 0x0000 921265555Sambrisko#define MFI_FRAME_SGL64 0x0002 922265555Sambrisko#define MFI_FRAME_SENSE32 0x0000 923265555Sambrisko#define MFI_FRAME_SENSE64 0x0004 924265555Sambrisko#define MFI_FRAME_DIR_NONE 0x0000 925265555Sambrisko#define MFI_FRAME_DIR_WRITE 0x0008 926265555Sambrisko#define MFI_FRAME_DIR_READ 0x0010 927265555Sambrisko#define MFI_FRAME_DIR_BOTH 0x0018 928265555Sambrisko#define MFI_FRAME_IEEE 0x0020 929265555Sambrisko 930265555Sambrisko/* 931265555Sambrisko * Definition for cmd_status 932265555Sambrisko */ 933265555Sambrisko#define MFI_CMD_STATUS_POLL_MODE 0xFF 934265555Sambrisko 935265555Sambrisko/* 936265555Sambrisko * MFI command opcodes 937265555Sambrisko */ 938265555Sambrisko#define MFI_CMD_INIT 0x00 939265555Sambrisko#define MFI_CMD_LD_READ 0x01 940265555Sambrisko#define MFI_CMD_LD_WRITE 0x02 941265555Sambrisko#define MFI_CMD_LD_SCSI_IO 0x03 942265555Sambrisko#define MFI_CMD_PD_SCSI_IO 0x04 943265555Sambrisko#define MFI_CMD_DCMD 0x05 944265555Sambrisko#define MFI_CMD_ABORT 0x06 945265555Sambrisko#define MFI_CMD_SMP 0x07 946265555Sambrisko#define MFI_CMD_STP 0x08 947265555Sambrisko#define MFI_CMD_INVALID 0xff 948265555Sambrisko 949265555Sambrisko#define MR_DCMD_CTRL_GET_INFO 0x01010000 950265555Sambrisko#define MR_DCMD_LD_GET_LIST 0x03010000 951265555Sambrisko#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 952265555Sambrisko#define MR_FLUSH_CTRL_CACHE 0x01 953265555Sambrisko#define MR_FLUSH_DISK_CACHE 0x02 954265555Sambrisko 955265555Sambrisko#define MR_DCMD_CTRL_SHUTDOWN 0x01050000 956265555Sambrisko#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 957265555Sambrisko#define MR_ENABLE_DRIVE_SPINDOWN 0x01 958265555Sambrisko 959265555Sambrisko#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 960265555Sambrisko#define MR_DCMD_CTRL_EVENT_GET 0x01040300 961265555Sambrisko#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 962265555Sambrisko#define MR_DCMD_LD_GET_PROPERTIES 0x03030000 963265555Sambrisko 964265555Sambrisko#define MR_DCMD_CLUSTER 0x08000000 965265555Sambrisko#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 966265555Sambrisko#define MR_DCMD_CLUSTER_RESET_LD 0x08010200 967265555Sambrisko#define MR_DCMD_PD_LIST_QUERY 0x02010100 968265555Sambrisko 969265555Sambrisko#define MR_DCMD_CTRL_MISC_CPX 0x0100e200 970265555Sambrisko#define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 971265555Sambrisko#define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 972265555Sambrisko#define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 973265555Sambrisko#define MAX_MR_ROW_SIZE 32 974265555Sambrisko#define MR_CPX_DIR_WRITE 1 975265555Sambrisko#define MR_CPX_DIR_READ 0 976265555Sambrisko#define MR_CPX_VERSION 1 977265555Sambrisko 978265555Sambrisko#define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 // get IO metrics 979265555Sambrisko 980265555Sambrisko#define MR_EVT_CFG_CLEARED 0x0004 981265555Sambrisko 982265555Sambrisko#define MR_EVT_LD_STATE_CHANGE 0x0051 983265555Sambrisko#define MR_EVT_PD_INSERTED 0x005b 984265555Sambrisko#define MR_EVT_PD_REMOVED 0x0070 985265555Sambrisko#define MR_EVT_LD_CREATED 0x008a 986265555Sambrisko#define MR_EVT_LD_DELETED 0x008b 987265555Sambrisko#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 988265555Sambrisko#define MR_EVT_LD_OFFLINE 0x00fc 989265555Sambrisko#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 990265555Sambrisko#define MR_EVT_CTRL_PERF_COLLECTION 0x017e 991265555Sambrisko 992265555Sambrisko/* 993265555Sambrisko * MFI command completion codes 994265555Sambrisko */ 995265555Sambriskoenum MFI_STAT { 996265555Sambrisko MFI_STAT_OK = 0x00, 997265555Sambrisko MFI_STAT_INVALID_CMD = 0x01, 998265555Sambrisko MFI_STAT_INVALID_DCMD = 0x02, 999265555Sambrisko MFI_STAT_INVALID_PARAMETER = 0x03, 1000265555Sambrisko MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 1001265555Sambrisko MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 1002265555Sambrisko MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 1003265555Sambrisko MFI_STAT_APP_IN_USE = 0x07, 1004265555Sambrisko MFI_STAT_APP_NOT_INITIALIZED = 0x08, 1005265555Sambrisko MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 1006265555Sambrisko MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 1007265555Sambrisko MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 1008265555Sambrisko MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 1009265555Sambrisko MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 1010265555Sambrisko MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 1011265555Sambrisko MFI_STAT_FLASH_BUSY = 0x0f, 1012265555Sambrisko MFI_STAT_FLASH_ERROR = 0x10, 1013265555Sambrisko MFI_STAT_FLASH_IMAGE_BAD = 0x11, 1014265555Sambrisko MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 1015265555Sambrisko MFI_STAT_FLASH_NOT_OPEN = 0x13, 1016265555Sambrisko MFI_STAT_FLASH_NOT_STARTED = 0x14, 1017265555Sambrisko MFI_STAT_FLUSH_FAILED = 0x15, 1018265555Sambrisko MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 1019265555Sambrisko MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 1020265555Sambrisko MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 1021265555Sambrisko MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 1022265555Sambrisko MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 1023265555Sambrisko MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 1024265555Sambrisko MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 1025265555Sambrisko MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 1026265555Sambrisko MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 1027265555Sambrisko MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 1028265555Sambrisko MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 1029265555Sambrisko MFI_STAT_MFC_HW_ERROR = 0x21, 1030265555Sambrisko MFI_STAT_NO_HW_PRESENT = 0x22, 1031265555Sambrisko MFI_STAT_NOT_FOUND = 0x23, 1032265555Sambrisko MFI_STAT_NOT_IN_ENCL = 0x24, 1033265555Sambrisko MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 1034265555Sambrisko MFI_STAT_PD_TYPE_WRONG = 0x26, 1035265555Sambrisko MFI_STAT_PR_DISABLED = 0x27, 1036265555Sambrisko MFI_STAT_ROW_INDEX_INVALID = 0x28, 1037265555Sambrisko MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 1038265555Sambrisko MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 1039265555Sambrisko MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 1040265555Sambrisko MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 1041265555Sambrisko MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 1042265555Sambrisko MFI_STAT_SCSI_IO_FAILED = 0x2e, 1043265555Sambrisko MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 1044265555Sambrisko MFI_STAT_SHUTDOWN_FAILED = 0x30, 1045265555Sambrisko MFI_STAT_TIME_NOT_SET = 0x31, 1046265555Sambrisko MFI_STAT_WRONG_STATE = 0x32, 1047265555Sambrisko MFI_STAT_LD_OFFLINE = 0x33, 1048265555Sambrisko MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 1049265555Sambrisko MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 1050265555Sambrisko MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 1051265555Sambrisko MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 1052265555Sambrisko MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 1053265555Sambrisko MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 1054265555Sambrisko 1055265555Sambrisko MFI_STAT_INVALID_STATUS = 0xFF 1056265555Sambrisko}; 1057265555Sambrisko 1058265555Sambrisko/* 1059265555Sambrisko * Number of mailbox bytes in DCMD message frame 1060265555Sambrisko */ 1061265555Sambrisko#define MFI_MBOX_SIZE 12 1062265555Sambrisko 1063265555Sambriskoenum MR_EVT_CLASS { 1064265555Sambrisko 1065265555Sambrisko MR_EVT_CLASS_DEBUG = -2, 1066265555Sambrisko MR_EVT_CLASS_PROGRESS = -1, 1067265555Sambrisko MR_EVT_CLASS_INFO = 0, 1068265555Sambrisko MR_EVT_CLASS_WARNING = 1, 1069265555Sambrisko MR_EVT_CLASS_CRITICAL = 2, 1070265555Sambrisko MR_EVT_CLASS_FATAL = 3, 1071265555Sambrisko MR_EVT_CLASS_DEAD = 4, 1072265555Sambrisko 1073265555Sambrisko}; 1074265555Sambrisko 1075265555Sambriskoenum MR_EVT_LOCALE { 1076265555Sambrisko 1077265555Sambrisko MR_EVT_LOCALE_LD = 0x0001, 1078265555Sambrisko MR_EVT_LOCALE_PD = 0x0002, 1079265555Sambrisko MR_EVT_LOCALE_ENCL = 0x0004, 1080265555Sambrisko MR_EVT_LOCALE_BBU = 0x0008, 1081265555Sambrisko MR_EVT_LOCALE_SAS = 0x0010, 1082265555Sambrisko MR_EVT_LOCALE_CTRL = 0x0020, 1083265555Sambrisko MR_EVT_LOCALE_CONFIG = 0x0040, 1084265555Sambrisko MR_EVT_LOCALE_CLUSTER = 0x0080, 1085265555Sambrisko MR_EVT_LOCALE_ALL = 0xffff, 1086265555Sambrisko 1087265555Sambrisko}; 1088265555Sambrisko 1089265555Sambriskoenum MR_EVT_ARGS { 1090265555Sambrisko 1091265555Sambrisko MR_EVT_ARGS_NONE, 1092265555Sambrisko MR_EVT_ARGS_CDB_SENSE, 1093265555Sambrisko MR_EVT_ARGS_LD, 1094265555Sambrisko MR_EVT_ARGS_LD_COUNT, 1095265555Sambrisko MR_EVT_ARGS_LD_LBA, 1096265555Sambrisko MR_EVT_ARGS_LD_OWNER, 1097265555Sambrisko MR_EVT_ARGS_LD_LBA_PD_LBA, 1098265555Sambrisko MR_EVT_ARGS_LD_PROG, 1099265555Sambrisko MR_EVT_ARGS_LD_STATE, 1100265555Sambrisko MR_EVT_ARGS_LD_STRIP, 1101265555Sambrisko MR_EVT_ARGS_PD, 1102265555Sambrisko MR_EVT_ARGS_PD_ERR, 1103265555Sambrisko MR_EVT_ARGS_PD_LBA, 1104265555Sambrisko MR_EVT_ARGS_PD_LBA_LD, 1105265555Sambrisko MR_EVT_ARGS_PD_PROG, 1106265555Sambrisko MR_EVT_ARGS_PD_STATE, 1107265555Sambrisko MR_EVT_ARGS_PCI, 1108265555Sambrisko MR_EVT_ARGS_RATE, 1109265555Sambrisko MR_EVT_ARGS_STR, 1110265555Sambrisko MR_EVT_ARGS_TIME, 1111265555Sambrisko MR_EVT_ARGS_ECC, 1112265555Sambrisko MR_EVT_ARGS_LD_PROP, 1113265555Sambrisko MR_EVT_ARGS_PD_SPARE, 1114265555Sambrisko MR_EVT_ARGS_PD_INDEX, 1115265555Sambrisko MR_EVT_ARGS_DIAG_PASS, 1116265555Sambrisko MR_EVT_ARGS_DIAG_FAIL, 1117265555Sambrisko MR_EVT_ARGS_PD_LBA_LBA, 1118265555Sambrisko MR_EVT_ARGS_PORT_PHY, 1119265555Sambrisko MR_EVT_ARGS_PD_MISSING, 1120265555Sambrisko MR_EVT_ARGS_PD_ADDRESS, 1121265555Sambrisko MR_EVT_ARGS_BITMAP, 1122265555Sambrisko MR_EVT_ARGS_CONNECTOR, 1123265555Sambrisko MR_EVT_ARGS_PD_PD, 1124265555Sambrisko MR_EVT_ARGS_PD_FRU, 1125265555Sambrisko MR_EVT_ARGS_PD_PATHINFO, 1126265555Sambrisko MR_EVT_ARGS_PD_POWER_STATE, 1127265555Sambrisko MR_EVT_ARGS_GENERIC, 1128265555Sambrisko}; 1129265555Sambrisko 1130265555Sambrisko 1131265555Sambrisko/* 1132265555Sambrisko * Thunderbolt (and later) Defines 1133265555Sambrisko */ 1134265555Sambrisko#define MRSAS_MAX_SZ_CHAIN_FRAME 1024 1135265555Sambrisko#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1136265555Sambrisko#define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1137265555Sambrisko#define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1138265555Sambrisko#define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1139265555Sambrisko#define MRSAS_LOAD_BALANCE_FLAG 0x1 1140265555Sambrisko#define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1141265555Sambrisko#define HOST_DIAG_WRITE_ENABLE 0x80 1142265555Sambrisko#define HOST_DIAG_RESET_ADAPTER 0x4 1143265555Sambrisko#define MRSAS_TBOLT_MAX_RESET_TRIES 3 1144265555Sambrisko#define MRSAS_MAX_MFI_CMDS 32 1145265555Sambrisko 1146265555Sambrisko/* 1147265555Sambrisko * Invader Defines 1148265555Sambrisko */ 1149265555Sambrisko#define MPI2_TYPE_CUDA 0x2 1150265555Sambrisko#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1151265555Sambrisko#define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1152265555Sambrisko#define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1153265555Sambrisko#define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1154265555Sambrisko#define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1155265555Sambrisko 1156265555Sambrisko/* 1157265555Sambrisko * T10 PI defines 1158265555Sambrisko */ 1159265555Sambrisko#define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1160265555Sambrisko#define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1161265555Sambrisko#define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1162265555Sambrisko#define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1163265555Sambrisko#define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1164265555Sambrisko#define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1165265555Sambrisko#define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1166265555Sambrisko#define MRSAS_SCSIBLOCKSIZE 512 1167265555Sambrisko 1168265555Sambrisko/* 1169265555Sambrisko * Raid context flags 1170265555Sambrisko */ 1171265555Sambrisko#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1172265555Sambrisko#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1173265555Sambriskotypedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1174265555Sambrisko MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1175265555Sambrisko MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1176265555Sambrisko} MR_RAID_FLAGS_IO_SUB_TYPE; 1177265555Sambrisko 1178265555Sambrisko/* 1179265555Sambrisko * Request descriptor types 1180265555Sambrisko */ 1181265555Sambrisko#define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1182265555Sambrisko#define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1183265555Sambrisko#define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1184265555Sambrisko#define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1185265555Sambrisko#define MRSAS_FP_CMD_LEN 16 1186265555Sambrisko#define MRSAS_FUSION_IN_RESET 0 1187265555Sambrisko 1188265555Sambrisko#define RAID_CTX_SPANARM_ARM_SHIFT (0) 1189265555Sambrisko#define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1190265555Sambrisko#define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1191265555Sambrisko#define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1192265555Sambrisko 1193265555Sambrisko/* 1194265555Sambrisko * Define region lock types 1195265555Sambrisko */ 1196265555Sambriskotypedef enum _REGION_TYPE { 1197265555Sambrisko REGION_TYPE_UNUSED = 0, // lock is currently not active 1198265555Sambrisko REGION_TYPE_SHARED_READ = 1, // shared lock (for reads) 1199265555Sambrisko REGION_TYPE_SHARED_WRITE = 2, 1200265555Sambrisko REGION_TYPE_EXCLUSIVE = 3, // exclusive lock (for writes) 1201265555Sambrisko} REGION_TYPE; 1202265555Sambrisko 1203265555Sambrisko/* 1204265555Sambrisko * MR private defines 1205265555Sambrisko */ 1206265555Sambrisko#define MR_PD_INVALID 0xFFFF 1207265555Sambrisko#define MAX_SPAN_DEPTH 8 1208265555Sambrisko#define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 1209265555Sambrisko#define MAX_ROW_SIZE 32 1210265555Sambrisko#define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 1211265555Sambrisko#define MAX_LOGICAL_DRIVES 64 1212265555Sambrisko#define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 1213265555Sambrisko#define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 1214265555Sambrisko#define MAX_ARRAYS 128 1215265555Sambrisko#define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 1216265555Sambrisko#define MAX_PHYSICAL_DEVICES 256 1217265555Sambrisko#define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 1218265555Sambrisko#define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 1219265555Sambrisko 1220265555Sambrisko/* 1221265555Sambrisko * SCSI-CAM Related Defines 1222265555Sambrisko */ 1223265555Sambrisko#define MRSAS_SCSI_MAX_LUNS 0 //zero for now 1224265555Sambrisko#define MRSAS_SCSI_INITIATOR_ID 255 1225265555Sambrisko#define MRSAS_SCSI_MAX_CMDS 8 1226265555Sambrisko#define MRSAS_SCSI_MAX_CDB_LEN 16 1227265555Sambrisko#define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1228265555Sambrisko#define MRSAS_MAX_SGL 70 1229265555Sambrisko#define MRSAS_MAX_IO_SIZE (256 * 1024) 1230265555Sambrisko#define MRSAS_INTERNAL_CMDS 32 1231265555Sambrisko 1232265555Sambrisko/* Request types */ 1233265555Sambrisko#define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1234265555Sambrisko#define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1235265555Sambrisko#define MRSAS_REQ_TYPE_PASSTHRU 0x2 1236265555Sambrisko#define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1237265555Sambrisko#define MRSAS_REQ_TYPE_SCSI_IO 0x4 1238265555Sambrisko 1239265555Sambrisko/* Request states */ 1240265555Sambrisko#define MRSAS_REQ_STATE_FREE 0 1241265555Sambrisko#define MRSAS_REQ_STATE_BUSY 1 1242265555Sambrisko#define MRSAS_REQ_STATE_TRAN 2 1243265555Sambrisko#define MRSAS_REQ_STATE_COMPLETE 3 1244265555Sambrisko 1245265555Sambriskoenum mrsas_req_flags { 1246265555Sambrisko MRSAS_DIR_UNKNOWN = 0x1, 1247265555Sambrisko MRSAS_DIR_IN = 0x2, 1248265555Sambrisko MRSAS_DIR_OUT = 0x4, 1249265555Sambrisko MRSAS_DIR_NONE = 0x8, 1250265555Sambrisko}; 1251265555Sambrisko 1252265555Sambrisko/* 1253265555Sambrisko * Adapter Reset States 1254265555Sambrisko */ 1255265555Sambriskoenum { 1256265555Sambrisko MRSAS_HBA_OPERATIONAL = 0, 1257265555Sambrisko MRSAS_ADPRESET_SM_INFAULT = 1, 1258265555Sambrisko MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1259265555Sambrisko MRSAS_ADPRESET_SM_OPERATIONAL = 3, 1260265555Sambrisko MRSAS_HW_CRITICAL_ERROR = 4, 1261265555Sambrisko MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1262265555Sambrisko}; 1263265555Sambrisko 1264265555Sambrisko/* 1265265555Sambrisko * MPT Command Structure 1266265555Sambrisko */ 1267265555Sambriskostruct mrsas_mpt_cmd { 1268265555Sambrisko MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1269265555Sambrisko bus_addr_t io_request_phys_addr; 1270265555Sambrisko MPI2_SGE_IO_UNION *chain_frame; 1271265555Sambrisko bus_addr_t chain_frame_phys_addr; 1272265555Sambrisko u_int32_t sge_count; 1273265555Sambrisko u_int8_t *sense; 1274265555Sambrisko bus_addr_t sense_phys_addr; 1275265555Sambrisko u_int8_t retry_for_fw_reset; 1276265555Sambrisko MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1277265555Sambrisko u_int32_t sync_cmd_idx; //For getting MFI cmd from list when complete 1278265555Sambrisko u_int32_t index; 1279265555Sambrisko u_int8_t flags; 1280265555Sambrisko u_int8_t load_balance; 1281265555Sambrisko bus_size_t length; // request length 1282265555Sambrisko u_int32_t error_code; // error during request dmamap load 1283265555Sambrisko bus_dmamap_t data_dmamap; 1284265555Sambrisko void *data; 1285265555Sambrisko union ccb *ccb_ptr; // pointer to ccb 1286265555Sambrisko struct callout cm_callout; 1287265555Sambrisko struct mrsas_softc *sc; 1288265555Sambrisko TAILQ_ENTRY(mrsas_mpt_cmd) next; 1289265555Sambrisko}; 1290265555Sambrisko 1291265555Sambrisko/* 1292265555Sambrisko * MFI Command Structure 1293265555Sambrisko */ 1294265555Sambriskostruct mrsas_mfi_cmd { 1295265555Sambrisko union mrsas_frame *frame; 1296265555Sambrisko bus_dmamap_t frame_dmamap; // mfi frame dmamap 1297265555Sambrisko void *frame_mem; // mfi frame virtual addr 1298265555Sambrisko bus_addr_t frame_phys_addr; // mfi frame physical addr 1299265555Sambrisko u_int8_t *sense; 1300265555Sambrisko bus_dmamap_t sense_dmamap; // mfi sense dmamap 1301265555Sambrisko void *sense_mem; // mfi sense virtual addr 1302265555Sambrisko bus_addr_t sense_phys_addr; 1303265555Sambrisko u_int32_t index; 1304265555Sambrisko u_int8_t sync_cmd; 1305265555Sambrisko u_int8_t cmd_status; 1306265555Sambrisko u_int8_t abort_aen; 1307265555Sambrisko u_int8_t retry_for_fw_reset; 1308265555Sambrisko struct mrsas_softc *sc; 1309265555Sambrisko union ccb *ccb_ptr; 1310265555Sambrisko union { 1311265555Sambrisko struct { 1312265555Sambrisko u_int16_t smid; 1313265555Sambrisko u_int16_t resvd; 1314265555Sambrisko } context; 1315265555Sambrisko u_int32_t frame_count; 1316265555Sambrisko } cmd_id; 1317265555Sambrisko TAILQ_ENTRY(mrsas_mfi_cmd) next; 1318265555Sambrisko}; 1319265555Sambrisko 1320265555Sambrisko 1321265555Sambrisko/* 1322265555Sambrisko * define constants for device list query options 1323265555Sambrisko */ 1324265555Sambriskoenum MR_PD_QUERY_TYPE { 1325265555Sambrisko MR_PD_QUERY_TYPE_ALL = 0, 1326265555Sambrisko MR_PD_QUERY_TYPE_STATE = 1, 1327265555Sambrisko MR_PD_QUERY_TYPE_POWER_STATE = 2, 1328265555Sambrisko MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1329265555Sambrisko MR_PD_QUERY_TYPE_SPEED = 4, 1330265555Sambrisko MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1331265555Sambrisko}; 1332265555Sambrisko 1333265555Sambrisko#define MR_EVT_CFG_CLEARED 0x0004 1334265555Sambrisko#define MR_EVT_LD_STATE_CHANGE 0x0051 1335265555Sambrisko#define MR_EVT_PD_INSERTED 0x005b 1336265555Sambrisko#define MR_EVT_PD_REMOVED 0x0070 1337265555Sambrisko#define MR_EVT_LD_CREATED 0x008a 1338265555Sambrisko#define MR_EVT_LD_DELETED 0x008b 1339265555Sambrisko#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1340265555Sambrisko#define MR_EVT_LD_OFFLINE 0x00fc 1341265555Sambrisko#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1342265555Sambrisko 1343265555Sambriskoenum MR_PD_STATE { 1344265555Sambrisko MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1345265555Sambrisko MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1346265555Sambrisko MR_PD_STATE_HOT_SPARE = 0x02, 1347265555Sambrisko MR_PD_STATE_OFFLINE = 0x10, 1348265555Sambrisko MR_PD_STATE_FAILED = 0x11, 1349265555Sambrisko MR_PD_STATE_REBUILD = 0x14, 1350265555Sambrisko MR_PD_STATE_ONLINE = 0x18, 1351265555Sambrisko MR_PD_STATE_COPYBACK = 0x20, 1352265555Sambrisko MR_PD_STATE_SYSTEM = 0x40, 1353265555Sambrisko }; 1354265555Sambrisko 1355265555Sambrisko /* 1356265555Sambrisko * defines the physical drive address structure 1357265555Sambrisko */ 1358265555Sambrisko#pragma pack(1) 1359265555Sambriskostruct MR_PD_ADDRESS { 1360265555Sambrisko u_int16_t deviceId; 1361265555Sambrisko u_int16_t enclDeviceId; 1362265555Sambrisko 1363265555Sambrisko union { 1364265555Sambrisko struct { 1365265555Sambrisko u_int8_t enclIndex; 1366265555Sambrisko u_int8_t slotNumber; 1367265555Sambrisko } mrPdAddress; 1368265555Sambrisko struct { 1369265555Sambrisko u_int8_t enclPosition; 1370265555Sambrisko u_int8_t enclConnectorIndex; 1371265555Sambrisko } mrEnclAddress; 1372265555Sambrisko } u1; 1373265555Sambrisko u_int8_t scsiDevType; 1374265555Sambrisko union { 1375265555Sambrisko u_int8_t connectedPortBitmap; 1376265555Sambrisko u_int8_t connectedPortNumbers; 1377265555Sambrisko } u2; 1378265555Sambrisko u_int64_t sasAddr[2]; 1379265555Sambrisko}; 1380265555Sambrisko#pragma pack() 1381265555Sambrisko 1382265555Sambrisko/* 1383265555Sambrisko * defines the physical drive list structure 1384265555Sambrisko */ 1385265555Sambrisko#pragma pack(1) 1386265555Sambriskostruct MR_PD_LIST { 1387265555Sambrisko u_int32_t size; 1388265555Sambrisko u_int32_t count; 1389265555Sambrisko struct MR_PD_ADDRESS addr[1]; 1390265555Sambrisko}; 1391265555Sambrisko#pragma pack() 1392265555Sambrisko 1393265555Sambrisko#pragma pack(1) 1394265555Sambriskostruct mrsas_pd_list { 1395265555Sambrisko u_int16_t tid; 1396265555Sambrisko u_int8_t driveType; 1397265555Sambrisko u_int8_t driveState; 1398265555Sambrisko}; 1399265555Sambrisko#pragma pack() 1400265555Sambrisko 1401265555Sambrisko /* 1402265555Sambrisko * defines the logical drive reference structure 1403265555Sambrisko */ 1404265555Sambriskotypedef union _MR_LD_REF { // LD reference structure 1405265555Sambrisko struct { 1406265555Sambrisko u_int8_t targetId; // LD target id (0 to MAX_TARGET_ID) 1407265555Sambrisko u_int8_t reserved; // reserved to make in line with MR_PD_REF 1408265555Sambrisko u_int16_t seqNum; // Sequence Number 1409265555Sambrisko } ld_context; 1410265555Sambrisko u_int32_t ref; // shorthand reference to full 32-bits 1411265555Sambrisko} MR_LD_REF; // 4 bytes 1412265555Sambrisko 1413265555Sambrisko 1414265555Sambrisko/* 1415265555Sambrisko * defines the logical drive list structure 1416265555Sambrisko */ 1417265555Sambrisko#pragma pack(1) 1418265555Sambriskostruct MR_LD_LIST { 1419265555Sambrisko u_int32_t ldCount; // number of LDs 1420265555Sambrisko u_int32_t reserved; // pad to 8-byte boundary 1421265555Sambrisko struct { 1422265555Sambrisko MR_LD_REF ref; // LD reference 1423265555Sambrisko u_int8_t state; // current LD state (MR_LD_STATE) 1424265555Sambrisko u_int8_t reserved[3]; // pad to 8-byte boundary 1425265555Sambrisko u_int64_t size; // LD size 1426265555Sambrisko } ldList[MAX_LOGICAL_DRIVES]; 1427265555Sambrisko}; 1428265555Sambrisko#pragma pack() 1429265555Sambrisko 1430265555Sambrisko/* 1431265555Sambrisko * SAS controller properties 1432265555Sambrisko */ 1433265555Sambrisko#pragma pack(1) 1434265555Sambriskostruct mrsas_ctrl_prop { 1435265555Sambrisko u_int16_t seq_num; 1436265555Sambrisko u_int16_t pred_fail_poll_interval; 1437265555Sambrisko u_int16_t intr_throttle_count; 1438265555Sambrisko u_int16_t intr_throttle_timeouts; 1439265555Sambrisko u_int8_t rebuild_rate; 1440265555Sambrisko u_int8_t patrol_read_rate; 1441265555Sambrisko u_int8_t bgi_rate; 1442265555Sambrisko u_int8_t cc_rate; 1443265555Sambrisko u_int8_t recon_rate; 1444265555Sambrisko u_int8_t cache_flush_interval; 1445265555Sambrisko u_int8_t spinup_drv_count; 1446265555Sambrisko u_int8_t spinup_delay; 1447265555Sambrisko u_int8_t cluster_enable; 1448265555Sambrisko u_int8_t coercion_mode; 1449265555Sambrisko u_int8_t alarm_enable; 1450265555Sambrisko u_int8_t disable_auto_rebuild; 1451265555Sambrisko u_int8_t disable_battery_warn; 1452265555Sambrisko u_int8_t ecc_bucket_size; 1453265555Sambrisko u_int16_t ecc_bucket_leak_rate; 1454265555Sambrisko u_int8_t restore_hotspare_on_insertion; 1455265555Sambrisko u_int8_t expose_encl_devices; 1456265555Sambrisko u_int8_t maintainPdFailHistory; 1457265555Sambrisko u_int8_t disallowHostRequestReordering; 1458265555Sambrisko u_int8_t abortCCOnError; // set TRUE to abort CC on detecting an inconsistency 1459265555Sambrisko u_int8_t loadBalanceMode; // load balance mode (MR_LOAD_BALANCE_MODE) 1460265555Sambrisko u_int8_t disableAutoDetectBackplane; // 0 - use auto detect logic of backplanes 1461265555Sambrisko // like SGPIO, i2c SEP using h/w mechansim 1462265555Sambrisko // like GPIO pins. 1463265555Sambrisko // 1 - disable auto detect SGPIO, 1464265555Sambrisko // 2 - disable i2c SEP auto detect 1465265555Sambrisko // 3 - disable both auto detect 1466265555Sambrisko u_int8_t snapVDSpace; // % of source LD to be reserved for a VDs snapshot in 1467265555Sambrisko // snapshot repository, for metadata and user data. 1468265555Sambrisko // 1=5%, 2=10%, 3=15% and so on. 1469265555Sambrisko /* 1470265555Sambrisko * Add properties that can be controlled by a bit in the following structure. 1471265555Sambrisko */ 1472265555Sambrisko struct { 1473265555Sambrisko u_int32_t copyBackDisabled : 1; // set TRUE to disable copyBack 1474265555Sambrisko // (0=copback enabled) 1475265555Sambrisko u_int32_t SMARTerEnabled : 1; 1476265555Sambrisko u_int32_t prCorrectUnconfiguredAreas : 1; 1477265555Sambrisko u_int32_t useFdeOnly : 1; 1478265555Sambrisko u_int32_t disableNCQ : 1; 1479265555Sambrisko u_int32_t SSDSMARTerEnabled : 1; 1480265555Sambrisko u_int32_t SSDPatrolReadEnabled : 1; 1481265555Sambrisko u_int32_t enableSpinDownUnconfigured : 1; 1482265555Sambrisko u_int32_t autoEnhancedImport : 1; 1483265555Sambrisko u_int32_t enableSecretKeyControl : 1; 1484265555Sambrisko u_int32_t disableOnlineCtrlReset : 1; 1485265555Sambrisko u_int32_t allowBootWithPinnedCache : 1; 1486265555Sambrisko u_int32_t disableSpinDownHS : 1; 1487265555Sambrisko u_int32_t enableJBOD : 1; 1488265555Sambrisko u_int32_t reserved :18; 1489265555Sambrisko } OnOffProperties; 1490265555Sambrisko u_int8_t autoSnapVDSpace; // % of source LD to be reserved for auto 1491265555Sambrisko // snapshot in snapshot repository, for 1492265555Sambrisko // metadata and user data. 1493265555Sambrisko // 1=5%, 2=10%, 3=15% and so on. 1494265555Sambrisko u_int8_t viewSpace; // snapshot writeable VIEWs capacity as a % 1495265555Sambrisko // of source LD capacity. 0=READ only. 1496265555Sambrisko // 1=5%, 2=10%, 3=15% and so on 1497265555Sambrisko u_int16_t spinDownTime; // # of idle minutes before device is spun 1498265555Sambrisko // down (0=use FW defaults). 1499265555Sambrisko u_int8_t reserved[24]; 1500265555Sambrisko 1501265555Sambrisko}; 1502265555Sambrisko#pragma pack() 1503265555Sambrisko 1504265555Sambrisko 1505265555Sambrisko/* 1506265555Sambrisko * SAS controller information 1507265555Sambrisko */ 1508265555Sambrisko//#pragma pack(1) 1509265555Sambriskostruct mrsas_ctrl_info { 1510265555Sambrisko /* 1511265555Sambrisko * PCI device information 1512265555Sambrisko */ 1513265555Sambrisko struct { 1514265555Sambrisko u_int16_t vendor_id; 1515265555Sambrisko u_int16_t device_id; 1516265555Sambrisko u_int16_t sub_vendor_id; 1517265555Sambrisko u_int16_t sub_device_id; 1518265555Sambrisko u_int8_t reserved[24]; 1519265555Sambrisko } __packed pci; 1520265555Sambrisko /* 1521265555Sambrisko * Host interface information 1522265555Sambrisko */ 1523265555Sambrisko struct { 1524265555Sambrisko u_int8_t PCIX:1; 1525265555Sambrisko u_int8_t PCIE:1; 1526265555Sambrisko u_int8_t iSCSI:1; 1527265555Sambrisko u_int8_t SAS_3G:1; 1528265555Sambrisko u_int8_t reserved_0:4; 1529265555Sambrisko u_int8_t reserved_1[6]; 1530265555Sambrisko u_int8_t port_count; 1531265555Sambrisko u_int64_t port_addr[8]; 1532265555Sambrisko } __packed host_interface; 1533265555Sambrisko /* 1534265555Sambrisko * Device (backend) interface information 1535265555Sambrisko */ 1536265555Sambrisko struct { 1537265555Sambrisko u_int8_t SPI:1; 1538265555Sambrisko u_int8_t SAS_3G:1; 1539265555Sambrisko u_int8_t SATA_1_5G:1; 1540265555Sambrisko u_int8_t SATA_3G:1; 1541265555Sambrisko u_int8_t reserved_0:4; 1542265555Sambrisko u_int8_t reserved_1[6]; 1543265555Sambrisko u_int8_t port_count; 1544265555Sambrisko u_int64_t port_addr[8]; 1545265555Sambrisko } __packed device_interface; 1546265555Sambrisko 1547265555Sambrisko /* 1548265555Sambrisko * List of components residing in flash. All str are null terminated 1549265555Sambrisko */ 1550265555Sambrisko u_int32_t image_check_word; 1551265555Sambrisko u_int32_t image_component_count; 1552265555Sambrisko 1553265555Sambrisko struct { 1554265555Sambrisko char name[8]; 1555265555Sambrisko char version[32]; 1556265555Sambrisko char build_date[16]; 1557265555Sambrisko char built_time[16]; 1558265555Sambrisko } __packed image_component[8]; 1559265555Sambrisko /* 1560265555Sambrisko * List of flash components that have been flashed on the card, but 1561265555Sambrisko * are not in use, pending reset of the adapter. This list will be 1562265555Sambrisko * empty if a flash operation has not occurred. All stings are null 1563265555Sambrisko * terminated 1564265555Sambrisko */ 1565265555Sambrisko u_int32_t pending_image_component_count; 1566265555Sambrisko 1567265555Sambrisko struct { 1568265555Sambrisko char name[8]; 1569265555Sambrisko char version[32]; 1570265555Sambrisko char build_date[16]; 1571265555Sambrisko char build_time[16]; 1572265555Sambrisko } __packed pending_image_component[8]; 1573265555Sambrisko 1574265555Sambrisko u_int8_t max_arms; 1575265555Sambrisko u_int8_t max_spans; 1576265555Sambrisko u_int8_t max_arrays; 1577265555Sambrisko u_int8_t max_lds; 1578265555Sambrisko char product_name[80]; 1579265555Sambrisko char serial_no[32]; 1580265555Sambrisko 1581265555Sambrisko /* 1582265555Sambrisko * Other physical/controller/operation information. Indicates the 1583265555Sambrisko * presence of the hardware 1584265555Sambrisko */ 1585265555Sambrisko struct { 1586265555Sambrisko u_int32_t bbu:1; 1587265555Sambrisko u_int32_t alarm:1; 1588265555Sambrisko u_int32_t nvram:1; 1589265555Sambrisko u_int32_t uart:1; 1590265555Sambrisko u_int32_t reserved:28; 1591265555Sambrisko } __packed hw_present; 1592265555Sambrisko 1593265555Sambrisko u_int32_t current_fw_time; 1594265555Sambrisko 1595265555Sambrisko /* 1596265555Sambrisko * Maximum data transfer sizes 1597265555Sambrisko */ 1598265555Sambrisko u_int16_t max_concurrent_cmds; 1599265555Sambrisko u_int16_t max_sge_count; 1600265555Sambrisko u_int32_t max_request_size; 1601265555Sambrisko 1602265555Sambrisko /* 1603265555Sambrisko * Logical and physical device counts 1604265555Sambrisko */ 1605265555Sambrisko u_int16_t ld_present_count; 1606265555Sambrisko u_int16_t ld_degraded_count; 1607265555Sambrisko u_int16_t ld_offline_count; 1608265555Sambrisko 1609265555Sambrisko u_int16_t pd_present_count; 1610265555Sambrisko u_int16_t pd_disk_present_count; 1611265555Sambrisko u_int16_t pd_disk_pred_failure_count; 1612265555Sambrisko u_int16_t pd_disk_failed_count; 1613265555Sambrisko 1614265555Sambrisko /* 1615265555Sambrisko * Memory size information 1616265555Sambrisko */ 1617265555Sambrisko u_int16_t nvram_size; 1618265555Sambrisko u_int16_t memory_size; 1619265555Sambrisko u_int16_t flash_size; 1620265555Sambrisko 1621265555Sambrisko /* 1622265555Sambrisko * Error counters 1623265555Sambrisko */ 1624265555Sambrisko u_int16_t mem_correctable_error_count; 1625265555Sambrisko u_int16_t mem_uncorrectable_error_count; 1626265555Sambrisko 1627265555Sambrisko /* 1628265555Sambrisko * Cluster information 1629265555Sambrisko */ 1630265555Sambrisko u_int8_t cluster_permitted; 1631265555Sambrisko u_int8_t cluster_active; 1632265555Sambrisko 1633265555Sambrisko /* 1634265555Sambrisko * Additional max data transfer sizes 1635265555Sambrisko */ 1636265555Sambrisko u_int16_t max_strips_per_io; 1637265555Sambrisko 1638265555Sambrisko /* 1639265555Sambrisko * Controller capabilities structures 1640265555Sambrisko */ 1641265555Sambrisko struct { 1642265555Sambrisko u_int32_t raid_level_0:1; 1643265555Sambrisko u_int32_t raid_level_1:1; 1644265555Sambrisko u_int32_t raid_level_5:1; 1645265555Sambrisko u_int32_t raid_level_1E:1; 1646265555Sambrisko u_int32_t raid_level_6:1; 1647265555Sambrisko u_int32_t reserved:27; 1648265555Sambrisko } __packed raid_levels; 1649265555Sambrisko 1650265555Sambrisko struct { 1651265555Sambrisko u_int32_t rbld_rate:1; 1652265555Sambrisko u_int32_t cc_rate:1; 1653265555Sambrisko u_int32_t bgi_rate:1; 1654265555Sambrisko u_int32_t recon_rate:1; 1655265555Sambrisko u_int32_t patrol_rate:1; 1656265555Sambrisko u_int32_t alarm_control:1; 1657265555Sambrisko u_int32_t cluster_supported:1; 1658265555Sambrisko u_int32_t bbu:1; 1659265555Sambrisko u_int32_t spanning_allowed:1; 1660265555Sambrisko u_int32_t dedicated_hotspares:1; 1661265555Sambrisko u_int32_t revertible_hotspares:1; 1662265555Sambrisko u_int32_t foreign_config_import:1; 1663265555Sambrisko u_int32_t self_diagnostic:1; 1664265555Sambrisko u_int32_t mixed_redundancy_arr:1; 1665265555Sambrisko u_int32_t global_hot_spares:1; 1666265555Sambrisko u_int32_t reserved:17; 1667265555Sambrisko } __packed adapter_operations; 1668265555Sambrisko 1669265555Sambrisko struct { 1670265555Sambrisko u_int32_t read_policy:1; 1671265555Sambrisko u_int32_t write_policy:1; 1672265555Sambrisko u_int32_t io_policy:1; 1673265555Sambrisko u_int32_t access_policy:1; 1674265555Sambrisko u_int32_t disk_cache_policy:1; 1675265555Sambrisko u_int32_t reserved:27; 1676265555Sambrisko } __packed ld_operations; 1677265555Sambrisko 1678265555Sambrisko struct { 1679265555Sambrisko u_int8_t min; 1680265555Sambrisko u_int8_t max; 1681265555Sambrisko u_int8_t reserved[2]; 1682265555Sambrisko } __packed stripe_sz_ops; 1683265555Sambrisko 1684265555Sambrisko struct { 1685265555Sambrisko u_int32_t force_online:1; 1686265555Sambrisko u_int32_t force_offline:1; 1687265555Sambrisko u_int32_t force_rebuild:1; 1688265555Sambrisko u_int32_t reserved:29; 1689265555Sambrisko } __packed pd_operations; 1690265555Sambrisko 1691265555Sambrisko struct { 1692265555Sambrisko u_int32_t ctrl_supports_sas:1; 1693265555Sambrisko u_int32_t ctrl_supports_sata:1; 1694265555Sambrisko u_int32_t allow_mix_in_encl:1; 1695265555Sambrisko u_int32_t allow_mix_in_ld:1; 1696265555Sambrisko u_int32_t allow_sata_in_cluster:1; 1697265555Sambrisko u_int32_t reserved:27; 1698265555Sambrisko } __packed pd_mix_support; 1699265555Sambrisko 1700265555Sambrisko /* 1701265555Sambrisko * Define ECC single-bit-error bucket information 1702265555Sambrisko */ 1703265555Sambrisko u_int8_t ecc_bucket_count; 1704265555Sambrisko u_int8_t reserved_2[11]; 1705265555Sambrisko 1706265555Sambrisko /* 1707265555Sambrisko * Include the controller properties (changeable items) 1708265555Sambrisko */ 1709265555Sambrisko struct mrsas_ctrl_prop properties; 1710265555Sambrisko 1711265555Sambrisko /* 1712265555Sambrisko * Define FW pkg version (set in envt v'bles on OEM basis) 1713265555Sambrisko */ 1714265555Sambrisko char package_version[0x60]; 1715265555Sambrisko 1716265555Sambrisko /* 1717265555Sambrisko * If adapterOperations.supportMoreThan8Phys is set, and deviceInterface.portCount is greater than 8, 1718265555Sambrisko * SAS Addrs for first 8 ports shall be populated in deviceInterface.portAddr, and the rest shall be 1719265555Sambrisko * populated in deviceInterfacePortAddr2. 1720265555Sambrisko */ 1721265555Sambrisko u_int64_t deviceInterfacePortAddr2[8]; //0x6a0 1722265555Sambrisko u_int8_t reserved3[128]; //0x6e0 1723265555Sambrisko 1724265555Sambrisko struct { //0x760 1725265555Sambrisko u_int16_t minPdRaidLevel_0 : 4; 1726265555Sambrisko u_int16_t maxPdRaidLevel_0 : 12; 1727265555Sambrisko 1728265555Sambrisko u_int16_t minPdRaidLevel_1 : 4; 1729265555Sambrisko u_int16_t maxPdRaidLevel_1 : 12; 1730265555Sambrisko 1731265555Sambrisko u_int16_t minPdRaidLevel_5 : 4; 1732265555Sambrisko u_int16_t maxPdRaidLevel_5 : 12; 1733265555Sambrisko 1734265555Sambrisko u_int16_t minPdRaidLevel_1E : 4; 1735265555Sambrisko u_int16_t maxPdRaidLevel_1E : 12; 1736265555Sambrisko 1737265555Sambrisko u_int16_t minPdRaidLevel_6 : 4; 1738265555Sambrisko u_int16_t maxPdRaidLevel_6 : 12; 1739265555Sambrisko 1740265555Sambrisko u_int16_t minPdRaidLevel_10 : 4; 1741265555Sambrisko u_int16_t maxPdRaidLevel_10 : 12; 1742265555Sambrisko 1743265555Sambrisko u_int16_t minPdRaidLevel_50 : 4; 1744265555Sambrisko u_int16_t maxPdRaidLevel_50 : 12; 1745265555Sambrisko 1746265555Sambrisko u_int16_t minPdRaidLevel_60 : 4; 1747265555Sambrisko u_int16_t maxPdRaidLevel_60 : 12; 1748265555Sambrisko 1749265555Sambrisko u_int16_t minPdRaidLevel_1E_RLQ0 : 4; 1750265555Sambrisko u_int16_t maxPdRaidLevel_1E_RLQ0 : 12; 1751265555Sambrisko 1752265555Sambrisko u_int16_t minPdRaidLevel_1E0_RLQ0 : 4; 1753265555Sambrisko u_int16_t maxPdRaidLevel_1E0_RLQ0 : 12; 1754265555Sambrisko 1755265555Sambrisko u_int16_t reserved[6]; 1756265555Sambrisko } pdsForRaidLevels; 1757265555Sambrisko 1758265555Sambrisko u_int16_t maxPds; //0x780 1759265555Sambrisko u_int16_t maxDedHSPs; //0x782 1760265555Sambrisko u_int16_t maxGlobalHSPs; //0x784 1761265555Sambrisko u_int16_t ddfSize; //0x786 1762265555Sambrisko u_int8_t maxLdsPerArray; //0x788 1763265555Sambrisko u_int8_t partitionsInDDF; //0x789 1764265555Sambrisko u_int8_t lockKeyBinding; //0x78a 1765265555Sambrisko u_int8_t maxPITsPerLd; //0x78b 1766265555Sambrisko u_int8_t maxViewsPerLd; //0x78c 1767265555Sambrisko u_int8_t maxTargetId; //0x78d 1768265555Sambrisko u_int16_t maxBvlVdSize; //0x78e 1769265555Sambrisko 1770265555Sambrisko u_int16_t maxConfigurableSSCSize; //0x790 1771265555Sambrisko u_int16_t currentSSCsize; //0x792 1772265555Sambrisko 1773265555Sambrisko char expanderFwVersion[12]; //0x794 1774265555Sambrisko 1775265555Sambrisko u_int16_t PFKTrialTimeRemaining; //0x7A0 1776265555Sambrisko 1777265555Sambrisko u_int16_t cacheMemorySize; //0x7A2 1778265555Sambrisko 1779265555Sambrisko struct { //0x7A4 1780265555Sambrisko u_int32_t supportPIcontroller :1; 1781265555Sambrisko u_int32_t supportLdPIType1 :1; 1782265555Sambrisko u_int32_t supportLdPIType2 :1; 1783265555Sambrisko u_int32_t supportLdPIType3 :1; 1784265555Sambrisko u_int32_t supportLdBBMInfo :1; 1785265555Sambrisko u_int32_t supportShieldState :1; 1786265555Sambrisko u_int32_t blockSSDWriteCacheChange :1; 1787265555Sambrisko u_int32_t supportSuspendResumeBGops :1; 1788265555Sambrisko u_int32_t supportEmergencySpares :1; 1789265555Sambrisko u_int32_t supportSetLinkSpeed :1; 1790265555Sambrisko u_int32_t supportBootTimePFKChange :1; 1791265555Sambrisko u_int32_t supportJBOD :1; 1792265555Sambrisko u_int32_t disableOnlinePFKChange :1; 1793265555Sambrisko u_int32_t supportPerfTuning :1; 1794265555Sambrisko u_int32_t supportSSDPatrolRead :1; 1795265555Sambrisko u_int32_t realTimeScheduler :1; 1796265555Sambrisko 1797265555Sambrisko u_int32_t supportResetNow :1; 1798265555Sambrisko u_int32_t supportEmulatedDrives :1; 1799265555Sambrisko u_int32_t headlessMode :1; 1800265555Sambrisko u_int32_t dedicatedHotSparesLimited :1; 1801265555Sambrisko 1802265555Sambrisko 1803265555Sambrisko u_int32_t supportUnevenSpans :1; 1804265555Sambrisko u_int32_t reserved :11; 1805265555Sambrisko } adapterOperations2; 1806265555Sambrisko 1807265555Sambrisko u_int8_t driverVersion[32]; //0x7A8 1808265555Sambrisko u_int8_t maxDAPdCountSpinup60; //0x7C8 1809265555Sambrisko u_int8_t temperatureROC; //0x7C9 1810265555Sambrisko u_int8_t temperatureCtrl; //0x7CA 1811265555Sambrisko u_int8_t reserved4; //0x7CB 1812265555Sambrisko u_int16_t maxConfigurablePds; //0x7CC 1813265555Sambrisko 1814265555Sambrisko 1815265555Sambrisko u_int8_t reserved5[2]; //0x7CD reserved for future use 1816265555Sambrisko 1817265555Sambrisko /* 1818265555Sambrisko * HA cluster information 1819265555Sambrisko */ 1820265555Sambrisko struct { 1821265555Sambrisko u_int32_t peerIsPresent :1; 1822265555Sambrisko u_int32_t peerIsIncompatible :1; 1823265555Sambrisko 1824265555Sambrisko u_int32_t hwIncompatible :1; 1825265555Sambrisko u_int32_t fwVersionMismatch :1; 1826265555Sambrisko u_int32_t ctrlPropIncompatible :1; 1827265555Sambrisko u_int32_t premiumFeatureMismatch :1; 1828265555Sambrisko u_int32_t reserved :26; 1829265555Sambrisko } cluster; 1830265555Sambrisko 1831265555Sambrisko char clusterId[16]; //0x7D4 1832265555Sambrisko 1833265555Sambrisko u_int8_t pad[0x800-0x7E4]; //0x7E4 1834265555Sambrisko} __packed; 1835265555Sambrisko 1836265555Sambrisko/* 1837265555Sambrisko * Ld and PD Max Support Defines 1838265555Sambrisko */ 1839265555Sambrisko#define MRSAS_MAX_PD 256 1840265555Sambrisko#define MRSAS_MAX_LD 64 1841265555Sambrisko 1842265555Sambrisko/* 1843265555Sambrisko * When SCSI mid-layer calls driver's reset routine, driver waits for 1844265555Sambrisko * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1845265555Sambrisko * that the driver cannot _actually_ abort or reset pending commands. While 1846265555Sambrisko * it is waiting for the commands to complete, it prints a diagnostic message 1847265555Sambrisko * every MRSAS_RESET_NOTICE_INTERVAL seconds 1848265555Sambrisko */ 1849265555Sambrisko#define MRSAS_RESET_WAIT_TIME 180 1850265555Sambrisko#define MRSAS_INTERNAL_CMD_WAIT_TIME 180 1851265555Sambrisko#define MRSAS_IOC_INIT_WAIT_TIME 60 1852265555Sambrisko#define MRSAS_RESET_NOTICE_INTERVAL 5 1853265555Sambrisko#define MRSAS_IOCTL_CMD 0 1854265555Sambrisko#define MRSAS_DEFAULT_CMD_TIMEOUT 90 1855265555Sambrisko#define MRSAS_THROTTLE_QUEUE_DEPTH 16 1856265555Sambrisko 1857265555Sambrisko/* 1858265555Sambrisko * FW reports the maximum of number of commands that it can accept (maximum 1859265555Sambrisko * commands that can be outstanding) at any time. The driver must report a 1860265555Sambrisko * lower number to the mid layer because it can issue a few internal commands 1861265555Sambrisko * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1862265555Sambrisko * is shown below 1863265555Sambrisko */ 1864265555Sambrisko#define MRSAS_INT_CMDS 32 1865265555Sambrisko#define MRSAS_SKINNY_INT_CMDS 5 1866265555Sambrisko#define MRSAS_MAX_MSIX_QUEUES 16 1867265555Sambrisko 1868265555Sambrisko/* 1869265555Sambrisko * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 1870265555Sambrisko * SGLs based on the size of bus_addr_t 1871265555Sambrisko */ 1872265555Sambrisko#define IS_DMA64 (sizeof(bus_addr_t) == 8) 1873265555Sambrisko 1874265555Sambrisko#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 // MFI state change interrupt 1875265555Sambrisko#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1876265555Sambrisko#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1877265555Sambrisko#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 //MFI state change interrupt 1878265555Sambrisko 1879265555Sambrisko#define MFI_OB_INTR_STATUS_MASK 0x00000002 1880265555Sambrisko#define MFI_POLL_TIMEOUT_SECS 60 1881265555Sambrisko 1882265555Sambrisko#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1883265555Sambrisko#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1884265555Sambrisko#define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 1885265555Sambrisko#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1886265555Sambrisko#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1887265555Sambrisko#define MFI_1068_PCSR_OFFSET 0x84 1888265555Sambrisko#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1889265555Sambrisko#define MFI_1068_FW_READY 0xDDDD0000 1890265555Sambrisko 1891265555Sambrisko#pragma pack(1) 1892265555Sambriskostruct mrsas_sge32 { 1893265555Sambrisko u_int32_t phys_addr; 1894265555Sambrisko u_int32_t length; 1895265555Sambrisko}; 1896265555Sambrisko#pragma pack() 1897265555Sambrisko 1898265555Sambrisko#pragma pack(1) 1899265555Sambriskostruct mrsas_sge64 { 1900265555Sambrisko u_int64_t phys_addr; 1901265555Sambrisko u_int32_t length; 1902265555Sambrisko}; 1903265555Sambrisko#pragma pack() 1904265555Sambrisko 1905265555Sambrisko#pragma pack() 1906265555Sambriskounion mrsas_sgl { 1907265555Sambrisko struct mrsas_sge32 sge32[1]; 1908265555Sambrisko struct mrsas_sge64 sge64[1]; 1909265555Sambrisko}; 1910265555Sambrisko#pragma pack() 1911265555Sambrisko 1912265555Sambrisko#pragma pack(1) 1913265555Sambriskostruct mrsas_header { 1914265555Sambrisko u_int8_t cmd; /*00e */ 1915265555Sambrisko u_int8_t sense_len; /*01h */ 1916265555Sambrisko u_int8_t cmd_status; /*02h */ 1917265555Sambrisko u_int8_t scsi_status; /*03h */ 1918265555Sambrisko 1919265555Sambrisko u_int8_t target_id; /*04h */ 1920265555Sambrisko u_int8_t lun; /*05h */ 1921265555Sambrisko u_int8_t cdb_len; /*06h */ 1922265555Sambrisko u_int8_t sge_count; /*07h */ 1923265555Sambrisko 1924265555Sambrisko u_int32_t context; /*08h */ 1925265555Sambrisko u_int32_t pad_0; /*0Ch */ 1926265555Sambrisko 1927265555Sambrisko u_int16_t flags; /*10h */ 1928265555Sambrisko u_int16_t timeout; /*12h */ 1929265555Sambrisko u_int32_t data_xferlen; /*14h */ 1930265555Sambrisko}; 1931265555Sambrisko#pragma pack() 1932265555Sambrisko 1933265555Sambrisko#pragma pack(1) 1934265555Sambriskostruct mrsas_init_frame { 1935265555Sambrisko u_int8_t cmd; /*00h */ 1936265555Sambrisko u_int8_t reserved_0; /*01h */ 1937265555Sambrisko u_int8_t cmd_status; /*02h */ 1938265555Sambrisko 1939265555Sambrisko u_int8_t reserved_1; /*03h */ 1940265555Sambrisko u_int32_t reserved_2; /*04h */ 1941265555Sambrisko 1942265555Sambrisko u_int32_t context; /*08h */ 1943265555Sambrisko u_int32_t pad_0; /*0Ch */ 1944265555Sambrisko 1945265555Sambrisko u_int16_t flags; /*10h */ 1946265555Sambrisko u_int16_t reserved_3; /*12h */ 1947265555Sambrisko u_int32_t data_xfer_len; /*14h */ 1948265555Sambrisko 1949265555Sambrisko u_int32_t queue_info_new_phys_addr_lo; /*18h */ 1950265555Sambrisko u_int32_t queue_info_new_phys_addr_hi; /*1Ch */ 1951265555Sambrisko u_int32_t queue_info_old_phys_addr_lo; /*20h */ 1952265555Sambrisko u_int32_t queue_info_old_phys_addr_hi; /*24h */ 1953265555Sambrisko u_int32_t driver_ver_lo; /*28h */ 1954265555Sambrisko u_int32_t driver_ver_hi; /*2Ch */ 1955265555Sambrisko u_int32_t reserved_4[4]; /*30h */ 1956265555Sambrisko}; 1957265555Sambrisko#pragma pack() 1958265555Sambrisko 1959265555Sambrisko#pragma pack(1) 1960265555Sambriskostruct mrsas_io_frame { 1961265555Sambrisko u_int8_t cmd; /*00h */ 1962265555Sambrisko u_int8_t sense_len; /*01h */ 1963265555Sambrisko u_int8_t cmd_status; /*02h */ 1964265555Sambrisko u_int8_t scsi_status; /*03h */ 1965265555Sambrisko 1966265555Sambrisko u_int8_t target_id; /*04h */ 1967265555Sambrisko u_int8_t access_byte; /*05h */ 1968265555Sambrisko u_int8_t reserved_0; /*06h */ 1969265555Sambrisko u_int8_t sge_count; /*07h */ 1970265555Sambrisko 1971265555Sambrisko u_int32_t context; /*08h */ 1972265555Sambrisko u_int32_t pad_0; /*0Ch */ 1973265555Sambrisko 1974265555Sambrisko u_int16_t flags; /*10h */ 1975265555Sambrisko u_int16_t timeout; /*12h */ 1976265555Sambrisko u_int32_t lba_count; /*14h */ 1977265555Sambrisko 1978265555Sambrisko u_int32_t sense_buf_phys_addr_lo; /*18h */ 1979265555Sambrisko u_int32_t sense_buf_phys_addr_hi; /*1Ch */ 1980265555Sambrisko 1981265555Sambrisko u_int32_t start_lba_lo; /*20h */ 1982265555Sambrisko u_int32_t start_lba_hi; /*24h */ 1983265555Sambrisko 1984265555Sambrisko union mrsas_sgl sgl; /*28h */ 1985265555Sambrisko}; 1986265555Sambrisko#pragma pack() 1987265555Sambrisko 1988265555Sambrisko#pragma pack(1) 1989265555Sambriskostruct mrsas_pthru_frame { 1990265555Sambrisko u_int8_t cmd; /*00h */ 1991265555Sambrisko u_int8_t sense_len; /*01h */ 1992265555Sambrisko u_int8_t cmd_status; /*02h */ 1993265555Sambrisko u_int8_t scsi_status; /*03h */ 1994265555Sambrisko 1995265555Sambrisko u_int8_t target_id; /*04h */ 1996265555Sambrisko u_int8_t lun; /*05h */ 1997265555Sambrisko u_int8_t cdb_len; /*06h */ 1998265555Sambrisko u_int8_t sge_count; /*07h */ 1999265555Sambrisko 2000265555Sambrisko u_int32_t context; /*08h */ 2001265555Sambrisko u_int32_t pad_0; /*0Ch */ 2002265555Sambrisko 2003265555Sambrisko u_int16_t flags; /*10h */ 2004265555Sambrisko u_int16_t timeout; /*12h */ 2005265555Sambrisko u_int32_t data_xfer_len; /*14h */ 2006265555Sambrisko 2007265555Sambrisko u_int32_t sense_buf_phys_addr_lo; /*18h */ 2008265555Sambrisko u_int32_t sense_buf_phys_addr_hi; /*1Ch */ 2009265555Sambrisko 2010265555Sambrisko u_int8_t cdb[16]; /*20h */ 2011265555Sambrisko union mrsas_sgl sgl; /*30h */ 2012265555Sambrisko}; 2013265555Sambrisko#pragma pack() 2014265555Sambrisko 2015265555Sambrisko#pragma pack(1) 2016265555Sambriskostruct mrsas_dcmd_frame { 2017265555Sambrisko u_int8_t cmd; /*00h */ 2018265555Sambrisko u_int8_t reserved_0; /*01h */ 2019265555Sambrisko u_int8_t cmd_status; /*02h */ 2020265555Sambrisko u_int8_t reserved_1[4]; /*03h */ 2021265555Sambrisko u_int8_t sge_count; /*07h */ 2022265555Sambrisko 2023265555Sambrisko u_int32_t context; /*08h */ 2024265555Sambrisko u_int32_t pad_0; /*0Ch */ 2025265555Sambrisko 2026265555Sambrisko u_int16_t flags; /*10h */ 2027265555Sambrisko u_int16_t timeout; /*12h */ 2028265555Sambrisko 2029265555Sambrisko u_int32_t data_xfer_len; /*14h */ 2030265555Sambrisko u_int32_t opcode; /*18h */ 2031265555Sambrisko 2032265555Sambrisko union { /*1Ch */ 2033265555Sambrisko u_int8_t b[12]; 2034265555Sambrisko u_int16_t s[6]; 2035265555Sambrisko u_int32_t w[3]; 2036265555Sambrisko } mbox; 2037265555Sambrisko 2038265555Sambrisko union mrsas_sgl sgl; /*28h */ 2039265555Sambrisko}; 2040265555Sambrisko#pragma pack() 2041265555Sambrisko 2042265555Sambrisko#pragma pack(1) 2043265555Sambriskostruct mrsas_abort_frame { 2044265555Sambrisko u_int8_t cmd; /*00h */ 2045265555Sambrisko u_int8_t reserved_0; /*01h */ 2046265555Sambrisko u_int8_t cmd_status; /*02h */ 2047265555Sambrisko 2048265555Sambrisko u_int8_t reserved_1; /*03h */ 2049265555Sambrisko u_int32_t reserved_2; /*04h */ 2050265555Sambrisko 2051265555Sambrisko u_int32_t context; /*08h */ 2052265555Sambrisko u_int32_t pad_0; /*0Ch */ 2053265555Sambrisko 2054265555Sambrisko u_int16_t flags; /*10h */ 2055265555Sambrisko u_int16_t reserved_3; /*12h */ 2056265555Sambrisko u_int32_t reserved_4; /*14h */ 2057265555Sambrisko 2058265555Sambrisko u_int32_t abort_context; /*18h */ 2059265555Sambrisko u_int32_t pad_1; /*1Ch */ 2060265555Sambrisko 2061265555Sambrisko u_int32_t abort_mfi_phys_addr_lo; /*20h */ 2062265555Sambrisko u_int32_t abort_mfi_phys_addr_hi; /*24h */ 2063265555Sambrisko 2064265555Sambrisko u_int32_t reserved_5[6]; /*28h */ 2065265555Sambrisko}; 2066265555Sambrisko#pragma pack() 2067265555Sambrisko 2068265555Sambrisko#pragma pack(1) 2069265555Sambriskostruct mrsas_smp_frame { 2070265555Sambrisko u_int8_t cmd; /*00h */ 2071265555Sambrisko u_int8_t reserved_1; /*01h */ 2072265555Sambrisko u_int8_t cmd_status; /*02h */ 2073265555Sambrisko u_int8_t connection_status; /*03h */ 2074265555Sambrisko 2075265555Sambrisko u_int8_t reserved_2[3]; /*04h */ 2076265555Sambrisko u_int8_t sge_count; /*07h */ 2077265555Sambrisko 2078265555Sambrisko u_int32_t context; /*08h */ 2079265555Sambrisko u_int32_t pad_0; /*0Ch */ 2080265555Sambrisko 2081265555Sambrisko u_int16_t flags; /*10h */ 2082265555Sambrisko u_int16_t timeout; /*12h */ 2083265555Sambrisko 2084265555Sambrisko u_int32_t data_xfer_len; /*14h */ 2085265555Sambrisko u_int64_t sas_addr; /*18h */ 2086265555Sambrisko 2087265555Sambrisko union { 2088265555Sambrisko struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 2089265555Sambrisko struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 2090265555Sambrisko } sgl; 2091265555Sambrisko}; 2092265555Sambrisko#pragma pack() 2093265555Sambrisko 2094265555Sambrisko 2095265555Sambrisko#pragma pack(1) 2096265555Sambriskostruct mrsas_stp_frame { 2097265555Sambrisko u_int8_t cmd; /*00h */ 2098265555Sambrisko u_int8_t reserved_1; /*01h */ 2099265555Sambrisko u_int8_t cmd_status; /*02h */ 2100265555Sambrisko u_int8_t reserved_2; /*03h */ 2101265555Sambrisko 2102265555Sambrisko u_int8_t target_id; /*04h */ 2103265555Sambrisko u_int8_t reserved_3[2]; /*05h */ 2104265555Sambrisko u_int8_t sge_count; /*07h */ 2105265555Sambrisko 2106265555Sambrisko u_int32_t context; /*08h */ 2107265555Sambrisko u_int32_t pad_0; /*0Ch */ 2108265555Sambrisko 2109265555Sambrisko u_int16_t flags; /*10h */ 2110265555Sambrisko u_int16_t timeout; /*12h */ 2111265555Sambrisko 2112265555Sambrisko u_int32_t data_xfer_len; /*14h */ 2113265555Sambrisko 2114265555Sambrisko u_int16_t fis[10]; /*18h */ 2115265555Sambrisko u_int32_t stp_flags; 2116265555Sambrisko 2117265555Sambrisko union { 2118265555Sambrisko struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2119265555Sambrisko struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2120265555Sambrisko } sgl; 2121265555Sambrisko}; 2122265555Sambrisko#pragma pack() 2123265555Sambrisko 2124265555Sambriskounion mrsas_frame { 2125265555Sambrisko struct mrsas_header hdr; 2126265555Sambrisko struct mrsas_init_frame init; 2127265555Sambrisko struct mrsas_io_frame io; 2128265555Sambrisko struct mrsas_pthru_frame pthru; 2129265555Sambrisko struct mrsas_dcmd_frame dcmd; 2130265555Sambrisko struct mrsas_abort_frame abort; 2131265555Sambrisko struct mrsas_smp_frame smp; 2132265555Sambrisko struct mrsas_stp_frame stp; 2133265555Sambrisko u_int8_t raw_bytes[64]; 2134265555Sambrisko}; 2135265555Sambrisko 2136265555Sambrisko#pragma pack(1) 2137265555Sambriskounion mrsas_evt_class_locale { 2138265555Sambrisko 2139265555Sambrisko struct { 2140265555Sambrisko u_int16_t locale; 2141265555Sambrisko u_int8_t reserved; 2142265555Sambrisko int8_t class; 2143265555Sambrisko } __packed members; 2144265555Sambrisko 2145265555Sambrisko u_int32_t word; 2146265555Sambrisko 2147265555Sambrisko} __packed; 2148265555Sambrisko 2149265555Sambrisko#pragma pack() 2150265555Sambrisko 2151265555Sambrisko 2152265555Sambrisko#pragma pack(1) 2153265555Sambriskostruct mrsas_evt_log_info { 2154265555Sambrisko u_int32_t newest_seq_num; 2155265555Sambrisko u_int32_t oldest_seq_num; 2156265555Sambrisko u_int32_t clear_seq_num; 2157265555Sambrisko u_int32_t shutdown_seq_num; 2158265555Sambrisko u_int32_t boot_seq_num; 2159265555Sambrisko 2160265555Sambrisko} __packed; 2161265555Sambrisko 2162265555Sambrisko#pragma pack() 2163265555Sambrisko 2164265555Sambriskostruct mrsas_progress { 2165265555Sambrisko 2166265555Sambrisko u_int16_t progress; 2167265555Sambrisko u_int16_t elapsed_seconds; 2168265555Sambrisko 2169265555Sambrisko} __packed; 2170265555Sambrisko 2171265555Sambriskostruct mrsas_evtarg_ld { 2172265555Sambrisko 2173265555Sambrisko u_int16_t target_id; 2174265555Sambrisko u_int8_t ld_index; 2175265555Sambrisko u_int8_t reserved; 2176265555Sambrisko 2177265555Sambrisko} __packed; 2178265555Sambrisko 2179265555Sambriskostruct mrsas_evtarg_pd { 2180265555Sambrisko u_int16_t device_id; 2181265555Sambrisko u_int8_t encl_index; 2182265555Sambrisko u_int8_t slot_number; 2183265555Sambrisko 2184265555Sambrisko} __packed; 2185265555Sambrisko 2186265555Sambriskostruct mrsas_evt_detail { 2187265555Sambrisko 2188265555Sambrisko u_int32_t seq_num; 2189265555Sambrisko u_int32_t time_stamp; 2190265555Sambrisko u_int32_t code; 2191265555Sambrisko union mrsas_evt_class_locale cl; 2192265555Sambrisko u_int8_t arg_type; 2193265555Sambrisko u_int8_t reserved1[15]; 2194265555Sambrisko 2195265555Sambrisko union { 2196265555Sambrisko struct { 2197265555Sambrisko struct mrsas_evtarg_pd pd; 2198265555Sambrisko u_int8_t cdb_length; 2199265555Sambrisko u_int8_t sense_length; 2200265555Sambrisko u_int8_t reserved[2]; 2201265555Sambrisko u_int8_t cdb[16]; 2202265555Sambrisko u_int8_t sense[64]; 2203265555Sambrisko } __packed cdbSense; 2204265555Sambrisko 2205265555Sambrisko struct mrsas_evtarg_ld ld; 2206265555Sambrisko 2207265555Sambrisko struct { 2208265555Sambrisko struct mrsas_evtarg_ld ld; 2209265555Sambrisko u_int64_t count; 2210265555Sambrisko } __packed ld_count; 2211265555Sambrisko 2212265555Sambrisko struct { 2213265555Sambrisko u_int64_t lba; 2214265555Sambrisko struct mrsas_evtarg_ld ld; 2215265555Sambrisko } __packed ld_lba; 2216265555Sambrisko 2217265555Sambrisko struct { 2218265555Sambrisko struct mrsas_evtarg_ld ld; 2219265555Sambrisko u_int32_t prevOwner; 2220265555Sambrisko u_int32_t newOwner; 2221265555Sambrisko } __packed ld_owner; 2222265555Sambrisko 2223265555Sambrisko struct { 2224265555Sambrisko u_int64_t ld_lba; 2225265555Sambrisko u_int64_t pd_lba; 2226265555Sambrisko struct mrsas_evtarg_ld ld; 2227265555Sambrisko struct mrsas_evtarg_pd pd; 2228265555Sambrisko } __packed ld_lba_pd_lba; 2229265555Sambrisko 2230265555Sambrisko struct { 2231265555Sambrisko struct mrsas_evtarg_ld ld; 2232265555Sambrisko struct mrsas_progress prog; 2233265555Sambrisko } __packed ld_prog; 2234265555Sambrisko 2235265555Sambrisko struct { 2236265555Sambrisko struct mrsas_evtarg_ld ld; 2237265555Sambrisko u_int32_t prev_state; 2238265555Sambrisko u_int32_t new_state; 2239265555Sambrisko } __packed ld_state; 2240265555Sambrisko 2241265555Sambrisko struct { 2242265555Sambrisko u_int64_t strip; 2243265555Sambrisko struct mrsas_evtarg_ld ld; 2244265555Sambrisko } __packed ld_strip; 2245265555Sambrisko 2246265555Sambrisko struct mrsas_evtarg_pd pd; 2247265555Sambrisko 2248265555Sambrisko struct { 2249265555Sambrisko struct mrsas_evtarg_pd pd; 2250265555Sambrisko u_int32_t err; 2251265555Sambrisko } __packed pd_err; 2252265555Sambrisko 2253265555Sambrisko struct { 2254265555Sambrisko u_int64_t lba; 2255265555Sambrisko struct mrsas_evtarg_pd pd; 2256265555Sambrisko } __packed pd_lba; 2257265555Sambrisko 2258265555Sambrisko struct { 2259265555Sambrisko u_int64_t lba; 2260265555Sambrisko struct mrsas_evtarg_pd pd; 2261265555Sambrisko struct mrsas_evtarg_ld ld; 2262265555Sambrisko } __packed pd_lba_ld; 2263265555Sambrisko 2264265555Sambrisko struct { 2265265555Sambrisko struct mrsas_evtarg_pd pd; 2266265555Sambrisko struct mrsas_progress prog; 2267265555Sambrisko } __packed pd_prog; 2268265555Sambrisko 2269265555Sambrisko struct { 2270265555Sambrisko struct mrsas_evtarg_pd pd; 2271265555Sambrisko u_int32_t prevState; 2272265555Sambrisko u_int32_t newState; 2273265555Sambrisko } __packed pd_state; 2274265555Sambrisko 2275265555Sambrisko struct { 2276265555Sambrisko u_int16_t vendorId; 2277265555Sambrisko u_int16_t deviceId; 2278265555Sambrisko u_int16_t subVendorId; 2279265555Sambrisko u_int16_t subDeviceId; 2280265555Sambrisko } __packed pci; 2281265555Sambrisko 2282265555Sambrisko u_int32_t rate; 2283265555Sambrisko char str[96]; 2284265555Sambrisko 2285265555Sambrisko struct { 2286265555Sambrisko u_int32_t rtc; 2287265555Sambrisko u_int32_t elapsedSeconds; 2288265555Sambrisko } __packed time; 2289265555Sambrisko 2290265555Sambrisko struct { 2291265555Sambrisko u_int32_t ecar; 2292265555Sambrisko u_int32_t elog; 2293265555Sambrisko char str[64]; 2294265555Sambrisko } __packed ecc; 2295265555Sambrisko 2296265555Sambrisko u_int8_t b[96]; 2297265555Sambrisko u_int16_t s[48]; 2298265555Sambrisko u_int32_t w[24]; 2299265555Sambrisko u_int64_t d[12]; 2300265555Sambrisko } args; 2301265555Sambrisko 2302265555Sambrisko char description[128]; 2303265555Sambrisko 2304265555Sambrisko} __packed; 2305265555Sambrisko 2306265555Sambrisko 2307265555Sambrisko/******************************************************************* 2308265555Sambrisko * per-instance data 2309265555Sambrisko ********************************************************************/ 2310265555Sambriskostruct mrsas_softc { 2311265555Sambrisko device_t mrsas_dev; // bus device 2312265555Sambrisko struct cdev *mrsas_cdev; // controller device 2313265555Sambrisko uint16_t device_id; // pci device 2314265555Sambrisko struct resource *reg_res; // register interface window 2315265555Sambrisko int reg_res_id; // register resource id 2316265555Sambrisko bus_space_tag_t bus_tag; // bus space tag 2317265555Sambrisko bus_space_handle_t bus_handle; // bus space handle 2318265555Sambrisko bus_dma_tag_t mrsas_parent_tag; // bus dma parent tag 2319265555Sambrisko bus_dma_tag_t verbuf_tag; // verbuf tag 2320265555Sambrisko bus_dmamap_t verbuf_dmamap; // verbuf dmamap 2321265555Sambrisko void *verbuf_mem; // verbuf mem 2322265555Sambrisko bus_addr_t verbuf_phys_addr; // verbuf physical addr 2323265555Sambrisko bus_dma_tag_t sense_tag; // bus dma verbuf tag 2324265555Sambrisko bus_dmamap_t sense_dmamap; // bus dma verbuf dmamap 2325265555Sambrisko void *sense_mem; // pointer to sense buf 2326265555Sambrisko bus_addr_t sense_phys_addr; // bus dma verbuf mem 2327265555Sambrisko bus_dma_tag_t io_request_tag; // bus dma io request tag 2328265555Sambrisko bus_dmamap_t io_request_dmamap; // bus dma io request dmamap 2329265555Sambrisko void *io_request_mem; // bus dma io request mem 2330265555Sambrisko bus_addr_t io_request_phys_addr; // io request physical address 2331265555Sambrisko bus_dma_tag_t chain_frame_tag; // bus dma chain frame tag 2332265555Sambrisko bus_dmamap_t chain_frame_dmamap; // bus dma chain frame dmamap 2333265555Sambrisko void *chain_frame_mem; // bus dma chain frame mem 2334265555Sambrisko bus_addr_t chain_frame_phys_addr; // chain frame phys address 2335265555Sambrisko bus_dma_tag_t reply_desc_tag; // bus dma io request tag 2336265555Sambrisko bus_dmamap_t reply_desc_dmamap; // bus dma io request dmamap 2337265555Sambrisko void *reply_desc_mem; // bus dma io request mem 2338265555Sambrisko bus_addr_t reply_desc_phys_addr; // bus dma io request mem 2339265555Sambrisko bus_dma_tag_t ioc_init_tag; // bus dma io request tag 2340265555Sambrisko bus_dmamap_t ioc_init_dmamap; // bus dma io request dmamap 2341265555Sambrisko void *ioc_init_mem; // bus dma io request mem 2342265555Sambrisko bus_addr_t ioc_init_phys_mem; // io request physical address 2343265555Sambrisko bus_dma_tag_t data_tag; // bus dma data from OS tag 2344265555Sambrisko struct cam_sim *sim_0; // SIM pointer 2345265555Sambrisko struct cam_sim *sim_1; // SIM pointer 2346265555Sambrisko struct cam_path *path_0; // ldio path pointer to CAM 2347265555Sambrisko struct cam_path *path_1; // syspd path pointer to CAM 2348265555Sambrisko struct mtx sim_lock; // sim lock 2349265555Sambrisko struct mtx pci_lock; // serialize pci access 2350265555Sambrisko struct mtx io_lock; // IO lock 2351265555Sambrisko struct mtx ioctl_lock; // IOCTL lock 2352265555Sambrisko struct mtx mpt_cmd_pool_lock; // lock for cmd pool linked list 2353265555Sambrisko struct mtx mfi_cmd_pool_lock; // lock for cmd pool linked list 2354265555Sambrisko struct mtx raidmap_lock; // lock for raid map access/update 2355265555Sambrisko struct mtx aen_lock; // aen lock 2356265555Sambrisko uint32_t max_fw_cmds; // Max commands from FW 2357265555Sambrisko uint32_t max_num_sge; // Max number of SGEs 2358265555Sambrisko struct resource *mrsas_irq; // interrupt interface window 2359265555Sambrisko void *intr_handle; // handle 2360265555Sambrisko int irq_id; // intr resource id 2361265555Sambrisko struct mrsas_mpt_cmd **mpt_cmd_list; 2362265555Sambrisko struct mrsas_mfi_cmd **mfi_cmd_list; 2363265555Sambrisko TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head; 2364265555Sambrisko TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head; 2365265555Sambrisko bus_addr_t req_frames_desc_phys; 2366265555Sambrisko u_int8_t *req_frames_desc; 2367265555Sambrisko u_int8_t *req_desc; 2368265555Sambrisko bus_addr_t io_request_frames_phys; 2369265555Sambrisko u_int8_t *io_request_frames; 2370265555Sambrisko bus_addr_t reply_frames_desc_phys; 2371265555Sambrisko u_int16_t last_reply_idx; 2372265555Sambrisko u_int32_t reply_q_depth; 2373265555Sambrisko u_int32_t request_alloc_sz; 2374265555Sambrisko u_int32_t reply_alloc_sz; 2375265555Sambrisko u_int32_t io_frames_alloc_sz; 2376265555Sambrisko u_int32_t chain_frames_alloc_sz; 2377265555Sambrisko u_int16_t max_sge_in_main_msg; 2378265555Sambrisko u_int16_t max_sge_in_chain; 2379265555Sambrisko u_int8_t chain_offset_io_request; 2380265555Sambrisko u_int8_t chain_offset_mfi_pthru; 2381265555Sambrisko u_int32_t map_sz; 2382265555Sambrisko u_int64_t map_id; 2383265555Sambrisko struct mrsas_mfi_cmd *map_update_cmd; 2384265555Sambrisko struct mrsas_mfi_cmd *aen_cmd; 2385265555Sambrisko u_int8_t fast_path_io; 2386265555Sambrisko void* chan; 2387265555Sambrisko void* ocr_chan; 2388265555Sambrisko u_int8_t adprecovery; 2389265555Sambrisko u_int8_t remove_in_progress; 2390265555Sambrisko u_int8_t ocr_thread_active; 2391265555Sambrisko u_int8_t do_timedout_reset; 2392265555Sambrisko u_int32_t reset_in_progress; 2393265555Sambrisko u_int32_t reset_count; 2394265555Sambrisko bus_dma_tag_t raidmap_tag[2]; // bus dma tag for RAID map 2395265555Sambrisko bus_dmamap_t raidmap_dmamap[2]; // bus dma dmamap RAID map 2396265555Sambrisko void *raidmap_mem[2]; // bus dma mem RAID map 2397265555Sambrisko bus_addr_t raidmap_phys_addr[2]; // RAID map physical address 2398265555Sambrisko bus_dma_tag_t mficmd_frame_tag; // tag for mfi frame 2399265555Sambrisko bus_dma_tag_t mficmd_sense_tag; // tag for mfi sense 2400265555Sambrisko bus_dma_tag_t evt_detail_tag; // event detail tag 2401265555Sambrisko bus_dmamap_t evt_detail_dmamap; // event detail dmamap 2402265555Sambrisko struct mrsas_evt_detail *evt_detail_mem; // event detail mem 2403265555Sambrisko bus_addr_t evt_detail_phys_addr; // event detail physical addr 2404265555Sambrisko bus_dma_tag_t ctlr_info_tag; // tag for get ctlr info cmd 2405265555Sambrisko bus_dmamap_t ctlr_info_dmamap; // get ctlr info cmd dmamap 2406265555Sambrisko void *ctlr_info_mem; // get ctlr info cmd virtual addr 2407265555Sambrisko bus_addr_t ctlr_info_phys_addr; //get ctlr info cmd physical addr 2408265555Sambrisko u_int32_t max_sectors_per_req; 2409265555Sambrisko u_int8_t disableOnlineCtrlReset; 2410265555Sambrisko atomic_t fw_outstanding; 2411265555Sambrisko u_int32_t mrsas_debug; 2412265555Sambrisko u_int32_t mrsas_io_timeout; 2413265555Sambrisko u_int32_t mrsas_fw_fault_check_delay; 2414265555Sambrisko u_int32_t io_cmds_highwater; 2415265555Sambrisko u_int8_t UnevenSpanSupport; 2416265555Sambrisko struct sysctl_ctx_list sysctl_ctx; 2417265555Sambrisko struct sysctl_oid *sysctl_tree; 2418265555Sambrisko struct proc *ocr_thread; 2419265555Sambrisko u_int32_t last_seq_num; 2420265555Sambrisko bus_dma_tag_t el_info_tag; // tag for get event log info cmd 2421265555Sambrisko bus_dmamap_t el_info_dmamap; // get event log info cmd dmamap 2422265555Sambrisko void *el_info_mem; // get event log info cmd virtual addr 2423265555Sambrisko bus_addr_t el_info_phys_addr; //get event log info cmd physical addr 2424265555Sambrisko struct mrsas_pd_list pd_list[MRSAS_MAX_PD]; 2425265555Sambrisko struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD]; 2426265555Sambrisko u_int8_t ld_ids[MRSAS_MAX_LD]; 2427265555Sambrisko struct taskqueue *ev_tq; //taskqueue for events 2428265555Sambrisko struct task ev_task; 2429265555Sambrisko u_int32_t CurLdCount; 2430265555Sambrisko u_int64_t reset_flags; 2431265555Sambrisko LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES]; 2432265555Sambrisko LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES]; 2433265555Sambrisko}; 2434265555Sambrisko 2435265555Sambrisko/* Compatibility shims for different OS versions */ 2436265555Sambrisko#if __FreeBSD_version >= 800001 2437265555Sambrisko#define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 2438265555Sambrisko kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 2439265555Sambrisko#define mrsas_kproc_exit(arg) kproc_exit(arg) 2440265555Sambrisko#else 2441265555Sambrisko#define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 2442265555Sambrisko kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 2443265555Sambrisko#define mrsas_kproc_exit(arg) kthread_exit(arg) 2444265555Sambrisko#endif 2445265555Sambrisko 2446265555Sambriskostatic __inline void 2447265555Sambriskoclear_bit(int b, volatile void *p) 2448265555Sambrisko{ 2449265555Sambrisko atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 2450265555Sambrisko} 2451265555Sambrisko 2452265555Sambriskostatic __inline void 2453265555Sambriskoset_bit(int b, volatile void *p) 2454265555Sambrisko{ 2455265555Sambrisko atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 2456265555Sambrisko} 2457265555Sambrisko 2458265555Sambriskostatic __inline int 2459265555Sambriskotest_bit(int b, volatile void *p) 2460265555Sambrisko{ 2461265555Sambrisko return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 2462265555Sambrisko} 2463265555Sambrisko 2464265555Sambrisko#endif /* MRSAS_H */ 2465