mpt.c revision 224493
1/*- 2 * Generic routines for LSI Fusion adapters. 3 * FreeBSD Version. 4 * 5 * Copyright (c) 2000, 2001 by Greg Ansley 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice immediately at the beginning of the file, without modification, 12 * this list of conditions, and the following disclaimer. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28/*- 29 * Copyright (c) 2002, 2006 by Matthew Jacob 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions are 34 * met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 38 * substantially similar to the "NO WARRANTY" disclaimer below 39 * ("Disclaimer") and any redistribution must be conditioned upon including 40 * a substantially similar Disclaimer requirement for further binary 41 * redistribution. 42 * 3. Neither the names of the above listed copyright holders nor the names 43 * of any contributors may be used to endorse or promote products derived 44 * from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 47 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 49 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 50 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 51 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 52 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 53 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 54 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 55 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 56 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 * 58 * Support from Chris Ellsworth in order to make SAS adapters work 59 * is gratefully acknowledged. 60 * 61 * 62 * Support from LSI-Logic has also gone a great deal toward making this a 63 * workable subsystem and is gratefully acknowledged. 64 */ 65/*- 66 * Copyright (c) 2004, Avid Technology, Inc. and its contributors. 67 * Copyright (c) 2005, WHEEL Sp. z o.o. 68 * Copyright (c) 2004, 2005 Justin T. Gibbs 69 * All rights reserved. 70 * 71 * Redistribution and use in source and binary forms, with or without 72 * modification, are permitted provided that the following conditions are 73 * met: 74 * 1. Redistributions of source code must retain the above copyright 75 * notice, this list of conditions and the following disclaimer. 76 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 77 * substantially similar to the "NO WARRANTY" disclaimer below 78 * ("Disclaimer") and any redistribution must be conditioned upon including 79 * a substantially similar Disclaimer requirement for further binary 80 * redistribution. 81 * 3. Neither the names of the above listed copyright holders nor the names 82 * of any contributors may be used to endorse or promote products derived 83 * from this software without specific prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 86 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 88 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 89 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 90 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 91 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 92 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 93 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 94 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 95 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 96 */ 97 98#include <sys/cdefs.h> 99__FBSDID("$FreeBSD: head/sys/dev/mpt/mpt.c 224493 2011-07-29 18:35:10Z marius $"); 100 101#include <dev/mpt/mpt.h> 102#include <dev/mpt/mpt_cam.h> /* XXX For static handler registration */ 103#include <dev/mpt/mpt_raid.h> /* XXX For static handler registration */ 104 105#include <dev/mpt/mpilib/mpi.h> 106#include <dev/mpt/mpilib/mpi_ioc.h> 107#include <dev/mpt/mpilib/mpi_fc.h> 108#include <dev/mpt/mpilib/mpi_targ.h> 109 110#include <sys/sysctl.h> 111 112#define MPT_MAX_TRYS 3 113#define MPT_MAX_WAIT 300000 114 115static int maxwait_ack = 0; 116static int maxwait_int = 0; 117static int maxwait_state = 0; 118 119static TAILQ_HEAD(, mpt_softc) mpt_tailq = TAILQ_HEAD_INITIALIZER(mpt_tailq); 120mpt_reply_handler_t *mpt_reply_handlers[MPT_NUM_REPLY_HANDLERS]; 121 122static mpt_reply_handler_t mpt_default_reply_handler; 123static mpt_reply_handler_t mpt_config_reply_handler; 124static mpt_reply_handler_t mpt_handshake_reply_handler; 125static mpt_reply_handler_t mpt_event_reply_handler; 126static void mpt_send_event_ack(struct mpt_softc *mpt, request_t *ack_req, 127 MSG_EVENT_NOTIFY_REPLY *msg, uint32_t context); 128static int mpt_send_event_request(struct mpt_softc *mpt, int onoff); 129static int mpt_soft_reset(struct mpt_softc *mpt); 130static void mpt_hard_reset(struct mpt_softc *mpt); 131static int mpt_dma_buf_alloc(struct mpt_softc *mpt); 132static void mpt_dma_buf_free(struct mpt_softc *mpt); 133static int mpt_configure_ioc(struct mpt_softc *mpt, int, int); 134static int mpt_enable_ioc(struct mpt_softc *mpt, int); 135 136/************************* Personality Module Support *************************/ 137/* 138 * We include one extra entry that is guaranteed to be NULL 139 * to simplify our itterator. 140 */ 141static struct mpt_personality *mpt_personalities[MPT_MAX_PERSONALITIES + 1]; 142static __inline struct mpt_personality* 143 mpt_pers_find(struct mpt_softc *, u_int); 144static __inline struct mpt_personality* 145 mpt_pers_find_reverse(struct mpt_softc *, u_int); 146 147static __inline struct mpt_personality * 148mpt_pers_find(struct mpt_softc *mpt, u_int start_at) 149{ 150 KASSERT(start_at <= MPT_MAX_PERSONALITIES, 151 ("mpt_pers_find: starting position out of range\n")); 152 153 while (start_at < MPT_MAX_PERSONALITIES 154 && (mpt->mpt_pers_mask & (0x1 << start_at)) == 0) { 155 start_at++; 156 } 157 return (mpt_personalities[start_at]); 158} 159 160/* 161 * Used infrequently, so no need to optimize like a forward 162 * traversal where we use the MAX+1 is guaranteed to be NULL 163 * trick. 164 */ 165static __inline struct mpt_personality * 166mpt_pers_find_reverse(struct mpt_softc *mpt, u_int start_at) 167{ 168 while (start_at < MPT_MAX_PERSONALITIES 169 && (mpt->mpt_pers_mask & (0x1 << start_at)) == 0) { 170 start_at--; 171 } 172 if (start_at < MPT_MAX_PERSONALITIES) 173 return (mpt_personalities[start_at]); 174 return (NULL); 175} 176 177#define MPT_PERS_FOREACH(mpt, pers) \ 178 for (pers = mpt_pers_find(mpt, /*start_at*/0); \ 179 pers != NULL; \ 180 pers = mpt_pers_find(mpt, /*start_at*/pers->id+1)) 181 182#define MPT_PERS_FOREACH_REVERSE(mpt, pers) \ 183 for (pers = mpt_pers_find_reverse(mpt, MPT_MAX_PERSONALITIES-1);\ 184 pers != NULL; \ 185 pers = mpt_pers_find_reverse(mpt, /*start_at*/pers->id-1)) 186 187static mpt_load_handler_t mpt_stdload; 188static mpt_probe_handler_t mpt_stdprobe; 189static mpt_attach_handler_t mpt_stdattach; 190static mpt_enable_handler_t mpt_stdenable; 191static mpt_ready_handler_t mpt_stdready; 192static mpt_event_handler_t mpt_stdevent; 193static mpt_reset_handler_t mpt_stdreset; 194static mpt_shutdown_handler_t mpt_stdshutdown; 195static mpt_detach_handler_t mpt_stddetach; 196static mpt_unload_handler_t mpt_stdunload; 197static struct mpt_personality mpt_default_personality = 198{ 199 .load = mpt_stdload, 200 .probe = mpt_stdprobe, 201 .attach = mpt_stdattach, 202 .enable = mpt_stdenable, 203 .ready = mpt_stdready, 204 .event = mpt_stdevent, 205 .reset = mpt_stdreset, 206 .shutdown = mpt_stdshutdown, 207 .detach = mpt_stddetach, 208 .unload = mpt_stdunload 209}; 210 211static mpt_load_handler_t mpt_core_load; 212static mpt_attach_handler_t mpt_core_attach; 213static mpt_enable_handler_t mpt_core_enable; 214static mpt_reset_handler_t mpt_core_ioc_reset; 215static mpt_event_handler_t mpt_core_event; 216static mpt_shutdown_handler_t mpt_core_shutdown; 217static mpt_shutdown_handler_t mpt_core_detach; 218static mpt_unload_handler_t mpt_core_unload; 219static struct mpt_personality mpt_core_personality = 220{ 221 .name = "mpt_core", 222 .load = mpt_core_load, 223// .attach = mpt_core_attach, 224// .enable = mpt_core_enable, 225 .event = mpt_core_event, 226 .reset = mpt_core_ioc_reset, 227 .shutdown = mpt_core_shutdown, 228 .detach = mpt_core_detach, 229 .unload = mpt_core_unload, 230}; 231 232/* 233 * Manual declaration so that DECLARE_MPT_PERSONALITY doesn't need 234 * ordering information. We want the core to always register FIRST. 235 * other modules are set to SI_ORDER_SECOND. 236 */ 237static moduledata_t mpt_core_mod = { 238 "mpt_core", mpt_modevent, &mpt_core_personality 239}; 240DECLARE_MODULE(mpt_core, mpt_core_mod, SI_SUB_DRIVERS, SI_ORDER_FIRST); 241MODULE_VERSION(mpt_core, 1); 242 243#define MPT_PERS_ATTACHED(pers, mpt) ((mpt)->mpt_pers_mask & (0x1 << pers->id)) 244 245int 246mpt_modevent(module_t mod, int type, void *data) 247{ 248 struct mpt_personality *pers; 249 int error; 250 251 pers = (struct mpt_personality *)data; 252 253 error = 0; 254 switch (type) { 255 case MOD_LOAD: 256 { 257 mpt_load_handler_t **def_handler; 258 mpt_load_handler_t **pers_handler; 259 int i; 260 261 for (i = 0; i < MPT_MAX_PERSONALITIES; i++) { 262 if (mpt_personalities[i] == NULL) 263 break; 264 } 265 if (i >= MPT_MAX_PERSONALITIES) { 266 error = ENOMEM; 267 break; 268 } 269 pers->id = i; 270 mpt_personalities[i] = pers; 271 272 /* Install standard/noop handlers for any NULL entries. */ 273 def_handler = MPT_PERS_FIRST_HANDLER(&mpt_default_personality); 274 pers_handler = MPT_PERS_FIRST_HANDLER(pers); 275 while (pers_handler <= MPT_PERS_LAST_HANDLER(pers)) { 276 if (*pers_handler == NULL) 277 *pers_handler = *def_handler; 278 pers_handler++; 279 def_handler++; 280 } 281 282 error = (pers->load(pers)); 283 if (error != 0) 284 mpt_personalities[i] = NULL; 285 break; 286 } 287 case MOD_SHUTDOWN: 288 break; 289#if __FreeBSD_version >= 500000 290 case MOD_QUIESCE: 291 break; 292#endif 293 case MOD_UNLOAD: 294 error = pers->unload(pers); 295 mpt_personalities[pers->id] = NULL; 296 break; 297 default: 298 error = EINVAL; 299 break; 300 } 301 return (error); 302} 303 304static int 305mpt_stdload(struct mpt_personality *pers) 306{ 307 308 /* Load is always successful. */ 309 return (0); 310} 311 312static int 313mpt_stdprobe(struct mpt_softc *mpt) 314{ 315 316 /* Probe is always successful. */ 317 return (0); 318} 319 320static int 321mpt_stdattach(struct mpt_softc *mpt) 322{ 323 324 /* Attach is always successful. */ 325 return (0); 326} 327 328static int 329mpt_stdenable(struct mpt_softc *mpt) 330{ 331 332 /* Enable is always successful. */ 333 return (0); 334} 335 336static void 337mpt_stdready(struct mpt_softc *mpt) 338{ 339 340} 341 342static int 343mpt_stdevent(struct mpt_softc *mpt, request_t *req, MSG_EVENT_NOTIFY_REPLY *msg) 344{ 345 346 mpt_lprt(mpt, MPT_PRT_DEBUG, "mpt_stdevent: 0x%x\n", msg->Event & 0xFF); 347 /* Event was not for us. */ 348 return (0); 349} 350 351static void 352mpt_stdreset(struct mpt_softc *mpt, int type) 353{ 354 355} 356 357static void 358mpt_stdshutdown(struct mpt_softc *mpt) 359{ 360 361} 362 363static void 364mpt_stddetach(struct mpt_softc *mpt) 365{ 366 367} 368 369static int 370mpt_stdunload(struct mpt_personality *pers) 371{ 372 373 /* Unload is always successful. */ 374 return (0); 375} 376 377/* 378 * Post driver attachment, we may want to perform some global actions. 379 * Here is the hook to do so. 380 */ 381 382static void 383mpt_postattach(void *unused) 384{ 385 struct mpt_softc *mpt; 386 struct mpt_personality *pers; 387 388 TAILQ_FOREACH(mpt, &mpt_tailq, links) { 389 MPT_PERS_FOREACH(mpt, pers) 390 pers->ready(mpt); 391 } 392} 393SYSINIT(mptdev, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE, mpt_postattach, NULL); 394 395/******************************* Bus DMA Support ******************************/ 396void 397mpt_map_rquest(void *arg, bus_dma_segment_t *segs, int nseg, int error) 398{ 399 struct mpt_map_info *map_info; 400 401 map_info = (struct mpt_map_info *)arg; 402 map_info->error = error; 403 map_info->phys = segs->ds_addr; 404} 405 406/**************************** Reply/Event Handling ****************************/ 407int 408mpt_register_handler(struct mpt_softc *mpt, mpt_handler_type type, 409 mpt_handler_t handler, uint32_t *phandler_id) 410{ 411 412 switch (type) { 413 case MPT_HANDLER_REPLY: 414 { 415 u_int cbi; 416 u_int free_cbi; 417 418 if (phandler_id == NULL) 419 return (EINVAL); 420 421 free_cbi = MPT_HANDLER_ID_NONE; 422 for (cbi = 0; cbi < MPT_NUM_REPLY_HANDLERS; cbi++) { 423 /* 424 * If the same handler is registered multiple 425 * times, don't error out. Just return the 426 * index of the original registration. 427 */ 428 if (mpt_reply_handlers[cbi] == handler.reply_handler) { 429 *phandler_id = MPT_CBI_TO_HID(cbi); 430 return (0); 431 } 432 433 /* 434 * Fill from the front in the hope that 435 * all registered handlers consume only a 436 * single cache line. 437 * 438 * We don't break on the first empty slot so 439 * that the full table is checked to see if 440 * this handler was previously registered. 441 */ 442 if (free_cbi == MPT_HANDLER_ID_NONE && 443 (mpt_reply_handlers[cbi] 444 == mpt_default_reply_handler)) 445 free_cbi = cbi; 446 } 447 if (free_cbi == MPT_HANDLER_ID_NONE) { 448 return (ENOMEM); 449 } 450 mpt_reply_handlers[free_cbi] = handler.reply_handler; 451 *phandler_id = MPT_CBI_TO_HID(free_cbi); 452 break; 453 } 454 default: 455 mpt_prt(mpt, "mpt_register_handler unknown type %d\n", type); 456 return (EINVAL); 457 } 458 return (0); 459} 460 461int 462mpt_deregister_handler(struct mpt_softc *mpt, mpt_handler_type type, 463 mpt_handler_t handler, uint32_t handler_id) 464{ 465 466 switch (type) { 467 case MPT_HANDLER_REPLY: 468 { 469 u_int cbi; 470 471 cbi = MPT_CBI(handler_id); 472 if (cbi >= MPT_NUM_REPLY_HANDLERS 473 || mpt_reply_handlers[cbi] != handler.reply_handler) 474 return (ENOENT); 475 mpt_reply_handlers[cbi] = mpt_default_reply_handler; 476 break; 477 } 478 default: 479 mpt_prt(mpt, "mpt_deregister_handler unknown type %d\n", type); 480 return (EINVAL); 481 } 482 return (0); 483} 484 485static int 486mpt_default_reply_handler(struct mpt_softc *mpt, request_t *req, 487 uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) 488{ 489 490 mpt_prt(mpt, 491 "Default Handler Called: req=%p:%u reply_descriptor=%x frame=%p\n", 492 req, req->serno, reply_desc, reply_frame); 493 494 if (reply_frame != NULL) 495 mpt_dump_reply_frame(mpt, reply_frame); 496 497 mpt_prt(mpt, "Reply Frame Ignored\n"); 498 499 return (/*free_reply*/TRUE); 500} 501 502static int 503mpt_config_reply_handler(struct mpt_softc *mpt, request_t *req, 504 uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) 505{ 506 507 if (req != NULL) { 508 if (reply_frame != NULL) { 509 MSG_CONFIG *cfgp; 510 MSG_CONFIG_REPLY *reply; 511 512 cfgp = (MSG_CONFIG *)req->req_vbuf; 513 reply = (MSG_CONFIG_REPLY *)reply_frame; 514 req->IOCStatus = le16toh(reply_frame->IOCStatus); 515 bcopy(&reply->Header, &cfgp->Header, 516 sizeof(cfgp->Header)); 517 cfgp->ExtPageLength = reply->ExtPageLength; 518 cfgp->ExtPageType = reply->ExtPageType; 519 } 520 req->state &= ~REQ_STATE_QUEUED; 521 req->state |= REQ_STATE_DONE; 522 TAILQ_REMOVE(&mpt->request_pending_list, req, links); 523 if ((req->state & REQ_STATE_NEED_WAKEUP) != 0) { 524 wakeup(req); 525 } else if ((req->state & REQ_STATE_TIMEDOUT) != 0) { 526 /* 527 * Whew- we can free this request (late completion) 528 */ 529 mpt_free_request(mpt, req); 530 } 531 } 532 533 return (TRUE); 534} 535 536static int 537mpt_handshake_reply_handler(struct mpt_softc *mpt, request_t *req, 538 uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) 539{ 540 541 /* Nothing to be done. */ 542 return (TRUE); 543} 544 545static int 546mpt_event_reply_handler(struct mpt_softc *mpt, request_t *req, 547 uint32_t reply_desc, MSG_DEFAULT_REPLY *reply_frame) 548{ 549 int free_reply; 550 551 KASSERT(reply_frame != NULL, ("null reply in mpt_event_reply_handler")); 552 KASSERT(req != NULL, ("null request in mpt_event_reply_handler")); 553 554 free_reply = TRUE; 555 switch (reply_frame->Function) { 556 case MPI_FUNCTION_EVENT_NOTIFICATION: 557 { 558 MSG_EVENT_NOTIFY_REPLY *msg; 559 struct mpt_personality *pers; 560 u_int handled; 561 562 handled = 0; 563 msg = (MSG_EVENT_NOTIFY_REPLY *)reply_frame; 564 msg->EventDataLength = le16toh(msg->EventDataLength); 565 msg->IOCStatus = le16toh(msg->IOCStatus); 566 msg->IOCLogInfo = le32toh(msg->IOCLogInfo); 567 msg->Event = le32toh(msg->Event); 568 MPT_PERS_FOREACH(mpt, pers) 569 handled += pers->event(mpt, req, msg); 570 571 if (handled == 0 && mpt->mpt_pers_mask == 0) { 572 mpt_lprt(mpt, MPT_PRT_INFO, 573 "No Handlers For Any Event Notify Frames. " 574 "Event %#x (ACK %sequired).\n", 575 msg->Event, msg->AckRequired? "r" : "not r"); 576 } else if (handled == 0) { 577 mpt_lprt(mpt, 578 msg->AckRequired? MPT_PRT_WARN : MPT_PRT_INFO, 579 "Unhandled Event Notify Frame. Event %#x " 580 "(ACK %sequired).\n", 581 msg->Event, msg->AckRequired? "r" : "not r"); 582 } 583 584 if (msg->AckRequired) { 585 request_t *ack_req; 586 uint32_t context; 587 588 context = req->index | MPT_REPLY_HANDLER_EVENTS; 589 ack_req = mpt_get_request(mpt, FALSE); 590 if (ack_req == NULL) { 591 struct mpt_evtf_record *evtf; 592 593 evtf = (struct mpt_evtf_record *)reply_frame; 594 evtf->context = context; 595 LIST_INSERT_HEAD(&mpt->ack_frames, evtf, links); 596 free_reply = FALSE; 597 break; 598 } 599 mpt_send_event_ack(mpt, ack_req, msg, context); 600 /* 601 * Don't check for CONTINUATION_REPLY here 602 */ 603 return (free_reply); 604 } 605 break; 606 } 607 case MPI_FUNCTION_PORT_ENABLE: 608 mpt_lprt(mpt, MPT_PRT_DEBUG , "enable port reply\n"); 609 break; 610 case MPI_FUNCTION_EVENT_ACK: 611 break; 612 default: 613 mpt_prt(mpt, "unknown event function: %x\n", 614 reply_frame->Function); 615 break; 616 } 617 618 /* 619 * I'm not sure that this continuation stuff works as it should. 620 * 621 * I've had FC async events occur that free the frame up because 622 * the continuation bit isn't set, and then additional async events 623 * then occur using the same context. As you might imagine, this 624 * leads to Very Bad Thing. 625 * 626 * Let's just be safe for now and not free them up until we figure 627 * out what's actually happening here. 628 */ 629#if 0 630 if ((reply_frame->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY) == 0) { 631 TAILQ_REMOVE(&mpt->request_pending_list, req, links); 632 mpt_free_request(mpt, req); 633 mpt_prt(mpt, "event_reply %x for req %p:%u NOT a continuation", 634 reply_frame->Function, req, req->serno); 635 if (reply_frame->Function == MPI_FUNCTION_EVENT_NOTIFICATION) { 636 MSG_EVENT_NOTIFY_REPLY *msg = 637 (MSG_EVENT_NOTIFY_REPLY *)reply_frame; 638 mpt_prtc(mpt, " Event=0x%x AckReq=%d", 639 msg->Event, msg->AckRequired); 640 } 641 } else { 642 mpt_prt(mpt, "event_reply %x for %p:%u IS a continuation", 643 reply_frame->Function, req, req->serno); 644 if (reply_frame->Function == MPI_FUNCTION_EVENT_NOTIFICATION) { 645 MSG_EVENT_NOTIFY_REPLY *msg = 646 (MSG_EVENT_NOTIFY_REPLY *)reply_frame; 647 mpt_prtc(mpt, " Event=0x%x AckReq=%d", 648 msg->Event, msg->AckRequired); 649 } 650 mpt_prtc(mpt, "\n"); 651 } 652#endif 653 return (free_reply); 654} 655 656/* 657 * Process an asynchronous event from the IOC. 658 */ 659static int 660mpt_core_event(struct mpt_softc *mpt, request_t *req, 661 MSG_EVENT_NOTIFY_REPLY *msg) 662{ 663 664 mpt_lprt(mpt, MPT_PRT_DEBUG, "mpt_core_event: 0x%x\n", 665 msg->Event & 0xFF); 666 switch(msg->Event & 0xFF) { 667 case MPI_EVENT_NONE: 668 break; 669 case MPI_EVENT_LOG_DATA: 670 { 671 int i; 672 673 /* Some error occurred that LSI wants logged */ 674 mpt_prt(mpt, "EvtLogData: IOCLogInfo: 0x%08x\n", 675 msg->IOCLogInfo); 676 mpt_prt(mpt, "\tEvtLogData: Event Data:"); 677 for (i = 0; i < msg->EventDataLength; i++) 678 mpt_prtc(mpt, " %08x", msg->Data[i]); 679 mpt_prtc(mpt, "\n"); 680 break; 681 } 682 case MPI_EVENT_EVENT_CHANGE: 683 /* 684 * This is just an acknowledgement 685 * of our mpt_send_event_request. 686 */ 687 break; 688 case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE: 689 break; 690 default: 691 return (0); 692 break; 693 } 694 return (1); 695} 696 697static void 698mpt_send_event_ack(struct mpt_softc *mpt, request_t *ack_req, 699 MSG_EVENT_NOTIFY_REPLY *msg, uint32_t context) 700{ 701 MSG_EVENT_ACK *ackp; 702 703 ackp = (MSG_EVENT_ACK *)ack_req->req_vbuf; 704 memset(ackp, 0, sizeof (*ackp)); 705 ackp->Function = MPI_FUNCTION_EVENT_ACK; 706 ackp->Event = htole32(msg->Event); 707 ackp->EventContext = htole32(msg->EventContext); 708 ackp->MsgContext = htole32(context); 709 mpt_check_doorbell(mpt); 710 mpt_send_cmd(mpt, ack_req); 711} 712 713/***************************** Interrupt Handling *****************************/ 714void 715mpt_intr(void *arg) 716{ 717 struct mpt_softc *mpt; 718 uint32_t reply_desc; 719 int ntrips = 0; 720 721 mpt = (struct mpt_softc *)arg; 722 mpt_lprt(mpt, MPT_PRT_DEBUG2, "enter mpt_intr\n"); 723 MPT_LOCK_ASSERT(mpt); 724 725 while ((reply_desc = mpt_pop_reply_queue(mpt)) != MPT_REPLY_EMPTY) { 726 request_t *req; 727 MSG_DEFAULT_REPLY *reply_frame; 728 uint32_t reply_baddr; 729 uint32_t ctxt_idx; 730 u_int cb_index; 731 u_int req_index; 732 u_int offset; 733 int free_rf; 734 735 req = NULL; 736 reply_frame = NULL; 737 reply_baddr = 0; 738 offset = 0; 739 if ((reply_desc & MPI_ADDRESS_REPLY_A_BIT) != 0) { 740 /* 741 * Ensure that the reply frame is coherent. 742 */ 743 reply_baddr = MPT_REPLY_BADDR(reply_desc); 744 offset = reply_baddr - (mpt->reply_phys & 0xFFFFFFFF); 745 bus_dmamap_sync_range(mpt->reply_dmat, 746 mpt->reply_dmap, offset, MPT_REPLY_SIZE, 747 BUS_DMASYNC_POSTREAD); 748 reply_frame = MPT_REPLY_OTOV(mpt, offset); 749 ctxt_idx = le32toh(reply_frame->MsgContext); 750 } else { 751 uint32_t type; 752 753 type = MPI_GET_CONTEXT_REPLY_TYPE(reply_desc); 754 ctxt_idx = reply_desc; 755 mpt_lprt(mpt, MPT_PRT_DEBUG1, "Context Reply: 0x%08x\n", 756 reply_desc); 757 758 switch (type) { 759 case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT: 760 ctxt_idx &= MPI_CONTEXT_REPLY_CONTEXT_MASK; 761 break; 762 case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET: 763 ctxt_idx = GET_IO_INDEX(reply_desc); 764 if (mpt->tgt_cmd_ptrs == NULL) { 765 mpt_prt(mpt, 766 "mpt_intr: no target cmd ptrs\n"); 767 reply_desc = MPT_REPLY_EMPTY; 768 break; 769 } 770 if (ctxt_idx >= mpt->tgt_cmds_allocated) { 771 mpt_prt(mpt, 772 "mpt_intr: bad tgt cmd ctxt %u\n", 773 ctxt_idx); 774 reply_desc = MPT_REPLY_EMPTY; 775 ntrips = 1000; 776 break; 777 } 778 req = mpt->tgt_cmd_ptrs[ctxt_idx]; 779 if (req == NULL) { 780 mpt_prt(mpt, "no request backpointer " 781 "at index %u", ctxt_idx); 782 reply_desc = MPT_REPLY_EMPTY; 783 ntrips = 1000; 784 break; 785 } 786 /* 787 * Reformulate ctxt_idx to be just as if 788 * it were another type of context reply 789 * so the code below will find the request 790 * via indexing into the pool. 791 */ 792 ctxt_idx = 793 req->index | mpt->scsi_tgt_handler_id; 794 req = NULL; 795 break; 796 case MPI_CONTEXT_REPLY_TYPE_LAN: 797 mpt_prt(mpt, "LAN CONTEXT REPLY: 0x%08x\n", 798 reply_desc); 799 reply_desc = MPT_REPLY_EMPTY; 800 break; 801 default: 802 mpt_prt(mpt, "Context Reply 0x%08x?\n", type); 803 reply_desc = MPT_REPLY_EMPTY; 804 break; 805 } 806 if (reply_desc == MPT_REPLY_EMPTY) { 807 if (ntrips++ > 1000) { 808 break; 809 } 810 continue; 811 } 812 } 813 814 cb_index = MPT_CONTEXT_TO_CBI(ctxt_idx); 815 req_index = MPT_CONTEXT_TO_REQI(ctxt_idx); 816 if (req_index < MPT_MAX_REQUESTS(mpt)) { 817 req = &mpt->request_pool[req_index]; 818 } else { 819 mpt_prt(mpt, "WARN: mpt_intr index == %d (reply_desc ==" 820 " 0x%x)\n", req_index, reply_desc); 821 } 822 823 bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, 824 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 825 free_rf = mpt_reply_handlers[cb_index](mpt, req, 826 reply_desc, reply_frame); 827 828 if (reply_frame != NULL && free_rf) { 829 bus_dmamap_sync_range(mpt->reply_dmat, 830 mpt->reply_dmap, offset, MPT_REPLY_SIZE, 831 BUS_DMASYNC_PREREAD); 832 mpt_free_reply(mpt, reply_baddr); 833 } 834 835 /* 836 * If we got ourselves disabled, don't get stuck in a loop 837 */ 838 if (mpt->disabled) { 839 mpt_disable_ints(mpt); 840 break; 841 } 842 if (ntrips++ > 1000) { 843 break; 844 } 845 } 846 mpt_lprt(mpt, MPT_PRT_DEBUG2, "exit mpt_intr\n"); 847} 848 849/******************************* Error Recovery *******************************/ 850void 851mpt_complete_request_chain(struct mpt_softc *mpt, struct req_queue *chain, 852 u_int iocstatus) 853{ 854 MSG_DEFAULT_REPLY ioc_status_frame; 855 request_t *req; 856 857 memset(&ioc_status_frame, 0, sizeof(ioc_status_frame)); 858 ioc_status_frame.MsgLength = roundup2(sizeof(ioc_status_frame), 4); 859 ioc_status_frame.IOCStatus = iocstatus; 860 while((req = TAILQ_FIRST(chain)) != NULL) { 861 MSG_REQUEST_HEADER *msg_hdr; 862 u_int cb_index; 863 864 bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, 865 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 866 msg_hdr = (MSG_REQUEST_HEADER *)req->req_vbuf; 867 ioc_status_frame.Function = msg_hdr->Function; 868 ioc_status_frame.MsgContext = msg_hdr->MsgContext; 869 cb_index = MPT_CONTEXT_TO_CBI(le32toh(msg_hdr->MsgContext)); 870 mpt_reply_handlers[cb_index](mpt, req, msg_hdr->MsgContext, 871 &ioc_status_frame); 872 if (mpt_req_on_pending_list(mpt, req) != 0) 873 TAILQ_REMOVE(chain, req, links); 874 } 875} 876 877/********************************* Diagnostics ********************************/ 878/* 879 * Perform a diagnostic dump of a reply frame. 880 */ 881void 882mpt_dump_reply_frame(struct mpt_softc *mpt, MSG_DEFAULT_REPLY *reply_frame) 883{ 884 885 mpt_prt(mpt, "Address Reply:\n"); 886 mpt_print_reply(reply_frame); 887} 888 889/******************************* Doorbell Access ******************************/ 890static __inline uint32_t mpt_rd_db(struct mpt_softc *mpt); 891static __inline uint32_t mpt_rd_intr(struct mpt_softc *mpt); 892 893static __inline uint32_t 894mpt_rd_db(struct mpt_softc *mpt) 895{ 896 897 return mpt_read(mpt, MPT_OFFSET_DOORBELL); 898} 899 900static __inline uint32_t 901mpt_rd_intr(struct mpt_softc *mpt) 902{ 903 904 return mpt_read(mpt, MPT_OFFSET_INTR_STATUS); 905} 906 907/* Busy wait for a door bell to be read by IOC */ 908static int 909mpt_wait_db_ack(struct mpt_softc *mpt) 910{ 911 int i; 912 913 for (i=0; i < MPT_MAX_WAIT; i++) { 914 if (!MPT_DB_IS_BUSY(mpt_rd_intr(mpt))) { 915 maxwait_ack = i > maxwait_ack ? i : maxwait_ack; 916 return (MPT_OK); 917 } 918 DELAY(200); 919 } 920 return (MPT_FAIL); 921} 922 923/* Busy wait for a door bell interrupt */ 924static int 925mpt_wait_db_int(struct mpt_softc *mpt) 926{ 927 int i; 928 929 for (i = 0; i < MPT_MAX_WAIT; i++) { 930 if (MPT_DB_INTR(mpt_rd_intr(mpt))) { 931 maxwait_int = i > maxwait_int ? i : maxwait_int; 932 return MPT_OK; 933 } 934 DELAY(100); 935 } 936 return (MPT_FAIL); 937} 938 939/* Wait for IOC to transition to a give state */ 940void 941mpt_check_doorbell(struct mpt_softc *mpt) 942{ 943 uint32_t db = mpt_rd_db(mpt); 944 945 if (MPT_STATE(db) != MPT_DB_STATE_RUNNING) { 946 mpt_prt(mpt, "Device not running\n"); 947 mpt_print_db(db); 948 } 949} 950 951/* Wait for IOC to transition to a give state */ 952static int 953mpt_wait_state(struct mpt_softc *mpt, enum DB_STATE_BITS state) 954{ 955 int i; 956 957 for (i = 0; i < MPT_MAX_WAIT; i++) { 958 uint32_t db = mpt_rd_db(mpt); 959 if (MPT_STATE(db) == state) { 960 maxwait_state = i > maxwait_state ? i : maxwait_state; 961 return (MPT_OK); 962 } 963 DELAY(100); 964 } 965 return (MPT_FAIL); 966} 967 968 969/************************* Intialization/Configuration ************************/ 970static int mpt_download_fw(struct mpt_softc *mpt); 971 972/* Issue the reset COMMAND to the IOC */ 973static int 974mpt_soft_reset(struct mpt_softc *mpt) 975{ 976 977 mpt_lprt(mpt, MPT_PRT_DEBUG, "soft reset\n"); 978 979 /* Have to use hard reset if we are not in Running state */ 980 if (MPT_STATE(mpt_rd_db(mpt)) != MPT_DB_STATE_RUNNING) { 981 mpt_prt(mpt, "soft reset failed: device not running\n"); 982 return (MPT_FAIL); 983 } 984 985 /* If door bell is in use we don't have a chance of getting 986 * a word in since the IOC probably crashed in message 987 * processing. So don't waste our time. 988 */ 989 if (MPT_DB_IS_IN_USE(mpt_rd_db(mpt))) { 990 mpt_prt(mpt, "soft reset failed: doorbell wedged\n"); 991 return (MPT_FAIL); 992 } 993 994 /* Send the reset request to the IOC */ 995 mpt_write(mpt, MPT_OFFSET_DOORBELL, 996 MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET << MPI_DOORBELL_FUNCTION_SHIFT); 997 if (mpt_wait_db_ack(mpt) != MPT_OK) { 998 mpt_prt(mpt, "soft reset failed: ack timeout\n"); 999 return (MPT_FAIL); 1000 } 1001 1002 /* Wait for the IOC to reload and come out of reset state */ 1003 if (mpt_wait_state(mpt, MPT_DB_STATE_READY) != MPT_OK) { 1004 mpt_prt(mpt, "soft reset failed: device did not restart\n"); 1005 return (MPT_FAIL); 1006 } 1007 1008 return MPT_OK; 1009} 1010 1011static int 1012mpt_enable_diag_mode(struct mpt_softc *mpt) 1013{ 1014 int try; 1015 1016 try = 20; 1017 while (--try) { 1018 1019 if ((mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC) & MPI_DIAG_DRWE) != 0) 1020 break; 1021 1022 /* Enable diagnostic registers */ 1023 mpt_write(mpt, MPT_OFFSET_SEQUENCE, 0xFF); 1024 mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_1ST_KEY_VALUE); 1025 mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_2ND_KEY_VALUE); 1026 mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_3RD_KEY_VALUE); 1027 mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_4TH_KEY_VALUE); 1028 mpt_write(mpt, MPT_OFFSET_SEQUENCE, MPI_WRSEQ_5TH_KEY_VALUE); 1029 1030 DELAY(100000); 1031 } 1032 if (try == 0) 1033 return (EIO); 1034 return (0); 1035} 1036 1037static void 1038mpt_disable_diag_mode(struct mpt_softc *mpt) 1039{ 1040 1041 mpt_write(mpt, MPT_OFFSET_SEQUENCE, 0xFFFFFFFF); 1042} 1043 1044/* This is a magic diagnostic reset that resets all the ARM 1045 * processors in the chip. 1046 */ 1047static void 1048mpt_hard_reset(struct mpt_softc *mpt) 1049{ 1050 int error; 1051 int wait; 1052 uint32_t diagreg; 1053 1054 mpt_lprt(mpt, MPT_PRT_DEBUG, "hard reset\n"); 1055 1056 error = mpt_enable_diag_mode(mpt); 1057 if (error) { 1058 mpt_prt(mpt, "WARNING - Could not enter diagnostic mode !\n"); 1059 mpt_prt(mpt, "Trying to reset anyway.\n"); 1060 } 1061 1062 diagreg = mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC); 1063 1064 /* 1065 * This appears to be a workaround required for some 1066 * firmware or hardware revs. 1067 */ 1068 mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, diagreg | MPI_DIAG_DISABLE_ARM); 1069 DELAY(1000); 1070 1071 /* Diag. port is now active so we can now hit the reset bit */ 1072 mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, diagreg | MPI_DIAG_RESET_ADAPTER); 1073 1074 /* 1075 * Ensure that the reset has finished. We delay 1ms 1076 * prior to reading the register to make sure the chip 1077 * has sufficiently completed its reset to handle register 1078 * accesses. 1079 */ 1080 wait = 5000; 1081 do { 1082 DELAY(1000); 1083 diagreg = mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC); 1084 } while (--wait && (diagreg & MPI_DIAG_RESET_ADAPTER) == 0); 1085 1086 if (wait == 0) { 1087 mpt_prt(mpt, "WARNING - Failed hard reset! " 1088 "Trying to initialize anyway.\n"); 1089 } 1090 1091 /* 1092 * If we have firmware to download, it must be loaded before 1093 * the controller will become operational. Do so now. 1094 */ 1095 if (mpt->fw_image != NULL) { 1096 1097 error = mpt_download_fw(mpt); 1098 1099 if (error) { 1100 mpt_prt(mpt, "WARNING - Firmware Download Failed!\n"); 1101 mpt_prt(mpt, "Trying to initialize anyway.\n"); 1102 } 1103 } 1104 1105 /* 1106 * Reseting the controller should have disabled write 1107 * access to the diagnostic registers, but disable 1108 * manually to be sure. 1109 */ 1110 mpt_disable_diag_mode(mpt); 1111} 1112 1113static void 1114mpt_core_ioc_reset(struct mpt_softc *mpt, int type) 1115{ 1116 1117 /* 1118 * Complete all pending requests with a status 1119 * appropriate for an IOC reset. 1120 */ 1121 mpt_complete_request_chain(mpt, &mpt->request_pending_list, 1122 MPI_IOCSTATUS_INVALID_STATE); 1123} 1124 1125/* 1126 * Reset the IOC when needed. Try software command first then if needed 1127 * poke at the magic diagnostic reset. Note that a hard reset resets 1128 * *both* IOCs on dual function chips (FC929 && LSI1030) as well as 1129 * fouls up the PCI configuration registers. 1130 */ 1131int 1132mpt_reset(struct mpt_softc *mpt, int reinit) 1133{ 1134 struct mpt_personality *pers; 1135 int ret; 1136 int retry_cnt = 0; 1137 1138 /* 1139 * Try a soft reset. If that fails, get out the big hammer. 1140 */ 1141 again: 1142 if ((ret = mpt_soft_reset(mpt)) != MPT_OK) { 1143 int cnt; 1144 for (cnt = 0; cnt < 5; cnt++) { 1145 /* Failed; do a hard reset */ 1146 mpt_hard_reset(mpt); 1147 1148 /* 1149 * Wait for the IOC to reload 1150 * and come out of reset state 1151 */ 1152 ret = mpt_wait_state(mpt, MPT_DB_STATE_READY); 1153 if (ret == MPT_OK) { 1154 break; 1155 } 1156 /* 1157 * Okay- try to check again... 1158 */ 1159 ret = mpt_wait_state(mpt, MPT_DB_STATE_READY); 1160 if (ret == MPT_OK) { 1161 break; 1162 } 1163 mpt_prt(mpt, "mpt_reset: failed hard reset (%d:%d)\n", 1164 retry_cnt, cnt); 1165 } 1166 } 1167 1168 if (retry_cnt == 0) { 1169 /* 1170 * Invoke reset handlers. We bump the reset count so 1171 * that mpt_wait_req() understands that regardless of 1172 * the specified wait condition, it should stop its wait. 1173 */ 1174 mpt->reset_cnt++; 1175 MPT_PERS_FOREACH(mpt, pers) 1176 pers->reset(mpt, ret); 1177 } 1178 1179 if (reinit) { 1180 ret = mpt_enable_ioc(mpt, 1); 1181 if (ret == MPT_OK) { 1182 mpt_enable_ints(mpt); 1183 } 1184 } 1185 if (ret != MPT_OK && retry_cnt++ < 2) { 1186 goto again; 1187 } 1188 return ret; 1189} 1190 1191/* Return a command buffer to the free queue */ 1192void 1193mpt_free_request(struct mpt_softc *mpt, request_t *req) 1194{ 1195 request_t *nxt; 1196 struct mpt_evtf_record *record; 1197 uint32_t offset, reply_baddr; 1198 1199 if (req == NULL || req != &mpt->request_pool[req->index]) { 1200 panic("mpt_free_request bad req ptr\n"); 1201 return; 1202 } 1203 if ((nxt = req->chain) != NULL) { 1204 req->chain = NULL; 1205 mpt_free_request(mpt, nxt); /* NB: recursion */ 1206 } 1207 KASSERT(req->state != REQ_STATE_FREE, ("freeing free request")); 1208 KASSERT(!(req->state & REQ_STATE_LOCKED), ("freeing locked request")); 1209 MPT_LOCK_ASSERT(mpt); 1210 KASSERT(mpt_req_on_free_list(mpt, req) == 0, 1211 ("mpt_free_request: req %p:%u func %x already on freelist", 1212 req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); 1213 KASSERT(mpt_req_on_pending_list(mpt, req) == 0, 1214 ("mpt_free_request: req %p:%u func %x on pending list", 1215 req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); 1216#ifdef INVARIANTS 1217 mpt_req_not_spcl(mpt, req, "mpt_free_request", __LINE__); 1218#endif 1219 1220 req->ccb = NULL; 1221 if (LIST_EMPTY(&mpt->ack_frames)) { 1222 /* 1223 * Insert free ones at the tail 1224 */ 1225 req->serno = 0; 1226 req->state = REQ_STATE_FREE; 1227#ifdef INVARIANTS 1228 memset(req->req_vbuf, 0xff, sizeof (MSG_REQUEST_HEADER)); 1229#endif 1230 TAILQ_INSERT_TAIL(&mpt->request_free_list, req, links); 1231 if (mpt->getreqwaiter != 0) { 1232 mpt->getreqwaiter = 0; 1233 wakeup(&mpt->request_free_list); 1234 } 1235 return; 1236 } 1237 1238 /* 1239 * Process an ack frame deferred due to resource shortage. 1240 */ 1241 record = LIST_FIRST(&mpt->ack_frames); 1242 LIST_REMOVE(record, links); 1243 req->state = REQ_STATE_ALLOCATED; 1244 mpt_assign_serno(mpt, req); 1245 mpt_send_event_ack(mpt, req, &record->reply, record->context); 1246 offset = (uint32_t)((uint8_t *)record - mpt->reply); 1247 reply_baddr = offset + (mpt->reply_phys & 0xFFFFFFFF); 1248 bus_dmamap_sync_range(mpt->reply_dmat, mpt->reply_dmap, offset, 1249 MPT_REPLY_SIZE, BUS_DMASYNC_PREREAD); 1250 mpt_free_reply(mpt, reply_baddr); 1251} 1252 1253/* Get a command buffer from the free queue */ 1254request_t * 1255mpt_get_request(struct mpt_softc *mpt, int sleep_ok) 1256{ 1257 request_t *req; 1258 1259retry: 1260 MPT_LOCK_ASSERT(mpt); 1261 req = TAILQ_FIRST(&mpt->request_free_list); 1262 if (req != NULL) { 1263 KASSERT(req == &mpt->request_pool[req->index], 1264 ("mpt_get_request: corrupted request free list\n")); 1265 KASSERT(req->state == REQ_STATE_FREE, 1266 ("req %p:%u not free on free list %x index %d function %x", 1267 req, req->serno, req->state, req->index, 1268 ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); 1269 TAILQ_REMOVE(&mpt->request_free_list, req, links); 1270 req->state = REQ_STATE_ALLOCATED; 1271 req->chain = NULL; 1272 mpt_assign_serno(mpt, req); 1273 } else if (sleep_ok != 0) { 1274 mpt->getreqwaiter = 1; 1275 mpt_sleep(mpt, &mpt->request_free_list, PUSER, "mptgreq", 0); 1276 goto retry; 1277 } 1278 return (req); 1279} 1280 1281/* Pass the command to the IOC */ 1282void 1283mpt_send_cmd(struct mpt_softc *mpt, request_t *req) 1284{ 1285 1286 if (mpt->verbose > MPT_PRT_DEBUG2) { 1287 mpt_dump_request(mpt, req); 1288 } 1289 bus_dmamap_sync(mpt->request_dmat, mpt->request_dmap, 1290 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1291 req->state |= REQ_STATE_QUEUED; 1292 KASSERT(mpt_req_on_free_list(mpt, req) == 0, 1293 ("req %p:%u func %x on freelist list in mpt_send_cmd", 1294 req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); 1295 KASSERT(mpt_req_on_pending_list(mpt, req) == 0, 1296 ("req %p:%u func %x already on pending list in mpt_send_cmd", 1297 req, req->serno, ((MSG_REQUEST_HEADER *)req->req_vbuf)->Function)); 1298 TAILQ_INSERT_HEAD(&mpt->request_pending_list, req, links); 1299 mpt_write(mpt, MPT_OFFSET_REQUEST_Q, (uint32_t) req->req_pbuf); 1300} 1301 1302/* 1303 * Wait for a request to complete. 1304 * 1305 * Inputs: 1306 * mpt softc of controller executing request 1307 * req request to wait for 1308 * sleep_ok nonzero implies may sleep in this context 1309 * time_ms timeout in ms. 0 implies no timeout. 1310 * 1311 * Return Values: 1312 * 0 Request completed 1313 * non-0 Timeout fired before request completion. 1314 */ 1315int 1316mpt_wait_req(struct mpt_softc *mpt, request_t *req, 1317 mpt_req_state_t state, mpt_req_state_t mask, 1318 int sleep_ok, int time_ms) 1319{ 1320 int error; 1321 int timeout; 1322 u_int saved_cnt; 1323 1324 /* 1325 * timeout is in ms. 0 indicates infinite wait. 1326 * Convert to ticks or 500us units depending on 1327 * our sleep mode. 1328 */ 1329 if (sleep_ok != 0) { 1330 timeout = (time_ms * hz) / 1000; 1331 } else { 1332 timeout = time_ms * 2; 1333 } 1334 req->state |= REQ_STATE_NEED_WAKEUP; 1335 mask &= ~REQ_STATE_NEED_WAKEUP; 1336 saved_cnt = mpt->reset_cnt; 1337 while ((req->state & mask) != state && mpt->reset_cnt == saved_cnt) { 1338 if (sleep_ok != 0) { 1339 error = mpt_sleep(mpt, req, PUSER, "mptreq", timeout); 1340 if (error == EWOULDBLOCK) { 1341 timeout = 0; 1342 break; 1343 } 1344 } else { 1345 if (time_ms != 0 && --timeout == 0) { 1346 break; 1347 } 1348 DELAY(500); 1349 mpt_intr(mpt); 1350 } 1351 } 1352 req->state &= ~REQ_STATE_NEED_WAKEUP; 1353 if (mpt->reset_cnt != saved_cnt) { 1354 return (EIO); 1355 } 1356 if (time_ms && timeout <= 0) { 1357 MSG_REQUEST_HEADER *msg_hdr = req->req_vbuf; 1358 req->state |= REQ_STATE_TIMEDOUT; 1359 mpt_prt(mpt, "mpt_wait_req(%x) timed out\n", msg_hdr->Function); 1360 return (ETIMEDOUT); 1361 } 1362 return (0); 1363} 1364 1365/* 1366 * Send a command to the IOC via the handshake register. 1367 * 1368 * Only done at initialization time and for certain unusual 1369 * commands such as device/bus reset as specified by LSI. 1370 */ 1371int 1372mpt_send_handshake_cmd(struct mpt_softc *mpt, size_t len, void *cmd) 1373{ 1374 int i; 1375 uint32_t data, *data32; 1376 1377 /* Check condition of the IOC */ 1378 data = mpt_rd_db(mpt); 1379 if ((MPT_STATE(data) != MPT_DB_STATE_READY 1380 && MPT_STATE(data) != MPT_DB_STATE_RUNNING 1381 && MPT_STATE(data) != MPT_DB_STATE_FAULT) 1382 || MPT_DB_IS_IN_USE(data)) { 1383 mpt_prt(mpt, "handshake aborted - invalid doorbell state\n"); 1384 mpt_print_db(data); 1385 return (EBUSY); 1386 } 1387 1388 /* We move things in 32 bit chunks */ 1389 len = (len + 3) >> 2; 1390 data32 = cmd; 1391 1392 /* Clear any left over pending doorbell interrupts */ 1393 if (MPT_DB_INTR(mpt_rd_intr(mpt))) 1394 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1395 1396 /* 1397 * Tell the handshake reg. we are going to send a command 1398 * and how long it is going to be. 1399 */ 1400 data = (MPI_FUNCTION_HANDSHAKE << MPI_DOORBELL_FUNCTION_SHIFT) | 1401 (len << MPI_DOORBELL_ADD_DWORDS_SHIFT); 1402 mpt_write(mpt, MPT_OFFSET_DOORBELL, data); 1403 1404 /* Wait for the chip to notice */ 1405 if (mpt_wait_db_int(mpt) != MPT_OK) { 1406 mpt_prt(mpt, "mpt_send_handshake_cmd: db ignored\n"); 1407 return (ETIMEDOUT); 1408 } 1409 1410 /* Clear the interrupt */ 1411 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1412 1413 if (mpt_wait_db_ack(mpt) != MPT_OK) { 1414 mpt_prt(mpt, "mpt_send_handshake_cmd: db ack timed out\n"); 1415 return (ETIMEDOUT); 1416 } 1417 1418 /* Send the command */ 1419 for (i = 0; i < len; i++) { 1420 mpt_write(mpt, MPT_OFFSET_DOORBELL, htole32(*data32++)); 1421 if (mpt_wait_db_ack(mpt) != MPT_OK) { 1422 mpt_prt(mpt, 1423 "mpt_send_handshake_cmd: timeout @ index %d\n", i); 1424 return (ETIMEDOUT); 1425 } 1426 } 1427 return MPT_OK; 1428} 1429 1430/* Get the response from the handshake register */ 1431int 1432mpt_recv_handshake_reply(struct mpt_softc *mpt, size_t reply_len, void *reply) 1433{ 1434 int left, reply_left; 1435 u_int16_t *data16; 1436 uint32_t data; 1437 MSG_DEFAULT_REPLY *hdr; 1438 1439 /* We move things out in 16 bit chunks */ 1440 reply_len >>= 1; 1441 data16 = (u_int16_t *)reply; 1442 1443 hdr = (MSG_DEFAULT_REPLY *)reply; 1444 1445 /* Get first word */ 1446 if (mpt_wait_db_int(mpt) != MPT_OK) { 1447 mpt_prt(mpt, "mpt_recv_handshake_cmd timeout1\n"); 1448 return ETIMEDOUT; 1449 } 1450 data = mpt_read(mpt, MPT_OFFSET_DOORBELL); 1451 *data16++ = le16toh(data & MPT_DB_DATA_MASK); 1452 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1453 1454 /* Get Second Word */ 1455 if (mpt_wait_db_int(mpt) != MPT_OK) { 1456 mpt_prt(mpt, "mpt_recv_handshake_cmd timeout2\n"); 1457 return ETIMEDOUT; 1458 } 1459 data = mpt_read(mpt, MPT_OFFSET_DOORBELL); 1460 *data16++ = le16toh(data & MPT_DB_DATA_MASK); 1461 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1462 1463 /* 1464 * With the second word, we can now look at the length. 1465 * Warn about a reply that's too short (except for IOC FACTS REPLY) 1466 */ 1467 if ((reply_len >> 1) != hdr->MsgLength && 1468 (hdr->Function != MPI_FUNCTION_IOC_FACTS)){ 1469#if __FreeBSD_version >= 500000 1470 mpt_prt(mpt, "reply length does not match message length: " 1471 "got %x; expected %zx for function %x\n", 1472 hdr->MsgLength << 2, reply_len << 1, hdr->Function); 1473#else 1474 mpt_prt(mpt, "reply length does not match message length: " 1475 "got %x; expected %x for function %x\n", 1476 hdr->MsgLength << 2, reply_len << 1, hdr->Function); 1477#endif 1478 } 1479 1480 /* Get rest of the reply; but don't overflow the provided buffer */ 1481 left = (hdr->MsgLength << 1) - 2; 1482 reply_left = reply_len - 2; 1483 while (left--) { 1484 u_int16_t datum; 1485 1486 if (mpt_wait_db_int(mpt) != MPT_OK) { 1487 mpt_prt(mpt, "mpt_recv_handshake_cmd timeout3\n"); 1488 return ETIMEDOUT; 1489 } 1490 data = mpt_read(mpt, MPT_OFFSET_DOORBELL); 1491 datum = le16toh(data & MPT_DB_DATA_MASK); 1492 1493 if (reply_left-- > 0) 1494 *data16++ = datum; 1495 1496 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1497 } 1498 1499 /* One more wait & clear at the end */ 1500 if (mpt_wait_db_int(mpt) != MPT_OK) { 1501 mpt_prt(mpt, "mpt_recv_handshake_cmd timeout4\n"); 1502 return ETIMEDOUT; 1503 } 1504 mpt_write(mpt, MPT_OFFSET_INTR_STATUS, 0); 1505 1506 if ((hdr->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 1507 if (mpt->verbose >= MPT_PRT_TRACE) 1508 mpt_print_reply(hdr); 1509 return (MPT_FAIL | hdr->IOCStatus); 1510 } 1511 1512 return (0); 1513} 1514 1515static int 1516mpt_get_iocfacts(struct mpt_softc *mpt, MSG_IOC_FACTS_REPLY *freplp) 1517{ 1518 MSG_IOC_FACTS f_req; 1519 int error; 1520 1521 memset(&f_req, 0, sizeof f_req); 1522 f_req.Function = MPI_FUNCTION_IOC_FACTS; 1523 f_req.MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); 1524 error = mpt_send_handshake_cmd(mpt, sizeof f_req, &f_req); 1525 if (error) { 1526 return(error); 1527 } 1528 error = mpt_recv_handshake_reply(mpt, sizeof (*freplp), freplp); 1529 return (error); 1530} 1531 1532static int 1533mpt_get_portfacts(struct mpt_softc *mpt, U8 port, MSG_PORT_FACTS_REPLY *freplp) 1534{ 1535 MSG_PORT_FACTS f_req; 1536 int error; 1537 1538 memset(&f_req, 0, sizeof f_req); 1539 f_req.Function = MPI_FUNCTION_PORT_FACTS; 1540 f_req.PortNumber = port; 1541 f_req.MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); 1542 error = mpt_send_handshake_cmd(mpt, sizeof f_req, &f_req); 1543 if (error) { 1544 return(error); 1545 } 1546 error = mpt_recv_handshake_reply(mpt, sizeof (*freplp), freplp); 1547 return (error); 1548} 1549 1550/* 1551 * Send the initialization request. This is where we specify how many 1552 * SCSI busses and how many devices per bus we wish to emulate. 1553 * This is also the command that specifies the max size of the reply 1554 * frames from the IOC that we will be allocating. 1555 */ 1556static int 1557mpt_send_ioc_init(struct mpt_softc *mpt, uint32_t who) 1558{ 1559 int error = 0; 1560 MSG_IOC_INIT init; 1561 MSG_IOC_INIT_REPLY reply; 1562 1563 memset(&init, 0, sizeof init); 1564 init.WhoInit = who; 1565 init.Function = MPI_FUNCTION_IOC_INIT; 1566 init.MaxDevices = 0; /* at least 256 devices per bus */ 1567 init.MaxBuses = 16; /* at least 16 busses */ 1568 1569 init.MsgVersion = htole16(MPI_VERSION); 1570 init.HeaderVersion = htole16(MPI_HEADER_VERSION); 1571 init.ReplyFrameSize = htole16(MPT_REPLY_SIZE); 1572 init.MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); 1573 1574 if ((error = mpt_send_handshake_cmd(mpt, sizeof init, &init)) != 0) { 1575 return(error); 1576 } 1577 1578 error = mpt_recv_handshake_reply(mpt, sizeof reply, &reply); 1579 return (error); 1580} 1581 1582 1583/* 1584 * Utiltity routine to read configuration headers and pages 1585 */ 1586int 1587mpt_issue_cfg_req(struct mpt_softc *mpt, request_t *req, cfgparms_t *params, 1588 bus_addr_t addr, bus_size_t len, int sleep_ok, int timeout_ms) 1589{ 1590 MSG_CONFIG *cfgp; 1591 SGE_SIMPLE32 *se; 1592 1593 cfgp = req->req_vbuf; 1594 memset(cfgp, 0, sizeof *cfgp); 1595 cfgp->Action = params->Action; 1596 cfgp->Function = MPI_FUNCTION_CONFIG; 1597 cfgp->Header.PageVersion = params->PageVersion; 1598 cfgp->Header.PageNumber = params->PageNumber; 1599 cfgp->PageAddress = htole32(params->PageAddress); 1600 if ((params->PageType & MPI_CONFIG_PAGETYPE_MASK) == 1601 MPI_CONFIG_PAGETYPE_EXTENDED) { 1602 cfgp->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 1603 cfgp->Header.PageLength = 0; 1604 cfgp->ExtPageLength = htole16(params->ExtPageLength); 1605 cfgp->ExtPageType = params->ExtPageType; 1606 } else { 1607 cfgp->Header.PageType = params->PageType; 1608 cfgp->Header.PageLength = params->PageLength; 1609 } 1610 se = (SGE_SIMPLE32 *)&cfgp->PageBufferSGE; 1611 se->Address = htole32(addr); 1612 MPI_pSGE_SET_LENGTH(se, len); 1613 MPI_pSGE_SET_FLAGS(se, (MPI_SGE_FLAGS_SIMPLE_ELEMENT | 1614 MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER | 1615 MPI_SGE_FLAGS_END_OF_LIST | 1616 ((params->Action == MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT 1617 || params->Action == MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM) 1618 ? MPI_SGE_FLAGS_HOST_TO_IOC : MPI_SGE_FLAGS_IOC_TO_HOST))); 1619 se->FlagsLength = htole32(se->FlagsLength); 1620 cfgp->MsgContext = htole32(req->index | MPT_REPLY_HANDLER_CONFIG); 1621 1622 mpt_check_doorbell(mpt); 1623 mpt_send_cmd(mpt, req); 1624 return (mpt_wait_req(mpt, req, REQ_STATE_DONE, REQ_STATE_DONE, 1625 sleep_ok, timeout_ms)); 1626} 1627 1628int 1629mpt_read_extcfg_header(struct mpt_softc *mpt, int PageVersion, int PageNumber, 1630 uint32_t PageAddress, int ExtPageType, 1631 CONFIG_EXTENDED_PAGE_HEADER *rslt, 1632 int sleep_ok, int timeout_ms) 1633{ 1634 request_t *req; 1635 cfgparms_t params; 1636 MSG_CONFIG_REPLY *cfgp; 1637 int error; 1638 1639 req = mpt_get_request(mpt, sleep_ok); 1640 if (req == NULL) { 1641 mpt_prt(mpt, "mpt_extread_cfg_header: Get request failed!\n"); 1642 return (ENOMEM); 1643 } 1644 1645 params.Action = MPI_CONFIG_ACTION_PAGE_HEADER; 1646 params.PageVersion = PageVersion; 1647 params.PageLength = 0; 1648 params.PageNumber = PageNumber; 1649 params.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 1650 params.PageAddress = PageAddress; 1651 params.ExtPageType = ExtPageType; 1652 params.ExtPageLength = 0; 1653 error = mpt_issue_cfg_req(mpt, req, ¶ms, /*addr*/0, /*len*/0, 1654 sleep_ok, timeout_ms); 1655 if (error != 0) { 1656 /* 1657 * Leave the request. Without resetting the chip, it's 1658 * still owned by it and we'll just get into trouble 1659 * freeing it now. Mark it as abandoned so that if it 1660 * shows up later it can be freed. 1661 */ 1662 mpt_prt(mpt, "read_extcfg_header timed out\n"); 1663 return (ETIMEDOUT); 1664 } 1665 1666 switch (req->IOCStatus & MPI_IOCSTATUS_MASK) { 1667 case MPI_IOCSTATUS_SUCCESS: 1668 cfgp = req->req_vbuf; 1669 rslt->PageVersion = cfgp->Header.PageVersion; 1670 rslt->PageNumber = cfgp->Header.PageNumber; 1671 rslt->PageType = cfgp->Header.PageType; 1672 rslt->ExtPageLength = le16toh(cfgp->ExtPageLength); 1673 rslt->ExtPageType = cfgp->ExtPageType; 1674 error = 0; 1675 break; 1676 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: 1677 mpt_lprt(mpt, MPT_PRT_DEBUG, 1678 "Invalid Page Type %d Number %d Addr 0x%0x\n", 1679 MPI_CONFIG_PAGETYPE_EXTENDED, PageNumber, PageAddress); 1680 error = EINVAL; 1681 break; 1682 default: 1683 mpt_prt(mpt, "mpt_read_extcfg_header: Config Info Status %x\n", 1684 req->IOCStatus); 1685 error = EIO; 1686 break; 1687 } 1688 mpt_free_request(mpt, req); 1689 return (error); 1690} 1691 1692int 1693mpt_read_extcfg_page(struct mpt_softc *mpt, int Action, uint32_t PageAddress, 1694 CONFIG_EXTENDED_PAGE_HEADER *hdr, void *buf, size_t len, 1695 int sleep_ok, int timeout_ms) 1696{ 1697 request_t *req; 1698 cfgparms_t params; 1699 int error; 1700 1701 req = mpt_get_request(mpt, sleep_ok); 1702 if (req == NULL) { 1703 mpt_prt(mpt, "mpt_read_extcfg_page: Get request failed!\n"); 1704 return (-1); 1705 } 1706 1707 params.Action = Action; 1708 params.PageVersion = hdr->PageVersion; 1709 params.PageLength = 0; 1710 params.PageNumber = hdr->PageNumber; 1711 params.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 1712 params.PageAddress = PageAddress; 1713 params.ExtPageType = hdr->ExtPageType; 1714 params.ExtPageLength = hdr->ExtPageLength; 1715 error = mpt_issue_cfg_req(mpt, req, ¶ms, 1716 req->req_pbuf + MPT_RQSL(mpt), 1717 len, sleep_ok, timeout_ms); 1718 if (error != 0) { 1719 mpt_prt(mpt, "read_extcfg_page(%d) timed out\n", Action); 1720 return (-1); 1721 } 1722 1723 if ((req->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 1724 mpt_prt(mpt, "mpt_read_extcfg_page: Config Info Status %x\n", 1725 req->IOCStatus); 1726 mpt_free_request(mpt, req); 1727 return (-1); 1728 } 1729 memcpy(buf, ((uint8_t *)req->req_vbuf)+MPT_RQSL(mpt), len); 1730 mpt_free_request(mpt, req); 1731 return (0); 1732} 1733 1734int 1735mpt_read_cfg_header(struct mpt_softc *mpt, int PageType, int PageNumber, 1736 uint32_t PageAddress, CONFIG_PAGE_HEADER *rslt, 1737 int sleep_ok, int timeout_ms) 1738{ 1739 request_t *req; 1740 cfgparms_t params; 1741 MSG_CONFIG *cfgp; 1742 int error; 1743 1744 req = mpt_get_request(mpt, sleep_ok); 1745 if (req == NULL) { 1746 mpt_prt(mpt, "mpt_read_cfg_header: Get request failed!\n"); 1747 return (ENOMEM); 1748 } 1749 1750 params.Action = MPI_CONFIG_ACTION_PAGE_HEADER; 1751 params.PageVersion = 0; 1752 params.PageLength = 0; 1753 params.PageNumber = PageNumber; 1754 params.PageType = PageType; 1755 params.PageAddress = PageAddress; 1756 error = mpt_issue_cfg_req(mpt, req, ¶ms, /*addr*/0, /*len*/0, 1757 sleep_ok, timeout_ms); 1758 if (error != 0) { 1759 /* 1760 * Leave the request. Without resetting the chip, it's 1761 * still owned by it and we'll just get into trouble 1762 * freeing it now. Mark it as abandoned so that if it 1763 * shows up later it can be freed. 1764 */ 1765 mpt_prt(mpt, "read_cfg_header timed out\n"); 1766 return (ETIMEDOUT); 1767 } 1768 1769 switch (req->IOCStatus & MPI_IOCSTATUS_MASK) { 1770 case MPI_IOCSTATUS_SUCCESS: 1771 cfgp = req->req_vbuf; 1772 bcopy(&cfgp->Header, rslt, sizeof(*rslt)); 1773 error = 0; 1774 break; 1775 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: 1776 mpt_lprt(mpt, MPT_PRT_DEBUG, 1777 "Invalid Page Type %d Number %d Addr 0x%0x\n", 1778 PageType, PageNumber, PageAddress); 1779 error = EINVAL; 1780 break; 1781 default: 1782 mpt_prt(mpt, "mpt_read_cfg_header: Config Info Status %x\n", 1783 req->IOCStatus); 1784 error = EIO; 1785 break; 1786 } 1787 mpt_free_request(mpt, req); 1788 return (error); 1789} 1790 1791int 1792mpt_read_cfg_page(struct mpt_softc *mpt, int Action, uint32_t PageAddress, 1793 CONFIG_PAGE_HEADER *hdr, size_t len, int sleep_ok, 1794 int timeout_ms) 1795{ 1796 request_t *req; 1797 cfgparms_t params; 1798 int error; 1799 1800 req = mpt_get_request(mpt, sleep_ok); 1801 if (req == NULL) { 1802 mpt_prt(mpt, "mpt_read_cfg_page: Get request failed!\n"); 1803 return (-1); 1804 } 1805 1806 params.Action = Action; 1807 params.PageVersion = hdr->PageVersion; 1808 params.PageLength = hdr->PageLength; 1809 params.PageNumber = hdr->PageNumber; 1810 params.PageType = hdr->PageType & MPI_CONFIG_PAGETYPE_MASK; 1811 params.PageAddress = PageAddress; 1812 error = mpt_issue_cfg_req(mpt, req, ¶ms, 1813 req->req_pbuf + MPT_RQSL(mpt), 1814 len, sleep_ok, timeout_ms); 1815 if (error != 0) { 1816 mpt_prt(mpt, "read_cfg_page(%d) timed out\n", Action); 1817 return (-1); 1818 } 1819 1820 if ((req->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 1821 mpt_prt(mpt, "mpt_read_cfg_page: Config Info Status %x\n", 1822 req->IOCStatus); 1823 mpt_free_request(mpt, req); 1824 return (-1); 1825 } 1826 memcpy(hdr, ((uint8_t *)req->req_vbuf)+MPT_RQSL(mpt), len); 1827 mpt_free_request(mpt, req); 1828 return (0); 1829} 1830 1831int 1832mpt_write_cfg_page(struct mpt_softc *mpt, int Action, uint32_t PageAddress, 1833 CONFIG_PAGE_HEADER *hdr, size_t len, int sleep_ok, 1834 int timeout_ms) 1835{ 1836 request_t *req; 1837 cfgparms_t params; 1838 u_int hdr_attr; 1839 int error; 1840 1841 hdr_attr = hdr->PageType & MPI_CONFIG_PAGEATTR_MASK; 1842 if (hdr_attr != MPI_CONFIG_PAGEATTR_CHANGEABLE && 1843 hdr_attr != MPI_CONFIG_PAGEATTR_PERSISTENT) { 1844 mpt_prt(mpt, "page type 0x%x not changeable\n", 1845 hdr->PageType & MPI_CONFIG_PAGETYPE_MASK); 1846 return (-1); 1847 } 1848 1849#if 0 1850 /* 1851 * We shouldn't mask off other bits here. 1852 */ 1853 hdr->PageType &= MPI_CONFIG_PAGETYPE_MASK; 1854#endif 1855 1856 req = mpt_get_request(mpt, sleep_ok); 1857 if (req == NULL) 1858 return (-1); 1859 1860 memcpy(((caddr_t)req->req_vbuf) + MPT_RQSL(mpt), hdr, len); 1861 1862 /* 1863 * There isn't any point in restoring stripped out attributes 1864 * if you then mask them going down to issue the request. 1865 */ 1866 1867 params.Action = Action; 1868 params.PageVersion = hdr->PageVersion; 1869 params.PageLength = hdr->PageLength; 1870 params.PageNumber = hdr->PageNumber; 1871 params.PageAddress = PageAddress; 1872#if 0 1873 /* Restore stripped out attributes */ 1874 hdr->PageType |= hdr_attr; 1875 params.PageType = hdr->PageType & MPI_CONFIG_PAGETYPE_MASK; 1876#else 1877 params.PageType = hdr->PageType; 1878#endif 1879 error = mpt_issue_cfg_req(mpt, req, ¶ms, 1880 req->req_pbuf + MPT_RQSL(mpt), 1881 len, sleep_ok, timeout_ms); 1882 if (error != 0) { 1883 mpt_prt(mpt, "mpt_write_cfg_page timed out\n"); 1884 return (-1); 1885 } 1886 1887 if ((req->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 1888 mpt_prt(mpt, "mpt_write_cfg_page: Config Info Status %x\n", 1889 req->IOCStatus); 1890 mpt_free_request(mpt, req); 1891 return (-1); 1892 } 1893 mpt_free_request(mpt, req); 1894 return (0); 1895} 1896 1897/* 1898 * Read IOC configuration information 1899 */ 1900static int 1901mpt_read_config_info_ioc(struct mpt_softc *mpt) 1902{ 1903 CONFIG_PAGE_HEADER hdr; 1904 struct mpt_raid_volume *mpt_raid; 1905 int rv; 1906 int i; 1907 size_t len; 1908 1909 rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_IOC, 1910 2, 0, &hdr, FALSE, 5000); 1911 /* 1912 * If it's an invalid page, so what? Not a supported function.... 1913 */ 1914 if (rv == EINVAL) { 1915 return (0); 1916 } 1917 if (rv) { 1918 return (rv); 1919 } 1920 1921 mpt_lprt(mpt, MPT_PRT_DEBUG, 1922 "IOC Page 2 Header: Version %x len %x PageNumber %x PageType %x\n", 1923 hdr.PageVersion, hdr.PageLength << 2, 1924 hdr.PageNumber, hdr.PageType); 1925 1926 len = hdr.PageLength * sizeof(uint32_t); 1927 mpt->ioc_page2 = malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 1928 if (mpt->ioc_page2 == NULL) { 1929 mpt_prt(mpt, "unable to allocate memory for IOC page 2\n"); 1930 mpt_raid_free_mem(mpt); 1931 return (ENOMEM); 1932 } 1933 memcpy(&mpt->ioc_page2->Header, &hdr, sizeof(hdr)); 1934 rv = mpt_read_cur_cfg_page(mpt, 0, 1935 &mpt->ioc_page2->Header, len, FALSE, 5000); 1936 if (rv) { 1937 mpt_prt(mpt, "failed to read IOC Page 2\n"); 1938 mpt_raid_free_mem(mpt); 1939 return (EIO); 1940 } 1941 mpt2host_config_page_ioc2(mpt->ioc_page2); 1942 1943 if (mpt->ioc_page2->CapabilitiesFlags != 0) { 1944 uint32_t mask; 1945 1946 mpt_prt(mpt, "Capabilities: ("); 1947 for (mask = 1; mask != 0; mask <<= 1) { 1948 if ((mpt->ioc_page2->CapabilitiesFlags & mask) == 0) { 1949 continue; 1950 } 1951 switch (mask) { 1952 case MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT: 1953 mpt_prtc(mpt, " RAID-0"); 1954 break; 1955 case MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT: 1956 mpt_prtc(mpt, " RAID-1E"); 1957 break; 1958 case MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT: 1959 mpt_prtc(mpt, " RAID-1"); 1960 break; 1961 case MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT: 1962 mpt_prtc(mpt, " SES"); 1963 break; 1964 case MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT: 1965 mpt_prtc(mpt, " SAFTE"); 1966 break; 1967 case MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT: 1968 mpt_prtc(mpt, " Multi-Channel-Arrays"); 1969 default: 1970 break; 1971 } 1972 } 1973 mpt_prtc(mpt, " )\n"); 1974 if ((mpt->ioc_page2->CapabilitiesFlags 1975 & (MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT 1976 | MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT 1977 | MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT)) != 0) { 1978 mpt_prt(mpt, "%d Active Volume%s(%d Max)\n", 1979 mpt->ioc_page2->NumActiveVolumes, 1980 mpt->ioc_page2->NumActiveVolumes != 1 1981 ? "s " : " ", 1982 mpt->ioc_page2->MaxVolumes); 1983 mpt_prt(mpt, "%d Hidden Drive Member%s(%d Max)\n", 1984 mpt->ioc_page2->NumActivePhysDisks, 1985 mpt->ioc_page2->NumActivePhysDisks != 1 1986 ? "s " : " ", 1987 mpt->ioc_page2->MaxPhysDisks); 1988 } 1989 } 1990 1991 len = mpt->ioc_page2->MaxVolumes * sizeof(struct mpt_raid_volume); 1992 mpt->raid_volumes = malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 1993 if (mpt->raid_volumes == NULL) { 1994 mpt_prt(mpt, "Could not allocate RAID volume data\n"); 1995 mpt_raid_free_mem(mpt); 1996 return (ENOMEM); 1997 } 1998 1999 /* 2000 * Copy critical data out of ioc_page2 so that we can 2001 * safely refresh the page without windows of unreliable 2002 * data. 2003 */ 2004 mpt->raid_max_volumes = mpt->ioc_page2->MaxVolumes; 2005 2006 len = sizeof(*mpt->raid_volumes->config_page) + 2007 (sizeof (RAID_VOL0_PHYS_DISK) * (mpt->ioc_page2->MaxPhysDisks - 1)); 2008 for (i = 0; i < mpt->ioc_page2->MaxVolumes; i++) { 2009 mpt_raid = &mpt->raid_volumes[i]; 2010 mpt_raid->config_page = 2011 malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 2012 if (mpt_raid->config_page == NULL) { 2013 mpt_prt(mpt, "Could not allocate RAID page data\n"); 2014 mpt_raid_free_mem(mpt); 2015 return (ENOMEM); 2016 } 2017 } 2018 mpt->raid_page0_len = len; 2019 2020 len = mpt->ioc_page2->MaxPhysDisks * sizeof(struct mpt_raid_disk); 2021 mpt->raid_disks = malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 2022 if (mpt->raid_disks == NULL) { 2023 mpt_prt(mpt, "Could not allocate RAID disk data\n"); 2024 mpt_raid_free_mem(mpt); 2025 return (ENOMEM); 2026 } 2027 mpt->raid_max_disks = mpt->ioc_page2->MaxPhysDisks; 2028 2029 /* 2030 * Load page 3. 2031 */ 2032 rv = mpt_read_cfg_header(mpt, MPI_CONFIG_PAGETYPE_IOC, 2033 3, 0, &hdr, FALSE, 5000); 2034 if (rv) { 2035 mpt_raid_free_mem(mpt); 2036 return (EIO); 2037 } 2038 2039 mpt_lprt(mpt, MPT_PRT_DEBUG, "IOC Page 3 Header: %x %x %x %x\n", 2040 hdr.PageVersion, hdr.PageLength, hdr.PageNumber, hdr.PageType); 2041 2042 len = hdr.PageLength * sizeof(uint32_t); 2043 mpt->ioc_page3 = malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 2044 if (mpt->ioc_page3 == NULL) { 2045 mpt_prt(mpt, "unable to allocate memory for IOC page 3\n"); 2046 mpt_raid_free_mem(mpt); 2047 return (ENOMEM); 2048 } 2049 memcpy(&mpt->ioc_page3->Header, &hdr, sizeof(hdr)); 2050 rv = mpt_read_cur_cfg_page(mpt, 0, 2051 &mpt->ioc_page3->Header, len, FALSE, 5000); 2052 if (rv) { 2053 mpt_raid_free_mem(mpt); 2054 return (EIO); 2055 } 2056 mpt2host_config_page_ioc3(mpt->ioc_page3); 2057 mpt_raid_wakeup(mpt); 2058 return (0); 2059} 2060 2061/* 2062 * Enable IOC port 2063 */ 2064static int 2065mpt_send_port_enable(struct mpt_softc *mpt, int port) 2066{ 2067 request_t *req; 2068 MSG_PORT_ENABLE *enable_req; 2069 int error; 2070 2071 req = mpt_get_request(mpt, /*sleep_ok*/FALSE); 2072 if (req == NULL) 2073 return (-1); 2074 2075 enable_req = req->req_vbuf; 2076 memset(enable_req, 0, MPT_RQSL(mpt)); 2077 2078 enable_req->Function = MPI_FUNCTION_PORT_ENABLE; 2079 enable_req->MsgContext = htole32(req->index | MPT_REPLY_HANDLER_CONFIG); 2080 enable_req->PortNumber = port; 2081 2082 mpt_check_doorbell(mpt); 2083 mpt_lprt(mpt, MPT_PRT_DEBUG, "enabling port %d\n", port); 2084 2085 mpt_send_cmd(mpt, req); 2086 error = mpt_wait_req(mpt, req, REQ_STATE_DONE, REQ_STATE_DONE, 2087 FALSE, (mpt->is_sas || mpt->is_fc)? 30000 : 3000); 2088 if (error != 0) { 2089 mpt_prt(mpt, "port %d enable timed out\n", port); 2090 return (-1); 2091 } 2092 mpt_free_request(mpt, req); 2093 mpt_lprt(mpt, MPT_PRT_DEBUG, "enabled port %d\n", port); 2094 return (0); 2095} 2096 2097/* 2098 * Enable/Disable asynchronous event reporting. 2099 */ 2100static int 2101mpt_send_event_request(struct mpt_softc *mpt, int onoff) 2102{ 2103 request_t *req; 2104 MSG_EVENT_NOTIFY *enable_req; 2105 2106 req = mpt_get_request(mpt, FALSE); 2107 if (req == NULL) { 2108 return (ENOMEM); 2109 } 2110 enable_req = req->req_vbuf; 2111 memset(enable_req, 0, sizeof *enable_req); 2112 2113 enable_req->Function = MPI_FUNCTION_EVENT_NOTIFICATION; 2114 enable_req->MsgContext = htole32(req->index | MPT_REPLY_HANDLER_EVENTS); 2115 enable_req->Switch = onoff; 2116 2117 mpt_check_doorbell(mpt); 2118 mpt_lprt(mpt, MPT_PRT_DEBUG, "%sabling async events\n", 2119 onoff ? "en" : "dis"); 2120 /* 2121 * Send the command off, but don't wait for it. 2122 */ 2123 mpt_send_cmd(mpt, req); 2124 return (0); 2125} 2126 2127/* 2128 * Un-mask the interrupts on the chip. 2129 */ 2130void 2131mpt_enable_ints(struct mpt_softc *mpt) 2132{ 2133 2134 /* Unmask every thing except door bell int */ 2135 mpt_write(mpt, MPT_OFFSET_INTR_MASK, MPT_INTR_DB_MASK); 2136} 2137 2138/* 2139 * Mask the interrupts on the chip. 2140 */ 2141void 2142mpt_disable_ints(struct mpt_softc *mpt) 2143{ 2144 2145 /* Mask all interrupts */ 2146 mpt_write(mpt, MPT_OFFSET_INTR_MASK, 2147 MPT_INTR_REPLY_MASK | MPT_INTR_DB_MASK); 2148} 2149 2150static void 2151mpt_sysctl_attach(struct mpt_softc *mpt) 2152{ 2153#if __FreeBSD_version >= 500000 2154 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(mpt->dev); 2155 struct sysctl_oid *tree = device_get_sysctl_tree(mpt->dev); 2156 2157 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2158 "debug", CTLFLAG_RW, &mpt->verbose, 0, 2159 "Debugging/Verbose level"); 2160 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2161 "role", CTLFLAG_RD, &mpt->role, 0, 2162 "HBA role"); 2163#ifdef MPT_TEST_MULTIPATH 2164 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 2165 "failure_id", CTLFLAG_RW, &mpt->failure_id, -1, 2166 "Next Target to Fail"); 2167#endif 2168#endif 2169} 2170 2171int 2172mpt_attach(struct mpt_softc *mpt) 2173{ 2174 struct mpt_personality *pers; 2175 int i; 2176 int error; 2177 2178 mpt_core_attach(mpt); 2179 mpt_core_enable(mpt); 2180 2181 TAILQ_INSERT_TAIL(&mpt_tailq, mpt, links); 2182 for (i = 0; i < MPT_MAX_PERSONALITIES; i++) { 2183 pers = mpt_personalities[i]; 2184 if (pers == NULL) { 2185 continue; 2186 } 2187 if (pers->probe(mpt) == 0) { 2188 error = pers->attach(mpt); 2189 if (error != 0) { 2190 mpt_detach(mpt); 2191 return (error); 2192 } 2193 mpt->mpt_pers_mask |= (0x1 << pers->id); 2194 pers->use_count++; 2195 } 2196 } 2197 2198 /* 2199 * Now that we've attached everything, do the enable function 2200 * for all of the personalities. This allows the personalities 2201 * to do setups that are appropriate for them prior to enabling 2202 * any ports. 2203 */ 2204 for (i = 0; i < MPT_MAX_PERSONALITIES; i++) { 2205 pers = mpt_personalities[i]; 2206 if (pers != NULL && MPT_PERS_ATTACHED(pers, mpt) != 0) { 2207 error = pers->enable(mpt); 2208 if (error != 0) { 2209 mpt_prt(mpt, "personality %s attached but would" 2210 " not enable (%d)\n", pers->name, error); 2211 mpt_detach(mpt); 2212 return (error); 2213 } 2214 } 2215 } 2216 return (0); 2217} 2218 2219int 2220mpt_shutdown(struct mpt_softc *mpt) 2221{ 2222 struct mpt_personality *pers; 2223 2224 MPT_PERS_FOREACH_REVERSE(mpt, pers) { 2225 pers->shutdown(mpt); 2226 } 2227 return (0); 2228} 2229 2230int 2231mpt_detach(struct mpt_softc *mpt) 2232{ 2233 struct mpt_personality *pers; 2234 2235 MPT_PERS_FOREACH_REVERSE(mpt, pers) { 2236 pers->detach(mpt); 2237 mpt->mpt_pers_mask &= ~(0x1 << pers->id); 2238 pers->use_count--; 2239 } 2240 TAILQ_REMOVE(&mpt_tailq, mpt, links); 2241 return (0); 2242} 2243 2244static int 2245mpt_core_load(struct mpt_personality *pers) 2246{ 2247 int i; 2248 2249 /* 2250 * Setup core handlers and insert the default handler 2251 * into all "empty slots". 2252 */ 2253 for (i = 0; i < MPT_NUM_REPLY_HANDLERS; i++) { 2254 mpt_reply_handlers[i] = mpt_default_reply_handler; 2255 } 2256 2257 mpt_reply_handlers[MPT_CBI(MPT_REPLY_HANDLER_EVENTS)] = 2258 mpt_event_reply_handler; 2259 mpt_reply_handlers[MPT_CBI(MPT_REPLY_HANDLER_CONFIG)] = 2260 mpt_config_reply_handler; 2261 mpt_reply_handlers[MPT_CBI(MPT_REPLY_HANDLER_HANDSHAKE)] = 2262 mpt_handshake_reply_handler; 2263 return (0); 2264} 2265 2266/* 2267 * Initialize per-instance driver data and perform 2268 * initial controller configuration. 2269 */ 2270static int 2271mpt_core_attach(struct mpt_softc *mpt) 2272{ 2273 int val, error; 2274 2275 LIST_INIT(&mpt->ack_frames); 2276 /* Put all request buffers on the free list */ 2277 TAILQ_INIT(&mpt->request_pending_list); 2278 TAILQ_INIT(&mpt->request_free_list); 2279 TAILQ_INIT(&mpt->request_timeout_list); 2280 for (val = 0; val < MPT_MAX_LUNS; val++) { 2281 STAILQ_INIT(&mpt->trt[val].atios); 2282 STAILQ_INIT(&mpt->trt[val].inots); 2283 } 2284 STAILQ_INIT(&mpt->trt_wildcard.atios); 2285 STAILQ_INIT(&mpt->trt_wildcard.inots); 2286#ifdef MPT_TEST_MULTIPATH 2287 mpt->failure_id = -1; 2288#endif 2289 mpt->scsi_tgt_handler_id = MPT_HANDLER_ID_NONE; 2290 mpt_sysctl_attach(mpt); 2291 mpt_lprt(mpt, MPT_PRT_DEBUG, "doorbell req = %s\n", 2292 mpt_ioc_diag(mpt_read(mpt, MPT_OFFSET_DOORBELL))); 2293 2294 MPT_LOCK(mpt); 2295 error = mpt_configure_ioc(mpt, 0, 0); 2296 MPT_UNLOCK(mpt); 2297 2298 return (error); 2299} 2300 2301static int 2302mpt_core_enable(struct mpt_softc *mpt) 2303{ 2304 2305 /* 2306 * We enter with the IOC enabled, but async events 2307 * not enabled, ports not enabled and interrupts 2308 * not enabled. 2309 */ 2310 MPT_LOCK(mpt); 2311 2312 /* 2313 * Enable asynchronous event reporting- all personalities 2314 * have attached so that they should be able to now field 2315 * async events. 2316 */ 2317 mpt_send_event_request(mpt, 1); 2318 2319 /* 2320 * Catch any pending interrupts 2321 * 2322 * This seems to be crucial- otherwise 2323 * the portenable below times out. 2324 */ 2325 mpt_intr(mpt); 2326 2327 /* 2328 * Enable Interrupts 2329 */ 2330 mpt_enable_ints(mpt); 2331 2332 /* 2333 * Catch any pending interrupts 2334 * 2335 * This seems to be crucial- otherwise 2336 * the portenable below times out. 2337 */ 2338 mpt_intr(mpt); 2339 2340 /* 2341 * Enable the port. 2342 */ 2343 if (mpt_send_port_enable(mpt, 0) != MPT_OK) { 2344 mpt_prt(mpt, "failed to enable port 0\n"); 2345 MPT_UNLOCK(mpt); 2346 return (ENXIO); 2347 } 2348 MPT_UNLOCK(mpt); 2349 return (0); 2350} 2351 2352static void 2353mpt_core_shutdown(struct mpt_softc *mpt) 2354{ 2355 2356 mpt_disable_ints(mpt); 2357} 2358 2359static void 2360mpt_core_detach(struct mpt_softc *mpt) 2361{ 2362 int val; 2363 2364 /* 2365 * XXX: FREE MEMORY 2366 */ 2367 mpt_disable_ints(mpt); 2368 2369 /* Make sure no request has pending timeouts. */ 2370 for (val = 0; val < MPT_MAX_REQUESTS(mpt); val++) { 2371 request_t *req = &mpt->request_pool[val]; 2372 mpt_callout_drain(mpt, &req->callout); 2373 } 2374 2375 mpt_dma_buf_free(mpt); 2376} 2377 2378static int 2379mpt_core_unload(struct mpt_personality *pers) 2380{ 2381 2382 /* Unload is always successful. */ 2383 return (0); 2384} 2385 2386#define FW_UPLOAD_REQ_SIZE \ 2387 (sizeof(MSG_FW_UPLOAD) - sizeof(SGE_MPI_UNION) \ 2388 + sizeof(FW_UPLOAD_TCSGE) + sizeof(SGE_SIMPLE32)) 2389 2390static int 2391mpt_upload_fw(struct mpt_softc *mpt) 2392{ 2393 uint8_t fw_req_buf[FW_UPLOAD_REQ_SIZE]; 2394 MSG_FW_UPLOAD_REPLY fw_reply; 2395 MSG_FW_UPLOAD *fw_req; 2396 FW_UPLOAD_TCSGE *tsge; 2397 SGE_SIMPLE32 *sge; 2398 uint32_t flags; 2399 int error; 2400 2401 memset(&fw_req_buf, 0, sizeof(fw_req_buf)); 2402 fw_req = (MSG_FW_UPLOAD *)fw_req_buf; 2403 fw_req->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM; 2404 fw_req->Function = MPI_FUNCTION_FW_UPLOAD; 2405 fw_req->MsgContext = htole32(MPT_REPLY_HANDLER_HANDSHAKE); 2406 tsge = (FW_UPLOAD_TCSGE *)&fw_req->SGL; 2407 tsge->DetailsLength = 12; 2408 tsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT; 2409 tsge->ImageSize = htole32(mpt->fw_image_size); 2410 sge = (SGE_SIMPLE32 *)(tsge + 1); 2411 flags = (MPI_SGE_FLAGS_LAST_ELEMENT | MPI_SGE_FLAGS_END_OF_BUFFER 2412 | MPI_SGE_FLAGS_END_OF_LIST | MPI_SGE_FLAGS_SIMPLE_ELEMENT 2413 | MPI_SGE_FLAGS_32_BIT_ADDRESSING | MPI_SGE_FLAGS_IOC_TO_HOST); 2414 flags <<= MPI_SGE_FLAGS_SHIFT; 2415 sge->FlagsLength = htole32(flags | mpt->fw_image_size); 2416 sge->Address = htole32(mpt->fw_phys); 2417 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_PREREAD); 2418 error = mpt_send_handshake_cmd(mpt, sizeof(fw_req_buf), &fw_req_buf); 2419 if (error) 2420 return(error); 2421 error = mpt_recv_handshake_reply(mpt, sizeof(fw_reply), &fw_reply); 2422 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_POSTREAD); 2423 return (error); 2424} 2425 2426static void 2427mpt_diag_outsl(struct mpt_softc *mpt, uint32_t addr, 2428 uint32_t *data, bus_size_t len) 2429{ 2430 uint32_t *data_end; 2431 2432 data_end = data + (roundup2(len, sizeof(uint32_t)) / 4); 2433 if (mpt->is_sas) { 2434 pci_enable_io(mpt->dev, SYS_RES_IOPORT); 2435 } 2436 mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, addr); 2437 while (data != data_end) { 2438 mpt_pio_write(mpt, MPT_OFFSET_DIAG_DATA, *data); 2439 data++; 2440 } 2441 if (mpt->is_sas) { 2442 pci_disable_io(mpt->dev, SYS_RES_IOPORT); 2443 } 2444} 2445 2446static int 2447mpt_download_fw(struct mpt_softc *mpt) 2448{ 2449 MpiFwHeader_t *fw_hdr; 2450 int error; 2451 uint32_t ext_offset; 2452 uint32_t data; 2453 2454 mpt_prt(mpt, "Downloading Firmware - Image Size %d\n", 2455 mpt->fw_image_size); 2456 2457 error = mpt_enable_diag_mode(mpt); 2458 if (error != 0) { 2459 mpt_prt(mpt, "Could not enter diagnostic mode!\n"); 2460 return (EIO); 2461 } 2462 2463 mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, 2464 MPI_DIAG_RW_ENABLE|MPI_DIAG_DISABLE_ARM); 2465 2466 fw_hdr = (MpiFwHeader_t *)mpt->fw_image; 2467 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_PREWRITE); 2468 mpt_diag_outsl(mpt, fw_hdr->LoadStartAddress, (uint32_t*)fw_hdr, 2469 fw_hdr->ImageSize); 2470 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, BUS_DMASYNC_POSTWRITE); 2471 2472 ext_offset = fw_hdr->NextImageHeaderOffset; 2473 while (ext_offset != 0) { 2474 MpiExtImageHeader_t *ext; 2475 2476 ext = (MpiExtImageHeader_t *)((uintptr_t)fw_hdr + ext_offset); 2477 ext_offset = ext->NextImageHeaderOffset; 2478 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, 2479 BUS_DMASYNC_PREWRITE); 2480 mpt_diag_outsl(mpt, ext->LoadStartAddress, (uint32_t*)ext, 2481 ext->ImageSize); 2482 bus_dmamap_sync(mpt->fw_dmat, mpt->fw_dmap, 2483 BUS_DMASYNC_POSTWRITE); 2484 } 2485 2486 if (mpt->is_sas) { 2487 pci_enable_io(mpt->dev, SYS_RES_IOPORT); 2488 } 2489 /* Setup the address to jump to on reset. */ 2490 mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, fw_hdr->IopResetRegAddr); 2491 mpt_pio_write(mpt, MPT_OFFSET_DIAG_DATA, fw_hdr->IopResetVectorValue); 2492 2493 /* 2494 * The controller sets the "flash bad" status after attempting 2495 * to auto-boot from flash. Clear the status so that the controller 2496 * will continue the boot process with our newly installed firmware. 2497 */ 2498 mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, MPT_DIAG_MEM_CFG_BASE); 2499 data = mpt_pio_read(mpt, MPT_OFFSET_DIAG_DATA) | MPT_DIAG_MEM_CFG_BADFL; 2500 mpt_pio_write(mpt, MPT_OFFSET_DIAG_ADDR, MPT_DIAG_MEM_CFG_BASE); 2501 mpt_pio_write(mpt, MPT_OFFSET_DIAG_DATA, data); 2502 2503 if (mpt->is_sas) { 2504 pci_disable_io(mpt->dev, SYS_RES_IOPORT); 2505 } 2506 2507 /* 2508 * Re-enable the processor and clear the boot halt flag. 2509 */ 2510 data = mpt_read(mpt, MPT_OFFSET_DIAGNOSTIC); 2511 data &= ~(MPI_DIAG_PREVENT_IOC_BOOT|MPI_DIAG_DISABLE_ARM); 2512 mpt_write(mpt, MPT_OFFSET_DIAGNOSTIC, data); 2513 2514 mpt_disable_diag_mode(mpt); 2515 return (0); 2516} 2517 2518static int 2519mpt_dma_buf_alloc(struct mpt_softc *mpt) 2520{ 2521 struct mpt_map_info mi; 2522 uint8_t *vptr; 2523 uint32_t pptr, end; 2524 int i, error; 2525 2526 /* Create a child tag for data buffers */ 2527 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, 1, 2528 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 2529 NULL, NULL, (mpt->max_cam_seg_cnt - 1) * PAGE_SIZE, 2530 mpt->max_cam_seg_cnt, BUS_SPACE_MAXSIZE_32BIT, 0, 2531 &mpt->buffer_dmat) != 0) { 2532 mpt_prt(mpt, "cannot create a dma tag for data buffers\n"); 2533 return (1); 2534 } 2535 2536 /* Create a child tag for request buffers */ 2537 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, PAGE_SIZE, 0, 2538 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 2539 NULL, NULL, MPT_REQ_MEM_SIZE(mpt), 1, BUS_SPACE_MAXSIZE_32BIT, 0, 2540 &mpt->request_dmat) != 0) { 2541 mpt_prt(mpt, "cannot create a dma tag for requests\n"); 2542 return (1); 2543 } 2544 2545 /* Allocate some DMA accessible memory for requests */ 2546 if (bus_dmamem_alloc(mpt->request_dmat, (void **)&mpt->request, 2547 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &mpt->request_dmap) != 0) { 2548 mpt_prt(mpt, "cannot allocate %d bytes of request memory\n", 2549 MPT_REQ_MEM_SIZE(mpt)); 2550 return (1); 2551 } 2552 2553 mi.mpt = mpt; 2554 mi.error = 0; 2555 2556 /* Load and lock it into "bus space" */ 2557 bus_dmamap_load(mpt->request_dmat, mpt->request_dmap, mpt->request, 2558 MPT_REQ_MEM_SIZE(mpt), mpt_map_rquest, &mi, 0); 2559 2560 if (mi.error) { 2561 mpt_prt(mpt, "error %d loading dma map for DMA request queue\n", 2562 mi.error); 2563 return (1); 2564 } 2565 mpt->request_phys = mi.phys; 2566 2567 /* 2568 * Now create per-request dma maps 2569 */ 2570 i = 0; 2571 pptr = mpt->request_phys; 2572 vptr = mpt->request; 2573 end = pptr + MPT_REQ_MEM_SIZE(mpt); 2574 while(pptr < end) { 2575 request_t *req = &mpt->request_pool[i]; 2576 req->index = i++; 2577 2578 /* Store location of Request Data */ 2579 req->req_pbuf = pptr; 2580 req->req_vbuf = vptr; 2581 2582 pptr += MPT_REQUEST_AREA; 2583 vptr += MPT_REQUEST_AREA; 2584 2585 req->sense_pbuf = (pptr - MPT_SENSE_SIZE); 2586 req->sense_vbuf = (vptr - MPT_SENSE_SIZE); 2587 2588 error = bus_dmamap_create(mpt->buffer_dmat, 0, &req->dmap); 2589 if (error) { 2590 mpt_prt(mpt, "error %d creating per-cmd DMA maps\n", 2591 error); 2592 return (1); 2593 } 2594 } 2595 2596 return (0); 2597} 2598 2599static void 2600mpt_dma_buf_free(struct mpt_softc *mpt) 2601{ 2602 int i; 2603 2604 if (mpt->request_dmat == 0) { 2605 mpt_lprt(mpt, MPT_PRT_DEBUG, "already released dma memory\n"); 2606 return; 2607 } 2608 for (i = 0; i < MPT_MAX_REQUESTS(mpt); i++) { 2609 bus_dmamap_destroy(mpt->buffer_dmat, mpt->request_pool[i].dmap); 2610 } 2611 bus_dmamap_unload(mpt->request_dmat, mpt->request_dmap); 2612 bus_dmamem_free(mpt->request_dmat, mpt->request, mpt->request_dmap); 2613 bus_dma_tag_destroy(mpt->request_dmat); 2614 mpt->request_dmat = 0; 2615 bus_dma_tag_destroy(mpt->buffer_dmat); 2616} 2617 2618/* 2619 * Allocate/Initialize data structures for the controller. Called 2620 * once at instance startup. 2621 */ 2622static int 2623mpt_configure_ioc(struct mpt_softc *mpt, int tn, int needreset) 2624{ 2625 PTR_MSG_PORT_FACTS_REPLY pfp; 2626 int error, port, val; 2627 size_t len; 2628 2629 if (tn == MPT_MAX_TRYS) { 2630 return (-1); 2631 } 2632 2633 /* 2634 * No need to reset if the IOC is already in the READY state. 2635 * 2636 * Force reset if initialization failed previously. 2637 * Note that a hard_reset of the second channel of a '929 2638 * will stop operation of the first channel. Hopefully, if the 2639 * first channel is ok, the second will not require a hard 2640 * reset. 2641 */ 2642 if (needreset || MPT_STATE(mpt_rd_db(mpt)) != MPT_DB_STATE_READY) { 2643 if (mpt_reset(mpt, FALSE) != MPT_OK) { 2644 return (mpt_configure_ioc(mpt, tn++, 1)); 2645 } 2646 needreset = 0; 2647 } 2648 2649 if (mpt_get_iocfacts(mpt, &mpt->ioc_facts) != MPT_OK) { 2650 mpt_prt(mpt, "mpt_get_iocfacts failed\n"); 2651 return (mpt_configure_ioc(mpt, tn++, 1)); 2652 } 2653 mpt2host_iocfacts_reply(&mpt->ioc_facts); 2654 2655 mpt_prt(mpt, "MPI Version=%d.%d.%d.%d\n", 2656 mpt->ioc_facts.MsgVersion >> 8, 2657 mpt->ioc_facts.MsgVersion & 0xFF, 2658 mpt->ioc_facts.HeaderVersion >> 8, 2659 mpt->ioc_facts.HeaderVersion & 0xFF); 2660 2661 /* 2662 * Now that we know request frame size, we can calculate 2663 * the actual (reasonable) segment limit for read/write I/O. 2664 * 2665 * This limit is constrained by: 2666 * 2667 * + The size of each area we allocate per command (and how 2668 * many chain segments we can fit into it). 2669 * + The total number of areas we've set up. 2670 * + The actual chain depth the card will allow. 2671 * 2672 * The first area's segment count is limited by the I/O request 2673 * at the head of it. We cannot allocate realistically more 2674 * than MPT_MAX_REQUESTS areas. Therefore, to account for both 2675 * conditions, we'll just start out with MPT_MAX_REQUESTS-2. 2676 * 2677 */ 2678 /* total number of request areas we (can) allocate */ 2679 mpt->max_seg_cnt = MPT_MAX_REQUESTS(mpt) - 2; 2680 2681 /* converted to the number of chain areas possible */ 2682 mpt->max_seg_cnt *= MPT_NRFM(mpt); 2683 2684 /* limited by the number of chain areas the card will support */ 2685 if (mpt->max_seg_cnt > mpt->ioc_facts.MaxChainDepth) { 2686 mpt_lprt(mpt, MPT_PRT_INFO, 2687 "chain depth limited to %u (from %u)\n", 2688 mpt->ioc_facts.MaxChainDepth, mpt->max_seg_cnt); 2689 mpt->max_seg_cnt = mpt->ioc_facts.MaxChainDepth; 2690 } 2691 2692 /* converted to the number of simple sges in chain segments. */ 2693 mpt->max_seg_cnt *= (MPT_NSGL(mpt) - 1); 2694 2695 /* 2696 * Use this as the basis for reporting the maximum I/O size to CAM. 2697 */ 2698 mpt->max_cam_seg_cnt = min(mpt->max_seg_cnt, (MAXPHYS / PAGE_SIZE) + 1); 2699 2700 error = mpt_dma_buf_alloc(mpt); 2701 if (error != 0) { 2702 mpt_prt(mpt, "mpt_dma_buf_alloc() failed!\n"); 2703 return (EIO); 2704 } 2705 2706 for (val = 0; val < MPT_MAX_REQUESTS(mpt); val++) { 2707 request_t *req = &mpt->request_pool[val]; 2708 req->state = REQ_STATE_ALLOCATED; 2709 mpt_callout_init(mpt, &req->callout); 2710 mpt_free_request(mpt, req); 2711 } 2712 2713 mpt_lprt(mpt, MPT_PRT_INFO, "Maximum Segment Count: %u, Maximum " 2714 "CAM Segment Count: %u\n", mpt->max_seg_cnt, 2715 mpt->max_cam_seg_cnt); 2716 2717 mpt_lprt(mpt, MPT_PRT_INFO, "MsgLength=%u IOCNumber = %d\n", 2718 mpt->ioc_facts.MsgLength, mpt->ioc_facts.IOCNumber); 2719 mpt_lprt(mpt, MPT_PRT_INFO, 2720 "IOCFACTS: GlobalCredits=%d BlockSize=%u bytes " 2721 "Request Frame Size %u bytes Max Chain Depth %u\n", 2722 mpt->ioc_facts.GlobalCredits, mpt->ioc_facts.BlockSize, 2723 mpt->ioc_facts.RequestFrameSize << 2, 2724 mpt->ioc_facts.MaxChainDepth); 2725 mpt_lprt(mpt, MPT_PRT_INFO, "IOCFACTS: Num Ports %d, FWImageSize %d, " 2726 "Flags=%#x\n", mpt->ioc_facts.NumberOfPorts, 2727 mpt->ioc_facts.FWImageSize, mpt->ioc_facts.Flags); 2728 2729 len = mpt->ioc_facts.NumberOfPorts * sizeof (MSG_PORT_FACTS_REPLY); 2730 mpt->port_facts = malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO); 2731 if (mpt->port_facts == NULL) { 2732 mpt_prt(mpt, "unable to allocate memory for port facts\n"); 2733 return (ENOMEM); 2734 } 2735 2736 2737 if ((mpt->ioc_facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) && 2738 (mpt->fw_uploaded == 0)) { 2739 struct mpt_map_info mi; 2740 2741 /* 2742 * In some configurations, the IOC's firmware is 2743 * stored in a shared piece of system NVRAM that 2744 * is only accessible via the BIOS. In this 2745 * case, the firmware keeps a copy of firmware in 2746 * RAM until the OS driver retrieves it. Once 2747 * retrieved, we are responsible for re-downloading 2748 * the firmware after any hard-reset. 2749 */ 2750 mpt->fw_image_size = mpt->ioc_facts.FWImageSize; 2751 error = mpt_dma_tag_create(mpt, mpt->parent_dmat, 1, 0, 2752 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2753 mpt->fw_image_size, 1, mpt->fw_image_size, 0, 2754 &mpt->fw_dmat); 2755 if (error != 0) { 2756 mpt_prt(mpt, "cannot create firmware dma tag\n"); 2757 return (ENOMEM); 2758 } 2759 error = bus_dmamem_alloc(mpt->fw_dmat, 2760 (void **)&mpt->fw_image, BUS_DMA_NOWAIT | 2761 BUS_DMA_COHERENT, &mpt->fw_dmap); 2762 if (error != 0) { 2763 mpt_prt(mpt, "cannot allocate firmware memory\n"); 2764 bus_dma_tag_destroy(mpt->fw_dmat); 2765 return (ENOMEM); 2766 } 2767 mi.mpt = mpt; 2768 mi.error = 0; 2769 bus_dmamap_load(mpt->fw_dmat, mpt->fw_dmap, 2770 mpt->fw_image, mpt->fw_image_size, mpt_map_rquest, &mi, 0); 2771 mpt->fw_phys = mi.phys; 2772 2773 error = mpt_upload_fw(mpt); 2774 if (error != 0) { 2775 mpt_prt(mpt, "firmware upload failed.\n"); 2776 bus_dmamap_unload(mpt->fw_dmat, mpt->fw_dmap); 2777 bus_dmamem_free(mpt->fw_dmat, mpt->fw_image, 2778 mpt->fw_dmap); 2779 bus_dma_tag_destroy(mpt->fw_dmat); 2780 mpt->fw_image = NULL; 2781 return (EIO); 2782 } 2783 mpt->fw_uploaded = 1; 2784 } 2785 2786 for (port = 0; port < mpt->ioc_facts.NumberOfPorts; port++) { 2787 pfp = &mpt->port_facts[port]; 2788 error = mpt_get_portfacts(mpt, 0, pfp); 2789 if (error != MPT_OK) { 2790 mpt_prt(mpt, 2791 "mpt_get_portfacts on port %d failed\n", port); 2792 free(mpt->port_facts, M_DEVBUF); 2793 mpt->port_facts = NULL; 2794 return (mpt_configure_ioc(mpt, tn++, 1)); 2795 } 2796 mpt2host_portfacts_reply(pfp); 2797 2798 if (port > 0) { 2799 error = MPT_PRT_INFO; 2800 } else { 2801 error = MPT_PRT_DEBUG; 2802 } 2803 mpt_lprt(mpt, error, 2804 "PORTFACTS[%d]: Type %x PFlags %x IID %d MaxDev %d\n", 2805 port, pfp->PortType, pfp->ProtocolFlags, pfp->PortSCSIID, 2806 pfp->MaxDevices); 2807 2808 } 2809 2810 /* 2811 * XXX: Not yet supporting more than port 0 2812 */ 2813 pfp = &mpt->port_facts[0]; 2814 if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_FC) { 2815 mpt->is_fc = 1; 2816 mpt->is_sas = 0; 2817 mpt->is_spi = 0; 2818 } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_SAS) { 2819 mpt->is_fc = 0; 2820 mpt->is_sas = 1; 2821 mpt->is_spi = 0; 2822 } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_SCSI) { 2823 mpt->is_fc = 0; 2824 mpt->is_sas = 0; 2825 mpt->is_spi = 1; 2826 if (mpt->mpt_ini_id == MPT_INI_ID_NONE) 2827 mpt->mpt_ini_id = pfp->PortSCSIID; 2828 } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_ISCSI) { 2829 mpt_prt(mpt, "iSCSI not supported yet\n"); 2830 return (ENXIO); 2831 } else if (pfp->PortType == MPI_PORTFACTS_PORTTYPE_INACTIVE) { 2832 mpt_prt(mpt, "Inactive Port\n"); 2833 return (ENXIO); 2834 } else { 2835 mpt_prt(mpt, "unknown Port Type %#x\n", pfp->PortType); 2836 return (ENXIO); 2837 } 2838 2839 /* 2840 * Set our role with what this port supports. 2841 * 2842 * Note this might be changed later in different modules 2843 * if this is different from what is wanted. 2844 */ 2845 mpt->role = MPT_ROLE_NONE; 2846 if (pfp->ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) { 2847 mpt->role |= MPT_ROLE_INITIATOR; 2848 } 2849 if (pfp->ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) { 2850 mpt->role |= MPT_ROLE_TARGET; 2851 } 2852 2853 /* 2854 * Enable the IOC 2855 */ 2856 if (mpt_enable_ioc(mpt, 1) != MPT_OK) { 2857 mpt_prt(mpt, "unable to initialize IOC\n"); 2858 return (ENXIO); 2859 } 2860 2861 /* 2862 * Read IOC configuration information. 2863 * 2864 * We need this to determine whether or not we have certain 2865 * settings for Integrated Mirroring (e.g.). 2866 */ 2867 mpt_read_config_info_ioc(mpt); 2868 2869 return (0); 2870} 2871 2872static int 2873mpt_enable_ioc(struct mpt_softc *mpt, int portenable) 2874{ 2875 uint32_t pptr; 2876 int val; 2877 2878 if (mpt_send_ioc_init(mpt, MPI_WHOINIT_HOST_DRIVER) != MPT_OK) { 2879 mpt_prt(mpt, "mpt_send_ioc_init failed\n"); 2880 return (EIO); 2881 } 2882 2883 mpt_lprt(mpt, MPT_PRT_DEBUG, "mpt_send_ioc_init ok\n"); 2884 2885 if (mpt_wait_state(mpt, MPT_DB_STATE_RUNNING) != MPT_OK) { 2886 mpt_prt(mpt, "IOC failed to go to run state\n"); 2887 return (ENXIO); 2888 } 2889 mpt_lprt(mpt, MPT_PRT_DEBUG, "IOC now at RUNSTATE\n"); 2890 2891 /* 2892 * Give it reply buffers 2893 * 2894 * Do *not* exceed global credits. 2895 */ 2896 for (val = 0, pptr = mpt->reply_phys; 2897 (pptr + MPT_REPLY_SIZE) < (mpt->reply_phys + PAGE_SIZE); 2898 pptr += MPT_REPLY_SIZE) { 2899 mpt_free_reply(mpt, pptr); 2900 if (++val == mpt->ioc_facts.GlobalCredits - 1) 2901 break; 2902 } 2903 2904 2905 /* 2906 * Enable the port if asked. This is only done if we're resetting 2907 * the IOC after initial startup. 2908 */ 2909 if (portenable) { 2910 /* 2911 * Enable asynchronous event reporting 2912 */ 2913 mpt_send_event_request(mpt, 1); 2914 2915 if (mpt_send_port_enable(mpt, 0) != MPT_OK) { 2916 mpt_prt(mpt, "%s: failed to enable port 0\n", __func__); 2917 return (ENXIO); 2918 } 2919 } 2920 return (MPT_OK); 2921} 2922 2923/* 2924 * Endian Conversion Functions- only used on Big Endian machines 2925 */ 2926#if _BYTE_ORDER == _BIG_ENDIAN 2927void 2928mpt2host_sge_simple_union(SGE_SIMPLE_UNION *sge) 2929{ 2930 2931 MPT_2_HOST32(sge, FlagsLength); 2932 MPT_2_HOST32(sge, u.Address64.Low); 2933 MPT_2_HOST32(sge, u.Address64.High); 2934} 2935 2936void 2937mpt2host_iocfacts_reply(MSG_IOC_FACTS_REPLY *rp) 2938{ 2939 2940 MPT_2_HOST16(rp, MsgVersion); 2941 MPT_2_HOST16(rp, HeaderVersion); 2942 MPT_2_HOST32(rp, MsgContext); 2943 MPT_2_HOST16(rp, IOCExceptions); 2944 MPT_2_HOST16(rp, IOCStatus); 2945 MPT_2_HOST32(rp, IOCLogInfo); 2946 MPT_2_HOST16(rp, ReplyQueueDepth); 2947 MPT_2_HOST16(rp, RequestFrameSize); 2948 MPT_2_HOST16(rp, Reserved_0101_FWVersion); 2949 MPT_2_HOST16(rp, ProductID); 2950 MPT_2_HOST32(rp, CurrentHostMfaHighAddr); 2951 MPT_2_HOST16(rp, GlobalCredits); 2952 MPT_2_HOST32(rp, CurrentSenseBufferHighAddr); 2953 MPT_2_HOST16(rp, CurReplyFrameSize); 2954 MPT_2_HOST32(rp, FWImageSize); 2955 MPT_2_HOST32(rp, IOCCapabilities); 2956 MPT_2_HOST32(rp, FWVersion.Word); 2957 MPT_2_HOST16(rp, HighPriorityQueueDepth); 2958 MPT_2_HOST16(rp, Reserved2); 2959 mpt2host_sge_simple_union(&rp->HostPageBufferSGE); 2960 MPT_2_HOST32(rp, ReplyFifoHostSignalingAddr); 2961} 2962 2963void 2964mpt2host_portfacts_reply(MSG_PORT_FACTS_REPLY *pfp) 2965{ 2966 2967 MPT_2_HOST16(pfp, Reserved); 2968 MPT_2_HOST16(pfp, Reserved1); 2969 MPT_2_HOST32(pfp, MsgContext); 2970 MPT_2_HOST16(pfp, Reserved2); 2971 MPT_2_HOST16(pfp, IOCStatus); 2972 MPT_2_HOST32(pfp, IOCLogInfo); 2973 MPT_2_HOST16(pfp, MaxDevices); 2974 MPT_2_HOST16(pfp, PortSCSIID); 2975 MPT_2_HOST16(pfp, ProtocolFlags); 2976 MPT_2_HOST16(pfp, MaxPostedCmdBuffers); 2977 MPT_2_HOST16(pfp, MaxPersistentIDs); 2978 MPT_2_HOST16(pfp, MaxLanBuckets); 2979 MPT_2_HOST16(pfp, Reserved4); 2980 MPT_2_HOST32(pfp, Reserved5); 2981} 2982 2983void 2984mpt2host_config_page_ioc2(CONFIG_PAGE_IOC_2 *ioc2) 2985{ 2986 int i; 2987 2988 MPT_2_HOST32(ioc2, CapabilitiesFlags); 2989 for (i = 0; i < MPI_IOC_PAGE_2_RAID_VOLUME_MAX; i++) { 2990 MPT_2_HOST16(ioc2, RaidVolume[i].Reserved3); 2991 } 2992} 2993 2994void 2995mpt2host_config_page_ioc3(CONFIG_PAGE_IOC_3 *ioc3) 2996{ 2997 2998 MPT_2_HOST16(ioc3, Reserved2); 2999} 3000 3001void 3002mpt2host_config_page_scsi_port_0(CONFIG_PAGE_SCSI_PORT_0 *sp0) 3003{ 3004 3005 MPT_2_HOST32(sp0, Capabilities); 3006 MPT_2_HOST32(sp0, PhysicalInterface); 3007} 3008 3009void 3010mpt2host_config_page_scsi_port_1(CONFIG_PAGE_SCSI_PORT_1 *sp1) 3011{ 3012 3013 MPT_2_HOST32(sp1, Configuration); 3014 MPT_2_HOST32(sp1, OnBusTimerValue); 3015 MPT_2_HOST16(sp1, IDConfig); 3016} 3017 3018void 3019host2mpt_config_page_scsi_port_1(CONFIG_PAGE_SCSI_PORT_1 *sp1) 3020{ 3021 3022 HOST_2_MPT32(sp1, Configuration); 3023 HOST_2_MPT32(sp1, OnBusTimerValue); 3024 HOST_2_MPT16(sp1, IDConfig); 3025} 3026 3027void 3028mpt2host_config_page_scsi_port_2(CONFIG_PAGE_SCSI_PORT_2 *sp2) 3029{ 3030 int i; 3031 3032 MPT_2_HOST32(sp2, PortFlags); 3033 MPT_2_HOST32(sp2, PortSettings); 3034 for (i = 0; i < sizeof(sp2->DeviceSettings) / 3035 sizeof(*sp2->DeviceSettings); i++) { 3036 MPT_2_HOST16(sp2, DeviceSettings[i].DeviceFlags); 3037 } 3038} 3039 3040void 3041mpt2host_config_page_scsi_device_0(CONFIG_PAGE_SCSI_DEVICE_0 *sd0) 3042{ 3043 3044 MPT_2_HOST32(sd0, NegotiatedParameters); 3045 MPT_2_HOST32(sd0, Information); 3046} 3047 3048void 3049mpt2host_config_page_scsi_device_1(CONFIG_PAGE_SCSI_DEVICE_1 *sd1) 3050{ 3051 3052 MPT_2_HOST32(sd1, RequestedParameters); 3053 MPT_2_HOST32(sd1, Reserved); 3054 MPT_2_HOST32(sd1, Configuration); 3055} 3056 3057void 3058host2mpt_config_page_scsi_device_1(CONFIG_PAGE_SCSI_DEVICE_1 *sd1) 3059{ 3060 3061 HOST_2_MPT32(sd1, RequestedParameters); 3062 HOST_2_MPT32(sd1, Reserved); 3063 HOST_2_MPT32(sd1, Configuration); 3064} 3065 3066void 3067mpt2host_config_page_fc_port_0(CONFIG_PAGE_FC_PORT_0 *fp0) 3068{ 3069 3070 MPT_2_HOST32(fp0, Flags); 3071 MPT_2_HOST32(fp0, PortIdentifier); 3072 MPT_2_HOST32(fp0, WWNN.Low); 3073 MPT_2_HOST32(fp0, WWNN.High); 3074 MPT_2_HOST32(fp0, WWPN.Low); 3075 MPT_2_HOST32(fp0, WWPN.High); 3076 MPT_2_HOST32(fp0, SupportedServiceClass); 3077 MPT_2_HOST32(fp0, SupportedSpeeds); 3078 MPT_2_HOST32(fp0, CurrentSpeed); 3079 MPT_2_HOST32(fp0, MaxFrameSize); 3080 MPT_2_HOST32(fp0, FabricWWNN.Low); 3081 MPT_2_HOST32(fp0, FabricWWNN.High); 3082 MPT_2_HOST32(fp0, FabricWWPN.Low); 3083 MPT_2_HOST32(fp0, FabricWWPN.High); 3084 MPT_2_HOST32(fp0, DiscoveredPortsCount); 3085 MPT_2_HOST32(fp0, MaxInitiators); 3086} 3087 3088void 3089mpt2host_config_page_fc_port_1(CONFIG_PAGE_FC_PORT_1 *fp1) 3090{ 3091 3092 MPT_2_HOST32(fp1, Flags); 3093 MPT_2_HOST32(fp1, NoSEEPROMWWNN.Low); 3094 MPT_2_HOST32(fp1, NoSEEPROMWWNN.High); 3095 MPT_2_HOST32(fp1, NoSEEPROMWWPN.Low); 3096 MPT_2_HOST32(fp1, NoSEEPROMWWPN.High); 3097} 3098 3099void 3100host2mpt_config_page_fc_port_1(CONFIG_PAGE_FC_PORT_1 *fp1) 3101{ 3102 3103 HOST_2_MPT32(fp1, Flags); 3104 HOST_2_MPT32(fp1, NoSEEPROMWWNN.Low); 3105 HOST_2_MPT32(fp1, NoSEEPROMWWNN.High); 3106 HOST_2_MPT32(fp1, NoSEEPROMWWPN.Low); 3107 HOST_2_MPT32(fp1, NoSEEPROMWWPN.High); 3108} 3109 3110void 3111mpt2host_config_page_raid_vol_0(CONFIG_PAGE_RAID_VOL_0 *volp) 3112{ 3113 int i; 3114 3115 MPT_2_HOST16(volp, VolumeStatus.Reserved); 3116 MPT_2_HOST16(volp, VolumeSettings.Settings); 3117 MPT_2_HOST32(volp, MaxLBA); 3118 MPT_2_HOST32(volp, MaxLBAHigh); 3119 MPT_2_HOST32(volp, StripeSize); 3120 MPT_2_HOST32(volp, Reserved2); 3121 MPT_2_HOST32(volp, Reserved3); 3122 for (i = 0; i < MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX; i++) { 3123 MPT_2_HOST16(volp, PhysDisk[i].Reserved); 3124 } 3125} 3126 3127void 3128mpt2host_config_page_raid_phys_disk_0(CONFIG_PAGE_RAID_PHYS_DISK_0 *rpd0) 3129{ 3130 3131 MPT_2_HOST32(rpd0, Reserved1); 3132 MPT_2_HOST16(rpd0, PhysDiskStatus.Reserved); 3133 MPT_2_HOST32(rpd0, MaxLBA); 3134 MPT_2_HOST16(rpd0, ErrorData.Reserved); 3135 MPT_2_HOST16(rpd0, ErrorData.ErrorCount); 3136 MPT_2_HOST16(rpd0, ErrorData.SmartCount); 3137} 3138 3139void 3140mpt2host_mpi_raid_vol_indicator(MPI_RAID_VOL_INDICATOR *vi) 3141{ 3142 3143 MPT_2_HOST16(vi, TotalBlocks.High); 3144 MPT_2_HOST16(vi, TotalBlocks.Low); 3145 MPT_2_HOST16(vi, BlocksRemaining.High); 3146 MPT_2_HOST16(vi, BlocksRemaining.Low); 3147} 3148#endif 3149